Entry Kaneko:1990:RVS from ieeemicro.bib

Last update: Fri Jul 3 02:09:12 MDT 2009                Valid HTML 3.2!

Index sections

Top | Symbols | Math | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z

BibTeX entry

@Article{Kaneko:1990:RVS,
  author =       "Hiroaki Kaneko and Nariko Suzuki and Hiroshi Wabuka
                 and Koji Maemura",
  title =        "Realizing the {V80} and Its System Support Functions",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "2",
  pages =        "56--69",
  month =        apr,
  year =         "1990",
  CODEN =        "IEMIDZ",
  ISSN =         "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database; Science Citation Index database
                 (1980--2000)",
  abstract =     "Two 1-Kbyte cache memories and a branch prediction
                 mechanism help make this 32-bit microprocessor suitable
                 for multiprocessor and highly reliable system
                 configurations.",
  acknowledgement = ack-nhfb,
  affiliation =  "NEC Corp, Jpn",
  classcodes =   "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5440 (Multiprocessor systems
                 and techniques); C5220 (Computer architecture); C5470
                 (Performance evaluation and testing)",
  classification = "722; 723",
  corpsource =   "NEC Corp., Kanagawa, Japan",
  keywords =     "1 kB; 1-kB cache memories; 25 MHz; 32 bit; 32-b V80
                 microprocessor; 33 MHz; architectures; branch; Branch
                 Prediction Mechanism; Cache Memories; Computer
                 Architecture; Computer Systems, Digital; Computers,
                 Microcomputer; fault tolerant computing; functions;
                 high-reliability systems; microprocessor chips;
                 Multiprocessing; multiprocessor; parallel; parallel
                 machines; Pipeline Processing; pipeline processing;
                 prediction mechanism; system support; Two-Stage
                 Decoding; V80 Microprocessor",
  treatment =    "P Practical",
}

Related entries