Entry Circello:1995:SAM from ieeemicro.bib

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BibTeX entry

@Article{Circello:1995:SAM,
  author =       "Joe Circello and Greg Edgington and Dan McCarthy and
                 James Gay and David Schimke and Steven Sullivan and
                 Richard Duerden and Chris Hinds and Danny Marquette and
                 Lal Sood and Al Crouch and Daniel Chow",
  title =        "The Superscalar Architecture of the {MC68060}",
  journal =      j-IEEE-MICRO,
  volume =       "15",
  number =       "2",
  pages =        "10--21",
  month =        apr,
  year =         "1995",
  CODEN =        "IEMIDZ",
  ISSN =         "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database; Science Citation Index database
                 (1980--2000)",
  note =         "Presented at Hot Chips VI, Stanford University, CA,
                 August 14--16, 1994.",
  acknowledgement = ack-nhfb,
  affiliation =  "Motorola",
  affiliationaddress = "Phoenix, AZ, USA",
  classcodes =   "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220P (Parallel
                 architecture)",
  classification = "714.2; 721.2; 721.3; 722.2; 722.4",
  corpsource =   "Motorola Inc., Phoenix, AZ, USA",
  keywords =     "66 MHz; cmos integrated circuits; Computer
                 architecture; Cost effectiveness; Data address
                 translation caches; Digital arithmetic; Dual integer
                 execution units; Dual operand execution pipelines;
                 Embedded processing applications; features; Flip flop
                 circuits; high-; Logic design; MC68060 microprocessor;
                 microarchitectural; Microarchitectural features;
                 Microcomputers; Microprocessor chips; microprocessor
                 chips; Performance; performance embedded processing;
                 performance objectives; pipeline processing; Pipeline
                 processing systems; Single floating point execution
                 units; Superscalar architecture; superscalar
                 architecture; superscalar pipeline implementation;
                 Transistors; User code compatibility; User interfaces",
  treatment =    "P Practical",
}

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