Entry Wang:1995:DMP from ieeemicro.bib

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BibTeX entry

@Article{Wang:1995:DMP,
  author =       "Karl Wang and Chris Bryant and Mike Carlson and Tom
                 Elmer and Adrian Harris and Michael Garcia and C. S.
                 Hui and C. K. Leung and Brian Reynolds and Raymond Tang
                 and Laura Weber and Jim Wenzel and Glen Wilson and Mike
                 Becker",
  title =        "Designing the {MPC105 PCI} bridge\slash memory
                 controller",
  journal =      j-IEEE-MICRO,
  volume =       "15",
  number =       "2",
  pages =        "44--49",
  month =        apr,
  year =         "1995",
  CODEN =        "IEMIDZ",
  ISSN =         "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database; Science Citation Index database
                 (1980--2000)",
  note =         "Presented at Hot Chips VI, Stanford University, CA,
                 August 14--16, 1994.",
  acknowledgement = ack-nhfb,
  affiliation =  "Somerset Design Cent",
  affiliationaddress = "Austin, TX, USA",
  classcodes =   "B1265F (Microprocessors and microcomputers); B1265D
                 (Memory circuits); C5610P (Peripheral interfaces);
                 C5130 (Microprocessor chips); C5320G (Semiconductor
                 storage)",
  classification = "714.2; 721.3; 722.1; 722.2; 722.4; 723.2",
  corpsource =   "Somerset Design Center, Austin, TX, USA",
  keywords =     "Bit address bus; Bridge chip; Bridge/memory
                 controller; Buffer storage; cmos integrated circuits;
                 compliant bridge; Computer architecture; Computer
                 peripheral equipment; Data transfer; DRAM; DRAM chips;
                 flash ROM; high-; Interconnection networks; Interfaces
                 (computer); Memory controller; Microcomputers;
                 microcontrollers; Microprocessor chips; MPC105 PCI
                 bridge/memory controller; Multiprocessing systems; PCI
                 bus; performance memory controller; Peripheral
                 component interconnection; peripheral interfaces;
                 Platform specification compliant bridge;
                 platform-specification-; Power PC microprocessors;
                 Random access storage; rom; ROM; Secondary cache
                 controller; secondary cache controller; Specifications;
                 standard PC interfaces; synchronous DRAM",
  treatment =    "A Application; P Practical",
}

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