Entry Sakamura:1987:ATV from ieeemicro.bib

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BibTeX entry

@Article{Sakamura:1987:ATV,
  author =       "Ken Sakamura",
  title =        "Architecture of the {Tron VLSI CPU}",
  journal =      j-IEEE-MICRO,
  volume =       "7",
  number =       "2",
  pages =        "17--31",
  month =        apr,
  year =         "1987",
  CODEN =        "IEMIDZ",
  ISSN =         "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database; Science Citation Index database
                 (1980--2000)",
  acknowledgement = ack-nhfb,
  affiliationaddress = "Univ of Tokyo, Jpn",
  classcodes =   "C5130 (Microprocessor chips); C5220 (Computer
                 architecture); C6140B (Machine-oriented languages)",
  classification = "713; 714; 722; 723",
  corpsource =   "Dept. of Inf. Sci., Tokyo Univ., Japan",
  keywords =     "32 bit; 32-bit microprocessor; 64 bit; 64-bit
                 addressing; 64-bit addressing expandability; chips;
                 compiler-; compiler-oriented instruction set; computer
                 architecture; computer operating systems --- Program
                 Compilers; computers, microcomputer; exception
                 processing; instruction format; instruction set;
                 instruction sets; integrated circuits, VLSI; interrupt
                 processing; memory management; memory management unit;
                 microprocessor; open architecture;
                 operating-system-oriented; oriented instruction set;
                 standard instruction set; standards; trap processing;
                 TRON 32-bit microprocessor; TRON VLSI CPU; VLSI; VLSI
                 cpu-supported high-speed execution",
  treatment =    "P Practical",
}

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