Entry Kawasaki:1989:FPV from ieeemicro.bib

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BibTeX entry

@Article{Kawasaki:1989:FPV,
  author =       "Shumpei Kawasaki and Mitsuru Watabe and Shigeki
                 Morinaga",
  title =        "A floating-point {VLSI} chip for the {TRON}
                 architecture: an architecture for reliable numerical
                 programming",
  journal =      j-IEEE-MICRO,
  volume =       "9",
  number =       "3",
  pages =        "26--44",
  month =        jun,
  year =         "1989",
  CODEN =        "IEMIDZ",
  ISSN =         "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database;
                 garbo.uwasa.fi:/pc/doc-soft/fpbiblio.txt; Science
                 Citation Index database (1980--2000)",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  affiliation =  "Hitachi Ltd, Kodaira, Jpn",
  classcodes =   "B1265F (Microprocessors and microcomputers); B2570
                 (Semiconductor integrated circuits); C5220 (Computer
                 architecture); C5130 (Microprocessor chips)",
  classification = "722; 723; 921",
  corpsource =   "Hitachi Ltd., Tokyo, Japan",
  keywords =     "Computer Architecture; computer architecture; Computer
                 Interfaces; Computer Networks; Computer Operating
                 Systems--Program Compilers; coprocessor instructions;
                 Cordic Algorithm; Floating Point VLSI Chip;
                 floating-point VLSI chip; Gmicro VLSI cpu; Gmicro/200;
                 Gmicro/300; Gmicro/FPU; implementation; Instruction
                 Pipelining; Integrated Circuits, VLSI; Mathematical
                 Techniques--Digital Arithmetic; microprocessor chips;
                 microprocessors; numerical programming; Protocol
                 Sequences; Protocols; reliable; requirements; TRON
                 Architecture; TRON architecture; VLSI",
  treatment =    "P Practical",
}

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