Entry Lee:1991:FPP from sigplan1990.bib

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BibTeX entry

@Article{Lee:1991:FPP,
  author =       "Roland L. Lee and Alex Y. Kwok and Fay{\'e} A.
                 Briggs",
  title =        "The Floating-Point Performance of a Superscalar
                 {SPARC} Processor",
  journal =      j-SIGPLAN,
  volume =       "26",
  number =       "4",
  pages =        "28--37",
  month =        apr,
  year =         "1991",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  abstract =     "The floating point performance of superscalar SPARC
                 processors is evaluated based on empirical data from 12
                 benchmarks. This evaluation is done in the context of
                 two software instruction scheduling optimizations: loop
                 unrolling and software pipelining, and for three
                 machine models: 1-scalar, 2-scalar and 4-scalar. The
                 authors also consider the effect of the memory system
                 on the performance improvements. Superscalar hardware
                 alone exhibit little performance improvement without
                 software optimization. Of the two scheduling methods,
                 software pipelining more effectively takes advantage of
                 increased hardware parallelism, and achieves near
                 optimal speedup on the 4-scalar machine model. The
                 performance of loop unrolling is restricted by the
                 limited number of floating point registers in the SPARC
                 architecture. The best performance level is obtained by
                 applying both optimization techniques. A superscalar
                 SPARC processor can provide improved floating point
                 performance but with significant software and hardware
                 development costs.",
  acknowledgement = ack-nhfb,
  affiliation =  "Sun Microsyst. Inc., Mountain View, CA, USA",
  classification = "C5220 (Computer architecture); C5470 (Performance
                 evaluation and testing)",
  confdate =     "8-11 April 1991",
  conflocation = "Santa Clara, CA, USA",
  confsponsor =  "IEEE; ACM",
  keywords =     "Benchmarks; Development costs; Floating point
                 performance; Floating point registers; Hardware
                 parallelism; Loop unrolling; Memory system; N-scalar
                 machine models; Optimal speedup; Software instruction
                 scheduling optimizations; Software pipelining; SPARC
                 architecture; Superscalar SPARC processor",
  thesaurus =    "Optimisation; Parallel architectures; Performance
                 evaluation; Pipeline processing; Scheduling",
}

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