Entry Thekkath:1994:HSS from sigplan1990.bib

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BibTeX entry

@Article{Thekkath:1994:HSS,
  author =       "Chandramohan A. Thekkath and Henry M. Levy",
  title =        "Hardware and software support for efficient exception
                 handling",
  journal =      j-SIGPLAN,
  volume =       "29",
  number =       "11",
  pages =        "110--119",
  month =        nov,
  year =         "1994",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:16:57 MST 2003",
  bibsource =    "http://portal.acm.org/; http://www.acm.org/pubs/toc/",
  URL =          "http://www.acm.org:80/pubs/citations/proceedings/asplos/195473/p110-thekkath/",
  abstract =     "Program-synchronous exceptions, for example,
                 breakpoints, watchpoints, illegal opcodes, and memory
                 access violations, provide information about {\em
                 exceptional\/} conditions, interrupting the program and
                 vectoring to an operating system handler. Over the last
                 decade, however, programs and run-time systems have
                 increasingly employed these mechanisms as a performance
                 optimization to detect {\em normal\/} and {\em
                 expected\/} conditions. Unfortunately, current
                 architecture and operating system structures are
                 designed for exceptional or erroneous conditions, where
                 performance is of secondary importance, rather than
                 normal conditions. Consequently, this has limited the
                 practicality of such hardware-based detection
                 mechanisms. We propose both hardware and software
                 structures that permit efficient handling of
                 synchronous exceptions by user-level code. We
                 demonstrate a software implementation that reduces
                 exception-delivery cost by an order-of-magnitude on
                 current RISC processors, and show the performance
                 benefits of that mechanism for several example
                 applications.",
  acknowledgement = ack-nhfb,
  classification = "C5220 (Computer architecture); C6130 (Data handling
                 techniques); C6150J (Operating systems)",
  conflocation = "San Jose, CA, USA; 4-7 Oct. 1994",
  conftitle =    "Sixth International Conference on Architectural
                 Support for Programming Languages and Operating Systems
                 (ASPLOS-VI)",
  corpsource =   "Dept. of Comput. Sci. and Eng., Washington Univ.,
                 Seattle, WA, USA",
  keywords =     "breakpoints; design; erroneous conditions; exception
                 delivery cost; exception delivery synchronous
                 exceptions; exception handling; hardware support;
                 hardware-based detection mechanisms; illegal opcodes;
                 languages; measurement; memory access violation;
                 operating system handler; operating systems
                 (computers); optimisation; performance; performance
                 benefits; performance optimization; program-synchronous
                 exceptions; reduced instruction set computing; RISC
                 processors; run-time systems; software support;
                 synchronous exceptions; theory; user-level code;
                 watchpoints",
  sponsororg =   "ACM; IEEE Comput. Soc",
  subject =      "{\bf D.3.3} Software, PROGRAMMING LANGUAGES, Language
                 Constructs and Features, Control structures. {\bf C.0}
                 Computer Systems Organization, GENERAL, Instruction set
                 design. {\bf C.4} Computer Systems Organization,
                 PERFORMANCE OF SYSTEMS.",
  treatment =    "P Practical",
}

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