Entry Thekkath:1994:EMH from sigplan1990.bib

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BibTeX entry

@Article{Thekkath:1994:EMH,
  author =       "Radhika Thekkath and Susan J. Eggers",
  title =        "The effectiveness of multiple hardware contexts",
  journal =      j-SIGPLAN,
  volume =       "29",
  number =       "11",
  pages =        "328--337",
  month =        nov,
  year =         "1994",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:16:57 MST 2003",
  bibsource =    "http://portal.acm.org/; http://www.acm.org/pubs/toc/",
  URL =          "http://www.acm.org:80/pubs/citations/proceedings/asplos/195473/p328-thekkath/",
  abstract =     "Multithreaded processors are used to tolerate long
                 memory latencies. By executing threads loaded in
                 multiple hardware contexts, an otherwise idle processor
                 can keep busy, thus increasing its utilization.
                 However, the larger size of a multi-thread working set
                 can have a negative effect on cache conflict misses. In
                 this paper we evaluate the two phenomena together,
                 examining their combined effect on execution time. The
                 usefulness of multiple hardware contexts depends on:
                 program data locality, cache organization and degree of
                 multiprocessing. Multiple hardware contexts are most
                 effective on programs that have been optimized for data
                 locality. For these programs, execution time dropped
                 with increasing contexts, over widely varying
                 architectures. With unoptimized applications, multiple
                 contexts had limited value. The best performance was
                 seen with only two contexts, and only on uniprocessors
                 and small multiprocessors. The behavior of the
                 unoptimized applications changed more noticeably with
                 variations in cache associativity and cache hierarchy,
                 unlike the optimized programs. As a mechanism for
                 exploiting program parallelism, an additional processor
                 is clearly better than another context. However, there
                 were many configurations for which the addition of a
                 few hardware contexts brought as much or greater
                 performance than a larger multiprocessor with fewer
                 than the optimal number of contexts.",
  acknowledgement = ack-nhfb,
  classification = "C5320G (Semiconductor storage); C5440
                 (Multiprocessing systems); C6110P (Parallel
                 programming); C6120 (File organisation); C6150N
                 (Distributed systems software)",
  conflocation = "San Jose, CA, USA; 4-7 Oct. 1994",
  conftitle =    "Sixth International Conference on Architectural
                 Support for Programming Languages and Operating Systems
                 (ASPLOS-VI)",
  corpsource =   "Dept. of Comput. Sci. and Eng., Washington Univ.,
                 Seattle, WA, USA",
  keywords =     "cache associativity; cache conflict misses; cache
                 hierarchy; cache organization; cache storage; data
                 locality; design; long; long memory latencies;
                 measurement; multi-thread working set; multiple
                 hardware contexts; multiprocessing; multiprocessing
                 systems; multithreaded processors; parallel
                 programming; performance; program data locality;
                 program parallelism; storage management; theory;
                 unoptimized applications",
  sponsororg =   "ACM; IEEE Comput. Soc",
  subject =      "{\bf C.5.3} Computer Systems Organization, COMPUTER
                 SYSTEM IMPLEMENTATION, Microcomputers. {\bf C.4}
                 Computer Systems Organization, PERFORMANCE OF
                 SYSTEMS.",
  treatment =    "P Practical",
}

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