Entry Upton:1994:RAH from sigplan1990.bib

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BibTeX entry

@Article{Upton:1994:RAH,
  author =       "Michael Upton and Thomas Huff and Trevor Mudge and
                 Richard Brown",
  title =        "Resource allocation in a high clock rate
                 microprocessor",
  journal =      j-SIGPLAN,
  volume =       "29",
  number =       "11",
  pages =        "98--109",
  month =        nov,
  year =         "1994",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:16:57 MST 2003",
  bibsource =    "http://portal.acm.org/; http://www.acm.org/pubs/toc/",
  URL =          "http://www.acm.org:80/pubs/citations/proceedings/asplos/195473/p98-upton/",
  abstract =     "This paper discusses the design of a high clock rate
                 (300 MHz) processor. The architecture is described, and
                 the goals for the design are explained. The performance
                 of three processor models is evaluated using
                 trace-driven simulation. A cost model is used to
                 estimate the resources required to build processors
                 with varying sizes of on-chip memories, in both single
                 and dual issue models. Recommendations are then made to
                 increase the effectiveness of each of the models.",
  acknowledgement = ack-nhfb,
  affiliation =  "Dept. of Electr. Eng. and Comput. Sci., Michigan
                 Univ., Ann Arbor, MI, USA",
  classification = "C5130 (Microprocessor chips); C5220 (Computer
                 architecture); C5230 (Digital arithmetic methods);
                 C6150J (Operating systems)",
  confdate =     "4-7 Oct. 1994",
  conflocation = "San Jose, CA, USA; 4-7 Oct. 1994",
  confsponsor =  "ACM; IEEE Comput. Soc",
  conftitle =    "Sixth International Conference on Architectural
                 Support for Programming Languages and Operating Systems
                 (ASPLOS-VI)",
  corpsource =   "Dept. of Electr. Eng. and Comput. Sci., Michigan
                 Univ., Ann Arbor, MI, USA",
  keywords =     "computer architecture; Cost model; cost model; design;
                 floating point arithmetic; Floating point latency;
                 floating point latency; High clock rate microprocessor;
                 high clock rate microprocessor; measurement;
                 microprocessor chips; Nonblocking cache; nonblocking
                 cache; On-chip memories; on-chip memories; performance;
                 performance evaluation; Pipelining; pipelining;
                 Prefetching; prefetching; Processor model performance;
                 processor model performance; Resource allocation;
                 resource allocation; theory; Trace-driven simulation;
                 trace-driven simulation; virtual machines",
  sponsororg =   "ACM; IEEE Comput. Soc",
  subject =      "{\bf C.1.2} Computer Systems Organization, PROCESSOR
                 ARCHITECTURES, Multiple Data Stream Architectures
                 (Multiprocessors), Pipeline processors**. {\bf D.4.2}
                 Software, OPERATING SYSTEMS, Storage Management,
                 Allocation/deallocation strategies. {\bf C.4} Computer
                 Systems Organization, PERFORMANCE OF SYSTEMS.",
  thesaurus =    "Computer architecture; Floating point arithmetic;
                 Microprocessor chips; Performance evaluation; Resource
                 allocation; Virtual machines",
  treatment =    "P Practical; T Theoretical or Mathematical",
}

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