Entry Seznec:1996:MAB from sigplan1990.bib

Last update: Thu Apr 12 03:37:15 MDT 2012                Valid HTML 3.2!

Index sections

Top | Symbols | Numbers | Math | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z

BibTeX entry

@Article{Seznec:1996:MAB,
  author =       "Andr{\'e} Seznec and St{\'e}phan Jourdan and Pascal
                 Sainrat and Pierre Michaud",
  title =        "Multiple-Block Ahead Branch Predictors",
  journal =      j-SIGPLAN,
  volume =       "31",
  number =       "9",
  pages =        "116--127",
  month =        sep,
  year =         "1996",
  CODEN =        "SINODQ",
  ISBN =         "0-89791-767-7",
  ISBN-13 =      "978-0-89791-767-4",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sat May 1 15:50:57 MDT 1999",
  bibsource =    "http://www.acm.org/pubs/toc/",
  note =         "Co-published as SIGOPS Operating Systems Review {\bf
                 30}(5), December 1996, and as SIGARCH Computer
                 Architecture News, {\bf 24}(special issue), October
                 1996.",
  URL =          "http://www.acm.org:80/pubs/citations/proceedings/asplos/237090/p116-seznec/",
  acknowledgement = ack-nhfb,
  keywords =     "algorithms; experimentation; performance",
  subject =      "{\bf B.5.2} Hardware, REGISTER-TRANSFER-LEVEL
                 IMPLEMENTATION, Design Aids, Optimization. {\bf B.5.1}
                 Hardware, REGISTER-TRANSFER-LEVEL IMPLEMENTATION,
                 Design, Control design. {\bf B.5.1} Hardware,
                 REGISTER-TRANSFER-LEVEL IMPLEMENTATION, Design, Memory
                 design.",
}

Related entries