Entry Gloy:1999:PPU from toplas.bib

Last update: Tue May 1 02:05:46 MDT 2012                Valid HTML 3.2!

Index sections

Top | Symbols | Math | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z

BibTeX entry

@Article{Gloy:1999:PPU,
  author =       "Nikolas Gloy and Michael D. Smith",
  title =        "Procedure placement using temporal-ordering
                 information",
  journal =      j-TOPLAS,
  volume =       "21",
  number =       "5",
  pages =        "977--1027",
  month =        sep,
  year =         "1999",
  CODEN =        "ATPSDT",
  ISSN =         "0164-0925 (print), 1558-4593 (electronic)",
  ISSN-L =       "0164-0925",
  bibdate =      "Tue Sep 26 10:12:58 MDT 2000",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toplas/;
                 http://www.math.utah.edu/pub/tex/bib/toplas.bib",
  URL =          "http://www.acm.org/pubs/articles/journals/toplas/1999-21-5/p977-gloy/p977-gloy.pdf;
                 http://www.acm.org/pubs/citations/journals/toplas/1999-21-5/p977-gloy/",
  abstract =     "Instruction cache performance is important to
                 instruction fetch efficiency and overall processor
                 performance. The layout of an executable has a
                 substantial effect on the cache miss rate and the
                 instruction working set size during execution. This
                 means that the performance of an executable can be
                 improved by applying a code-placement algorithm that
                 minimizes instruction cache conflicts and improves
                 spatial locality. We describe an algorithm for
                 procedure placement, one type of code placement, that
                 significantly differs from previous approaches in the
                 type of information used to drive the placement
                 algorithm. In particular, we gather temporal-ordering
                 information that summarizes the interleaving of
                 procedures in a program trace. Our algorithm uses this
                 information along with cache configuration and
                 procedure size information to better estimate the
                 conflict cost of a potential procedure ordering. It
                 optimizes the procedure placement for single level and
                 multilevel caches. In addition to reducing instruction
                 cache conflicts, the algorithm simultaneously minimizes
                 the instruction working set size of the program. We
                 compare the performance of our algorithm with a
                 particularly successful procedure-placement algorithm
                 and show noticeable improvements in the instruction
                 cache behavior, while maintaining the same instruction
                 working set size.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Programming Languages and
                 Systems",
  generalterms = "Algorithms; Performance",
  keywords =     "code placement; conflict misses; temporal profiling;
                 working-set optimization",
  subject =      "Hardware --- Memory Structures --- Performance
                 Analysis and Design Aids** (B.3.3): {\bf Simulation**};
                 Software --- Programming Languages --- Processors
                 (D.3.4): {\bf Compilers}; Software --- Programming
                 Languages --- Processors (D.3.4): {\bf Optimization}",
}

Related entries