# bibtab

bibtype: article
filename: fparith.bib
label: Smith:1988:ASD
author: S. G. Smith and P. B. Denyer
title: Advanced serial-data computation
journal: j-J-PAR-DIST-COMP
volume: 5
number: 3
pages: 228--249
month: jun
monthnumber: 6
year: 1988
CODEN: JPDCER
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Sat Apr 12 19:06:31 MDT 1997
bibsource: Compendex database; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1997.04.12 19:06:31 MDT
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
affiliationaddress: Univ of Edinburgh, Edinburgh, Scotl
corpsource: Department of Electr. Eng., Edinburgh University, UK
journalURL: http://www.sciencedirect.com/science/journal/07437315
journalabr: J Parallel Distrib Comput
treatment: P Practical
rawauthor: S. G. Smith and P. B. Denyer
rawtitle: Advanced serial-data computation
keywords:
arithmetic operations; bit-parallel architectures; Computational Methods; computational modules; computer architecture; computers, digital; digital arithmetic; dynamic range; high-; multiwire; multiwire techniques; performance computer arithmetic; serial data architectures; serial data computation; serial-data architectures; signal processing --- Digital Techniques; symmetric-coded distributed arithmetic; techniques

entry:
@Article{Smith:1988:ASD,
  author =       "S. G. Smith and P. B. Denyer",
  title =        "Advanced serial-data computation",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "5",
  number =       "3",
  pages =        "228--249",
  month =        jun,
  year =         "1988",
  CODEN =        "JPDCER",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Sat Apr 12 19:06:31 MDT 1997",
  bibsource =    "Compendex database;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliationaddress = "Univ of Edinburgh, Edinburgh, Scotl",
  classification = "716; 718; 721; 722; 723; C5230 (Digital arithmetic
                 methods)",
  corpsource =   "Department of Electr. Eng., Edinburgh University, UK",
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
  journalabr =   "J Parallel Distrib Comput",
  keywords =     "arithmetic operations; bit-parallel architectures;
                 Computational Methods; computational modules; computer
                 architecture; computers, digital; digital arithmetic;
                 dynamic range; high-; multiwire; multiwire techniques;
                 performance computer arithmetic; serial data
                 architectures; serial data computation; serial-data
                 architectures; signal processing --- Digital
                 Techniques; symmetric-coded distributed arithmetic;
                 techniques",
  treatment =    "P Practical",
}


bibtype: article
filename: fparith.bib
label: Sohie:1988:DSP
author: G. R. L. Sohie and K. L. Kloker
title: A Digital Signal Processor with IEEE Floating-Point Arithmetic
journal: j-IEEE-MICRO
volume: 8
number: 6
pages: 49--67
month: nov
monthnumber: 11
year: 1988
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.16780
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Micro
acknowledgement: ack-nj
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawauthor: G. R. L. Sohie and K. L. Kloker
rawtitle: A Digital Signal Processor with {IEEE} Floating-Point Arithmetic
entry:
@Article{Sohie:1988:DSP,
  author =       "G. R. L. Sohie and K. L. Kloker",
  title =        "A Digital Signal Processor with {IEEE} Floating-Point
                 Arithmetic",
  journal =      j-IEEE-MICRO,
  volume =       "8",
  number =       "6",
  pages =        "49--67",
  month =        nov # "\slash " # dec,
  year =         "1988",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.16780",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  summary =      "A overview is given of Motorola's DSP96002, a digital
                 signal processor that implements IEEE-standard
                 floating-point arithmetic. It is designed for graphics,
                 image processing, spectral analysis and scientific
                 computing applications. Performance peaks \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Sridharan:1988:BFP
author: S. Sridharan and G. Dickman
title: Block floating-point implementation of digital filters using the DSP56000
journal: j-MICROPROC-MICROSYS
volume: 12
number: 6
pages: 299--308
month: aug
monthnumber: 8
year: 1988
CODEN: MIMID5
ISSN: 0141-9331 (print), 1872-9436 (electronic) OR 01419331 (print), 18729436 (electronic)
ISSNL: 0141-9331 OR 01419331
bibdate: Sat Nov 9 08:26:18 MST 2002
bibsource: ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.09 08:26:18 MST
fjournal: Microprocessors and Microsystems
acknowledgement: ack-nhfb
rawauthor: S. Sridharan and G. Dickman
rawtitle: Block floating-point implementation of digital filters using the {DSP56000}
subject:
G. Mathematics of Computing; G.m MISCELLANEOUS; I. Computing Methodologies; I.5 PATTERN RECOGNITION; C. Computer Systems Organization; C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS; C. Computer Systems Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION

affiliation:
Queensland Institute of Technology, Queensland, Australia; Queensland Institute of Technology, Queensland, Australia

entry:
@Article{Sridharan:1988:BFP,
  author =       "S. Sridharan and G. Dickman",
  title =        "Block floating-point implementation of digital filters
                 using the {DSP56000}",
  journal =      j-MICROPROC-MICROSYS,
  volume =       "12",
  number =       "6",
  pages =        "299--308",
  month =        aug,
  year =         "1988",
  CODEN =        "MIMID5",
  ISSN =         "0141-9331 (print), 1872-9436 (electronic)",
  ISSN-L =       "0141-9331",
  bibdate =      "Sat Nov 9 08:26:18 MST 2002",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Queensland Institute of Technology, Queensland,
                 Australia; Queensland Institute of Technology,
                 Queensland, Australia",
  bibno =        "49397",
  catcode =      "G.m; I.5.4; C.3; C.5.3",
  CRclass =      "I.5.4 Applications; I.5.4 Signal processing; C.3
                 Signal processing systems; C.5.3 Microcomputers; C.5.3
                 Microprocessors",
  descriptor =   "Mathematics of Computing, MISCELLANEOUS; Computing
                 Methodologies, PATTERN RECOGNITION, Applications,
                 Signal processing; Computer Systems Organization,
                 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS, Signal
                 processing systems; Computer Systems Organization,
                 COMPUTER SYSTEM IMPLEMENTATION, Microcomputers,
                 Microprocessors",
  fjournal =     "Microprocessors and Microsystems",
  genterm =      "ALGORITHMS; DESIGN",
  guideno =      "1988-12500",
  journalabbrev = "Microprocess. Microsyst.",
  subject =      "G. Mathematics of Computing; G.m MISCELLANEOUS; I.
                 Computing Methodologies; I.5 PATTERN RECOGNITION; C.
                 Computer Systems Organization; C.3 SPECIAL-PURPOSE AND
                 APPLICATION-BASED SYSTEMS; C. Computer Systems
                 Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION",
}


bibtype: book
filename: fparith.bib
label: Startz:1988:IPC
author: Richard Startz
publisher: pub-BRADY
address: pub-BRADY:adr
edition: Third
pages: xviii + 296
year: 1988
ISBN: 0-13-246604-X OR 013246604X
ISBN13: 978-0-13-246604-2 OR 9780132466042
LCCN: QA76.8.I2923 S79 1988
bibdate: Wed Sep 14 20:23:49 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.14 20:23:49 ???
acknowledgement: ack-nj
rawauthor: Richard Startz
title:
8087 / 80287 / 80387 for the IBM PC and Compatibles: Applications and Programming with Intel's Math Coprocessors

rawtitle:
8087\slash 80287\slash 80387 for the {IBM PC} and Compatibles: Applications and Programming with {Intel}'s Math Coprocessors

entry:
@Book{Startz:1988:IPC,
  author =       "Richard Startz",
  title =        "8087\slash 80287\slash 80387 for the {IBM PC} and
                 Compatibles: Applications and Programming with
                 {Intel}'s Math Coprocessors",
  publisher =    pub-BRADY,
  address =      pub-BRADY:adr,
  edition =      "Third",
  pages =        "xviii + 296",
  year =         "1988",
  ISBN =         "0-13-246604-X",
  ISBN-13 =      "978-0-13-246604-2",
  LCCN =         "QA76.8.I2923 S79 1988",
  bibdate =      "Wed Sep 14 20:23:49 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: inproceedings
filename: fparith.bib
label: Stasinski:1988:MRE
author: R. Stasinski and E. Lukasik
title: Minimization of rounding errors in WFTA programs
volume: 3
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1423--1426
year: 1988
bibdate: Sat Jul 16 11:25:03 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:03 MDT
acknowledgement: ack-nhfb
rawauthor: R. Stasinski and E. Lukasik
rawtitle: Minimization of rounding errors in {WFTA} programs
booktitle:
Acoustics, Speech, and Signal Processing, 1988. ICASSP-88., 1988 International Conference on. 11--14 April 1988

rawbooktitle:
Acoustics, Speech, and Signal Processing, 1988. {ICASSP-88., 1988} International Conference on. 11--14 April 1988

entry:
@InProceedings{Stasinski:1988:MRE,
  author =       "R. Stasinski and E. Lukasik",
  booktitle =    "Acoustics, Speech, and Signal Processing, 1988.
                 {ICASSP-88., 1988} International Conference on. 11--14
                 April 1988",
  title =        "Minimization of rounding errors in {WFTA} programs",
  volume =       "3",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1423--1426",
  year =         "1988",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:03 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Two ideas linked with high-precision computation of
                 WFTAs (Winograd-Fourier transform algorithm) using
                 fixed-point arithmetic are analyzed. Use of the best,
                 optimized small-N DFT (discrete Fourier transform)
                 modules is considered. The sizes \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Stouraitis:1988:FPL
author: Thanos Stouraitis and Fred J. Taylor
title: Floating-point to logarithmic encoder error analysis
journal: j-IEEE-TRANS-COMPUT
volume: 37
number: 7
pages: 858--863
month: jul
monthnumber: 7
year: 1988
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.2232
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
affiliation: Ohio State University of University, Columbus; University of Florida, Gainesville
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Thanos Stouraitis and Fred J. Taylor
rawtitle: Floating-point to logarithmic encoder error analysis
subject:
F. Theory of Computation; F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY; G. Mathematics of Computing; G.m MISCELLANEOUS; C. Computer Systems Organization; C.1 PROCESSOR ARCHITECTURES

entry:
@Article{Stouraitis:1988:FPL,
  author =       "Thanos Stouraitis and Fred J. Taylor",
  title =        "Floating-point to logarithmic encoder error analysis",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "37",
  number =       "7",
  pages =        "858--863",
  month =        jul,
  year =         "1988",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.2232",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Ohio State University of University, Columbus;
                 University of Florida, Gainesville",
  ajournal =     "IEEE Trans. Comput.",
  bibno =        "48698",
  catcode =      "F.2.1; G.m; C.1.m",
  CRclass =      "F.2.1 Numerical Algorithms and Problems; F.2.1
                 Number-theoretic computations; C.1.m Miscellaneous",
  descriptor =   "Theory of Computation, ANALYSIS OF ALGORITHMS AND
                 PROBLEM COMPLEXITY, Numerical Algorithms and Problems,
                 Number-theoretic computations; Mathematics of
                 Computing, MISCELLANEOUS; Computer Systems
                 Organization, PROCESSOR ARCHITECTURES, Miscellaneous",
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  genterm =      "DESIGN; THEORY; VERIFICATION",
  guideno =      "1988-08687",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  journalabbrev = "IEEE Trans. Comput.",
  subject =      "F. Theory of Computation; F.2 ANALYSIS OF ALGORITHMS
                 AND PROBLEM COMPLEXITY; G. Mathematics of Computing;
                 G.m MISCELLANEOUS; C. Computer Systems Organization;
                 C.1 PROCESSOR ARCHITECTURES",
  summary =      "The logarithmic number (LNS), which supports
                 high-speed, high-precision arithmetic, is envisioned as
                 a possible arithmetic coprocessor attachment to a
                 floating-point (FLP) processor. An error analysis of an
                 FLP-to-LNS encoder is presented. Analytic \ldots{}",
}


bibtype: manual
filename: fparith.bib
label: Sun:1988:PG
title: Programmer's guides
publisher: Sun Microsystems
address: Mountain View, CA, USA
pages: 858--863
year: 1988
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
note: 12 volumes in 1 case.
keywords: Operating systems (Computers); Sun computers --- Programming.; SunOS (Computer operating system)
acknowledgement: ack-nhfb
rawnote: 12 volumes in 1 case.
rawtitle: Programmer's guides
remark:
Title from container. Contents sheet has title: 4.0 programmer's guides minibox. ``Revision A, of 9 May 1988.''--Contents. ``825-1050-10.''--Contents. C programmer's guide --- Assembly language reference for the Sun-2 and Sun-3 --- Programming utilities and libraries --- Debugging tools --- Network programming --- Writing device drivers --- Floating point programmer's guide --- SunView 1 programmer's guide --- SunView 1 system programmer's guide --- Pixrect reference manual --- SunCGI reference manual --- SunCore reference manual.

entry:
@Manual{Sun:1988:PG,
  title =        "Programmer's guides",
  publisher =    "Sun Microsystems",
  address =      "Mountain View, CA, USA",
  year =         "1988",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "12 volumes in 1 case.",
  acknowledgement = ack-nhfb,
  keywords =     "Operating systems (Computers); Sun computers ---
                 Programming.; SunOS (Computer operating system)",
  remark =       "Title from container. Contents sheet has title: 4.0
                 programmer's guides minibox. ``Revision A, of 9 May
                 1988.''--Contents. ``825-1050-10.''--Contents. C
                 programmer's guide --- Assembly language reference for
                 the Sun-2 and Sun-3 --- Programming utilities and
                 libraries --- Debugging tools --- Network programming
                 --- Writing device drivers --- Floating point
                 programmer's guide --- SunView 1 programmer's guide ---
                 SunView 1 system programmer's guide --- Pixrect
                 reference manual --- SunCGI reference manual ---
                 SunCore reference manual.",
}


bibtype: article
filename: fparith.bib
label: Taylor:1988:BLN
author: F. J. Taylor and R. Gill and J. Joseph and J. Radke
title: A 20 Bit Logarithmic Number System Processor
journal: j-IEEE-TRANS-COMPUT
volume: C-37
number: 2
pages: 190--199
year: 1988
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.2148
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jun 24 19:49:19 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 19:49:19 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: F. J. Taylor and R. Gill and J. Joseph and J. Radke
rawtitle: A 20 Bit Logarithmic Number System Processor
abstract:
The architecture and performance of a 20-bit arithmetic processor based on the logarithmic number system (LNS) is described. The processor performed LNS multiplication and division rapidly and with a low hardware complexity. Addition and subtraction in the LNS require the support of a table lookup unit. A scheme is proposed to minimize this complexity using a partitioned memory (ROM) and a PLA (programmable logic array). For performance evaluation, the target technology is integrated Schottky logic. The processor is shown to compare well with, if not to outperform, existing floating point (FLP) processors of equivalent range and precision. The speed-power-product ratio of an equivalent FLP processor, compared with that of the LNS processor, is reported to be 20 to 1 in the case of the square and square-root operation and 1 to 1 in the case of addition and subtraction. For multiplication and division, this ratio is about 5 to 1.

rawabstract:
The architecture and performance of a 20-bit arithmetic processor based on the logarithmic number system (LNS) is described. The processor performed LNS multiplication and division rapidly and with a low hardware complexity. Addition and subtraction in the LNS require the support of a table lookup unit. A scheme is proposed to minimize this complexity using a partitioned memory (ROM) and a PLA (programmable logic array). For performance evaluation, the target technology is integrated Schottky logic. The processor is shown to compare well with, if not to outperform, existing floating point (FLP) processors of equivalent range and precision. The speed-power-product ratio of an equivalent FLP processor, compared with that of the LNS processor, is reported to be 20 to 1 in the case of the square and square-root operation and 1 to 1 in the case of addition and subtraction. For multiplication and division, this ratio is about 5 to 1.

entry:
@Article{Taylor:1988:BLN,
  author =       "F. J. Taylor and R. Gill and J. Joseph and J. Radke",
  title =        "A 20 Bit Logarithmic Number System Processor",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "C-37",
  number =       "2",
  pages =        "190--199",
  year =         "1988",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.2148",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jun 24 19:49:19 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The architecture and performance of a 20-bit
                 arithmetic processor based on the logarithmic number
                 system (LNS) is described. The processor performed LNS
                 multiplication and division rapidly and with a low
                 hardware complexity. Addition and subtraction in the
                 LNS require the support of a table lookup unit. A
                 scheme is proposed to minimize this complexity using a
                 partitioned memory (ROM) and a PLA (programmable logic
                 array). For performance evaluation, the target
                 technology is integrated Schottky logic. The processor
                 is shown to compare well with, if not to outperform,
                 existing floating point (FLP) processors of equivalent
                 range and precision. The speed-power-product ratio of
                 an equivalent FLP processor, compared with that of the
                 LNS processor, is reported to be 20 to 1 in the case of
                 the square and square-root operation and 1 to 1 in the
                 case of addition and subtraction. For multiplication
                 and division, this ratio is about 5 to 1.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: misc
filename: fparith.bib
label: Taylor:1988:HFP
author: Fred J. Taylor
title: Hybrid floating point / logarithmic number system arithmetic processor
pages: 190--199
day: 19
month: jan
monthnumber: 1
year: 1988
bibdate: Tue Jan 08 21:48:35 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.01.08 21:48:35 ???
URL: http://www.freepatentsonline.com/4720809.html
acknowledgement: ack-nhfb
howpublished: United States Patent 4,720,809
rawauthor: Fred J. Taylor
rawtitle: Hybrid floating point\slash logarithmic number system arithmetic processor
abstract:
A hybrid arithmetic processor which combines attributes of conventional floating point (F.P.) arithmetic with logarithmic number system (LNS) arithmetic. The arithmetic processor includes an input section (forward code converter) for converting input operands in F.P. format to intermediate operands in LNS format, an LNS arithmetic section for performing an arithmetic operation on the LNS intermediate operands and providing an intermediate output in LNS format, and an output section (inverse code converter) for converting the LNS intermediate output to an output in F.P. format. Significantly, output is provided in normalized floating point format but without the need for a time-consuming exponent alignment operation. Arithmetic operations, including addition and multiplication, are accomplished at a high speed, which speed moreover is constant and independent of the data. An efficient accumulator structure and the structure of an ultra-fast numeric processor are disclosed.

rawabstract:
A hybrid arithmetic processor which combines attributes of conventional floating point (F.P.) arithmetic with logarithmic number system (LNS) arithmetic. The arithmetic processor includes an input section (forward code converter) for converting input operands in F.P. format to intermediate operands in LNS format, an LNS arithmetic section for performing an arithmetic operation on the LNS intermediate operands and providing an intermediate output in LNS format, and an output section (inverse code converter) for converting the LNS intermediate output to an output in F.P. format. Significantly, output is provided in normalized floating point format but without the need for a time-consuming exponent alignment operation. Arithmetic operations, including addition and multiplication, are accomplished at a high speed, which speed moreover is constant and independent of the data. An efficient accumulator structure and the structure of an ultra-fast numeric processor are disclosed.

entry:
@Misc{Taylor:1988:HFP,
  author =       "Fred J. Taylor",
  title =        "Hybrid floating point\slash logarithmic number system
                 arithmetic processor",
  howpublished = "United States Patent 4,720,809",
  day =          "19",
  month =        jan,
  year =         "1988",
  bibdate =      "Tue Jan 08 21:48:35 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.freepatentsonline.com/4720809.html",
  abstract =     "A hybrid arithmetic processor which combines
                 attributes of conventional floating point (F.P.)
                 arithmetic with logarithmic number system (LNS)
                 arithmetic. The arithmetic processor includes an input
                 section (forward code converter) for converting input
                 operands in F.P. format to intermediate operands in LNS
                 format, an LNS arithmetic section for performing an
                 arithmetic operation on the LNS intermediate operands
                 and providing an intermediate output in LNS format, and
                 an output section (inverse code converter) for
                 converting the LNS intermediate output to an output in
                 F.P. format. Significantly, output is provided in
                 normalized floating point format but without the need
                 for a time-consuming exponent alignment operation.
                 Arithmetic operations, including addition and
                 multiplication, are accomplished at a high speed, which
                 speed moreover is constant and independent of the data.
                 An efficient accumulator structure and the structure of
                 an ultra-fast numeric processor are disclosed.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Thistle:1988:PAH
author: M. R. Thistle and B. J. Smith
title: A processor architecture for Horizon
crossref: IEEE:1988:PSN
volume: 1
pages: 35--41
year: 1988
bibdate: Thu Apr 16 07:55:03 MDT 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.16 07:55:03 MDT
acknowledgement: ack-nhfb
corpsource: Supercomput. Res. Center, Lanham, MD, USA
treatment: P Practical
rawauthor: M. R. Thistle and B. J. Smith
rawtitle: A processor architecture for {Horizon}
keywords:
floating-point operations; Horizon; horizontal instruction set; parallel architectures; parallel machines; processor architecture; scalable shared-memory MIMD computer; scalable shared-memory multiple-instruction-stream-multiple-data-stream computer; scalar processors; three-dimensional nearest-neighbor network

entry:
@InProceedings{Thistle:1988:PAH,
  author =       "M. R. Thistle and B. J. Smith",
  title =        "A processor architecture for {Horizon}",
  crossref =     "IEEE:1988:PSN",
  volume =       "1",
  pages =        "35--41",
  year =         "1988",
  bibdate =      "Thu Apr 16 07:55:03 MDT 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "C5220 (Computer architecture); C5440 (Multiprocessor
                 systems and techniques)",
  corpsource =   "Supercomput. Res. Center, Lanham, MD, USA",
  keywords =     "floating-point operations; Horizon; horizontal
                 instruction set; parallel architectures; parallel
                 machines; processor architecture; scalable
                 shared-memory MIMD computer; scalable shared-memory
                 multiple-instruction-stream-multiple-data-stream
                 computer; scalar processors; three-dimensional
                 nearest-neighbor network",
  sponsororg =   "IEEE; ACM",
  treatment =    "P Practical",
}


bibtype: techreport
filename: fparith.bib
label: Tsao:1988:AST
author: Nai-kuan Tsao
title: On the accuracy of solving triangular systems in parallel
address: Washington, DC, USA
year: 1988
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
series: NASA technical memorandum; 101384 ICOMP; 88-19
keywords: Algorithms.; Error analysis.; Errors.; Floating point arithmetic.
acknowledgement: ack-nhfb
rawauthor: Nai-kuan Tsao
rawtitle: On the accuracy of solving triangular systems in parallel
institution:
National Aeronautics and Space Administration; For sale by the National Technical Information Service

remark:
Distributed to depository libraries in microfiche. Microfiche. [Washington, D.C.: National Aeronautics and Space Administration, 1989] 1 microfiche.

entry:
@TechReport{Tsao:1988:AST,
  author =       "Nai-kuan Tsao",
  title =        "On the accuracy of solving triangular systems in
                 parallel",
  institution =  "National Aeronautics and Space Administration; For
                 sale by the National Technical Information Service",
  address =      "Washington, DC, USA",
  pages =        "????",
  year =         "1988",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "NASA technical memorandum; 101384 ICOMP; 88-19",
  acknowledgement = ack-nhfb,
  govtdocnumber = "NAS 1.15:101384 0830-D (MF)",
  keywords =     "Algorithms.; Error analysis.; Errors.; Floating point
                 arithmetic.",
  remark =       "Distributed to depository libraries in microfiche.
                 Microfiche. [Washington, D.C.: National Aeronautics and
                 Space Administration, 1989] 1 microfiche.",
}


bibtype: article
filename: fparith.bib
label: Venkaiah:1988:CMS
author: V. Ch Venkaiah and S. K. Sen
title: Computing a matrix symmetrizer exactly using modified multiple modulus residue arithmetic
journal: j-J-COMPUT-APPL-MATH
volume: 21
number: 1
pages: 27--40
month: jan
monthnumber: 1
year: 1988
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 12:20:37 MST 2017
bibtimestamp: 2017.02.25 12:20:37 MST
URL: http://www.sciencedirect.com/science/article/pii/0377042788903858
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: V. Ch Venkaiah and S. K. Sen
rawtitle: Computing a matrix symmetrizer exactly using modified multiple modulus residue arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath1980.bib

entry:
@Article{Venkaiah:1988:CMS,
  author =       "V. Ch Venkaiah and S. K. Sen",
  title =        "Computing a matrix symmetrizer exactly using modified
                 multiple modulus residue arithmetic",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "21",
  number =       "1",
  pages =        "27--40",
  month =        jan,
  year =         "1988",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 12:20:37 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath1980.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/0377042788903858",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: article
filename: fparith.bib
label: Voelzke:1988:FSAa
author: H. Volzke
journal: j-MC
volume: 10
pages: 123--129
year: 1988
ISSN: 0720-4442, 0941-777x , 0943-5409 OR 07204442, 0941777x , 09435409
bibdate: Fri Sep 16 16:30:39 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:39 ???
fjournal: MC: Die Mikrocomputer-Zeitschrift
acknowledgement: ack-nj
rawauthor: H. V{\"o}lzke
title:
Fliess komma-Arithmetik und IEEE-Spezifikationen. Teil 1: Standards und Strukturen toenglish Floating-point Arithmetic and its IEEE Specification. Part 1: Standards and Structures endtoenglish 

rawtitle:
{Flie{\ss}komma-Arithmetik und IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 1: Standards und Strukturen} \toenglish {Floating-point Arithmetic and its IEEE Specification. Part 1: Standards and Structures} \endtoenglish

entry:
@Article{Voelzke:1988:FSAa,
  author =       "H. V{\"o}lzke",
  title =        "{Flie{\ss}komma-Arithmetik und
                 IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 1: Standards und
                 Strukturen} \toenglish {Floating-point Arithmetic and
                 its IEEE Specification. Part 1: Standards and
                 Structures} \endtoenglish",
  journal =      j-MC,
  volume =       "10",
  pages =        "123--129",
  year =         "1988",
  ISSN =         "0720-4442, 0941-777x , 0943-5409",
  bibdate =      "Fri Sep 16 16:30:39 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "MC: Die Mikrocomputer-Zeitschrift",
}


bibtype: article
filename: fparith.bib
label: Voelzke:1988:FSAb
author: H. Volzke
journal: j-MC
volume: 11
pages: 78--95
year: 1988
ISSN: 0720-4442, 0941-777x , 0943-5409 OR 07204442, 0941777x , 09435409
bibdate: Fri Sep 16 16:30:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:40 ???
fjournal: MC: Die Mikrocomputer-Zeitschrift
acknowledgement: ack-nj
rawauthor: H. V{\"o}lzke
title:
Fliess komma-Arithmetik und IEEE-Spezifikationen. Teil 2: Entwurf eines Fliess kommapakets toenglish Floating-point Arithmetic and its IEEE Specification. Part 2: Design of a Floating-Point Package endtoenglish 

rawtitle:
{Flie{\ss}komma-Arithmetik und IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 2: Entwurf eines Flie{\ss}kommapakets} \toenglish {Floating-point Arithmetic and its IEEE Specification. Part 2: Design of a Floating-Point Package} \endtoenglish

entry:
@Article{Voelzke:1988:FSAb,
  author =       "H. V{\"o}lzke",
  title =        "{Flie{\ss}komma-Arithmetik und
                 IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 2: Entwurf eines
                 Flie{\ss}kommapakets} \toenglish {Floating-point
                 Arithmetic and its IEEE Specification. Part 2: Design
                 of a Floating-Point Package} \endtoenglish",
  journal =      j-MC,
  volume =       "11",
  pages =        "78--95",
  year =         "1988",
  ISSN =         "0720-4442, 0941-777x , 0943-5409",
  bibdate =      "Fri Sep 16 16:30:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "MC: Die Mikrocomputer-Zeitschrift",
}


bibtype: article
filename: fparith.bib
label: Voelzke:1988:FSAc
author: H. Volzke
journal: j-MC
volume: 12
pages: 95--108
year: 1988
ISSN: 0720-4442, 0941-777x , 0943-5409 OR 07204442, 0941777x , 09435409
bibdate: Fri Sep 16 16:30:40 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:40 ???
fjournal: MC: Die Mikrocomputer-Zeitschrift
acknowledgement: ack-nj
rawauthor: H. V{\"o}lzke
title:
Fliess komma-Arithmetik und IEEE-Spezifikationen. Teil 3: Die verwendeten Algorithmen toenglish Floating-point Arithmetic and its IEEE Specification. Part 3: The Algorithms Used endtoenglish 

rawtitle:
{Flie{\ss}komma-Arithmetik und IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 3: Die verwendeten Algorithmen} \toenglish {Floating-point Arithmetic and its IEEE Specification. Part 3: The Algorithms Used} \endtoenglish

entry:
@Article{Voelzke:1988:FSAc,
  author =       "H. V{\"o}lzke",
  title =        "{Flie{\ss}komma-Arithmetik und
                 IEEE-Spez\-i\-fi\-ka\-tion\-en. Teil 3: Die verwendeten
                 Algorithmen} \toenglish {Floating-point Arithmetic and
                 its IEEE Specification. Part 3: The Algorithms Used}
                 \endtoenglish",
  journal =      j-MC,
  volume =       "12",
  pages =        "95--108",
  year =         "1988",
  ISSN =         "0720-4442, 0941-777x , 0943-5409",
  bibdate =      "Fri Sep 16 16:30:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "MC: Die Mikrocomputer-Zeitschrift",
}


bibtype: article
filename: fparith.bib
label: Weyland:1988:LCS
author: Nicholas J. Weyland and Edward A. Puckett
title: Lossless coding for sources of floating-point and fixed-precision numbers
journal: j-IEEE-TRANS-INF-THEORY
volume: 34
number: 4
pages: 882--888
month: jul
monthnumber: 7
year: 1988
CODEN: IETTAW
DOI: https://doi.org/10.1109/18.9791
ISSN: 0018-9448 (print), 1557-9654 (electronic) OR 00189448 (print), 15579654 (electronic)
ISSNL: 0018-9448 OR 00189448
MRclass: 94A29
MRnumber: 89i:94023
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Information Theory
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=18
rawauthor: Nicholas J. Weyland and Edward A. Puckett
rawtitle: Lossless coding for sources of floating-point and fixed-precision numbers
entry:
@Article{Weyland:1988:LCS,
  author =       "Nicholas J. Weyland and Edward A. Puckett",
  title =        "Lossless coding for sources of floating-point and
                 fixed-precision numbers",
  journal =      j-IEEE-TRANS-INF-THEORY,
  volume =       "34",
  number =       "4",
  pages =        "882--888",
  month =        jul,
  year =         "1988",
  CODEN =        "IETTAW",
  DOI =          "https://doi.org/10.1109/18.9791",
  ISSN =         "0018-9448 (print), 1557-9654 (electronic)",
  ISSN-L =       "0018-9448",
  MRclass =      "94A29",
  MRnumber =     "89i:94023",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Information Theory",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=18",
  summary =      "A procedure for constructing binary models for sources
                 of floating-point and fixed-precision numbers is given
                 and used together with the minimum description length
                 principle to find optimal models. These models are used
                 to design noiseless source code \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Wilson:1988:FPS
author: Pete Wilson
title: Floating-Point Survival Kit
journal: j-BYTE
volume: 13
number: 3
pages: 217--217
month: mar
monthnumber: 3
year: 1988
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Thu Oct 31 18:51:38 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.10.31 18:51:38 ???
fjournal: BYTE Magazine
acknowledgement: ack-nhfb
rawauthor: Pete Wilson
rawtitle: Floating-Point Survival Kit
entry:
@Article{Wilson:1988:FPS,
  author =       "Pete Wilson",
  title =        "Floating-Point Survival Kit",
  journal =      j-BYTE,
  volume =       "13",
  number =       "3",
  pages =        "217--217",
  month =        mar,
  year =         "1988",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Thu Oct 31 18:51:38 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "BYTE Magazine",
}


bibtype: article
filename: fparith.bib
label: Wilson:1988:NDP
author: Fred Wilson
title: A Note on Division of Positive Integers
journal: j-SIGMICRO
volume: 19
number: 1--2
pages: 4--4
month: jun
monthnumber: 6
year: 1988
CODEN: SIGMDJ
DOI: https://doi.org/10.1145/62197.1096672
ISSN: 0163-5751, 1050-916X OR 01635751, 1050916X
ISSNL: 0163-5751 OR 01635751
bibdate: Fri Apr 16 10:27:39 MDT 2021
bibtimestamp: 2021.04.16 10:27:39 MDT
URL: https://dl.acm.org/doi/10.1145/62197.1096672
fjournal: ACM SIGMICRO Newsletter
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/sigmicro
rawauthor: Fred Wilson
rawtitle: A Note on Division of Positive Integers
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigmicro.bib

abstract:
At the risk of flaunting a marginal grasp of the obvious I would like to make a few observations on the division of fixed point numbers.

rawabstract:
At the risk of flaunting a marginal grasp of the obvious I would like to make a few observations on the division of fixed point numbers.

entry:
@Article{Wilson:1988:NDP,
  author =       "Fred Wilson",
  title =        "A Note on Division of Positive Integers",
  journal =      j-SIGMICRO,
  volume =       "19",
  number =       "1--2",
  pages =        "4--4",
  month =        jun,
  year =         "1988",
  CODEN =        "SIGMDJ",
  DOI =          "https://doi.org/10.1145/62197.1096672",
  ISSN =         "0163-5751, 1050-916X",
  ISSN-L =       "0163-5751",
  bibdate =      "Fri Apr 16 10:27:39 MDT 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigmicro.bib",
  URL =          "https://dl.acm.org/doi/10.1145/62197.1096672",
  abstract =     "At the risk of flaunting a marginal grasp of the
                 obvious I would like to make a few observations on the
                 division of fixed point numbers.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGMICRO Newsletter",
  journal-URL =  "https://dl.acm.org/loi/sigmicro",
}


bibtype: article
filename: fparith.bib
label: Wilson:1988:NFP
author: R. Wilson
title: Newest floating-point processors blur architectural distinctions
journal: j-COMP-DESIGN
volume: 27
number: 8
pages: 32--43
day: 15
month: apr
monthnumber: 4
year: 1988
CODEN: CMPDAM
ISSN: 0010-4566 OR 00104566
bibdate: Sat Nov 9 08:26:18 MST 2002
bibsource: ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.09 08:26:18 MST
fjournal: Computer Design
acknowledgement: ack-nhfb
rawauthor: R. Wilson
rawtitle: Newest floating-point processors blur architectural distinctions
subject:
B. Hardware; B.7 INTEGRATED CIRCUITS; C. Computer Systems Organization; C.1 PROCESSOR ARCHITECTURES; C. Computer Systems Organization; C.1 PROCESSOR ARCHITECTURES

entry:
@Article{Wilson:1988:NFP,
  author =       "R. Wilson",
  title =        "Newest floating-point processors blur architectural
                 distinctions",
  journal =      j-COMP-DESIGN,
  volume =       "27",
  number =       "8",
  pages =        "32--43",
  day =          "15",
  month =        apr,
  year =         "1988",
  CODEN =        "CMPDAM",
  ISSN =         "0010-4566",
  bibdate =      "Sat Nov 9 08:26:18 MST 2002",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  bibno =        "44373",
  catcode =      "B.7.1; C.1.1; C.1.1",
  CRclass =      "B.7.1 Types and Design Styles; B.7.1 Memory
                 technologies; C.1.1 Single Data Stream Architectures;
                 C.1.1 RISC; C.1.1 Single Data Stream Architectures;
                 C.1.1 CISC",
  descriptor =   "Hardware, INTEGRATED CIRCUITS, Types and Design
                 Styles, Memory technologies; Computer Systems
                 Organization, PROCESSOR ARCHITECTURES, Single Data
                 Stream Architectures, RISC; Computer Systems
                 Organization, PROCESSOR ARCHITECTURES, Single Data
                 Stream Architectures, CISC",
  fjournal =     "Computer Design",
  genterm =      "PERFORMANCE; DESIGN",
  guideno =      "1988-05955",
  journalabbrev = "Comput. Des.",
  subject =      "B. Hardware; B.7 INTEGRATED CIRCUITS; C. Computer
                 Systems Organization; C.1 PROCESSOR ARCHITECTURES; C.
                 Computer Systems Organization; C.1 PROCESSOR
                 ARCHITECTURES",
}


bibtype: article
filename: fparith.bib
label: Wollard:1988:TSS
author: K. Wollard
title: Technology '88: Solid state
journal: j-IEEE-SPECTRUM
volume: 25
number: 1
pages: 44--46
month: jan
monthnumber: 1
year: 1988
CODEN: IEESAM
DOI: https://doi.org/10.1109/6.4483
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Mon Jan 20 06:41:24 2020
bibtimestamp: 2020.01.20 06:41:24 ???
fjournal: IEEE Spectrum
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: K. Wollard
rawtitle: Technology '88: Solid state
keywords:
16 Mbit; 4 Mbit; application-specific ICs; Consumer electronics; digital integrated circuits; Electronics industry; EPROM; floating-point digital signal processors; GaAs-Si; Government; high-density packaging; integrated circuit technology; Japan; Manufacturing industries; Microprocessors; Production; Semiconductor device manufacture; solid state; Solid state circuits; Trade agreements; US

entry:
@Article{Wollard:1988:TSS,
  author =       "K. Wollard",
  title =        "Technology '88: Solid state",
  journal =      j-IEEE-SPECTRUM,
  volume =       "25",
  number =       "1",
  pages =        "44--46",
  month =        jan,
  year =         "1988",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/6.4483",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Mon Jan 20 06:41:24 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeespectrum1980.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "16 Mbit; 4 Mbit; application-specific ICs; Consumer
                 electronics; digital integrated circuits; Electronics
                 industry; EPROM; floating-point digital signal
                 processors; GaAs-Si; Government; high-density
                 packaging; integrated circuit technology; Japan;
                 Manufacturing industries; Microprocessors; Production;
                 Semiconductor device manufacture; solid state; Solid
                 state circuits; Trade agreements; US",
}


bibtype: book
filename: fparith.bib
label: Young:1988:SNMa
author: David M. Young and Robert Todd Gregory
title: A Survey of Numerical Mathematics
volume: I
publisher: pub-DOVER
address: pub-DOVER:adr
pages: x + 492 + A22 + B16 + I18
year: 1988
ISBN: 0-486-65691-8 OR 0486656918
ISBN13: 978-0-486-65691-5 OR 9780486656915
LCCN: QA297.Y63 1972
MRclass: 65-02
MRnumber: 92b:65005b
bibdate: Wed Jan 17 10:30:33 1996
bibtimestamp: 1996.01.17 10:30:33 ???
note: Corrected reprint of the 1973 original.
URL: http://www.zentralblatt-math.org/zmath/en/search/?an=0732.65002
ZMnumber: 0732.65002
acknowledgement: ack-nhfb
rawauthor: David M. Young and Robert Todd Gregory
rawnote: Corrected reprint of the 1973 original.
rawtitle: A Survey of Numerical Mathematics
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/y/young-david-m.bib; https://www.math.utah.edu/pub/bibnet/subjects/matrix-analysis-2ed.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

TOC:
1: Numerical Analysis as a Subject Area 1.1 Introduction 1.2 Some pitfalls in computation 1.3 Mathematical and computer aspects of an algorithm 1.4 Numerical instability of algorithms and ill-conditioned problems 1.5 Typical problems of interest to the numerical analyst 1.6 Iterative methods 2: Elementary Operations with Automatic Digital Computers 2.1 Introduction 2.2 Binary arithmetic 2.3 Conversion from base $D$ to base $B$ representation 2.4 Representation of integers on a binary computer 2.5 Floating-point representations 2.6 Computer-representable numbers 2.7 Floating-point arithmetic operations 2.8 Fortran analysis of a floating-point number 2.9 Calculation of elementary functions 3: Surveillance of Number Ranges 3.1 Introduction 3.2 Allowable number ranges 3.3 Basic real arithmetic operations 3.4 The quadratic equation 3.5 Complex arithmetic operations 4: Solution of Equations 4.1 Introduction 4.2 Attainable accuracy 4.3 Graphical methods 4.4 The method of bisection 4.5 The method of false position 4.6 The secant method 4.7 General properties of iterative methods 4.8 Generation of iterative methods 4.9 The Newton method 4.10 Muller's method 4.11 Orders of convergence of iterative methods 4.12 Acceleration of the convergence 4.13 Systems of nonlinear equations 5: Roots of Polynomial Equations 5.1 Introduction 5.2 General properties of polynomials 5.3 The Newton method and related methods 5.4 Muller's method and Cauchy's method 5.5 Location of the roots 5.6 Root acceptance and refinement 5.7 Matrix related methods: the modified Bernoulli method 5.8 Matrix related methods: the IP method 5.9 Polyalgorithms 5.10 Other methods 6: Interpolation and Approximation 6.1 Introduction 6.2 Linear interpolation 6.3 Convergence and accuracy of linear interpolation 6.4 Lagrangian interpolation 6.5 Convergence and accuracy of Lagrangian interpolation 6.6 Interpolation with equal intervals 6.7 Hermite interpolation 6.8 Limitations on polynomial interpolation: smooth interpolation 6.9 Inverse interpolation 6.10 Approximation by polynomials 6.11 Least squares approximation by polynomials 6.12 Rational approximation 6.13 Trigonometric interpolation and approximation 6.14 Interpolation in two variables 7: Numerical Differentiation and Quadrature 7.1 Introduction 7.2 The method of undetermined weights 7.3 Numerical differentiation 7.4 Numerical quadrature --- equal intervals 7.5 The Euler--MacLaurin formula 7.6 Romberg integration 7.7 Error determination 7.8 Numerical quadrature --- unequal intervals 8: Ordinary Differential Equations 8.1 Introduction 8.2 Existence and uniqueness 8.3 Analytic methods 8.4 Integral equation formulation --- the Picard method of successive approximations 8.5 The Euler method 8.6 Methods based on numerical quadrature 8.7 Error estimation for predictor-corrector methods 8.8 A numerical example 8.9 Runge--Kutta methods 8.10 Methods based on numerical differentiation 8.11 Higher-order equations and systems of first-order equations 8.12 The use of high-speed computers Appendix A Appendix B Appendix C Bibliography Index

rawTOC:
1: Numerical Analysis as a Subject Area \\ 1.1 Introduction \\ 1.2 Some pitfalls in computation \\ 1.3 Mathematical and computer aspects of an algorithm \\ 1.4 Numerical instability of algorithms and ill-conditioned problems \\ 1.5 Typical problems of interest to the numerical analyst \\ 1.6 Iterative methods \\ 2: Elementary Operations with Automatic Digital Computers \\ 2.1 Introduction \\ 2.2 Binary arithmetic \\ 2.3 Conversion from base $D$ to base $B$ representation \\ 2.4 Representation of integers on a binary computer \\ 2.5 Floating-point representations \\ 2.6 Computer-representable numbers \\ 2.7 Floating-point arithmetic operations \\ 2.8 Fortran analysis of a floating-point number \\ 2.9 Calculation of elementary functions \\ 3: Surveillance of Number Ranges \\ 3.1 Introduction \\ 3.2 Allowable number ranges \\ 3.3 Basic real arithmetic operations \\ 3.4 The quadratic equation \\ 3.5 Complex arithmetic operations \\ 4: Solution of Equations \\ 4.1 Introduction \\ 4.2 Attainable accuracy \\ 4.3 Graphical methods \\ 4.4 The method of bisection \\ 4.5 The method of false position \\ 4.6 The secant method \\ 4.7 General properties of iterative methods \\ 4.8 Generation of iterative methods \\ 4.9 The Newton method \\ 4.10 Muller's method \\ 4.11 Orders of convergence of iterative methods \\ 4.12 Acceleration of the convergence \\ 4.13 Systems of nonlinear equations \\ 5: Roots of Polynomial Equations \\ 5.1 Introduction \\ 5.2 General properties of polynomials \\ 5.3 The Newton method and related methods \\ 5.4 Muller's method and Cauchy's method \\ 5.5 Location of the roots \\ 5.6 Root acceptance and refinement \\ 5.7 Matrix related methods: the modified Bernoulli method \\ 5.8 Matrix related methods: the IP method \\ 5.9 Polyalgorithms \\ 5.10 Other methods \\ 6: Interpolation and Approximation \\ 6.1 Introduction \\ 6.2 Linear interpolation \\ 6.3 Convergence and accuracy of linear interpolation \\ 6.4 Lagrangian interpolation \\ 6.5 Convergence and accuracy of Lagrangian interpolation \\ 6.6 Interpolation with equal intervals \\ 6.7 Hermite interpolation \\ 6.8 Limitations on polynomial interpolation: smooth interpolation \\ 6.9 Inverse interpolation \\ 6.10 Approximation by polynomials \\ 6.11 Least squares approximation by polynomials \\ 6.12 Rational approximation \\ 6.13 Trigonometric interpolation and approximation \\ 6.14 Interpolation in two variables \\ 7: Numerical Differentiation and Quadrature \\ 7.1 Introduction \\ 7.2 The method of undetermined weights \\ 7.3 Numerical differentiation \\ 7.4 Numerical quadrature --- equal intervals \\ 7.5 The Euler--MacLaurin formula \\ 7.6 Romberg integration \\ 7.7 Error determination \\ 7.8 Numerical quadrature --- unequal intervals \\ 8: Ordinary Differential Equations \\ 8.1 Introduction \\ 8.2 Existence and uniqueness \\ 8.3 Analytic methods \\ 8.4 Integral equation formulation --- the Picard method of successive approximations \\ 8.5 The Euler method \\ 8.6 Methods based on numerical quadrature \\ 8.7 Error estimation for predictor-corrector methods \\ 8.8 A numerical example \\ 8.9 Runge--Kutta methods \\ 8.10 Methods based on numerical differentiation \\ 8.11 Higher-order equations and systems of first-order equations \\ 8.12 The use of high-speed computers \\ Appendix A \\ Appendix B \\ Appendix C \\ Bibliography \\ Index

entry:
@Book{Young:1988:SNMa,
  author =       "David M. Young and Robert Todd Gregory",
  title =        "A Survey of Numerical Mathematics",
  volume =       "I",
  publisher =    pub-DOVER,
  address =      pub-DOVER:adr,
  pages =        "x + 492 + A22 + B16 + I18",
  year =         "1988",
  ISBN =         "0-486-65691-8",
  ISBN-13 =      "978-0-486-65691-5",
  LCCN =         "QA297.Y63 1972",
  MRclass =      "65-02",
  MRnumber =     "92b:65005b",
  bibdate =      "Wed Jan 17 10:30:33 1996",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/y/young-david-m.bib;
                 https://www.math.utah.edu/pub/bibnet/subjects/matrix-analysis-2ed.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Corrected reprint of the 1973 original.",
  URL =          "http://www.zentralblatt-math.org/zmath/en/search/?an=0732.65002",
  ZMnumber =     "0732.65002",
  acknowledgement = ack-nhfb,
  tableofcontents = "1: Numerical Analysis as a Subject Area \\
                 1.1 Introduction \\
                 1.2 Some pitfalls in computation \\
                 1.3 Mathematical and computer aspects of an algorithm
                 \\
                 1.4 Numerical instability of algorithms and
                 ill-conditioned problems \\
                 1.5 Typical problems of interest to the numerical
                 analyst \\
                 1.6 Iterative methods \\
                 2: Elementary Operations with Automatic Digital
                 Computers \\
                 2.1 Introduction \\
                 2.2 Binary arithmetic \\
                 2.3 Conversion from base $D$ to base $B$ representation
                 \\
                 2.4 Representation of integers on a binary computer \\
                 2.5 Floating-point representations \\
                 2.6 Computer-representable numbers \\
                 2.7 Floating-point arithmetic operations \\
                 2.8 Fortran analysis of a floating-point number \\
                 2.9 Calculation of elementary functions \\
                 3: Surveillance of Number Ranges \\
                 3.1 Introduction \\
                 3.2 Allowable number ranges \\
                 3.3 Basic real arithmetic operations \\
                 3.4 The quadratic equation \\
                 3.5 Complex arithmetic operations \\
                 4: Solution of Equations \\
                 4.1 Introduction \\
                 4.2 Attainable accuracy \\
                 4.3 Graphical methods \\
                 4.4 The method of bisection \\
                 4.5 The method of false position \\
                 4.6 The secant method \\
                 4.7 General properties of iterative methods \\
                 4.8 Generation of iterative methods \\
                 4.9 The Newton method \\
                 4.10 Muller's method \\
                 4.11 Orders of convergence of iterative methods \\
                 4.12 Acceleration of the convergence \\
                 4.13 Systems of nonlinear equations \\
                 5: Roots of Polynomial Equations \\
                 5.1 Introduction \\
                 5.2 General properties of polynomials \\
                 5.3 The Newton method and related methods \\
                 5.4 Muller's method and Cauchy's method \\
                 5.5 Location of the roots \\
                 5.6 Root acceptance and refinement \\
                 5.7 Matrix related methods: the modified Bernoulli
                 method \\
                 5.8 Matrix related methods: the IP method \\
                 5.9 Polyalgorithms \\
                 5.10 Other methods \\
                 6: Interpolation and Approximation \\
                 6.1 Introduction \\
                 6.2 Linear interpolation \\
                 6.3 Convergence and accuracy of linear interpolation
                 \\
                 6.4 Lagrangian interpolation \\
                 6.5 Convergence and accuracy of Lagrangian
                 interpolation \\
                 6.6 Interpolation with equal intervals \\
                 6.7 Hermite interpolation \\
                 6.8 Limitations on polynomial interpolation: smooth
                 interpolation \\
                 6.9 Inverse interpolation \\
                 6.10 Approximation by polynomials \\
                 6.11 Least squares approximation by polynomials \\
                 6.12 Rational approximation \\
                 6.13 Trigonometric interpolation and approximation \\
                 6.14 Interpolation in two variables \\
                 7: Numerical Differentiation and Quadrature \\
                 7.1 Introduction \\
                 7.2 The method of undetermined weights \\
                 7.3 Numerical differentiation \\
                 7.4 Numerical quadrature --- equal intervals \\
                 7.5 The Euler--MacLaurin formula \\
                 7.6 Romberg integration \\
                 7.7 Error determination \\
                 7.8 Numerical quadrature --- unequal intervals \\
                 8: Ordinary Differential Equations \\
                 8.1 Introduction \\
                 8.2 Existence and uniqueness \\
                 8.3 Analytic methods \\
                 8.4 Integral equation formulation --- the Picard method
                 of successive approximations \\
                 8.5 The Euler method \\
                 8.6 Methods based on numerical quadrature \\
                 8.7 Error estimation for predictor-corrector methods
                 \\
                 8.8 A numerical example \\
                 8.9 Runge--Kutta methods \\
                 8.10 Methods based on numerical differentiation \\
                 8.11 Higher-order equations and systems of first-order
                 equations \\
                 8.12 The use of high-speed computers \\
                 Appendix A \\
                 Appendix B \\
                 Appendix C \\
                 Bibliography \\
                 Index",
}


bibtype: inproceedings
filename: fparith.bib
label: Yuen:1988:IFP
author: A. K. Yuen
title: Intel's floating-point processors
crossref: Electro:1988:ECR
pages: 48/5/1--7
year: 1988
bibdate: Wed Sep 7 22:32:00 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:00 ???
acknowledgement: ack-nj
rawauthor: A. K. Yuen
rawtitle: {Intel}'s floating-point processors
entry:
@InProceedings{Yuen:1988:IFP,
  author =       "A. K. Yuen",
  title =        "{Intel}'s floating-point processors",
  crossref =     "Electro:1988:ECR",
  pages =        "48/5/1--7",
  year =         "1988",
  bibdate =      "Wed Sep 7 22:32:00 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Zhou:1988:NBS
author: B. B. Zhou
title: A new bit-serial systolic multiplier over $ mathrm GF(2^m) $
journal: j-IEEE-TRANS-COMPUT
volume: 37
number: 6
pages: 749--751
month: jun
monthnumber: 6
year: 1988
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.2216
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Jul 9 08:33:27 MDT 2011
bibtimestamp: 2011.07.09 08:33:27 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=2216
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: B. B. Zhou
rawtitle: A new bit-serial systolic multiplier over {$ \mathrm {GF}(2^m) $}
entry:
@Article{Zhou:1988:NBS,
  author =       "B. B. Zhou",
  title =        "A new bit-serial systolic multiplier over {$ \mathrm
                 {GF}(2^m) $}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "37",
  number =       "6",
  pages =        "749--751",
  month =        jun,
  year =         "1988",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.2216",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Jul 9 08:33:27 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=2216",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Zoicas:1988:PBG
author: A. Zoicas and K. Grohe and C. Kellerhoff
crossref: Lacoume:1988:SPI
pages: 1233--1236 vol.3
year: 1988
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
note: 3 vol.
acknowledgement: ack-nhfb
affiliation: NEC Electron. GmbH, Dusseldorf, West Germany
rawauthor: A. Zoicas and K. Grohe and C. Kellerhoff
rawnote: 3 vol.
title:
PC based general-purpose floating-point DSP $ mu $PD77230 board with various analog front end options and application software packages

abstract:
The EBIBM-77230 FFT is a software and hardware DSP engineering environment incorporated in a PC in the form of a plug-in board. It offers no downgrade from the ideal in terms of its processing power, which amounts of 27 MFLOPs, its open architecture, standard cross-software support and interfaces to popular commercial DSP packages. A variety of analog front-end options and supervisor modules (for stand-alone operation) can be hooked onto the board itself thereby opening its application to most DSP areas. A math library, which features interfaces to most high level languages (C, Fortran, Pascal, Basic), brings workstation computational power to the PC. The EBIBM-77230 FFT bridges the gap between fast high precision number crunching and an accessible user-friendly environment. The turn-around time from an idea to its real-time execution is thus minimised and cost-wise it is an economic solution in relation to most DSP working environments.

keywords:
27 MFLOPS; Analog front end; Application software packages; Basic; C; DSP engineering environment; EBIBM-77230 FFT; Fortran; General purpose floating point DSP; High level languages; Interfaces; Math library; Microprocessor D77230 board; Open architecture; Pascal; PC; Personal computer; Plug-in board; Supervisor modules

thesaurus:
Add-on boards; Computerised signal processing; Microcomputer applications; Microprocessor chips; Software packages

rawabstract:
The EBIBM-77230 FFT is a software and hardware DSP engineering environment incorporated in a PC in the form of a plug-in board. It offers no downgrade from the ideal in terms of its processing power, which amounts of 27 MFLOPs, its open architecture, standard cross-software support and interfaces to popular commercial DSP packages. A variety of analog front-end options and supervisor modules (for stand-alone operation) can be hooked onto the board itself thereby opening its application to most DSP areas. A math library, which features interfaces to most high level languages (C, Fortran, Pascal, Basic), brings workstation computational power to the PC. The EBIBM-77230 FFT bridges the gap between fast high precision number crunching and an accessible user-friendly environment. The turn-around time from an idea to its real-time execution is thus minimised and cost-wise it is an economic solution in relation to most DSP working environments.

rawtitle:
{PC} based general-purpose floating-point {DSP $ \mu $PD77230} board with various analog front end options and application software packages

entry:
@InProceedings{Zoicas:1988:PBG,
  author =       "A. Zoicas and K. Grohe and C. Kellerhoff",
  title =        "{PC} based general-purpose floating-point {DSP $ \mu
                 $PD77230} board with various analog front end options
                 and application software packages",
  crossref =     "Lacoume:1988:SPI",
  pages =        "1233--1236 vol.3",
  year =         "1988",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "3 vol.",
  abstract =     "The EBIBM-77230 FFT is a software and hardware DSP
                 engineering environment incorporated in a PC in the
                 form of a plug-in board. It offers no downgrade from
                 the ideal in terms of its processing power, which
                 amounts of 27 MFLOPs, its open architecture, standard
                 cross-software support and interfaces to popular
                 commercial DSP packages. A variety of analog front-end
                 options and supervisor modules (for stand-alone
                 operation) can be hooked onto the board itself thereby
                 opening its application to most DSP areas. A math
                 library, which features interfaces to most high level
                 languages (C, Fortran, Pascal, Basic), brings
                 workstation computational power to the PC. The
                 EBIBM-77230 FFT bridges the gap between fast high
                 precision number crunching and an accessible
                 user-friendly environment. The turn-around time from an
                 idea to its real-time execution is thus minimised and
                 cost-wise it is an economic solution in relation to
                 most DSP working environments.",
  acknowledgement = ack-nhfb,
  affiliation =  "NEC Electron. GmbH, Dusseldorf, West Germany",
  classification = "B1265F (Microprocessors and microcomputers); B6140
                 (Signal processing and detection); C5130
                 (Microprocessor chips); C5150 (Other circuits for
                 digital computers); C7410F (Communications)",
  keywords =     "27 MFLOPS; Analog front end; Application software
                 packages; Basic; C; DSP engineering environment;
                 EBIBM-77230 FFT; Fortran; General purpose floating
                 point DSP; High level languages; Interfaces; Math
                 library; Microprocessor D77230 board; Open
                 architecture; Pascal; PC; Personal computer; Plug-in
                 board; Supervisor modules",
  numericalindex = "Computer speed 2.7E+07 FLOPS",
  thesaurus =    "Add-on boards; Computerised signal processing;
                 Microcomputer applications; Microprocessor chips;
                 Software packages",
}


bibtype: inproceedings
filename: fparith.bib
label: Ahmed:1989:EEF
author: H. M. Ahmed
title: Efficient Elementary Function Generation with Multipliers
crossref: Ercegovac:1989:PSC
pages: 52--59
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Ahmed.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: H. M. Ahmed
rawtitle: Efficient Elementary Function Generation with Multipliers
entry:
@InProceedings{Ahmed:1989:EEF,
  author =       "H. M. Ahmed",
  title =        "Efficient Elementary Function Generation with
                 Multipliers",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "52--59",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Ahmed.pdf",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Amit:1989:MRE
author: G. Amit and U. Shaked
title: Minimization of roundoff errors in digital realizations of Kalman filters
journal: j-IEEE-TRANS-ACOUST-SPEECH
volume: 37
number: 12
pages: 1980--1982
month: dec
monthnumber: 12
year: 1989
CODEN: IETABA
ISSN: 0096-3518 OR 00963518
bibdate: Sat Jul 16 11:25:06 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:06 MDT
fjournal: IEEE Transactions on Acoustics, Speech, and Signal Processing
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=29
rawauthor: G. Amit and U. Shaked
rawtitle: Minimization of roundoff errors in digital realizations of {Kalman} filters
entry:
@Article{Amit:1989:MRE,
  author =       "G. Amit and U. Shaked",
  title =        "Minimization of roundoff errors in digital
                 realizations of {Kalman} filters",
  journal =      j-IEEE-TRANS-ACOUST-SPEECH,
  volume =       "37",
  number =       "12",
  pages =        "1980--1982",
  month =        dec,
  year =         "1989",
  CODEN =        "IETABA",
  ISSN =         "0096-3518",
  bibdate =      "Sat Jul 16 11:25:06 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Acoustics, Speech, and Signal
                 Processing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=29",
  summary =      "A comparison between D. Williamson's method (IEEE
                 Trans. Autom. Contr., vol.AC-30, p.930-9, 1985) and the
                 0-1 method for the design of the digital Kalman filter
                 is made. The 0-1 method is shown to be much better than
                 Williamson's method and the \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Arison:1989:SAN
author: D. Arison and A. Genusov and L. Gerzberg
title: System applications of a new 32-bit floating-point DSP processor
crossref: Chen:1989:TSA
pages: 890--897 vol.2
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Zoran Corp., Santa Clara, CA, USA
thesaurus: Computerised signal processing; Digital signal processing chips; Parallel processing
rawauthor: D. Arison and A. Genusov and L. Gerzberg
rawtitle: System applications of a new 32-bit floating-point {DSP} processor
abstract:
The authors present the ZR34325, a novel floating-point vector signal processor in the context of system applications. The ZR34325 represents the first full IEEE floating-point integrated array processor on silicon, supplemented with the pertinent scalar and control flow capabilities. The ZR34325 directly executes embedded DSP (digital signal processing) and array processing primitives on multidimensional arrays. Furthermore, an integrated development environment which includes a system software simulation, vectorized and parametric DSP, arithmetic and matrix library, C-based assembler/linker, and hardware development tools facilities top-down complete application development. The ZR34325 enables very efficient multiprocessor multitasking schemes for tasks where execution time is either data independent or data dependent. The authors show the top-down integrated design methodology via sample signal/image processing application examples such as Kalman filtering, spectral analysis, and constant false alarm rate processing for radar applications as well as two-dimensional image filtering.

keywords:
32 Bit; Arithmetic library; C-based assembler/linker; Digital signal processing; False alarm rate processing; Floating-point DSP processor; Image filtering; Kalman filtering; Matrix library; Multidimensional arrays; Radar; Spectral analysis; Vector signal processor; ZR34325

rawabstract:
The authors present the ZR34325, a novel floating-point vector signal processor in the context of system applications. The ZR34325 represents the first full IEEE floating-point integrated array processor on silicon, supplemented with the pertinent scalar and control flow capabilities. The ZR34325 directly executes embedded DSP (digital signal processing) and array processing primitives on multidimensional arrays. Furthermore, an integrated development environment which includes a system software simulation, vectorized and parametric DSP, arithmetic and matrix library, C-based assembler/linker, and hardware development tools facilities top-down complete application development. The ZR34325 enables very efficient multiprocessor multitasking schemes for tasks where execution time is either data independent or data dependent. The authors show the top-down integrated design methodology via sample signal/image processing application examples such as Kalman filtering, spectral analysis, and constant false alarm rate processing for radar applications as well as two-dimensional image filtering.

entry:
@InProceedings{Arison:1989:SAN,
  author =       "D. Arison and A. Genusov and L. Gerzberg",
  title =        "System applications of a new 32-bit floating-point
                 {DSP} processor",
  crossref =     "Chen:1989:TSA",
  pages =        "890--897 vol.2",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The authors present the ZR34325, a novel
                 floating-point vector signal processor in the context
                 of system applications. The ZR34325 represents the
                 first full IEEE floating-point integrated array
                 processor on silicon, supplemented with the pertinent
                 scalar and control flow capabilities. The ZR34325
                 directly executes embedded DSP (digital signal
                 processing) and array processing primitives on
                 multidimensional arrays. Furthermore, an integrated
                 development environment which includes a system
                 software simulation, vectorized and parametric DSP,
                 arithmetic and matrix library, C-based
                 assembler/linker, and hardware development tools
                 facilities top-down complete application development.
                 The ZR34325 enables very efficient multiprocessor
                 multitasking schemes for tasks where execution time is
                 either data independent or data dependent. The authors
                 show the top-down integrated design methodology via
                 sample signal/image processing application examples
                 such as Kalman filtering, spectral analysis, and
                 constant false alarm rate processing for radar
                 applications as well as two-dimensional image
                 filtering.",
  acknowledgement = ack-nhfb,
  affiliation =  "Zoran Corp., Santa Clara, CA, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5260 (Digital signal
                 processing)",
  keywords =     "32 Bit; Arithmetic library; C-based assembler/linker;
                 Digital signal processing; False alarm rate processing;
                 Floating-point DSP processor; Image filtering; Kalman
                 filtering; Matrix library; Multidimensional arrays;
                 Radar; Spectral analysis; Vector signal processor;
                 ZR34325",
  numericalindex = "Word length 3.2E+01 bit",
  thesaurus =    "Computerised signal processing; Digital signal
                 processing chips; Parallel processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Arnold:1989:RLN
author: M. G. Arnold and T. A. Bailey and J. R. Cowles and J. J. Cupal
title: Redundant logarithmic number systems
crossref: Ercegovac:1989:PSC
pages: 144--151
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Arnold.pdf
acknowledgement: ack-nhfb
affiliation: Wyoming University, Laramie, WY, USA
thesaurus: Digital arithmetic; Table lookup
rawauthor: M. G. Arnold and T. A. Bailey and J. R. Cowles and J. J. Cupal
rawtitle: Redundant logarithmic number systems
abstract:
A new number system that offers advantages over conventional floating-point and sign/logarithm number systems is described. Called redundant logarithmic arithmetic, it relies, like conventional logarithmic arithmetic, on table lookups to make the arithmetic unit simpler than an equivalent floating-point unit. The cost of 32-b subtraction in a redundant logarithmic number system is lower than that of previously published logarithmic subtraction methods. Another advantage of a redundant logarithmic number system is that a single arithmetic unit can use the same hardware to add, subtract, or multiply in similar times. (25 Refs.)

keywords:
Add; ARITH-9; Floating-point; Multiply; Number system; Redundant logarithmic arithmetic; Sign/logarithm number systems; Subtract; Table lookups

rawabstract:
A new number system that offers advantages over conventional floating-point and sign/logarithm number systems is described. Called redundant logarithmic arithmetic, it relies, like conventional logarithmic arithmetic, on table lookups to make the arithmetic unit simpler than an equivalent floating-point unit. The cost of 32-b subtraction in a redundant logarithmic number system is lower than that of previously published logarithmic subtraction methods. Another advantage of a redundant logarithmic number system is that a single arithmetic unit can use the same hardware to add, subtract, or multiply in similar times. (25 Refs.)

entry:
@InProceedings{Arnold:1989:RLN,
  author =       "M. G. Arnold and T. A. Bailey and J. R. Cowles and J.
                 J. Cupal",
  title =        "Redundant logarithmic number systems",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "144--151",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Arnold.pdf",
  abstract =     "A new number system that offers advantages over
                 conventional floating-point and sign/logarithm number
                 systems is described. Called redundant logarithmic
                 arithmetic, it relies, like conventional logarithmic
                 arithmetic, on table lookups to make the arithmetic
                 unit simpler than an equivalent floating-point unit.
                 The cost of 32-b subtraction in a redundant logarithmic
                 number system is lower than that of previously
                 published logarithmic subtraction methods. Another
                 advantage of a redundant logarithmic number system is
                 that a single arithmetic unit can use the same hardware
                 to add, subtract, or multiply in similar times. (25
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Wyoming University, Laramie, WY, USA",
  classification = "C5230 (Digital arithmetic methods)",
  keywords =     "Add; ARITH-9; Floating-point; Multiply; Number system;
                 Redundant logarithmic arithmetic; Sign/logarithm number
                 systems; Subtract; Table lookups",
  thesaurus =    "Digital arithmetic; Table lookup",
}


bibtype: article
filename: fparith.bib
label: Ashton:1989:AFP
author: C. Ashton
title: The Am29C327 floating point processor
journal: Electronic Product Design
volume: 10
number: 3
pages: 51--59
month: mar
monthnumber: 3
year: 1989
bibdate: Wed Sep 7 22:32:01 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:01 ???
acknowledgement: ack-nj
rawauthor: C. Ashton
rawtitle: The {Am29C327} floating point processor
entry:
@Article{Ashton:1989:AFP,
  author =       "C. Ashton",
  title =        "The {Am29C327} floating point processor",
  journal =      "Electronic Product Design",
  volume =       "10",
  number =       "3",
  pages =        "51--59",
  month =        mar,
  year =         "1989",
  bibdate =      "Wed Sep 7 22:32:01 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: inproceedings
filename: fparith.bib
label: Azmi:1989:TFP
author: A. M. Azmi and F. Lombardi
title: On a tapered floating point system
crossref: Ercegovac:1989:PSC
pages: 2--9
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Azmi.pdf
keywords: ARITH-9; Error analysis; Exponents; Tapered floating point system
acknowledgement: ack-nhfb
affiliation: Department of Electr. and Comput. Eng., Colorado University, Boulder, CO, USA
thesaurus: Digital arithmetic
rawauthor: A. M. Azmi and F. Lombardi
rawtitle: On a tapered floating point system
abstract:
R. Morris (see IEEE Trans. Comput., vol. TC-20, p. 1578--1579, 1971), suggested adding an extra field to the fixed floating point system, so that exponents can be stored more efficiently. The exponents are stored in the smallest possible space, passing the extra bits to the mantissa. The extra field is used to monitor the current length of the exponent. The gain in precision and/or exponent range outweighs the overhead of the extra field and the processing speed. The authors provide implementation details, error analysis, and some future research ideas. Simulation results are provided for comparison purposes.

rawabstract:
R. Morris (see IEEE Trans. Comput., vol. TC-20, p. 1578--1579, 1971), suggested adding an extra field to the fixed floating point system, so that exponents can be stored more efficiently. The exponents are stored in the smallest possible space, passing the extra bits to the mantissa. The extra field is used to monitor the current length of the exponent. The gain in precision and/or exponent range outweighs the overhead of the extra field and the processing speed. The authors provide implementation details, error analysis, and some future research ideas. Simulation results are provided for comparison purposes.

entry:
@InProceedings{Azmi:1989:TFP,
  author =       "A. M. Azmi and F. Lombardi",
  title =        "On a tapered floating point system",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "2--9",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Azmi.pdf",
  abstract =     "R. Morris (see IEEE Trans. Comput., vol. TC-20, p.
                 1578--1579, 1971), suggested adding an extra field to
                 the fixed floating point system, so that exponents can
                 be stored more efficiently. The exponents are stored in
                 the smallest possible space, passing the extra bits to
                 the mantissa. The extra field is used to monitor the
                 current length of the exponent. The gain in precision
                 and/or exponent range outweighs the overhead of the
                 extra field and the processing speed. The authors
                 provide implementation details, error analysis, and
                 some future research ideas. Simulation results are
                 provided for comparison purposes.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. and Comput. Eng., Colorado
                 University, Boulder, CO, USA",
  classification = "C5230 (Digital arithmetic methods)",
  keywords =     "ARITH-9; Error analysis; Exponents; Tapered floating
                 point system",
  thesaurus =    "Digital arithmetic",
}


bibtype: article
filename: fparith.bib
label: Bailey:1989:FPA
author: D. H. Bailey and H. D. Simon and J. T. Barton
title: Floating Point Arithmetic in Future Supercomputers
journal: j-IJSA
volume: 3
number: 3
pages: 86--90
month: Fall
year: 1989
CODEN: IJSAE9
ISSN: 0890-2720 OR 08902720
bibdate: Thu Aug 22 17:56:36 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; UnCover library database
bibtimestamp: 1996.08.22 17:56:36 MDT
fjournal: International Journal of Supercomputer Applications
acknowledgement: ack-nhfb
journalURL: http://hpc.sagepub.com/content/by/year
rawauthor: D. H. Bailey and H. D. Simon and J. T. Barton
rawtitle: Floating Point Arithmetic in Future Supercomputers
entry:
@Article{Bailey:1989:FPA,
  author =       "D. H. Bailey and H. D. Simon and J. T. Barton",
  title =        "Floating Point Arithmetic in Future Supercomputers",
  journal =      j-IJSA,
  volume =       "3",
  number =       "3",
  pages =        "86--90",
  month =        "Fall",
  year =         "1989",
  CODEN =        "IJSAE9",
  ISSN =         "0890-2720",
  bibdate =      "Thu Aug 22 17:56:36 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 UnCover library database",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of Supercomputer Applications",
  journal-URL =  "http://hpc.sagepub.com/content/by/year",
}


bibtype: article
filename: fparith.bib
label: Baran:1989:MST
author: N. Baran
title: The Mac SE takes off
journal: j-BYTE
volume: 14
number: 2
pages: 113--116
month: feb
monthnumber: 2
year: 1989
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Thu Sep 12 17:54:09 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.09.12 17:54:09 MDT
fjournal: BYTE Magazine
acknowledgement: ack-nhfb
thesaurus: Apple computers; Microcomputers
rawauthor: N. Baran
rawtitle: The {Mac SE} takes off
keywords:
16 MHz; 2 MBytes; 4 MBytes; 68030 CPU; 68882 Floating-point unit; Apple Macintosh SE/30; Built-in memory management unit; FPU; Logic board; Mac SE/30; MMU; Motorola 68030 processor; SIMM-mounted ROMs; Single in-line memory module RAM chips

entry:
@Article{Baran:1989:MST,
  author =       "N. Baran",
  title =        "The {Mac SE} takes off",
  journal =      j-BYTE,
  volume =       "14",
  number =       "2",
  pages =        "113--116",
  month =        feb,
  year =         "1989",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Thu Sep 12 17:54:09 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "C5430 (Microcomputers)",
  fjournal =     "BYTE Magazine",
  keywords =     "16 MHz; 2 MBytes; 4 MBytes; 68030 CPU; 68882
                 Floating-point unit; Apple Macintosh SE/30; Built-in
                 memory management unit; FPU; Logic board; Mac SE/30;
                 MMU; Motorola 68030 processor; SIMM-mounted ROMs;
                 Single in-line memory module RAM chips",
  numericalindex = "Frequency 1.6E+07 Hz; Memory size 2.1E+06 Byte;
                 Memory size 4.2E+06 Byte",
  thesaurus =    "Apple computers; Microcomputers",
}


bibtype: article
filename: fparith.bib
label: Bardin:1989:IUI
author: B. Bardin and C. Colket and D. Smith
title: Implementation of unsigned integers in Ada
journal: j-SIGADA-LETTERS
volume: 9
number: 1
pages: 47--70
month: jan
monthnumber: 1
year: 1989
CODEN: AALEE5
ISSN: 1094-3641 (print), 1557-9476 (electronic) OR 10943641 (print), 15579476 (electronic)
ISSNL: 1094-3641 OR 10943641
bibdate: Thu Mar 20 07:41:09 MST 1997
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigada.bib
bibtimestamp: 1997.03.20 07:41:09 MST
fjournal: ACM SIGAda Ada Letters
acknowledgement: ack-nhfb
classcodes: C6140D (High level languages); C6130 (Data handling techniques)
journalURL: http://portal.acm.org/citation.cfm?id=J32
treatment: P Practical
rawauthor: B. Bardin and C. Colket and D. Smith
rawtitle: Implementation of unsigned integers in {Ada}
keywords:
Ada; address arithmetic; digital arithmetic; full range; logical operations; modular arithmetic; numeric literals; symbol manipulation; unsigned integers

entry:
@Article{Bardin:1989:IUI,
  author =       "B. Bardin and C. Colket and D. Smith",
  title =        "Implementation of unsigned integers in {Ada}",
  journal =      j-SIGADA-LETTERS,
  volume =       "9",
  number =       "1",
  pages =        "47--70",
  month =        jan # "\slash " # feb,
  year =         "1989",
  CODEN =        "AALEE5",
  ISSN =         "1094-3641 (print), 1557-9476 (electronic)",
  ISSN-L =       "1094-3641",
  bibdate =      "Thu Mar 20 07:41:09 MST 1997",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigada.bib",
  acknowledgement = ack-nhfb,
  classcodes =   "C6140D (High level languages); C6130 (Data handling
                 techniques)",
  fjournal =     "ACM SIGAda Ada Letters",
  journal-URL =  "http://portal.acm.org/citation.cfm?id=J32",
  keywords =     "Ada; address arithmetic; digital arithmetic; full
                 range; logical operations; modular arithmetic; numeric
                 literals; symbol manipulation; unsigned integers",
  treatment =    "P Practical",
}


bibtype: article
filename: fparith.bib
label: Barrett:1989:FMA
author: Geoff Barrett
title: Formal methods applied to a floating-point number system
journal: j-IEEE-TRANS-SOFTW-ENG
volume: 15
number: 5
pages: 611--621
month: may
monthnumber: 5
year: 1989
CODEN: IESEDJ
DOI: https://doi.org/10.1109/32.24710
ISSN: 0098-5589 (print), 1939-3520 (electronic) OR 00985589 (print), 19393520 (electronic)
ISSNL: 0098-5589 OR 00985589
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Software Engineering
acknowledgement: ack-nhfb
affiliation: Oxford University, Oxford, UK
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=32
reviewer: Simon Thompson
rawauthor: Geoff Barrett
rawtitle: Formal methods applied to a floating-point number system
abstract:
A formalization of the IEEE standard for binary floating-point arithmetic (ANSI/IEEE Std. 754-1985) is presented in the set-theoretic specification language Z. The formal specification is refined into four sequential components, which unpack the operands, perform the arithmetic, and pack and round the result. This refinement follows proven rules and so demonstrates a mathematically rigorous method of program development. In the course of the proofs, useful internal representations of floating-point numbers are specified. The procedures presented form the basis for the floating-point unit of the Inmos IMS T800 transputer.

subject:
F. Theory of Computation; F.3 LOGICS AND MEANINGS OF PROGRAMS; C. Computer Systems Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION; D. Software; D.2 SOFTWARE ENGINEERING; D. Software; D.2 SOFTWARE ENGINEERING; B. Hardware; B.2 ARITHMETIC AND LOGIC STRUCTURES; B. Hardware; B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION

rawabstract:
A formalization of the IEEE standard for binary floating-point arithmetic (ANSI/IEEE Std. 754-1985) is presented in the set-theoretic specification language Z. The formal specification is refined into four sequential components, which unpack the operands, perform the arithmetic, and pack and round the result. This refinement follows proven rules and so demonstrates a mathematically rigorous method of program development. In the course of the proofs, useful internal representations of floating-point numbers are specified. The procedures presented form the basis for the floating-point unit of the Inmos IMS T800 transputer.

entry:
@Article{Barrett:1989:FMA,
  author =       "Geoff Barrett",
  title =        "Formal methods applied to a floating-point number
                 system",
  journal =      j-IEEE-TRANS-SOFTW-ENG,
  volume =       "15",
  number =       "5",
  pages =        "611--621",
  month =        may,
  year =         "1989",
  CODEN =        "IESEDJ",
  DOI =          "https://doi.org/10.1109/32.24710",
  ISSN =         "0098-5589 (print), 1939-3520 (electronic)",
  ISSN-L =       "0098-5589",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A formalization of the IEEE standard for binary
                 floating-point arithmetic (ANSI/IEEE Std. 754-1985) is
                 presented in the set-theoretic specification language
                 Z. The formal specification is refined into four
                 sequential components, which unpack the operands,
                 perform the arithmetic, and pack and round the result.
                 This refinement follows proven rules and so
                 demonstrates a mathematically rigorous method of
                 program development. In the course of the proofs,
                 useful internal representations of floating-point
                 numbers are specified. The procedures presented form
                 the basis for the floating-point unit of the Inmos IMS
                 T800 transputer.",
  acknowledgement = ack-nhfb,
  affiliation =  "Oxford University, Oxford, UK",
  bibno =        "65476",
  catcode =      "F.3.1; C.5.3; D.2.1; D.2.0; B.2.0; B.5.1",
  content =      "It is paradoxical that no programming language can be
                 completely defined unless it has a formally defined
                 syntax, yet at the same time, languages have informal
                 semantic descriptions. This is most evident in
                 arithmetic, in which the closest thing to a formal
                 description lies in the IEEE standard for binary
                 floating point arithmetic adopted by ANSI in 1985. The
                 standard is written in natural language, with the
                 attendant possibility of ambiguity and inconsistency.
                 The author of this paper has given a formal version of
                 the standard in the Z specification language, which can
                 be thought of as a structured version of predicate
                 logic. After giving a cogent argument for the use of
                 formal methods in standardization, the author presents
                 a stage-by-stage development of the formal description
                 of the standard; while doing this, he stresses the
                 modularity of the description, as exemplified by the
                 separation of normal and exceptional conditions.\par

                 As he introduces the concepts of Z, the author gives
                 brief explanations of the notation, but for a beginner
                 in the field, the paper is best read in conjunction
                 with the original standard and a description of
                 Z.\par

                 A very powerful argument for the formal approach lies
                 in the specification's use. The INMOS T800 floating
                 point unit was developed by means of a series of
                 refinements of the formal specification; the",
  CRclass =      "F.3.1 Specifying and Verifying and Reasoning about
                 Programs; F.3.1 Specification techniques; C.5.3
                 Microcomputers; C.5.3 INMOS Transputer; D.2.1
                 Requirements/Specifications; D.2.1 Z; D.2.0 General;
                 D.2.0 Standards; B.2.0 General; B.5.1 Design; B.5.1
                 Arithmetic and logic units",
  CRnumber =     "9004-0316",
  descriptor =   "Theory of Computation, LOGICS AND MEANINGS OF
                 PROGRAMS, Specifying and Verifying and Reasoning about
                 Programs, Specification techniques; Computer Systems
                 Organization, COMPUTER SYSTEM IMPLEMENTATION,
                 Microcomputers, INMOS Transputer; Software, SOFTWARE
                 ENGINEERING, Requirements/Specifications, Z; Software,
                 SOFTWARE ENGINEERING, General, Standards; Hardware,
                 ARITHMETIC AND LOGIC STRUCTURES, General; Hardware,
                 REGISTER-TRANSFER-LEVEL IMPLEMENTATION, Design,
                 Arithmetic and logic units",
  fjournal =     "IEEE Transactions on Software Engineering",
  genterm =      "ALGORITHMS; DOCUMENTATION; LANGUAGES; STANDARDIZATION;
                 THEORY",
  guideno =      "1989-06803",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=32",
  journalabbrev = "IEEE Trans. Softw. Eng.",
  reviewer =     "Simon Thompson",
  subject =      "F. Theory of Computation; F.3 LOGICS AND MEANINGS OF
                 PROGRAMS; C. Computer Systems Organization; C.5
                 COMPUTER SYSTEM IMPLEMENTATION; D. Software; D.2
                 SOFTWARE ENGINEERING; D. Software; D.2 SOFTWARE
                 ENGINEERING; B. Hardware; B.2 ARITHMETIC AND LOGIC
                 STRUCTURES; B. Hardware; B.5 REGISTER-TRANSFER-LEVEL
                 IMPLEMENTATION",
}


bibtype: inproceedings
filename: fparith.bib
label: Bedard:1989:WFD
author: N. Bedard and M. Birman and G. Chu and L. Hu and C. M. Lim and J. McLeod and L. Torban and F. Ware
title: The Weitek 64-bit floating-point datapath unit
crossref: Chen:1989:TSA
pages: 898--902 (vol. 2)
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Weitek Corp., Sunnyvale, CA, USA
rawauthor: N. Bedard and M. Birman and G. Chu and L. Hu and C. M. Lim and J. McLeod and L. Torban and F. Ware
rawtitle: The {Weitek} 64-bit floating-point datapath unit
abstract:
The authors describe the WTL 3165 and WTL 3364, jointly referred to as the WTL 3X64, which are each 64-bit floating-point data path units designed for high-speed operation in pipelined environment while making possible full compliance with the IEEE standard for binary floating-point arithmetic. It also provides full interruptibility, even in a pipelined environment. The architecture and performance of the 3X64 are described, and a detailed block diagram is presented.

keywords:
64 Bit; Architecture; Binary floating-point arithmetic; Computerised signal processing; DSP chip; Floating-point data path units; Interruptibility; Pipelined environment; Weitek; WTL 3165; WTL 3364; WTL 3X64

thesaurus:
CMOS integrated circuits; Computerised signal processing; Digital arithmetic; Digital signal processing chips; Parallel architectures; Pipeline processing

rawabstract:
The authors describe the WTL 3165 and WTL 3364, jointly referred to as the WTL 3X64, which are each 64-bit floating-point data path units designed for high-speed operation in pipelined environment while making possible full compliance with the IEEE standard for binary floating-point arithmetic. It also provides full interruptibility, even in a pipelined environment. The architecture and performance of the 3X64 are described, and a detailed block diagram is presented.

entry:
@InProceedings{Bedard:1989:WFD,
  author =       "N. Bedard and M. Birman and G. Chu and L. Hu and C. M.
                 Lim and J. McLeod and L. Torban and F. Ware",
  title =        "The {Weitek} 64-bit floating-point datapath unit",
  crossref =     "Chen:1989:TSA",
  pages =        "898--902 (vol. 2)",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The authors describe the WTL 3165 and WTL 3364,
                 jointly referred to as the WTL 3X64, which are each
                 64-bit floating-point data path units designed for
                 high-speed operation in pipelined environment while
                 making possible full compliance with the IEEE standard
                 for binary floating-point arithmetic. It also provides
                 full interruptibility, even in a pipelined environment.
                 The architecture and performance of the 3X64 are
                 described, and a detailed block diagram is presented.",
  acknowledgement = ack-nhfb,
  affiliation =  "Weitek Corp., Sunnyvale, CA, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5220 (Computer architecture); C5230 (Digital
                 arithmetic methods); C5260 (Digital signal
                 processing)",
  keywords =     "64 Bit; Architecture; Binary floating-point
                 arithmetic; Computerised signal processing; DSP chip;
                 Floating-point data path units; Interruptibility;
                 Pipelined environment; Weitek; WTL 3165; WTL 3364; WTL
                 3X64",
  numericalindex = "Word length 6.4E+01 bit",
  thesaurus =    "CMOS integrated circuits; Computerised signal
                 processing; Digital arithmetic; Digital signal
                 processing chips; Parallel architectures; Pipeline
                 processing",
}


bibtype: book
filename: fparith.bib
label: Beliankov:1989:NPO
author: A. Ia Beliankov
title: Nekotorye primeneniia otsenochnoi (``gruboi'') arifmetiki
publisher: VTS AN SSSR
address: Moskva, Russia
pages: 35
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
series: Soobshcheniia po vychislitelnoi matematike
keywords: Algebras, Linear.; Computer arithmetic.; Floating-point arithmetic.
remark: At head of title: Akademiia nauk SSSR. Vychislitelnyi tsentr.
acknowledgement: ack-nhfb
rawauthor: A. Ia Beliankov
rawtitle: Nekotorye primeneniia otsenochnoi (``gruboi'') arifmetiki
entry:
@Book{Beliankov:1989:NPO,
  author =       "A. Ia Beliankov",
  title =        "Nekotorye primeneniia otsenochnoi (``gruboi'')
                 arifmetiki",
  publisher =    "VTS AN SSSR",
  address =      "Moskva, Russia",
  pages =        "35",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "Soobshcheniia po vychislitelnoi matematike",
  acknowledgement = ack-nhfb,
  keywords =     "Algebras, Linear.; Computer arithmetic.;
                 Floating-point arithmetic.",
  remark =       "At head of title: Akademiia nauk SSSR. Vychislitelnyi
                 tsentr.",
}


bibtype: inproceedings
filename: fparith.bib
label: Benschneider:1989:MUP
title: A 50 MHz Uniformly Pipelined 64b Floating-Point Arithmetic Processor
crossref: Wuorinen:1989:DTP
pages: 50--51, 288
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Digital Equipment Corp., Hudson, MA, USA
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Pipeline processing
rawtitle: A 50 {MHz} Uniformly Pipelined 64b Floating-Point Arithmetic Processor
author:
B. J. Benschneider and W. J. Bowhill and E. M. Cooper and M. N. Gavrielov and P. E. Gronowski and V. K. Maheshwari and V. Peng and J. D. Pickholtz and S. Samudrala

abstract:
A description is given of a uniformly pipelined, 50-MHz, 64-b floating-point arithmetic processor implemented in a 1.5- mu m (drawn) CMOS technology which performs single- and double-precision floating-point operations and integer multiplication as defined by a superminicomputer architecture standard. The chip is composed of an interface section and a five-segment execution core. The core insists of a divider, bypassed in all instruction except division, and four fully pipelined stages that are uniformly utilized in the execution of all instructions. The performance is summarized. First pass silicon has been functionally verified at 50 MHz with a set of over one million vectors.

keywords:
1.5 Micron; 50 MHz; 64 Bit; CMOS technology; Divider; Double-precision floating-point operations; Five-segment execution core; Floating-point arithmetic processor; Fully pipelined stages; Integer multiplication; Interface section; Single-precision floating point; Superminicomputer architecture standard

rawabstract:
A description is given of a uniformly pipelined, 50-MHz, 64-b floating-point arithmetic processor implemented in a 1.5- mu m (drawn) CMOS technology which performs single- and double-precision floating-point operations and integer multiplication as defined by a superminicomputer architecture standard. The chip is composed of an interface section and a five-segment execution core. The core insists of a divider, bypassed in all instruction except division, and four fully pipelined stages that are uniformly utilized in the execution of all instructions. The performance is summarized. First pass silicon has been functionally verified at 50 MHz with a set of over one million vectors.

rawauthor:
B. J. Benschneider and W. J. Bowhill and E. M. Cooper and M. N. Gavrielov and P. E. Gronowski and V. K. Maheshwari and V. Peng and J. D. Pickholtz and S. Samudrala

entry:
@InProceedings{Benschneider:1989:MUP,
  author =       "B. J. Benschneider and W. J. Bowhill and E. M. Cooper
                 and M. N. Gavrielov and P. E. Gronowski and V. K.
                 Maheshwari and V. Peng and J. D. Pickholtz and S.
                 Samudrala",
  title =        "A 50 {MHz} Uniformly Pipelined 64b Floating-Point
                 Arithmetic Processor",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "50--51, 288",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A description is given of a uniformly pipelined,
                 50-MHz, 64-b floating-point arithmetic processor
                 implemented in a 1.5- mu m (drawn) CMOS technology
                 which performs single- and double-precision
                 floating-point operations and integer multiplication as
                 defined by a superminicomputer architecture standard.
                 The chip is composed of an interface section and a
                 five-segment execution core. The core insists of a
                 divider, bypassed in all instruction except division,
                 and four fully pipelined stages that are uniformly
                 utilized in the execution of all instructions. The
                 performance is summarized. First pass silicon has been
                 functionally verified at 50 MHz with a set of over one
                 million vectors.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Digital Equipment Corp., Hudson, MA, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5220 (Computer architecture); C5230 (Digital
                 arithmetic methods)",
  confdate =     "15-17 Feb. 1989",
  conflocation = "New York, NY, USA",
  confsponsor =  "IEEE; University of Pennsylvania",
  keywords =     "1.5 Micron; 50 MHz; 64 Bit; CMOS technology; Divider;
                 Double-precision floating-point operations;
                 Five-segment execution core; Floating-point arithmetic
                 processor; Fully pipelined stages; Integer
                 multiplication; Interface section; Single-precision
                 floating point; Superminicomputer architecture
                 standard",
  numericalindex = "Frequency 5.0E+07 Hz; Word length 6.4E+01 bit; Size
                 1.5E-06 m",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Pipeline processing",
}


bibtype: article
filename: fparith.bib
label: Benschneider:1989:PMC
title: A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1317--1323
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
affiliation: Digital Equipment Corp., Hudson, MA, USA
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Pipeline processing
rawtitle: A pipelined {50-MHz} {CMOS} 64-bit floating-point arithmetic processor
author:
Bradley J. Benschneider and William J. Bowhill and Elizabeth M. Cooper and Moshe N. Gavrielov and Paul E. Gronowski and Vijay K. Maheshwari and Victor Peng and Jeffrey D. Pickholtz and Sridhar Samudrala

abstract:
A 135K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except double-precision multiply (40 ns) and divide. The chip employs an exponent difference prediction scheme and a unified leading-one and sticky-bit computation logic for the addition and subtraction operations. A hardware multiplier using a radix-8 modified Booth algorithm and a divider using a radix-2 SRT algorithm are employed.

keywords:
20 Ns; 40 Ns; 50 MHz; 64 Bit; Addition; CMOS; Divider; Execution unit; Exponent difference prediction scheme; Floating-point arithmetic processor; Hardware multiplier; Microprocessor; Processor chip; Radix-2 SRT algorithm; Radix-8 modified Booth algorithm; Sticky-bit computation logic; Subtraction; Unified leading-one; Uniformly pipelined

rawabstract:
A 135K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except double-precision multiply (40 ns) and divide. The chip employs an exponent difference prediction scheme and a unified leading-one and sticky-bit computation logic for the addition and subtraction operations. A hardware multiplier using a radix-8 modified Booth algorithm and a divider using a radix-2 SRT algorithm are employed.

rawauthor:
Bradley J. Benschneider and William J. Bowhill and Elizabeth M. Cooper and Moshe N. Gavrielov and Paul E. Gronowski and Vijay K. Maheshwari and Victor Peng and Jeffrey D. Pickholtz and Sridhar Samudrala

entry:
@Article{Benschneider:1989:PMC,
  author =       "Bradley J. Benschneider and William J. Bowhill and
                 Elizabeth M. Cooper and Moshe N. Gavrielov and Paul E.
                 Gronowski and Vijay K. Maheshwari and Victor Peng and
                 Jeffrey D. Pickholtz and Sridhar Samudrala",
  title =        "A pipelined {50-MHz} {CMOS} 64-bit floating-point
                 arithmetic processor",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1317--1323",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 135K transistor, uniformly pipelined 50-MHz CMOS
                 64-bit floating-point arithmetic processor chip is
                 described. The execution unit is capable of sustaining
                 pipelined performance of one 32-bit or 64-bit result
                 every 20 ns for all operations except double-precision
                 multiply (40 ns) and divide. The chip employs an
                 exponent difference prediction scheme and a unified
                 leading-one and sticky-bit computation logic for the
                 addition and subtraction operations. A hardware
                 multiplier using a radix-8 modified Booth algorithm and
                 a divider using a radix-2 SRT algorithm are employed.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Digital Equipment Corp., Hudson, MA, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5230 (Digital arithmetic methods)",
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "20 Ns; 40 Ns; 50 MHz; 64 Bit; Addition; CMOS; Divider;
                 Execution unit; Exponent difference prediction scheme;
                 Floating-point arithmetic processor; Hardware
                 multiplier; Microprocessor; Processor chip; Radix-2 SRT
                 algorithm; Radix-8 modified Booth algorithm; Sticky-bit
                 computation logic; Subtraction; Unified leading-one;
                 Uniformly pipelined",
  numericalindex = "Word length 6.4E+01 bit; Frequency 5.0E+07 Hz; Time
                 2.0E-08 s; Time 4.0E-08 s",
  summary =      "A 135K transistor, uniformly pipelined 50-MHz CMOS
                 64-bit floating-point arithmetic processor chip is
                 described. The execution unit is capable of sustaining
                 pipelined performance of one 32-bit or 64-bit result
                 every 20 ns for all operations except \ldots{}",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Pipeline processing",
}


bibtype: misc
filename: fparith.bib
label: Bleher:1989:MCA
author: J. Hartmut Bleher and Axel T. Gerlicher and Siegfried M. Rump and Dieter K. Unkauf
title: Method and circuit arrangement for adding floating point numbers
pages: 1317--1323
day: 12
month: sep
monthnumber: 9
year: 1989
bibdate: Mon Dec 29 16:18:28 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.29 16:18:28 ???
URL: http://www.patentstorm.us/patents/4866651/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 4866651
rawauthor: J. Hartmut Bleher and Axel T. Gerlicher and Siegfried M. Rump and Dieter K. Unkauf
rawtitle: Method and circuit arrangement for adding floating point numbers
abstract:
For successively adding a series of floating point numbers, a floating point adder stage (FIG. 2) is used which, in addition to the sum of two floating point operands, emits the remainder, truncated from the smaller operand, as a floating point number. For obtaining an exact sum of the operands, these remainders are summed in the form of intermediate sums. A circuit arrangement for parallel operation comprises series-connected floating point adder stages (FIG. 6), the intermediate sum occurring at the output of each stage and the intermediate remainder being buffered. Remainders are in each case passed on to the next stage, their value decreasing until they are zero. A serially operating arrangement (FIG. 8) comprises a single adder stage (30) and a register stack (34) for buffering the intermediate sums and the final result. A remainder occurring is stored in a remainder register (32) at the output of the adder stage and added to the intermediate sums until the remainder is zero. Subsequently, a fresh operand is applied to the input of the adder stage.

rawabstract:
For successively adding a series of floating point numbers, a floating point adder stage (FIG. 2) is used which, in addition to the sum of two floating point operands, emits the remainder, truncated from the smaller operand, as a floating point number. For obtaining an exact sum of the operands, these remainders are summed in the form of intermediate sums. A circuit arrangement for parallel operation comprises series-connected floating point adder stages (FIG. 6), the intermediate sum occurring at the output of each stage and the intermediate remainder being buffered. Remainders are in each case passed on to the next stage, their value decreasing until they are zero. A serially operating arrangement (FIG. 8) comprises a single adder stage (30) and a register stack (34) for buffering the intermediate sums and the final result. A remainder occurring is stored in a remainder register (32) at the output of the adder stage and added to the intermediate sums until the remainder is zero. Subsequently, a fresh operand is applied to the input of the adder stage.

entry:
@Misc{Bleher:1989:MCA,
  author =       "J. Hartmut Bleher and Axel T. Gerlicher and Siegfried
                 M. Rump and Dieter K. Unkauf",
  title =        "Method and circuit arrangement for adding floating
                 point numbers",
  howpublished = "US Patent 4866651",
  day =          "12",
  month =        sep,
  year =         "1989",
  bibdate =      "Mon Dec 29 16:18:28 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/4866651/fulltext.html",
  abstract =     "For successively adding a series of floating point
                 numbers, a floating point adder stage (FIG. 2) is used
                 which, in addition to the sum of two floating point
                 operands, emits the remainder, truncated from the
                 smaller operand, as a floating point number. For
                 obtaining an exact sum of the operands, these
                 remainders are summed in the form of intermediate sums.
                 A circuit arrangement for parallel operation comprises
                 series-connected floating point adder stages (FIG. 6),
                 the intermediate sum occurring at the output of each
                 stage and the intermediate remainder being buffered.
                 Remainders are in each case passed on to the next
                 stage, their value decreasing until they are zero. A
                 serially operating arrangement (FIG. 8) comprises a
                 single adder stage (30) and a register stack (34) for
                 buffering the intermediate sums and the final result. A
                 remainder occurring is stored in a remainder register
                 (32) at the output of the adder stage and added to the
                 intermediate sums until the remainder is zero.
                 Subsequently, a fresh operand is applied to the input
                 of the adder stage.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Boddie:1989:FDC
author: J. R. Boddie and R. N. Gadenz and C. J. Garen and J. M. Huser and B. Ng and S. P. Pekarich
title: A 32-bit floating-point DSP with C compiler
crossref: Chen:1989:TSA
pages: 880--884 vol.2
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: AT&T Bell Lab., Holmdel, NJ, USA
rawauthor: J. R. Boddie and R. N. Gadenz and C. J. Garen and J. M. Huser and B. Ng and S. P. Pekarich
rawtitle: A 32-bit floating-point {DSP} with {C} compiler
abstract:
A novel digital signal processor (the DSP32C) has been developed which performs 32-bit floating point operations at a rate of 25 MFLOPS (million floating-point operations per second) and can be programmed using a standard C compiler. The authors present an overview of the architecture and instruction set with emphasis on the enhancements over its predecessor, the DSP32. The performance is expressed with common signal processor benchmarks. The application development environment is described which highlights the C compiler and hardware development system. Finally, an application example illustrates the power and ease of this DSP.

keywords:
25 MFLOPS; 32 Bit; Architecture; C compiler; Computerised signal processing; DSP32C; Floating point digital signal processor; Instruction set

thesaurus:
CMOS integrated circuits; Computerised signal processing; Digital signal processing chips; Program compilers

rawabstract:
A novel digital signal processor (the DSP32C) has been developed which performs 32-bit floating point operations at a rate of 25 MFLOPS (million floating-point operations per second) and can be programmed using a standard C compiler. The authors present an overview of the architecture and instruction set with emphasis on the enhancements over its predecessor, the DSP32. The performance is expressed with common signal processor benchmarks. The application development environment is described which highlights the C compiler and hardware development system. Finally, an application example illustrates the power and ease of this DSP.

entry:
@InProceedings{Boddie:1989:FDC,
  author =       "J. R. Boddie and R. N. Gadenz and C. J. Garen and J.
                 M. Huser and B. Ng and S. P. Pekarich",
  title =        "A 32-bit floating-point {DSP} with {C} compiler",
  crossref =     "Chen:1989:TSA",
  pages =        "880--884 vol.2",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A novel digital signal processor (the DSP32C) has been
                 developed which performs 32-bit floating point
                 operations at a rate of 25 MFLOPS (million
                 floating-point operations per second) and can be
                 programmed using a standard C compiler. The authors
                 present an overview of the architecture and instruction
                 set with emphasis on the enhancements over its
                 predecessor, the DSP32. The performance is expressed
                 with common signal processor benchmarks. The
                 application development environment is described which
                 highlights the C compiler and hardware development
                 system. Finally, an application example illustrates the
                 power and ease of this DSP.",
  acknowledgement = ack-nhfb,
  affiliation =  "AT\&T Bell Lab., Holmdel, NJ, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5260 (Digital signal processing); C6150C
                 (Compilers, interpreters and other processors)",
  keywords =     "25 MFLOPS; 32 Bit; Architecture; C compiler;
                 Computerised signal processing; DSP32C; Floating point
                 digital signal processor; Instruction set",
  numericalindex = "Word length 3.2E+01 bit; Computer speed 2.5E+07
                 FLOPS",
  thesaurus =    "CMOS integrated circuits; Computerised signal
                 processing; Digital signal processing chips; Program
                 compilers",
}


bibtype: techreport
filename: fparith.bib
label: Bohlender:1989:FST
author: Gerd Bohlender and Gudenberg, J. Wolff von (Jurgen Wolff) and Willard L. Miranker
title: Floating-point systems for theorem proving
type: Research report
number: RC 15101 (\#67356)
institution: IBM T.J. Watson Research Center
address: Yorktown Heights, NY, USA
pages: 14
day: 2
month: nov
monthnumber: 11
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Electronic digital computers --- Programming.; Floating-point arithmetic.
acknowledgement: ack-nhfb
rawauthor: Gerd Bohlender and Gudenberg, J. Wolff von (Jurgen Wolff) and Willard L. Miranker
rawtitle: Floating-point systems for theorem proving
abstract:
There are a number of existing floating-point systems (programming languages and libraries) which allow the computer user to produce computation with guarantees. These systems may be conveniently used as a component in theorem proving. Following a brief description of the methodology which underlies these systems, we tabulate them, indicating some properties and noting where they may be obtained for use. A brief appendix supplies an introduction to the formalism of the methodology.

rawabstract:
There are a number of existing floating-point systems (programming languages and libraries) which allow the computer user to produce computation with guarantees. These systems may be conveniently used as a component in theorem proving. Following a brief description of the methodology which underlies these systems, we tabulate them, indicating some properties and noting where they may be obtained for use. A brief appendix supplies an introduction to the formalism of the methodology.

entry:
@TechReport{Bohlender:1989:FST,
  author =       "Gerd Bohlender and Gudenberg, J. Wolff von (Jurgen
                 Wolff) and Willard L. Miranker",
  title =        "Floating-point systems for theorem proving",
  type =         "Research report",
  number =       "RC 15101 (\#67356)",
  institution =  "IBM T.J. Watson Research Center",
  address =      "Yorktown Heights, NY, USA",
  pages =        "14",
  day =          "2",
  month =        nov,
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "There are a number of existing floating-point systems
                 (programming languages and libraries) which allow the
                 computer user to produce computation with guarantees.
                 These systems may be conveniently used as a component
                 in theorem proving. Following a brief description of
                 the methodology which underlies these systems, we
                 tabulate them, indicating some properties and noting
                 where they may be obtained for use. A brief appendix
                 supplies an introduction to the formalism of the
                 methodology.",
  acknowledgement = ack-nhfb,
  keywords =     "Electronic digital computers --- Programming.;
                 Floating-point arithmetic.",
}


bibtype: inproceedings
filename: fparith.bib
label: Brackert:1989:DLM
author: R. H. Brackert, Jr. and M. D. Ercegovac and A. N. Willson, Jr.
title: Design of an on-line multiply-add module for recursive digital filters
crossref: Ercegovac:1989:PSC
pages: 34--41
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Brackert.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: R. H. {Brackert, Jr.} and M. D. Ercegovac and A. N. {Willson, Jr.}
rawtitle: Design of an on-line multiply-add module for recursive digital filters
entry:
@InProceedings{Brackert:1989:DLM,
  author =       "R. H. {Brackert, Jr.} and M. D. Ercegovac and A. N.
                 {Willson, Jr.}",
  title =        "Design of an on-line multiply-add module for recursive
                 digital filters",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "34--41",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Brackert.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Brightman:1989:ASF
author: T. Brightman
title: Advancing the Standard in Floating-Point Performance
journal: j-HIGH-PERFORM-SYST
volume: 10
number: 11
pages: 59, 62--64
month: nov
monthnumber: 11
year: 1989
CODEN: HPSYEA
ISSN: 0279-2834 OR 02792834
bibdate: Wed Dec 13 18:25:43 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.13 18:25:43 ???
fjournal: High performance systems
acknowledgement: ack-nhfb
affiliation: Cyrix Corp., Richardson, TX, USA
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Satellite computers; VLSI
rawauthor: T. Brightman
rawtitle: Advancing the Standard in Floating-Point Performance
abstract:
The Cyrix FasMath 83D87 is a floating-point coprocessor chip that combines Intel 80387 socket and software compatibility with the high performance of Weitek's industry-leading coprocessor. The chip is a VLSI CMOS integrated circuit built initially using 1.2-micron double-layer-metal, single-layer-polysilicon process technology. It was designed to minimize complications in the design of high-performance desktop and laptop computer systems.

keywords:
Cyrix FasMath 83D87; Desktop computer systems; Double-layer-metal; Floating-point coprocessor chip; Intel 80387; Laptop computer systems; Math coprocessor; Si; Single-layer-polysilicon process technology; Socket compatibility; Software compatibility; VLSI CMOS integrated circuit

rawabstract:
The Cyrix FasMath 83D87 is a floating-point coprocessor chip that combines Intel 80387 socket and software compatibility with the high performance of Weitek's industry-leading coprocessor. The chip is a VLSI CMOS integrated circuit built initially using 1.2-micron double-layer-metal, single-layer-polysilicon process technology. It was designed to minimize complications in the design of high-performance desktop and laptop computer systems.

entry:
@Article{Brightman:1989:ASF,
  author =       "T. Brightman",
  title =        "Advancing the Standard in Floating-Point Performance",
  journal =      j-HIGH-PERFORM-SYST,
  volume =       "10",
  number =       "11",
  pages =        "59, 62--64",
  month =        nov,
  year =         "1989",
  CODEN =        "HPSYEA",
  ISSN =         "0279-2834",
  bibdate =      "Wed Dec 13 18:25:43 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Cyrix FasMath 83D87 is a floating-point
                 coprocessor chip that combines Intel 80387 socket and
                 software compatibility with the high performance of
                 Weitek's industry-leading coprocessor. The chip is a
                 VLSI CMOS integrated circuit built initially using
                 1.2-micron double-layer-metal, single-layer-polysilicon
                 process technology. It was designed to minimize
                 complications in the design of high-performance desktop
                 and laptop computer systems.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Cyrix Corp., Richardson, TX, USA",
  chemicalindex = "Si/int Si/el",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips)",
  fjournal =     "High performance systems",
  keywords =     "Cyrix FasMath 83D87; Desktop computer systems;
                 Double-layer-metal; Floating-point coprocessor chip;
                 Intel 80387; Laptop computer systems; Math coprocessor;
                 Si; Single-layer-polysilicon process technology; Socket
                 compatibility; Software compatibility; VLSI CMOS
                 integrated circuit",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Satellite computers; VLSI",
}


bibtype: article
filename: fparith.bib
label: Buell:1989:MIA
author: D. Buell and R. Ward
title: A Multiprecise Integer Arithmetic Package
journal: j-J-SUPERCOMPUTING
volume: 3
pages: 89--107
year: 1989
CODEN: JOSUED
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Sun Sep 11 21:56:51 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.11 21:56:51 ???
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11227
rawauthor: D. Buell and R. Ward
rawtitle: A Multiprecise Integer Arithmetic Package
entry:
@Article{Buell:1989:MIA,
  author =       "D. Buell and R. Ward",
  title =        "A Multiprecise Integer Arithmetic Package",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "3",
  number =       "??",
  pages =        "89--107",
  month =        "????",
  year =         "1989",
  CODEN =        "JOSUED",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Sun Sep 11 21:56:51 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: inproceedings
filename: fparith.bib
label: Carter:1989:CHH
author: T. M. Carter
title: Cascade: hardware for high / variable precision arithmetic
crossref: Ercegovac:1989:PSC
pages: 184--191
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Carter.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: T. M. Carter
rawtitle: {Cascade}: hardware for high\slash variable precision arithmetic
entry:
@InProceedings{Carter:1989:CHH,
  author =       "T. M. Carter",
  title =        "{Cascade}: hardware for high\slash variable precision
                 arithmetic",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "184--191",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Carter.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Chan:1989:ADC
author: P. K. Chan and M. D. F. Schlag
title: Analysis and design of CMOS Manchester adders with variable carry-skip
crossref: Ercegovac:1989:PSC
pages: 86--95
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Chan.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: P. K. Chan and M. D. F. Schlag
rawtitle: Analysis and design of {CMOS Manchester} adders with variable carry-skip
entry:
@InProceedings{Chan:1989:ADC,
  author =       "P. K. Chan and M. D. F. Schlag",
  title =        "Analysis and design of {CMOS Manchester} adders with
                 variable carry-skip",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "86--95",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Chan.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:1989:DRN
author: J. T. Chen and W. K. Jenkins
booktitle: IEEE International Symposium on Circuits and Systems, 8--11 May 1989
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 208--211
year: 1989
DOI: https://doi.org/10.1109/ISCAS.1989.100328
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: J. T. Chen and W. K. Jenkins
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, 8--11 May 1989
title:
Design of a residue number system digital correlator for real-time processing in ultrasonic blood flow measurements

rawtitle:
Design of a residue number system digital correlator for real-time processing in ultrasonic blood flow measurements

entry:
@InProceedings{Chen:1989:DRN,
  author =       "J. T. Chen and W. K. Jenkins",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, 8--11 May 1989",
  title =        "Design of a residue number system digital correlator
                 for real-time processing in ultrasonic blood flow
                 measurements",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "208--211",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1989.100328",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The design of a high-speed digital correlator for
                 implementing the real-time correlation function
                 required in an ultrasonic blood flowmeter is presented.
                 In order to achieve the necessary real-time processing
                 rates, a residue number system (RNS) \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Chen:1989:FCN
author: S. G. Chen and P. Y. Hsieh
title: Fast Computation of the $N$ th Root
journal: j-COMPUT-MATH-APPL
volume: 17
number: 10
pages: 1423--1427
year: 1989
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Thu Sep 15 18:41:31 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.15 18:41:31 ???
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nj
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: S. G. Chen and P. Y. Hsieh
rawtitle: Fast Computation of the {$N$ th} Root
entry:
@Article{Chen:1989:FCN,
  author =       "S. G. Chen and P. Y. Hsieh",
  title =        "Fast Computation of the {$N$ th} Root",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "17",
  number =       "10",
  pages =        "1423--1427",
  year =         "1989",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Thu Sep 15 18:41:31 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
  xxmonth =      "(none)",
}


bibtype: article
filename: fparith.bib
label: Chen:1989:FCTa
author: S.-G. Chen and P. Y. Hsieh
title: Fast computation of the $N$-th root
journal: j-COMPUT-MATH-APPL
volume: 17
number: 10
pages: 1423--1427
year: 1989
CODEN: CMAPDK
DOI: https://doi.org/10.1016/0898-1221(89)90024-2
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 19:01:11 MST 2017
bibtimestamp: 2017.03.01 19:01:11 MST
URL: http://www.sciencedirect.com/science/article/pii/0898122189900242
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nj
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: S.-G. Chen and P. Y. Hsieh
rawtitle: Fast computation of the {$N$}-th root
bibsource:
ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/computmathappl1980.bib; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

remark:
From the abstract: ``A new class of iterative methods for computing a differentiable function is proposed, which is based on Pade approximation to Taylor's series of the function. It leads to a faster algorithm than Newton's method for $ x^1 / N $ and a different interpretation of Newton's method.''

entry:
@Article{Chen:1989:FCTa,
  author =       "S.-G. Chen and P. Y. Hsieh",
  title =        "Fast computation of the {$N$}-th root",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "17",
  number =       "10",
  pages =        "1423--1427",
  month =        "????",
  year =         "1989",
  CODEN =        "CMAPDK",
  DOI =          "https://doi.org/10.1016/0898-1221(89)90024-2",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 19:01:11 MST 2017",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/computmathappl1980.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/0898122189900242",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
  remark =       "From the abstract: ``A new class of iterative methods
                 for computing a differentiable function is proposed,
                 which is based on Pad{\'e} approximation to Taylor's
                 series of the function. It leads to a faster algorithm
                 than Newton's method for $ x^{1 / N} $ and a different
                 interpretation of Newton's method.''",
}


bibtype: mastersthesis
filename: fparith.bib
label: Chinn:1989:DIA
author: Patty Chinn
type: Thesis (M.S.E.E.)
school: University of Washingto
address: Seattle, WA, USA
pages: vi + 45 + 1
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Image processing --- Digital techniques.
acknowledgement: ack-nhfb
rawauthor: Patty Chinn
title:
The design, implementation, and applications of an ACT8837 floating point processor in an image processing hardware subsystem

rawtitle:
The design, implementation, and applications of an {ACT8837} floating point processor in an image processing hardware subsystem

entry:
@MastersThesis{Chinn:1989:DIA,
  author =       "Patty Chinn",
  title =        "The design, implementation, and applications of an
                 {ACT8837} floating point processor in an image
                 processing hardware subsystem",
  type =         "Thesis ({M.S.E.E.})",
  school =       "University of Washingto",
  address =      "Seattle, WA, USA",
  pages =        "vi + 45 + 1",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Image processing --- Digital techniques.",
}


bibtype: book
filename: fparith.bib
label: Chow:1989:MXR
editor: Paul Chow
title: The MIPS-X RISC Microprocessor
publisher: pub-KLUWER
address: pub-KLUWER:adr
pages: xxiv + 231
year: 1989
ISBN: 0-7923-9045-8 OR 0792390458
ISBN13: 978-0-7923-9045-9 OR 9780792390459
LCCN: QA76.8.M524 M57 1989
bibdate: Tue Dec 14 23:27:43 1993
bibtimestamp: 1993.12.14 23:27:43 ???
series: The Kluwer international series in engineering and computer science
keywords: MIPS-X (microprocessor); VLSI, computer architecture, and digital signal processing SECS 81
ZMnumber: 0706.68010
acknowledgement: ack-nhfb
raweditor: Paul Chow
rawtitle: The {MIPS-X RISC} Microprocessor
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/master.bib; https://www.math.utah.edu/pub/tex/bib/microchip.bib

entry:
@Book{Chow:1989:MXR,
  editor =       "Paul Chow",
  title =        "The {MIPS-X RISC} Microprocessor",
  publisher =    pub-KLUWER,
  address =      pub-KLUWER:adr,
  pages =        "xxiv + 231",
  year =         "1989",
  ISBN =         "0-7923-9045-8",
  ISBN-13 =      "978-0-7923-9045-9",
  LCCN =         "QA76.8.M524 M57 1989",
  bibdate =      "Tue Dec 14 23:27:43 1993",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib;
                 https://www.math.utah.edu/pub/tex/bib/microchip.bib",
  series =       "The Kluwer international series in engineering and
                 computer science",
  ZMnumber =     "0706.68010",
  acknowledgement = ack-nhfb,
  keywords =     "MIPS-X (microprocessor); VLSI, computer architecture,
                 and digital signal processing SECS 81",
}


bibtype: inproceedings
filename: fparith.bib
label: Clenshaw:1989:LIA
author: C. W. Clenshaw and F. W. J. Olver and P. R. Turner
title: Level-index arithmetic: An introductory survey
crossref: Turner:1989:NAP
pages: 95--168
year: 1989
DOI: https://doi.org/10.1007/BFb0085715
bibdate: Tue Oct 09 09:58:20 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 09:58:20 ???
acknowledgement: ack-nhfb
rawauthor: C. W. Clenshaw and F. W. J. Olver and P. R. Turner
rawtitle: Level-index arithmetic: An introductory survey
entry:
@InProceedings{Clenshaw:1989:LIA,
  author =       "C. W. Clenshaw and F. W. J. Olver and P. R. Turner",
  title =        "Level-index arithmetic: An introductory survey",
  crossref =     "Turner:1989:NAP",
  pages =        "95--168",
  year =         "1989",
  DOI =          "https://doi.org/10.1007/BFb0085715",
  bibdate =      "Tue Oct 09 09:58:20 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Clenshaw:1989:RSU
author: C. W. Clenshaw and Peter R. Turner
title: Root squaring using level-index arithmetic
journal: j-COMPUTING
volume: 43
number: 2
pages: 171--185
month: jun
monthnumber: 6
year: 1989
CODEN: CMPTA2
DOI: https://doi.org/10.1007/BF02241860
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
MRclass: 65G99 (65H05)
MRnumber: 1 034 362
bibdate: Sun Nov 12 06:18:24 2023
bibtimestamp: 2023.11.12 06:18:24 ???
fjournal: Computing. Archives for Scientific Computing
acknowledgement: ack-nhfb
authordates: Charles William Clenshaw (15 March 1926--23 September 2004)
journalURL: http://link.springer.com/journal/607
subjectdates: Frank William John Olver (15 December 1924--23 April 2013)
rawauthor: C. W. Clenshaw and Peter R. Turner
rawtitle: Root squaring using level-index arithmetic
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=journal&issn=0010-485X; https://www.math.utah.edu/pub/bibnet/authors/c/clenshaw-charles-w.bib; https://www.math.utah.edu/pub/bibnet/authors/o/olver-frank-w-j.bib; https://www.math.utah.edu/pub/tex/bib/computing.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; MathSciNet database

entry:
@Article{Clenshaw:1989:RSU,
  author =       "C. W. Clenshaw and Peter R. Turner",
  title =        "Root squaring using level-index arithmetic",
  journal =      j-COMPUTING,
  volume =       "43",
  number =       "2",
  pages =        "171--185",
  month =        jun,
  year =         "1989",
  CODEN =        "CMPTA2",
  DOI =          "https://doi.org/10.1007/BF02241860",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  MRclass =      "65G99 (65H05)",
  MRnumber =     "1 034 362",
  bibdate =      "Sun Nov 12 06:18:24 2023",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=journal&issn=0010-485X;
                 https://www.math.utah.edu/pub/bibnet/authors/c/clenshaw-charles-w.bib;
                 https://www.math.utah.edu/pub/bibnet/authors/o/olver-frank-w-j.bib;
                 https://www.math.utah.edu/pub/tex/bib/computing.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 MathSciNet database",
  acknowledgement = ack-nhfb,
  author-dates = "Charles William Clenshaw (15 March 1926--23 September
                 2004)",
  fjournal =     "Computing. Archives for Scientific Computing",
  journal-URL =  "http://link.springer.com/journal/607",
  subject-dates = "Frank William John Olver (15 December 1924--23 April
                 2013)",
  xxtitle =      "{Das Graeffe-Verfahren mit H{\"o}henindexarithmetik}",
}


bibtype: techreport
filename: fparith.bib
label: Cody:1989:AXF
author: W. J. Cody
title: Algorithm XXX: Functions to Support the IEEE Standard for Binary Floating-Point Arithmetic
number: MCS-P90-0789
institution: Mathematics and Computer Science Division, Argonne National Laboratory
address: Argonne, IL, USA
month: jul
monthnumber: 7
year: 1989
bibdate: Thu Sep 01 10:38:08 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:38:08 ???
acknowledgement: ack-nj
rawauthor: W. J. Cody
rawtitle: Algorithm {XXX}: Functions to Support the {IEEE} Standard for Binary Floating-Point Arithmetic
entry:
@TechReport{Cody:1989:AXF,
  author =       "W. J. Cody",
  title =        "Algorithm {XXX}: Functions to Support the {IEEE}
                 Standard for Binary Floating-Point Arithmetic",
  number =       "MCS-P90-0789",
  institution =  "Mathematics and Computer Science Division, Argonne
                 National Laboratory",
  address =      "Argonne, IL, USA",
  pages =        "??",
  month =        jul,
  year =         "1989",
  bibdate =      "Thu Sep 01 10:38:08 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: inproceedings
filename: fparith.bib
label: Dadda:1989:PC
author: Luigi Dadda
title: Polyphase convolvers
crossref: Ercegovac:1989:PSC
pages: 78--85
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Dadda.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
authordates: 29 April 1923--26 October 2012
rawauthor: Luigi Dadda
rawtitle: Polyphase convolvers
entry:
@InProceedings{Dadda:1989:PC,
  author =       "Luigi Dadda",
  title =        "Polyphase convolvers",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "78--85",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Dadda.pdf",
  acknowledgement = ack-nhfb,
  author-dates = "29 April 1923--26 October 2012",
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Dadda:1989:SIM
author: Luigi Dadda
title: On serial-input multipliers for two's complement numbers
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 9
pages: 1341--1345
month: sep
monthnumber: 9
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.29478
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:41 MDT 2011
bibtimestamp: 2011.07.08 19:00:41 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=29478
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
authordates: 29 April 1923--26 October 2012
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Luigi Dadda
rawtitle: On serial-input multipliers for two's complement numbers
entry:
@Article{Dadda:1989:SIM,
  author =       "Luigi Dadda",
  title =        "On serial-input multipliers for two's complement
                 numbers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "9",
  pages =        "1341--1345",
  month =        sep,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.29478",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:41 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=29478",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  author-dates = "29 April 1923--26 October 2012",
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Dally:1989:MOF
author: W. J. Dally
title: Micro-optimization of floating-point operations
journal: j-COMP-ARCH-NEWS
volume: 17
number: 2
pages: 283--289
month: apr
monthnumber: 4
year: 1989
CODEN: CANED2
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Fri May 12 09:40:39 MDT 2006
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.12 09:40:39 MDT
fjournal: ACM SIGARCH Computer Architecture News
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J89
rawauthor: W. J. Dally
rawtitle: Micro-optimization of floating-point operations
entry:
@Article{Dally:1989:MOF,
  author =       "W. J. Dally",
  title =        "Micro-optimization of floating-point operations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "283--289",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
}


bibtype: article
filename: fparith.bib
label: DAngelo:1989:DEA
author: S. D'Angelo and G. R. Sechi
title: Definition of elementary arithmetic operations by using ACM
journal: j-SIGMICRO
volume: 20
number: 3
pages: 160--162
month: aug
monthnumber: 8
year: 1989
CODEN: SIGMDJ
DOI: https://doi.org/10.1145/75395.75414
ISSN: 0163-5751, 1050-916X OR 01635751, 1050916X
ISSNL: 0163-5751 OR 01635751
bibdate: Fri Apr 16 10:27:41 MDT 2021
bibtimestamp: 2021.04.16 10:27:41 MDT
URL: https://dl.acm.org/doi/10.1145/75395.75414
fjournal: ACM SIGMICRO Newsletter
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/sigmicro
rawauthor: S. D'Angelo and G. R. Sechi
rawtitle: Definition of elementary arithmetic operations by using {ACM}
entry:
@Article{DAngelo:1989:DEA,
  author =       "S. D'Angelo and G. R. Sechi",
  title =        "Definition of elementary arithmetic operations by
                 using {ACM}",
  journal =      j-SIGMICRO,
  volume =       "20",
  number =       "3",
  pages =        "160--162",
  month =        aug,
  year =         "1989",
  CODEN =        "SIGMDJ",
  DOI =          "https://doi.org/10.1145/75395.75414",
  ISSN =         "0163-5751, 1050-916X",
  ISSN-L =       "0163-5751",
  bibdate =      "Fri Apr 16 10:27:41 MDT 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigmicro.bib",
  URL =          "https://dl.acm.org/doi/10.1145/75395.75414",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGMICRO Newsletter",
  journal-URL =  "https://dl.acm.org/loi/sigmicro",
}


bibtype: misc
filename: fparith.bib
label: Darley:1989:FPI
title: Floating Point / Integer Processor with Divide and Square Root Functions
pages: 160--162
day: 31
month: oct
monthnumber: 10
year: 1989
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
note: U.S. Patent No. 4,878,190 held by Texas Instruments. Expired 2008-01-29.
URL: https://patentimages.storage.googleapis.com/bb/ca/c5/ed5ce0fc874200/US4878190.pdf
acknowledgement: ack-sfo
rawnote: U.S. Patent No. 4,878,190 held by Texas Instruments. Expired 2008-01-29.
rawtitle: Floating Point\slash Integer Processor with Divide and Square Root Functions
author:
Henry M. Darley and Michael C. Gill and Dale C. Earl and Dinh T. Ngo and Paul C. Wang and Maria B. L. Hipona and Jim Dodrill

rawauthor:
Henry M. Darley and Michael C. Gill and Dale C. Earl and Dinh T. Ngo and Paul C. Wang and Maria B. L. Hipona and Jim Dodrill

entry:
@Misc{Darley:1989:FPI,
  author =       "Henry M. Darley and Michael C. Gill and Dale C. Earl
                 and Dinh T. Ngo and Paul C. Wang and Maria B. L. Hipona
                 and Jim Dodrill",
  title =        "Floating Point\slash Integer Processor with Divide and
                 Square Root Functions",
  day =          "31",
  month =        oct,
  year =         "1989",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "U.S. Patent No. 4,878,190 held by Texas Instruments.
                 Expired 2008-01-29.",
  URL =          "https://patentimages.storage.googleapis.com/bb/ca/c5/ed5ce0fc874200/US4878190.pdf",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: deLange:1989:DMA
author: A. A. J. de Lange and A. J. van der Hoeven and E. F. Deprettere and P. Dewilde and J. Bu
crossref: IEE:1989:EEC
pages: 410--414
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Delft University of Technol., Netherlands
rawauthor: A. A. J. de Lange and A. J. van der Hoeven and E. F. Deprettere and P. Dewilde and J. Bu
title:
The design of a 50 Mflop arithmetic chip for massively parallel pipelined DSP algorithms: the floating point pipeline CORDIC processor

abstract:
The paper describes a high performance VLSI CORDIC arithmetic chip. It performs 15 10/sup 6/ rotations/sec (50 Mflops) and can be applied as a processing element in parallel/pipelined processor structures (systolic and wavefront arrays) for real time/high speed signal processing algorithms and matrix computation applications. The authors present a novel optimized (floating point) CORDIC algorithm, and architecture, its performance and layout. Algorithm, architecture, performance and layout are parametrized which allows automatic generation of the chip layout for any required chip performance, accuracy and dynamic range of arithmetic operations.

keywords:
50 MFLOPS; Chip layout automatic generation; Dynamic range; Floating point pipeline CORDIC processor; High speed signal processing algorithm; Matrix computation applications; Parallel structure; Pipelined processor structure; Real time signal processing; Systolic arrays; VLSI CORDIC arithmetic chip; Wavefront arrays

thesaurus:
Digital arithmetic; Digital signal processing chips; Parallel architectures; Pipeline processing; VLSI

rawabstract:
The paper describes a high performance VLSI CORDIC arithmetic chip. It performs 15 10/sup 6/ rotations/sec (50 Mflops) and can be applied as a processing element in parallel/pipelined processor structures (systolic and wavefront arrays) for real time/high speed signal processing algorithms and matrix computation applications. The authors present a novel optimized (floating point) CORDIC algorithm, and architecture, its performance and layout. Algorithm, architecture, performance and layout are parametrized which allows automatic generation of the chip layout for any required chip performance, accuracy and dynamic range of arithmetic operations.

rawtitle:
The design of a 50 Mflop arithmetic chip for massively parallel pipelined {DSP} algorithms: the floating point pipeline {CORDIC} processor

entry:
@InProceedings{deLange:1989:DMA,
  author =       "A. A. J. de Lange and A. J. van der Hoeven and E. F.
                 Deprettere and P. Dewilde and J. Bu",
  title =        "The design of a 50 Mflop arithmetic chip for massively
                 parallel pipelined {DSP} algorithms: the floating point
                 pipeline {CORDIC} processor",
  crossref =     "IEE:1989:EEC",
  pages =        "410--414",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The paper describes a high performance VLSI CORDIC
                 arithmetic chip. It performs 15 10/sup 6/ rotations/sec
                 (50 Mflops) and can be applied as a processing element
                 in parallel/pipelined processor structures (systolic
                 and wavefront arrays) for real time/high speed signal
                 processing algorithms and matrix computation
                 applications. The authors present a novel optimized
                 (floating point) CORDIC algorithm, and architecture,
                 its performance and layout. Algorithm, architecture,
                 performance and layout are parametrized which allows
                 automatic generation of the chip layout for any
                 required chip performance, accuracy and dynamic range
                 of arithmetic operations.",
  acknowledgement = ack-nhfb,
  affiliation =  "Delft University of Technol., Netherlands",
  classification = "B1265F (Microprocessors and microcomputers); B2570
                 (Semiconductor integrated circuits); C5220 (Computer
                 architecture); C5230 (Digital arithmetic methods);
                 C5260 (Digital signal processing)",
  keywords =     "50 MFLOPS; Chip layout automatic generation; Dynamic
                 range; Floating point pipeline CORDIC processor; High
                 speed signal processing algorithm; Matrix computation
                 applications; Parallel structure; Pipelined processor
                 structure; Real time signal processing; Systolic
                 arrays; VLSI CORDIC arithmetic chip; Wavefront arrays",
  numericalindex = "Computer speed 5.0E+07 FLOPS",
  thesaurus =    "Digital arithmetic; Digital signal processing chips;
                 Parallel architectures; Pipeline processing; VLSI",
}


bibtype: techreport
filename: fparith.bib
label: Demmel:1989:FPE
author: J. Demmel
title: On Floating Point Errors in Cholesky
type: LAPACK Working Note
number: 14
institution: inst-UT-CS
address: inst-UT-CS:adr
pages: 410--414
month: oct
monthnumber: 10
year: 1989
bibdate: Fri Apr 22 17:06:37 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.22 17:06:37 ???
note: UT-CS-89-87, October 1989.
URL: http://www.netlib.org/lapack/lawns/lawn14.ps; http://www.netlib.org/lapack/lawnspdf/lawn14.pdf
acknowledgement: ack-nhfb
rawauthor: J. Demmel
rawnote: UT-CS-89-87, October 1989.
rawtitle: On Floating Point Errors in {Cholesky}
entry:
@TechReport{Demmel:1989:FPE,
  author =       "J. Demmel",
  title =        "On Floating Point Errors in {Cholesky}",
  type =         "{LAPACK} Working Note",
  number =       "14",
  institution =  inst-UT-CS,
  address =      inst-UT-CS:adr,
  month =        oct,
  year =         "1989",
  bibdate =      "Fri Apr 22 17:06:37 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "UT-CS-89-87, October 1989.",
  URL =          "http://www.netlib.org/lapack/lawns/lawn14.ps;
                 http://www.netlib.org/lapack/lawnspdf/lawn14.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Dennis:1989:AAD
author: A. M. Dennis and C. B. Marshall and I. A. Burgess
booktitle: IEE Colloquium on Signal Processing Applications of Finite Field Mathematics, 1 June 1989
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1/1--1/5
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266615
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: A. M. Dennis and C. B. Marshall and I. A. Burgess
rawbooktitle: {IEE} Colloquium on Signal Processing Applications of Finite Field Mathematics, 1 June 1989
title:
Algorithm and architecture design for the implementation of high order FIR filters using the residue number system

rawtitle:
Algorithm and architecture design for the implementation of high order {FIR} filters using the residue number system

entry:
@InProceedings{Dennis:1989:AAD,
  author =       "A. M. Dennis and C. B. Marshall and I. A. Burgess",
  booktitle =    "{IEE} Colloquium on Signal Processing Applications of
                 Finite Field Mathematics, 1 June 1989",
  title =        "Algorithm and architecture design for the
                 implementation of high order {FIR} filters using the
                 residue number system",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1/1--1/5",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266615",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The computational speed requirements of future signal
                 processing algorithms necessitate the use of special
                 purpose multiprocessor systems implemented using VLSI
                 technology. Finite field arithmetic and algorithms
                 offer an extra degree of freedom in \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Dowling:1989:MVF
author: E. Dowling and M. Griffin and M. Lynch and F. Taylor
title: A multi-purpose VLSI floating-point array processor
crossref: Chen:1989:TSA
pages: 730--734 vol.2
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Department of Electr. Eng., Florida University, Gainesville, FL, USA
rawauthor: E. Dowling and M. Griffin and M. Lynch and F. Taylor
rawtitle: A multi-purpose {VLSI} floating-point array processor
abstract:
A 3*3 single-instruction multiple-data (SIMD) array processor for the IBM PC/AT is described. This array processor is a modified bus-connected architecture (MBCA) using TI's SN74ACT8847 64-bit VLSI floating-point units for processing elements. The array processor can operate four different modes of operation: scalar, vector processor, full utilization, and simulated systolic. In full utilization mode, this array processor can sustain a 90-MFLOP computational rate. System software is also discussed, and attention is given to how it will be used with the SIGLAB programming environment.

keywords:
64 Bit; 90 MFLOPS; Full utilization mode; IBM PC/AT; Modes of operation; Modified bus-connected architecture; SIGLAB programming environment; SIMD; Single-instruction multiple-data; SN74ACT8847; VLSI floating-point array processor

thesaurus:
CMOS integrated circuits; IBM computers; Microcomputers; Microprocessor chips; Parallel architectures; Parallel processing; VLSI

rawabstract:
A 3*3 single-instruction multiple-data (SIMD) array processor for the IBM PC/AT is described. This array processor is a modified bus-connected architecture (MBCA) using TI's SN74ACT8847 64-bit VLSI floating-point units for processing elements. The array processor can operate four different modes of operation: scalar, vector processor, full utilization, and simulated systolic. In full utilization mode, this array processor can sustain a 90-MFLOP computational rate. System software is also discussed, and attention is given to how it will be used with the SIGLAB programming environment.

entry:
@InProceedings{Dowling:1989:MVF,
  author =       "E. Dowling and M. Griffin and M. Lynch and F. Taylor",
  title =        "A multi-purpose {VLSI} floating-point array
                 processor",
  crossref =     "Chen:1989:TSA",
  pages =        "730--734 vol.2",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 3*3 single-instruction multiple-data (SIMD) array
                 processor for the IBM PC/AT is described. This array
                 processor is a modified bus-connected architecture
                 (MBCA) using TI's SN74ACT8847 64-bit VLSI
                 floating-point units for processing elements. The array
                 processor can operate four different modes of
                 operation: scalar, vector processor, full utilization,
                 and simulated systolic. In full utilization mode, this
                 array processor can sustain a 90-MFLOP computational
                 rate. System software is also discussed, and attention
                 is given to how it will be used with the SIGLAB
                 programming environment.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Electr. Eng., Florida University,
                 Gainesville, FL, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5220 (Computer architecture); C5430
                 (Microcomputers); C5440 (Multiprocessor systems and
                 techniques)",
  keywords =     "64 Bit; 90 MFLOPS; Full utilization mode; IBM PC/AT;
                 Modes of operation; Modified bus-connected
                 architecture; SIGLAB programming environment; SIMD;
                 Single-instruction multiple-data; SN74ACT8847; VLSI
                 floating-point array processor",
  numericalindex = "Word length 6.4E+01 bit; Computer speed 9.0E+07
                 FLOPS",
  thesaurus =    "CMOS integrated circuits; IBM computers;
                 Microcomputers; Microprocessor chips; Parallel
                 architectures; Parallel processing; VLSI",
}


bibtype: techreport
filename: fparith.bib
label: Dritz:1989:RPS
author: K. W. Dritz
title: Rationale for the Proposed Standard for a Generic Package of Elementary Functions for Ada
type: Report
number: ANL-89/2 Rev. 1
institution: Argonne National Laboratory, Mathematics and Computer Science Division
address: Argonne, IL, USA
month: oct
monthnumber: 10
year: 1989
bibdate: Thu Sep 01 12:08:24 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 12:08:24 ???
acknowledgement: ack-nj
rawauthor: K. W. Dritz
rawtitle: Rationale for the Proposed Standard for a Generic Package of Elementary Functions for {Ada}
entry:
@TechReport{Dritz:1989:RPS,
  author =       "K. W. Dritz",
  title =        "Rationale for the Proposed Standard for a Generic
                 Package of Elementary Functions for {Ada}",
  type =         "Report",
  number =       "ANL-89/2 Rev. 1",
  institution =  "Argonne National Laboratory, Mathematics and Computer
                 Science Division",
  address =      "Argonne, IL, USA",
  pages =        "??",
  month =        oct,
  year =         "1989",
  bibdate =      "Thu Sep 01 12:08:24 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Dunham:1989:ICA
author: C. B. Dunham
title: Improvement of complex arithmetic by use of double elements
journal: j-SIGNUM
volume: 24
number: 4
pages: 3--7
month: oct
monthnumber: 10
year: 1989
CODEN: SNEWD6
ISSN: 0163-5778 (print), 1558-0237 (electronic) OR 01635778 (print), 15580237 (electronic)
ISSNL: 0163-5778 OR 01635778
bibdate: Tue Apr 12 07:50:18 MDT 2005
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.12 07:50:18 MDT
fjournal: ACM SIGNUM Newsletter
keywords: algorithms; theory
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J690
rawauthor: C. B. Dunham
rawtitle: Improvement of complex arithmetic by use of double elements
subject:
G.1.3 Mathematics of Computing, NUMERICAL ANALYSIS, Numerical Linear Algebra, Matrix inversion G.1.0 Mathematics of Computing, NUMERICAL ANALYSIS, General, Computer arithmetic

entry:
@Article{Dunham:1989:ICA,
  author =       "C. B. Dunham",
  title =        "Improvement of complex arithmetic by use of double
                 elements",
  journal =      j-SIGNUM,
  volume =       "24",
  number =       "4",
  pages =        "3--7",
  month =        oct,
  year =         "1989",
  CODEN =        "SNEWD6",
  ISSN =         "0163-5778 (print), 1558-0237 (electronic)",
  ISSN-L =       "0163-5778",
  bibdate =      "Tue Apr 12 07:50:18 MDT 2005",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGNUM Newsletter",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J690",
  keywords =     "algorithms; theory",
  subject =      "G.1.3 Mathematics of Computing, NUMERICAL ANALYSIS,
                 Numerical Linear Algebra, Matrix inversion \\ G.1.0
                 Mathematics of Computing, NUMERICAL ANALYSIS, General,
                 Computer arithmetic",
}


bibtype: article
filename: fparith.bib
label: Dunham:1989:PAH
author: C. B. Dunham
title: Perturbation Analysis of Horner's Method for Nice Cases
journal: j-SIGNUM
volume: 24
number: 2 and 3
pages: 8--9
month: apr
monthnumber: 4
year: 1989
CODEN: SNEWD6
ISSN: 0163-5778 (print), 1558-0237 (electronic) OR 01635778 (print), 15580237 (electronic)
ISSNL: 0163-5778 OR 01635778
bibdate: Thu Sep 1 10:15:41 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:15:41 ???
fjournal: ACM SIGNUM Newsletter
acknowledgement: ack-nj
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J690
rawauthor: C. B. Dunham
rawtitle: Perturbation Analysis of {Horner}'s Method for Nice Cases
entry:
@Article{Dunham:1989:PAH,
  author =       "C. B. Dunham",
  title =        "Perturbation Analysis of {Horner}'s Method for Nice
                 Cases",
  journal =      j-SIGNUM,
  volume =       "24",
  number =       "2 and 3",
  pages =        "8--9",
  month =        apr # "/" # jul,
  year =         "1989",
  CODEN =        "SNEWD6",
  ISSN =         "0163-5778 (print), 1558-0237 (electronic)",
  ISSN-L =       "0163-5778",
  bibdate =      "Thu Sep 1 10:15:41 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "ACM SIGNUM Newsletter",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J690",
}


bibtype: article
filename: fparith.bib
label: Dunham:1989:S
author: C. B. Dunham
title: Summation
journal: j-SIGNUM
volume: 24
number: 1
pages: 14--15
month: jan
monthnumber: 1
year: 1989
CODEN: SNEWD6
ISSN: 0163-5778 (print), 1558-0237 (electronic) OR 01635778 (print), 15580237 (electronic)
ISSNL: 0163-5778 OR 01635778
bibdate: Tue Sep 13 08:58:48 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.13 08:58:48 ???
fjournal: ACM SIGNUM Newsletter
keywords: accurate floating-point summation
acknowledgement: ack-nj
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J690
rawauthor: C. B. Dunham
rawtitle: Summation
entry:
@Article{Dunham:1989:S,
  author =       "C. B. Dunham",
  title =        "Summation",
  journal =      j-SIGNUM,
  volume =       "24",
  number =       "1",
  pages =        "14--15",
  month =        jan,
  year =         "1989",
  CODEN =        "SNEWD6",
  ISSN =         "0163-5778 (print), 1558-0237 (electronic)",
  ISSN-L =       "0163-5778",
  bibdate =      "Tue Sep 13 08:58:48 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "ACM SIGNUM Newsletter",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J690",
  keywords =     "accurate floating-point summation",
}


bibtype: inproceedings
filename: fparith.bib
label: Duprat:1989:SRA
author: Jean Duprat and Yves Herreros and Jean-Michel Muller
title: Some results about on-line computation of functions
crossref: Ercegovac:1989:PSC
pages: 112--118
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Duprat.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Jean Duprat and Yves Herreros and Jean-Michel Muller
rawtitle: Some results about on-line computation of functions
entry:
@InProceedings{Duprat:1989:SRA,
  author =       "Jean Duprat and Yves Herreros and Jean-Michel Muller",
  title =        "Some results about on-line computation of functions",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "112--118",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Duprat.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Elleithy:1989:ARA
author: K. M. Elleithy and M. A. Bayoumi and K. P. Lee
title: $ theta (log N) $ architectures for RNS arithmetic decoding
crossref: Ercegovac:1989:PSC
pages: 202--209
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Elleithy.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: K. M. Elleithy and M. A. Bayoumi and K. P. Lee
rawtitle: {$ \theta (\log N) $} architectures for {RNS} arithmetic decoding
entry:
@InProceedings{Elleithy:1989:ARA,
  author =       "K. M. Elleithy and M. A. Bayoumi and K. P. Lee",
  title =        "{$ \theta (\log N) $} architectures for {RNS}
                 arithmetic decoding",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "202--209",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Elleithy.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Ercegovac:1989:FRD
author: M. D. Ercegovac and T. Lang
title: On-the-fly rounding for division and square root
crossref: Ercegovac:1989:PSC
pages: 169--173
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Ercegovac_rounding.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: M. D. Ercegovac and T. Lang
rawtitle: On-the-fly rounding for division and square root
entry:
@InProceedings{Ercegovac:1989:FRD,
  author =       "M. D. Ercegovac and T. Lang",
  title =        "On-the-fly rounding for division and square root",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "169--173",
  year =         "1989",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Ercegovac_rounding.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
  summary =      "In division and square root implementation based on
                 digit-recurrence algorithms, the result is obtained in
                 digit-serial form, from most significant digit to least
                 significant. To reduce the complexity of the
                 result-digit selection and to allow the \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Ercegovac:1989:FSC
author: Milos D. Ercegovac and Algirdas Avizienis and Earl Swartzlander
title: Foreword: 9th Symposium on Computer Arithmetic (ARITH9)
crossref: Ercegovac:1989:PSC
pages: v--v
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Milo{\v{s}} D. Ercegovac and Algirdas Avi{\v{z}}ienis and Earl Swartzlander
rawtitle: Foreword: {9th Symposium on Computer Arithmetic (ARITH9)}
URL:
http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_contents.pdf; http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_foreword.pdf; http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_preface.pdf

entry:
@InProceedings{Ercegovac:1989:FSC,
  author =       "Milo{\v{s}} D. Ercegovac and Algirdas Avi{\v{z}}ienis
                 and Earl Swartzlander",
  title =        "Foreword: {9th Symposium on Computer Arithmetic
                 (ARITH9)}",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "v--v",
  year =         "1989",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_contents.pdf;
                 http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_foreword.pdf;
                 http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_preface.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Ercegovac:1989:IMC
author: M. D. Ercegovac and T. Lang
booktitle: IEEE International Symposium on Circuits and Systems, 8--11 May 1989
title: Implementation of module combining multiplication, division, and square root
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 150--153
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
acknowledgement: ack-nhfb
rawauthor: M. D. Ercegovac and T. Lang
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, 8--11 May 1989
rawtitle: Implementation of module combining multiplication, division, and square root
entry:
@InProceedings{Ercegovac:1989:IMC,
  author =       "M. D. Ercegovac and T. Lang",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, 8--11 May 1989",
  title =        "Implementation of module combining multiplication,
                 division, and square root",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "150--153",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The implementation of a module that performs radix-$2$
                 multiplication, division, and square root is presented.
                 The module is compact because most of the components
                 are shared by all three operations, the complexity
                 being similar to that of a radix-$2$ \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Ercegovac:1989:RSR
author: Milos D. Ercegovac and Tomas Lang
title: Radix-4 square root without initial PLA
crossref: Ercegovac:1989:PSC
pages: 162--168
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Ercegovac_radix4.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Milo{\v{s}} D. Ercegovac and Tomas Lang
rawtitle: Radix-4 square root without initial {PLA}
entry:
@InProceedings{Ercegovac:1989:RSR,
  author =       "Milo{\v{s}} D. Ercegovac and Tomas Lang",
  title =        "Radix-4 square root without initial {PLA}",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "162--168",
  year =         "1989",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Ercegovac_radix4.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
  summary =      "A systematic derivation of a radix-$4$ square root
                 algorithm using redundance in the partial residuals and
                 the result is presented. Unlike other similar schemes,
                 the algorithm does not use a table-lookup or
                 programmable logic array (PLA) for the \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Fandrianto:1989:AHS
author: Jan Fandrianto
title: Algorithms for high-speed shared radix 8 division and radix 8 square root
crossref: Ercegovac:1989:PSC
pages: 68--75
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Fandrianto.pdf
keywords: ARITH-9
acknowledgement: ack-sfo
rawauthor: Jan Fandrianto
rawtitle: Algorithms for high-speed shared radix 8 division and radix 8 square root
entry:
@InProceedings{Fandrianto:1989:AHS,
  author =       "Jan Fandrianto",
  title =        "Algorithms for high-speed shared radix 8 division and
                 radix 8 square root",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "68--75",
  year =         "1989",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Fandrianto.pdf",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
  keywords =     "ARITH-9",
  summary =      "An algorithm for performing radix-$8$ division and
                 square root in a shared hardware is described. To
                 achieve short iteration cycle time, it utilizes an
                 optimized `next quotient/root prediction PLA' generally
                 used in a radix-$4$ SRT division with minimal
                 \ldots{}",
}


bibtype: inbook
filename: fparith.bib
label: Feldstein:1989:NAP
author: Alan Feldstein and Richard H. Goodman
title: Some aspects of floating point computation
crossref: Turner:1989:NAP
pages: 169--181
year: 1989
DOI: https://doi.org/10.1007/BFb0085718
MRclass: 65G05
MRnumber: 022 264
bibdate: Fri Dec 8 08:24:14 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:14 ???
acknowledgement: ack-nhfb
rawauthor: Alan Feldstein and Richard H. Goodman
rawtitle: Some aspects of floating point computation
abstract:
The floating point format is widely used in computing because it allows for the representation of numbers with greatly varying magnitude. This paper introduces some general aspects of floating point representation and includes a discussion of the implications of balanced and unbalanced exponent ranges. A statistical approach is presented in order to analyze the error in floating point computations. The shortening of computer words is discussed and is applied to study aspects of the fraction error and the relative error.

rawabstract:
The floating point format is widely used in computing because it allows for the representation of numbers with greatly varying magnitude. This paper introduces some general aspects of floating point representation and includes a discussion of the implications of balanced and unbalanced exponent ranges. A statistical approach is presented in order to analyze the error in floating point computations. The shortening of computer words is discussed and is applied to study aspects of the fraction error and the relative error.

entry:
@InBook{Feldstein:1989:NAP,
  author =       "Alan Feldstein and Richard H. Goodman",
  title =        "Some aspects of floating point computation",
  crossref =     "Turner:1989:NAP",
  pages =        "169--181",
  year =         "1989",
  DOI =          "https://doi.org/10.1007/BFb0085718",
  MRclass =      "65G05",
  MRnumber =     "022 264",
  bibdate =      "Fri Dec 8 08:24:14 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The floating point format is widely used in computing
                 because it allows for the representation of numbers
                 with greatly varying magnitude. This paper introduces
                 some general aspects of floating point representation
                 and includes a discussion of the implications of
                 balanced and unbalanced exponent ranges. A statistical
                 approach is presented in order to analyze the error in
                 floating point computations. The shortening of computer
                 words is discussed and is applied to study aspects of
                 the fraction error and the relative error.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Fowler:1989:AHS
author: D. L. Fowler and J. E. Smith
title: An accurate, high speed implementation of division by reciprocal approximation
crossref: Ercegovac:1989:PSC
pages: 60--67
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Fowler.pdf
acknowledgement: ack-nhfb
affiliation: Astronaut. Corp. of America, Madison, WI, USA
bookpages: xv + 247
thesaurus: Digital arithmetic; Interpolation; Table lookup
rawauthor: D. L. Fowler and J. E. Smith
rawtitle: An accurate, high speed implementation of division by reciprocal approximation
abstract:
While unlimited accuracy is theoretically possible, it is very important to minimize the number of iteration steps to improve performance and/or to reduce hardware requirements. Consequently, there is an important accuracy/speed/cost tradeoff in reciprocal approximation implementations. A reciprocal approximation implementation is discussed, with special attention given to these tradeoffs. An interpolation method is used to ensure that an initial approximation, held in a ROM table, is as accurate as possible. A method for implementing the iteration steps is given. Special instructions are used so that maximum accuracy can be carried between iteration operations. For 64-b floating-point operands (53-b mantissa), a table lookup and only two iterations are required, and high accuracy is maintained. The rounded reciprocal rarely differs from a true round-to-nearest value based on an infinite precision result. When the results do differ (less than once every 1000 calculations), the difference in accuracy is shown to be less than 0.025 of a least significant bit (LSB).

keywords:
ARITH-9; Division; Hardware requirements; High speed implementation; Interpolation; Reciprocal approximation; ROM table; Rounded reciprocal; Table lookup

rawabstract:
While unlimited accuracy is theoretically possible, it is very important to minimize the number of iteration steps to improve performance and/or to reduce hardware requirements. Consequently, there is an important accuracy/speed/cost tradeoff in reciprocal approximation implementations. A reciprocal approximation implementation is discussed, with special attention given to these tradeoffs. An interpolation method is used to ensure that an initial approximation, held in a ROM table, is as accurate as possible. A method for implementing the iteration steps is given. Special instructions are used so that maximum accuracy can be carried between iteration operations. For 64-b floating-point operands (53-b mantissa), a table lookup and only two iterations are required, and high accuracy is maintained. The rounded reciprocal rarely differs from a true round-to-nearest value based on an infinite precision result. When the results do differ (less than once every 1000 calculations), the difference in accuracy is shown to be less than 0.025 of a least significant bit (LSB).

entry:
@InProceedings{Fowler:1989:AHS,
  author =       "D. L. Fowler and J. E. Smith",
  title =        "An accurate, high speed implementation of division by
                 reciprocal approximation",
  crossref =     "Ercegovac:1989:PSC",
  bookpages =    "xv + 247",
  pages =        "60--67",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Fowler.pdf",
  abstract =     "While unlimited accuracy is theoretically possible, it
                 is very important to minimize the number of iteration
                 steps to improve performance and/or to reduce hardware
                 requirements. Consequently, there is an important
                 accuracy/speed/cost tradeoff in reciprocal
                 approximation implementations. A reciprocal
                 approximation implementation is discussed, with special
                 attention given to these tradeoffs. An interpolation
                 method is used to ensure that an initial approximation,
                 held in a ROM table, is as accurate as possible. A
                 method for implementing the iteration steps is given.
                 Special instructions are used so that maximum accuracy
                 can be carried between iteration operations. For 64-b
                 floating-point operands (53-b mantissa), a table lookup
                 and only two iterations are required, and high accuracy
                 is maintained. The rounded reciprocal rarely differs
                 from a true round-to-nearest value based on an infinite
                 precision result. When the results do differ (less than
                 once every 1000 calculations), the difference in
                 accuracy is shown to be less than 0.025 of a least
                 significant bit (LSB).",
  acknowledgement = ack-nhfb,
  affiliation =  "Astronaut. Corp. of America, Madison, WI, USA",
  classification = "C4130 (Interpolation and function approximation);
                 C5230 (Digital arithmetic methods); C6130 (Data
                 handling techniques)",
  confdate =     "6-8 Sept. 1989",
  conflocation = "Santa Monica, CA, USA",
  confsponsor =  "IEEE; IFIP; University of California",
  keywords =     "ARITH-9; Division; Hardware requirements; High speed
                 implementation; Interpolation; Reciprocal
                 approximation; ROM table; Rounded reciprocal; Table
                 lookup",
  thesaurus =    "Digital arithmetic; Interpolation; Table lookup",
}


bibtype: article
filename: fparith.bib
label: Fried:1989:ONC
author: S. Fried
title: Optimizing numeric coprocessing
journal: j-BYTE
volume: 14
number: 11
pages: 221--224
year: 1989
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Thu Sep 12 17:47:21 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.09.12 17:47:21 MDT
fjournal: BYTE Magazine
acknowledgement: ack-nhfb
thesaurus: Computer testing; Digital arithmetic; Performance evaluation; Satellite computers
rawauthor: S. Fried
rawtitle: Optimizing numeric coprocessing
keywords:
Addition; Compiler optimizations; CPU code; Floating-point operations; Multiplication; Numeric coprocessing; Optimisation; Weitek 3167

entry:
@Article{Fried:1989:ONC,
  author =       "S. Fried",
  title =        "Optimizing numeric coprocessing",
  journal =      j-BYTE,
  volume =       "14",
  number =       "11",
  pages =        "221--224",
  month =        "????",
  year =         "1989",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Thu Sep 12 17:47:21 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "C5230 (Digital arithmetic methods); C5470
                 (Performance evaluation and testing)",
  fjournal =     "BYTE Magazine",
  keywords =     "Addition; Compiler optimizations; CPU code;
                 Floating-point operations; Multiplication; Numeric
                 coprocessing; Optimisation; Weitek 3167",
  thesaurus =    "Computer testing; Digital arithmetic; Performance
                 evaluation; Satellite computers",
}


bibtype: inproceedings
filename: fparith.bib
label: Fu:1989:PMI
author: B. Fu and A. Saini and P. P. Gelsinger
title: Performance and Microarchitecture of the i486TM Processor
crossref: IEEE:1989:PII
pages: 182--187
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Intel Corp., Santa Clara, CA, USA
thesaurus: Microprocessor chips
rawauthor: B. Fu and A. Saini and P. P. Gelsinger
rawtitle: Performance and Microarchitecture of the i486{\TM} Processor
abstract:
The i486 microprocessor includes a carefully tuned, five-stage pipeline with an integrated 8-kB cache. A variety of techniques previously associated only with RISC (reduced-instruction-set computer) processors are used to execute the average instruction in 1.8 clocks. This represents a 2.5* reduction from its predecessor, the 386 microprocessor. The pipeline and clock count comparisons are described in detail. In addition, an onchip floating-point unit is included which yields a 4* clock count reduction from the 387 numeric coprocessor. The microarchitecture enhancements and optimizations used to achieve this goal, most of which are non-silicon-intensive, are discussed. All instructions of the 386 microprocessor and the 387 numeric coprocessor are implemented in a completely compatible fashion.

keywords:
386 Microprocessor; 387 Numeric coprocessor; Clock count; Five-stage pipeline; I486 processor; Intel; Microarchitecture; Onchip floating-point unit; Performance

rawabstract:
The i486 microprocessor includes a carefully tuned, five-stage pipeline with an integrated 8-kB cache. A variety of techniques previously associated only with RISC (reduced-instruction-set computer) processors are used to execute the average instruction in 1.8 clocks. This represents a 2.5* reduction from its predecessor, the 386 microprocessor. The pipeline and clock count comparisons are described in detail. In addition, an onchip floating-point unit is included which yields a 4* clock count reduction from the 387 numeric coprocessor. The microarchitecture enhancements and optimizations used to achieve this goal, most of which are non-silicon-intensive, are discussed. All instructions of the 386 microprocessor and the 387 numeric coprocessor are implemented in a completely compatible fashion.

entry:
@InProceedings{Fu:1989:PMI,
  author =       "B. Fu and A. Saini and P. P. Gelsinger",
  title =        "Performance and Microarchitecture of the i486{\TM}
                 Processor",
  crossref =     "IEEE:1989:PII",
  pages =        "182--187",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The i486 microprocessor includes a carefully tuned,
                 five-stage pipeline with an integrated 8-kB cache. A
                 variety of techniques previously associated only with
                 RISC (reduced-instruction-set computer) processors are
                 used to execute the average instruction in 1.8 clocks.
                 This represents a 2.5* reduction from its predecessor,
                 the 386 microprocessor. The pipeline and clock count
                 comparisons are described in detail. In addition, an
                 onchip floating-point unit is included which yields a
                 4* clock count reduction from the 387 numeric
                 coprocessor. The microarchitecture enhancements and
                 optimizations used to achieve this goal, most of which
                 are non-silicon-intensive, are discussed. All
                 instructions of the 386 microprocessor and the 387
                 numeric coprocessor are implemented in a completely
                 compatible fashion.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Intel Corp., Santa Clara, CA, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips)",
  confdate =     "2-4 Oct. 1989",
  conflocation = "Cambridge, MA, USA",
  confsponsor =  "IEEE",
  keywords =     "386 Microprocessor; 387 Numeric coprocessor; Clock
                 count; Five-stage pipeline; I486 processor; Intel;
                 Microarchitecture; Onchip floating-point unit;
                 Performance",
  thesaurus =    "Microprocessor chips",
}


bibtype: article
filename: fparith.bib
label: Fujiyama:1989:FD
author: T. Fujiyama and Y. Shimazu and T. Tokuda and S. Tsujimichi
title: A 24-bit floating-point DSP
journal: Mitsubishi Denki Giho
volume: 63
number: 12
pages: 59--62
year: 1989
ISSN: 0369-2302 OR 03692302
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
language: Japanese
acknowledgement: ack-nhfb
affiliation: Mitsubishi Electr. Corp., Tokyo, Japan
thesaurus: Computerised signal processing; Digital signal processing chips
rawauthor: T. Fujiyama and Y. Shimazu and T. Tokuda and S. Tsujimichi
rawtitle: A 24-bit floating-point {DSP}
abstract:
The authors report on a new high-speed 24-bit floating point DSP (digital signal processor) and its development tools. The DSP features a short 75 ns instruction cycle and low 750 mW power dissipation. Other features include a large memory space, internal RAM that can be configured as a cache, and speed control via an internal clock prescaler that is accessed by a special instruction. The DSP is suitable for application in audio and image processing, communications and numerical control.

keywords:
24 Bit; 24-Bit floating-point DSP; 75 Ns; 750 MW; Audio processing; Communications; Development; Digital signal processor; DSP chips; Image processing; Instruction cycle; Internal clock prescaler; Memory; Numerical control; Power dissipation; RAM; Speed control

rawabstract:
The authors report on a new high-speed 24-bit floating point DSP (digital signal processor) and its development tools. The DSP features a short 75 ns instruction cycle and low 750 mW power dissipation. Other features include a large memory space, internal RAM that can be configured as a cache, and speed control via an internal clock prescaler that is accessed by a special instruction. The DSP is suitable for application in audio and image processing, communications and numerical control.

entry:
@Article{Fujiyama:1989:FD,
  author =       "T. Fujiyama and Y. Shimazu and T. Tokuda and S.
                 Tsujimichi",
  title =        "A 24-bit floating-point {DSP}",
  journal =      "Mitsubishi Denki Giho",
  volume =       "63",
  number =       "12",
  pages =        "59--62",
  month =        "????",
  year =         "1989",
  ISSN =         "0369-2302",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The authors report on a new high-speed 24-bit floating
                 point DSP (digital signal processor) and its
                 development tools. The DSP features a short 75 ns
                 instruction cycle and low 750 mW power dissipation.
                 Other features include a large memory space, internal
                 RAM that can be configured as a cache, and speed
                 control via an internal clock prescaler that is
                 accessed by a special instruction. The DSP is suitable
                 for application in audio and image processing,
                 communications and numerical control.",
  acknowledgement = ack-nhfb,
  affiliation =  "Mitsubishi Electr. Corp., Tokyo, Japan",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5260 (Digital signal
                 processing)",
  keywords =     "24 Bit; 24-Bit floating-point DSP; 75 Ns; 750 MW;
                 Audio processing; Communications; Development; Digital
                 signal processor; DSP chips; Image processing;
                 Instruction cycle; Internal clock prescaler; Memory;
                 Numerical control; Power dissipation; RAM; Speed
                 control",
  language =     "Japanese",
  numericalindex = "Power 7.5E-01 W; Time 7.5E-08 s; Word length 2.4E+01
                 bit",
  pubcountry =   "Japan",
  thesaurus =    "Computerised signal processing; Digital signal
                 processing chips",
}


bibtype: inproceedings
filename: fparith.bib
label: Gamberger:1989:ISN
author: D. Gamberger
title: Incompletely specified numbers in the residue number system-definition and applications
crossref: Ercegovac:1989:PSC
pages: 210--215
year: 1989
DOI: https://doi.org/10.1109/ARITH.1989.72828
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Gamberger.pdf
keywords: ARITH-9; residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: D. Gamberger
rawtitle: Incompletely specified numbers in the residue number system-definition and applications
entry:
@InProceedings{Gamberger:1989:ISN,
  author =       "D. Gamberger",
  title =        "Incompletely specified numbers in the residue number
                 system-definition and applications",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "210--215",
  year =         "1989",
  DOI =          "https://doi.org/10.1109/ARITH.1989.72828",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Gamberger.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9; residue arithmetic; residue number system",
  summary =      "Incompletely specified numbers in the residue number
                 system (RNS) are defined in order to make
                 multiplicative inverse computation of a number
                 regardless of its magnitude possible. Incompletely
                 specified RNS is the general RNS model in which
                 \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Games:1989:AIQ
author: R. A. Games and D. Moulin and S. D. O'Neil and J. J. Rushanan
booktitle: International Conference on Acoustics, Speech, and Signal Processing, ICASSP-89, 23--26 May 1989
title: Algebraic-integer quantization an residue number system processing
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 948--951
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266586
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: R. A. Games and D. Moulin and S. D. O'Neil and J. J. Rushanan
rawbooktitle: International Conference on Acoustics, Speech, and Signal Processing, {ICASSP-89, 23--26} May 1989
rawtitle: Algebraic-integer quantization an residue number system processing
entry:
@InProceedings{Games:1989:AIQ,
  author =       "R. A. Games and D. Moulin and S. D. O'Neil and J. J.
                 Rushanan",
  booktitle =    "International Conference on Acoustics, Speech, and
                 Signal Processing, {ICASSP-89, 23--26} May 1989",
  title =        "Algebraic-integer quantization an residue number
                 system processing",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "948--951",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266586",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The algebraic-integer number representation, in which
                 the signal sample is represented by a set of (typically
                 four to eight) small integers, combines with residue
                 number system (RNS) processing to produce processors
                 composed of simple parallel \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Goel:1989:RTA
author: B. D. Goel and M. M. Jamali and S. C. Kwatra
booktitle: IEEE International Symposium on Circuits and Systems, 8--11 May 1989
title: Real time architecture for vector quantization in residue number system
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 204--207
year: 1989
DOI: https://doi.org/10.1109/ISCAS.1989.100327
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: B. D. Goel and M. M. Jamali and S. C. Kwatra
rawbooktitle: {IEEE} International Symposium on Circuits and Systems, 8--11 May 1989
rawtitle: Real time architecture for vector quantization in residue number system
entry:
@InProceedings{Goel:1989:RTA,
  author =       "B. D. Goel and M. M. Jamali and S. C. Kwatra",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems, 8--11 May 1989",
  title =        "Real time architecture for vector quantization in
                 residue number system",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "204--207",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.1989.100327",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A fast and simplified systolic array architecture for
                 real-time implementation of vector quantization is
                 proposed. The proposed architecture uses the residue
                 number system (RNS) for arithmetic operations. The
                 arithmetic operations can be precomputed \ldots{}",
}


bibtype: techreport
filename: fparith.bib
label: Goldberg:1989:FCS
author: David Goldberg
title: Floating-point and computer systems
type: Technical report
number: CSL-89-9
institution: Xerox Corp., Palo Alto Research Center
address: Palo Alto, CA, USA
pages: 58
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Floating-point arithmetic.
remark: ``August 1989.'' ``A version of this paper will appear in Computing Surveys.''
acknowledgement: ack-nhfb
rawauthor: David Goldberg
rawtitle: Floating-point and computer systems
entry:
@TechReport{Goldberg:1989:FCS,
  author =       "David Goldberg",
  title =        "Floating-point and computer systems",
  type =         "Technical report",
  number =       "CSL-89-9",
  institution =  "Xerox Corp., Palo Alto Research Center",
  address =      "Palo Alto, CA, USA",
  pages =        "58",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Floating-point arithmetic.",
  remark =       "``August 1989.'' ``A version of this paper will appear
                 in Computing Surveys.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Gonnella:1989:ACF
author: J. Gonnella and J. Periard
title: The application of core functions to residue number system signal processing
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 604--608
year: 1989
DOI: https://doi.org/10.1109/MILCOM.1989.103996
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: J. Gonnella and J. Periard
rawtitle: The application of core functions to residue number system signal processing
booktitle:
IEEE Military Communications Conference, 1989. MILCOM '89. Conference Record. Bridging the Gap. Interoperability, Survivability, Security, 1989

rawbooktitle:
{IEEE} Military Communications Conference, 1989. {MILCOM '89}. Conference Record. Bridging the Gap. Interoperability, Survivability, Security, 1989

entry:
@InProceedings{Gonnella:1989:ACF,
  author =       "J. Gonnella and J. Periard",
  booktitle =    "{IEEE} Military Communications Conference, 1989.
                 {MILCOM '89}. Conference Record. Bridging the Gap.
                 Interoperability, Survivability, Security, 1989",
  title =        "The application of core functions to residue number
                 system signal processing",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "604--608",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MILCOM.1989.103996",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The authors briefly outline core-based residue number
                 system (RNS) processing. An RNS adaptive array
                 processor using Choleski decomposition and forward
                 elimination/back substitution is described as an
                 example. The RNS adaptive processor was \ldots{}",
}


bibtype: mastersthesis
filename: fparith.bib
label: Gordon:1989:RDF
author: Stephen E. Gordon
type: Thesis (M.S.E.C.E.)
school: University of Massachusetts at Amherst
address: Amherst, MA, USA
pages: xi + 123
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Digital filters (Mathematics)
acknowledgement: ack-nhfb
rawauthor: Stephen E. Gordon
title:
Recursive digital filtering with digital differential analyzers and floating point incremental coders

rawtitle:
Recursive digital filtering with digital differential analyzers and floating point incremental coders

entry:
@MastersThesis{Gordon:1989:RDF,
  author =       "Stephen E. Gordon",
  title =        "Recursive digital filtering with digital differential
                 analyzers and floating point incremental coders",
  type =         "Thesis ({M.S.E.C.E.})",
  school =       "University of Massachusetts at Amherst",
  address =      "Amherst, MA, USA",
  pages =        "xi + 123",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Digital filters (Mathematics)",
}


bibtype: article
filename: fparith.bib
label: Grassmann:1989:PAR
author: Winfried K. Grassmann
journal: j-CONG-NUM
volume: 68
pages: 171--182
year: 1989
ISSN: 0384-9864 OR 03849864
MRclass: 65G05
MRnumber: 90d:65089
bibdate: Fri Dec 8 08:24:13 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:13 ???
fjournal: Congressus Numerantium
acknowledgement: ack-nhfb
rawauthor: Winfried K. Grassmann
title:
A probabilistic analysis of rounding errors of floating point numbers. Eighteenth Manitoba Conference on Numerical Mathematics and Computing (Winnipeg, MB, 1988)

rawtitle:
A probabilistic analysis of rounding errors of floating point numbers. {Eighteenth Manitoba Conference on Numerical Mathematics and Computing (Winnipeg, MB, 1988)}

entry:
@Article{Grassmann:1989:PAR,
  author =       "Winfried K. Grassmann",
  title =        "A probabilistic analysis of rounding errors of
                 floating point numbers. {Eighteenth Manitoba Conference
                 on Numerical Mathematics and Computing (Winnipeg, MB,
                 1988)}",
  journal =      j-CONG-NUM,
  volume =       "68",
  pages =        "171--182",
  year =         "1989",
  ISSN =         "0384-9864",
  MRclass =      "65G05",
  MRnumber =     "90d:65089",
  bibdate =      "Fri Dec 8 08:24:13 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Congressus Numerantium",
}


bibtype: article
filename: fparith.bib
label: Grehan:1989:FPR
author: R. Grehan
title: Floating-Point Revisited
journal: j-BYTE
volume: 14
number: 4
pages: 311--318
month: apr
monthnumber: 4
year: 1989
CODEN: BYTEDJ
ISSN: 0360-5280 (print), 1082-7838 (electronic) OR 03605280 (print), 10827838 (electronic)
ISSNL: 0360-5280 OR 03605280
bibdate: Thu Sep 1 10:15:05 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:15:05 ???
fjournal: BYTE Magazine
acknowledgement: ack-nj
rawauthor: R. Grehan
rawtitle: Floating-Point Revisited
entry:
@Article{Grehan:1989:FPR,
  author =       "R. Grehan",
  title =        "Floating-Point Revisited",
  journal =      j-BYTE,
  volume =       "14",
  number =       "4",
  pages =        "311--318",
  month =        apr,
  year =         "1989",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280 (print), 1082-7838 (electronic)",
  ISSN-L =       "0360-5280",
  bibdate =      "Thu Sep 1 10:15:05 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "BYTE Magazine",
}


bibtype: inproceedings
filename: fparith.bib
label: Griffin:1989:ESR
author: M. Griffin and M. Sousa and F. Taylor
booktitle: International Conference on Acoustics, Speech, and Signal Processing, ICASSP-89, 23--26 May 1989
title: Efficient scaling in the residue number system
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1075--1078
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266618
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. Griffin and M. Sousa and F. Taylor
rawbooktitle: International Conference on Acoustics, Speech, and Signal Processing, {ICASSP-89, 23--26} May 1989
rawtitle: Efficient scaling in the residue number system
entry:
@InProceedings{Griffin:1989:ESR,
  author =       "M. Griffin and M. Sousa and F. Taylor",
  booktitle =    "International Conference on Acoustics, Speech, and
                 Signal Processing, {ICASSP-89, 23--26} May 1989",
  title =        "Efficient scaling in the residue number system",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1075--1078",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266618",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A unified residue number system scaling technique that
                 allows the designer a great deal of flexibility in
                 choosing the scale factor is presented. The technique
                 is based on the L({\&}epsi;+{\delta})-CRT (Chinese
                 remainder theorem). By embedding \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Griffin:1989:RNS
author: M. F. Griffin and F. J. Taylor
booktitle: International Conference on Acoustics, Speech, and Signal Processing, ICASSP-89, 23--26 May 1989
title: A residue number system reduced instruction set computer (RISC) concept
volume: 4
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 2581--2584
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266995
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. F. Griffin and F. J. Taylor
rawbooktitle: International Conference on Acoustics, Speech, and Signal Processing, {ICASSP-89, 23--26} May 1989
rawtitle: A residue number system reduced instruction set computer ({RISC}) concept
entry:
@InProceedings{Griffin:1989:RNS,
  author =       "M. F. Griffin and F. J. Taylor",
  booktitle =    "International Conference on Acoustics, Speech, and
                 Signal Processing, {ICASSP-89, 23--26} May 1989",
  title =        "A residue number system reduced instruction set
                 computer ({RISC}) concept",
  volume =       "4",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2581--2584",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266995",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A reduced-instruction-set RNS (residue number system)
                 processor is proposed for digital signal processing
                 algorithms. Issues leading toward a RNS RISC are
                 examined, namely suitable RNS algorithms. It is argued
                 that this is a reasonable next step in \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Groeger:1989:DRG
author: Detlef Groger
journal: j-MATH-SEMESTERBER
volume: 36
number: 1
pages: 106--111
year: 1989
ISSN: 0720-728x (print), 1432-1815 (electronic) OR 0720728x (print), 14321815 (electronic)
ISSNL: 0720-728X OR 0720728X
MRclass: 65G99 (11Y16)
MRnumber: 90g:65070
bibdate: Fri Dec 8 08:24:13 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.08 08:24:13 ???
fjournal: Mathematische Semesterberichte
language: German
acknowledgement: ack-nhfb
rawauthor: Detlef Gr{\"o}ger
title:
Zur Division mit Rest auf Gleitkommarechnern. (German) [On division with remainder on floating point computers]

rawtitle:
{Zur Division mit Rest auf Gleitkommarechnern. (German)} [On division with remainder on floating point computers]

entry:
@Article{Groeger:1989:DRG,
  author =       "Detlef Gr{\"o}ger",
  title =        "{Zur Division mit Rest auf Gleitkommarechnern.
                 (German)} [On division with remainder on floating point
                 computers]",
  journal =      j-MATH-SEMESTERBER,
  volume =       "36",
  number =       "1",
  pages =        "106--111",
  year =         "1989",
  ISSN =         "0720-728x (print), 1432-1815 (electronic)",
  ISSN-L =       "0720-728X",
  MRclass =      "65G99 (11Y16)",
  MRnumber =     "90g:65070",
  bibdate =      "Fri Dec 8 08:24:13 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Mathematische Semesterberichte",
  language =     "German",
}


bibtype: inproceedings
filename: fparith.bib
label: Guyot:1989:JLM
author: Alain Guyot and Bertrand Hochet and Jean-Michel Muller
title: JANUS, an on-line multiplier / divider for manipulating large numbers
crossref: Ercegovac:1989:PSC
pages: 106--111
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Guyot.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Alain Guyot and Bertrand Hochet and Jean-Michel Muller
rawtitle: {JANUS}, an on-line multiplier\slash divider for manipulating large numbers
entry:
@InProceedings{Guyot:1989:JLM,
  author =       "Alain Guyot and Bertrand Hochet and Jean-Michel
                 Muller",
  title =        "{JANUS}, an on-line multiplier\slash divider for
                 manipulating large numbers",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "106--111",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Guyot.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: article
filename: fparith.bib
label: Hoffmann:1989:PAR
author: C. M. Hoffmann
title: The Problems of Accuracy and Robustness in Geometric Computation
journal: j-COMPUTER
volume: 22
number: 3
institution: Purdue U
pages: 31--39, 41
month: mar
monthnumber: 3
year: 1989
CODEN: CPTRB4
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Sat Sep 14 07:29:35 MDT 1996
bibsource: Graphics/rosenfeld/1989.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; Misc/IMMD_IV.bib
bibtimestamp: 1996.09.14 07:29:35 MDT
fjournal: Computer
acknowledgement: ack-nhfb
affiliation: Computer Science Dept., Purdue University, West Lafayette, IN, USA
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
thesaurus: Computational geometry
rawauthor: C. M. Hoffmann
rawtitle: The Problems of Accuracy and Robustness in Geometric Computation
keywords:
Accuracy; Degeneracies avoidance; Degenerate positions; Floating-point computation; Geometric computation; Geometric operations; Interacting numeric data; Interacting symbolic data; Limited-precision rational arithmetic; Linear elements; Model, IMAGE PART MEASUREMENT; Numerical precision; Perturbation-free methods; Purely symbolic representations; Representation; Robustness; Symbolic data alteration

entry:
@Article{Hoffmann:1989:PAR,
  author =       "C. M. Hoffmann",
  title =        "The Problems of Accuracy and Robustness in Geometric
                 Computation",
  journal =      j-COMPUTER,
  volume =       "22",
  number =       "3",
  institution =  "Purdue U",
  pages =        "31--39, 41",
  month =        mar,
  year =         "1989",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Sat Sep 14 07:29:35 MDT 1996",
  bibsource =    "Graphics/rosenfeld/1989.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Misc/IMMD_IV.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Computer Science Dept., Purdue University, West
                 Lafayette, IN, USA",
  classification = "C1160 (Combinatorial mathematics); C4190 (Other
                 numerical methods); C4290 (Other computer theory)",
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "Accuracy; Degeneracies avoidance; Degenerate
                 positions; Floating-point computation; Geometric
                 computation; Geometric operations; Interacting numeric
                 data; Interacting symbolic data; Limited-precision
                 rational arithmetic; Linear elements; Model, IMAGE PART
                 MEASUREMENT; Numerical precision; Perturbation-free
                 methods; Purely symbolic representations;
                 Representation; Robustness; Symbolic data alteration",
  thesaurus =    "Computational geometry",
}


bibtype: inproceedings
filename: fparith.bib
label: Hohne:1989:PHP
author: R. A. Hohne and R. Siferd
title: A programmable high performance processor using the residue number system and CMOS VLSI technology
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 41--43
year: 1989
DOI: https://doi.org/10.1109/NAECON.1989.40188
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: R. A. Hohne and R. Siferd
booktitle:
Proceedings of the IEEE 1989 National Aerospace and Electronics Conference, NAECON 1989, 22--26 May 1989

rawbooktitle:
Proceedings of the {IEEE 1989} National Aerospace and Electronics Conference, {NAECON 1989}, 22--26 May 1989

rawtitle:
A programmable high performance processor using the residue number system and {CMOS} {VLSI} technology

entry:
@InProceedings{Hohne:1989:PHP,
  author =       "R. A. Hohne and R. Siferd",
  booktitle =    "Proceedings of the {IEEE 1989} National Aerospace and
                 Electronics Conference, {NAECON 1989}, 22--26 May
                 1989",
  title =        "A programmable high performance processor using the
                 residue number system and {CMOS} {VLSI} technology",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "41--43",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/NAECON.1989.40188",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The authors describe the general architecture of RNS
                 (residue number system) processors, the VLSI
                 implementation of the associated hardware, and finally,
                 an RNS processor designed by the authors. The 2-{\mu}m
                 CMOS implementation of the processor \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Hollingsworth:1989:CPI
author: Walter Hollingsworth and Howard Sachs and Alan Jay Smith
title: The ClipperTM Processor: Instruction Set Architecture and Implementation
journal: j-CACM
volume: 32
number: 2
pages: 200--219
month: feb
monthnumber: 2
year: 1989
CODEN: CACMA2
ISSN: 0001-0782 (print), 1557-7317 (electronic) OR 00010782 (print), 15577317 (electronic)
ISSNL: 0001-0782 OR 00010782
bibdate: Mon Sep 26 13:49:15 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.26 13:49:15 ???
fjournal: Communications of the ACM
keywords: design; measurement; performance
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/cacm
rawauthor: Walter Hollingsworth and Howard Sachs and Alan Jay Smith
rawtitle: The {Clipper\TM} Processor: Instruction Set Architecture and Implementation
subject:
C.5.3 Computer Systems Organization, COMPUTER SYSTEM IMPLEMENTATION, Microcomputers, CLIPPER C.1.1 Computer Systems Organization, PROCESSOR ARCHITECTURES, Single Data Stream Architectures, Single-instruction-stream, single-data-stream processors (SISD) C.4 Computer Systems Organization, PERFORMANCE OF SYSTEMS C.0 Computer Systems Organization, GENERAL, Instruction set design

entry:
@Article{Hollingsworth:1989:CPI,
  author =       "Walter Hollingsworth and Howard Sachs and Alan Jay
                 Smith",
  title =        "The {Clipper\TM} Processor: Instruction Set
                 Architecture and Implementation",
  journal =      j-CACM,
  volume =       "32",
  number =       "2",
  pages =        "200--219",
  month =        feb,
  year =         "1989",
  CODEN =        "CACMA2",
  ISSN =         "0001-0782 (print), 1557-7317 (electronic)",
  ISSN-L =       "0001-0782",
  bibdate =      "Mon Sep 26 13:49:15 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Communications of the ACM",
  journal-URL =  "https://dl.acm.org/loi/cacm",
  keywords =     "design; measurement; performance",
  review =       "ACM CR 9002-0119",
  subject =      "C.5.3 Computer Systems Organization, COMPUTER SYSTEM
                 IMPLEMENTATION, Microcomputers, CLIPPER \\ C.1.1
                 Computer Systems Organization, PROCESSOR ARCHITECTURES,
                 Single Data Stream Architectures,
                 Single-instruction-stream, single-data-stream
                 processors (SISD) \\ C.4 Computer Systems Organization,
                 PERFORMANCE OF SYSTEMS \\ C.0 Computer Systems
                 Organization, GENERAL, Instruction set design",
}


bibtype: article
filename: fparith.bib
label: Hoshi:1989:RPV
title: RISC processor V/sub R/3000
journal: j-NEC-TECH-J
volume: 42
number: 11
pages: 34--38
month: dec
monthnumber: 12
year: 1989
CODEN: NECGEZ
ISSN: 0285-4139 OR 02854139
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
fjournal: NEC Technical Journal = NEC giho
keywords: Floating point processor; NEC; RISC type microprocessor; V/sub R/3000; V/sub R/3010
language: Japanese
acknowledgement: ack-nhfb
thesaurus: Microprocessor chips; Reduced instruction set computing
rawtitle: {RISC} processor {V}/sub {R}/3000
author:
T. Hoshi and K. Koya and A. Kuwata and T. Uno and M. Kashimura and T. Kuwata and T. Nishigouri and K. Obuchi and N. Morikawa

abstract:
Outlines NEC's first RISC type microprocessor, the V/sub R/3000 and its developmental environment. V/sub R/3000 is fully compatible with the R3000 developed by MIPS Computer Systems, USA. It offers one of the fastest microprocessor systems in the world, together with a floating point processor V/sub R/3010 that is fully compatible with the R3010.

rawabstract:
Outlines NEC's first RISC type microprocessor, the V/sub R/3000 and its developmental environment. V/sub R/3000 is fully compatible with the R3000 developed by MIPS Computer Systems, USA. It offers one of the fastest microprocessor systems in the world, together with a floating point processor V/sub R/3010 that is fully compatible with the R3010.

rawauthor:
T. Hoshi and K. Koya and A. Kuwata and T. Uno and M. Kashimura and T. Kuwata and T. Nishigouri and K. Obuchi and N. Morikawa

entry:
@Article{Hoshi:1989:RPV,
  author =       "T. Hoshi and K. Koya and A. Kuwata and T. Uno and M.
                 Kashimura and T. Kuwata and T. Nishigouri and K. Obuchi
                 and N. Morikawa",
  title =        "{RISC} processor {V}/sub {R}/3000",
  journal =      j-NEC-TECH-J,
  volume =       "42",
  number =       "11",
  pages =        "34--38",
  month =        dec,
  year =         "1989",
  CODEN =        "NECGEZ",
  ISSN =         "0285-4139",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Outlines NEC's first RISC type microprocessor, the
                 V/sub R/3000 and its developmental environment. V/sub
                 R/3000 is fully compatible with the R3000 developed by
                 MIPS Computer Systems, USA. It offers one of the
                 fastest microprocessor systems in the world, together
                 with a floating point processor V/sub R/3010 that is
                 fully compatible with the R3010.",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture)",
  fjournal =     "NEC Technical Journal = NEC giho",
  keywords =     "Floating point processor; NEC; RISC type
                 microprocessor; V/sub R/3000; V/sub R/3010",
  language =     "Japanese",
  pubcountry =   "Japan",
  thesaurus =    "Microprocessor chips; Reduced instruction set
                 computing",
}


bibtype: inproceedings
filename: fparith.bib
label: Hu:1989:ARM
author: Y. H. Hu and S. Naganathan
title: Angle Recoding Method for Efficient Implementation of the CORDIC Algorithm
crossref: IEEE:1989:IISa
pages: 175--178 (Vol. 1)
year: 1989
bibdate: Thu Sep 01 11:41:20 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 11:41:20 ???
acknowledgement: ack-nj
rawauthor: Y. H. Hu and S. Naganathan
rawtitle: Angle Recoding Method for Efficient Implementation of the {CORDIC} Algorithm
entry:
@InProceedings{Hu:1989:ARM,
  author =       "Y. H. Hu and S. Naganathan",
  title =        "Angle Recoding Method for Efficient Implementation of
                 the {CORDIC} Algorithm",
  crossref =     "IEEE:1989:IISa",
  pages =        "175--178 (Vol. 1)",
  year =         "1989",
  bibdate =      "Thu Sep 01 11:41:20 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: book
filename: fparith.bib
label: Huck:1989:ACA
author: Jerome C. Huck and Michael J. Flynn
title: Analyzing Computer Architectures
publisher: pub-IEEE
address: pub-IEEE:adr
pages: xiii + 188
year: 1989
LCCN: QA76.9.A73 H83 1989
bibdate: Thu Apr 2 08:38:35 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.02 08:38:35 ???
note: IEEE Computer Society order number 857. IEEE catalog number EH0285-7. SAN 264-620X.
acknowledgement: ack-sfo
rawauthor: Jerome C. Huck and Michael J. Flynn
rawnote: IEEE Computer Society order number 857. IEEE catalog number EH0285-7. SAN 264-620X.
rawtitle: Analyzing Computer Architectures
ISBN:
0-8186-8857-2, 0-8186-4857-0 (microfiche), 0-8186-8857-2 (casebound) OR 0818688572, 0818648570 (microfiche), 0818688572 (casebound)

ISBN13:
978-0-8186-8857-7, 978-0-8186-4857-1 (microfiche), 978-0-8186-8857-7 (casebound) OR 9780818688577, 9780818648571 (microfiche), 9780818688577 (casebound)

entry:
@Book{Huck:1989:ACA,
  author =       "Jerome C. Huck and Michael J. Flynn",
  title =        "Analyzing Computer Architectures",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "xiii + 188",
  year =         "1989",
  ISBN =         "0-8186-8857-2, 0-8186-4857-0 (microfiche),
                 0-8186-8857-2 (casebound)",
  ISBN-13 =      "978-0-8186-8857-7, 978-0-8186-4857-1 (microfiche),
                 978-0-8186-8857-7 (casebound)",
  LCCN =         "QA76.9.A73 H83 1989",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "IEEE Computer Society order number 857. IEEE catalog
                 number EH0285-7. SAN 264-620X.",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Husby:1989:FPE
title: A floating point engine for lattice gauge calculations
journal: j-IEEE-TRANS-NUCL-SCI
volume: 36
number: 1
pages: 734--737
month: feb
monthnumber: 2
year: 1989
CODEN: IRNSAM
ISSN: 0018-9499 (print), 1558-1578 (electronic) OR 00189499 (print), 15581578 (electronic)
ISSNL: 0018-9499 OR 00189499
LCCN: TK6540 .I573 Jan-June 1988
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
URL: http://weblib.cern.ch/format/showfull?uid=1451323_18194&base=CERCER&sysnb=0105825
fjournal: IEEE Transactions on Nuclear Science
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=23
rawtitle: A floating point engine for lattice gauge calculations
author:
D. Husby and R. Atac and A. Cook and J. Deppe and M. Fischler and I. Gaines and T. Nash and T. Pham and T. Zmuda and E. Eichten and G. M. Hockney and P. B. Mackenzie and H. B. Thacker and D. Toussaint

rawauthor:
D. Husby and R. Atac and A. Cook and J. Deppe and M. Fischler and I. Gaines and T. Nash and T. Pham and T. Zmuda and E. Eichten and G. M. Hockney and P. B. Mackenzie and H. B. Thacker and D. Toussaint

entry:
@Article{Husby:1989:FPE,
  author =       "D. Husby and R. Atac and A. Cook and J. Deppe and M.
                 Fischler and I. Gaines and T. Nash and T. Pham and T.
                 Zmuda and E. Eichten and G. M. Hockney and P. B.
                 Mackenzie and H. B. Thacker and D. Toussaint",
  title =        "A floating point engine for lattice gauge
                 calculations",
  journal =      j-IEEE-TRANS-NUCL-SCI,
  volume =       "36",
  number =       "1",
  pages =        "734--737",
  month =        feb,
  year =         "1989",
  CODEN =        "IRNSAM",
  ISSN =         "0018-9499 (print), 1558-1578 (electronic)",
  ISSN-L =       "0018-9499",
  LCCN =         "TK6540 .I573 Jan-June 1988",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://weblib.cern.ch/format/showfull?uid=1451323_18194&base=CERCER&sysnb=0105825",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Nuclear Science",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=23",
  summary =      "The Fermilab Advanced Computer Program Multiple Array
                 Processor System, which dedicated to solving problems
                 in the field of quantum chromodynamics, is discussed. A
                 typical system with 256 processors, 2.5 Gb of memory,
                 and 64 Gb of online tape storage \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Hwang:1989:OAU
author: Kai Hwang and D. K. Panda
title: Optical arithmetic using high-radix symbolic substitution rules
crossref: Ercegovac:1989:PSC
pages: 226--232
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Hwang.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Kai Hwang and D. K. Panda
rawtitle: Optical arithmetic using high-radix symbolic substitution rules
entry:
@InProceedings{Hwang:1989:OAU,
  author =       "Kai Hwang and D. K. Panda",
  title =        "Optical arithmetic using high-radix symbolic
                 substitution rules",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "226--232",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Hwang.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: book
filename: fparith.bib
label: IEC:1989:IBF
author: IEC
title: IEC 60559 (1989-01): Binary floating-point arithmetic for microprocessor systems
publisher: pub-IEC
address: pub-IEC:adr
pages: 45
year: 1989
bibdate: Mon Apr 24 06:17:57 2000
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2000.04.24 06:17:57 ???
note: This Standard was formerly known as IEEE 754.
URL: http://www.iec.ch/cgi-bin/procgi.pl/www/iecwww.p?wwwlang=E&wwwprog=cat-det.p&wartnum=019113
acknowledgement: ack-nhfb
rawauthor: {IEC}
rawnote: This Standard was formerly known as IEEE 754.
rawtitle: {IEC 60559 (1989-01)}: Binary floating-point arithmetic for microprocessor systems
remark:
Working Draft, 1997-11-21, WG14/N794 J11/97-158 of the ISO C9X Standard references ``Binary floating-point arithmetic for microprocessor systems, second edition (IEC 559:1993)''. However, I cannot locate that edition at the IEC Web site. The 1997 renumbering of IEC Standards by the addition of 60000 indicates that this document should now be IED 60559:1993, but only the 1989 version is listed in the IEC catalog.

entry:
@Book{IEC:1989:IBF,
  author =       "{IEC}",
  title =        "{IEC 60559 (1989-01)}: Binary floating-point
                 arithmetic for microprocessor systems",
  publisher =    pub-IEC,
  address =      pub-IEC:adr,
  pages =        "45",
  year =         "1989",
  bibdate =      "Mon Apr 24 06:17:57 2000",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "This Standard was formerly known as IEEE 754.",
  price =        "US\$86.00",
  URL =          "http://www.iec.ch/cgi-bin/procgi.pl/www/iecwww.p?wwwlang=E&wwwprog=cat-det.p&wartnum=019113",
  acknowledgement = ack-nhfb,
  remark =       "Working Draft, 1997-11-21, WG14/N794 J11/97-158 of the
                 ISO C9X Standard references ``Binary floating-point
                 arithmetic for microprocessor systems, second edition
                 (IEC 559:1993)''. However, I cannot locate that edition
                 at the IEC Web site. The 1997 renumbering of IEC
                 Standards by the addition of 60000 indicates that this
                 document should now be IED 60559:1993, but only the
                 1989 version is listed in the IEC catalog.",
}


bibtype: mastersthesis
filename: fparith.bib
label: Intwala:1989:BFP
author: Jaiprakash D. Intwala
title: 8085A based floating point arithmetic system
type: Thesis (M.S.)
school: California State University, Northridge
address: Northridge, CA, USA
pages: viii + 81
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
acknowledgement: ack-nhfb
rawauthor: Jaiprakash D. Intwala
rawtitle: {8085A} based floating point arithmetic system
entry:
@MastersThesis{Intwala:1989:BFP,
  author =       "Jaiprakash D. Intwala",
  title =        "{8085A} based floating point arithmetic system",
  type =         "Thesis ({M.S.})",
  school =       "California State University, Northridge",
  address =      "Northridge, CA, USA",
  pages =        "viii + 81",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Jain:1989:SLU
author: V. K. Jain and D. L. Landia and C. E. Alvarez
title: Systolic L-U Decomposition Array With a New Reciprocal Cell
crossref: IEEE:1989:PII
pages: 460--465
year: 1989
bibdate: Sun Sep 11 20:59:19 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.11 20:59:19 ???
acknowledgement: ack-nj
rawauthor: V. K. Jain and D. L. Landia and C. E. Alvarez
rawtitle: Systolic {L-U} Decomposition Array With a New Reciprocal Cell
entry:
@InProceedings{Jain:1989:SLU,
  author =       "V. K. Jain and D. L. Landia and C. E. Alvarez",
  title =        "Systolic {L-U} Decomposition Array With a New
                 Reciprocal Cell",
  crossref =     "IEEE:1989:PII",
  pages =        "460--465",
  year =         "1989",
  bibdate =      "Sun Sep 11 20:59:19 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Jamieson:1989:SNR
author: M. J. Jamieson
journal: j-COMP-J
volume: 32
number: 1
pages: 93--94
month: feb
monthnumber: 2
year: 1989
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/32.1.93
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
MRclass: 65H05
MRnumber: 89k:65063
bibdate: Tue Dec 4 14:48:26 MST 2012
bibtimestamp: 2012.12.04 14:48:26 MST
note: This work generalizes the Pythagorean sums in cite Dubrulle:1983:CNM,Moler:1983:RSR.
fjournal: The Computer Journal
acknowledgement: ack-nhfb
affiliation: Department of Computer Science, Glasgow University, UK
affiliationaddress: Glasgow, Scotl
classcodes: B0290F (Interpolation and function approximation); C4130 (Interpolation and function approximation)
corpsource: Department of Computer Science, Glasgow University, UK
journalURL: http://comjnl.oxfordjournals.org/
thesaurus: Convergence of numerical methods; Function approximation; Iterative methods
treatment: P Practical
rawauthor: M. J. Jamieson
rawnote: This work generalizes the Pythagorean sums in \cite{Dubrulle:1983:CNM,Moler:1983:RSR}.
title:
Short Notes: Rapidly Converging Iterative Formulae for Finding Square Roots and their Computational Efficiencies

bibsource:
Compendex database; http://comjnl.oxfordjournals.org/content/32/1.toc; http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_01/; https://www.math.utah.edu/pub/tex/bib/compj1980.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://comjnl.oxfordjournals.org/content/32/1/93.full.pdf+html; http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_01/tiff/93.tif; http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_01/tiff/94.tif

abstract:
A derivation is given of rapidly converging iterative formulae for finding square roots which include, as special cases, some recently published examples. Their computational efficiencies are investigated for sequential and parallel implementation. It is concluded that the most efficient method is equivalent to sequential application of the Newton Raphson formula; a simple modification is suggested which brings the advantage of root bracketing at little extra computational cost.

keywords:
computational; Computational efficiencies; Computational Efficiency; Computer Metatheory; Convergence; convergence of numerical methods; Converging iterative formulae; converging iterative formulae; efficiencies; formula; function approximation; Iterative Methods; iterative methods; Newton Raphson; Newton Raphson formula, Mathematical Techniques; Parallel implementation; parallel implementation; Square Roots; Square roots; square roots

rawabstract:
A derivation is given of rapidly converging iterative formulae for finding square roots which include, as special cases, some recently published examples. Their computational efficiencies are investigated for sequential and parallel implementation. It is concluded that the most efficient method is equivalent to sequential application of the Newton Raphson formula; a simple modification is suggested which brings the advantage of root bracketing at little extra computational cost.

rawtitle:
Short Notes: Rapidly Converging Iterative Formulae for Finding Square Roots and their Computational Efficiencies

entry:
@Article{Jamieson:1989:SNR,
  author =       "M. J. Jamieson",
  title =        "Short Notes: Rapidly Converging Iterative Formulae for
                 Finding Square Roots and their Computational
                 Efficiencies",
  journal =      j-COMP-J,
  volume =       "32",
  number =       "1",
  pages =        "93--94",
  month =        feb,
  year =         "1989",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/32.1.93",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  MRclass =      "65H05",
  MRnumber =     "89k:65063",
  bibdate =      "Tue Dec 4 14:48:26 MST 2012",
  bibsource =    "Compendex database;
                 http://comjnl.oxfordjournals.org/content/32/1.toc;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_01/;
                 https://www.math.utah.edu/pub/tex/bib/compj1980.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "This work generalizes the Pythagorean sums in
                 \cite{Dubrulle:1983:CNM,Moler:1983:RSR}.",
  URL =          "http://comjnl.oxfordjournals.org/content/32/1/93.full.pdf+html;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_01/tiff/93.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_01/tiff/94.tif",
  abstract =     "A derivation is given of rapidly converging iterative
                 formulae for finding square roots which include, as
                 special cases, some recently published examples. Their
                 computational efficiencies are investigated for
                 sequential and parallel implementation. It is concluded
                 that the most efficient method is equivalent to
                 sequential application of the Newton Raphson formula; a
                 simple modification is suggested which brings the
                 advantage of root bracketing at little extra
                 computational cost.",
  acknowledgement = ack-nhfb,
  affiliation =  "Department of Computer Science, Glasgow University,
                 UK",
  affiliationaddress = "Glasgow, Scotl",
  classcodes =   "B0290F (Interpolation and function approximation);
                 C4130 (Interpolation and function approximation)",
  classification = "723; 921; B0290F (Interpolation and function
                 approximation); C4130 (Interpolation and function
                 approximation)",
  corpsource =   "Department of Computer Science, Glasgow University,
                 UK",
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "computational; Computational efficiencies;
                 Computational Efficiency; Computer Metatheory;
                 Convergence; convergence of numerical methods;
                 Converging iterative formulae; converging iterative
                 formulae; efficiencies; formula; function
                 approximation; Iterative Methods; iterative methods;
                 Newton Raphson; Newton Raphson formula, Mathematical
                 Techniques; Parallel implementation; parallel
                 implementation; Square Roots; Square roots; square
                 roots",
  thesaurus =    "Convergence of numerical methods; Function
                 approximation; Iterative methods",
  treatment =    "P Practical",
}


bibtype: inproceedings
filename: fparith.bib
label: Jenkins:1989:AFP
author: W. K. Jenkins and J. K. Yun
booktitle: European Conference on Circuit Theory and Design, 5--8 Sep 1989
title: Analysis of fixed point roundoff effects in transform domain LMS adaptive filters
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 228--232
year: 1989
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: W. K. Jenkins and J. K. Yun
rawbooktitle: European Conference on Circuit Theory and Design, 5--8 Sep 1989
rawtitle: Analysis of fixed point roundoff effects in transform domain {LMS} adaptive filters
entry:
@InProceedings{Jenkins:1989:AFP,
  author =       "W. K. Jenkins and J. K. Yun",
  booktitle =    "European Conference on Circuit Theory and Design, 5--8
                 Sep 1989",
  title =        "Analysis of fixed point roundoff effects in transform
                 domain {LMS} adaptive filters",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "228--232",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "One of the disadvantages of the well known LMS FIR
                 adaptive digital filter is that, for a colored noise
                 input signals, the filter tends to converge slowly. One
                 way to improve the convergence rate is to prefilter the
                 input signal with an \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Johnson:1989:IMA
author: K. R. Johnson
title: An Iterative Method for Approximating Square Roots
journal: j-MATH-MAG
volume: 62
number: 4
pages: 253--259
month: oct
monthnumber: 10
year: 1989
CODEN: MAMGA8
ISSN: 0025-570X OR 0025570X
bibdate: Thu Sep 1 10:15:42 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.01 10:15:42 ???
fjournal: Mathematics Magazine
acknowledgement: ack-nj
journalURL: http://www.maa.org/pubs/mathmag.html
rawauthor: K. R. Johnson
rawtitle: An Iterative Method for Approximating Square Roots
entry:
@Article{Johnson:1989:IMA,
  author =       "K. R. Johnson",
  title =        "An Iterative Method for Approximating Square Roots",
  journal =      j-MATH-MAG,
  volume =       "62",
  number =       "4",
  pages =        "253--259",
  month =        oct,
  year =         "1989",
  CODEN =        "MAMGA8",
  ISSN =         "0025-570X",
  bibdate =      "Thu Sep 1 10:15:42 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  fjournal =     "Mathematics Magazine",
  journal-URL =  "http://www.maa.org/pubs/mathmag.html",
}


bibtype: inproceedings
filename: fparith.bib
label: Johnstone:1989:HRF
author: Paul Johnstone and Frederick E. Petry
title: Higher Radix Floating Point Representations
crossref: Ercegovac:1989:PSC
pages: 128--135
year: 1989
DOI: https://doi.org/10.1109/ARITH.1989.72818
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Johnstone.pdf
acknowledgement: ack-nhfb
affiliation: Telerate Syst. Inc., New Orleans, LA, USA
thesaurus: Digital arithmetic
rawauthor: Paul Johnstone and Frederick E. Petry
rawtitle: Higher Radix Floating Point Representations
abstract:
An examination is made of the feasibility of higher-radix floating-point representations and, in particular, decimal-based representations. Traditional analyses of such representations have assumed the format of a floating-point datum to be roughly identical to that of traditional binary floating-point encodings such as the IEEE P754 task group standard representations. The authors relax this restriction and propose a method of encoding higher-radix floating-point data with range, precision, and storage requirements comparable to those exhibited by traditional binary representations. The results of other authors are extended to accommodate the proposed representation. A decimal alternative to traditional binary representations is proposed, and the behavior of such a system is contrasted with that of a comparable binary system.

keywords:
ARITH-9; Binary representations; decimal floating-point arithmetic; Decimal-based representations; encodings; higher radix floating point representation; IEEE P754 task group standard representations

rawabstract:
An examination is made of the feasibility of higher-radix floating-point representations and, in particular, decimal-based representations. Traditional analyses of such representations have assumed the format of a floating-point datum to be roughly identical to that of traditional binary floating-point encodings such as the IEEE P754 task group standard representations. The authors relax this restriction and propose a method of encoding higher-radix floating-point data with range, precision, and storage requirements comparable to those exhibited by traditional binary representations. The results of other authors are extended to accommodate the proposed representation. A decimal alternative to traditional binary representations is proposed, and the behavior of such a system is contrasted with that of a comparable binary system.

entry:
@InProceedings{Johnstone:1989:HRF,
  author =       "Paul Johnstone and Frederick E. Petry",
  title =        "Higher Radix Floating Point Representations",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "128--135",
  year =         "1989",
  DOI =          "https://doi.org/10.1109/ARITH.1989.72818",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Johnstone.pdf",
  abstract =     "An examination is made of the feasibility of
                 higher-radix floating-point representations and, in
                 particular, decimal-based representations. Traditional
                 analyses of such representations have assumed the
                 format of a floating-point datum to be roughly
                 identical to that of traditional binary floating-point
                 encodings such as the IEEE P754 task group standard
                 representations. The authors relax this restriction and
                 propose a method of encoding higher-radix
                 floating-point data with range, precision, and storage
                 requirements comparable to those exhibited by
                 traditional binary representations. The results of
                 other authors are extended to accommodate the proposed
                 representation. A decimal alternative to traditional
                 binary representations is proposed, and the behavior of
                 such a system is contrasted with that of a comparable
                 binary system.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Telerate Syst. Inc., New Orleans, LA, USA",
  classification = "C5230 (Digital arithmetic methods)",
  confdate =     "6-8 Sept. 1989",
  conflocation = "Santa Monica, CA, USA",
  confsponsor =  "IEEE; IFIP; University of California",
  keywords =     "ARITH-9; Binary representations; decimal
                 floating-point arithmetic; Decimal-based
                 representations; encodings; higher radix floating point
                 representation; IEEE P754 task group standard
                 representations",
  thesaurus =    "Digital arithmetic",
}


bibtype: article
filename: fparith.bib
label: Jones:1989:EDC
author: Tom Jones
title: Engineering design of the Convex C2
journal: j-COMPUTER
volume: 22
number: 1
pages: 36--44
month: jan
monthnumber: 1
year: 1989
CODEN: CPTRB4
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Sat Nov 9 08:26:18 MST 2002
bibsource: ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.09 08:26:18 MST
fjournal: Computer
acknowledgement: ack-nhfb
affiliation: Convex Computer Corp., Richardson, TX
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
key: C.5.1 Convex C2
reviewer: P. C. Patton
rawauthor: Tom Jones
rawtitle: Engineering design of the {Convex C2}
subject:
C. Computer Systems Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION; C. Computer Systems Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION; B. Hardware; B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS; B. Hardware; B.7 INTEGRATED CIRCUITS; C. Computer Systems Organization; C.1 PROCESSOR ARCHITECTURES

entry:
@Article{Jones:1989:EDC,
  author =       "Tom Jones",
  key =          "C.5.1 Convex C2",
  title =        "Engineering design of the {Convex C2}",
  journal =      j-COMPUTER,
  volume =       "22",
  number =       "1",
  pages =        "36--44",
  month =        jan,
  year =         "1989",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Sat Nov 9 08:26:18 MST 2002",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Convex Computer Corp., Richardson, TX",
  bibno =        "58556",
  catcode =      "C.5.1; C.5.1; B.4.3; B.7.1; C.1.2",
  content =      "The Convex C220 and C240 supercomputers are 64-bit
                 multiprocessors that are tightly coupled through a
                 shared main memory. Each processor contains an
                 integrated vector processor. A microcoded instruction
                 set controls all processor features, including the
                 vector processor. The system is implemented in 100K
                 emitter-coupled logic with a cycle time of 40
                 nanoseconds. The C220 contains two processors, an I/O
                 system, and memory. The C240 contains four processors,
                 a larger I/O system, and memory. This paper describes
                 the design process of this computer family and tries to
                 illuminate the methods and rationale behind
                 project-related decisions.\par

                 The original C1 system was designed in early 1983 using
                 transistor-transistor logic and complementary
                 metal-oxide semiconductor (CMOS) technologies. The bulk
                 of the machine consisted of medium- and
                 small-scale-integration logic, and the vector
                 functional units were built with 8,000-gate CMOS
                 arrays. The original C1 (later dubbed the C1-XL) had no
                 scalar floating-point hardware but sent the operands to
                 the vector processor. In 1984, floating-point
                 add-and-multiply functional units were designed in
                 20,000-gate CMOS arrays, and the C1 was upgraded to the
                 C1-XP. That machine, with minor changes, became the
                 C120 when the C2 was announced.\par

                 This paper is unusually frank for a retrospective
                 design trade-off study. The author describes",
  CRclass =      "C.5.1 Large and Medium (``Mainframe'') Computers;
                 C.5.1 Super (very large) computers; C.5.1 Large and
                 Medium (``Mainframe'') Computers; C.5.1 Convex C2;
                 B.4.3 Interconnections (subsystems); B.7.1 Types and
                 Design Styles; B.7.1 Gate arrays; C.1.2 Multiple Data
                 Stream Architectures (Multiprocessors); C.1.2
                 Interconnection architectures",
  CRnumber =     "8909-0654",
  descriptor =   "Computer Systems Organization, COMPUTER SYSTEM
                 IMPLEMENTATION, Large and Medium (``Mainframe'')
                 Computers, Super (very large) computers; Computer
                 Systems Organization, COMPUTER SYSTEM IMPLEMENTATION,
                 Large and Medium (``Mainframe'') Computers, Convex C2;
                 Hardware, INPUT/OUTPUT AND DATA COMMUNICATIONS,
                 Interconnections (subsystems); Hardware, INTEGRATED
                 CIRCUITS, Types and Design Styles, Gate arrays;
                 Computer Systems Organization, PROCESSOR ARCHITECTURES,
                 Multiple Data Stream Architectures (Multiprocessors),
                 Interconnection architectures",
  fjournal =     "Computer",
  genterm =      "DESIGN; MANAGEMENT; PERFORMANCE; ECONOMICS",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  journalabbrev = "Computer",
  reviewer =     "P. C. Patton",
  subject =      "C. Computer Systems Organization; C.5 COMPUTER SYSTEM
                 IMPLEMENTATION; C. Computer Systems Organization; C.5
                 COMPUTER SYSTEM IMPLEMENTATION; B. Hardware; B.4
                 INPUT/OUTPUT AND DATA COMMUNICATIONS; B. Hardware; B.7
                 INTEGRATED CIRCUITS; C. Computer Systems Organization;
                 C.1 PROCESSOR ARCHITECTURES",
}


bibtype: book
filename: fparith.bib
label: Jorke:1989:AAM
author: Gunter Jorke and Bernhard Lampe and Norbert Wengel
publisher: pub-VEB-VERLAG-TECHNIK
address: pub-VEB-VERLAG-TECHNIK:adr
pages: 323
year: 1989
ISBN: 3-341-00515-3 OR 3341005153
ISBN13: 978-3-341-00515-6 OR 9783341005156
bibdate: Fri Sep 16 16:30:36 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.16 16:30:36 ???
acknowledgement: ack-nj
rawauthor: G{\"u}nter Jorke and Bernhard Lampe and Norbert Wengel
title:
Arithmetische Algorithmen der Mikrorechentechnik toenglish Arithmetic Algorithms of Microcomputing endtoenglish 

rawtitle:
{Arithmetische Algorithmen der Mikrorechentechnik} \toenglish {Arithmetic Algorithms of Microcomputing} \endtoenglish

entry:
@Book{Jorke:1989:AAM,
  author =       "G{\"u}nter Jorke and Bernhard Lampe and Norbert
                 Wengel",
  title =        "{Arithmetische Algorithmen der Mikrorechentechnik}
                 \toenglish {Arithmetic Algorithms of Microcomputing}
                 \endtoenglish",
  publisher =    pub-VEB-VERLAG-TECHNIK,
  address =      pub-VEB-VERLAG-TECHNIK:adr,
  pages =        "323",
  year =         "1989",
  ISBN =         "3-341-00515-3",
  ISBN-13 =      "978-3-341-00515-6",
  LCCN =         "????",
  bibdate =      "Fri Sep 16 16:30:36 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
  xxnote =       "fpbiblio.txt 1.8 has order Lampe, Jorke, Wengel, but
                 RLIN catalog has Jorke, Lampe, Wengel.",
}


bibtype: article
filename: fparith.bib
label: Joslin:1989:EPN
author: David A. Joslin
title: Extended Pascal --- numerical features
journal: j-SIGPLAN
volume: 24
number: 6
pages: 77--80
month: jun
monthnumber: 6
year: 1989
CODEN: SINODQ
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Sun Dec 14 09:15:40 MST 2003
bibsource: Compendex database; http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.14 09:15:40 MST
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
affiliationaddress: Middlesbrough, Engl
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
journalabr: SIGPLAN Not
rawauthor: David A. Joslin
rawtitle: Extended {Pascal} --- numerical features
abstract:
The Extended Pascal standard, drafted by the Joint X3J9 / IEEE-770 Pascal Standards Committee (JPC) in conjunction with the ISO Pascal working group (ISO / IEC JTC1 / SC22 / WG2), completed its second public comment period at the end of 1988. The comments received have been considered by JPC and the ISO group, and the standard is now almost certainly in its final form. Earlier papers by this author described the main features of the standard by means of illustrative examples. This is now the first in an occasional series of articles, by this author and other JPC & WG2 members, describing in more detail various extensions which have been made to the Pascal language; rationale is given where appropriate. This paper describes the predefined type COMPLEX, the range and precision of type REAL, and the EXPONENTIATION operators.

keywords:
Complex Arithmetic; Computer Operating Systems--Program Compilers; Computer Programming Languages; design; Extended Pascal; languages; pascal; standardization; Standards

subject:
D.2.1 Software, SOFTWARE ENGINEERING, Requirements/Specifications D.3.2 Software, PROGRAMMING LANGUAGES, Language Classifications, Pascal

rawabstract:
The Extended Pascal standard, drafted by the Joint X3J9\slash IEEE-770 Pascal Standards Committee (JPC) in conjunction with the ISO Pascal working group (ISO\slash IEC JTC1\slash SC22\slash WG2), completed its second public comment period at the end of 1988. The comments received have been considered by JPC and the ISO group, and the standard is now almost certainly in its final form. Earlier papers by this author described the main features of the standard by means of illustrative examples. This is now the first in an occasional series of articles, by this author and other JPC \& WG2 members, describing in more detail various extensions which have been made to the Pascal language; rationale is given where appropriate. This paper describes the predefined type COMPLEX, the range and precision of type REAL, and the EXPONENTIATION operators.

entry:
@Article{Joslin:1989:EPN,
  author =       "David A. Joslin",
  title =        "Extended {Pascal} --- numerical features",
  journal =      j-SIGPLAN,
  volume =       "24",
  number =       "6",
  pages =        "77--80",
  month =        jun,
  year =         "1989",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sun Dec 14 09:15:40 MST 2003",
  bibsource =    "Compendex database; http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Extended Pascal standard, drafted by the Joint
                 X3J9\slash IEEE-770 Pascal Standards Committee (JPC) in
                 conjunction with the ISO Pascal working group
                 (ISO\slash IEC JTC1\slash SC22\slash WG2), completed
                 its second public comment period at the end of 1988.
                 The comments received have been considered by JPC and
                 the ISO group, and the standard is now almost certainly
                 in its final form. Earlier papers by this author
                 described the main features of the standard by means of
                 illustrative examples. This is now the first in an
                 occasional series of articles, by this author and other
                 JPC \& WG2 members, describing in more detail various
                 extensions which have been made to the Pascal language;
                 rationale is given where appropriate. This paper
                 describes the predefined type COMPLEX, the range and
                 precision of type REAL, and the EXPONENTIATION
                 operators.",
  acknowledgement = ack-nhfb,
  affiliationaddress = "Middlesbrough, Engl",
  classification = "723; 902",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  journalabr =   "SIGPLAN Not",
  keywords =     "Complex Arithmetic; Computer Operating
                 Systems--Program Compilers; Computer Programming
                 Languages; design; Extended Pascal; languages; pascal;
                 standardization; Standards",
  subject =      "D.2.1 Software, SOFTWARE ENGINEERING,
                 Requirements/Specifications \\ D.3.2 Software,
                 PROGRAMMING LANGUAGES, Language Classifications,
                 Pascal",
}


bibtype: techreport
filename: fparith.bib
label: Jouppi:1989:UVSa
author: Norman Paul Jouppi and Jonathan Bertoni and David Wayne Wall
title: A unified vector / scalar floating-point architecture
institution: Digital Western Research Laboratory
address: Palo Alto, CA, USA
pages: v + 23
month: jul
monthnumber: 7
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
series: WRL research report; 89/8
acknowledgement: ack-nhfb
rawauthor: Norman Paul Jouppi and Jonathan Bertoni and David Wayne Wall
rawtitle: A unified vector\slash scalar floating-point architecture
keywords:
Computer architecture.; Floating-point arithmetic.; MultiTitan (Computer); Scalar field theory.; Supercomputers.; Vector processing (Computer science)

entry:
@TechReport{Jouppi:1989:UVSa,
  author =       "Norman Paul Jouppi and Jonathan Bertoni and David
                 Wayne Wall",
  title =        "A unified vector\slash scalar floating-point
                 architecture",
  institution =  "Digital Western Research Laboratory",
  address =      "Palo Alto, CA, USA",
  pages =        "v + 23",
  month =        jul,
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "WRL research report; 89/8",
  acknowledgement = ack-nhfb,
  keywords =     "Computer architecture.; Floating-point arithmetic.;
                 MultiTitan (Computer); Scalar field theory.;
                 Supercomputers.; Vector processing (Computer science)",
}


bibtype: article
filename: fparith.bib
label: Jouppi:1989:UVSb
author: N. P. Jouppi and J. Bertoni and D. W. Wall
title: A unified vector / scalar floating-point architecture
journal: j-COMP-ARCH-NEWS
volume: 17
number: 2
pages: 134--143
month: apr
monthnumber: 4
year: 1989
CODEN: CANED2
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Fri May 12 09:40:39 MDT 2006
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.12 09:40:39 MDT
fjournal: ACM SIGARCH Computer Architecture News
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J89
rawauthor: N. P. Jouppi and J. Bertoni and D. W. Wall
rawtitle: A unified vector\slash scalar floating-point architecture
entry:
@Article{Jouppi:1989:UVSb,
  author =       "N. P. Jouppi and J. Bertoni and D. W. Wall",
  title =        "A unified vector\slash scalar floating-point
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "134--143",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
}


bibtype: misc
filename: fparith.bib
label: Kahan:1989:PCA
author: W. Kahan
title: Paradoxes in Concepts of Accuracy
pages: 134--143
year: 1989
bibdate: Sat Sep 17 18:40:08 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.17 18:40:08 ???
acknowledgement: ack-nhfb
howpublished: Lecture notes from Joint Seminar on Issues and Directions in Scientific Computation, Berkeley
rawauthor: W. Kahan
rawtitle: Paradoxes in Concepts of Accuracy
entry:
@Misc{Kahan:1989:PCA,
  author =       "W. Kahan",
  title =        "Paradoxes in Concepts of Accuracy",
  howpublished = "Lecture notes from Joint Seminar on Issues and
                 Directions in Scientific Computation, Berkeley",
  year =         "1989",
  bibdate =      "Sat Sep 17 18:40:08 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kak:1989:BAS
author: S. C. Kak and A. O. Barbir
booktitle: Proceedings of the Twenty-First Southeastern Symposium on System Theory, 26--28 March 1989
title: The Brahmagupta algorithm for square rooting
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 456--459
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
acknowledgement: ack-nhfb
rawauthor: S. C. Kak and A. O. Barbir
rawbooktitle: Proceedings of the Twenty-First Southeastern Symposium on System Theory, 26--28 March 1989
rawtitle: The {Brahmagupta} algorithm for square rooting
entry:
@InProceedings{Kak:1989:BAS,
  author =       "S. C. Kak and A. O. Barbir",
  booktitle =    "Proceedings of the Twenty-First Southeastern Symposium
                 on System Theory, 26--28 March 1989",
  title =        "The {Brahmagupta} algorithm for square rooting",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "456--459",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "An algorithm for square root evaluation is introduced.
                 Novel features of the algorithm include suitability for
                 parallel processing and multi-initial guesses of the
                 root. An extension of the algorithm to the nth rooting
                 is provided. A VLSI \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Kaneko:1989:VRM
title: A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1331--1340
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
rawtitle: A {VLSI RISC} with {20-MFLOPS} peak, 64-bit floating-point unit
author:
K. Kaneko and T. Okamoto and M. Nakajima and Y. Nakakura and S. Gokita and J. Nishikawa and Y. Tanikawa and H. Kadota

rawauthor:
K. Kaneko and T. Okamoto and M. Nakajima and Y. Nakakura and S. Gokita and J. Nishikawa and Y. Tanikawa and H. Kadota

entry:
@Article{Kaneko:1989:VRM,
  author =       "K. Kaneko and T. Okamoto and M. Nakajima and Y.
                 Nakakura and S. Gokita and J. Nishikawa and Y. Tanikawa
                 and H. Kadota",
  title =        "A {VLSI RISC} with {20-MFLOPS} peak, 64-bit
                 floating-point unit",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1331--1340",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  summary =      "A microprocessor designed as a processing element of a
                 scientific parallel computer system is described. This
                 chip consists of a simple integer processor core and
                 dedicated floating-point hardware and executes 64-bit
                 floating-point addition, subtraction \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Kaneko:1989:VRP
title: A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1331--1340
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
affiliation: Semicond. Research Center, Matsushita Electr. Ind. Co., Ltd., Osaka, Japan
rawtitle: A {VLSI RISC} with 20-{MFLOPS} peak, 64-bit floating-point unit
author:
K. Kaneko and T. Okamoto and M. Nakajima and Y. Nakakura and S. Gokita and J. Nishikawa and Y. Tanikawa and H. Kadota

abstract:
A microprocessor designed as a processing element of a scientific parallel computer system is described. This chip consists of a simple integer processor core and dedicated floating-point hardware and executes 64-bit floating-point addition, subtraction, and multiplication at a rate of every 50 ns and division every 350 ns. The processor, which employs RISC architecture and Harvard-style bus organization, executes most of the 47 instructions in one 50-ns cycle. The chip is fabricated in 1.2- mu m n-well CMOS technology, containing 440K transistors in a 14.4*13.5-mm/sup 2/ die. The authors provide an overview of the processor, especially focusing on the functions for a parallel system, floating-point hardware, and the new divide algorithm.

keywords:
1.2 Micron; 20 MFLOPS; 350 Ns; 50 Ns; 64 Bit; Addition; Dedicated floating-point hardware; Division; Floating-point unit; Harvard-style bus organization; Integer processor core; Microprocessor; Multiplication; N-well CMOS technology; RISC architecture; Scientific parallel computer system; Subtraction; VLSI

thesaurus:
CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Parallel processing; Reduced instruction set computing; VLSI

rawabstract:
A microprocessor designed as a processing element of a scientific parallel computer system is described. This chip consists of a simple integer processor core and dedicated floating-point hardware and executes 64-bit floating-point addition, subtraction, and multiplication at a rate of every 50 ns and division every 350 ns. The processor, which employs RISC architecture and Harvard-style bus organization, executes most of the 47 instructions in one 50-ns cycle. The chip is fabricated in 1.2- mu m n-well CMOS technology, containing 440K transistors in a 14.4*13.5-mm/sup 2/ die. The authors provide an overview of the processor, especially focusing on the functions for a parallel system, floating-point hardware, and the new divide algorithm.

entry:
@Article{Kaneko:1989:VRP,
  author =       "K. Kaneko and T. Okamoto and M. Nakajima and Y.
                 Nakakura and S. Gokita and J. Nishikawa and Y. Tanikawa
                 and H. Kadota",
  title =        "A {VLSI RISC} with 20-{MFLOPS} peak, 64-bit
                 floating-point unit",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1331--1340",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A microprocessor designed as a processing element of a
                 scientific parallel computer system is described. This
                 chip consists of a simple integer processor core and
                 dedicated floating-point hardware and executes 64-bit
                 floating-point addition, subtraction, and
                 multiplication at a rate of every 50 ns and division
                 every 350 ns. The processor, which employs RISC
                 architecture and Harvard-style bus organization,
                 executes most of the 47 instructions in one 50-ns
                 cycle. The chip is fabricated in 1.2- mu m n-well CMOS
                 technology, containing 440K transistors in a
                 14.4*13.5-mm/sup 2/ die. The authors provide an
                 overview of the processor, especially focusing on the
                 functions for a parallel system, floating-point
                 hardware, and the new divide algorithm.",
  acknowledgement = ack-nhfb,
  affiliation =  "Semicond. Research Center, Matsushita Electr. Ind.
                 Co., Ltd., Osaka, Japan",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5230 (Digital arithmetic methods)",
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "1.2 Micron; 20 MFLOPS; 350 Ns; 50 Ns; 64 Bit;
                 Addition; Dedicated floating-point hardware; Division;
                 Floating-point unit; Harvard-style bus organization;
                 Integer processor core; Microprocessor; Multiplication;
                 N-well CMOS technology; RISC architecture; Scientific
                 parallel computer system; Subtraction; VLSI",
  numericalindex = "Computer speed 2.0E+07 FLOPS; Word length 6.4E+01
                 bit; Time 5.0E-08 s; Time 3.5E-07 s; Size 1.2E-06 m",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Parallel processing; Reduced
                 instruction set computing; VLSI",
}


bibtype: inproceedings
filename: fparith.bib
label: Kawarai:1989:OPM
author: S. Kawarai and T. Murakami
title: An optimization procedure to minimize the roundoff noise in cascade floating-point digital filters
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 884--887
year: 1989
bibdate: Sat Jul 16 11:25:07 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:07 MDT
acknowledgement: ack-nhfb
rawauthor: S. Kawarai and T. Murakami
rawtitle: An optimization procedure to minimize the roundoff noise in cascade floating-point digital filters
booktitle:
Acoustics, Speech, and Signal Processing, 1989. ICASSP-89., 1989 International Conference on. 23--26 May 1989

rawbooktitle:
Acoustics, Speech, and Signal Processing, 1989. {ICASSP-89., 1989} International Conference on. 23--26 May 1989

entry:
@InProceedings{Kawarai:1989:OPM,
  author =       "S. Kawarai and T. Murakami",
  booktitle =    "Acoustics, Speech, and Signal Processing, 1989.
                 {ICASSP-89., 1989} International Conference on. 23--26
                 May 1989",
  title =        "An optimization procedure to minimize the roundoff
                 noise in cascade floating-point digital filters",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "884--887",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:07 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The authors study the roundoff errors in
                 floating-point arithmetic and present an optimization
                 procedure for cascade floating-point digital filters.
                 Applying the isosceles trapezoidal distribution to the
                 error analysis of cascade floating-point \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Kawasaki:1989:FPV
author: S. Kawasaki and M. Watabe and S. Morinaga
journal: j-IEEE-MICRO
volume: 9
number: 3
pages: 26--44
month: may
monthnumber: 5
year: 1989
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/40.31476
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Micro
acknowledgement: ack-nj
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawauthor: S. Kawasaki and M. Watabe and S. Morinaga
title:
A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming

rawtitle:
A floating-point {VLSI} chip for the {TRON} architecture: an architecture for reliable numerical programming

entry:
@Article{Kawasaki:1989:FPV,
  author =       "S. Kawasaki and M. Watabe and S. Morinaga",
  title =        "A floating-point {VLSI} chip for the {TRON}
                 architecture: an architecture for reliable numerical
                 programming",
  journal =      j-IEEE-MICRO,
  volume =       "9",
  number =       "3",
  pages =        "26--44",
  month =        may # "\slash " # jun,
  year =         "1989",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/40.31476",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  summary =      "A description is given of the Gmicro/FPU
                 (floating-point unit), a chip that provides
                 floating-point instructions for both the Gmicro/200 and
                 the Gmicro/300 microprocessors. The VLSI
                 central-processing-unit architecture, for which it is
                 designed, \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Koc:1989:SAI
author: C. K. Koc and P. R. Cappello
title: Systolic arrays for integer Chinese remaindering
crossref: Ercegovac:1989:PSC
pages: 216--223
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Koc.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: {\c{C}}. K. Ko{\c{c}} and P. R. Cappello
rawtitle: Systolic arrays for integer {Chinese} remaindering
entry:
@InProceedings{Koc:1989:SAI,
  author =       "{\c{C}}. K. Ko{\c{c}} and P. R. Cappello",
  title =        "Systolic arrays for integer {Chinese} remaindering",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "216--223",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Koc.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Kohn:1989:ISM
author: L. Kohn and N. Margulis
title: The i860 64-bit supercomputing microprocessor
crossref: ACM:1989:PSN
pages: 450--456
year: 1989
bibdate: Wed Apr 15 19:32:44 MDT 1998
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1998.04.15 19:32:44 MDT
acknowledgement: ack-nhfb
corpsource: Intel Corp., Santa Clara, CA, USA
treatment: P Practical
rawauthor: L. Kohn and N. Margulis
rawtitle: The {i860} 64-bit supercomputing microprocessor
keywords:
64 bit; caches; floating point unit; i860 64-bit supercomputing microprocessor; Intel; memory management; microprocessor chips; multiplier units; parallel architectures; parallelism; pipelined adder; pipelining; reduced instruction set computing; RISC based microprocessor; three-dimensional graphics

entry:
@InProceedings{Kohn:1989:ISM,
  author =       "L. Kohn and N. Margulis",
  title =        "The {i860} 64-bit supercomputing microprocessor",
  crossref =     "ACM:1989:PSN",
  pages =        "450--456",
  year =         "1989",
  bibdate =      "Wed Apr 15 19:32:44 MDT 1998",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture)",
  corpsource =   "Intel Corp., Santa Clara, CA, USA",
  keywords =     "64 bit; caches; floating point unit; i860 64-bit
                 supercomputing microprocessor; Intel; memory
                 management; microprocessor chips; multiplier units;
                 parallel architectures; parallelism; pipelined adder;
                 pipelining; reduced instruction set computing; RISC
                 based microprocessor; three-dimensional graphics",
  sponsororg =   "ACM; IEEE",
  treatment =    "P Practical",
}


bibtype: inproceedings
filename: fparith.bib
label: Kohn:1989:TM
author: L. Kohn and S.-W. Fu
title: A 1,000,000 Transistor Microprocessor
crossref: Wuorinen:1989:DTP
pages: 54--55, 290
year: 1989
bibdate: Wed Sep 7 22:32:01 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:01 ???
acknowledgement: ack-nj
rawauthor: L. Kohn and S.-W. Fu
rawtitle: A 1,000,000 Transistor Microprocessor
entry:
@InProceedings{Kohn:1989:TM,
  author =       "L. Kohn and S.-W. Fu",
  title =        "A 1,000,000 Transistor Microprocessor",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "54--55, 290",
  year =         "1989",
  bibdate =      "Wed Sep 7 22:32:01 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Komori:1989:FPE
title: A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1341--1347
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
affiliation: LSI Res. and Dev. Lab., Misubishi Electr. Corp., Hyogo, Japan
thesaurus: Large scale integration; Microprocessor chips; Pipeline processing
rawtitle: A 40-{MFLOPS} 32-bit floating-point processor with elastic pipeline scheme
author:
S. Komori and H. Takata and T. Tamura and F. Asai and T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima and H. Nishikawa and H. Terada

abstract:
The authors present a 40-MFLOPS 32-bit floating-point processor (FP) which is a component chip for a data-driven single-board processor. The FP is the first practical LSI chip which has introduced the elastic pipeline scheme. All parts in the FP are autonomously controlled by self-timed circuits, and no system clock is needed for processing. The elastic pipeline scheme provides data buffering capability and stabilization of circuit operation at the same time. Pipelining has been extensively utilized so that high throughput over 40-MFLOPS can be achieved. An automatic power conservation technique, called `latch mode control', is also described.

keywords:
32 Bit; 40 MFLOPS; Automatic power conservation; Component chip; Data buffering capability; Data-driven single-board processor; Elastic pipeline scheme; Floating-point processor; Latch mode control; LSI chip; Microprocessor; Self-timed circuits; Stabilization

rawabstract:
The authors present a 40-MFLOPS 32-bit floating-point processor (FP) which is a component chip for a data-driven single-board processor. The FP is the first practical LSI chip which has introduced the elastic pipeline scheme. All parts in the FP are autonomously controlled by self-timed circuits, and no system clock is needed for processing. The elastic pipeline scheme provides data buffering capability and stabilization of circuit operation at the same time. Pipelining has been extensively utilized so that high throughput over 40-MFLOPS can be achieved. An automatic power conservation technique, called `latch mode control', is also described.

rawauthor:
S. Komori and H. Takata and T. Tamura and F. Asai and T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima and H. Nishikawa and H. Terada

entry:
@Article{Komori:1989:FPE,
  author =       "S. Komori and H. Takata and T. Tamura and F. Asai and
                 T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima
                 and H. Nishikawa and H. Terada",
  title =        "A 40-{MFLOPS} 32-bit floating-point processor with
                 elastic pipeline scheme",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1341--1347",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The authors present a 40-MFLOPS 32-bit floating-point
                 processor (FP) which is a component chip for a
                 data-driven single-board processor. The FP is the first
                 practical LSI chip which has introduced the elastic
                 pipeline scheme. All parts in the FP are autonomously
                 controlled by self-timed circuits, and no system clock
                 is needed for processing. The elastic pipeline scheme
                 provides data buffering capability and stabilization of
                 circuit operation at the same time. Pipelining has been
                 extensively utilized so that high throughput over
                 40-MFLOPS can be achieved. An automatic power
                 conservation technique, called `latch mode control', is
                 also described.",
  acknowledgement = ack-nhfb,
  affiliation =  "LSI Res. and Dev. Lab., Misubishi Electr. Corp.,
                 Hyogo, Japan",
  classification = "B1265F (Microprocessors and microcomputers); B2570
                 (Semiconductor integrated circuits); C5130
                 (Microprocessor chips)",
  fjournal =     "IEEE Journal of Solid-State Circuits",
  keywords =     "32 Bit; 40 MFLOPS; Automatic power conservation;
                 Component chip; Data buffering capability; Data-driven
                 single-board processor; Elastic pipeline scheme;
                 Floating-point processor; Latch mode control; LSI chip;
                 Microprocessor; Self-timed circuits; Stabilization",
  numericalindex = "Computer speed 4.0E+07 FLOPS; Word length 3.2E+01
                 bit",
  thesaurus =    "Large scale integration; Microprocessor chips;
                 Pipeline processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Komori:1989:MBFa
title: A 40 MFLOPS 32-bit Floating-Point Processor
crossref: Wuorinen:1989:DTP
pages: 46--47, 286
year: 1989
bibdate: Wed Sep 7 22:32:01 1994
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.07 22:32:01 ???
acknowledgement: ack-nj
rawtitle: A 40 {MFLOPS} 32-bit Floating-Point Processor
author:
S. Komori and H. Takata and T. Tamura and F. Asai and T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima and H. Nishikawa and H. Terada

entry:
@InProceedings{Komori:1989:MBFa,
  author =       "S. Komori and H. Takata and T. Tamura and F. Asai and
                 T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima
                 and H. Nishikawa and H. Terada",
  title =        "A 40 {MFLOPS} 32-bit Floating-Point Processor",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "46--47, 286",
  year =         "1989",
  bibdate =      "Wed Sep 7 22:32:01 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nj,
}


bibtype: article
filename: fparith.bib
label: Komori:1989:MBFb
title: A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 24
number: 5
pages: 1341--1347
month: oct
monthnumber: 10
year: 1989
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
rawtitle: A {40-MFLOPS} 32-bit floating-point processor with elastic pipeline scheme
entry:
@Article{Komori:1989:MBFb,
  author =       "S. Komori and H. Takata and T. Tamura and F. Asai and
                 T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima
                 and H. Nishikawa and H. Terada",
  title =        "A {40-MFLOPS} 32-bit floating-point processor with
                 elastic pipeline scheme",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "24",
  number =       "5",
  pages =        "1341--1347",
  month =        oct,
  year =         "1989",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  summary =      "The authors present a 40-MFLOPS 32-bit floating-point
                 processor (FP) which is a component chip for a
                 data-driven single-board processor. The FP is the first
                 practical LSI chip which has introduced the elastic
                 pipeline scheme. All parts in the FP are \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Komori:1989:MFP
title: A 40 MFLOPS 32-bit floating-point processor
crossref: Wuorinen:1989:DTP
pages: 46--47, 286
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Mitsubishi Electr. Corp., Hyogo, Japan
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips; Pipeline processing
rawtitle: A 40 {MFLOPS} 32-bit floating-point processor
abstract:
A 40 MFLOPS (million floating-point operations per second), 32-bit floating-point processor (FP) for a single-board data-driven processor is developed using a pipeline configuration called the elastic pipeline structure. Because there is no need to add controls for pipeline flushing by virtue of the data-driven processing principle, it is possible to employ extensively subdivided pipeline stages. The elastic mode of data transfer between pipeline stages and distributed execution controls along the pipeline result in minimum deterioration of the inherent logic switching speed. The structure of the FP is shown together with details of the ALU (arithmetic logic unit) block. The fabrication process and chip specifications are summarized.

keywords:
32 Bit; 40 MFLOPS; ALU; Chip specifications; CMOS chip; Data transfer; Distributed execution controls; Elastic pipeline structure; Fabrication process; Floating-point processor; Logic switching speed; Pipeline configuration; Single-board data-driven processor; Subdivided pipeline stages

rawabstract:
A 40 MFLOPS (million floating-point operations per second), 32-bit floating-point processor (FP) for a single-board data-driven processor is developed using a pipeline configuration called the elastic pipeline structure. Because there is no need to add controls for pipeline flushing by virtue of the data-driven processing principle, it is possible to employ extensively subdivided pipeline stages. The elastic mode of data transfer between pipeline stages and distributed execution controls along the pipeline result in minimum deterioration of the inherent logic switching speed. The structure of the FP is shown together with details of the ALU (arithmetic logic unit) block. The fabrication process and chip specifications are summarized.

entry:
@InProceedings{Komori:1989:MFP,
  author =       "S. Komori and H. Takata and T. Tamura and F. Asai and
                 T. Ohno and O. Tomisawa and T. Yamasaki and K. Shima
                 and H. Nishikawa and H. Terada",
  title =        "A 40 {MFLOPS} 32-bit floating-point processor",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "46--47, 286",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A 40 MFLOPS (million floating-point operations per
                 second), 32-bit floating-point processor (FP) for a
                 single-board data-driven processor is developed using a
                 pipeline configuration called the elastic pipeline
                 structure. Because there is no need to add controls for
                 pipeline flushing by virtue of the data-driven
                 processing principle, it is possible to employ
                 extensively subdivided pipeline stages. The elastic
                 mode of data transfer between pipeline stages and
                 distributed execution controls along the pipeline
                 result in minimum deterioration of the inherent logic
                 switching speed. The structure of the FP is shown
                 together with details of the ALU (arithmetic logic
                 unit) block. The fabrication process and chip
                 specifications are summarized.",
  acknowledgement = ack-nhfb,
  affiliation =  "Mitsubishi Electr. Corp., Hyogo, Japan",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5220 (Computer architecture); C5230 (Digital
                 arithmetic methods)",
  keywords =     "32 Bit; 40 MFLOPS; ALU; Chip specifications; CMOS
                 chip; Data transfer; Distributed execution controls;
                 Elastic pipeline structure; Fabrication process;
                 Floating-point processor; Logic switching speed;
                 Pipeline configuration; Single-board data-driven
                 processor; Subdivided pipeline stages",
  numericalindex = "Computer speed 4.0E+07 FLOPS; Word length 3.2E+01
                 bit",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips; Pipeline processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Kornerup:1989:ERB
author: Peter Kornerup and David W. Matula
title: Exploiting Redundancy in Bit-Pipelined Rational Arithmetic
crossref: Ercegovac:1989:PSC
pages: 119--126
year: 1989
DOI: https://doi.org/10.1109/ARITH.1989.72817
bibdate: Wed Nov 14 18:29:43 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.14 18:29:43 ???
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Kornerup.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Peter Kornerup and David W. Matula
rawtitle: Exploiting Redundancy in Bit-Pipelined Rational Arithmetic
abstract:
The authors develop and analyze a redundant continued-fraction representation of the rationals in the implementation of an arithmetic unit for computing the sum, difference, product, quotient, and other useful functions of two rational operands. Their representation of operands and results allows the computations of the unit to be performed in a signed bit-serial, online fashion. Several such units can then be interconnected for the computation of more complicated expressions in a pipelined manner. Redundancy is used to help achieve a small bounded online delay and uniform throughput

rawabstract:
The authors develop and analyze a redundant continued-fraction representation of the rationals in the implementation of an arithmetic unit for computing the sum, difference, product, quotient, and other useful functions of two rational operands. Their representation of operands and results allows the computations of the unit to be performed in a signed bit-serial, online fashion. Several such units can then be interconnected for the computation of more complicated expressions in a pipelined manner. Redundancy is used to help achieve a small bounded online delay and uniform throughput

entry:
@InProceedings{Kornerup:1989:ERB,
  author =       "Peter Kornerup and David W. Matula",
  title =        "Exploiting Redundancy in Bit-Pipelined Rational
                 Arithmetic",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "119--126",
  year =         "1989",
  DOI =          "https://doi.org/10.1109/ARITH.1989.72817",
  bibdate =      "Wed Nov 14 18:29:43 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Kornerup.pdf",
  abstract =     "The authors develop and analyze a redundant
                 continued-fraction representation of the rationals in
                 the implementation of an arithmetic unit for computing
                 the sum, difference, product, quotient, and other
                 useful functions of two rational operands. Their
                 representation of operands and results allows the
                 computations of the unit to be performed in a signed
                 bit-serial, online fashion. Several such units can then
                 be interconnected for the computation of more
                 complicated expressions in a pipelined manner.
                 Redundancy is used to help achieve a small bounded
                 online delay and uniform throughput",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Krishna:1989:NAC
author: H. Krishna and Kuo Yu Lin
booktitle: Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989
title: New algorithms for correcting errors in redundant residue number systems
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 653--657
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266586
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: H. Krishna and Kuo Yu Lin
rawbooktitle: Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989
rawtitle: New algorithms for correcting errors in redundant residue number systems
entry:
@InProceedings{Krishna:1989:NAC,
  author =       "H. Krishna and Kuo Yu Lin",
  booktitle =    "Twenty-Third Asilomar Conference on Signals, Systems
                 and Computers, 1989",
  title =        "New algorithms for correcting errors in redundant
                 residue number systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "653--657",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266586",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
}


bibtype: inproceedings
filename: fparith.bib
label: Krishnan:1989:CBN
author: R. Krishnan
booktitle: Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 873--877
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266586
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: R. Krishnan
rawbooktitle: Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989
title:
Conventional binary number system (BNS) versus residue number system (RNS) digital signal processing architecture suitable for complex digital filtering

rawtitle:
Conventional binary number system ({BNS}) versus residue number system ({RNS}) digital signal processing architecture suitable for complex digital filtering

entry:
@InProceedings{Krishnan:1989:CBN,
  author =       "R. Krishnan",
  booktitle =    "Twenty-Third Asilomar Conference on Signals, Systems
                 and Computers, 1989",
  title =        "Conventional binary number system ({BNS}) versus
                 residue number system ({RNS}) digital signal processing
                 architecture suitable for complex digital filtering",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "873--877",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266586",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
}


bibtype: inproceedings
filename: fparith.bib
label: Krishnan:1989:ESA
author: R. Krishnan
booktitle: International Conference on Acoustics, Speech, and Signal Processing, ICASSP-89, 23--26 May 1989
volume: 4
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 2585--2588
year: 1989
DOI: https://doi.org/10.1109/ICASSP.1989.266996
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: R. Krishnan
rawbooktitle: International Conference on Acoustics, Speech, and Signal Processing, {ICASSP-89, 23--26} May 1989
title:
An efficient systolic array VLSI cell architecture for the implementation of transversal filter based on the quadratic residue number systems

rawtitle:
An efficient systolic array {VLSI} cell architecture for the implementation of transversal filter based on the quadratic residue number systems

entry:
@InProceedings{Krishnan:1989:ESA,
  author =       "R. Krishnan",
  booktitle =    "International Conference on Acoustics, Speech, and
                 Signal Processing, {ICASSP-89, 23--26} May 1989",
  title =        "An efficient systolic array {VLSI} cell architecture
                 for the implementation of transversal filter based on
                 the quadratic residue number systems",
  volume =       "4",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2585--2588",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICASSP.1989.266996",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "The author presents efficient direct and indirect
                 implementations of transversal filter architectures
                 using the quadratic residue number system (QRNS). In
                 the case of the direct transversal filter, a systolic
                 array architecture has been developed \ldots{}",
}


bibtype: misc
filename: fparith.bib
label: Kulisch:1989:CGS
author: Ulrich Kulisch and Reinhard Kirchner
title: Circuitry for generating sums, especially scalar products
pages: 2585--2588
day: 12
month: sep
monthnumber: 9
year: 1989
bibdate: Mon Dec 29 16:20:01 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.29 16:20:01 ???
URL: http://www.patentstorm.us/patents/4866653/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 4866653
rawauthor: Ulrich Kulisch and Reinhard Kirchner
rawtitle: Circuitry for generating sums, especially scalar products
abstract:
Circuitry for the summation, especially for generation, of scalar products, to which one summand in floating-point representation is conveyed per machine cycle (ZT), in which, after conversion into fixed point representation, it is received in a summing unit with an accumulator (AS1,-AS4) comprising the whole exponent range. The accumulator is subdivided into row sections, which are longer than the mantissa of the summands. Partial exponents (EPK1,-EPK4) generated in an exponent analyzer (EXA) control the mantissa positioner (PM) or are allocated to the mantissas and delivered continuously and cycle-wise to transfer registers (RE1,-RE4; RVS1,-RVS4; RNS1, RNS4), controlling summation row-wise. The carriers are allocated to the accumulator sections and intermediately stored in carry memory sections (CS1,-CS4) and are not added digit positionwise to the contents of each adjacent memory section until the sum is output, further carries being continuously processed. Afterwards the rounded result mantissa (ME) is generated in transfer registers (RA1, RA2, RPR) arranged downstream and the result exponent (EE) is generated in an exponent generator (EXG).

rawabstract:
Circuitry for the summation, especially for generation, of scalar products, to which one summand in floating-point representation is conveyed per machine cycle (ZT), in which, after conversion into fixed point representation, it is received in a summing unit with an accumulator (AS1,-AS4) comprising the whole exponent range. The accumulator is subdivided into row sections, which are longer than the mantissa of the summands. Partial exponents (EPK1,-EPK4) generated in an exponent analyzer (EXA) control the mantissa positioner (PM) or are allocated to the mantissas and delivered continuously and cycle-wise to transfer registers (RE1,-RE4; RVS1,-RVS4; RNS1, RNS4), controlling summation row-wise. The carriers are allocated to the accumulator sections and intermediately stored in carry memory sections (CS1,-CS4) and are not added digit positionwise to the contents of each adjacent memory section until the sum is output, further carries being continuously processed. Afterwards the rounded result mantissa (ME) is generated in transfer registers (RA1, RA2, RPR) arranged downstream and the result exponent (EE) is generated in an exponent generator (EXG).

entry:
@Misc{Kulisch:1989:CGS,
  author =       "Ulrich Kulisch and Reinhard Kirchner",
  title =        "Circuitry for generating sums, especially scalar
                 products",
  howpublished = "US Patent 4866653",
  day =          "12",
  month =        sep,
  year =         "1989",
  bibdate =      "Mon Dec 29 16:20:01 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/4866653/fulltext.html",
  abstract =     "Circuitry for the summation, especially for
                 generation, of scalar products, to which one summand in
                 floating-point representation is conveyed per machine
                 cycle (ZT), in which, after conversion into fixed point
                 representation, it is received in a summing unit with
                 an accumulator (AS1,-AS4) comprising the whole exponent
                 range. The accumulator is subdivided into row sections,
                 which are longer than the mantissa of the summands.
                 Partial exponents (EPK1,-EPK4) generated in an exponent
                 analyzer (EXA) control the mantissa positioner (PM) or
                 are allocated to the mantissas and delivered
                 continuously and cycle-wise to transfer registers
                 (RE1,-RE4; RVS1,-RVS4; RNS1, RNS4), controlling
                 summation row-wise. The carriers are allocated to the
                 accumulator sections and intermediately stored in carry
                 memory sections (CS1,-CS4) and are not added digit
                 positionwise to the contents of each adjacent memory
                 section until the sum is output, further carries being
                 continuously processed. Afterwards the rounded result
                 mantissa (ME) is generated in transfer registers (RA1,
                 RA2, RPR) arranged downstream and the result exponent
                 (EE) is generated in an exponent generator (EXG).",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lai:1989:HNS
author: F. S. Lai and C. E. Wu
title: A hybrid number system multiplier for graphics and complex arithmetic applications
crossref: IEEE:1989:ISV
pages: 352--356
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: IBM Thomas J. Watson Res Center, Yorktown-Heights, NY, USA
rawauthor: F. S. Lai and C. E. Wu
rawtitle: A hybrid number system multiplier for graphics and complex arithmetic applications
abstract:
A hybrid multiplier design which supports 32-bit floating-point, 24-bit fixed-point and 32-bit logarithmic number systems is described. Except for additions and subtractions, floating-point operations such as multiplication, division, and square root are all performed in the logarithmic number system domain. A modified squaring approach is adopted for fixed-point multiplications with little extra hardware. The performance of this multiplier is shown to be superior to that of conventional binary multipliers for most graphics and digital signal processing applications, and the size of the multiplier is comparable to that of conventional multipliers in terms of silicon area.

keywords:
Complex arithmetic; Digital signal processing; Division; Fixed-point multiplications; Floating-point operations; Graphics; Hybrid number system multiplier; Logarithmic number; Modified squaring approach; Multiplication; Square root

thesaurus:
Computer graphic equipment; Computerised signal processing; Digital arithmetic; Multiplying circuits

rawabstract:
A hybrid multiplier design which supports 32-bit floating-point, 24-bit fixed-point and 32-bit logarithmic number systems is described. Except for additions and subtractions, floating-point operations such as multiplication, division, and square root are all performed in the logarithmic number system domain. A modified squaring approach is adopted for fixed-point multiplications with little extra hardware. The performance of this multiplier is shown to be superior to that of conventional binary multipliers for most graphics and digital signal processing applications, and the size of the multiplier is comparable to that of conventional multipliers in terms of silicon area.

entry:
@InProceedings{Lai:1989:HNS,
  author =       "F. S. Lai and C. E. Wu",
  title =        "A hybrid number system multiplier for graphics and
                 complex arithmetic applications",
  crossref =     "IEEE:1989:ISV",
  pages =        "352--356",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A hybrid multiplier design which supports 32-bit
                 floating-point, 24-bit fixed-point and 32-bit
                 logarithmic number systems is described. Except for
                 additions and subtractions, floating-point operations
                 such as multiplication, division, and square root are
                 all performed in the logarithmic number system domain.
                 A modified squaring approach is adopted for fixed-point
                 multiplications with little extra hardware. The
                 performance of this multiplier is shown to be superior
                 to that of conventional binary multipliers for most
                 graphics and digital signal processing applications,
                 and the size of the multiplier is comparable to that of
                 conventional multipliers in terms of silicon area.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Thomas J. Watson Res Center, Yorktown-Heights, NY,
                 USA",
  classification = "B1265B (Logic circuits); C5230 (Digital arithmetic
                 methods); C5260 (Digital signal processing); C5540
                 (Terminals and graphic displays)",
  keywords =     "Complex arithmetic; Digital signal processing;
                 Division; Fixed-point multiplications; Floating-point
                 operations; Graphics; Hybrid number system multiplier;
                 Logarithmic number; Modified squaring approach;
                 Multiplication; Square root",
  thesaurus =    "Computer graphic equipment; Computerised signal
                 processing; Digital arithmetic; Multiplying circuits",
}


bibtype: inproceedings
filename: fparith.bib
label: Langston:1989:DBT
author: J. L. Langston and K. Hinman
title: Digital beamforming techniques and processors based on quadratic residue number system techniques
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 609--614
year: 1989
DOI: https://doi.org/10.1109/MILCOM.1989.103997
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: J. L. Langston and K. Hinman
rawtitle: Digital beamforming techniques and processors based on quadratic residue number system techniques
booktitle:
IEEE Military Communications Conference, 1989. MILCOM '89. Conference Record. Bridging the Gap. Interoperability, Survivability, Security, 1989

rawbooktitle:
{IEEE} Military Communications Conference, 1989. {MILCOM '89}. Conference Record. Bridging the Gap. Interoperability, Survivability, Security, 1989

entry:
@InProceedings{Langston:1989:DBT,
  author =       "J. L. Langston and K. Hinman",
  booktitle =    "{IEEE} Military Communications Conference, 1989.
                 {MILCOM '89}. Conference Record. Bridging the Gap.
                 Interoperability, Survivability, Security, 1989",
  title =        "Digital beamforming techniques and processors based on
                 quadratic residue number system techniques",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "609--614",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MILCOM.1989.103997",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A very-high-performance digital beamforming processor
                 has been implemented using ASICs (application-specific
                 integrated circuits) fabricated in readily available
                 commercial CMOS process technology by using QRNS
                 (quadratic residue number system) \ldots{}",
}


bibtype: techreport
filename: fparith.bib
label: Lee:1989:FIR
author: Jeong-A Lee and Tomas Lang
title: Floating-point implementation of redundant CORDIC for QR decomposition
type: Technical report
number: CSD-890044
institution: Computer Science Dept., University of California
address: Los Angeles, CA, USA
pages: 15 + 8
year: 1989
bibdate: Sat Feb 24 15:01:45 MST 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1996.02.24 15:01:45 MST
keywords: Decomposition method.; Matrices.
remark: ``July 1989.'' Supported by the National Science Foundation.
acknowledgement: ack-nhfb
rawauthor: Jeong-A Lee and Tomas Lang
rawtitle: Floating-point implementation of redundant {CORDIC} for {QR} decomposition
entry:
@TechReport{Lee:1989:FIR,
  author =       "Jeong-A Lee and Tomas Lang",
  title =        "Floating-point implementation of redundant {CORDIC}
                 for {QR} decomposition",
  type =         "Technical report",
  number =       "CSD-890044",
  institution =  "Computer Science Dept., University of California",
  address =      "Los Angeles, CA, USA",
  pages =        "15 + 8",
  year =         "1989",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Decomposition method.; Matrices.",
  remark =       "``July 1989.'' Supported by the National Science
                 Foundation.",
}


bibtype: article
filename: fparith.bib
label: Lee:1989:MGR
author: Corinna Lee
title: Multistep Gradual Rounding
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 4
pages: 595--600
month: apr
monthnumber: 4
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.21152
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:39 MDT 2011
bibtimestamp: 2011.07.08 19:00:39 MDT
fjournal: IEEE Transactions on Computers
keywords: double rounding
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Corinna Lee
rawtitle: Multistep Gradual Rounding
URL:
http://dlib.computer.org/tc/books/tc1989/pdf/t0593.pdf; http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=21152; http://www.computer.org/tc/tc1989/t0595abs.htm

abstract:
A value $V$ is to be rounded to an arbitrary precision resulting in the value $ V' $. Conventional rounding technique uses one step to accomplish this. Alternatively, em multistep rounding uses several steps to round the value $V$ to successively shorter precisions with the final rounding step producing the desired value $ V' $. This alternate rounding method is one way to implement, with the minimum of hardware, the denormalization process that the IEEE Floating-Point Standard 754 requires when underflow occurs. There are certain cases for which multistep rounding produces a different result than single-step rounding. To prevent such a em step error, the author introduces a rounding procedure called em gradual rounding that is very similar to conventional rounding with the addition of two tag bits associated with each floating-point register.

rawabstract:
A value $V$ is to be rounded to an arbitrary precision resulting in the value $ V' $. Conventional rounding technique uses one step to accomplish this. Alternatively, {\em multistep rounding\/} uses several steps to round the value $V$ to successively shorter precisions with the final rounding step producing the desired value $ V' $. This alternate rounding method is one way to implement, with the minimum of hardware, the denormalization process that the IEEE Floating-Point Standard 754 requires when underflow occurs. There are certain cases for which multistep rounding produces a different result than single-step rounding. To prevent such a {\em step error}, the author introduces a rounding procedure called {\em gradual rounding} that is very similar to conventional rounding with the addition of two tag bits associated with each floating-point register.

entry:
@Article{Lee:1989:MGR,
  author =       "Corinna Lee",
  title =        "Multistep Gradual Rounding",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "4",
  pages =        "595--600",
  month =        apr,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.21152",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:39 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "http://dlib.computer.org/tc/books/tc1989/pdf/t0593.pdf;
                 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=21152;
                 http://www.computer.org/tc/tc1989/t0595abs.htm",
  abstract =     "A value $V$ is to be rounded to an arbitrary precision
                 resulting in the value $ V' $. Conventional rounding
                 technique uses one step to accomplish this.
                 Alternatively, {\em multistep rounding\/} uses several
                 steps to round the value $V$ to successively shorter
                 precisions with the final rounding step producing the
                 desired value $ V' $. This alternate rounding method is
                 one way to implement, with the minimum of hardware, the
                 denormalization process that the IEEE Floating-Point
                 Standard 754 requires when underflow occurs. There are
                 certain cases for which multistep rounding produces a
                 different result than single-step rounding. To prevent
                 such a {\em step error}, the author introduces a
                 rounding procedure called {\em gradual rounding} that
                 is very similar to conventional rounding with the
                 addition of two tag bits associated with each
                 floating-point register.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "double rounding",
}


bibtype: article
filename: fparith.bib
label: Lee:1989:QCC
author: Jon Lee
title: A quirk of the CRAY CFT77 compiler: IF (logical) in lieu of IF (arithmetic)
journal: j-J-SUPERCOMPUTING
volume: 3
number: 4
pages: 351--355
month: dec
monthnumber: 12
year: 1989
CODEN: JOSUED
DOI: https://doi.org/10.1007/BF00128170
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Wed Jul 6 11:13:01 MDT 2005
bibtimestamp: 2005.07.06 11:13:01 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0920-8542&volume=3&issue=4&spage=351
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
affiliation: Flight Dynamics Lab., Wright-Patterson AFB, OH, USA
corpsource: Flight Dynamics Lab., Wright-Patterson AFB, OH, USA
journalURL: http://link.springer.com/journal/11227
treatment: X Experimental
rawauthor: Jon Lee
rawtitle: A quirk of the {CRAY CFT77} compiler: {IF} (logical) in lieu of {IF} (arithmetic)
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0920-8542&volume=3&issue=4; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
CFT77 compiler; CIVIC; computational fluid dynamics code; conditional IF exit; DO-loops; homogeneous turbulence; optimised code; parallel programming; program compilers; vectorization

entry:
@Article{Lee:1989:QCC,
  author =       "Jon Lee",
  title =        "A quirk of the {CRAY CFT77} compiler: {IF} (logical)
                 in lieu of {IF} (arithmetic)",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "3",
  number =       "4",
  pages =        "351--355",
  month =        dec,
  year =         "1989",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/BF00128170",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Wed Jul 6 11:13:01 MDT 2005",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0920-8542&volume=3&issue=4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0920-8542&volume=3&issue=4&spage=351",
  acknowledgement = ack-nhfb,
  affiliation =  "Flight Dynamics Lab., Wright-Patterson AFB, OH, USA",
  classification = "C5440 (Multiprocessor systems and techniques); C6110
                 (Systems analysis and programming); C6150C (Compilers,
                 interpreters and other processors); C7440 (Civil and
                 mechanical engineering)",
  corpsource =   "Flight Dynamics Lab., Wright-Patterson AFB, OH, USA",
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
  keywords =     "CFT77 compiler; CIVIC; computational fluid dynamics
                 code; conditional IF exit; DO-loops; homogeneous
                 turbulence; optimised code; parallel programming;
                 program compilers; vectorization",
  treatment =    "X Experimental",
}


bibtype: book
filename: fparith.bib
label: Levy:1989:CPA
author: Henry M. Levy and Richard H. Eckhouse, Jr.
title: Computer programming and architecture: the VAX
publisher: pub-DP
address: pub-DP:adr
edition: Second
pages: xix + 444
year: 1989
ISBN: 1-55558-015-7 OR 1555580157
ISBN13: 978-1-55558-015-5 OR 9781555580155
LCCN: QA76.8.V32 L48 1989
bibdate: Wed Sep 14 22:51:31 1994
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1994.09.14 22:51:31 ???
acknowledgement: ack-nhfb
rawauthor: Henry M. Levy and Richard H. {Eckhouse, Jr.}
rawtitle: Computer programming and architecture: the {VAX}
entry:
@Book{Levy:1989:CPA,
  author =       "Henry M. Levy and Richard H. {Eckhouse, Jr.}",
  title =        "Computer programming and architecture: the {VAX}",
  publisher =    pub-DP,
  address =      pub-DP:adr,
  edition =      "Second",
  pages =        "xix + 444",
  year =         "1989",
  ISBN =         "1-55558-015-7",
  ISBN-13 =      "978-1-55558-015-5",
  LCCN =         "QA76.8.V32 L48 1989",
  bibdate =      "Wed Sep 14 22:51:31 1994",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lewis:1989:ADB
author: D. M. Lewis and L. K. Yu
title: Algorithm design for a 30-bit integrated logarithmic processor
crossref: Ercegovac:1989:PSC
pages: 192--199
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Lewis.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: D. M. Lewis and L. K. Yu
rawtitle: Algorithm design for a 30-bit integrated logarithmic processor
entry:
@InProceedings{Lewis:1989:ADB,
  author =       "D. M. Lewis and L. K. Yu",
  title =        "Algorithm design for a 30-bit integrated logarithmic
                 processor",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "192--199",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Lewis.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Lin:1989:LCA
author: H. Lin and H. J. Sips
title: On-line CORDIC algorithms
crossref: Ercegovac:1989:PSC
pages: 26--33
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Lin.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: H. Lin and H. J. Sips
rawtitle: On-line {CORDIC} algorithms
entry:
@InProceedings{Lin:1989:LCA,
  author =       "H. Lin and H. J. Sips",
  title =        "On-line {CORDIC} algorithms",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "26--33",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Lin.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Lo:1989:CED
author: J.-C. Lo and S. Thanawastien and T. R. N. Rao
title: Concurrent error detection in arithmetic and logical operations using Berger codes
crossref: Ercegovac:1989:PSC
pages: 233--240
year: 1989
bibdate: Sat Nov 27 14:19:10 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.27 14:19:10 MST
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Lo.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: J.-C. Lo and S. Thanawastien and T. R. N. Rao
rawtitle: Concurrent error detection in arithmetic and logical operations using {Berger} codes
entry:
@InProceedings{Lo:1989:CED,
  author =       "J.-C. Lo and S. Thanawastien and T. R. N. Rao",
  title =        "Concurrent error detection in arithmetic and logical
                 operations using {Berger} codes",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "233--240",
  year =         "1989",
  bibdate =      "Sat Nov 27 14:19:10 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Lo.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
}


bibtype: inproceedings
filename: fparith.bib
label: Lu:1989:VMI
author: P. Y. Lu and K. Dawallu
title: A VLSI Module for IEEE Floating-Point Multiplication / Division / Square Root
crossref: IEEE:1989:PII
pages: 366--368
year: 1989
bibdate: Wed Nov 06 12:08:38 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.06 12:08:38 ???
acknowledgement: ack-nhfb
affiliation: LSI Logic Corp., Menlo Park, CA, USA
bookpages: xvii + 587
rawauthor: P. Y. Lu and K. Dawallu
rawtitle: A {VLSI} Module for {IEEE} Floating-Point Multiplication\slash Division\slash Square Root
abstract:
The major objective of this VLSI module design is to determine how to modify a fast floating-point multiplier so that it can perform division and square root in accordance with IEEE standards. This has been achieved by applying the Newton-Ralphson iteration only on the mantissa and adjusting the iterated result by a rounding algorithm. Using 1.0- mu m CMOS standard cell technology, the total area of this module is approximately 7.0 mm*6.5 mm, which is just 25% larger than the floating-point multiplier. The module can compute multiplication, division, and square root in 3, 31, and 43 cycles, respectively. The cycle time, under nominal conditions, is expected to be 20 ns. (2 Refs.)

keywords:
1 Micron; 20 Ns; 7 To 6.5 mm; CMOS standard cell technology; Cycle time; Fast floating-point multiplier; Floating point division; Floating point square root; IEEE standards; Iterated result; Mantissa; Multiplier modification; Newton-Ralphson iteration; Rounding algorithm; VLSI module design

thesaurus:
Cellular arrays; CMOS integrated circuits; Digital arithmetic; Dividing circuits; Iterative methods; Modules; Multiplying circuits; VLSI

rawabstract:
The major objective of this VLSI module design is to determine how to modify a fast floating-point multiplier so that it can perform division and square root in accordance with IEEE standards. This has been achieved by applying the Newton-Ralphson iteration only on the mantissa and adjusting the iterated result by a rounding algorithm. Using 1.0- mu m CMOS standard cell technology, the total area of this module is approximately 7.0 mm*6.5 mm, which is just 25\% larger than the floating-point multiplier. The module can compute multiplication, division, and square root in 3, 31, and 43 cycles, respectively. The cycle time, under nominal conditions, is expected to be 20 ns. (2 Refs.)

entry:
@InProceedings{Lu:1989:VMI,
  author =       "P. Y. Lu and K. Dawallu",
  title =        "A {VLSI} Module for {IEEE} Floating-Point
                 Multiplication\slash Division\slash Square Root",
  crossref =     "IEEE:1989:PII",
  bookpages =    "xvii + 587",
  pages =        "366--368",
  year =         "1989",
  bibdate =      "Wed Nov 06 12:08:38 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The major objective of this VLSI module design is to
                 determine how to modify a fast floating-point
                 multiplier so that it can perform division and square
                 root in accordance with IEEE standards. This has been
                 achieved by applying the Newton-Ralphson iteration only
                 on the mantissa and adjusting the iterated result by a
                 rounding algorithm. Using 1.0- mu m CMOS standard cell
                 technology, the total area of this module is
                 approximately 7.0 mm*6.5 mm, which is just 25\% larger
                 than the floating-point multiplier. The module can
                 compute multiplication, division, and square root in 3,
                 31, and 43 cycles, respectively. The cycle time, under
                 nominal conditions, is expected to be 20 ns. (2
                 Refs.)",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "LSI Logic Corp., Menlo Park, CA, USA",
  classification = "B1265B (Logic circuits); B2570D (CMOS integrated
                 circuits); C4130 (Interpolation and function
                 approximation); C5230 (Digital arithmetic methods)",
  keywords =     "1 Micron; 20 Ns; 7 To 6.5 mm; CMOS standard cell
                 technology; Cycle time; Fast floating-point multiplier;
                 Floating point division; Floating point square root;
                 IEEE standards; Iterated result; Mantissa; Multiplier
                 modification; Newton-Ralphson iteration; Rounding
                 algorithm; VLSI module design",
  numericalindex = "Time 2.0E-08 s; Size 1.0E-06 m; Size 6.5E-03 to
                 7.0E-03 m",
  thesaurus =    "Cellular arrays; CMOS integrated circuits; Digital
                 arithmetic; Dividing circuits; Iterative methods;
                 Modules; Multiplying circuits; VLSI",
}


bibtype: inproceedings
filename: fparith.bib
label: Malarkey:1989:RNS
title: Residue-number-system-based optical adaptive processor
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 620--623
year: 1989
DOI: https://doi.org/10.1109/MILCOM.1989.103999
bibdate: Fri Nov 9 11:38:58 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:58 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawtitle: Residue-number-system-based optical adaptive processor
author:
E. C. Malarkey and G. E. Marx and J. D. Fogarty and D. Mergerian and H. K. Hahn and J. C. Bradley and P. R. Beaudet and R. Fenton

booktitle:
IEEE Military Communications Conference, 1989. MILCOM '89. Conference Record. Bridging the Gap. Interoperability, Survivability, Security, 1989

rawauthor:
E. C. Malarkey and G. E. Marx and J. D. Fogarty and D. Mergerian and H. K. Hahn and J. C. Bradley and P. R. Beaudet and R. Fenton

rawbooktitle:
{IEEE} Military Communications Conference, 1989. {MILCOM '89}. Conference Record. Bridging the Gap. Interoperability, Survivability, Security, 1989

entry:
@InProceedings{Malarkey:1989:RNS,
  author =       "E. C. Malarkey and G. E. Marx and J. D. Fogarty and D.
                 Mergerian and H. K. Hahn and J. C. Bradley and P. R.
                 Beaudet and R. Fenton",
  booktitle =    "{IEEE} Military Communications Conference, 1989.
                 {MILCOM '89}. Conference Record. Bridging the Gap.
                 Interoperability, Survivability, Security, 1989",
  title =        "Residue-number-system-based optical adaptive
                 processor",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "620--623",
  year =         "1989",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MILCOM.1989.103999",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:58 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "An optical adaptive processor with 4 degrees of
                 freedom is under development. This processor is based
                 upon the use of optical lookup tables and operates
                 within the residue number system to provide adaptive
                 tap weights for nulling applications. The \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Mansour:1989:CAS
author: Y. Mansour and B. Schieber and P. Tiwari
booktitle: 30th Annual Symposium on Foundations of Computer Science, 1989
title: The complexity of approximating the square root
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 325--330
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
acknowledgement: ack-nhfb
rawauthor: Y. Mansour and B. Schieber and P. Tiwari
rawbooktitle: 30th Annual Symposium on Foundations of Computer Science, 1989
rawtitle: The complexity of approximating the square root
entry:
@InProceedings{Mansour:1989:CAS,
  author =       "Y. Mansour and B. Schieber and P. Tiwari",
  booktitle =    "30th Annual Symposium on Foundations of Computer
                 Science, 1989",
  title =        "The complexity of approximating the square root",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "325--330",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "The authors prove upper and lower bounds for
                 approximately computing the square root using a given
                 set of operations. The bounds are extended to hold for
                 approximating the kth root, for any fixed k. Several
                 tools from approximation \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Marshall:1989:TUT
author: Mark Marshall
title: Techniques for user testing of the 68882
journal: j-MICROPROC-MICROSYS
volume: 13
number: 6
pages: 382--386
month: jul
monthnumber: 7
year: 1989
CODEN: MIMID5
ISSN: 0141-9331 (print), 1872-9436 (electronic) OR 01419331 (print), 18729436 (electronic)
ISSNL: 0141-9331 OR 01419331
bibdate: Sat Nov 9 08:26:18 MST 2002
bibsource: ACM Computing Archive CD-ROM database (1991); https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.09 08:26:18 MST
fjournal: Microprocessors and Microsystems
keywords: floating-point testing
acknowledgement: ack-nhfb
affiliation: NCR Corp., Wichita, KS
reviewer: E. Mallach
rawauthor: Mark Marshall
rawtitle: Techniques for user testing of the 68882
subject:
B. Hardware; B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION; C. Computer Systems Organization; C.5 COMPUTER SYSTEM IMPLEMENTATION; B. Hardware; B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION

entry:
@Article{Marshall:1989:TUT,
  author =       "Mark Marshall",
  title =        "Techniques for user testing of the 68882",
  journal =      j-MICROPROC-MICROSYS,
  volume =       "13",
  number =       "6",
  pages =        "382--386",
  month =        jul # "\slash " # aug,
  year =         "1989",
  CODEN =        "MIMID5",
  ISSN =         "0141-9331 (print), 1872-9436 (electronic)",
  ISSN-L =       "0141-9331",
  bibdate =      "Sat Nov 9 08:26:18 MST 2002",
  bibsource =    "ACM Computing Archive CD-ROM database (1991);
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "NCR Corp., Wichita, KS",
  bibno =        "72545",
  catcode =      "B.5.3; C.5.3; B.5.1",
  content =      "This short, clearly written paper describes how NCR
                 Corporation developed a series of programs to test the
                 Motorola 68882 floating-point coprocessor for
                 Motorola's 68020 and 68030 microprocessors. Integrated
                 circuits are tested for two reasons: to ensure that a
                 properly working unit meets its specifications, and to
                 ensure that a particular unit works properly. As
                 Marshall points out, manufacturers cannot always be
                 relied upon to perform either of these tests perfectly.
                 The programs described in this paper have been used
                 both to monitor the quality of incoming parts and to
                 verify that device mask or specification changes do not
                 effect the part's usability for NCR's
                 purposes.\par

                 This paper describes the methods by which NCR's
                 2700-instruction, 550,000-clock cycle test program was
                 developed and how it works. Since the internal workings
                 of the 68882 are not visible to the user, NCR adopted
                 the functional testing approach. Of particular interest
                 is NCR's sequential approach to the testing proper,
                 which assumes that ``no element is functional unless
                 previously tested.'' While the specifics of each step
                 vary from one microprocessor to another, the principles
                 still apply.\par

                 This is not a research paper. It does not disclose
                 startling new results or advance the frontiers of human
                 knowledge. It does show how state-of-the-art
                 engineering practice can achieve desirable \ldots{}",
  CRclass =      "B.5.3 Reliability and Testing; B.5.3 Test generation;
                 C.5.3 Microcomputers; B.5.1 Design",
  CRnumber =     "9006-0473",
  descriptor =   "Hardware, REGISTER-TRANSFER-LEVEL IMPLEMENTATION,
                 Reliability and Testing, Test generation; Computer
                 Systems Organization, COMPUTER SYSTEM IMPLEMENTATION,
                 Microcomputers; Hardware, REGISTER-TRANSFER-LEVEL
                 IMPLEMENTATION, Design",
  fjournal =     "Microprocessors and Microsystems",
  genterm =      "ALGORITHMS; DESIGN; VERIFICATION",
  guideno =      "1989-09211",
  journalabbrev = "Microprocess. Microsyst.",
  keywords =     "floating-point testing",
  reviewer =     "E. Mallach",
  subject =      "B. Hardware; B.5 REGISTER-TRANSFER-LEVEL
                 IMPLEMENTATION; C. Computer Systems Organization; C.5
                 COMPUTER SYSTEM IMPLEMENTATION; B. Hardware; B.5
                 REGISTER-TRANSFER-LEVEL IMPLEMENTATION",
}


bibtype: article
filename: fparith.bib
label: Mastrovito:1989:VDM
author: E. D. Mastrovito
title: VLSI designs for multiplication over finite fields $ mathrm GF(2^m) $
journal: j-LECT-NOTES-COMP-SCI
volume: 357
pages: 397--309
year: 1989
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Fri Jun 24 21:09:00 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 21:09:00 ???
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: E. D. Mastrovito
rawtitle: {VLSI} designs for multiplication over finite fields {$ \mathrm {GF}(2^m) $}
entry:
@Article{Mastrovito:1989:VDM,
  author =       "E. D. Mastrovito",
  title =        "{VLSI} designs for multiplication over finite fields
                 {$ \mathrm {GF}(2^m) $}",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "357",
  pages =        "397--309",
  year =         "1989",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Fri Jun 24 21:09:00 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Maytal:1989:DCG
author: B. Maytal and S. Iacobovici and D. B. Alpert and D. Biran and J. Levy and S. Y. Tov
title: Design considerations for a general-purpose microprocessor
journal: j-COMPUTER
volume: 22
number: 1
pages: 66--76
month: jan
monthnumber: 1
year: 1989
CODEN: CPTRB4
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Sat Sep 14 07:29:35 MDT 1996
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; Misc/IMMD_IV.bib
bibtimestamp: 1996.09.14 07:29:35 MDT
fjournal: Computer
acknowledgement: ack-nhfb
affiliation: Nat. Semicond., Santa Clara, CA, USA
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
thesaurus: Computer architecture; Microcomputers; Microprocessor chips
rawauthor: B. Maytal and S. Iacobovici and D. B. Alpert and D. Biran and J. Levy and S. Y. Tov
rawtitle: Design considerations for a general-purpose microprocessor
keywords:
32 Bit; Clock frequency; Data-flow monitoring mechanisms; Floating-point operations; General-purpose microprocessor; Instruction-flow; Market requirements; Memory hierarchy; Memory reference transactions; Microarchitecture; Multiprocessing support; NS 32532; On-chip caches; Packaging technologies; Pipeline; System interface; Target applications; VLSI

entry:
@Article{Maytal:1989:DCG,
  author =       "B. Maytal and S. Iacobovici and D. B. Alpert and D.
                 Biran and J. Levy and S. Y. Tov",
  title =        "Design considerations for a general-purpose
                 microprocessor",
  journal =      j-COMPUTER,
  volume =       "22",
  number =       "1",
  pages =        "66--76",
  month =        jan,
  year =         "1989",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Sat Sep 14 07:29:35 MDT 1996",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 Misc/IMMD_IV.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Nat. Semicond., Santa Clara, CA, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture)",
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "32 Bit; Clock frequency; Data-flow monitoring
                 mechanisms; Floating-point operations; General-purpose
                 microprocessor; Instruction-flow; Market requirements;
                 Memory hierarchy; Memory reference transactions;
                 Microarchitecture; Multiprocessing support; NS 32532;
                 On-chip caches; Packaging technologies; Pipeline;
                 System interface; Target applications; VLSI",
  numericalindex = "Word length 3.2E+01 bit",
  thesaurus =    "Computer architecture; Microcomputers; Microprocessor
                 chips",
}


bibtype: inproceedings
filename: fparith.bib
label: Milenkovic:1989:DPG
author: V. Milenkovic
booktitle: 30th Annual Symposium on Foundations of Computer Science, 1989
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 500--505
year: 1989
bibdate: Sat Jul 16 11:25:03 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:03 MDT
acknowledgement: ack-nhfb
rawauthor: V. Milenkovic
rawbooktitle: 30th Annual Symposium on Foundations of Computer Science, 1989
title:
Double precision geometry: a general technique for calculating line and segment intersections using rounded arithmetic

rawtitle:
Double precision geometry: a general technique for calculating line and segment intersections using rounded arithmetic

entry:
@InProceedings{Milenkovic:1989:DPG,
  author =       "V. Milenkovic",
  booktitle =    "30th Annual Symposium on Foundations of Computer
                 Science, 1989",
  title =        "Double precision geometry: a general technique for
                 calculating line and segment intersections using
                 rounded arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "500--505",
  year =         "1989",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:03 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "For the first time it is shown how to reduce the cost
                 of performing specific geometric constructions by using
                 rounded arithmetic instead of exact arithmetic. By
                 exploiting a property of floating-point arithmetic
                 called monotonicity, a technique \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Milutinovic:1989:MSD
author: V. Milutinovic and M. Bettinger and W. Helbig
title: Multiplier / shifter design tradeoffs in a 32-bit microprocessor
journal: j-IEEE-TRANS-COMPUT
volume: 38
number: 6
pages: 874--880
month: jun
monthnumber: 6
year: 1989
CODEN: ITCOB4
DOI: https://doi.org/10.1109/12.24298
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 8 19:00:40 MDT 2011
bibtimestamp: 2011.07.08 19:00:40 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=24298
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: V. Milutinovic and M. Bettinger and W. Helbig
rawtitle: Multiplier\slash shifter design tradeoffs in a 32-bit microprocessor
entry:
@Article{Milutinovic:1989:MSD,
  author =       "V. Milutinovic and M. Bettinger and W. Helbig",
  title =        "Multiplier\slash shifter design tradeoffs in a 32-bit
                 microprocessor",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "38",
  number =       "6",
  pages =        "874--880",
  month =        jun,
  year =         "1989",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/12.24298",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 8 19:00:40 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput1980.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=24298",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Molnar:1989:MBF
author: K. Molnar and C.-Y. Ho and D. Staver and B. Davis and R. Jerdonek
title: A 40 MHz 64-Bit Floating-Point Co-Processor
crossref: Wuorinen:1989:DTP
pages: 48--49, 287
year: 1989
bibdate: Tue Dec 12 09:17:24 MST 1995
bibsource: ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 1995.12.12 09:17:24 MST
acknowledgement: ack-nhfb
affiliation: Gen. Electr. Corp. Res. and Dev. Center, Schenectady, NY, USA
thesaurus: CMOS integrated circuits; Digital arithmetic; Microprocessor chips
rawauthor: K. Molnar and C.-Y. Ho and D. Staver and B. Davis and R. Jerdonek
rawtitle: A 40 {MHz} 64-Bit Floating-Point Co-Processor
abstract:
An arithmetic coprocessor capable of executing 64-bit double-precision floating-point, 32-bit single-precision floating-point, and 32-bit integer instructions has been integrated onto a 1.0-cm*1.1-cm chip in a 1.2- mu m, single-poly, double-metal bulk CMOS process. The chip contains 17000 transistors and includes a register file, two accumulators, and separate interface, multiplication, and addition subprocessors. The coprocessor which is the arithmetic unit for a multichip microprocessor system, is packaged in a 132-pin leadless ceramic chip carrier. The coprocessor can be issued a new instruction each 25-ns clock cycle, and 64-bit double-precision arithmetic with full IEEE rounding is executed at a peak rate of 26.7 MFLOPs (million floating-point operations per second). The waveforms of a store instruction operating at 40 MHz are shown.

keywords:
1.2 Micron; 26.7 MFLOPS; 32-Bit integer instructions; 40 MHz; 64 Bit; Accumulators; Addition subprocessors; Arithmetic coprocessor; Double-metal bulk CMOS process; Double-precision floating-point; Floating point coprocessor; Interface subprocessor; Leadless ceramic chip carrier; Multichip microprocessor system; Multiplication subprocessor; Peak rate; Register file; Single-precision floating-point; Store instruction; Waveforms

rawabstract:
An arithmetic coprocessor capable of executing 64-bit double-precision floating-point, 32-bit single-precision floating-point, and 32-bit integer instructions has been integrated onto a 1.0-cm*1.1-cm chip in a 1.2- mu m, single-poly, double-metal bulk CMOS process. The chip contains 17000 transistors and includes a register file, two accumulators, and separate interface, multiplication, and addition subprocessors. The coprocessor which is the arithmetic unit for a multichip microprocessor system, is packaged in a 132-pin leadless ceramic chip carrier. The coprocessor can be issued a new instruction each 25-ns clock cycle, and 64-bit double-precision arithmetic with full IEEE rounding is executed at a peak rate of 26.7 MFLOPs (million floating-point operations per second). The waveforms of a store instruction operating at 40 MHz are shown.

entry:
@InProceedings{Molnar:1989:MBF,
  author =       "K. Molnar and C.-Y. Ho and D. Staver and B. Davis and
                 R. Jerdonek",
  title =        "A 40 {MHz} 64-Bit Floating-Point Co-Processor",
  crossref =     "Wuorinen:1989:DTP",
  pages =        "48--49, 287",
  year =         "1989",
  bibdate =      "Tue Dec 12 09:17:24 MST 1995",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "An arithmetic coprocessor capable of executing 64-bit
                 double-precision floating-point, 32-bit
                 single-precision floating-point, and 32-bit integer
                 instructions has been integrated onto a 1.0-cm*1.1-cm
                 chip in a 1.2- mu m, single-poly, double-metal bulk
                 CMOS process. The chip contains 17000 transistors and
                 includes a register file, two accumulators, and
                 separate interface, multiplication, and addition
                 subprocessors. The coprocessor which is the arithmetic
                 unit for a multichip microprocessor system, is packaged
                 in a 132-pin leadless ceramic chip carrier. The
                 coprocessor can be issued a new instruction each 25-ns
                 clock cycle, and 64-bit double-precision arithmetic
                 with full IEEE rounding is executed at a peak rate of
                 26.7 MFLOPs (million floating-point operations per
                 second). The waveforms of a store instruction operating
                 at 40 MHz are shown.",
  acknowledgement = ack-nhfb # " and " # ack-nj,
  affiliation =  "Gen. Electr. Corp. Res. and Dev. Center, Schenectady,
                 NY, USA",
  classification = "B1265F (Microprocessors and microcomputers); B2570D
                 (CMOS integrated circuits); C5130 (Microprocessor
                 chips); C5230 (Digital arithmetic methods)",
  keywords =     "1.2 Micron; 26.7 MFLOPS; 32-Bit integer instructions;
                 40 MHz; 64 Bit; Accumulators; Addition subprocessors;
                 Arithmetic coprocessor; Double-metal bulk CMOS process;
                 Double-precision floating-point; Floating point
                 coprocessor; Interface subprocessor; Leadless ceramic
                 chip carrier; Multichip microprocessor system;
                 Multiplication subprocessor; Peak rate; Register file;
                 Single-precision floating-point; Store instruction;
                 Waveforms",
  numericalindex = "Frequency 4.0E+07 Hz; Word length 6.4E+01 bit; Size
                 1.2E-06 m; Computer speed 2.67E+07 FLOPS",
  thesaurus =    "CMOS integrated circuits; Digital arithmetic;
                 Microprocessor chips",
}


bibtype: inproceedings
filename: fparith.bib
label: Montuschi:1989:EIH
author: Paolo Montuschi and Luigi Cinimera
title: On the efficient implementation of higher radix square root algorithms
crossref: Ercegovac:1989:PSC
pages: 154--161
year: 1989
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
URL: http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Montuschi.pdf
keywords: ARITH-9
acknowledgement: ack-nhfb
rawauthor: Paolo Montuschi and Luigi Cinimera
rawtitle: On the efficient implementation of higher radix square root algorithms
entry:
@InProceedings{Montuschi:1989:EIH,
  author =       "Paolo Montuschi and Luigi Cinimera",
  title =        "On the efficient implementation of higher radix square
                 root algorithms",
  crossref =     "Ercegovac:1989:PSC",
  pages =        "154--161",
  year =         "1989",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith9/papers/ARITH9_Montuschi.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-9",
  summary =      "Square root nonrestoring algorithms operating with a
                 radix higher than two (but power of 2) are discussed.
                 Formulas are derived delimiting the feasibility space
                 of the class of algorithms considered as a function of
                 the different parameters. This \ldots{}",
}


bibtype: book
filename: fparith.bib
label: Moshier:1989:MPM
author: Stephen L. B. Moshier
title: Methods and Programs for Mathematical Functions
publisher: pub-ELLIS-HORWOOD
address: pub-ELLIS-HORWOOD:adr
pages: vii + 415
year: 1989
ISBN: 0-7458-0289-3 OR 0745802893
ISBN13: 978-0-7458-0289-3 OR 9780745802893
LCCN: QA331 .M84 1989
MRclass: *65D20, 26-04, 33-04, 65-02, 65C99
bibdate: Thu Sep 01 10:33:40 1994
bibtimestamp: 1994.09.01 10:33:40 ???
URL: http://www.moshier.net/; http://www.netlib.org/cephes
ZMnumber: 0701.65011
acknowledgement: ack-nj
rawauthor: Stephen L. B. Moshier
rawtitle: Methods and Programs for Mathematical Functions
bibsource:
ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/master.bib

TOC:
Preface / vii 1: Floating Point Arithmetic / 1 1.1 Numeric Data Structures / 1 1.2 Rounding / 5 1.3 Addition and Subtraction / 6 1.4 Multiplication / 7 1.4.1 Long Multiplication in Binary Radix / 8 1.4.2 Multiplication in Word Integer Radix / 8 1.4.3 Fast Multiplication / 9 1.5 Division / 10 1.5.1 Long Division / 10 1.5.2 Division by Taylor Series / 11 1.5.3 Newton--Raphson Division / 11 1.6 C Language / 12 1.7 An Extended Double Arithmetic: ieee.c / 13 1.8 Binary - Decimal Conversion / 46 1.8.1 etoasc.c / 47 1.8.2 asctoe.c / 54 1.9 Analysis of Error / 58 1.9.1 Roundoff and Cancellation / 58 1.9.2 Error Propagation / 60 1.9.3 Error as a Random Variable / 61 1.9.4 Order of Summation / 62 1.10 Complex Arithmetic / 62 1.10.1 cmplx.c / 64 1.10.2 Absolute Value: cabs.c / 67 1.11 Rational Arithmetic / 69 1.11.1 euclid.c / 70 2: Approximation Methods / 75 2.1 Power Series / 75 2.2 Chebyshev Expansions / 76 2.2.1 chbevl.c / 79 2.3 Pade Approximations / 80 2.4 Least Maximum Approximations / 82 2.4.1 Best Polynomial Approximations / 82 2.4.2 Best Rational Approximations / 85 2.4.3 Special Rational Forms / 87 2.5 A Program to Find Best Approximations: remes.c / 88 2.6 Forms of Approximation / 111 2.7 Asymptotic Expansions / 113 2.8 Continued Fractions / 114 2.8.1 Continued Fractions from Recurrences / 115 2.8.2 Recurrences from Differential Equations / 116 2.8.3 Computing Continued Fractions / 117 2.9 Polynomials / 117 2.9.1 polevl.c / 118 2.10 Newton--Raphson Iterations / 119 2.10.1 Division / 120 2.10.2 Exponent Separation / 121 2.10.3 Square Root / 122 2.10.4 sqrt.c / 123 2.10.5 Longhand Square Root / 124 2.10.6 esqrt.c / 124 2.10.7 Cube Root / 126 2.10.8 cbrt.c / 127 3: Software Notes / 129 3.1 Design Strategy / 129 3.2 Testing / 131 3.3 System Utilities / 132 3.3.1 mconf.h / 132 3.3.2 mtherr.c / 134 3.3.3 const.c / 136 3.4 Arithmetic Utilities / 137 3.4.1 efloor.c / 138 3.4.2 efrexp.c / 140 3.4.3 eldexp.c / 140 4: Elementary Functions / 143 4.1 $e^x$ / 143 4.1.1 exp.c / 145 4.2 $ln x$ / 147 4.2.1 log.c / 149 4.3 Argument Transformation for Circular Functions / 152 4.4 Sine and cosine / 153 4.4.1 sin.c / 154 4.4.2 cos.c / 156 4.5 Tangent and Cotangent / 157 4.5.1 tan.c / 158 4.6 Complex Circular Functions / 161 4.7 $sin ^-1 x $ / 162 4.7.1 asin.c / 163 4.8 $cos ^-1 x $ / 165 4.8.1 acos.c / 165 4.9 $tan ^-1 x$ / 166 4.9.1 atan.c / 168 4.9.2 atan2.c / 169 4.10 Complex Inverse Circular Functions / 170 4.11 $sinh x$ / 170 4.11.1 sinh.c / 171 4.12 $cosh x$ / 172 4.12.1 cosh.c / 173 4.13 $tanh x$ / 173 4.13.1 tanh.c / 174 4.14 $sinh ^-1 x $ / 175 4.14.1 asinh.c / 176 4.15 $cosh ^-1 x $ / 177 4.15.1 acosh.c / 178 4.16 $tanh ^-1 x$ / 179 4.16.1 atanh.c / 180 4.17 Power Function / 181 4.17.1 Real Exponent / 182 4.17.2 pow.c / 182 4.17.3 Integer Exponent / 189 4.17.4 powi.c / 190 4.18 Testing / 192 4.19 Single Precision Polynomial Approximations / 193 4.19.1 $cos x$ / 193 4.19.2 $cosh ^-1 x $ / 193 4.19.3 $exp x$ / 196 4.19.4 $ln x$ / 196 4.19.5 $sin x$ / 197 4.19.6 $sin ^-1 x $ / 197 4.19.7 Square Root / 197 4.19.8 $tan x$ / 198 4.19.9 $tan ^-1 x$ / 198 4.19.10 $tanh x$ / 199 4.19.11 $tanh^-1 x$ / 199 5: Probability Distributions and Related Functions / 201 5.1 $n!$ / 202 5.1.1 fac.c / 204 5.2 $Gamma (x)$ / 206 5.2.1 gamma.c / 210 5.2.2 lgam.c / 214 5.3 Incomplete Gamma Integral / 217 5.3.1 igamc.c / 218 5.3.2 igam.c / 220 5.3.3 Functional Inverse of Incomplete Gamma Integral / 221 5.3.4 igami.c / 221 5.4 Gamma Distribution / 222 5.4.1 gdtr c / 222 5.4.2 gdtrc.c / 223 5.5 $chi ^2$ Distribution / 223 5.5.1 chdtrc.c / 224 5.5.2 chdtr.c / 224 5.5.3 chdtrl.c / 224 5.6 Poisson Distribution / 225 5.6.1 pdtrc.c / 225 5.6.2 pdtr.c / 226 5.6.3 pdtri.c / 226 5.7 Beta Function / 227 5.7.1 beta.c / 227 5.8 Incomplete Beta Integral / 229 5.8.1 ibet.c / 231 5.8.2 Functional Inverse of Incomplete Beta Integral / 238 5.9 Beta Distribution / 241 5.9.1 btdtr.c / 241 5.10 Binomial Distribution / 241 5.10.1 bdtrc.c / 242 5.10.2 bdtr.c / 243 5.10.3 bdtri.c / 244 5.11 Negative Binomial Distribution / 244 5.11.1 nbdtr.c / 245 5.11.2 nbdtrc.c / 245 5.12 F Distribution / 246 5.12.1 fdtrc.c / 247 5.12.2 fdtr.c / 247 5.12.3 fdtrci.c / 248 5.13 Student's $t$ distribution / 249 5.13.1 stdtr.c / 250 5.14 Gaussian Distribution / 252 5.14.1 ndtr.c / 254 5.14.2 erfc.c / 256 5.14.3 erf.c / 257 5.14.4 Functional Inverse of Gaussian Distribution / 258 5.14.5 ndtri.c / 259 6: Bessel Functions / 263 6.1 $J_0(x)$ / 263 6.1.1 jO.c / 265 6.2 $Y_0(x)$ / 268 6.2.1 yO.c / 269 6.3 Modulus and Phase / 270 6.4 $J_1(x)$ / 271 6.4.1 jl.c / 272 6.5 $Y_1(x)$ / 275 6.5.1 yl.c / 275 6.6 $J_n(x)$ / 276 6.1 $I_0(x)$ / 277 6.7.1 i0.c / 278 6.8 $I_1(x)$ / 281 6.8.1 i1.c / 283 6.9 $I_nu (x)$ / 285 6.9.1 iv.c / 286 6.10 $K_0(x)$ / 287 6.10.1 kO.c / 287 6.11 $K_1(x)$ / 291 6.11.1 kl.c / 291 6.12 $K_n(x)$ / 294 6.12.1 kn.c / 295 6.13 $J_nu (x)$ / 299 6.13.1 jv.c / 301 6.14 Airy Functions / 315 6.14.1 airy.c / 322 6.15 $Y_n(x)$ / 328 6.15.1 yn.c / 329 6.16 Testing / 330 7: Other Special Functions / 333 7.1 Hypergeometric Functions / 333 7.1.1 $_2F_1$ / 334 7.1.2 hyp2fi.c / 335 7.1.3 $_1F_1$ / 341 7.1.4 hyplfi.c / 342 7.1.5 $_2F_0$ / 346 7.1.6 hyp2ffi.c / 346 7.2 Struve Functions / 348 7.2.1 hypl1f2.c / 348 7.2.2 hyp3f0.c / 349 7.2.3 yv.c / 351 7.2.4 struve.c / 351 7.3 $psi (x)$ / 352 7.3.1 psi.c / 354 7.4 Exponential Integral / 355 7.4.1 en.c / 356 7.5 Sine and Cosine Integrals / 360 7.5.1 sici.c / 362 7.5.2 Hyperbolic Sine and Cosine Integrals / 367 7.5.3 shichi.c / 370 7.6 Dilogarithm / 374 7.6.1 spence.c / 375 7.7 Dawson's Integral / 377 7.7.1 dawsn.c / 378 7.8 Fresnel Integrals / 381 7.8.1 fresnl.c / 383 7.9 Elliptic Functions / 387 7.9.1 $K(m)$ / 387 7.9.2 ellpk.c / 388 7.9.3 $F(phi |m)$ / 389 7.9.4 ellik.c / 390 7.9.5 $E(m)$ / 392 7.9.6 ellpe.c / 392 7.9.7 $E(phi |m)$ / 393 7.9.8 ellie.c / 394 7.9.9 Jacobian Elliptic Functions / 396 7.9.10 ellpj.c / 398 7.10 Zeta Functions / 400 7.10.1 hurwiz.c / 400 7.10.2 Riemann Zeta Function / 402 7.10.3 zetac.c / 405 Bibliography / 411 Index / 413

shortTOC:
Preface / vii 1: Floating Point Arithmetic / 1 2: Approximation Methods / 75 3: Software Notes / 129 4: Elementary Functions / 143 5: Probability Distributions and Related Functions / 201 6: Bessel Functions / 263 7: Other Special Functions / 333 Bibliography / 411 Index / 413

rawshortTOC:
Preface / vii \\ 1: Floating Point Arithmetic / 1 \\ 2: Approximation Methods / 75 \\ 3: Software Notes / 129 \\ 4: Elementary Functions / 143 \\ 5: Probability Distributions and Related Functions / 201 6: Bessel Functions / 263 \\ 7: Other Special Functions / 333 \\ Bibliography / 411 \\ Index / 413

rawTOC:
Preface / vii \\ 1: Floating Point Arithmetic / 1 \\ 1.1 Numeric Data Structures / 1 \\ 1.2 Rounding / 5 \\ 1.3 Addition and Subtraction / 6 \\ 1.4 Multiplication / 7 \\ 1.4.1 Long Multiplication in Binary Radix / 8 \\ 1.4.2 Multiplication in Word Integer Radix / 8 \\ 1.4.3 Fast Multiplication / 9 \\ 1.5 Division / 10 \\ 1.5.1 Long Division / 10 \\ 1.5.2 Division by Taylor Series / 11 \\ 1.5.3 Newton--Raphson Division / 11 \\ 1.6 C Language / 12 \\ 1.7 An Extended Double Arithmetic: ieee.c / 13 \\ 1.8 Binary - Decimal Conversion / 46 \\ 1.8.1 etoasc.c / 47 \\ 1.8.2 asctoe.c / 54 \\ 1.9 Analysis of Error / 58 \\ 1.9.1 Roundoff and Cancellation / 58 \\ 1.9.2 Error Propagation / 60 \\ 1.9.3 Error as a Random Variable / 61 \\ 1.9.4 Order of Summation / 62 \\ 1.10 Complex Arithmetic / 62 \\ 1.10.1 cmplx.c / 64 \\ 1.10.2 Absolute Value: cabs.c / 67 \\ 1.11 Rational Arithmetic / 69 \\ 1.11.1 euclid.c / 70 \\ 2: Approximation Methods / 75 \\ 2.1 Power Series / 75 \\ 2.2 Chebyshev Expansions / 76 \\ 2.2.1 chbevl.c / 79 \\ 2.3 Pad{\'e} Approximations / 80 \\ 2.4 Least Maximum Approximations / 82 \\ 2.4.1 Best Polynomial Approximations / 82 \\ 2.4.2 Best Rational Approximations / 85 \\ 2.4.3 Special Rational Forms / 87 \\ 2.5 A Program to Find Best Approximations: remes.c / 88 \\ 2.6 Forms of Approximation / 111 \\ 2.7 Asymptotic Expansions / 113 \\ 2.8 Continued Fractions / 114 \\ 2.8.1 Continued Fractions from Recurrences / 115 \\ 2.8.2 Recurrences from Differential Equations / 116 \\ 2.8.3 Computing Continued Fractions / 117 \\ 2.9 Polynomials / 117 \\ 2.9.1 polevl.c / 118 \\ 2.10 Newton--Raphson Iterations / 119 \\ 2.10.1 Division / 120 \\ 2.10.2 Exponent Separation / 121 \\ 2.10.3 Square Root / 122 \\ 2.10.4 sqrt.c / 123 \\ 2.10.5 Longhand Square Root / 124 \\ 2.10.6 esqrt.c / 124 \\ 2.10.7 Cube Root / 126 \\ 2.10.8 cbrt.c / 127 \\ 3: Software Notes / 129 \\ 3.1 Design Strategy / 129 \\ 3.2 Testing / 131 \\ 3.3 System Utilities / 132 \\ 3.3.1 mconf.h / 132 \\ 3.3.2 mtherr.c / 134 \\ 3.3.3 const.c / 136 \\ 3.4 Arithmetic Utilities / 137 \\ 3.4.1 efloor.c / 138 \\ 3.4.2 efrexp.c / 140 \\ 3.4.3 eldexp.c / 140 \\ 4: Elementary Functions / 143 \\ 4.1 $e^x$ / 143 \\ 4.1.1 exp.c / 145 \\ 4.2 $\ln x$ / 147 \\ 4.2.1 log.c / 149 \\ 4.3 Argument Transformation for Circular Functions / 152 \\ 4.4 Sine and cosine / 153 \\ 4.4.1 sin.c / 154 \\ 4.4.2 cos.c / 156 \\ 4.5 Tangent and Cotangent / 157 \\ 4.5.1 tan.c / 158 \\ 4.6 Complex Circular Functions / 161 \\ 4.7 $\sin^{-1} x $ / 162 \\ 4.7.1 asin.c / 163 \\ 4.8 $\cos^{-1} x $ / 165 \\ 4.8.1 acos.c / 165 \\ 4.9 $\tan^{-1} x$ / 166 \\ 4.9.1 atan.c / 168 \\ 4.9.2 atan2.c / 169 \\ 4.10 Complex Inverse Circular Functions / 170 \\ 4.11 $\sinh x$ / 170 \\ 4.11.1 sinh.c / 171 \\ 4.12 $\cosh x$ / 172 \\ 4.12.1 cosh.c / 173 \\ 4.13 $\tanh x$ / 173 \\ 4.13.1 tanh.c / 174 \\ 4.14 $\sinh^{-1} x $ / 175 \\ 4.14.1 asinh.c / 176 \\ 4.15 $\cosh^{-1} x $ / 177 \\ 4.15.1 acosh.c / 178 \\ 4.16 $\tanh^{-1} x$ / 179 \\ 4.16.1 atanh.c / 180 \\ 4.17 Power Function / 181 \\ 4.17.1 Real Exponent / 182 \\ 4.17.2 pow.c / 182 \\ 4.17.3 Integer Exponent / 189 \\ 4.17.4 powi.c / 190 \\ 4.18 Testing / 192 \\ 4.19 Single Precision Polynomial Approximations / 193 \\ 4.19.1 $\cos x$ / 193 \\ 4.19.2 $\cosh^{-1} x $ / 193 \\ 4.19.3 $\exp x$ / 196 \\ 4.19.4 $\ln x$ / 196 \\ 4.19.5 $\sin x$ / 197 \\ 4.19.6 $\sin^{-1} x $ / 197 \\ 4.19.7 Square Root / 197 \\ 4.19.8 $\tan x$ / 198 \\ 4.19.9 $\tan^{-1} x$ / 198 \\ 4.19.10 $\tanh x$ / 199 \\ 4.19.11 $tanh^{-1} x$ / 199 \\ 5: Probability Distributions and Related Functions / 201 \\ 5.1 $n!$ / 202 \\ 5.1.1 fac.c / 204 \\ 5.2 $\Gamma(x)$ / 206 \\ 5.2.1 gamma.c / 210 \\ 5.2.2 lgam.c / 214 \\ 5.3 Incomplete Gamma Integral / 217 \\ 5.3.1 igamc.c / 218 \\ 5.3.2 igam.c / 220 \\ 5.3.3 Functional Inverse of Incomplete Gamma Integral / 221 \\ 5.3.4 igami.c / 221 \\ 5.4 Gamma Distribution / 222 \\ 5.4.1 gdtr c / 222 \\ 5.4.2 gdtrc.c / 223 \\ 5.5 $\chi^2$ Distribution / 223 \\ 5.5.1 chdtrc.c / 224 \\ 5.5.2 chdtr.c / 224 \\ 5.5.3 chdtrl.c / 224 \\ 5.6 Poisson Distribution / 225 \\ 5.6.1 pdtrc.c / 225 \\ 5.6.2 pdtr.c / 226 \\ 5.6.3 pdtri.c / 226 \\ 5.7 Beta Function / 227 \\ 5.7.1 beta.c / 227 \\ 5.8 Incomplete Beta Integral / 229 \\ 5.8.1 ibet.c / 231 \\ 5.8.2 Functional Inverse of Incomplete Beta Integral / 238 \\ 5.9 Beta Distribution / 241 \\ 5.9.1 btdtr.c / 241 \\ 5.10 Binomial Distribution / 241 \\ 5.10.1 bdtrc.c / 242 \\ 5.10.2 bdtr.c / 243 \\ 5.10.3 bdtri.c / 244 \\ 5.11 Negative Binomial Distribution / 244 \\ 5.11.1 nbdtr.c / 245 \\ 5.11.2 nbdtrc.c / 245 \\ 5.12 F Distribution / 246 \\ 5.12.1 fdtrc.c / 247 \\ 5.12.2 fdtr.c / 247 \\ 5.12.3 fdtrci.c / 248 \\ 5.13 Student's $t$ distribution / 249 \\ 5.13.1 stdtr.c / 250 \\ 5.14 Gaussian Distribution / 252 \\ 5.14.1 ndtr.c / 254 \\ 5.14.2 erfc.c / 256 \\ 5.14.3 erf.c / 257 \\ 5.14.4 Functional Inverse of Gaussian Distribution / 258 \\ 5.14.5 ndtri.c / 259 \\ 6: Bessel Functions / 263 \\ 6.1 $J_0(x)$ / 263 \\ 6.1.1 jO.c / 265 \\ 6.2 $Y_0(x)$ / 268 \\ 6.2.1 yO.c / 269 \\ 6.3 Modulus and Phase / 270 \\ 6.4 $J_1(x)$ / 271 \\ 6.4.1 jl.c / 272 \\ 6.5 $Y_1(x)$ / 275 \\ 6.5.1 yl.c / 275 \\ 6.6 $J_n(x)$ / 276 \\ 6.1 $I_0(x)$ / 277 \\ 6.7.1 i0.c / 278 \\ 6.8 $I_1(x)$ / 281 \\ 6.8.1 i1.c / 283 \\ 6.9 $I_\nu(x)$ / 285 \\ 6.9.1 iv.c / 286 \\ 6.10 $K_0(x)$ / 287 \\ 6.10.1 kO.c / 287 \\ 6.11 $K_1(x)$ / 291 \\ 6.11.1 kl.c / 291 \\ 6.12 $K_n(x)$ / 294 \\ 6.12.1 kn.c / 295 \\ 6.13 $J_\nu(x)$ / 299 \\ 6.13.1 jv.c / 301 \\ 6.14 Airy Functions / 315 \\ 6.14.1 airy.c / 322 \\ 6.15 $Y_n(x)$ / 328 \\ 6.15.1 yn.c / 329 \\ 6.16 Testing / 330 \\ 7: Other Special Functions / 333 \\ 7.1 Hypergeometric Functions / 333 \\ 7.1.1 $_2F_1$ / 334 \\ 7.1.2 hyp2fi.c / 335 \\ 7.1.3 $_1F_1$ / 341 \\ 7.1.4 hyplfi.c / 342 \\ 7.1.5 $_2F_0$ / 346 \\ 7.1.6 hyp2ffi.c / 346 \\ 7.2 Struve Functions / 348 \\ 7.2.1 hypl1f2.c / 348 \\ 7.2.2 hyp3f0.c / 349 \\ 7.2.3 yv.c / 351 \\ 7.2.4 struve.c / 351 \\ 7.3 $\psi(x)$ / 352 \\ 7.3.1 psi.c / 354 \\ 7.4 Exponential Integral / 355 \\ 7.4.1 en.c / 356 \\ 7.5 Sine and Cosine Integrals / 360 \\ 7.5.1 sici.c / 362 \\ 7.5.2 Hyperbolic Sine and Cosine Integrals / 367 \\ 7.5.3 shichi.c / 370 \\ 7.6 Dilogarithm / 374 \\ 7.6.1 spence.c / 375 \\ 7.7 Dawson's Integral / 377 \\ 7.7.1 dawsn.c / 378 \\ 7.8 Fresnel Integrals / 381 \\ 7.8.1 fresnl.c / 383 \\ 7.9 Elliptic Functions / 387 \\ 7.9.1 $K(m)$ / 387 \\ 7.9.2 ellpk.c / 388 \\ 7.9.3 $F(\phi|m)$ / 389 \\ 7.9.4 ellik.c / 390 \\ 7.9.5 $E(m)$ / 392 \\ 7.9.6 ellpe.c / 392 \\ 7.9.7 $E(\phi|m)$ / 393 \\ 7.9.8 ellie.c / 394 \\ 7.9.9 Jacobian Elliptic Functions / 396 \\ 7.9.10 ellpj.c / 398 \\ 7.10 Zeta Functions / 400 \\ 7.10.1 hurwiz.c / 400 \\ 7.10.2 Riemann Zeta Function / 402 \\ 7.10.3 zetac.c / 405 \\ Bibliography / 411 \\ Index / 413

entry:
@Book{Moshier:1989:MPM,
  author =       "Stephen L. B. Moshier",
  title =        "Methods and Programs for Mathematical Functions",
  publisher =    pub-ELLIS-HORWOOD,
  address =      pub-ELLIS-HORWOOD:adr,
  pages =        "vii + 415",
  year =         "1989",
  ISBN =         "0-7458-0289-3",
  ISBN-13 =      "978-0-7458-0289-3",
  LCCN =         "QA331 .M84 1989",
  MRclass =      "*65D20, 26-04, 33-04, 65-02, 65C99",
  bibdate =      "Thu Sep 01 10:33:40 1994",
  bibsource =    "ftp://garbo.uwasa.fi/pc/doc-soft/fpbibl18.zip;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib",
  price =        "US\pounds 48.00",
  URL =          "http://www.moshier.net/;
                 http://www.netlib.org/cephes",
  ZMnumber =     "0701.65011",
  acknowledgement = ack-nj,
  shorttableofcontents = "Preface / vii \\
                 1: Floating Point Arithmetic / 1 \\
                 2: Approximation Methods / 75 \\
                 3: Software Notes / 129 \\
                 4: Elementary Functions / 143 \\
                 5: Probability Distributions and Related Functions /
                 201 6: Bessel Functions / 263 \\
                 7: Other Special Functions / 333 \\
                 Bibliography / 411 \\
                 Index / 413",
  tableofcontents = "Preface / vii \\
                 1: Floating Point Arithmetic / 1 \\
                 1.1 Numeric Data Structures / 1 \\
                 1.2 Rounding / 5 \\
                 1.3 Addition and Subtraction / 6 \\
                 1.4 Multiplication / 7 \\
                 1.4.1 Long Multiplication in Binary Radix / 8 \\
                 1.4.2 Multiplication in Word Integer Radix / 8 \\
                 1.4.3 Fast Multiplication / 9 \\
                 1.5 Division / 10 \\
                 1.5.1 Long Division / 10 \\
                 1.5.2 Division by Taylor Series / 11 \\
                 1.5.3 Newton--Raphson Division / 11 \\
                 1.6 C Language / 12 \\
                 1.7 An Extended Double Arithmetic: ieee.c / 13 \\
                 1.8 Binary - Decimal Conversion / 46 \\
                 1.8.1 etoasc.c / 47 \\
                 1.8.2 asctoe.c / 54 \\
                 1.9 Analysis of Error / 58 \\
                 1.9.1 Roundoff and Cancellation / 58 \\
                 1.9.2 Error Propagation / 60 \\
                 1.9.3 Error as a Random Variable / 61 \\
                 1.9.4 Order of Summation / 62 \\
                 1.10 Complex Arithmetic / 62 \\
                 1.10.1 cmplx.c / 64 \\
                 1.10.2 Absolute Value: cabs.c / 67 \\
                 1.11 Rational Arithmetic / 69 \\
                 1.11.1 euclid.c / 70 \\
                 2: Approximation Methods / 75 \\
                 2.1 Power Series / 75 \\
                 2.2 Chebyshev Expansions / 76 \\
                 2.2.1 chbevl.c / 79 \\
                 2.3 Pad{\'e} Approximations / 80 \\
                 2.4 Least Maximum Approximations / 82 \\
                 2.4.1 Best Polynomial Approximations / 82 \\
                 2.4.2 Best Rational Approximations / 85 \\
                 2.4.3 Special Rational Forms / 87 \\
                 2.5 A Program to Find Best Approximations: remes.c / 88
                 \\
                 2.6 Forms of Approximation / 111 \\
                 2.7 Asymptotic Expansions / 113 \\
                 2.8 Continued Fractions / 114 \\
                 2.8.1 Continued Fractions from Recurrences / 115 \\
                 2.8.2 Recurrences from Differential Equations / 116 \\
                 2.8.3 Computing Continued Fractions / 117 \\
                 2.9 Polynomials / 117 \\
                 2.9.1 polevl.c / 118 \\
                 2.10 Newton--Raphson Iterations / 119 \\
                 2.10.1 Division / 120 \\
                 2.10.2 Exponent Separation / 121 \\
                 2.10.3 Square Root / 122 \\
                 2.10.4 sqrt.c / 123 \\
                 2.10.5 Longhand Square Root / 124 \\
                 2.10.6 esqrt.c / 124 \\
                 2.10.7 Cube Root / 126 \\
                 2.10.8 cbrt.c / 127 \\
                 3: Software Notes / 129 \\
                 3.1 Design Strategy / 129 \\
                 3.2 Testing / 131 \\
                 3.3 System Utilities / 132 \\
                 3.3.1 mconf.h / 132 \\
                 3.3.2 mtherr.c / 134 \\
                 3.3.3 const.c / 136 \\
                 3.4 Arithmetic Utilities / 137 \\
                 3.4.1 efloor.c / 138 \\
                 3.4.2 efrexp.c / 140 \\
                 3.4.3 eldexp.c / 140 \\
                 4: Elementary Functions / 143 \\
                 4.1 $e^x$ / 143 \\
                 4.1.1 exp.c / 145 \\
                 4.2 $\ln x$ / 147 \\
                 4.2.1 log.c / 149 \\
                 4.3 Argument Transformation for Circular Functions /
                 152 \\
                 4.4 Sine and cosine / 153 \\
                 4.4.1 sin.c / 154 \\
                 4.4.2 cos.c / 156 \\
                 4.5 Tangent and Cotangent / 157 \\
                 4.5.1 tan.c / 158 \\
                 4.6 Complex Circular Functions / 161 \\
                 4.7 $\sin^{-1} x $ / 162 \\
                 4.7.1 asin.c / 163 \\
                 4.8 $\cos^{-1} x $ / 165 \\
                 4.8.1 acos.c / 165 \\
                 4.9 $\tan^{-1} x$ / 166 \\
                 4.9.1 atan.c / 168 \\
                 4.9.2 atan2.c / 169 \\
                 4.10 Complex Inverse Circular Functions / 170 \\
                 4.11 $\sinh x$ / 170 \\
                 4.11.1 sinh.c / 171 \\
                 4.12 $\cosh x$ / 172 \\
                 4.12.1 cosh.c / 173 \\
                 4.13 $\tanh x$ / 173 \\
                 4.13.1 tanh.c / 174 \\
                 4.14 $\sinh^{-1} x $ / 175 \\
                 4.14.1 asinh.c / 176 \\
                 4.15 $\cosh^{-1} x $ / 177 \\
                 4.15.1 acosh.c / 178 \\
                 4.16 $\tanh^{-1} x$ / 179 \\
                 4.16.1 atanh.c / 180 \\
                 4.17 Power Function / 181 \\
                 4.17.1 Real Exponent / 182 \\
                 4.17.2 pow.c / 182 \\
                 4.17.3 Integer Exponent / 189 \\
                 4.17.4 powi.c / 190 \\
                 4.18 Testing / 192 \\
                 4.19 Single Precision Polynomial Approximations / 193
                 \\
                 4.19.1 $\cos x$ / 193 \\
                 4.19.2 $\cosh^{-1} x $ / 193 \\
                 4.19.3 $\exp x$ / 196 \\
                 4.19.4 $\ln x$ / 196 \\
                 4.19.5 $\sin x$ / 197 \\
                 4.19.6 $\sin^{-1} x $ / 197 \\
                 4.19.7 Square Root / 197 \\
                 4.19.8 $\tan x$ / 198 \\
                 4.19.9 $\tan^{-1} x$ / 198 \\
                 4.19.10 $\tanh x$ / 199 \\
                 4.19.11 $tanh^{-1} x$ / 199 \\
                 5: Probability Distributions and Related Functions /
                 201 \\
                 5.1 $n!$ / 202 \\
                 5.1.1 fac.c / 204 \\
                 5.2 $\Gamma(x)$ / 206 \\
                 5.2.1 gamma.c / 210 \\
                 5.2.2 lgam.c / 214 \\
                 5.3 Incomplete Gamma Integral / 217 \\
                 5.3.1 igamc.c / 218 \\
                 5.3.2 igam.c / 220 \\
                 5.3.3 Functional Inverse of Incomplete Gamma Integral /
                 221 \\
                 5.3.4 igami.c / 221 \\
                 5.4 Gamma Distribution / 222 \\
                 5.4.1 gdtr c / 222 \\
                 5.4.2 gdtrc.c / 223 \\
                 5.5 $\chi^2$ Distribution / 223 \\
                 5.5.1 chdtrc.c / 224 \\
                 5.5.2 chdtr.c / 224 \\
                 5.5.3 chdtrl.c / 224 \\
                 5.6 Poisson Distribution / 225 \\
                 5.6.1 pdtrc.c / 225 \\
                 5.6.2 pdtr.c / 226 \\
                 5.6.3 pdtri.c / 226 \\
                 5.7 Beta Function / 227 \\
                 5.7.1 beta.c / 227 \\
                 5.8 Incomplete Beta Integral / 229 \\
                 5.8.1 ibet.c / 231 \\
                 5.8.2 Functional Inverse of Incomplete Beta Integral /
                 238 \\
                 5.9 Beta Distribution / 241 \\
                 5.9.1 btdtr.c / 241 \\
                 5.10 Binomial Distribution / 241 \\
                 5.10.1 bdtrc.c / 242 \\
                 5.10.2 bdtr.c / 243 \\
                 5.10.3 bdtri.c / 244 \\
                 5.11 Negative Binomial Distribution / 244 \\
                 5.11.1 nbdtr.c / 245 \\
                 5.11.2 nbdtrc.c / 245 \\
                 5.12 F Distribution / 246 \\
                 5.12.1 fdtrc.c / 247 \\
                 5.12.2 fdtr.c / 247 \\
                 5.12.3 fdtrci.c / 248 \\
                 5.13 Student's $t$ distribution / 249 \\
                 5.13.1 stdtr.c / 250 \\
                 5.14 Gaussian Distribution / 252 \\
                 5.14.1 ndtr.c / 254 \\
                 5.14.2 erfc.c / 256 \\
                 5.14.3 erf.c / 257 \\
                 5.14.4 Functional Inverse of Gaussian Distribution /
                 258 \\
                 5.14.5 ndtri.c / 259 \\
                 6: Bessel Functions / 263 \\
                 6.1 $J_0(x)$ / 263 \\
                 6.1.1 jO.c / 265 \\
                 6.2 $Y_0(x)$ / 268 \\
                 6.2.1 yO.c / 269 \\
                 6.3 Modulus and Phase / 270 \\
                 6.4 $J_1(x)$ / 271 \\
                 6.4.1 jl.c / 272 \\
                 6.5 $Y_1(x)$ / 275 \\
                 6.5.1 yl.c / 275 \\
                 6.6 $J_n(x)$ / 276 \\
                 6.1 $I_0(x)$ / 277 \\
                 6.7.1 i0.c / 278 \\
                 6.8 $I_1(x)$ / 281 \\
                 6.8.1 i1.c / 283 \\
                 6.9 $I_\nu(x)$ / 285 \\
                 6.9.1 iv.c / 286 \\
                 6.10 $K_0(x)$ / 287 \\
                 6.10.1 kO.c / 287 \\
                 6.11 $K_1(x)$ / 291 \\
                 6.11.1 kl.c / 291 \\
                 6.12 $K_n(x)$ / 294 \\
                 6.12.1 kn.c / 295 \\
                 6.13 $J_\nu(x)$ / 299 \\
                 6.13.1 jv.c / 301 \\
                 6.14 Airy Functions / 315 \\
                 6.14.1 airy.c / 322 \\
                 6.15 $Y_n(x)$ / 328 \\
                 6.15.1 yn.c / 329 \\
                 6.16 Testing / 330 \\
                 7: Other Special Functions / 333 \\
                 7.1 Hypergeometric Functions / 333 \\
                 7.1.1 $_2F_1$ / 334 \\
                 7.1.2 hyp2fi.c / 335 \\
                 7.1.3 $_1F_1$ / 341 \\
                 7.1.4 hyplfi.c / 342 \\
                 7.1.5 $_2F_0$ / 346 \\
                 7.1.6 hyp2ffi.c / 346 \\
                 7.2 Struve Functions / 348 \\
                 7.2.1 hypl1f2.c / 348 \\
                 7.2.2 hyp3f0.c / 349 \\
                 7.2.3 yv.c / 351 \\
                 7.2.4 struve.c / 351 \\
                 7.3 $\psi(x)$ / 352 \\
                 7.3.1 psi.c / 354 \\
                 7.4 Exponential Integral / 355 \\
                 7.4.1 en.c / 356 \\
                 7.5 Sine and Cosine Integrals / 360 \\
                 7.5.1 sici.c / 362 \\
                 7.5.2 Hyperbolic Sine and Cosine Integrals / 367 \\
                 7.5.3 shichi.c / 370 \\
                 7.6 Dilogarithm / 374 \\
                 7.6.1 spence.c / 375 \\
                 7.7 Dawson's Integral / 377 \\
                 7.7.1 dawsn.c / 378 \\
                 7.8 Fresnel Integrals / 381 \\
                 7.8.1 fresnl.c / 383 \\
                 7.9 Elliptic Functions / 387 \\
                 7.9.1 $K(m)$ / 387 \\
                 7.9.2 ellpk.c / 388 \\
                 7.9.3 $F(\phi|m)$ / 389 \\
                 7.9.4 ellik.c / 390 \\
                 7.9.5 $E(m)$ / 392 \\
                 7.9.6 ellpe.c / 392 \\
                 7.9.7 $E(\phi|m)$ / 393 \\
                 7.9.8 ellie.c / 394 \\
                 7.9.9 Jacobian Elliptic Functions / 396 \\
                 7.9.10 ellpj.c / 398 \\
                 7.10 Zeta Functions / 400 \\
                 7.10.1 hurwiz.c / 400 \\
                 7.10.2 Riemann Zeta Function / 402 \\
                 7.10.3 zetac.c / 405 \\
                 Bibliography / 411 \\
                 Index / 413",
}


