# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Chaurasiya:2018:PPA
editor: IEEE
booktitle: 2018 IEEE 36th International Conference on Computer Design (ICCD)
title: Parameterized Posit Arithmetic Hardware Generator
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 334--341
year: 2018
DOI: https://doi.org/10.1109/ICCD.2018.00057
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawbooktitle: {2018 IEEE 36th International Conference on Computer Design (ICCD)}
raweditor: {IEEE}
rawtitle: Parameterized Posit Arithmetic Hardware Generator
author:
Rohit Chaurasiya and John Gustafson and Rahul Shrestha and Jonathan Neudorfer and Sangeeth Nambiar and Kaustav Niyogi and Farhad Merchant and Rainer Leupers

rawauthor:
Rohit Chaurasiya and John Gustafson and Rahul Shrestha and Jonathan Neudorfer and Sangeeth Nambiar and Kaustav Niyogi and Farhad Merchant and Rainer Leupers

entry:
@InProceedings{Chaurasiya:2018:PPA,
  author =       "Rohit Chaurasiya and John Gustafson and Rahul Shrestha
                 and Jonathan Neudorfer and Sangeeth Nambiar and Kaustav
                 Niyogi and Farhad Merchant and Rainer Leupers",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE 36th International Conference on Computer
                 Design (ICCD)}",
  title =        "Parameterized Posit Arithmetic Hardware Generator",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "334--341",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ICCD.2018.00057",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:2018:MMU
author: Jianyu Chen and Zaid Al-Ars
title: A Matrix-Multiply Unit for Posits in Reconfigurable Logic Using (OPEN)CAPI
crossref: ACM:2018:CNG
pages: 1--5
year: 2018
DOI: https://doi.org/10.1145/3190339.3190340
bibdate: Mon Dec 11 08:58:21 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.11 08:58:21 ???
keywords: posit arithmetic; universal number (unum) arithmetic
acknowledgement: ack-nhfb
articleno: 1
rawauthor: Jianyu Chen and Zaid Al-Ars
rawtitle: A Matrix-Multiply Unit for Posits in Reconfigurable Logic Using {(OPEN)CAPI}
entry:
@InProceedings{Chen:2018:MMU,
  author =       "Jianyu Chen and Zaid Al-Ars",
  title =        "A Matrix-Multiply Unit for Posits in Reconfigurable
                 Logic Using {(OPEN)CAPI}",
  crossref =     "ACM:2018:CNG",
  pages =        "1--5",
  year =         "2018",
  DOI =          "https://doi.org/10.1145/3190339.3190340",
  bibdate =      "Mon Dec 11 08:58:21 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  keywords =     "posit arithmetic; universal number (unum) arithmetic",
}


bibtype: misc
filename: fparith.bib
label: Cherkaev:2018:SLN
author: Annie Cherkaev
title: The secret life of NaN
pages: 1--5
month: mar
monthnumber: 3
year: 2018
bibdate: Fri Dec 01 14:21:50 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.01 14:21:50 ???
URL: https://anniecherkaev.com/the-secret-life-of-nan
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Annie Cherkaev
rawtitle: The secret life of {NaN}
remark:
The site discusses IEEE 754 number encoding, and how NaN payloads can be used to hold other things, like data type codes, integers, and pointers, hidden inside binary64 values.

entry:
@Misc{Cherkaev:2018:SLN,
  author =       "Annie Cherkaev",
  title =        "The secret life of {NaN}",
  howpublished = "Web site",
  month =        mar,
  year =         "2018",
  bibdate =      "Fri Dec 01 14:21:50 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://anniecherkaev.com/the-secret-life-of-nan",
  acknowledgement = ack-nhfb,
  remark =       "The site discusses IEEE 754 number encoding, and how
                 NaN payloads can be used to hold other things, like
                 data type codes, integers, and pointers, hidden inside
                 binary64 values.",
}


bibtype: inproceedings
filename: fparith.bib
label: Chung:2018:PCP
author: Shin Yee Chung
title: Provably Correct Posit Arithmetic with Fixed-Point Big Integer
crossref: ACM:2018:CNG
pages: 1--5
year: 2018
DOI: https://doi.org/10.1145/3190339.3190341
bibdate: Mon Dec 11 09:00:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.11 09:00:40 ???
keywords: posit arithmetic; universal number (unum) arithmetic
acknowledgement: ack-nhfb
articleno: 2
rawauthor: Shin Yee Chung
rawtitle: Provably Correct Posit Arithmetic with Fixed-Point Big Integer
entry:
@InProceedings{Chung:2018:PCP,
  author =       "Shin Yee Chung",
  title =        "Provably Correct Posit Arithmetic with Fixed-Point Big
                 Integer",
  crossref =     "ACM:2018:CNG",
  pages =        "1--5",
  year =         "2018",
  DOI =          "https://doi.org/10.1145/3190339.3190341",
  bibdate =      "Mon Dec 11 09:00:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  keywords =     "posit arithmetic; universal number (unum) arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Cococcioni:2018:EPA
author: Marco Cococcioni and Emanuele Ruffaldi and Sergio Saponara
editor: IEEE
booktitle: 2018 International Conference of Electrical and Electronic Technologies for Automotive
title: Exploiting Posit Arithmetic for Deep Neural Networks in Autonomous Driving Applications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2018
DOI: https://doi.org/10.23919/EETA.2018.8493233
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Marco Cococcioni and Emanuele Ruffaldi and Sergio Saponara
rawbooktitle: {2018 International Conference of Electrical and Electronic Technologies for Automotive}
raweditor: {IEEE}
rawtitle: Exploiting Posit Arithmetic for Deep Neural Networks in Autonomous Driving Applications
entry:
@InProceedings{Cococcioni:2018:EPA,
  author =       "Marco Cococcioni and Emanuele Ruffaldi and Sergio
                 Saponara",
  editor =       "{IEEE}",
  booktitle =    "{2018 International Conference of Electrical and
                 Electronic Technologies for Automotive}",
  title =        "Exploiting Posit Arithmetic for Deep Neural Networks
                 in Autonomous Driving Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2018",
  DOI =          "https://doi.org/10.23919/EETA.2018.8493233",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Costello:2018:MCT
author: Craig Costello and Benjamin Smith
title: Montgomery curves and their arithmetic
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 227--240
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0157-6
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
URL: http://link.springer.com/article/10.1007/s13389-017-0157-6
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Craig Costello and Benjamin Smith
rawtitle: {Montgomery} curves and their arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib

entry:
@Article{Costello:2018:MCT,
  author =       "Craig Costello and Benjamin Smith",
  title =        "{Montgomery} curves and their arithmetic",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "227--240",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0157-6",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0157-6",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Dai:2018:FBM
author: Wangchen Dai and Donglong Chen and Ray C. C. Cheung and Cetin Kaya Koc
title: FFT-Based McLaughlin's Montgomery Exponentiation without Conditional Selections
journal: j-IEEE-TRANS-COMPUT
volume: 67
number: 9
pages: 1301--1314
month: sep
monthnumber: 9
year: 2018
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2811466
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Mar 15 08:10:13 2019
bibtimestamp: 2019.03.15 08:10:13 ???
URL: https://ieeexplore.ieee.org/document/8307235/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Wangchen Dai and Donglong Chen and Ray C. C. Cheung and {\c{C}}etin Kaya Ko{\c{c}}
rawtitle: {FFT}-Based {McLaughlin}'s {Montgomery} Exponentiation without Conditional Selections
entry:
@Article{Dai:2018:FBM,
  author =       "Wangchen Dai and Donglong Chen and Ray C. C. Cheung
                 and {\c{C}}etin Kaya Ko{\c{c}}",
  title =        "{FFT}-Based {McLaughlin}'s {Montgomery} Exponentiation
                 without Conditional Selections",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "67",
  number =       "9",
  pages =        "1301--1314",
  month =        sep,
  year =         "2018",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2811466",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Mar 15 08:10:13 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "https://ieeexplore.ieee.org/document/8307235/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Dai:2018:SAM
author: Wangchen Dai and Ray C. C. Cheung
title: Spectral arithmetic in Montgomery modular multiplication
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 211--226
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0151-z
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
URL: http://link.springer.com/article/10.1007/s13389-017-0151-z
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Wangchen Dai and Ray C. C. Cheung
rawtitle: Spectral arithmetic in {Montgomery} modular multiplication
entry:
@Article{Dai:2018:SAM,
  author =       "Wangchen Dai and Ray C. C. Cheung",
  title =        "Spectral arithmetic in {Montgomery} modular
                 multiplication",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "211--226",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0151-z",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0151-z",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Das:2018:MPT
title: Mixed Precision Training of Convolutional Neural Networks using Integer Operations
journal: arXiv.org
pages: 11
day: 3
month: feb
monthnumber: 2
year: 2018
bibdate: Mon Feb 10 09:24:48 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 09:24:48 ???
URL: https://arxiv.org/abs/1802.00930
acknowledgement: ack-nhfb
rawtitle: Mixed Precision Training of Convolutional Neural Networks using Integer Operations
author:
Dipankar Das and Naveen Mellempudi and Dheevatsa Mudigere and Dhiraj Kalamkar and Sasikanth Avancha and Kunal Banerjee and Srinivas Sridharan and Karthik Vaidyanathan and Bharat Kaul and Evangelos Georganas and Alexander Heinecke and Pradeep Dubey and Jesus Corbal and Nikita Shustrov and Roma Dubtsov and Evarist Fomenko and Vadim Pirogov

abstract:
The state-of-the-art (SOTA) for mixed precision training is dominated by variants of low precision floating point operations, and in particular, FP16 accumulating into FP32 Micikevicius et al. (2017). On the other hand, while a lot of research has also happened in the domain of low and mixed-precision Integer training, these works either present results for non-SOTA networks (for instance only AlexNet for ImageNet-1K), or relatively small datasets (like CIFAR-10). In this work, we train state-of-the-art visual understanding neural networks on the ImageNet-1K dataset, with Integer operations on General Purpose (GP) hardware. In particular, we focus on Integer Fused-Multiply-and-Accumulate (FMA) operations which take two pairs of INT16 operands and accumulate results into an INT32 output.We propose a shared exponent representation of tensors and develop a Dynamic Fixed Point (DFP) scheme suitable for common neural network operations. The nuances of developing an efficient integer convolution kernel is examined, including methods to handle overflow of the INT32 accumulator. We implement CNN training for ResNet-50, GoogLeNet-v1, VGG-16 and AlexNet; and these networks achieve or exceed SOTA accuracy within the same number of iterations as their FP32 counterparts without any change in hyper-parameters and with a 1.8X improvement in end-to-end training throughput. To the best of our knowledge these results represent the first INT16 training results on GP hardware for ImageNet-1K dataset using SOTA CNNs and achieve highest reported accuracy using half-precision

rawabstract:
The state-of-the-art (SOTA) for mixed precision training is dominated by variants of low precision floating point operations, and in particular, FP16 accumulating into FP32 Micikevicius et al. (2017). On the other hand, while a lot of research has also happened in the domain of low and mixed-precision Integer training, these works either present results for non-SOTA networks (for instance only AlexNet for ImageNet-1K), or relatively small datasets (like CIFAR-10). In this work, we train state-of-the-art visual understanding neural networks on the ImageNet-1K dataset, with Integer operations on General Purpose (GP) hardware. In particular, we focus on Integer Fused-Multiply-and-Accumulate (FMA) operations which take two pairs of INT16 operands and accumulate results into an INT32 output.We propose a shared exponent representation of tensors and develop a Dynamic Fixed Point (DFP) scheme suitable for common neural network operations. The nuances of developing an efficient integer convolution kernel is examined, including methods to handle overflow of the INT32 accumulator. We implement CNN training for ResNet-50, GoogLeNet-v1, VGG-16 and AlexNet; and these networks achieve or exceed SOTA accuracy within the same number of iterations as their FP32 counterparts without any change in hyper-parameters and with a 1.8X improvement in end-to-end training throughput. To the best of our knowledge these results represent the first INT16 training results on GP hardware for ImageNet-1K dataset using SOTA CNNs and achieve highest reported accuracy using half-precision

rawauthor:
Dipankar Das and Naveen Mellempudi and Dheevatsa Mudigere and Dhiraj Kalamkar and Sasikanth Avancha and Kunal Banerjee and Srinivas Sridharan and Karthik Vaidyanathan and Bharat Kaul and Evangelos Georganas and Alexander Heinecke and Pradeep Dubey and Jesus Corbal and Nikita Shustrov and Roma Dubtsov and Evarist Fomenko and Vadim Pirogov

entry:
@Article{Das:2018:MPT,
  author =       "Dipankar Das and Naveen Mellempudi and Dheevatsa
                 Mudigere and Dhiraj Kalamkar and Sasikanth Avancha and
                 Kunal Banerjee and Srinivas Sridharan and Karthik
                 Vaidyanathan and Bharat Kaul and Evangelos Georganas
                 and Alexander Heinecke and Pradeep Dubey and Jesus
                 Corbal and Nikita Shustrov and Roma Dubtsov and Evarist
                 Fomenko and Vadim Pirogov",
  title =        "Mixed Precision Training of Convolutional Neural
                 Networks using Integer Operations",
  journal =      "arXiv.org",
  pages =        "11",
  day =          "3",
  month =        feb,
  year =         "2018",
  bibdate =      "Mon Feb 10 09:24:48 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1802.00930",
  abstract =     "The state-of-the-art (SOTA) for mixed precision
                 training is dominated by variants of low precision
                 floating point operations, and in particular, FP16
                 accumulating into FP32 Micikevicius et al. (2017). On
                 the other hand, while a lot of research has also
                 happened in the domain of low and mixed-precision
                 Integer training, these works either present results
                 for non-SOTA networks (for instance only AlexNet for
                 ImageNet-1K), or relatively small datasets (like
                 CIFAR-10). In this work, we train state-of-the-art
                 visual understanding neural networks on the ImageNet-1K
                 dataset, with Integer operations on General Purpose
                 (GP) hardware. In particular, we focus on Integer
                 Fused-Multiply-and-Accumulate (FMA) operations which
                 take two pairs of INT16 operands and accumulate results
                 into an INT32 output.We propose a shared exponent
                 representation of tensors and develop a Dynamic Fixed
                 Point (DFP) scheme suitable for common neural network
                 operations. The nuances of developing an efficient
                 integer convolution kernel is examined, including
                 methods to handle overflow of the INT32 accumulator. We
                 implement CNN training for ResNet-50, GoogLeNet-v1,
                 VGG-16 and AlexNet; and these networks achieve or
                 exceed SOTA accuracy within the same number of
                 iterations as their FP32 counterparts without any
                 change in hyper-parameters and with a 1.8X improvement
                 in end-to-end training throughput. To the best of our
                 knowledge these results represent the first INT16
                 training results on GP hardware for ImageNet-1K dataset
                 using SOTA CNNs and achieve highest reported accuracy
                 using half-precision",
  acknowledgement = ack-nhfb,
  primaryclass = "cs.NE",
}


bibtype: inproceedings
filename: fparith.bib
label: Defour:2018:FAR
author: David Defour
title: FP-ANR: A representation format to handle floating-point cancellation at run-time
crossref: Tenca:2018:PIS
pages: 76--83
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464784
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: David Defour
rawtitle: {FP-ANR}: A representation format to handle floating-point cancellation at run-time
abstract:
When dealing with floating-point numbers, there are several sources of error which can drastically reduce the numerical quality of computed results. One of those error sources is the loss of significance or cancellation, which occurs during for example, the subtraction of two nearly equal numbers. In this article, we propose a representation format named Floating-Point Adaptive Noise Reduction (FP-ANR). This format embeds cancellation information directly into the floating-point representation format thanks to a dedicated pattern. With this format, insignificant trailing bits lost during cancellation are removed from every manipulated floating-point number. The immediate consequence is that it increases the numerical confidence of computed values. The proposed representation format corresponds to a simple and efficient implementation of significance arithmetic based and compatible with the IEEE Standard 754 standard.

keywords:
adaptive signal processing; ARITH-25; cancellation information; Computers; Encoding; floating point arithmetic; Floating-Point Adaptive Noise Reduction; floating-point cancellation; floating-point numbers; floating-point representation format; FP-ANR; IEEE Standard 754 standard; IEEE standards; IEEE Standards; interference suppression; Noise reduction; numerical quality; signal denoising; Software; Uncertainty

rawabstract:
When dealing with floating-point numbers, there are several sources of error which can drastically reduce the numerical quality of computed results. One of those error sources is the loss of significance or cancellation, which occurs during for example, the subtraction of two nearly equal numbers. In this article, we propose a representation format named Floating-Point Adaptive Noise Reduction (FP-ANR). This format embeds cancellation information directly into the floating-point representation format thanks to a dedicated pattern. With this format, insignificant trailing bits lost during cancellation are removed from every manipulated floating-point number. The immediate consequence is that it increases the numerical confidence of computed values. The proposed representation format corresponds to a simple and efficient implementation of significance arithmetic based and compatible with the IEEE Standard 754 standard.

entry:
@InProceedings{Defour:2018:FAR,
  author =       "David Defour",
  title =        "{FP-ANR}: A representation format to handle
                 floating-point cancellation at run-time",
  crossref =     "Tenca:2018:PIS",
  pages =        "76--83",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464784",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "When dealing with floating-point numbers, there are
                 several sources of error which can drastically reduce
                 the numerical quality of computed results. One of those
                 error sources is the loss of significance or
                 cancellation, which occurs during for example, the
                 subtraction of two nearly equal numbers. In this
                 article, we propose a representation format named
                 Floating-Point Adaptive Noise Reduction (FP-ANR). This
                 format embeds cancellation information directly into
                 the floating-point representation format thanks to a
                 dedicated pattern. With this format, insignificant
                 trailing bits lost during cancellation are removed from
                 every manipulated floating-point number. The immediate
                 consequence is that it increases the numerical
                 confidence of computed values. The proposed
                 representation format corresponds to a simple and
                 efficient implementation of significance arithmetic
                 based and compatible with the IEEE Standard 754
                 standard.",
  acknowledgement = ack-nhfb,
  keywords =     "adaptive signal processing; ARITH-25; cancellation
                 information; Computers; Encoding; floating point
                 arithmetic; Floating-Point Adaptive Noise Reduction;
                 floating-point cancellation; floating-point numbers;
                 floating-point representation format; FP-ANR; IEEE
                 Standard 754 standard; IEEE standards; IEEE Standards;
                 interference suppression; Noise reduction; numerical
                 quality; signal denoising; Software; Uncertainty",
}


bibtype: article
filename: fparith.bib
label: Demmel:2018:RBM
author: James Demmel and Jason Riedy and Peter Ahrens
title: Reproducible BLAS: Make Addition Associative Again!
journal: j-SIAM-NEWS
volume: 51
number: 8
pages: ??--??
month: oct
monthnumber: 10
year: 2018
ISSN: 0036-1437 OR 00361437
ISSNL: 0036-1437 OR 00361437
bibdate: Sat Oct 06 08:42:06 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.10.06 08:42:06 ???
URL: https://sinews.siam.org/Details-Page/reproducible-blas-make-addition-associative-again
fjournal: SIAM News
acknowledgement: ack-nhfb
journalURL: http://www.siam.org/news/
rawauthor: James Demmel and Jason Riedy and Peter Ahrens
rawtitle: {Reproducible BLAS}: Make Addition Associative Again!
entry:
@Article{Demmel:2018:RBM,
  author =       "James Demmel and Jason Riedy and Peter Ahrens",
  title =        "{Reproducible BLAS}: Make Addition Associative
                 Again!",
  journal =      j-SIAM-NEWS,
  volume =       "51",
  number =       "8",
  pages =        "??--??",
  month =        oct,
  year =         "2018",
  ISSN =         "0036-1437",
  ISSN-L =       "0036-1437",
  bibdate =      "Sat Oct 06 08:42:06 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://sinews.siam.org/Details-Page/reproducible-blas-make-addition-associative-again",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM News",
  journal-URL =  "http://www.siam.org/news/",
}


bibtype: article
filename: fparith.bib
label: Dolbeau:2018:TPF
author: Romain Dolbeau
title: Theoretical peak FLOPS per instruction set: a tutorial
journal: j-J-SUPERCOMPUTING
volume: 74
number: 3
pages: 1341--1377
month: mar
monthnumber: 3
year: 2018
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-017-2177-5
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Fri Mar 2 12:22:02 MST 2018
bibtimestamp: 2018.03.02 12:22:02 MST
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11227
rawauthor: Romain Dolbeau
rawtitle: Theoretical peak {FLOPS} per instruction set: a tutorial
bibsource:
http://link.springer.com/journal/11227/74/3; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jsuper2010.bib; https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib

entry:
@Article{Dolbeau:2018:TPF,
  author =       "Romain Dolbeau",
  title =        "Theoretical peak {FLOPS} per instruction set: a
                 tutorial",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "74",
  number =       "3",
  pages =        "1341--1377",
  month =        mar,
  year =         "2018",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-017-2177-5",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Fri Mar 2 12:22:02 MST 2018",
  bibsource =    "http://link.springer.com/journal/11227/74/3;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: article
filename: fparith.bib
label: Doliskani:2018:SCR
author: Javad Doliskani and Pascal Giorgi and Romain Lebreton and Eric Schost
title: Simultaneous Conversions with the Residue Number System Using Linear Algebra
journal: j-TOMS
volume: 44
number: 3
pages: 27:1--27:21
month: apr
monthnumber: 4
year: 2018
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3145573
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Mon Jan 22 17:49:32 MST 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2018.01.22 17:49:32 MST
URL: https://dl.acm.org/citation.cfm?id=3145573
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 27
journalURL: https://dl.acm.org/loi/toms
rawauthor: Javad Doliskani and Pascal Giorgi and Romain Lebreton and Eric Schost
rawtitle: Simultaneous Conversions with the Residue Number System Using Linear Algebra
abstract:
We present an algorithm for simultaneous conversions between a given set of integers and their Residue Number System representations based on linear algebra. We provide a highly optimized implementation of the algorithm that exploits the computational features of modern processors. The main application of our algorithm is matrix multiplication over integers. Our speed-up of the conversions to and from the Residue Number System significantly improves the overall running time of matrix multiplication.

rawabstract:
We present an algorithm for simultaneous conversions between a given set of integers and their Residue Number System representations based on linear algebra. We provide a highly optimized implementation of the algorithm that exploits the computational features of modern processors. The main application of our algorithm is matrix multiplication over integers. Our speed-up of the conversions to and from the Residue Number System significantly improves the overall running time of matrix multiplication.

entry:
@Article{Doliskani:2018:SCR,
  author =       "Javad Doliskani and Pascal Giorgi and Romain Lebreton
                 and Eric Schost",
  title =        "Simultaneous Conversions with the Residue Number
                 System Using Linear Algebra",
  journal =      j-TOMS,
  volume =       "44",
  number =       "3",
  pages =        "27:1--27:21",
  month =        apr,
  year =         "2018",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3145573",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Mon Jan 22 17:49:32 MST 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3145573",
  abstract =     "We present an algorithm for simultaneous conversions
                 between a given set of integers and their Residue
                 Number System representations based on linear algebra.
                 We provide a highly optimized implementation of the
                 algorithm that exploits the computational features of
                 modern processors. The main application of our
                 algorithm is matrix multiplication over integers. Our
                 speed-up of the conversions to and from the Residue
                 Number System significantly improves the overall
                 running time of matrix multiplication.",
  acknowledgement = ack-nhfb,
  articleno =    "27",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Dosso:2018:EAC
author: Yssouf Dosso and Fabien Herbaut and Nicolas Meloni and Pascal Veron
title: Euclidean addition chains scalar multiplication on curves with efficient endomorphism
journal: j-J-CRYPTO-ENG
volume: 8
number: 4
pages: 351--367
month: nov
monthnumber: 11
year: 2018
DOI: https://doi.org/10.1007/s13389-018-0190-0
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
URL: http://link.springer.com/article/10.1007/s13389-018-0190-0
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Yssouf Dosso and Fabien Herbaut and Nicolas M{\'e}loni and Pascal V{\'e}ron
rawtitle: {Euclidean} addition chains scalar multiplication on curves with efficient endomorphism
entry:
@Article{Dosso:2018:EAC,
  author =       "Yssouf Dosso and Fabien Herbaut and Nicolas M{\'e}loni
                 and Pascal V{\'e}ron",
  title =        "{Euclidean} addition chains scalar multiplication on
                 curves with efficient endomorphism",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "4",
  pages =        "351--367",
  month =        nov,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-018-0190-0",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-018-0190-0",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: inproceedings
filename: fparith.bib
label: Drucker:2018:CRS
author: Nir Drucker and Shay Gueron and Vlad Krasnov
title: The Comeback of Reed--Solomon Codes
crossref: Tenca:2018:PIS
pages: 125--129
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464690
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Nir Drucker and Shay Gueron and Vlad Krasnov
rawtitle: The Comeback of {Reed--Solomon} Codes
abstract:
Distributed storage systems utilize erasure codes to reduce their storage costs while efficiently handling failures. Many of these codes (e.g., Reed-Solomon (RS) codes) rely on Galois Field (GF) arithmetic, which is considered to be fast when the field characteristic is 2. Nevertheless, some developments in the field of erasure codes offer new efficient techniques that require mostly XOR operations, and are thus faster than GF operations. Recently, Intel announced [1] that its future architecture (codename Ice Lake) will introduce new set of instructions called Galois Field New Instruction (GF-NI). These instructions allow software flows to perform vector and matrix multiplications over GF ($ 2^8$) on the wide registers that are available on the AVX512 architectures. In this paper, we explain the functionality of these instructions, and demonstrate their usage for some fast computations in GF($ 2^8$). We also use the Intel Intelligent Storage Acceleration Library (ISA-L) in order to estimate potential future improvement for erasure codes that are based on RS codes. Our results predict $ 1.4 times $ speedup for vectorized multiplication, and $ 1.83 times $ speedup for the actual encoding.

keywords:
Acceleration; ARITH-25; AVX512 architectures; codename Ice Lake; Computer architecture; distributed storage systems; Encoding; erasure codes; field characteristic; Galois Field arithmetic; Galois fields; GF operations; GF-NI; Intel; Intelligent Storage Acceleration Library; matrix multiplication; matrix multiplications; Reed-Solomon codes; Registers; RS codes; storage costs; vector; vectors; Web services; XOR operations

rawabstract:
Distributed storage systems utilize erasure codes to reduce their storage costs while efficiently handling failures. Many of these codes (e.g., Reed-Solomon (RS) codes) rely on Galois Field (GF) arithmetic, which is considered to be fast when the field characteristic is 2. Nevertheless, some developments in the field of erasure codes offer new efficient techniques that require mostly XOR operations, and are thus faster than GF operations. Recently, Intel announced [1] that its future architecture (codename Ice Lake) will introduce new set of instructions called Galois Field New Instruction (GF-NI). These instructions allow software flows to perform vector and matrix multiplications over GF ($ 2^8$) on the wide registers that are available on the AVX512 architectures. In this paper, we explain the functionality of these instructions, and demonstrate their usage for some fast computations in GF($ 2^8$). We also use the Intel Intelligent Storage Acceleration Library (ISA-L) in order to estimate potential future improvement for erasure codes that are based on RS codes. Our results predict $ 1.4 \times $ speedup for vectorized multiplication, and $ 1.83 \times $ speedup for the actual encoding.

entry:
@InProceedings{Drucker:2018:CRS,
  author =       "Nir Drucker and Shay Gueron and Vlad Krasnov",
  title =        "The Comeback of {Reed--Solomon} Codes",
  crossref =     "Tenca:2018:PIS",
  pages =        "125--129",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464690",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Distributed storage systems utilize erasure codes to
                 reduce their storage costs while efficiently handling
                 failures. Many of these codes (e.g., Reed-Solomon (RS)
                 codes) rely on Galois Field (GF) arithmetic, which is
                 considered to be fast when the field characteristic is
                 2. Nevertheless, some developments in the field of
                 erasure codes offer new efficient techniques that
                 require mostly XOR operations, and are thus faster than
                 GF operations. Recently, Intel announced [1] that its
                 future architecture (codename Ice Lake) will introduce
                 new set of instructions called Galois Field New
                 Instruction (GF-NI). These instructions allow software
                 flows to perform vector and matrix multiplications over
                 GF ($ 2^8$) on the wide registers that are available on
                 the AVX512 architectures. In this paper, we explain the
                 functionality of these instructions, and demonstrate
                 their usage for some fast computations in GF($ 2^8$).
                 We also use the Intel Intelligent Storage Acceleration
                 Library (ISA-L) in order to estimate potential future
                 improvement for erasure codes that are based on RS
                 codes. Our results predict $ 1.4 \times $ speedup for
                 vectorized multiplication, and $ 1.83 \times $ speedup
                 for the actual encoding.",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; ARITH-25; AVX512 architectures; codename
                 Ice Lake; Computer architecture; distributed storage
                 systems; Encoding; erasure codes; field characteristic;
                 Galois Field arithmetic; Galois fields; GF operations;
                 GF-NI; Intel; Intelligent Storage Acceleration Library;
                 matrix multiplication; matrix multiplications;
                 Reed-Solomon codes; Registers; RS codes; storage costs;
                 vector; vectors; Web services; XOR operations",
}


bibtype: inproceedings
filename: fparith.bib
label: Drucker:2018:FMB
author: Nir Drucker and Shay Gueron and Vlad Krasnov
title: Fast multiplication of binary polynomials with the forthcoming vectorized VPCLMULQDQ instruction
crossref: Tenca:2018:PIS
pages: 115--119
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464777
bibdate: Fri Jan 31 08:05:31 2020
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Nir Drucker and Shay Gueron and Vlad Krasnov
rawtitle: Fast multiplication of binary polynomials with the forthcoming vectorized {VPCLMULQDQ} instruction
abstract:
Polynomial multiplication over binary fields $ mathbb F_2^n $ is a common primitive, used for example by current cryptosystems such as AES-GCM (with $ n = 128$). It also turns out to be a primitive for other cryptosystems, that are being designed for the Post Quantum era, with values n 128. Examples from the recent submissions to the NIST Post-Quantum Cryptography project, are BIKE, LEDAKem, and GeMSS, where the performance of the polynomial multiplications, is significant. Therefore, efficient polynomial multiplication over $ mathbb F_2^n$, with large $n$, is a significant emerging optimization target. Anticipating future applications, Intel has recently announced that its future architecture (codename Ice Lake) will introduce a new vectorized way to use the current VPCLMULQDQ instruction. In this paper, we demonstrate how to use this instruction for accelerating polynomial multiplication. Our analysis shows a prediction for at least $ 2 times $ speedup for multiplications with polynomials of degree 512 or more.

keywords:
Acceleration; AES-GCM; ARITH-25; BIKE; binary field-mathbbF2n; Computer architecture; Cryptography; cryptosystems; fast binary polynomial multiplication; fast multiplication; GeMSS; ice lake; LEDAKem; NIST; NIST Post-Quantum Cryptography project; optimisation; Optimization; optimization target; polynomials; post quantum cryptography; quantum cryptography; Registers; vectorized VPCLMULQDQ instruction; Web services

rawabstract:
Polynomial multiplication over binary fields $ \mathbb {F}_{2^n} $ is a common primitive, used for example by current cryptosystems such as AES-GCM (with $ n = 128$). It also turns out to be a primitive for other cryptosystems, that are being designed for the Post Quantum era, with values n 128. Examples from the recent submissions to the NIST Post-Quantum Cryptography project, are BIKE, LEDAKem, and GeMSS, where the performance of the polynomial multiplications, is significant. Therefore, efficient polynomial multiplication over $ \mathbb {F}_{2^n}$, with large $n$, is a significant emerging optimization target. Anticipating future applications, Intel has recently announced that its future architecture (codename Ice Lake) will introduce a new vectorized way to use the current VPCLMULQDQ instruction. In this paper, we demonstrate how to use this instruction for accelerating polynomial multiplication. Our analysis shows a prediction for at least $ 2 \times $ speedup for multiplications with polynomials of degree 512 or more.

entry:
@InProceedings{Drucker:2018:FMB,
  author =       "Nir Drucker and Shay Gueron and Vlad Krasnov",
  title =        "Fast multiplication of binary polynomials with the
                 forthcoming vectorized {VPCLMULQDQ} instruction",
  crossref =     "Tenca:2018:PIS",
  pages =        "115--119",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464777",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Polynomial multiplication over binary fields $ \mathbb
                 {F}_{2^n} $ is a common primitive, used for example by
                 current cryptosystems such as AES-GCM (with $ n =
                 128$). It also turns out to be a primitive for other
                 cryptosystems, that are being designed for the Post
                 Quantum era, with values n 128. Examples from the
                 recent submissions to the NIST Post-Quantum
                 Cryptography project, are BIKE, LEDAKem, and GeMSS,
                 where the performance of the polynomial
                 multiplications, is significant. Therefore, efficient
                 polynomial multiplication over $ \mathbb {F}_{2^n}$,
                 with large $n$, is a significant emerging optimization
                 target. Anticipating future applications, Intel has
                 recently announced that its future architecture
                 (codename Ice Lake) will introduce a new vectorized way
                 to use the current VPCLMULQDQ instruction. In this
                 paper, we demonstrate how to use this instruction for
                 accelerating polynomial multiplication. Our analysis
                 shows a prediction for at least $ 2 \times $ speedup
                 for multiplications with polynomials of degree 512 or
                 more.",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; AES-GCM; ARITH-25; BIKE; binary
                 field-mathbbF2n; Computer architecture; Cryptography;
                 cryptosystems; fast binary polynomial multiplication;
                 fast multiplication; GeMSS; ice lake; LEDAKem; NIST;
                 NIST Post-Quantum Cryptography project; optimisation;
                 Optimization; optimization target; polynomials; post
                 quantum cryptography; quantum cryptography; Registers;
                 vectorized VPCLMULQDQ instruction; Web services",
}


bibtype: article
filename: fparith.bib
label: Dutt:2018:ADA
author: Sunil Dutt and Sukumar Nandi and Gaurav Trivedi
title: Analysis and Design of Adders for Approximate Computing
journal: j-TECS
volume: 17
number: 2
pages: 40:1--40:??
month: apr
monthnumber: 4
year: 2018
DOI: https://doi.org/10.1145/3131274
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Thu Oct 17 18:16:34 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tecs.bib
bibtimestamp: 2019.10.17 18:16:34 MDT
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
articleno: 40
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J840
rawauthor: Sunil Dutt and Sukumar Nandi and Gaurav Trivedi
rawtitle: Analysis and Design of Adders for Approximate Computing
abstract:
The concept of approximate computing, that is, to sacrifice computation quality for computation efforts, has recently emerged as a promising design approach. Over the past decade, several research works have explored approximate computing at both the software level and hardware level of abstraction with encouraging results. At the hardware level of abstraction, adders (being the fundamental and most widely used data operators in digital systems) have attracted a significant attention for approximation. In this article, we first explain briefly the need/significance of approximate adders. We then propose four Approximate Full Adders (AFAs) for high-performance energy-efficient approximate computing. The key design objective behind the proposed AFAs is to curtail the length of carry propagation subjected to minimal error rate. Next, we exploit one of the proposed AFAs (optimal one) to construct an N-bit approximate adder that hereinafter is referred as ``ApproxADD.'' An emergent property of ApproxADD is that carries do not propagate in it, and, consequently, it provides bit-width-aware constant delay (O(1)). ApproxADD also provides improvement in dynamic power consumption by 46.31% and in area by 28.57% w.r.t. Ripple Carry Adder (RCA), which exhibits the lowest power and area. Although ApproxADD provides a significant improvement in delay, power, and area, it may not be preferred for some of the error-resilient applications because its: (i) Error Distance (ED) is too high; and (ii) Error Rate (ER) increases rapidly with bit-width ($N$). To improve ED and ER, we exploit the concept of carry-lifetime and Error Detection and Correction logic, respectively. In this way, we introduce two more (improved) versions of ApproxADD--ApproxADD $ upsilon $ 1 and ApproxADD. We call these as ApproxADD $ upsilon $ 1 and ApproxADD $ upsilon $ 2 with existing approximate adders based on conventional design metrics and approximate computing design metrics. Furthermore, to inspect effectiveness of the proposed approach in real-life applications, we demonstrate image compression and decompression by replacing the conventional addition operations in Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) modules with ApproxADD $ upsilon $ 2.

rawabstract:
The concept of approximate computing, that is, to sacrifice computation quality for computation efforts, has recently emerged as a promising design approach. Over the past decade, several research works have explored approximate computing at both the software level and hardware level of abstraction with encouraging results. At the hardware level of abstraction, adders (being the fundamental and most widely used data operators in digital systems) have attracted a significant attention for approximation. In this article, we first explain briefly the need/significance of approximate adders. We then propose four Approximate Full Adders (AFAs) for high-performance energy-efficient approximate computing. The key design objective behind the proposed AFAs is to curtail the length of carry propagation subjected to minimal error rate. Next, we exploit one of the proposed AFAs (optimal one) to construct an N-bit approximate adder that hereinafter is referred as ``ApproxADD.'' An emergent property of ApproxADD is that carries do not propagate in it, and, consequently, it provides bit-width-aware constant delay (O(1)). ApproxADD also provides improvement in dynamic power consumption by 46.31\% and in area by 28.57\% w.r.t. Ripple Carry Adder (RCA), which exhibits the lowest power and area. Although ApproxADD provides a significant improvement in delay, power, and area, it may not be preferred for some of the error-resilient applications because its: (i) Error Distance (ED) is too high; and (ii) Error Rate (ER) increases rapidly with bit-width ($N$). To improve ED and ER, we exploit the concept of carry-lifetime and Error Detection and Correction logic, respectively. In this way, we introduce two more (improved) versions of ApproxADD--ApproxADD $ \upsilon $ 1 and ApproxADD. We call these as ApproxADD $ \upsilon $ 1 and ApproxADD $ \upsilon $ 2 with existing approximate adders based on conventional design metrics and approximate computing design metrics. Furthermore, to inspect effectiveness of the proposed approach in real-life applications, we demonstrate image compression and decompression by replacing the conventional addition operations in Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) modules with ApproxADD $ \upsilon $ 2.

entry:
@Article{Dutt:2018:ADA,
  author =       "Sunil Dutt and Sukumar Nandi and Gaurav Trivedi",
  title =        "Analysis and Design of Adders for Approximate
                 Computing",
  journal =      j-TECS,
  volume =       "17",
  number =       "2",
  pages =        "40:1--40:??",
  month =        apr,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3131274",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Thu Oct 17 18:16:34 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tecs.bib",
  abstract =     "The concept of approximate computing, that is, to
                 sacrifice computation quality for computation efforts,
                 has recently emerged as a promising design approach.
                 Over the past decade, several research works have
                 explored approximate computing at both the software
                 level and hardware level of abstraction with
                 encouraging results. At the hardware level of
                 abstraction, adders (being the fundamental and most
                 widely used data operators in digital systems) have
                 attracted a significant attention for approximation. In
                 this article, we first explain briefly the
                 need/significance of approximate adders. We then
                 propose four Approximate Full Adders (AFAs) for
                 high-performance energy-efficient approximate
                 computing. The key design objective behind the proposed
                 AFAs is to curtail the length of carry propagation
                 subjected to minimal error rate. Next, we exploit one
                 of the proposed AFAs (optimal one) to construct an
                 N-bit approximate adder that hereinafter is referred as
                 ``ApproxADD.'' An emergent property of ApproxADD is
                 that carries do not propagate in it, and, consequently,
                 it provides bit-width-aware constant delay (O(1)).
                 ApproxADD also provides improvement in dynamic power
                 consumption by 46.31\% and in area by 28.57\% w.r.t.
                 Ripple Carry Adder (RCA), which exhibits the lowest
                 power and area. Although ApproxADD provides a
                 significant improvement in delay, power, and area, it
                 may not be preferred for some of the error-resilient
                 applications because its: (i) Error Distance (ED) is
                 too high; and (ii) Error Rate (ER) increases rapidly
                 with bit-width ($N$). To improve ED and ER, we exploit
                 the concept of carry-lifetime and Error Detection and
                 Correction logic, respectively. In this way, we
                 introduce two more (improved) versions of
                 ApproxADD--ApproxADD $ \upsilon $ 1 and ApproxADD. We
                 call these as ApproxADD $ \upsilon $ 1 and ApproxADD $
                 \upsilon $ 2 with existing approximate adders based on
                 conventional design metrics and approximate computing
                 design metrics. Furthermore, to inspect effectiveness
                 of the proposed approach in real-life applications, we
                 demonstrate image compression and decompression by
                 replacing the conventional addition operations in
                 Discrete Cosine Transform (DCT) and Inverse Discrete
                 Cosine Transform (IDCT) modules with ApproxADD $
                 \upsilon $ 2.",
  acknowledgement = ack-nhfb,
  articleno =    "40",
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J840",
}


bibtype: inproceedings
filename: fparith.bib
label: Emmart:2018:FME
author: Niall Emmart and Fangyu Zhengt and Charles Weems
title: Faster Modular Exponentiation Using Double Precision Floating Point Arithmetic on the GPU
crossref: Tenca:2018:PIS
pages: 130--137
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464792
bibdate: Fri Jan 31 08:05:31 2020
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Niall Emmart and Fangyu Zhengt and Charles Weems
rawtitle: Faster Modular Exponentiation Using Double Precision Floating Point Arithmetic on the {GPU}
abstract:
This paper presents a new approach to integer multiple precision (MP) modular exponentiation, using double-precision floating point (DPF) operations, that is suitable for GPU implementation. We show speedups ranging from 20% to 34% over the best prior GPU times for sizes corresponding to common RSA cryptographic operations (2048 to 4096 bits). Three techniques are described. First, by adding $ 2^104 $ to the high half of the product, and $ 2^52 $ to the low half, we set the implicit leading 1 in the DPF mantissa so that the full 52 explicit bits are available for each half of the 104-bit products of samples. Second, the DPF values are cast bitwise to 64-bit integers for adding the column sums to get the MP result. Normally the cast would require masking off the exponents, but because they are constant, we can include them in the column sums and correct just once for their total. Third, by initializing the column sums with the appropriate negative value to compensate for the exponent sums, no corrective subtraction is needed. Our implementation on an NVIDIA GTX Titan Black GPU achieves between 132.5K and 161.9K modular exponentiations per second of size 1024 bits, with latencies ranging from 21.7 ms to 17.8 ms, making it practical for online RSA applications. Proportional results are shown for 1536 and 2048 bits. The implementation is so efficient that its maximum sustained performance is actually bounded by the thermal limit of the GPU.

keywords:
appropriate negative value; ARITH-25; column sums; common RSA cryptographic operations; Computer architecture; cryptography; Cryptography; double precision floating point arithmetic; DPF mantissa; exponent sum compensation; faster modular exponentiation; floating point arithmetic; Floating-point arithmetic; Graphics processing units; graphics processing units; Hardware; integer multiple precision modular exponentiation; multiple precision modular exponentiation; NVIDIA GTX Titan Black GPU; online RSA applications; parallel architectures; time 17.8 ms to 21.7 ms; word length 1024.0 bit; word length 104 bit; word length 1536.0 bit; word length 2048 bit to 4096 bit; word length 64 bit

rawabstract:
This paper presents a new approach to integer multiple precision (MP) modular exponentiation, using double-precision floating point (DPF) operations, that is suitable for GPU implementation. We show speedups ranging from 20\% to 34\% over the best prior GPU times for sizes corresponding to common RSA cryptographic operations (2048 to 4096 bits). Three techniques are described. First, by adding $ 2^{104} $ to the high half of the product, and $ 2^{52} $ to the low half, we set the implicit leading 1 in the DPF mantissa so that the full 52 explicit bits are available for each half of the 104-bit products of samples. Second, the DPF values are cast bitwise to 64-bit integers for adding the column sums to get the MP result. Normally the cast would require masking off the exponents, but because they are constant, we can include them in the column sums and correct just once for their total. Third, by initializing the column sums with the appropriate negative value to compensate for the exponent sums, no corrective subtraction is needed. Our implementation on an NVIDIA GTX Titan Black GPU achieves between 132.5K and 161.9K modular exponentiations per second of size 1024 bits, with latencies ranging from 21.7 ms to 17.8 ms, making it practical for online RSA applications. Proportional results are shown for 1536 and 2048 bits. The implementation is so efficient that its maximum sustained performance is actually bounded by the thermal limit of the GPU.

entry:
@InProceedings{Emmart:2018:FME,
  author =       "Niall Emmart and Fangyu Zhengt and Charles Weems",
  title =        "Faster Modular Exponentiation Using Double Precision
                 Floating Point Arithmetic on the {GPU}",
  crossref =     "Tenca:2018:PIS",
  pages =        "130--137",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464792",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents a new approach to integer multiple
                 precision (MP) modular exponentiation, using
                 double-precision floating point (DPF) operations, that
                 is suitable for GPU implementation. We show speedups
                 ranging from 20\% to 34\% over the best prior GPU times
                 for sizes corresponding to common RSA cryptographic
                 operations (2048 to 4096 bits). Three techniques are
                 described. First, by adding $ 2^{104} $ to the high
                 half of the product, and $ 2^{52} $ to the low half, we
                 set the implicit leading 1 in the DPF mantissa so that
                 the full 52 explicit bits are available for each half
                 of the 104-bit products of samples. Second, the DPF
                 values are cast bitwise to 64-bit integers for adding
                 the column sums to get the MP result. Normally the cast
                 would require masking off the exponents, but because
                 they are constant, we can include them in the column
                 sums and correct just once for their total. Third, by
                 initializing the column sums with the appropriate
                 negative value to compensate for the exponent sums, no
                 corrective subtraction is needed. Our implementation on
                 an NVIDIA GTX Titan Black GPU achieves between 132.5K
                 and 161.9K modular exponentiations per second of size
                 1024 bits, with latencies ranging from 21.7 ms to 17.8
                 ms, making it practical for online RSA applications.
                 Proportional results are shown for 1536 and 2048 bits.
                 The implementation is so efficient that its maximum
                 sustained performance is actually bounded by the
                 thermal limit of the GPU.",
  acknowledgement = ack-nhfb,
  keywords =     "appropriate negative value; ARITH-25; column sums;
                 common RSA cryptographic operations; Computer
                 architecture; cryptography; Cryptography; double
                 precision floating point arithmetic; DPF mantissa;
                 exponent sum compensation; faster modular
                 exponentiation; floating point arithmetic;
                 Floating-point arithmetic; Graphics processing units;
                 graphics processing units; Hardware; integer multiple
                 precision modular exponentiation; multiple precision
                 modular exponentiation; NVIDIA GTX Titan Black GPU;
                 online RSA applications; parallel architectures; time
                 17.8 ms to 21.7 ms; word length 1024.0 bit; word length
                 104 bit; word length 1536.0 bit; word length 2048 bit
                 to 4096 bit; word length 64 bit",
}


bibtype: inproceedings
filename: fparith.bib
label: Emmart:2018:NVB
author: Niall Emmart and Fangyu Zheng and Charles Weems
title: A New Variant of the Barrett Algorithm Applied to Quotient Selection
crossref: Tenca:2018:PIS
pages: 138--144
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464771
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Niall Emmart and Fangyu Zheng and Charles Weems
rawtitle: A New Variant of the {Barrett} Algorithm Applied to Quotient Selection
abstract:
Quotient Selection (QS) is a key step in the classic $ O(n^2) $ multiple precision division algorithm. On processors with fast hardware division, it is a trivial problem, but on GPUs, division is quite slow. In this paper we investigate the effectiveness of Brent and Zimmermann's variant as well as our own novel variant of Barrett's algorithm. Our new approach is shown to be suitable for low radix (single precision) QS. Three highly optimized implementations, two of the Brent and Zimmerman variant and one based on our new approach, have been developed and we show that each is many times faster than using the division operation built in to the compiler. In addition, our variant is on average 22% faster than the other two implementations. We also sketch proofs of correctness for all of the implementations and our new algorithm.

keywords:
Approximation algorithms; ARITH-25; Barrett algorithm; Barrett reduction; classic $O(n^2)$ multiple precision division algorithm; Computer security; digital arithmetic; Digital arithmetic; division operation; fast hardware division; GPU; graphics processing units; Hardware; low radix QS; multiple precision division; Newton method; O; processors; Program processors; quotient selection; Zimmermann variant

rawabstract:
Quotient Selection (QS) is a key step in the classic $ O(n^2) $ multiple precision division algorithm. On processors with fast hardware division, it is a trivial problem, but on GPUs, division is quite slow. In this paper we investigate the effectiveness of Brent and Zimmermann's variant as well as our own novel variant of Barrett's algorithm. Our new approach is shown to be suitable for low radix (single precision) QS. Three highly optimized implementations, two of the Brent and Zimmerman variant and one based on our new approach, have been developed and we show that each is many times faster than using the division operation built in to the compiler. In addition, our variant is on average 22\% faster than the other two implementations. We also sketch proofs of correctness for all of the implementations and our new algorithm.

entry:
@InProceedings{Emmart:2018:NVB,
  author =       "Niall Emmart and Fangyu Zheng and Charles Weems",
  title =        "A New Variant of the {Barrett} Algorithm Applied to
                 Quotient Selection",
  crossref =     "Tenca:2018:PIS",
  pages =        "138--144",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464771",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Quotient Selection (QS) is a key step in the classic $
                 O(n^2) $ multiple precision division algorithm. On
                 processors with fast hardware division, it is a trivial
                 problem, but on GPUs, division is quite slow. In this
                 paper we investigate the effectiveness of Brent and
                 Zimmermann's variant as well as our own novel variant
                 of Barrett's algorithm. Our new approach is shown to be
                 suitable for low radix (single precision) QS. Three
                 highly optimized implementations, two of the Brent and
                 Zimmerman variant and one based on our new approach,
                 have been developed and we show that each is many times
                 faster than using the division operation built in to
                 the compiler. In addition, our variant is on average
                 22\% faster than the other two implementations. We also
                 sketch proofs of correctness for all of the
                 implementations and our new algorithm.",
  acknowledgement = ack-nhfb,
  keywords =     "Approximation algorithms; ARITH-25; Barrett algorithm;
                 Barrett reduction; classic $O(n^2)$ multiple precision
                 division algorithm; Computer security; digital
                 arithmetic; Digital arithmetic; division operation;
                 fast hardware division; GPU; graphics processing units;
                 Hardware; low radix QS; multiple precision division;
                 Newton method; O; processors; Program processors;
                 quotient selection; Zimmermann variant",
}


bibtype: article
filename: fparith.bib
label: Ferguson:2018:DSM
author: Warren E. Ferguson and Jesse Bingham and Levent Erkok and John R. Harrison and Joe Leslie-Hurd
title: Digit Serial Methods with Applications to Division and Square Root
journal: j-IEEE-TRANS-COMPUT
volume: 67
number: 3
pages: 449--456
month: mar
monthnumber: 3
year: 2018
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2017.2759764
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Feb 15 05:53:34 MST 2018
bibtimestamp: 2018.02.15 05:53:34 MST
URL: http://ieeexplore.ieee.org/document/8060979/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Warren E. Ferguson and Jesse Bingham and Levent Erk{\"o}k and John R. Harrison and Joe Leslie-Hurd
rawtitle: Digit Serial Methods with Applications to Division and Square Root
entry:
@Article{Ferguson:2018:DSM,
  author =       "Warren E. Ferguson and Jesse Bingham and Levent
                 Erk{\"o}k and John R. Harrison and Joe Leslie-Hurd",
  title =        "Digit Serial Methods with Applications to Division and
                 Square Root",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "67",
  number =       "3",
  pages =        "449--456",
  month =        mar,
  year =         "2018",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2017.2759764",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Feb 15 05:53:34 MST 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/document/8060979/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Garland:2018:LCM
author: James Garland and David Gregg
title: Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing
journal: j-TACO
volume: 15
number: 3
pages: 31:1--31:??
month: oct
monthnumber: 10
year: 2018
DOI: https://doi.org/10.1145/3233300
ISSN: 1544-3566 (print), 1544-3973 (electronic) OR 15443566 (print), 15443973 (electronic)
ISSNL: 1544-3566 OR 15443566
bibdate: Tue Jan 8 17:19:59 MST 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/taco.bib
bibtimestamp: 2019.01.08 17:19:59 MST
fjournal: ACM Transactions on Architecture and Code Optimization (TACO)
acknowledgement: ack-nhfb
articleno: 31
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J924
rawauthor: James Garland and David Gregg
rawtitle: Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing
abstract:
Convolutional neural networks (CNNs) are one of the most successful machine-learning techniques for image, voice, and video processing. CNNs require large amounts of processing capacity and memory bandwidth. Hardware accelerators have been proposed for CNNs that typically contain large numbers of multiply-accumulate (MAC) units, the multipliers of which are large in integrated circuit (IC) gate count and power consumption. ``Weight-sharing'' accelerators have been proposed where the full range of weight values in a trained CNN are compressed and put into bins, and the bin index is used to access the weight-shared value. We reduce power and area of the CNN by implementing parallel accumulate shared MAC (PASM) in a weight-shared CNN. PASM re-architects the MAC to instead count the frequency of each weight and place it in a bin. The accumulated value is computed in a subsequent multiply phase, significantly reducing gate count and power consumption of the CNN. In this article, we implement PASM in a weight-shared CNN convolution hardware accelerator and analyze its effectiveness. Experiments show that for a clock speed 1GHz implemented on a 45nm ASIC process our approach results in fewer gates, smaller logic, and reduced power with only a slight increase in latency. We also show that the same weight-shared-with-PASM CNN accelerator can be implemented in resource-constrained FPGAs, where the FPGA has limited numbers of digital signal processor (DSP) units to accelerate the MAC operations.

rawabstract:
Convolutional neural networks (CNNs) are one of the most successful machine-learning techniques for image, voice, and video processing. CNNs require large amounts of processing capacity and memory bandwidth. Hardware accelerators have been proposed for CNNs that typically contain large numbers of multiply-accumulate (MAC) units, the multipliers of which are large in integrated circuit (IC) gate count and power consumption. ``Weight-sharing'' accelerators have been proposed where the full range of weight values in a trained CNN are compressed and put into bins, and the bin index is used to access the weight-shared value. We reduce power and area of the CNN by implementing parallel accumulate shared MAC (PASM) in a weight-shared CNN. PASM re-architects the MAC to instead count the frequency of each weight and place it in a bin. The accumulated value is computed in a subsequent multiply phase, significantly reducing gate count and power consumption of the CNN. In this article, we implement PASM in a weight-shared CNN convolution hardware accelerator and analyze its effectiveness. Experiments show that for a clock speed 1GHz implemented on a 45nm ASIC process our approach results in fewer gates, smaller logic, and reduced power with only a slight increase in latency. We also show that the same weight-shared-with-PASM CNN accelerator can be implemented in resource-constrained FPGAs, where the FPGA has limited numbers of digital signal processor (DSP) units to accelerate the MAC operations.

entry:
@Article{Garland:2018:LCM,
  author =       "James Garland and David Gregg",
  title =        "Low Complexity Multiply-Accumulate Units for
                 Convolutional Neural Networks with Weight-Sharing",
  journal =      j-TACO,
  volume =       "15",
  number =       "3",
  pages =        "31:1--31:??",
  month =        oct,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3233300",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Tue Jan 8 17:19:59 MST 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  abstract =     "Convolutional neural networks (CNNs) are one of the
                 most successful machine-learning techniques for image,
                 voice, and video processing. CNNs require large amounts
                 of processing capacity and memory bandwidth. Hardware
                 accelerators have been proposed for CNNs that typically
                 contain large numbers of multiply-accumulate (MAC)
                 units, the multipliers of which are large in integrated
                 circuit (IC) gate count and power consumption.
                 ``Weight-sharing'' accelerators have been proposed
                 where the full range of weight values in a trained CNN
                 are compressed and put into bins, and the bin index is
                 used to access the weight-shared value. We reduce power
                 and area of the CNN by implementing parallel accumulate
                 shared MAC (PASM) in a weight-shared CNN. PASM
                 re-architects the MAC to instead count the frequency of
                 each weight and place it in a bin. The accumulated
                 value is computed in a subsequent multiply phase,
                 significantly reducing gate count and power consumption
                 of the CNN. In this article, we implement PASM in a
                 weight-shared CNN convolution hardware accelerator and
                 analyze its effectiveness. Experiments show that for a
                 clock speed 1GHz implemented on a 45nm ASIC process our
                 approach results in fewer gates, smaller logic, and
                 reduced power with only a slight increase in latency.
                 We also show that the same weight-shared-with-PASM CNN
                 accelerator can be implemented in resource-constrained
                 FPGAs, where the FPGA has limited numbers of digital
                 signal processor (DSP) units to accelerate the MAC
                 operations.",
  acknowledgement = ack-nhfb,
  articleno =    "31",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J924",
}


bibtype: inproceedings
filename: fparith.bib
label: Glaser:2018:MMU
booktitle: 2018 IEEE International Symposium on Circuits and Systems (ISCAS)
title: An 826 MOPS, 210uW / MHz Unum ALU in 65nm
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2018
DOI: https://doi.org/10.1109/ISCAS.2018.8351546
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2018 IEEE International Symposium on Circuits and Systems (ISCAS)}
rawtitle: An {826 MOPS}, {210uW\slash MHz} Unum {ALU} in 65nm
author:
Florian Glaser and Stefan Mach and Abbas Rahimi and Frank K. Gurkaynak and Qiuting Huang and Luca Benini

rawauthor:
Florian Glaser and Stefan Mach and Abbas Rahimi and Frank K. G{\"u}rkaynak and Qiuting Huang and Luca Benini

entry:
@InProceedings{Glaser:2018:MMU,
  author =       "Florian Glaser and Stefan Mach and Abbas Rahimi and
                 Frank K. G{\"u}rkaynak and Qiuting Huang and Luca
                 Benini",
  booktitle =    "{2018 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "An {826 MOPS}, {210uW\slash MHz} Unum {ALU} in 65nm",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ISCAS.2018.8351546",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Graillat:2018:NVC
author: Stef Graillat and Fabienne Jezequel and Romain Picot
title: Numerical validation of compensated algorithms with stochastic arithmetic
journal: j-APPL-MATH-COMP
volume: 329
pages: 339--363
day: 15
month: jul
monthnumber: 7
year: 2018
CODEN: AMHCBQ
DOI: https://doi.org/10.1016/j.amc.2018.02.004
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Sat Mar 17 16:59:00 MDT 2018
bibtimestamp: 2018.03.17 16:59:00 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0096300318300985
fjournal: Applied Mathematics and Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: Stef Graillat and Fabienne J{\'e}z{\'e}quel and Romain Picot
rawtitle: Numerical validation of compensated algorithms with stochastic arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/applmathcomput2015.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
accurate floating-point dot product; accurate floating-point summation; CADNA; compensated algorithms; discrete stochastic arithmetic; error-free transformations; floating-point arithmetic; numerical validation; rounding errors

entry:
@Article{Graillat:2018:NVC,
  author =       "Stef Graillat and Fabienne J{\'e}z{\'e}quel and Romain
                 Picot",
  title =        "Numerical validation of compensated algorithms with
                 stochastic arithmetic",
  journal =      j-APPL-MATH-COMP,
  volume =       "329",
  number =       "??",
  pages =        "339--363",
  day =          "15",
  month =        jul,
  year =         "2018",
  CODEN =        "AMHCBQ",
  DOI =          "https://doi.org/10.1016/j.amc.2018.02.004",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Sat Mar 17 16:59:00 MDT 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/applmathcomput2015.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0096300318300985",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
  keywords =     "accurate floating-point dot product; accurate
                 floating-point summation; CADNA; compensated
                 algorithms; discrete stochastic arithmetic; error-free
                 transformations; floating-point arithmetic; numerical
                 validation; rounding errors",
}


bibtype: incollection
filename: fparith.bib
label: Haidar:2018:DFE
booktitle: Computational science---ICCS 2018. Part I
volume: 10860
publisher: Springer
address: Cham, Switzerland
pages: 586--600
year: 2018
MRclass: 65Fxx (65Y10)
MRnumber: 3815810
bibdate: Tue Jan 8 09:18:00 2019
bibtimestamp: 2019.01.08 09:18:00 ???
series: ser-LNCS
acknowledgement: ack-nhfb
rawbooktitle: Computational science---{ICCS 2018}. {Part I}
ORCID: Dongarra, Jack/0000-0003-3247-1782
author:
Azzam Haidar and Ahmad Abdelfattah and Mawussi Zounon and Panruo Wu and Srikara Pranesh and Stanimire Tomov and Jack Dongarra

title:
The design of fast and energy-efficient linear solvers: on the potential of half-precision arithmetic and iterative refinement techniques

bibsource:
https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawauthor:
Azzam Haidar and Ahmad Abdelfattah and Mawussi Zounon and Panruo Wu and Srikara Pranesh and Stanimire Tomov and Jack Dongarra

rawtitle:
The design of fast and energy-efficient linear solvers: on the potential of half-precision arithmetic and iterative refinement techniques

entry:
@InCollection{Haidar:2018:DFE,
  author =       "Azzam Haidar and Ahmad Abdelfattah and Mawussi Zounon
                 and Panruo Wu and Srikara Pranesh and Stanimire Tomov
                 and Jack Dongarra",
  booktitle =    "Computational science---{ICCS 2018}. {Part I}",
  title =        "The design of fast and energy-efficient linear
                 solvers: on the potential of half-precision arithmetic
                 and iterative refinement techniques",
  volume =       "10860",
  publisher =    "Springer",
  address =      "Cham, Switzerland",
  pages =        "586--600",
  year =         "2018",
  MRclass =      "65Fxx (65Y10)",
  MRnumber =     "3815810",
  bibdate =      "Tue Jan 8 09:18:00 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       ser-LNCS,
  acknowledgement = ack-nhfb,
  ORCID-numbers = "Dongarra, Jack/0000-0003-3247-1782",
}


bibtype: inproceedings
filename: fparith.bib
label: Haidar:2018:HGT
author: Azzam Haidar and Stanimire Tomov and Jack Dongarra and Nicholas J. Higham
editor: IEEE
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 47:1--47:11
year: 2018
ISBN: 1-5386-8384-9 OR 1538683849
ISBN13: 978-1-5386-8384-2 OR 9781538683842
bibdate: Sat Jan 19 18:51:19 2019
bibtimestamp: 2019.01.19 18:51:19 ???
URL: https://dl.acm.org/citation.cfm?id=3291656.3291719
acknowledgement: ack-nhfb
rawauthor: Azzam Haidar and Stanimire Tomov and Jack Dongarra and Nicholas J. Higham
raweditor: {IEEE}
booktitle:
SC '18 Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis, Dallas, Texas, November 11--16, 2018

title:
Harnessing GPU tensor cores for fast FP16 arithmetic to speed up mixed-precision iterative refinement solvers

bibsource:
https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib; https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
Low-precision floating-point arithmetic is a powerful tool for accelerating scientific computing applications, especially those in artificial intelligence. Here, we present an investigation showing that other high-performance computing (HPC) applications can also harness this power. Specifically, we use the general HPC problem, Ax = b, where A is a large dense matrix, and a double precision (FP64) solution is needed for accuracy. Our approach is based on mixed-precision (FP16 $ to $ FP64) iterative refinement, and we generalize and extend prior advances into a framework, for which we develop architecture-specific algorithms and highly tuned implementations. These new methods show how using half-precision Tensor Cores (FP16-TC) for the arithmetic can provide up to 4X speedup. This is due to the performance boost that the FP16-TC provide as well as to the improved accuracy over the classical FP16 arithmetic that is obtained because the GEMM accumulation occurs in FP32 arithmetic.

rawabstract:
Low-precision floating-point arithmetic is a powerful tool for accelerating scientific computing applications, especially those in artificial intelligence. Here, we present an investigation showing that other high-performance computing (HPC) applications can also harness this power. Specifically, we use the general HPC problem, Ax = b, where A is a large dense matrix, and a double precision (FP64) solution is needed for accuracy. Our approach is based on mixed-precision (FP16 $ \to $ FP64) iterative refinement, and we generalize and extend prior advances into a framework, for which we develop architecture-specific algorithms and highly tuned implementations. These new methods show how using half-precision Tensor Cores (FP16-TC) for the arithmetic can provide up to 4X speedup. This is due to the performance boost that the FP16-TC provide as well as to the improved accuracy over the classical FP16 arithmetic that is obtained because the GEMM accumulation occurs in FP32 arithmetic.

rawbooktitle:
{SC '18 Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis, Dallas, Texas, November 11--16, 2018}

rawtitle:
Harnessing {GPU} tensor cores for fast {FP16} arithmetic to speed up mixed-precision iterative refinement solvers

entry:
@InProceedings{Haidar:2018:HGT,
  author =       "Azzam Haidar and Stanimire Tomov and Jack Dongarra and
                 Nicholas J. Higham",
  editor =       "{IEEE}",
  booktitle =    "{SC '18 Proceedings of the International Conference
                 for High Performance Computing, Networking, Storage,
                 and Analysis, Dallas, Texas, November 11--16, 2018}",
  title =        "Harnessing {GPU} tensor cores for fast {FP16}
                 arithmetic to speed up mixed-precision iterative
                 refinement solvers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "47:1--47:11",
  year =         "2018",
  ISBN =         "1-5386-8384-9",
  ISBN-13 =      "978-1-5386-8384-2",
  LCCN =         "????",
  bibdate =      "Sat Jan 19 18:51:19 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib;
                 https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3291656.3291719",
  abstract =     "Low-precision floating-point arithmetic is a powerful
                 tool for accelerating scientific computing
                 applications, especially those in artificial
                 intelligence. Here, we present an investigation showing
                 that other high-performance computing (HPC)
                 applications can also harness this power. Specifically,
                 we use the general HPC problem, Ax = b, where A is a
                 large dense matrix, and a double precision (FP64)
                 solution is needed for accuracy. Our approach is based
                 on mixed-precision (FP16 $ \to $ FP64) iterative
                 refinement, and we generalize and extend prior advances
                 into a framework, for which we develop
                 architecture-specific algorithms and highly tuned
                 implementations. These new methods show how using
                 half-precision Tensor Cores (FP16-TC) for the
                 arithmetic can provide up to 4X speedup. This is due to
                 the performance boost that the FP16-TC provide as well
                 as to the improved accuracy over the classical FP16
                 arithmetic that is obtained because the GEMM
                 accumulation occurs in FP32 arithmetic.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Hanson:2018:RAM
author: Richard J. Hanson and Tim Hopkins
journal: j-TOMS
volume: 44
number: 3
pages: 24:1--24:23
month: apr
monthnumber: 4
year: 2018
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3134441
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Mon Jan 22 17:49:32 MST 2018
bibtimestamp: 2018.01.22 17:49:32 MST
URL: https://dl.acm.org/citation.cfm?id=3134441
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 24
journalURL: https://dl.acm.org/loi/toms
rawauthor: Richard J. Hanson and Tim Hopkins
title:
Remark on Algorithm 539: A Modern Fortran Reference Implementation for Carefully Computing the Euclidean Norm

bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fortran3.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

abstract:
We propose a set of new Fortran reference implementations, based on an algorithm proposed by Kahan, for the Level 1 BLAS routines *NRM2 that compute the Euclidean norm of a real or complex input vector. The principal advantage of these routines over the current offerings is that, rather than losing accuracy as the length of the vector increases, they generate results that are accurate to almost machine precision for vectors of length $ N < N_rm max $ where $ N_rm max $ depends upon the precision of the floating point arithmetic being used. In addition, we make use of intrinsic modules, introduced in the latest Fortran standards, to detect occurrences of non-finite numbers in the input data and return suitable values as well as setting IEEE floating point status flags as appropriate. A set of C interface routines is also provided to allow simple, portable access to the new routines. To improve execution speed, we advocate a hybrid algorithm; a simple loop is used first and, only if IEEE floating point exception flags signal, do we fall back on Kahan's algorithm. Since most input vectors are ``easy,'' i.e., they do not require the sophistication of Kahan's algorithm, the simple loop improves performance while the use of compensated summation ensures high accuracy. We also report on a comprehensive suite of test problems that has been developed to test both our new implementation and existing codes for both accuracy and the appropriate settings of the IEEE arithmetic status flags.

rawabstract:
We propose a set of new Fortran reference implementations, based on an algorithm proposed by Kahan, for the Level 1 BLAS routines *NRM2 that compute the Euclidean norm of a real or complex input vector. The principal advantage of these routines over the current offerings is that, rather than losing accuracy as the length of the vector increases, they generate results that are accurate to almost machine precision for vectors of length $ N < N_{\rm max} $ where $ N_{\rm max} $ depends upon the precision of the floating point arithmetic being used. In addition, we make use of intrinsic modules, introduced in the latest Fortran standards, to detect occurrences of non-finite numbers in the input data and return suitable values as well as setting IEEE floating point status flags as appropriate. A set of C interface routines is also provided to allow simple, portable access to the new routines. To improve execution speed, we advocate a hybrid algorithm; a simple loop is used first and, only if IEEE floating point exception flags signal, do we fall back on Kahan's algorithm. Since most input vectors are ``easy,'' i.e., they do not require the sophistication of Kahan's algorithm, the simple loop improves performance while the use of compensated summation ensures high accuracy. We also report on a comprehensive suite of test problems that has been developed to test both our new implementation and existing codes for both accuracy and the appropriate settings of the IEEE arithmetic status flags.

rawtitle:
Remark on {Algorithm 539: A Modern Fortran Reference Implementation for Carefully Computing the Euclidean Norm}

entry:
@Article{Hanson:2018:RAM,
  author =       "Richard J. Hanson and Tim Hopkins",
  title =        "Remark on {Algorithm 539: A Modern Fortran Reference
                 Implementation for Carefully Computing the Euclidean
                 Norm}",
  journal =      j-TOMS,
  volume =       "44",
  number =       "3",
  pages =        "24:1--24:23",
  month =        apr,
  year =         "2018",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3134441",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Mon Jan 22 17:49:32 MST 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fortran3.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3134441",
  abstract =     "We propose a set of new Fortran reference
                 implementations, based on an algorithm proposed by
                 Kahan, for the Level 1 BLAS routines *NRM2 that compute
                 the Euclidean norm of a real or complex input vector.
                 The principal advantage of these routines over the
                 current offerings is that, rather than losing accuracy
                 as the length of the vector increases, they generate
                 results that are accurate to almost machine precision
                 for vectors of length $ N < N_{\rm max} $ where $
                 N_{\rm max} $ depends upon the precision of the
                 floating point arithmetic being used. In addition, we
                 make use of intrinsic modules, introduced in the latest
                 Fortran standards, to detect occurrences of non-finite
                 numbers in the input data and return suitable values as
                 well as setting IEEE floating point status flags as
                 appropriate. A set of C interface routines is also
                 provided to allow simple, portable access to the new
                 routines. To improve execution speed, we advocate a
                 hybrid algorithm; a simple loop is used first and, only
                 if IEEE floating point exception flags signal, do we
                 fall back on Kahan's algorithm. Since most input
                 vectors are ``easy,'' i.e., they do not require the
                 sophistication of Kahan's algorithm, the simple loop
                 improves performance while the use of compensated
                 summation ensures high accuracy. We also report on a
                 comprehensive suite of test problems that has been
                 developed to test both our new implementation and
                 existing codes for both accuracy and the appropriate
                 settings of the IEEE arithmetic status flags.",
  acknowledgement = ack-nhfb,
  articleno =    "24",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  xxnote =       "See \cite{Lawson:1979:ABL}.",
}


bibtype: article
filename: fparith.bib
label: Hasanikhah:2018:EIS
author: Narjes Hasanikhah and Siavash Amin-Nejad and Ghafar Darvish and M. R. Moniri
journal: j-J-SUPERCOMPUTING
volume: 74
number: 7
pages: 3193--3210
month: jul
monthnumber: 7
year: 2018
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-018-2369-7
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Thu Oct 10 15:31:13 MDT 2019
bibtimestamp: 2019.10.10 15:31:13 MDT
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11227
rawauthor: Narjes Hasanikhah and Siavash Amin-Nejad and Ghafar Darvish and M. R. Moniri
title:
Efficient implementation of space-time adaptive processing for adaptive weights calculation based on floating point FPGAs

bibsource:
http://link.springer.com/journal/11227/74/7; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jsuper.bib

rawtitle:
Efficient implementation of space-time adaptive processing for adaptive weights calculation based on floating point {FPGAs}

entry:
@Article{Hasanikhah:2018:EIS,
  author =       "Narjes Hasanikhah and Siavash Amin-Nejad and Ghafar
                 Darvish and M. R. Moniri",
  title =        "Efficient implementation of space-time adaptive
                 processing for adaptive weights calculation based on
                 floating point {FPGAs}",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "74",
  number =       "7",
  pages =        "3193--3210",
  month =        jul,
  year =         "2018",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-018-2369-7",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Thu Oct 10 15:31:13 MDT 2019",
  bibsource =    "http://link.springer.com/journal/11227/74/7;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: misc
filename: fparith.bib
label: Higham:2018:HPA
author: Nicholas J. Higham
title: Half Precision Arithmetic: fp16 Versus bfloat16
pages: 3193--3210
day: 3
month: dec
monthnumber: 12
year: 2018
bibdate: Sat Jan 19 18:43:15 2019
bibtimestamp: 2019.01.19 18:43:15 ???
URL: https://nickhigham.wordpress.com/2018/12/03/half-precision-arithmetic-fp16-versus-bfloat16/
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Nicholas J. Higham
rawtitle: Half Precision Arithmetic: fp16 Versus bfloat16
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
The 2008 revision of the IEEE Standard for Floating-Point Arithmetic introduced a half precision 16-bit floating point format, known as fp16, as a storage format. Various manufacturers have adopted fp16 for computation, using the obvious extension of the rules for the fp32 (single precision) and fp64 (double precision) formats. For example, fp16 is supported by the NVIDIA P100 and V100 GPUs and the AMD Radeon Instinct MI25 GPU, as well as the A64FX Arm processor that will power the Fujitsu Post-K exascale computer.

rawabstract:
The 2008 revision of the IEEE Standard for Floating-Point Arithmetic introduced a half precision 16-bit floating point format, known as fp16, as a storage format. Various manufacturers have adopted fp16 for computation, using the obvious extension of the rules for the fp32 (single precision) and fp64 (double precision) formats. For example, fp16 is supported by the NVIDIA P100 and V100 GPUs and the AMD Radeon Instinct MI25 GPU, as well as the A64FX Arm processor that will power the Fujitsu Post-K exascale computer.

entry:
@Misc{Higham:2018:HPA,
  author =       "Nicholas J. Higham",
  title =        "Half Precision Arithmetic: fp16 Versus bfloat16",
  howpublished = "Web site.",
  day =          "3",
  month =        dec,
  year =         "2018",
  bibdate =      "Sat Jan 19 18:43:15 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://nickhigham.wordpress.com/2018/12/03/half-precision-arithmetic-fp16-versus-bfloat16/",
  abstract =     "The 2008 revision of the IEEE Standard for
                 Floating-Point Arithmetic introduced a half precision
                 16-bit floating point format, known as fp16, as a
                 storage format. Various manufacturers have adopted fp16
                 for computation, using the obvious extension of the
                 rules for the fp32 (single precision) and fp64 (double
                 precision) formats. For example, fp16 is supported by
                 the NVIDIA P100 and V100 GPUs and the AMD Radeon
                 Instinct MI25 GPU, as well as the A64FX Arm processor
                 that will power the Fujitsu Post-K exascale computer.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Higham:2018:UN
author: Nicholas J. Higham
title: The Unwinding Number
journal: j-SIAM-NEWS
volume: 51
number: 8
pages: ??--??
month: oct
monthnumber: 10
year: 2018
ISSN: 0036-1437 OR 00361437
ISSNL: 0036-1437 OR 00361437
bibdate: Sat Oct 06 08:46:15 2018
bibtimestamp: 2018.10.06 08:46:15 ???
URL: https://sinews.siam.org/Details-Page/the-unwinding-number
fjournal: SIAM News
acknowledgement: ack-nhfb
journalURL: https://sinews.siam.org/
rawauthor: Nicholas J. Higham
rawtitle: The Unwinding Number
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
While Fortran 66 had a complex data type, this was not true of most other early programming languages, such as Algol 60. As a result, programmers had to write their own procedures to implement complex arithmetic and transcendental functions in terms of separately stored real and imaginary parts. They quickly realized that this is not a trivial task; in the early 1960s, it took five published attempts over three years to obtain a correct implementation of the complex logarithm in Algol 60.

rawabstract:
While Fortran 66 had a complex data type, this was not true of most other early programming languages, such as Algol 60. As a result, programmers had to write their own procedures to implement complex arithmetic and transcendental functions in terms of separately stored real and imaginary parts. They quickly realized that this is not a trivial task; in the early 1960s, it took five published attempts over three years to obtain a correct implementation of the complex logarithm in Algol 60.

entry:
@Article{Higham:2018:UN,
  author =       "Nicholas J. Higham",
  title =        "The Unwinding Number",
  journal =      j-SIAM-NEWS,
  volume =       "51",
  number =       "8",
  pages =        "??--??",
  month =        oct,
  year =         "2018",
  ISSN =         "0036-1437",
  ISSN-L =       "0036-1437",
  bibdate =      "Sat Oct 06 08:46:15 2018",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://sinews.siam.org/Details-Page/the-unwinding-number",
  abstract =     "While Fortran 66 had a complex data type, this was not
                 true of most other early programming languages, such as
                 Algol 60. As a result, programmers had to write their
                 own procedures to implement complex arithmetic and
                 transcendental functions in terms of separately stored
                 real and imaginary parts. They quickly realized that
                 this is not a trivial task; in the early 1960s, it took
                 five published attempts over three years to obtain a
                 correct implementation of the complex logarithm in
                 Algol 60.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM News",
  journal-URL =  "https://sinews.siam.org/",
}


bibtype: article
filename: fparith.bib
label: Hines:2018:MPS
author: Jonathan Hines
title: Mixed Precision: A Strategy for New Science Opportunities
journal: j-COMPUT-SCI-ENG
volume: 20
number: 6
pages: 67--71
month: nov
monthnumber: 11
year: 2018
CODEN: CSENFA
DOI: https://doi.org/10.1109/MCSE.2018.2874161
ISSN: 1521-9615 (print), 1558-366X (electronic) OR 15219615 (print), 1558366X (electronic)
ISSNL: 1521-9615 OR 15219615
bibdate: Wed Jan 30 17:58:50 MST 2019
bibtimestamp: 2019.01.30 17:58:50 MST
URL: https://www.computer.org/csdl/mags/cs/2018/06/08625902-abs.html
fjournal: Computing in Science and Engineering
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5992
rawauthor: Jonathan Hines
rawtitle: Mixed Precision: A Strategy for New Science Opportunities
bibsource:
http://csdl.computer.org/comp/mags/cs/2018/06/c6toc.htm; https://www.math.utah.edu/pub/tex/bib/computscieng.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Hines:2018:MPS,
  author =       "Jonathan Hines",
  title =        "Mixed Precision: A Strategy for New Science
                 Opportunities",
  journal =      j-COMPUT-SCI-ENG,
  volume =       "20",
  number =       "6",
  pages =        "67--71",
  month =        nov # "\slash " # dec,
  year =         "2018",
  CODEN =        "CSENFA",
  DOI =          "https://doi.org/10.1109/MCSE.2018.2874161",
  ISSN =         "1521-9615 (print), 1558-366X (electronic)",
  ISSN-L =       "1521-9615",
  bibdate =      "Wed Jan 30 17:58:50 MST 2019",
  bibsource =    "http://csdl.computer.org/comp/mags/cs/2018/06/c6toc.htm;
                 https://www.math.utah.edu/pub/tex/bib/computscieng.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.computer.org/csdl/mags/cs/2018/06/08625902-abs.html",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing in Science and Engineering",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5992",
}


bibtype: article
filename: fparith.bib
label: Hou:2018:EAD
author: Junjie Hou and Yongxin Zhu and Sen Du and Shijin Song
journal: Journal of Signal Processing Systems
volume: 91
number: 10
publisher: pub-SV
address: pub-SV:adr
pages: 1137--1148
month: nov
monthnumber: 11
year: 2018
DOI: https://doi.org/10.1007/s11265-018-1420-5
ISSN: 1939-8018 (print), 1939-8115 (electronic) OR 19398018 (print), 19398115 (electronic)
ISSNL: 1939-8115 OR 19398115
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Junjie Hou and Yongxin Zhu and Sen Du and Shijin Song
title:
Enhancing Accuracy and Dynamic Range of Scientific Data Analytics by Implementing Posit Arithmetic on FPGA

rawtitle:
Enhancing Accuracy and Dynamic Range of Scientific Data Analytics by Implementing Posit Arithmetic on {FPGA}

entry:
@Article{Hou:2018:EAD,
  author =       "Junjie Hou and Yongxin Zhu and Sen Du and Shijin
                 Song",
  title =        "Enhancing Accuracy and Dynamic Range of Scientific
                 Data Analytics by Implementing Posit Arithmetic on
                 {FPGA}",
  journal =      "Journal of Signal Processing Systems",
  volume =       "91",
  number =       "10",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "1137--1148",
  month =        nov,
  year =         "2018",
  DOI =          "https://doi.org/10.1007/s11265-018-1420-5",
  ISSN =         "1939-8018 (print), 1939-8115 (electronic)",
  ISSN-L =       "1939-8115",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Hrycak:2018:ECP
author: Tomasz Hrycak and Sebastian Schmutzhard
title: Evaluation of Chebyshev polynomials by a three-term recurrence in floating-point arithmetic
journal: j-BIT-NUM-MATH
volume: 58
number: 2
pages: 317--330
month: jun
monthnumber: 6
year: 2018
CODEN: BITTEL, NBITAB
DOI: https://doi.org/10.1007/s10543-017-0683-8
ISSN: 0006-3835 (print), 1572-9125 (electronic) OR 00063835 (print), 15729125 (electronic)
ISSNL: 0006-3835 OR 00063835
bibdate: Wed Sep 26 07:36:57 MDT 2018
bibtimestamp: 2018.09.26 07:36:57 MDT
URL: https://link.springer.com/article/10.1007/s10543-017-0683-8
fjournal: BIT Numerical Mathematics
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10543
rawauthor: Tomasz Hrycak and Sebastian Schmutzhard
rawtitle: Evaluation of {Chebyshev} polynomials by a three-term recurrence in floating-point arithmetic
bibsource:
http://link.springer.com/journal/10543/58/2; https://www.math.utah.edu/pub/tex/bib/bit.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Hrycak:2018:ECP,
  author =       "Tomasz Hrycak and Sebastian Schmutzhard",
  title =        "Evaluation of {Chebyshev} polynomials by a three-term
                 recurrence in floating-point arithmetic",
  journal =      j-BIT-NUM-MATH,
  volume =       "58",
  number =       "2",
  pages =        "317--330",
  month =        jun,
  year =         "2018",
  CODEN =        "BITTEL, NBITAB",
  DOI =          "https://doi.org/10.1007/s10543-017-0683-8",
  ISSN =         "0006-3835 (print), 1572-9125 (electronic)",
  ISSN-L =       "0006-3835",
  bibdate =      "Wed Sep 26 07:36:57 MDT 2018",
  bibsource =    "http://link.springer.com/journal/10543/58/2;
                 https://www.math.utah.edu/pub/tex/bib/bit.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://link.springer.com/article/10.1007/s10543-017-0683-8",
  acknowledgement = ack-nhfb,
  fjournal =     "BIT Numerical Mathematics",
  journal-URL =  "http://link.springer.com/journal/10543",
}


bibtype: article
filename: fparith.bib
label: Hutter:2018:FMP
author: Michael Hutter and Erich Wenger
title: Fast Multi-precision Multiplication for Public-Key Cryptography on Embedded Microprocessors
journal: j-J-CRYPTOLOGY
volume: 31
number: 4
pages: 1164--1182
month: oct
monthnumber: 10
year: 2018
CODEN: JOCREQ
DOI: https://doi.org/10.1007/s00145-018-9298-8
ISSN: 0933-2790 (print), 1432-1378 (electronic) OR 09332790 (print), 14321378 (electronic)
ISSNL: 0933-2790 OR 09332790
bibdate: Wed Sep 26 09:58:08 MDT 2018
bibtimestamp: 2018.09.26 09:58:08 MDT
URL: https://link.springer.com/article/10.1007/s00145-018-9298-8
fjournal: Journal of Cryptology
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/145
rawauthor: Michael Hutter and Erich Wenger
rawtitle: Fast Multi-precision Multiplication for Public-Key Cryptography on Embedded Microprocessors
bibsource:
http://link.springer.com/journal/145/31/4; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcryptology.bib

entry:
@Article{Hutter:2018:FMP,
  author =       "Michael Hutter and Erich Wenger",
  title =        "Fast Multi-precision Multiplication for Public-Key
                 Cryptography on Embedded Microprocessors",
  journal =      j-J-CRYPTOLOGY,
  volume =       "31",
  number =       "4",
  pages =        "1164--1182",
  month =        oct,
  year =         "2018",
  CODEN =        "JOCREQ",
  DOI =          "https://doi.org/10.1007/s00145-018-9298-8",
  ISSN =         "0933-2790 (print), 1432-1378 (electronic)",
  ISSN-L =       "0933-2790",
  bibdate =      "Wed Sep 26 09:58:08 MDT 2018",
  bibsource =    "http://link.springer.com/journal/145/31/4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptology.bib",
  URL =          "https://link.springer.com/article/10.1007/s00145-018-9298-8",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptology",
  journal-URL =  "http://link.springer.com/journal/145",
}


bibtype: techreport
filename: fparith.bib
label: Intel:2018:BHN
author: Intel Corporation
title: BFLOAT16 --- Hardware Numerics Definition
type: White paper
number: 338302-001US
institution: pub-INTEL
address: pub-INTEL:adr
pages: 7
month: nov
monthnumber: 11
year: 2018
bibdate: Sat Jan 19 18:48:10 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.01.19 18:48:10 ???
URL: https://software.intel.com/en-us/download/bfloat16-hardware-numerics-definition
acknowledgement: ack-nhfb
rawauthor: {Intel Corporation}
rawtitle: {BFLOAT16} --- Hardware Numerics Definition
remark:
The BFLOAT16 (BF16) format has a 1-bit sign, 8-bit exponent, and 7-bit stored significand, corresponding to the top 16 bits of IEEE 754 Binary32. However, Intel's implementation does not provide subnormal numbers, or floating-point exceptions, and it only supports the IEEE 754 round-to-nearest ties-to-even rounding mode. Subnormal inputs are reduced to zero.

entry:
@TechReport{Intel:2018:BHN,
  author =       "{Intel Corporation}",
  title =        "{BFLOAT16} --- Hardware Numerics Definition",
  type =         "White paper",
  number =       "338302-001US",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "7",
  month =        nov,
  year =         "2018",
  bibdate =      "Sat Jan 19 18:48:10 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://software.intel.com/en-us/download/bfloat16-hardware-numerics-definition",
  acknowledgement = ack-nhfb,
  remark =       "The BFLOAT16 (BF16) format has a 1-bit sign, 8-bit
                 exponent, and 7-bit stored significand, corresponding
                 to the top 16 bits of IEEE 754 Binary32. However,
                 Intel's implementation does not provide subnormal
                 numbers, or floating-point exceptions, and it only
                 supports the IEEE 754 round-to-nearest ties-to-even
                 rounding mode. Subnormal inputs are reduced to zero.",
}


bibtype: inproceedings
filename: fparith.bib
label: Jaiswal:2018:AGT
author: Manish Kumar Jaiswal and Hayden K.-H So
editor: IEEE
booktitle: 2018 IEEE International Symposium on Circuits and Systems (ISCAS)
title: Architecture Generator for Type-3 Unum Posit Adder / Subtractor
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2018
DOI: https://doi.org/10.1109/ISCAS.2018.8351142
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawauthor: Manish Kumar Jaiswal and Hayden K.-H So
rawbooktitle: {2018 IEEE International Symposium on Circuits and Systems (ISCAS)}
raweditor: {IEEE}
rawtitle: Architecture Generator for {Type-3} Unum Posit Adder\slash Subtractor
entry:
@InProceedings{Jaiswal:2018:AGT,
  author =       "Manish Kumar Jaiswal and Hayden K.-H So",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Architecture Generator for {Type-3} Unum Posit
                 Adder\slash Subtractor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ISCAS.2018.8351142",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Jaiswal:2018:UNP
author: Manish Kumar Jaiswal and Hayden K.-H So
editor: IEEE
booktitle: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
title: Universal number posit arithmetic generator on FPGA
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1159--1162
year: 2018
DOI: https://doi.org/10.23919/DATE.2018.8342187
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Manish Kumar Jaiswal and Hayden K.-H So
rawbooktitle: {2018 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}
raweditor: {IEEE}
rawtitle: Universal number posit arithmetic generator on {FPGA}
entry:
@InProceedings{Jaiswal:2018:UNP,
  author =       "Manish Kumar Jaiswal and Hayden K.-H So",
  editor =       "{IEEE}",
  booktitle =    "{2018 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Universal number posit arithmetic generator on
                 {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1159--1162",
  year =         "2018",
  DOI =          "https://doi.org/10.23919/DATE.2018.8342187",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Jeangoudoux:2018:CRM
author: Clothilde Jeangoudoux and Christoph Lauter
title: A Correctly Rounded Mixed-Radix Fused-Multiply-Add
crossref: Tenca:2018:PIS
pages: 21--28
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464818
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Clothilde Jeangoudoux and Christoph Lauter
rawtitle: A Correctly Rounded Mixed-Radix Fused-Multiply-Add
abstract:
The IEEE 754-2008 Standard governs Floating-Point Arithmetic in all types of Computer Systems. The Standard provides for two radices, 2 and 10. It specifies conversion operations between these radices, but does not allow floating-point formats of different radices to be mixed in computational operations. In contrast, the Standard does provide for mixing formats of one radix in one operation. In order to enhance the Standard and make it closed under all basic computational operations, we propose an algorithm for a correctly rounded mixed-radix Fused-Multiply-and-Add (FMA). Our algorithm takes any combination of IEEE754 binary64 and decimal64 numbers in argument and provides a result in IEEE754 binary64 and decimal64, rounded according to any for the five IEEE754 rounding modes. Our implementation does not require any dynamic memory allocation; its runtime can be bounded statically. We compare our implementation to a basic mixed-radix FMA implementation based on the GMP Multiple Precision library.

keywords:
ARITH-25; basic computational operations; computer systems; conversion operations; correctly rounded mixed-radix Fused; decimal64 numbers; Electronic mail; floating point arithmetic; floating-point arithmetic; Floating-point arithmetic; floating-point formats; Heuristic algorithms; IEEE 754-2008 Standard; IEEE standards; IEEE754 rounding modes; Libraries; mixed-radix FMA implementation; Software; Standards; Systematics

rawabstract:
The IEEE 754-2008 Standard governs Floating-Point Arithmetic in all types of Computer Systems. The Standard provides for two radices, 2 and 10. It specifies conversion operations between these radices, but does not allow floating-point formats of different radices to be mixed in computational operations. In contrast, the Standard does provide for mixing formats of one radix in one operation. In order to enhance the Standard and make it closed under all basic computational operations, we propose an algorithm for a correctly rounded mixed-radix Fused-Multiply-and-Add (FMA). Our algorithm takes any combination of IEEE754 binary64 and decimal64 numbers in argument and provides a result in IEEE754 binary64 and decimal64, rounded according to any for the five IEEE754 rounding modes. Our implementation does not require any dynamic memory allocation; its runtime can be bounded statically. We compare our implementation to a basic mixed-radix FMA implementation based on the GMP Multiple Precision library.

entry:
@InProceedings{Jeangoudoux:2018:CRM,
  author =       "Clothilde Jeangoudoux and Christoph Lauter",
  title =        "A Correctly Rounded Mixed-Radix Fused-Multiply-Add",
  crossref =     "Tenca:2018:PIS",
  pages =        "21--28",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464818",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The IEEE 754-2008 Standard governs Floating-Point
                 Arithmetic in all types of Computer Systems. The
                 Standard provides for two radices, 2 and 10. It
                 specifies conversion operations between these radices,
                 but does not allow floating-point formats of different
                 radices to be mixed in computational operations. In
                 contrast, the Standard does provide for mixing formats
                 of one radix in one operation. In order to enhance the
                 Standard and make it closed under all basic
                 computational operations, we propose an algorithm for a
                 correctly rounded mixed-radix Fused-Multiply-and-Add
                 (FMA). Our algorithm takes any combination of IEEE754
                 binary64 and decimal64 numbers in argument and provides
                 a result in IEEE754 binary64 and decimal64, rounded
                 according to any for the five IEEE754 rounding modes.
                 Our implementation does not require any dynamic memory
                 allocation; its runtime can be bounded statically. We
                 compare our implementation to a basic mixed-radix FMA
                 implementation based on the GMP Multiple Precision
                 library.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-25; basic computational operations; computer
                 systems; conversion operations; correctly rounded
                 mixed-radix Fused; decimal64 numbers; Electronic mail;
                 floating point arithmetic; floating-point arithmetic;
                 Floating-point arithmetic; floating-point formats;
                 Heuristic algorithms; IEEE 754-2008 Standard; IEEE
                 standards; IEEE754 rounding modes; Libraries;
                 mixed-radix FMA implementation; Software; Standards;
                 Systematics",
}


bibtype: article
filename: fparith.bib
label: Jeannerod:2018:REF
author: Claude-Pierre Jeannerod and Siegfried M. Rump
title: On relative errors of floating-point operations: Optimal bounds and applications
journal: j-MATH-COMPUT
volume: 87
number: 310
pages: 803--819
year: 2018
CODEN: MCMPAF
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Sat Jan 13 15:49:09 MST 2018
bibtimestamp: 2018.01.13 15:49:09 MST
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Claude-Pierre Jeannerod and Siegfried M. Rump
rawtitle: On relative errors of floating-point operations: {Optimal} bounds and applications
bibsource:
http://www.ams.org/mcom/2018-87-310; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib

URL:
http://www.ams.org/journals/mcom/2018-87-310/S0025-5718-2017-03234-8; http://www.ams.org/journals/mcom/2018-87-310/S0025-5718-2017-03234-8/S0025-5718-2017-03234-8.pdf; https://www.ams.org/mathscinet/search/authors.html?authorName=Rump%2C%20Siegfried%20M.; https://www.ams.org/mathscinet/search/authors.html?mrauthid=644190

entry:
@Article{Jeannerod:2018:REF,
  author =       "Claude-Pierre Jeannerod and Siegfried M. Rump",
  title =        "On relative errors of floating-point operations:
                 {Optimal} bounds and applications",
  journal =      j-MATH-COMPUT,
  volume =       "87",
  number =       "310",
  pages =        "803--819",
  month =        "",
  year =         "2018",
  CODEN =        "MCMPAF",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Sat Jan 13 15:49:09 MST 2018",
  bibsource =    "http://www.ams.org/mcom/2018-87-310;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib",
  URL =          "http://www.ams.org/journals/mcom/2018-87-310/S0025-5718-2017-03234-8;
                 http://www.ams.org/journals/mcom/2018-87-310/S0025-5718-2017-03234-8/S0025-5718-2017-03234-8.pdf;
                 https://www.ams.org/mathscinet/search/authors.html?authorName=Rump%2C%20Siegfried%20M.;
                 https://www.ams.org/mathscinet/search/authors.html?mrauthid=644190",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
}


bibtype: inproceedings
filename: fparith.bib
label: Jeannerod:2018:VWS
author: Claude-Pierre Jeannerod and Jean-Michel Muller and Paul Zimmermann
title: On Various Ways to Split a Floating-Point Number
crossref: Tenca:2018:PIS
pages: 53--60
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464793
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Claude-Pierre Jeannerod and Jean-Michel Muller and Paul Zimmermann
rawtitle: On Various Ways to Split a Floating-Point Number
abstract:
We review several ways to split a floating-point number, that is, to decompose it into the exact sum of two floating-point numbers of smaller precision. All the methods considered here involve only a few IEEE floating-point operations, with rounding to nearest and including possibly the fused multiply -add (FMA). Applications range from the implementation of integer functions such as round and floor to the computation of suitable scaling factors aimed, for example, at avoiding spurious underflows and overflows when implementing functions such as the hypotenuse.

keywords:
ARITH-25; Computer architecture; Containers; Digital arithmetic; floating point arithmetic; floating-point number; Floors; IEEE floating-point operations; integer functions; Lips; Matlab; Optimization

rawabstract:
We review several ways to split a floating-point number, that is, to decompose it into the exact sum of two floating-point numbers of smaller precision. All the methods considered here involve only a few IEEE floating-point operations, with rounding to nearest and including possibly the fused multiply -add (FMA). Applications range from the implementation of integer functions such as round and floor to the computation of suitable scaling factors aimed, for example, at avoiding spurious underflows and overflows when implementing functions such as the hypotenuse.

entry:
@InProceedings{Jeannerod:2018:VWS,
  author =       "Claude-Pierre Jeannerod and Jean-Michel Muller and
                 Paul Zimmermann",
  title =        "On Various Ways to Split a Floating-Point Number",
  crossref =     "Tenca:2018:PIS",
  pages =        "53--60",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464793",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We review several ways to split a floating-point
                 number, that is, to decompose it into the exact sum of
                 two floating-point numbers of smaller precision. All
                 the methods considered here involve only a few IEEE
                 floating-point operations, with rounding to nearest and
                 including possibly the fused multiply -add (FMA).
                 Applications range from the implementation of integer
                 functions such as round and floor to the computation of
                 suitable scaling factors aimed, for example, at
                 avoiding spurious underflows and overflows when
                 implementing functions such as the hypotenuse.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-25; Computer architecture; Containers; Digital
                 arithmetic; floating point arithmetic; floating-point
                 number; Floors; IEEE floating-point operations; integer
                 functions; Lips; Matlab; Optimization",
}


bibtype: article
filename: fparith.bib
label: Jeon:2018:HMP
author: Dong-Ik Jeon and Kyeong-Bin Park and Ki-Seok Chung
journal: j-IEEE-COMPUT-ARCHIT-LETT
volume: 17
number: 1
pages: 5--8
month: jan
monthnumber: 1
year: 2018
DOI: https://doi.org/10.1109/LCA.2017.2700298
ISSN: 1556-6056 (print), 1556-6064 (electronic) OR 15566056 (print), 15566064 (electronic)
ISSNL: 1556-6056 OR 15566056
bibdate: Tue Jun 25 07:41:05 2019
bibtimestamp: 2019.06.25 07:41:05 ???
fjournal: IEEE Computer Architecture Letters
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10208
rawauthor: Dong-Ik Jeon and Kyeong-Bin Park and Ki-Seok Chung
ORCID: Jeon, Dong-Ik/0000-0002-8572-4184
title:
HMC-MAC: Processing-in Memory Architecture for Multiply--Accumulate Operations with Hybrid Memory Cube

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeecomputarchitlett.bib

abstract:
Many studies focus on implementing processing-in memory (PIM) on the logic die of the hybrid memory cube (HMC) architecture. The multiply-accumulate (MAC) operation is heavily used in digital signal processing (DSP) systems. In this paper, a novel PIM architecture called HMC-MAC that implements the MAC operation in the HMC is proposed. The vault controllers of the conventional HMC are working independently to maximize the parallelism, and HMC-MAC is based on the conventional HMC without modifying the architecture much. Therefore, a large number of MAC operations can be processed in parallel. In HMC-MAC, the MAC operation can be carried out simultaneously with as much as 128 KB data. The correctness on HMC-MAC is verified by simulations, and its performance is better than the conventional CPU-based MAC operation when the MAC operation is consecutively executed at least six times

keywords:
Computers; CPU-based MAC operation; digital signal processing; digital signal processing systems; DRAM chips; DSP systems; Electronic mail; HMC-MAC; hybrid memory cube architecture; logic circuits; logic die; memory architecture; Memory architecture; Memory management; memory size 128.0 KByte; Memory structures; memory used as logic; multiple data stream architectures; multiply-accumulate operation; parallel processing; processing-in memory architecture; Random access memory; Registers; vault controllers

affiliation:
Chung, KS (Reprint Author), Hanyang Univ, Dept Elect & Comp Engn, Seoul 04763, South Korea. Jeon, Dong-Ik; Park, Kyeong-Bin; Chung, Ki-Seok, Hanyang Univ, Dept Elect & Comp Engn, Seoul 04763, South Korea.

rawabstract:
Many studies focus on implementing processing-in memory (PIM) on the logic die of the hybrid memory cube (HMC) architecture. The multiply-accumulate (MAC) operation is heavily used in digital signal processing (DSP) systems. In this paper, a novel PIM architecture called HMC-MAC that implements the MAC operation in the HMC is proposed. The vault controllers of the conventional HMC are working independently to maximize the parallelism, and HMC-MAC is based on the conventional HMC without modifying the architecture much. Therefore, a large number of MAC operations can be processed in parallel. In HMC-MAC, the MAC operation can be carried out simultaneously with as much as 128 KB data. The correctness on HMC-MAC is verified by simulations, and its performance is better than the conventional CPU-based MAC operation when the MAC operation is consecutively executed at least six times

rawtitle:
{HMC-MAC}: Processing-in Memory Architecture for Multiply--Accumulate Operations with Hybrid Memory Cube

entry:
@Article{Jeon:2018:HMP,
  author =       "Dong-Ik Jeon and Kyeong-Bin Park and Ki-Seok Chung",
  title =        "{HMC-MAC}: Processing-in Memory Architecture for
                 Multiply--Accumulate Operations with Hybrid Memory
                 Cube",
  journal =      j-IEEE-COMPUT-ARCHIT-LETT,
  volume =       "17",
  number =       "1",
  pages =        "5--8",
  month =        jan # "\slash " # jun,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/LCA.2017.2700298",
  ISSN =         "1556-6056 (print), 1556-6064 (electronic)",
  ISSN-L =       "1556-6056",
  bibdate =      "Tue Jun 25 07:41:05 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeecomputarchitlett.bib",
  abstract =     "Many studies focus on implementing processing-in
                 memory (PIM) on the logic die of the hybrid memory cube
                 (HMC) architecture. The multiply-accumulate (MAC)
                 operation is heavily used in digital signal processing
                 (DSP) systems. In this paper, a novel PIM architecture
                 called HMC-MAC that implements the MAC operation in the
                 HMC is proposed. The vault controllers of the
                 conventional HMC are working independently to maximize
                 the parallelism, and HMC-MAC is based on the
                 conventional HMC without modifying the architecture
                 much. Therefore, a large number of MAC operations can
                 be processed in parallel. In HMC-MAC, the MAC operation
                 can be carried out simultaneously with as much as 128
                 KB data. The correctness on HMC-MAC is verified by
                 simulations, and its performance is better than the
                 conventional CPU-based MAC operation when the MAC
                 operation is consecutively executed at least six
                 times",
  acknowledgement = ack-nhfb,
  affiliation =  "Chung, KS (Reprint Author), Hanyang Univ, Dept Elect
                 \& Comp Engn, Seoul 04763, South Korea. Jeon, Dong-Ik;
                 Park, Kyeong-Bin; Chung, Ki-Seok, Hanyang Univ, Dept
                 Elect \& Comp Engn, Seoul 04763, South Korea.",
  author-email = "estwingz@naver.com lay1523@naver.com
                 kchung@hanyang.ac.kr",
  da =           "2019-06-20",
  doc-delivery-number = "FZ6EO",
  eissn =        "1556-6064",
  fjournal =     "IEEE Computer Architecture Letters",
  funding-acknowledgement = "Basic Science Research Program through the
                 National Research Foundation of Korea(NRF) --- Ministry
                 of Education [NRF-2015R1D1A1A09061079]",
  funding-text = "This research was supported by Basic Science Research
                 Program through the National Research Foundation of
                 Korea(NRF) funded by the Ministry of Education
                 (NRF-2015R1D1A1A09061079).",
  journal-iso =  "IEEE Comput. Archit. Lett.",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10208",
  keywords =     "Computers; CPU-based MAC operation; digital signal
                 processing; digital signal processing systems; DRAM
                 chips; DSP systems; Electronic mail; HMC-MAC; hybrid
                 memory cube architecture; logic circuits; logic die;
                 memory architecture; Memory architecture; Memory
                 management; memory size 128.0 KByte; Memory structures;
                 memory used as logic; multiple data stream
                 architectures; multiply-accumulate operation; parallel
                 processing; processing-in memory architecture; Random
                 access memory; Registers; vault controllers",
  number-of-cited-references = "11",
  ORCID-numbers = "Jeon, Dong-Ik/0000-0002-8572-4184",
  research-areas = "Computer Science",
  times-cited =  "0",
  unique-id =    "Jeon:2018:HMP",
  web-of-science-categories = "Computer Science, Hardware \&
                 Architecture",
}


bibtype: article
filename: fparith.bib
label: Jiang:2018:EFD
author: Xiaoyu Jiang and Kicheon Hong
title: Explicit form of determinants and inverse matrices of Tribonacci $r$-circulant type matrices
journal: j-J-MATH-CHEM
volume: 56
number: 4
pages: 1234--1249
month: apr
monthnumber: 4
year: 2018
CODEN: JMCHEG
DOI: https://doi.org/10.1007/s10910-017-0843-8
ISSN: 0259-9791 (print), 1572-8897 (electronic) OR 02599791 (print), 15728897 (electronic)
ISSNL: 0259-9791 OR 02599791
bibdate: Tue Mar 6 07:08:26 MST 2018
bibtimestamp: 2018.03.06 07:08:26 MST
URL: https://link.springer.com/article/10.1007/s10910-017-0843-8
fjournal: Journal of Mathematical Chemistry
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10910
journalabr: J. Math. Chem.
rawauthor: Xiaoyu Jiang and Kicheon Hong
rawtitle: Explicit form of determinants and inverse matrices of {Tribonacci} $r$-circulant type matrices
bibsource:
http://link.springer.com/journal/10910/56/4; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jmathchem.bib

entry:
@Article{Jiang:2018:EFD,
  author =       "Xiaoyu Jiang and Kicheon Hong",
  title =        "Explicit form of determinants and inverse matrices of
                 {Tribonacci} $r$-circulant type matrices",
  journal =      j-J-MATH-CHEM,
  volume =       "56",
  number =       "4",
  pages =        "1234--1249",
  month =        apr,
  year =         "2018",
  CODEN =        "JMCHEG",
  DOI =          "https://doi.org/10.1007/s10910-017-0843-8",
  ISSN =         "0259-9791 (print), 1572-8897 (electronic)",
  ISSN-L =       "0259-9791",
  bibdate =      "Tue Mar 6 07:08:26 MST 2018",
  bibsource =    "http://link.springer.com/journal/10910/56/4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jmathchem.bib",
  URL =          "https://link.springer.com/article/10.1007/s10910-017-0843-8",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Mathematical Chemistry",
  journal-URL =  "http://link.springer.com/journal/10910",
  journalabr =   "J. Math. Chem.",
}


bibtype: article
filename: fparith.bib
label: Johnson:2018:RFP
author: Jeff Johnson
title: Rethinking floating point for deep learning
journal: arXiv.org
pages: 8
day: 1
month: nov
monthnumber: 11
year: 2018
bibdate: Mon Feb 10 09:27:01 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 09:27:01 ???
URL: https://arxiv.org/abs/1811.01721
acknowledgement: ack-nhfb
rawauthor: Jeff Johnson
rawtitle: Rethinking floating point for deep learning
abstract:
Reducing hardware overhead of neural networks for faster or lower power inference and training is an active area of research. Uniform quantization using integer multiply-add has been thoroughly investigated, which requires learning many quantization parameters, fine-tuning training or other prerequisites. Little effort is made to improve floating point relative to this baseline; it remains energy inefficient, and word size reduction yields drastic loss in needed dynamic range. We improve floating point to be more energy efficient than equivalent bit width integer hardware on a 28 nm ASIC process while retaining accuracy in 8 bits with a novel hybrid log multiply / linear add, Kulisch accumulation and tapered encodings from Gustafson's posit format. With no network retraining, and drop-in replacement of all math and float32 parameters via round-to-nearest-even only, this open-sourced 8-bit log float is within 0.9% top-1 and 0.2% top-5 accuracy of the original float32 ResNet-50 CNN model on ImageNet. Unlike int8 quantization, it is still a general purpose floating point arithmetic, interpretable out-of-the-box. Our 8/38-bit log float multiply-add is synthesized and power profiled at 28 nm at $ 0.96 times $ the power and $ 1.12 times $ the area of 8/32-bit integer multiply-add. In 16 bits, our log float multiply-add is $ 0.59 times $ the power and $ 0.68 times $ the area of IEEE 754 float16 fused multiply-add, maintaining the same significand precision and dynamic range, proving useful for training ASICs as well.

rawabstract:
Reducing hardware overhead of neural networks for faster or lower power inference and training is an active area of research. Uniform quantization using integer multiply-add has been thoroughly investigated, which requires learning many quantization parameters, fine-tuning training or other prerequisites. Little effort is made to improve floating point relative to this baseline; it remains energy inefficient, and word size reduction yields drastic loss in needed dynamic range. We improve floating point to be more energy efficient than equivalent bit width integer hardware on a 28 nm ASIC process while retaining accuracy in 8 bits with a novel hybrid log multiply\slash linear add, Kulisch accumulation and tapered encodings from Gustafson's posit format. With no network retraining, and drop-in replacement of all math and float32 parameters via round-to-nearest-even only, this open-sourced 8-bit log float is within 0.9\% top-1 and 0.2\% top-5 accuracy of the original float32 ResNet-50 CNN model on ImageNet. Unlike int8 quantization, it is still a general purpose floating point arithmetic, interpretable out-of-the-box. Our 8/38-bit log float multiply-add is synthesized and power profiled at 28 nm at $ 0.96 \times $ the power and $ 1.12 \times $ the area of 8/32-bit integer multiply-add. In 16 bits, our log float multiply-add is $ 0.59 \times $ the power and $ 0.68 \times $ the area of IEEE 754 float16 fused multiply-add, maintaining the same significand precision and dynamic range, proving useful for training ASICs as well.

entry:
@Article{Johnson:2018:RFP,
  author =       "Jeff Johnson",
  title =        "Rethinking floating point for deep learning",
  journal =      "arXiv.org",
  pages =        "8",
  day =          "1",
  month =        nov,
  year =         "2018",
  bibdate =      "Mon Feb 10 09:27:01 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1811.01721",
  abstract =     "Reducing hardware overhead of neural networks for
                 faster or lower power inference and training is an
                 active area of research. Uniform quantization using
                 integer multiply-add has been thoroughly investigated,
                 which requires learning many quantization parameters,
                 fine-tuning training or other prerequisites. Little
                 effort is made to improve floating point relative to
                 this baseline; it remains energy inefficient, and word
                 size reduction yields drastic loss in needed dynamic
                 range. We improve floating point to be more energy
                 efficient than equivalent bit width integer hardware on
                 a 28 nm ASIC process while retaining accuracy in 8 bits
                 with a novel hybrid log multiply\slash linear add,
                 Kulisch accumulation and tapered encodings from
                 Gustafson's posit format. With no network retraining,
                 and drop-in replacement of all math and float32
                 parameters via round-to-nearest-even only, this
                 open-sourced 8-bit log float is within 0.9\% top-1 and
                 0.2\% top-5 accuracy of the original float32 ResNet-50
                 CNN model on ImageNet. Unlike int8 quantization, it is
                 still a general purpose floating point arithmetic,
                 interpretable out-of-the-box. Our 8/38-bit log float
                 multiply-add is synthesized and power profiled at 28 nm
                 at $ 0.96 \times $ the power and $ 1.12 \times $ the
                 area of 8/32-bit integer multiply-add. In 16 bits, our
                 log float multiply-add is $ 0.59 \times $ the power and
                 $ 0.68 \times $ the area of IEEE 754 float16 fused
                 multiply-add, maintaining the same significand
                 precision and dynamic range, proving useful for
                 training ASICs as well.",
  acknowledgement = ack-nhfb,
  primaryclass = "cs.NA",
}


bibtype: inproceedings
filename: fparith.bib
label: Kohlbecker:2018:SNF
author: Ignaz Kohlbecker
title: The Slide Number Format
crossref: ACM:2018:CNG
pages: 1--6
year: 2018
DOI: https://doi.org/10.1145/3190339.3190342
bibdate: Mon Dec 11 09:01:38 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.11 09:01:38 ???
keywords: posit arithmetic; slide number format; universal number (unum) arithmetic
acknowledgement: ack-nhfb
articleno: 3
rawauthor: Ignaz Kohlbecker
rawtitle: The Slide Number Format
abstract:
The Slide number format divides the real number line into connected sets. Compared to the unum format [3], there is no ubit, no infinity, and values are placed on a logarithmic scale with base 10. Formal definitions for Slides and intervals composed of Slide pairs are provided. The relative error is compared with that of single precision floats. The performance of conversions to and from human readable form is measured.

rawabstract:
The Slide number format divides the real number line into connected sets. Compared to the unum format [3], there is no ubit, no infinity, and values are placed on a logarithmic scale with base 10. Formal definitions for Slides and intervals composed of Slide pairs are provided. The relative error is compared with that of single precision floats. The performance of conversions to and from human readable form is measured.

entry:
@InProceedings{Kohlbecker:2018:SNF,
  author =       "Ignaz Kohlbecker",
  title =        "The Slide Number Format",
  crossref =     "ACM:2018:CNG",
  pages =        "1--6",
  year =         "2018",
  DOI =          "https://doi.org/10.1145/3190339.3190342",
  bibdate =      "Mon Dec 11 09:01:38 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Slide number format divides the real number line
                 into connected sets. Compared to the unum format [3],
                 there is no ubit, no infinity, and values are placed on
                 a logarithmic scale with base 10. Formal definitions
                 for Slides and intervals composed of Slide pairs are
                 provided. The relative error is compared with that of
                 single precision floats. The performance of conversions
                 to and from human readable form is measured.",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  keywords =     "posit arithmetic; slide number format; universal
                 number (unum) arithmetic",
}


bibtype: article
filename: fparith.bib
label: Kromer:2018:AQO
author: Pavel Kromer and Jan Platos and Jana Nowakova and Vaclav Snasel
title: An acceleration of quasigroup operations by residue arithmetic
journal: j-CCPE
volume: 30
number: 2
pages: ??--??
day: 25
month: jan
monthnumber: 1
year: 2018
CODEN: CCPEBO
DOI: https://doi.org/10.1002/cpe.4239
ISSN: 1532-0626 (print), 1532-0634 (electronic) OR 15320626 (print), 15320634 (electronic)
ISSNL: 1532-0626 OR 15320626
bibdate: Sat Dec 30 09:12:00 MST 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/ccpe.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.12.30 09:12:00 MST
fjournal: Concurrency and Computation: Practice and Experience
acknowledgement: ack-nhfb
journalURL: http://www.interscience.wiley.com/jpages/1532-0626
rawauthor: Pavel Kr{\"o}mer and Jan Plato{\v{s}} and Jana Nowakov{\'a} and V{\'a}clav Sn{\'a}{\v{s}}el
rawtitle: An acceleration of quasigroup operations by residue arithmetic
entry:
@Article{Kromer:2018:AQO,
  author =       "Pavel Kr{\"o}mer and Jan Plato{\v{s}} and Jana
                 Nowakov{\'a} and V{\'a}clav Sn{\'a}{\v{s}}el",
  title =        "An acceleration of quasigroup operations by residue
                 arithmetic",
  journal =      j-CCPE,
  volume =       "30",
  number =       "2",
  pages =        "??--??",
  day =          "25",
  month =        jan,
  year =         "2018",
  CODEN =        "CCPEBO",
  DOI =          "https://doi.org/10.1002/cpe.4239",
  ISSN =         "1532-0626 (print), 1532-0634 (electronic)",
  ISSN-L =       "1532-0626",
  bibdate =      "Sat Dec 30 09:12:00 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ccpe.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Concurrency and Computation: Practice and Experience",
  journal-URL =  "http://www.interscience.wiley.com/jpages/1532-0626",
}


bibtype: inproceedings
filename: fparith.bib
label: Kumm:2018:KRM
author: Martin Kumm and Oscar Gustafsson and Florent de Dinechin and Johannes Kappauf and Peter Zipf
title: Karatsuba with Rectangular Multipliers for FPGAs
crossref: Tenca:2018:PIS
pages: 13--20
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464809
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Martin Kumm and Oscar Gustafsson and Florent de Dinechin and Johannes Kappauf and Peter Zipf
rawtitle: {Karatsuba} with Rectangular Multipliers for {FPGAs}
abstract:
This work presents an extension of Karatsuba's method to efficiently use rectangular multipliers as a base for larger multipliers. The rectangular multipliers that motivate this work are the embedded $ 18 times 25$-bit signed multipliers found in the DSP blocks of recent Xilinx FPGAs: The traditional Karatsuba approach must under-use them as square $ 18 times 18 $ ones. This work shows that rectangular multipliers can be efficiently exploited in a modified Karatsuba method if their input word sizes have a large greatest common divider. In the Xilinx FPG A case, this can be obtained by using the embedded multipliers as $ 16 times 24 $ unsigned and as $ 17 times 25$ signed ones. The obtained architectures are implemented with due detail to architectural features such as the pre-adders and post-adders available in Xilinx DSP blocks. They are synthesized and compared with traditional Karatsuba, but also with (non-Karatsuba) state-of-the-art tiling techniques that make use of the full rectangular multipliers. The proposed technique improves resource consumption and performance for multipliers of numbers larger than 64 bits.

keywords:
25-bit signed multipliers; adders; ARITH-25; Computer architecture; Delays; Digital arithmetic; digital arithmetic; Electrical engineering; embedded multipliers; field programmable gate arrays; Field programmable gate arrays; Hardware; larger multipliers; modified Karatsuba method; multiplying circuits; rectangular multipliers; word length 64.0 bit

rawabstract:
This work presents an extension of Karatsuba's method to efficiently use rectangular multipliers as a base for larger multipliers. The rectangular multipliers that motivate this work are the embedded $ 18 \times 25$-bit signed multipliers found in the DSP blocks of recent Xilinx FPGAs: The traditional Karatsuba approach must under-use them as square $ 18 \times 18 $ ones. This work shows that rectangular multipliers can be efficiently exploited in a modified Karatsuba method if their input word sizes have a large greatest common divider. In the Xilinx FPG A case, this can be obtained by using the embedded multipliers as $ 16 \times 24 $ unsigned and as $ 17 \times 25$ signed ones. The obtained architectures are implemented with due detail to architectural features such as the pre-adders and post-adders available in Xilinx DSP blocks. They are synthesized and compared with traditional Karatsuba, but also with (non-Karatsuba) state-of-the-art tiling techniques that make use of the full rectangular multipliers. The proposed technique improves resource consumption and performance for multipliers of numbers larger than 64 bits.

entry:
@InProceedings{Kumm:2018:KRM,
  author =       "Martin Kumm and Oscar Gustafsson and Florent de
                 Dinechin and Johannes Kappauf and Peter Zipf",
  title =        "{Karatsuba} with Rectangular Multipliers for {FPGAs}",
  crossref =     "Tenca:2018:PIS",
  pages =        "13--20",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464809",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This work presents an extension of Karatsuba's method
                 to efficiently use rectangular multipliers as a base
                 for larger multipliers. The rectangular multipliers
                 that motivate this work are the embedded $ 18 \times
                 25$-bit signed multipliers found in the DSP blocks of
                 recent Xilinx FPGAs: The traditional Karatsuba approach
                 must under-use them as square $ 18 \times 18 $ ones.
                 This work shows that rectangular multipliers can be
                 efficiently exploited in a modified Karatsuba method if
                 their input word sizes have a large greatest common
                 divider. In the Xilinx FPG A case, this can be obtained
                 by using the embedded multipliers as $ 16 \times 24 $
                 unsigned and as $ 17 \times 25$ signed ones. The
                 obtained architectures are implemented with due detail
                 to architectural features such as the pre-adders and
                 post-adders available in Xilinx DSP blocks. They are
                 synthesized and compared with traditional Karatsuba,
                 but also with (non-Karatsuba) state-of-the-art tiling
                 techniques that make use of the full rectangular
                 multipliers. The proposed technique improves resource
                 consumption and performance for multipliers of numbers
                 larger than 64 bits.",
  acknowledgement = ack-nhfb,
  keywords =     "25-bit signed multipliers; adders; ARITH-25; Computer
                 architecture; Delays; Digital arithmetic; digital
                 arithmetic; Electrical engineering; embedded
                 multipliers; field programmable gate arrays; Field
                 programmable gate arrays; Hardware; larger multipliers;
                 modified Karatsuba method; multiplying circuits;
                 rectangular multipliers; word length 64.0 bit",
}


bibtype: article
filename: fparith.bib
label: Kumm:2018:OSC
author: Martin Kumm and Oscar Gustafsson and Mario Garrido and Peter Zipf
title: Optimal Single Constant Multiplication Using Ternary Adders
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 65
number: 7
pages: 928--932
month: jul
monthnumber: 7
year: 2018
DOI: https://doi.org/10.1109/TCSII.2016.2631630
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Sat Feb 8 09:52:23 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 09:52:23 ???
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
ajournal: IEEE trans. circuits syst., II Express briefs
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Martin Kumm and Oscar Gustafsson and Mario Garrido and Peter Zipf
rawtitle: Optimal Single Constant Multiplication Using Ternary Adders
keywords:
adders; Adders; Arithmetic; average adder reductions; bit shifts; circuit optimization; circuits; coefficient word sizes; Complexity theory; digital arithmetic; field programmable gate arrays; Field programmable gate arrays; field-programmable gate arrays; field-programmable gate arrays (FPGAs); fixed-point arithmetic optimization; FPGA; mathematics; multiplying circuits; numeric algorithms; optimal constant multiplication circuits; optimal single constant multiplication; Optimization; optimization methods; Signal processing algorithms; single constant coefficient multiplication; support efficient ternary adders; Topology; two-input adders; word length 22.0 bit; word length 5.0 bit

entry:
@Article{Kumm:2018:OSC,
  author =       "Martin Kumm and Oscar Gustafsson and Mario Garrido and
                 Peter Zipf",
  title =        "Optimal Single Constant Multiplication Using Ternary
                 Adders",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "65",
  number =       "7",
  pages =        "928--932",
  month =        jul,
  year =         "2018",
  DOI =          "https://doi.org/10.1109/TCSII.2016.2631630",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Sat Feb 8 09:52:23 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE trans. circuits syst., II Express briefs",
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
  keywords =     "adders; Adders; Arithmetic; average adder reductions;
                 bit shifts; circuit optimization; circuits; coefficient
                 word sizes; Complexity theory; digital arithmetic;
                 field programmable gate arrays; Field programmable gate
                 arrays; field-programmable gate arrays;
                 field-programmable gate arrays (FPGAs); fixed-point
                 arithmetic optimization; FPGA; mathematics; multiplying
                 circuits; numeric algorithms; optimal constant
                 multiplication circuits; optimal single constant
                 multiplication; Optimization; optimization methods;
                 Signal processing algorithms; single constant
                 coefficient multiplication; support efficient ternary
                 adders; Topology; two-input adders; word length 22.0
                 bit; word length 5.0 bit",
}


bibtype: article
filename: fparith.bib
label: Lam:2018:FGF
author: Michael O. Lam and Jeffrey K. Hollingsworth
title: Fine-grained floating-point precision analysis
journal: j-IJHPCA
volume: 32
number: 2
pages: 231--245
year: 2018
CODEN: IHPCFL
DOI: https://doi.org/10.1177/1094342016652462
ISSN: 1094-3420 (print), 1741-2846 (electronic) OR 10943420 (print), 17412846 (electronic)
ISSNL: 1094-3420 OR 10943420
bibdate: Mon Nov 5 17:34:16 MST 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ijsa.bib
bibtimestamp: 2018.11.05 17:34:16 MST
URL: http://journals.sagepub.com/doi/full/10.1177/1094342016652462
fjournal: International Journal of High Performance Computing Applications
keywords: interval arithmetic; truncating arithmetic; variable-precision arithmetic
acknowledgement: ack-nhfb
journalURL: http://hpc.sagepub.com/content/by/year
rawauthor: Michael O. Lam and Jeffrey K. Hollingsworth
rawtitle: Fine-grained floating-point precision analysis
entry:
@Article{Lam:2018:FGF,
  author =       "Michael O. Lam and Jeffrey K. Hollingsworth",
  title =        "Fine-grained floating-point precision analysis",
  journal =      j-IJHPCA,
  volume =       "32",
  number =       "2",
  pages =        "231--245",
  year =         "2018",
  CODEN =        "IHPCFL",
  DOI =          "https://doi.org/10.1177/1094342016652462",
  ISSN =         "1094-3420 (print), 1741-2846 (electronic)",
  ISSN-L =       "1094-3420",
  bibdate =      "Mon Nov 5 17:34:16 MST 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ijsa.bib",
  URL =          "http://journals.sagepub.com/doi/full/10.1177/1094342016652462",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of High Performance Computing
                 Applications",
  journal-URL =  "http://hpc.sagepub.com/content/by/year",
  keywords =     "interval arithmetic; truncating arithmetic;
                 variable-precision arithmetic",
  xxmonth =      mar,
}


bibtype: inproceedings
filename: fparith.bib
label: Langhammer:2018:HDP
author: Martin Langhammer and Gregg Baeckler
title: High Density and Performance Multiplication for FPGA
crossref: Tenca:2018:PIS
pages: 5--12
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464695
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Martin Langhammer and Gregg Baeckler
rawtitle: High Density and Performance Multiplication for {FPGA}
abstract:
Arithmetic based applications are one of the most common use cases for modern FPGAs. Currently, machine learning is emerging as the fastest growth area for FPG As, renewing an interest in low precision multiplication. There is now a new focus on multiplication in the soft fabric --- very high-density systems, consisting of many thousands of operations, are the current norm. In this paper we introduce multiplier regularization, which restructures common multiplier algorithms into smaller, and more efficient architectures. The multiplier structure is parameterizable, and results are given for a continuous range of input sizes, although the algorithm is most efficient for small input precisions. The multiplier is particularly effective for typical machine learning inferencing uses, and the presented cores can be used for dot products required for these applications. Although the examples presented here are optimized for Intel Stratix 10 devices, the concept of regularized arithmetic structures are applicable to generic FPGA LUT architectures. Results are compared to Intel Megafunction IP as well as contrasted with normalized representations of recently published results for Xilinx devices. We report a 10% to 35% smaller area, and a more significant latency reduction, in the range of 25% to 50%, for typical inferencing use cases.

keywords:
Adders; ARITH-25; arithmetic based applications; common multiplier algorithms; digital arithmetic; dot products; Field programmable gate arrays; field programmable gate arrays; generic FPGA LUT architectures; high-density systems; Intel Megafunction IP; Intel Stratix devices; IP networks; latency reduction; logic design; low precision multiplication; Machine learning; machine learning; multiplier regularization; multiplier structure; Performance evaluation; performance multiplication; regularized arithmetic structures; Routing; soft fabric-very high-density systems; table lookup; Table lookup

rawabstract:
Arithmetic based applications are one of the most common use cases for modern FPGAs. Currently, machine learning is emerging as the fastest growth area for FPG As, renewing an interest in low precision multiplication. There is now a new focus on multiplication in the soft fabric --- very high-density systems, consisting of many thousands of operations, are the current norm. In this paper we introduce multiplier regularization, which restructures common multiplier algorithms into smaller, and more efficient architectures. The multiplier structure is parameterizable, and results are given for a continuous range of input sizes, although the algorithm is most efficient for small input precisions. The multiplier is particularly effective for typical machine learning inferencing uses, and the presented cores can be used for dot products required for these applications. Although the examples presented here are optimized for Intel Stratix 10 devices, the concept of regularized arithmetic structures are applicable to generic FPGA LUT architectures. Results are compared to Intel Megafunction IP as well as contrasted with normalized representations of recently published results for Xilinx devices. We report a 10\% to 35\% smaller area, and a more significant latency reduction, in the range of 25\% to 50\%, for typical inferencing use cases.

entry:
@InProceedings{Langhammer:2018:HDP,
  author =       "Martin Langhammer and Gregg Baeckler",
  title =        "High Density and Performance Multiplication for
                 {FPGA}",
  crossref =     "Tenca:2018:PIS",
  pages =        "5--12",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464695",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Arithmetic based applications are one of the most
                 common use cases for modern FPGAs. Currently, machine
                 learning is emerging as the fastest growth area for FPG
                 As, renewing an interest in low precision
                 multiplication. There is now a new focus on
                 multiplication in the soft fabric --- very high-density
                 systems, consisting of many thousands of operations,
                 are the current norm. In this paper we introduce
                 multiplier regularization, which restructures common
                 multiplier algorithms into smaller, and more efficient
                 architectures. The multiplier structure is
                 parameterizable, and results are given for a continuous
                 range of input sizes, although the algorithm is most
                 efficient for small input precisions. The multiplier is
                 particularly effective for typical machine learning
                 inferencing uses, and the presented cores can be used
                 for dot products required for these applications.
                 Although the examples presented here are optimized for
                 Intel Stratix 10 devices, the concept of regularized
                 arithmetic structures are applicable to generic FPGA
                 LUT architectures. Results are compared to Intel
                 Megafunction IP as well as contrasted with normalized
                 representations of recently published results for
                 Xilinx devices. We report a 10\% to 35\% smaller area,
                 and a more significant latency reduction, in the range
                 of 25\% to 50\%, for typical inferencing use cases.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; ARITH-25; arithmetic based applications;
                 common multiplier algorithms; digital arithmetic; dot
                 products; Field programmable gate arrays; field
                 programmable gate arrays; generic FPGA LUT
                 architectures; high-density systems; Intel Megafunction
                 IP; Intel Stratix devices; IP networks; latency
                 reduction; logic design; low precision multiplication;
                 Machine learning; machine learning; multiplier
                 regularization; multiplier structure; Performance
                 evaluation; performance multiplication; regularized
                 arithmetic structures; Routing; soft fabric-very
                 high-density systems; table lookup; Table lookup",
}


bibtype: inproceedings
filename: fparith.bib
label: Langroudi:2018:DLI
author: Seyed Hamed Fatemi Langroudi and Tej Pandit and Dhireesha Kudithipudi
editor: IEEE
title: Deep Learning Inference on Embedded Devices: Fixed-Point vs Posit
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 19--23
year: 2018
DOI: https://doi.org/10.1109/EMC2.2018.00012
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Seyed Hamed Fatemi Langroudi and Tej Pandit and Dhireesha Kudithipudi
raweditor: {IEEE}
rawtitle: Deep Learning Inference on Embedded Devices: Fixed-Point vs Posit
booktitle:
2018 1st Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications (EMC2)

rawbooktitle:
{2018 1st Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications (EMC2)}

entry:
@InProceedings{Langroudi:2018:DLI,
  author =       "Seyed Hamed Fatemi Langroudi and Tej Pandit and
                 Dhireesha Kudithipudi",
  editor =       "{IEEE}",
  booktitle =    "{2018 1st Workshop on Energy Efficient Machine
                 Learning and Cognitive Computing for Embedded
                 Applications (EMC2)}",
  title =        "Deep Learning Inference on Embedded Devices:
                 Fixed-Point vs Posit",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "19--23",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/EMC2.2018.00012",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Lee:2018:APC
author: Wonyeol Lee and Rahul Sharma and Alex Aiken
title: On automatically proving the correctness of tt math.h implementations
journal: j-PACMPL
volume: 2
number: POPL
pages: 47:1--47:??
month: jan
monthnumber: 1
year: 2018
DOI: https://doi.org/10.1145/3158135
ISSN: 2475-1421 OR 24751421
bibdate: Wed Jan 10 09:45:26 MST 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pacmpl.bib
bibtimestamp: 2018.01.10 09:45:26 MST
fjournal: Proceedings of the ACM on Programming Languages
acknowledgement: ack-nhfb
articleno: 47
journalURL: https://pacmpl.acm.org/
rawauthor: Wonyeol Lee and Rahul Sharma and Alex Aiken
rawtitle: On automatically proving the correctness of {\tt math.h} implementations
abstract:
Industry standard implementations of tt math.h claim (often without formal proof) tight bounds on floating-point errors. We demonstrate a novel static analysis that proves these bounds and verifies the correctness of these implementations. Our key insight is a reduction of this verification task to a set of mathematical optimization problems that can be solved by off-the-shelf computer algebra systems. We use this analysis to prove the correctness of implementations in Intel's math library automatically. Prior to this work, these implementations could only be verified with significant manual effort.

rawabstract:
Industry standard implementations of {\tt math.h} claim (often without formal proof) tight bounds on floating-point errors. We demonstrate a novel static analysis that proves these bounds and verifies the correctness of these implementations. Our key insight is a reduction of this verification task to a set of mathematical optimization problems that can be solved by off-the-shelf computer algebra systems. We use this analysis to prove the correctness of implementations in Intel's math library automatically. Prior to this work, these implementations could only be verified with significant manual effort.

entry:
@Article{Lee:2018:APC,
  author =       "Wonyeol Lee and Rahul Sharma and Alex Aiken",
  title =        "On automatically proving the correctness of {\tt
                 math.h} implementations",
  journal =      j-PACMPL,
  volume =       "2",
  number =       "POPL",
  pages =        "47:1--47:??",
  month =        jan,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3158135",
  ISSN =         "2475-1421",
  bibdate =      "Wed Jan 10 09:45:26 MST 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pacmpl.bib",
  abstract =     "Industry standard implementations of {\tt math.h}
                 claim (often without formal proof) tight bounds on
                 floating-point errors. We demonstrate a novel static
                 analysis that proves these bounds and verifies the
                 correctness of these implementations. Our key insight
                 is a reduction of this verification task to a set of
                 mathematical optimization problems that can be solved
                 by off-the-shelf computer algebra systems. We use this
                 analysis to prove the correctness of implementations in
                 Intel's math library automatically. Prior to this work,
                 these implementations could only be verified with
                 significant manual effort.",
  acknowledgement = ack-nhfb,
  articleno =    "47",
  fjournal =     "Proceedings of the ACM on Programming Languages",
  journal-URL =  "https://pacmpl.acm.org/",
}


bibtype: inproceedings
filename: fparith.bib
label: Lehoczky:2018:HLN
crossref: ACM:2018:CNG
pages: 1--7
year: 2018
DOI: https://doi.org/10.1145/3190339.3190343
bibdate: Mon Dec 11 09:02:49 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.11 09:02:49 ???
keywords: posit arithmetic; universal number arithmetic
acknowledgement: ack-nhfb
articleno: 4
author:
Zoltan Lehoczky and Andras Retzler and Richard Toth and Almos Szabo and Benedek Farkas and Krisztian Somogyi

title:
High-level .NET Software Implementations of Unum Type I and Posit with Simultaneous FPGA Implementation Using Hastlayer

abstract:
The unum arithmetic framework has been proposed by Gustafson, D. J. to address the short-comings of the IEEE 754 Standard's floating-point. In this paper, we present our software and hardware implementations of Type I and posit unums. The software implementation is built on the .NET platform as an open source library written in the C# programming language. We automatically create hardware implementations using our .NET to FPGA converter tool called Hastlayer. The amount of hardware resources needed for addition operations are quantified, and the performance of software and prototype hardware for posits are compared. We show that posits are significantly more hardware friendly than Type I unums. Furthermore, our posit FPGA implementation is about 2.04 times more efficient per clock cycle than its software implementation.

rawabstract:
The unum arithmetic framework has been proposed by Gustafson, D. J. to address the short-comings of the IEEE 754 Standard's floating-point. In this paper, we present our software and hardware implementations of Type I and posit unums. The software implementation is built on the .NET platform as an open source library written in the C\# programming language. We automatically create hardware implementations using our .NET to FPGA converter tool called Hastlayer. The amount of hardware resources needed for addition operations are quantified, and the performance of software and prototype hardware for posits are compared. We show that posits are significantly more hardware friendly than Type I unums. Furthermore, our posit FPGA implementation is about 2.04 times more efficient per clock cycle than its software implementation.

rawauthor:
Zolt{\'a}n Leh{\'o}czky and Andr{\'a}s Retzler and Rich{\'a}rd T{\'o}th and {\'A}lmos Szab{\'o} and Benedek Farkas and Kriszti{\'a}n Somogyi

rawtitle:
High-level {.NET} Software Implementations of Unum {Type I} and Posit with Simultaneous {FPGA} Implementation Using {Hastlayer}

entry:
@InProceedings{Lehoczky:2018:HLN,
  author =       "Zolt{\'a}n Leh{\'o}czky and Andr{\'a}s Retzler and
                 Rich{\'a}rd T{\'o}th and {\'A}lmos Szab{\'o} and
                 Benedek Farkas and Kriszti{\'a}n Somogyi",
  title =        "High-level {.NET} Software Implementations of Unum
                 {Type I} and Posit with Simultaneous {FPGA}
                 Implementation Using {Hastlayer}",
  crossref =     "ACM:2018:CNG",
  pages =        "1--7",
  year =         "2018",
  DOI =          "https://doi.org/10.1145/3190339.3190343",
  bibdate =      "Mon Dec 11 09:02:49 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The unum arithmetic framework has been proposed by
                 Gustafson, D. J. to address the short-comings of the
                 IEEE 754 Standard's floating-point. In this paper, we
                 present our software and hardware implementations of
                 Type I and posit unums. The software implementation is
                 built on the .NET platform as an open source library
                 written in the C\# programming language. We
                 automatically create hardware implementations using our
                 .NET to FPGA converter tool called Hastlayer. The
                 amount of hardware resources needed for addition
                 operations are quantified, and the performance of
                 software and prototype hardware for posits are
                 compared. We show that posits are significantly more
                 hardware friendly than Type I unums. Furthermore, our
                 posit FPGA implementation is about 2.04 times more
                 efficient per clock cycle than its software
                 implementation.",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  keywords =     "posit arithmetic; universal number arithmetic",
}


bibtype: misc
filename: fparith.bib
label: Leong:2018:SV
author: Cerlane Leong
title: SoftPosit Version 0.4.1rc
pages: 1--7
year: 2018
bibdate: Sat Dec 16 15:18:01 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 15:18:01 ???
URL: https://gitlab.com/cerlane/SoftPosit
acknowledgement: ack-nhfb
howpublished: Web source code.
rawauthor: Cerlane Leong
rawtitle: {SoftPosit} Version 0.4.1rc
entry:
@Misc{Leong:2018:SV,
  author =       "Cerlane Leong",
  title =        "{SoftPosit} Version 0.4.1rc",
  howpublished = "Web source code.",
  year =         "2018",
  bibdate =      "Sat Dec 16 15:18:01 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://gitlab.com/cerlane/SoftPosit",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2018:DEA
author: He Li and James J. Davis and John Wickerson and George A. Constantinides
title: Digit Elision for Arbitrary-accuracy Iterative Computation
crossref: Tenca:2018:PIS
pages: 107--114
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464691
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: He Li and James J. Davis and John Wickerson and George A. Constantinides
rawtitle: Digit Elision for Arbitrary-accuracy Iterative Computation
abstract:
We recently proposed the first hardware architecture enabling the iterative solution of systems of linear equations to accuracies limited only by the amount of available memory. This technique, named ARCHITECT, achieves exact numeric computation by using online arithmetic to allow the refinement of results from earlier iterations over time, eschewing rounding error. ARCHITECT has a key drawback, however: often, many more digits than strictly necessary are generated, with this problem exacerbating the more accurate a solution is sought. In this paper, we infer the locations of these superfluous digits within stationary iterative calculations by exploiting online arithmetic's digit dependencies and using forward error analysis. We demonstrate that their lack of computation is guaranteed not to affect the ability to reach a solution of any accuracy. Versus ARCHITECT, our illustrative hardware implementation achieves a geometric mean $ 20.1 times $ speedup in the solution of a set of representative linear systems through the avoidance of redundant digit calculation. For the computation of high-precision results, we also obtain an up-to $ 22.4 times $ memory requirement reduction over the same baseline. Finally, we demonstrate that solvers implemented following our proposals can show superiority over conventional arithmetic implementations by virtue of their runtime-tunable precisions.

keywords:
arbitrary-accuracy iterative computation; ARCHITECT; ARITH-25; arithmetic implementations; Delays; digit dependencies; digit elision; digital arithmetic; error analysis; exact numeric computation; forward error analysis; Hardware; hardware architecture; iterative methods; Iterative methods; iterative solution; Jacobian matrices; linear equations; Linear systems; linear systems; memory requirement reduction; online arithmetic; Proposals; redundant digit calculation; rounding error; Runtime; stationary iterative calculations; superfluous digits

rawabstract:
We recently proposed the first hardware architecture enabling the iterative solution of systems of linear equations to accuracies limited only by the amount of available memory. This technique, named ARCHITECT, achieves exact numeric computation by using online arithmetic to allow the refinement of results from earlier iterations over time, eschewing rounding error. ARCHITECT has a key drawback, however: often, many more digits than strictly necessary are generated, with this problem exacerbating the more accurate a solution is sought. In this paper, we infer the locations of these superfluous digits within stationary iterative calculations by exploiting online arithmetic's digit dependencies and using forward error analysis. We demonstrate that their lack of computation is guaranteed not to affect the ability to reach a solution of any accuracy. Versus ARCHITECT, our illustrative hardware implementation achieves a geometric mean $ 20.1 \times $ speedup in the solution of a set of representative linear systems through the avoidance of redundant digit calculation. For the computation of high-precision results, we also obtain an up-to $ 22.4 \times $ memory requirement reduction over the same baseline. Finally, we demonstrate that solvers implemented following our proposals can show superiority over conventional arithmetic implementations by virtue of their runtime-tunable precisions.

entry:
@InProceedings{Li:2018:DEA,
  author =       "He Li and James J. Davis and John Wickerson and George
                 A. Constantinides",
  title =        "Digit Elision for Arbitrary-accuracy Iterative
                 Computation",
  crossref =     "Tenca:2018:PIS",
  pages =        "107--114",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464691",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We recently proposed the first hardware architecture
                 enabling the iterative solution of systems of linear
                 equations to accuracies limited only by the amount of
                 available memory. This technique, named ARCHITECT,
                 achieves exact numeric computation by using online
                 arithmetic to allow the refinement of results from
                 earlier iterations over time, eschewing rounding error.
                 ARCHITECT has a key drawback, however: often, many more
                 digits than strictly necessary are generated, with this
                 problem exacerbating the more accurate a solution is
                 sought. In this paper, we infer the locations of these
                 superfluous digits within stationary iterative
                 calculations by exploiting online arithmetic's digit
                 dependencies and using forward error analysis. We
                 demonstrate that their lack of computation is
                 guaranteed not to affect the ability to reach a
                 solution of any accuracy. Versus ARCHITECT, our
                 illustrative hardware implementation achieves a
                 geometric mean $ 20.1 \times $ speedup in the solution
                 of a set of representative linear systems through the
                 avoidance of redundant digit calculation. For the
                 computation of high-precision results, we also obtain
                 an up-to $ 22.4 \times $ memory requirement reduction
                 over the same baseline. Finally, we demonstrate that
                 solvers implemented following our proposals can show
                 superiority over conventional arithmetic
                 implementations by virtue of their runtime-tunable
                 precisions.",
  acknowledgement = ack-nhfb,
  keywords =     "arbitrary-accuracy iterative computation; ARCHITECT;
                 ARITH-25; arithmetic implementations; Delays; digit
                 dependencies; digit elision; digital arithmetic; error
                 analysis; exact numeric computation; forward error
                 analysis; Hardware; hardware architecture; iterative
                 methods; Iterative methods; iterative solution;
                 Jacobian matrices; linear equations; Linear systems;
                 linear systems; memory requirement reduction; online
                 arithmetic; Proposals; redundant digit calculation;
                 rounding error; Runtime; stationary iterative
                 calculations; superfluous digits",
}


bibtype: misc
filename: fparith.bib
label: Lie:2018:FPU
author: Sean Lie and Michael Edwin James and Michael Morrison and Gary R. Lauterbach and Srikanth Arekapudi
title: Floating-point unit stochastic rounding for accelerated deep learning
pages: 107--114
day: 13
month: apr
monthnumber: 4
year: 2018
bibdate: Fri Sep 22 17:25:05 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 17:25:05 ???
note: Patent granted 20 September 2022; expires 29 November 2038.
acknowledgement: ack-nhfb
howpublished: U.S. Patent US11449574B2
rawauthor: Sean Lie and Michael Edwin James and Michael Morrison and Gary R. Lauterbach and Srikanth Arekapudi
rawnote: Patent granted 20 September 2022; expires 29 November 2038.
rawtitle: Floating-point unit stochastic rounding for accelerated deep learning
abstract:
Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Each compute element has a respective floating-point unit enabled to perform stochastic rounding, thus in some circumstances enabling reducing systematic bias in long dependency chains of floating-point computations. The long dependency chains of floating-point computations are performed, e.g., to train a neural network or to perform inference with respect to a trained neural network.

rawabstract:
Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Each compute element has a respective floating-point unit enabled to perform stochastic rounding, thus in some circumstances enabling reducing systematic bias in long dependency chains of floating-point computations. The long dependency chains of floating-point computations are performed, e.g., to train a neural network or to perform inference with respect to a trained neural network.

entry:
@Misc{Lie:2018:FPU,
  author =       "Sean Lie and Michael Edwin James and Michael Morrison
                 and Gary R. Lauterbach and Srikanth Arekapudi",
  title =        "Floating-point unit stochastic rounding for
                 accelerated deep learning",
  howpublished = "U.S. Patent US11449574B2",
  day =          "13",
  month =        apr,
  year =         "2018",
  bibdate =      "Fri Sep 22 17:25:05 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Patent granted 20 September 2022; expires 29 November
                 2038.",
  abstract =     "Techniques in advanced deep learning provide
                 improvements in one or more of accuracy, performance,
                 and energy efficiency. An array of processing elements
                 comprising a portion of a neural network accelerator
                 performs flow-based computations on wavelets of data.
                 Each processing element has a respective compute
                 element and a respective routing element. Each compute
                 element has a respective floating-point unit enabled to
                 perform stochastic rounding, thus in some circumstances
                 enabling reducing systematic bias in long dependency
                 chains of floating-point computations. The long
                 dependency chains of floating-point computations are
                 performed, e.g., to train a neural network or to
                 perform inference with respect to a trained neural
                 network.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lindstrom:2018:UCR
author: Peter Lindstrom and Scott Lloyd and Jeffrey Hittinger
title: Universal Coding of the Reals: Alternatives to IEEE Floating Point
crossref: ACM:2018:CNG
pages: 1--14
year: 2018
DOI: https://doi.org/10.1145/3190339.3190344
bibdate: Sun Dec 10 14:24:09 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.10 14:24:09 ???
acknowledgement: ack-nhfb
articleno: 5
rawauthor: Peter Lindstrom and Scott Lloyd and Jeffrey Hittinger
rawtitle: Universal Coding of the Reals: Alternatives to {IEEE} Floating Point
abstract:
We propose a modular framework for representing the real numbers that generalizes IEEE, posits, and related floating-point number systems, and which has its roots in universal codes for the positive integers such as the Elias codes. This framework unifies several known but seemingly unrelated representations within a single schema while also introducing new representations. We particularly focus on variable-length encoding of the binary exponent and on the manner in which fraction bits are mapped to values. Our framework builds upon and shares many of the attractive properties of posits but allows for independent experimentation with exponent codes, fraction mappings, reciprocal closure, rounding modes, handling of under- and overflow, and underlying precision.

rawabstract:
We propose a modular framework for representing the real numbers that generalizes IEEE, posits, and related floating-point number systems, and which has its roots in universal codes for the positive integers such as the Elias codes. This framework unifies several known but seemingly unrelated representations within a single schema while also introducing new representations. We particularly focus on variable-length encoding of the binary exponent and on the manner in which fraction bits are mapped to values. Our framework builds upon and shares many of the attractive properties of posits but allows for independent experimentation with exponent codes, fraction mappings, reciprocal closure, rounding modes, handling of under- and overflow, and underlying precision.

entry:
@InProceedings{Lindstrom:2018:UCR,
  author =       "Peter Lindstrom and Scott Lloyd and Jeffrey
                 Hittinger",
  title =        "Universal Coding of the Reals: Alternatives to {IEEE}
                 Floating Point",
  crossref =     "ACM:2018:CNG",
  pages =        "1--14",
  year =         "2018",
  DOI =          "https://doi.org/10.1145/3190339.3190344",
  bibdate =      "Sun Dec 10 14:24:09 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We propose a modular framework for representing the
                 real numbers that generalizes IEEE, posits, and related
                 floating-point number systems, and which has its roots
                 in universal codes for the positive integers such as
                 the Elias codes. This framework unifies several known
                 but seemingly unrelated representations within a single
                 schema while also introducing new representations. We
                 particularly focus on variable-length encoding of the
                 binary exponent and on the manner in which fraction
                 bits are mapped to values. Our framework builds upon
                 and shares many of the attractive properties of posits
                 but allows for independent experimentation with
                 exponent codes, fraction mappings, reciprocal closure,
                 rounding modes, handling of under- and overflow, and
                 underlying precision.",
  acknowledgement = ack-nhfb,
  articleno =    "5",
}


bibtype: inproceedings
filename: fparith.bib
label: Liu:2018:CRA
author: Weiqiang Liu and Jing Li and Tao Xu and Chenghua Wang and Paolo Montuschi and Fabrizio Lombardi
title: Combining Restoring Array and Logarithmic Dividers into an Approximate Hybrid Design
crossref: Tenca:2018:PIS
pages: 92--98
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464807
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Weiqiang Liu and Jing Li and Tao Xu and Chenghua Wang and Paolo Montuschi and Fabrizio Lombardi
rawtitle: Combining Restoring Array and Logarithmic Dividers into an Approximate Hybrid Design
abstract:
This paper proposes a new design of an approximate hybrid divider (AXHD), which combines the restoring array and the logarithmic dividers to achieve an excellent tradeoff between accuracy and hardware performance. Exact restoring divider cells (EXDCrs) are used to generate the MSBs of the quotient for attaining a high accuracy; the other quotient digits are processed by a logarithmic divider as inexact scheme to improve figures of merit such as power consumption, area and delay. The proposed AXHD is evaluated and analyzed using error and hardware metrics. The proposed design is also compared with the exact restoring divider (EXDr) and previous approximate restoring dividers (AXDrs). The results show that the proposed design achieves very good performance in terms of accuracy and hardware; case studies for image processing also show the validity of the proposed designs.

keywords:
Adders; Approximate Computing; approximate hybrid divider design; approximate restoring dividers; ARITH-25; AXDrs; AXHD; circuit stability; dividing circuits; Electronic mail; Error analysis; exact restoring divider cells; EXDCrs; Hardware; hardware metrics; hardware performance; image processing; Image restoration; logarithmic divider; Logarithmic Divider; logic design; Low Power; MSBs; Power demand; quotient digit processing; restoring array; Restoring Array Divider

rawabstract:
This paper proposes a new design of an approximate hybrid divider (AXHD), which combines the restoring array and the logarithmic dividers to achieve an excellent tradeoff between accuracy and hardware performance. Exact restoring divider cells (EXDCrs) are used to generate the MSBs of the quotient for attaining a high accuracy; the other quotient digits are processed by a logarithmic divider as inexact scheme to improve figures of merit such as power consumption, area and delay. The proposed AXHD is evaluated and analyzed using error and hardware metrics. The proposed design is also compared with the exact restoring divider (EXDr) and previous approximate restoring dividers (AXDrs). The results show that the proposed design achieves very good performance in terms of accuracy and hardware; case studies for image processing also show the validity of the proposed designs.

entry:
@InProceedings{Liu:2018:CRA,
  author =       "Weiqiang Liu and Jing Li and Tao Xu and Chenghua Wang
                 and Paolo Montuschi and Fabrizio Lombardi",
  title =        "Combining Restoring Array and Logarithmic Dividers
                 into an Approximate Hybrid Design",
  crossref =     "Tenca:2018:PIS",
  pages =        "92--98",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464807",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper proposes a new design of an approximate
                 hybrid divider (AXHD), which combines the restoring
                 array and the logarithmic dividers to achieve an
                 excellent tradeoff between accuracy and hardware
                 performance. Exact restoring divider cells (EXDCrs) are
                 used to generate the MSBs of the quotient for attaining
                 a high accuracy; the other quotient digits are
                 processed by a logarithmic divider as inexact scheme to
                 improve figures of merit such as power consumption,
                 area and delay. The proposed AXHD is evaluated and
                 analyzed using error and hardware metrics. The proposed
                 design is also compared with the exact restoring
                 divider (EXDr) and previous approximate restoring
                 dividers (AXDrs). The results show that the proposed
                 design achieves very good performance in terms of
                 accuracy and hardware; case studies for image
                 processing also show the validity of the proposed
                 designs.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; Approximate Computing; approximate hybrid
                 divider design; approximate restoring dividers;
                 ARITH-25; AXDrs; AXHD; circuit stability; dividing
                 circuits; Electronic mail; Error analysis; exact
                 restoring divider cells; EXDCrs; Hardware; hardware
                 metrics; hardware performance; image processing; Image
                 restoration; logarithmic divider; Logarithmic Divider;
                 logic design; Low Power; MSBs; Power demand; quotient
                 digit processing; restoring array; Restoring Array
                 Divider",
}


bibtype: article
filename: fparith.bib
label: Loeffler:2018:WBP
author: John Loeffler
journal: Interesting Engineering
pages: ??--??
day: 22
month: nov
monthnumber: 11
year: 2018
bibdate: Fri Nov 23 11:32:14 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.11.23 11:32:14 ???
URL: https://interestingengineering.com/when-bad-programming-turns-deadly
keywords: floating-point arithmetic; Patriot missile; radiological equipment software malfunction
acknowledgement: ack-nhfb
rawauthor: John Loeffler
title:
When Bad Programming Turns Deadly: A look at programming disasters and how bad programming can be deadly

rawtitle:
When Bad Programming Turns Deadly: A look at programming disasters and how bad programming can be deadly

entry:
@Article{Loeffler:2018:WBP,
  author =       "John Loeffler",
  title =        "When Bad Programming Turns Deadly: A look at
                 programming disasters and how bad programming can be
                 deadly",
  journal =      "Interesting Engineering",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "22",
  month =        nov,
  year =         "2018",
  bibdate =      "Fri Nov 23 11:32:14 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://interestingengineering.com/when-bad-programming-turns-deadly",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point arithmetic; Patriot missile;
                 radiological equipment software malfunction",
}


bibtype: misc
filename: fparith.bib
label: Marchese:2018:ACM
author: Sergio Marchese
pages: ??--??
day: 27
month: sep
monthnumber: 9
year: 2018
bibdate: Fri Sep 28 06:12:07 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.09.28 06:12:07 ???
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Sergio Marchese
title:
AI Chips Must Get The Floating-Point Math Right: Formal verification of FPUs is no longer a prerogative of big companies spending big bucks

rawtitle:
{AI} Chips Must Get The Floating-Point Math Right: Formal verification of {FPUs} is no longer a prerogative of big companies spending big bucks

entry:
@Misc{Marchese:2018:ACM,
  author =       "Sergio Marchese",
  title =        "{AI} Chips Must Get The Floating-Point Math Right:
                 Formal verification of {FPUs} is no longer a
                 prerogative of big companies spending big bucks",
  howpublished = "Web site.",
  day =          "27",
  month =        sep,
  year =         "2018",
  bibdate =      "Fri Sep 28 06:12:07 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Mikaitis:2018:AFP
title: Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip
crossref: Tenca:2018:PIS
pages: 37--44
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464785
bibdate: Fri Jan 31 08:05:31 2020
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawtitle: Approximate Fixed-Point Elementary Function Accelerator for the {SpiNNaker-2} Neuromorphic Chip
author:
Mantas Mikaitis and David R. Lester and Delong Shang and Steve Furber and Gengting Liu and Jim Garside and Stefan Scholze and Sebastian Hoppner and Andreas Dixius

abstract:
Neuromorphic chips are used to model biologically inspired Spiking-Neural-Networks (SNNs) where most models are based on differential equations. Equations for most SNN algorithms usually contain variables with one or more ex components. SpiNNaker is a digital neuromorphic chip that has so far been using pre-calculated look-up tables for exponential function. However this approach is limited because the memory requirements grow as more complex neural models are developed. To save already limited memory resources in the next generation SpiNNaker chip, we are including a fast exponential function in the silicon. In this paper we analyse iterative algorithms for elementary functions and show how to build a single hardware accelerator for exp and natural log, for a neuromorphic chip prototype, to be manufactured in a 22 nm FDSOI process. We present the accelerator that has algorithmic level approximation control, allowing it to trade precision for latency and energy efficiency. As an addition to neuromorphic chip application, we provide analysis of a parameterized elementary function unit that can be tailored for other systems with different power, area, accuracy and latency constraints.

keywords:
Adders; algorithmic level approximation control; approximate arithmetic; approximate fixed-point elementary function accelerator; ARITH-25; Biological system modeling; biologically inspired spiking-neural-networks; complex neural models; Computational modeling; Convergence; differential equations; digital neuromorphic chip; energy efficiency; exponential function; fast exponential function; FDSOI process; fixed-point arithmetic; hardware accelerators; iterative algorithms; iterative methods; logarithm function; Mathematical model; memory requirements; memory resources; MPSoC; neural chips; neuromorphic chip prototype; neuromorphic computing; Neuromorphics; next generation SpiNNaker chip; parameterized elementary function unit; pre-calculated look-up tables; single hardware accelerator; size 22.0 nm; SNN algorithms; SpiNNaker-2 neuromorphic chip; SpiNNaker2; table lookup; Table lookup

rawabstract:
Neuromorphic chips are used to model biologically inspired Spiking-Neural-Networks (SNNs) where most models are based on differential equations. Equations for most SNN algorithms usually contain variables with one or more ex components. SpiNNaker is a digital neuromorphic chip that has so far been using pre-calculated look-up tables for exponential function. However this approach is limited because the memory requirements grow as more complex neural models are developed. To save already limited memory resources in the next generation SpiNNaker chip, we are including a fast exponential function in the silicon. In this paper we analyse iterative algorithms for elementary functions and show how to build a single hardware accelerator for exp and natural log, for a neuromorphic chip prototype, to be manufactured in a 22 nm FDSOI process. We present the accelerator that has algorithmic level approximation control, allowing it to trade precision for latency and energy efficiency. As an addition to neuromorphic chip application, we provide analysis of a parameterized elementary function unit that can be tailored for other systems with different power, area, accuracy and latency constraints.

rawauthor:
Mantas Mikaitis and David R. Lester and Delong Shang and Steve Furber and Gengting Liu and Jim Garside and Stefan Scholze and Sebastian H{\"o}ppner and Andreas Dixius

entry:
@InProceedings{Mikaitis:2018:AFP,
  author =       "Mantas Mikaitis and David R. Lester and Delong Shang
                 and Steve Furber and Gengting Liu and Jim Garside and
                 Stefan Scholze and Sebastian H{\"o}ppner and Andreas
                 Dixius",
  title =        "Approximate Fixed-Point Elementary Function
                 Accelerator for the {SpiNNaker-2} Neuromorphic Chip",
  crossref =     "Tenca:2018:PIS",
  pages =        "37--44",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464785",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Neuromorphic chips are used to model biologically
                 inspired Spiking-Neural-Networks (SNNs) where most
                 models are based on differential equations. Equations
                 for most SNN algorithms usually contain variables with
                 one or more ex components. SpiNNaker is a digital
                 neuromorphic chip that has so far been using
                 pre-calculated look-up tables for exponential function.
                 However this approach is limited because the memory
                 requirements grow as more complex neural models are
                 developed. To save already limited memory resources in
                 the next generation SpiNNaker chip, we are including a
                 fast exponential function in the silicon. In this paper
                 we analyse iterative algorithms for elementary
                 functions and show how to build a single hardware
                 accelerator for exp and natural log, for a neuromorphic
                 chip prototype, to be manufactured in a 22 nm FDSOI
                 process. We present the accelerator that has
                 algorithmic level approximation control, allowing it to
                 trade precision for latency and energy efficiency. As
                 an addition to neuromorphic chip application, we
                 provide analysis of a parameterized elementary function
                 unit that can be tailored for other systems with
                 different power, area, accuracy and latency
                 constraints.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; algorithmic level approximation control;
                 approximate arithmetic; approximate fixed-point
                 elementary function accelerator; ARITH-25; Biological
                 system modeling; biologically inspired
                 spiking-neural-networks; complex neural models;
                 Computational modeling; Convergence; differential
                 equations; digital neuromorphic chip; energy
                 efficiency; exponential function; fast exponential
                 function; FDSOI process; fixed-point arithmetic;
                 hardware accelerators; iterative algorithms; iterative
                 methods; logarithm function; Mathematical model; memory
                 requirements; memory resources; MPSoC; neural chips;
                 neuromorphic chip prototype; neuromorphic computing;
                 Neuromorphics; next generation SpiNNaker chip;
                 parameterized elementary function unit; pre-calculated
                 look-up tables; single hardware accelerator; size 22.0
                 nm; SNN algorithms; SpiNNaker-2 neuromorphic chip;
                 SpiNNaker2; table lookup; Table lookup",
}


bibtype: article
filename: fparith.bib
label: Moroz:2018:FCI
title: Fast calculation of inverse square root with the use of magic constant --- analytical approach
journal: j-APPL-MATH-COMP
volume: 316
pages: 245--255
day: 1
month: jan
monthnumber: 1
year: 2018
CODEN: AMHCBQ
DOI: https://doi.org/10.1016/j.amc.2017.08.025
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Tue Oct 10 15:56:03 MDT 2017
bibtimestamp: 2017.10.10 15:56:03 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0096300317305763
fjournal: Applied Mathematics and Computation
keywords: single-precision 32-bit IEEE 754 binary arithmetic
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawtitle: Fast calculation of inverse square root with the use of magic constant --- analytical approach
author:
Leonid V. Moroz and Cezary J. Walczyk and Andriy Hrynchyshyn and Vijay Holimath and Jan L. Cieslinski

bibsource:
https://www.math.utah.edu/pub/tex/bib/applmathcomput2015.bib; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawauthor:
Leonid V. Moroz and Cezary J. Walczyk and Andriy Hrynchyshyn and Vijay Holimath and Jan L. Cie{\'s}li{\'n}ski

entry:
@Article{Moroz:2018:FCI,
  author =       "Leonid V. Moroz and Cezary J. Walczyk and Andriy
                 Hrynchyshyn and Vijay Holimath and Jan L.
                 Cie{\'s}li{\'n}ski",
  title =        "Fast calculation of inverse square root with the use
                 of magic constant --- analytical approach",
  journal =      j-APPL-MATH-COMP,
  volume =       "316",
  number =       "??",
  pages =        "245--255",
  day =          "1",
  month =        jan,
  year =         "2018",
  CODEN =        "AMHCBQ",
  DOI =          "https://doi.org/10.1016/j.amc.2017.08.025",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Tue Oct 10 15:56:03 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/applmathcomput2015.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0096300317305763",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
  keywords =     "single-precision 32-bit IEEE 754 binary arithmetic",
}


bibtype: book
filename: fparith.bib
label: Muller:2018:HFP
title: Handbook of Floating-Point Arithmetic
publisher: pub-BIRKHAUSER
address: pub-BIRKHAUSER:adr
edition: Second
pages: 245--255
year: 2018
DOI: https://doi.org/10.1007/978-3-319-76526-6
ISBN: 3-319-76525-6, 3-319-76526-4 (e-book) OR 3319765256, 3319765264 (ebook)
ISBN13: 978-3-319-76525-9, 978-3-319-76526-6 (e-book) OR 9783319765259, 9783319765266 (ebook)
LCCN: QA76.9.C62
bibdate: Fri Jun 1 06:59:01 MDT 2018
bibsource: fsz3950.oclc.org:210/WorldCat; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.06.01 06:59:01 MDT
acknowledgement: ack-nhfb
rawtitle: Handbook of Floating-Point Arithmetic
author:
Jean-Michel Muller and Nicolas Brunie and Florent de Dinechin and Claude-Pierre Jeannerod and Mioara Joldes and Vincent Lefevre and Guillaume Melquiond and Nathalie Revol and Serge Torres

abstract:
This handbook aims to provide a complete overview of modern floating-point arithmetic. This includes a detailed treatment of the current (IEEE-754) and next (preliminarily called IEEE-754R) standards for floating-point arithmetic.

subject:
Floating-point arithmetic; Handbooks, manuals, etc; Computer arithmetic; COMPUTERS / Computer Literacy; COMPUTERS / Computer Science; COMPUTERS / Data Processing; COMPUTERS / Hardware / General; COMPUTERS / Information Technology; COMPUTERS / Machine Theory; COMPUTERS / Reference.

TOC:
Intro Contents List of Figures List of Tables Preface I Introduction, Basic Definitions, and Standards 1 Introduction 1.1 Some History 1.2 Desirable Properties 1.3 Some Strange Behaviors 1.3.1 Some famous bugs 1.3.2 Difficult problems 1.3.2.1 A sequence that seems to converge to a wrong limit 1.3.2.2 The Chaotic Bank Society 1.3.2.3 Rump's example 2 Definitions and Basic Notions 2.1 Floating-Point Numbers 2.1.1 Main definitions 2.1.2 Normalized representations, normal and subnormal numbers 2.1.3 A note on underflow 2.1.4 Special floating-point data 2.2 Rounding2.2.1 Rounding functions2.2.2 Useful properties 2.3 Tools for Manipulating Floating-Point Errors 2.3.1 Relative error due to rounding 2.3.2 The ulp function 2.3.3 Link between errors in ulps and relative errors 2.3.3.1 Converting from errors in ulps to relative errors 2.3.3.2 Converting from relative errors to errors in ulps 2.3.3.3 Loss of information during these conversions 2.3.4 An example: iterated products 2.4 The Fused Multiply-Add (FMA) Instruction 2.5 Exceptions 2.6 Lost and Preserved Properties of Real Arithmetic 2.7 Note on the Choice of the Radix2.7.1 Representation errors2.7.2 A case for radix 10 2.8 Reproducibility 3 Floating-Point Formats and Environment 3.1 The IEEE 754-2008 Standard 3.1.1 Formats 3.1.1.1 Binary interchange format encodings 3.1.1.2 Decimal interchange format encodings 3.1.1.3 Larger formats 3.1.1.4 Extended and extendable precisions 3.1.1.5 Little-endian, big-endian 3.1.2 Attributes and rounding 3.1.2.1 Rounding direction attributes 3.1.2.2 Alternate exception-handling attributes 3.1.2.3 Preferred width attributes 3.1.2.4 Value-changing optimization attributes 3.1.2.5 Reproducibility attributes3.1.3 Operations specified by the standard3.1.3.1 Arithmetic operations and square root 3.1.3.2 Remainders 3.1.3.3 Preferred exponent for arithmetic operations in the decimal format 3.1.3.4 scaleB and logB 3.1.3.5 Miscellaneous 3.1.4 Comparisons 3.1.5 Conversions to/from string representations 3.1.6 Default exception handling 3.1.6.1 Invalid operation 3.1.6.2 Division by zero 3.1.6.3 Overflow 3.1.6.4 Underflow 3.1.6.5 Inexact 3.1.7 Special values 3.1.7.1 NaN: Not a Number 3.1.7.2 Arithmetic of infinities and zeros 3.1.8 Recommended functions3.2 On the Possible Hidden Use of a Higher Internal Precision3.3 Revision of the IEEE 754-2008 Standard 3.4 Floating-Point Hardware in Current Processors 3.4.1 The common hardware denominator 3.4.2 Fused multiply-add 3.4.3 Extended precision and 128-bit formats 3.4.4 Rounding and precision control 3.4.5 SIMD instructions 3.4.6 Binary16 (half-precision) support 3.4.7 Decimal arithmetic 3.4.8 The legacy x87 processor 3.5 Floating-Point Hardware in Recent Graphics Processing Units 3.6 IEEE Support in Programming Languages 3.7 Checking the Environment 3.7.1 MACHAR 3.7.2 Paranoia ldots Basic Properties and Algorithms Enhanced Floating-Point Sums, Dot Products, and Polynomial Values Languages and Compilers Algorithms for the Basic Operations Hardware Implementation of Floating-Point Arithmetic Software Implementation of Floating-Point Arithmetic Evaluating Floating-Point Elementary Functions Complex Numbers Interval Arithmetic Verifying Floating-Point Algorithms Extending the Precision

rawabstract:
This handbook aims to provide a complete overview of modern floating-point arithmetic. This includes a detailed treatment of the current (IEEE-754) and next (preliminarily called IEEE-754R) standards for floating-point arithmetic.

rawauthor:
Jean-Michel Muller and Nicolas Brunie and Florent de Dinechin and Claude-Pierre Jeannerod and Mioara Joldes and Vincent Lef{\`e}vre and Guillaume Melquiond and Nathalie Revol and Serge Torres

shortTOC:
Introduction / 3--14 Definitions and Basic Notions / 15--45 Floating-Point Formats and Environment / 47--93 Basic Properties and Algorithms / 97--162 Enhanced Floating-Point Sums, Dot Products, and Polynomial Values / 163--192 Languages and Compilers / 193--230 Algorithms for the Basic Operations / 233--266 Hardware Implementation of Floating-Point Arithmetic / 267--320 Software Implementation of Floating-Point Arithmetic / 321--374 Evaluating Floating-Point Elementary Functions / 375--433 Complex Numbers / 437--452 Interval Arithmetic / 453--477 Verifying Floating-Point Algorithms / 479--511 Extending the Precision / 513--552

rawshortTOC:
Introduction / 3--14 \\ Definitions and Basic Notions / 15--45 \\ Floating-Point Formats and Environment / 47--93 \\ Basic Properties and Algorithms / 97--162 \\ Enhanced Floating-Point Sums, Dot Products, and Polynomial Values / 163--192 \\ Languages and Compilers / 193--230 \\ Algorithms for the Basic Operations / 233--266 \\ Hardware Implementation of Floating-Point Arithmetic / 267--320 \\ Software Implementation of Floating-Point Arithmetic / 321--374 \\ Evaluating Floating-Point Elementary Functions / 375--433 \\ Complex Numbers / 437--452 \\ Interval Arithmetic / 453--477 \\ Verifying Floating-Point Algorithms / 479--511 \\ Extending the Precision / 513--552

rawTOC:
Intro \\ Contents \\ List of Figures \\ List of Tables \\ Preface \\ I Introduction, Basic Definitions, and Standards \\ 1 Introduction \\ 1.1 Some History \\ 1.2 Desirable Properties \\ 1.3 Some Strange Behaviors \\ 1.3.1 Some famous bugs \\ 1.3.2 Difficult problems \\ 1.3.2.1 A sequence that seems to converge to a wrong limit \\ 1.3.2.2 The Chaotic Bank Society \\ 1.3.2.3 Rump's example \\ 2 Definitions and Basic Notions \\ 2.1 Floating-Point Numbers \\ 2.1.1 Main definitions \\ 2.1.2 Normalized representations, normal and subnormal numbers \\ 2.1.3 A note on underflow \\ 2.1.4 Special floating-point data \\ 2.2 Rounding2.2.1 Rounding functions2.2.2 Useful properties \\ 2.3 Tools for Manipulating Floating-Point Errors \\ 2.3.1 Relative error due to rounding \\ 2.3.2 The ulp function \\ 2.3.3 Link between errors in ulps and relative errors \\ 2.3.3.1 Converting from errors in ulps to relative errors \\ 2.3.3.2 Converting from relative errors to errors in ulps \\ 2.3.3.3 Loss of information during these conversions \\ 2.3.4 An example: iterated products \\ 2.4 The Fused Multiply-Add (FMA) Instruction \\ 2.5 Exceptions \\ 2.6 Lost and Preserved Properties of Real Arithmetic \\ 2.7 Note on the Choice of the Radix2.7.1 Representation errors2.7.2 A case for radix 10 \\ 2.8 Reproducibility \\ 3 Floating-Point Formats and Environment \\ 3.1 The IEEE 754-2008 Standard \\ 3.1.1 Formats \\ 3.1.1.1 Binary interchange format encodings \\ 3.1.1.2 Decimal interchange format encodings \\ 3.1.1.3 Larger formats \\ 3.1.1.4 Extended and extendable precisions \\ 3.1.1.5 Little-endian, big-endian \\ 3.1.2 Attributes and rounding \\ 3.1.2.1 Rounding direction attributes \\ 3.1.2.2 Alternate exception-handling attributes \\ 3.1.2.3 Preferred width attributes \\ 3.1.2.4 Value-changing optimization attributes \\ 3.1.2.5 Reproducibility attributes3.1.3 Operations specified by the standard3.1.3.1 Arithmetic operations and square root \\ 3.1.3.2 Remainders \\ 3.1.3.3 Preferred exponent for arithmetic operations in the decimal format \\ 3.1.3.4 scaleB and logB \\ 3.1.3.5 Miscellaneous \\ 3.1.4 Comparisons \\ 3.1.5 Conversions to/from string representations \\ 3.1.6 Default exception handling \\ 3.1.6.1 Invalid operation \\ 3.1.6.2 Division by zero \\ 3.1.6.3 Overflow \\ 3.1.6.4 Underflow \\ 3.1.6.5 Inexact \\ 3.1.7 Special values \\ 3.1.7.1 NaN: Not a Number \\ 3.1.7.2 Arithmetic of infinities and zeros \\ 3.1.8 Recommended functions3.2 On the Possible Hidden Use of a Higher Internal Precision3.3 Revision of the IEEE 754-2008 Standard \\ 3.4 Floating-Point Hardware in Current Processors \\ 3.4.1 The common hardware denominator \\ 3.4.2 Fused multiply-add \\ 3.4.3 Extended precision and 128-bit formats \\ 3.4.4 Rounding and precision control \\ 3.4.5 SIMD instructions \\ 3.4.6 Binary16 (half-precision) support \\ 3.4.7 Decimal arithmetic \\ 3.4.8 The legacy x87 processor \\ 3.5 Floating-Point Hardware in Recent Graphics Processing Units \\ 3.6 IEEE Support in Programming Languages \\ 3.7 Checking the Environment \\ 3.7.1 MACHAR \\ 3.7.2 Paranoia \\ \ldots{} \\ Basic Properties and Algorithms \\ Enhanced Floating-Point Sums, Dot Products, and Polynomial Values \\ Languages and Compilers \\ Algorithms for the Basic Operations \\ Hardware Implementation of Floating-Point Arithmetic \\ Software Implementation of Floating-Point Arithmetic \\ Evaluating Floating-Point Elementary Functions \\ Complex Numbers \\ Interval Arithmetic \\ Verifying Floating-Point Algorithms \\ Extending the Precision

entry:
@Book{Muller:2018:HFP,
  author =       "Jean-Michel Muller and Nicolas Brunie and Florent de
                 Dinechin and Claude-Pierre Jeannerod and Mioara Joldes
                 and Vincent Lef{\`e}vre and Guillaume Melquiond and
                 Nathalie Revol and Serge Torres",
  title =        "Handbook of Floating-Point Arithmetic",
  publisher =    pub-BIRKHAUSER,
  address =      pub-BIRKHAUSER:adr,
  edition =      "Second",
  year =         "2018",
  DOI =          "https://doi.org/10.1007/978-3-319-76526-6",
  ISBN =         "3-319-76525-6, 3-319-76526-4 (e-book)",
  ISBN-13 =      "978-3-319-76525-9, 978-3-319-76526-6 (e-book)",
  LCCN =         "QA76.9.C62",
  bibdate =      "Fri Jun 1 06:59:01 MDT 2018",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This handbook aims to provide a complete overview of
                 modern floating-point arithmetic. This includes a
                 detailed treatment of the current (IEEE-754) and next
                 (preliminarily called IEEE-754R) standards for
                 floating-point arithmetic.",
  acknowledgement = ack-nhfb,
  shorttableofcontents = "Introduction / 3--14 \\
                 Definitions and Basic Notions / 15--45 \\
                 Floating-Point Formats and Environment / 47--93 \\
                 Basic Properties and Algorithms / 97--162 \\
                 Enhanced Floating-Point Sums, Dot Products, and
                 Polynomial Values / 163--192 \\
                 Languages and Compilers / 193--230 \\
                 Algorithms for the Basic Operations / 233--266 \\
                 Hardware Implementation of Floating-Point Arithmetic /
                 267--320 \\
                 Software Implementation of Floating-Point Arithmetic /
                 321--374 \\
                 Evaluating Floating-Point Elementary Functions /
                 375--433 \\
                 Complex Numbers / 437--452 \\
                 Interval Arithmetic / 453--477 \\
                 Verifying Floating-Point Algorithms / 479--511 \\
                 Extending the Precision / 513--552",
  subject =      "Floating-point arithmetic; Handbooks, manuals, etc;
                 Computer arithmetic; COMPUTERS / Computer Literacy;
                 COMPUTERS / Computer Science; COMPUTERS / Data
                 Processing; COMPUTERS / Hardware / General; COMPUTERS /
                 Information Technology; COMPUTERS / Machine Theory;
                 COMPUTERS / Reference.",
  tableofcontents = "Intro \\
                 Contents \\
                 List of Figures \\
                 List of Tables \\
                 Preface \\
                 I Introduction, Basic Definitions, and Standards \\
                 1 Introduction \\
                 1.1 Some History \\
                 1.2 Desirable Properties \\
                 1.3 Some Strange Behaviors \\
                 1.3.1 Some famous bugs \\
                 1.3.2 Difficult problems \\
                 1.3.2.1 A sequence that seems to converge to a wrong
                 limit \\
                 1.3.2.2 The Chaotic Bank Society \\
                 1.3.2.3 Rump's example \\
                 2 Definitions and Basic Notions \\
                 2.1 Floating-Point Numbers \\
                 2.1.1 Main definitions \\
                 2.1.2 Normalized representations, normal and subnormal
                 numbers \\
                 2.1.3 A note on underflow \\
                 2.1.4 Special floating-point data \\
                 2.2 Rounding2.2.1 Rounding functions2.2.2 Useful
                 properties \\
                 2.3 Tools for Manipulating Floating-Point Errors \\
                 2.3.1 Relative error due to rounding \\
                 2.3.2 The ulp function \\
                 2.3.3 Link between errors in ulps and relative errors
                 \\
                 2.3.3.1 Converting from errors in ulps to relative
                 errors \\
                 2.3.3.2 Converting from relative errors to errors in
                 ulps \\
                 2.3.3.3 Loss of information during these conversions
                 \\
                 2.3.4 An example: iterated products \\
                 2.4 The Fused Multiply-Add (FMA) Instruction \\
                 2.5 Exceptions \\
                 2.6 Lost and Preserved Properties of Real Arithmetic
                 \\
                 2.7 Note on the Choice of the Radix2.7.1 Representation
                 errors2.7.2 A case for radix 10 \\
                 2.8 Reproducibility \\
                 3 Floating-Point Formats and Environment \\
                 3.1 The IEEE 754-2008 Standard \\
                 3.1.1 Formats \\
                 3.1.1.1 Binary interchange format encodings \\
                 3.1.1.2 Decimal interchange format encodings \\
                 3.1.1.3 Larger formats \\
                 3.1.1.4 Extended and extendable precisions \\
                 3.1.1.5 Little-endian, big-endian \\
                 3.1.2 Attributes and rounding \\
                 3.1.2.1 Rounding direction attributes \\
                 3.1.2.2 Alternate exception-handling attributes \\
                 3.1.2.3 Preferred width attributes \\
                 3.1.2.4 Value-changing optimization attributes \\
                 3.1.2.5 Reproducibility attributes3.1.3 Operations
                 specified by the standard3.1.3.1 Arithmetic operations
                 and square root \\
                 3.1.3.2 Remainders \\
                 3.1.3.3 Preferred exponent for arithmetic operations in
                 the decimal format \\
                 3.1.3.4 scaleB and logB \\
                 3.1.3.5 Miscellaneous \\
                 3.1.4 Comparisons \\
                 3.1.5 Conversions to/from string representations \\
                 3.1.6 Default exception handling \\
                 3.1.6.1 Invalid operation \\
                 3.1.6.2 Division by zero \\
                 3.1.6.3 Overflow \\
                 3.1.6.4 Underflow \\
                 3.1.6.5 Inexact \\
                 3.1.7 Special values \\
                 3.1.7.1 NaN: Not a Number \\
                 3.1.7.2 Arithmetic of infinities and zeros \\
                 3.1.8 Recommended functions3.2 On the Possible Hidden
                 Use of a Higher Internal Precision3.3 Revision of the
                 IEEE 754-2008 Standard \\
                 3.4 Floating-Point Hardware in Current Processors \\
                 3.4.1 The common hardware denominator \\
                 3.4.2 Fused multiply-add \\
                 3.4.3 Extended precision and 128-bit formats \\
                 3.4.4 Rounding and precision control \\
                 3.4.5 SIMD instructions \\
                 3.4.6 Binary16 (half-precision) support \\
                 3.4.7 Decimal arithmetic \\
                 3.4.8 The legacy x87 processor \\
                 3.5 Floating-Point Hardware in Recent Graphics
                 Processing Units \\
                 3.6 IEEE Support in Programming Languages \\
                 3.7 Checking the Environment \\
                 3.7.1 MACHAR \\
                 3.7.2 Paranoia \\
                 \ldots{} \\
                 Basic Properties and Algorithms \\
                 Enhanced Floating-Point Sums, Dot Products, and
                 Polynomial Values \\
                 Languages and Compilers \\
                 Algorithms for the Basic Operations \\
                 Hardware Implementation of Floating-Point Arithmetic
                 \\
                 Software Implementation of Floating-Point Arithmetic
                 \\
                 Evaluating Floating-Point Elementary Functions \\
                 Complex Numbers \\
                 Interval Arithmetic \\
                 Verifying Floating-Point Algorithms \\
                 Extending the Precision",
}


bibtype: article
filename: fparith.bib
label: Munoz-Coreas:2018:CQO
author: Edgard Munoz-Coreas and Himanshu Thapliyal
title: T-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm
journal: j-JETC
volume: 14
number: 3
pages: 36:1--36:15
month: oct
monthnumber: 10
year: 2018
DOI: https://doi.org/10.1145/3264816
ISSN: 1550-4832 (print), 1550-4840 (electronic) OR 15504832 (print), 15504840 (electronic)
ISSNL: 1550-4832 OR 15504832
bibdate: Thu Nov 1 16:44:41 MDT 2018
bibtimestamp: 2018.11.01 16:44:41 MDT
fjournal: ACM Journal on Emerging Technologies in Computing Systems (JETC)
acknowledgement: ack-nhfb
articleno: 36
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J967
rawauthor: Edgard Mu{\~n}oz-Coreas and Himanshu Thapliyal
rawtitle: {T}-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jetc.bib

abstract:
Quantum circuits for basic mathematical functions such as the square root are required to implement scientific computing algorithms on quantum computers. Quantum circuits that are based on Clifford+T gates can easily be made fault tolerant, but the T gate is very costly to implement. As a result, reducing T-count has become an important optimization goal. Further, quantum circuits with many qubits are difficult to realize, making designs that save qubits and produce no garbage outputs desirable. In this work, we present a T-count optimized quantum square root circuit with only $ 2 s n + 1 $ qubits and no garbage output. To make a fair comparison against existing work, the Bennett's garbage removal scheme is used to remove garbage output from existing works. We determined that our proposed design achieves an average T-count savings of 43.44%, 98.95%, 41.06%, and 20.28% as well as qubit savings of 85.46%, 95.16%, 90.59%, and 86.77% compared to existing works.

rawabstract:
Quantum circuits for basic mathematical functions such as the square root are required to implement scientific computing algorithms on quantum computers. Quantum circuits that are based on Clifford+T gates can easily be made fault tolerant, but the T gate is very costly to implement. As a result, reducing T-count has become an important optimization goal. Further, quantum circuits with many qubits are difficult to realize, making designs that save qubits and produce no garbage outputs desirable. In this work, we present a T-count optimized quantum square root circuit with only $ 2 s n + 1 $ qubits and no garbage output. To make a fair comparison against existing work, the Bennett's garbage removal scheme is used to remove garbage output from existing works. We determined that our proposed design achieves an average T-count savings of 43.44\%, 98.95\%, 41.06\%, and 20.28\% as well as qubit savings of 85.46\%, 95.16\%, 90.59\%, and 86.77\% compared to existing works.

entry:
@Article{Munoz-Coreas:2018:CQO,
  author =       "Edgard Mu{\~n}oz-Coreas and Himanshu Thapliyal",
  title =        "{T}-count and Qubit Optimized Quantum Circuit Design
                 of the Non-Restoring Square Root Algorithm",
  journal =      j-JETC,
  volume =       "14",
  number =       "3",
  pages =        "36:1--36:15",
  month =        oct,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3264816",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Nov 1 16:44:41 MDT 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Quantum circuits for basic mathematical functions such
                 as the square root are required to implement scientific
                 computing algorithms on quantum computers. Quantum
                 circuits that are based on Clifford+T gates can easily
                 be made fault tolerant, but the T gate is very costly
                 to implement. As a result, reducing T-count has become
                 an important optimization goal. Further, quantum
                 circuits with many qubits are difficult to realize,
                 making designs that save qubits and produce no garbage
                 outputs desirable. In this work, we present a T-count
                 optimized quantum square root circuit with only $ 2 s n
                 + 1 $ qubits and no garbage output. To make a fair
                 comparison against existing work, the Bennett's garbage
                 removal scheme is used to remove garbage output from
                 existing works. We determined that our proposed design
                 achieves an average T-count savings of 43.44\%,
                 98.95\%, 41.06\%, and 20.28\% as well as qubit savings
                 of 85.46\%, 95.16\%, 90.59\%, and 86.77\% compared to
                 existing works.",
  acknowledgement = ack-nhfb,
  articleno =    "36",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}


bibtype: inproceedings
filename: fparith.bib
label: Nannarelli:2018:TFP
author: Alberto Nannarelli
title: Tunable Floating-Point for Energy Efficient Accelerators
crossref: Tenca:2018:PIS
pages: 29--36
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464797
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Alberto Nannarelli
rawtitle: Tunable Floating-Point for Energy Efficient Accelerators
abstract:
In this work, we address the design of an on-chip accelerator for Machine Learning and other computation-demanding applications with a Tunable Floating-Point (TFP) precision. The precision can be chosen for a single operation by selecting a specific number of bits for significand and exponent in the floating-point representation. By tuning the precision of a given algorithm to the minimum precision achieving an acceptable target error, we can make the computation more power efficient. We focus on floating-point multiplication, which is the most power demanding arithmetic operation.

keywords:
Adders; ARITH-25; computation-demanding applications; Decoding; Dynamic range; electronic engineering computing; energy efficient accelerators; floating point arithmetic; floating-point multiplication; floating-point representation; Hardware; learning (artificial intelligence); Machine Learning; Machine learning; on-chip accelerator; Standards; System-on-chip; TFP precision; Tunable Floating-Point precision

rawabstract:
In this work, we address the design of an on-chip accelerator for Machine Learning and other computation-demanding applications with a Tunable Floating-Point (TFP) precision. The precision can be chosen for a single operation by selecting a specific number of bits for significand and exponent in the floating-point representation. By tuning the precision of a given algorithm to the minimum precision achieving an acceptable target error, we can make the computation more power efficient. We focus on floating-point multiplication, which is the most power demanding arithmetic operation.

entry:
@InProceedings{Nannarelli:2018:TFP,
  author =       "Alberto Nannarelli",
  title =        "Tunable Floating-Point for Energy Efficient
                 Accelerators",
  crossref =     "Tenca:2018:PIS",
  pages =        "29--36",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464797",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this work, we address the design of an on-chip
                 accelerator for Machine Learning and other
                 computation-demanding applications with a Tunable
                 Floating-Point (TFP) precision. The precision can be
                 chosen for a single operation by selecting a specific
                 number of bits for significand and exponent in the
                 floating-point representation. By tuning the precision
                 of a given algorithm to the minimum precision achieving
                 an acceptable target error, we can make the computation
                 more power efficient. We focus on floating-point
                 multiplication, which is the most power demanding
                 arithmetic operation.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; ARITH-25; computation-demanding applications;
                 Decoding; Dynamic range; electronic engineering
                 computing; energy efficient accelerators; floating
                 point arithmetic; floating-point multiplication;
                 floating-point representation; Hardware; learning
                 (artificial intelligence); Machine Learning; Machine
                 learning; on-chip accelerator; Standards;
                 System-on-chip; TFP precision; Tunable Floating-Point
                 precision",
}


bibtype: article
filename: fparith.bib
label: Numahata:2018:RAS
author: Dai Numahata and Hiroshi Sekigawa
title: Robust algorithms for sparse interpolation of multivariate polynomials
journal: j-ACM-COMM-COMP-ALGEBRA
volume: 52
number: 4
pages: 145--147
month: dec
monthnumber: 12
year: 2018
DOI: https://doi.org/10.1145/3338637.3338648
ISSN: 1932-2232 (print), 1932-2240 (electronic) OR 19322232 (print), 19322240 (electronic)
ISSNL: 1932-2232 OR 19322232
bibdate: Wed Oct 23 07:34:18 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigsam.bib
bibtimestamp: 2019.10.23 07:34:18 MDT
fjournal: ACM Communications in Computer Algebra
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J1000
rawauthor: Dai Numahata and Hiroshi Sekigawa
rawtitle: Robust algorithms for sparse interpolation of multivariate polynomials
abstract:
We consider the problem of symbolic-numeric sparse interpolation of multivariate polynomials. The problem is to find the coefficients and the exponents of a given black-box polynomial $ f(x_1, ldots , x_n) = sum _j = 1^t c_j x_1^d_j, 1 ldots x_n^d_j, n in mathbb C[x_1, ldots , x_n] (c_j neq 0) $ by evaluating the value of $ f(x_1, ldots , x_n) $ at any point in $ mathbb C^n $ in floating-point arithmetic and by using the conditions of the input.

rawabstract:
We consider the problem of symbolic-numeric sparse interpolation of multivariate polynomials. The problem is to find the coefficients and the exponents of a given black-box polynomial $ f(x_1, \ldots, x_n) = \sum_{j = 1}^t c_j x_1^{d_{j, 1}} \ldots {} x_n^{d_{j, n}} \in \mathbb {C}[x_1, \ldots, x_n] (c_j \neq 0) $ by evaluating the value of $ f(x_1, \ldots, x_n) $ at any point in $ \mathbb {C}^n $ in floating-point arithmetic and by using the conditions of the input.

entry:
@Article{Numahata:2018:RAS,
  author =       "Dai Numahata and Hiroshi Sekigawa",
  title =        "Robust algorithms for sparse interpolation of
                 multivariate polynomials",
  journal =      j-ACM-COMM-COMP-ALGEBRA,
  volume =       "52",
  number =       "4",
  pages =        "145--147",
  month =        dec,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3338637.3338648",
  ISSN =         "1932-2232 (print), 1932-2240 (electronic)",
  ISSN-L =       "1932-2232",
  bibdate =      "Wed Oct 23 07:34:18 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigsam.bib",
  abstract =     "We consider the problem of symbolic-numeric sparse
                 interpolation of multivariate polynomials. The problem
                 is to find the coefficients and the exponents of a
                 given black-box polynomial $ f(x_1, \ldots, x_n) =
                 \sum_{j = 1}^t c_j x_1^{d_{j, 1}} \ldots {} x_n^{d_{j,
                 n}} \in \mathbb {C}[x_1, \ldots, x_n] (c_j \neq 0) $ by
                 evaluating the value of $ f(x_1, \ldots, x_n) $ at any
                 point in $ \mathbb {C}^n $ in floating-point arithmetic
                 and by using the conditions of the input.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Communications in Computer Algebra",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J1000",
}


bibtype: article
filename: fparith.bib
label: Oliveira:2018:MLB
author: Thomaz Oliveira and Julio Lopez and Francisco Rodriguez-Henriquez
title: The Montgomery ladder on binary elliptic curves
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 241--258
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0163-8
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
URL: http://link.springer.com/article/10.1007/s13389-017-0163-8
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Thomaz Oliveira and Julio L{\'o}pez and Francisco Rodr{\'{\i}}guez-Henr{\'{\i}}quez
rawtitle: The {Montgomery} ladder on binary elliptic curves
entry:
@Article{Oliveira:2018:MLB,
  author =       "Thomaz Oliveira and Julio L{\'o}pez and Francisco
                 Rodr{\'{\i}}guez-Henr{\'{\i}}quez",
  title =        "The {Montgomery} ladder on binary elliptic curves",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "241--258",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0163-8",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0163-8",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: inproceedings
filename: fparith.bib
label: Podobas:2018:HIP
author: Artur Podobas and Satoshi Matsuoka
editor: IEEE
booktitle: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
title: Hardware Implementation of POSITs and Their Application in FPGAs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 138--145
year: 2018
DOI: https://doi.org/10.1109/IPDPSW.2018.00029
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Artur Podobas and Satoshi Matsuoka
rawbooktitle: {2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}
raweditor: {IEEE}
rawtitle: Hardware Implementation of {POSITs} and Their Application in {FPGAs}
entry:
@InProceedings{Podobas:2018:HIP,
  author =       "Artur Podobas and Satoshi Matsuoka",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE International Parallel and Distributed
                 Processing Symposium Workshops (IPDPSW)}",
  title =        "Hardware Implementation of {POSITs} and Their
                 Application in {FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "138--145",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/IPDPSW.2018.00029",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Popescu:2018:FPN
author: Valentina Popescu and Marcel Nassar and Xin Wang and Evren Tumer and Tristania Webb
title: Flexpoint: Predictive Numerics for Deep Learning
crossref: Tenca:2018:PIS
pages: 1--4
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464801
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Valentina Popescu and Marcel Nassar and Xin Wang and Evren Tumer and Tristania Webb
rawtitle: {Flexpoint}: Predictive Numerics for Deep Learning
abstract:
Deep learning has been undergoing rapid growth in recent years thanks to its state-of-the-art performance across a wide range of real-world applications. Traditionally neural networks were trained in IEEE-754 binary64 or binary32 format, a common practice in general scientific computing. However, the unique computational requirements of deep neural network training workloads allow for much more efficient and inexpensive alternatives, unleashing a new wave of numerical innovations powering specialized computing hardware. We previously presented Flexpoint, a blocked fixed-point data type combined with a novel predictive exponent management algorithm designed to support training of deep networks without modifications, aiming at a seamless replacement of the binary32 widely in practice today. We showed that Flexpoint with 16-bit mantissa and 5-bit shared exponent (flex16+S) achieved numerical parity to binary32 in training a number of convolutional neural networks. In the current paper we review the continuing trend of predictive numerics enhancing deep neural network training in specialized computing devices such as the Intel Nervana Neural Network Processor.

keywords:
ARITH-25; blocked fixed-point data type; convolution; convolutional neural networks; deep learning; Deep Learning; deep neural network training; feedforward neural nets; Flexpoint; floating point arithmetic; general scientific computing; Hardware; learning (artificial intelligence); Machine learning; Market research; Neural networks; Neural Networks; Prediction algorithms; predictive exponent management algorithm; Tensile stress; Training

rawabstract:
Deep learning has been undergoing rapid growth in recent years thanks to its state-of-the-art performance across a wide range of real-world applications. Traditionally neural networks were trained in IEEE-754 binary64 or binary32 format, a common practice in general scientific computing. However, the unique computational requirements of deep neural network training workloads allow for much more efficient and inexpensive alternatives, unleashing a new wave of numerical innovations powering specialized computing hardware. We previously presented Flexpoint, a blocked fixed-point data type combined with a novel predictive exponent management algorithm designed to support training of deep networks without modifications, aiming at a seamless replacement of the binary32 widely in practice today. We showed that Flexpoint with 16-bit mantissa and 5-bit shared exponent (flex16+S) achieved numerical parity to binary32 in training a number of convolutional neural networks. In the current paper we review the continuing trend of predictive numerics enhancing deep neural network training in specialized computing devices such as the Intel Nervana Neural Network Processor.

entry:
@InProceedings{Popescu:2018:FPN,
  author =       "Valentina Popescu and Marcel Nassar and Xin Wang and
                 Evren Tumer and Tristania Webb",
  title =        "{Flexpoint}: Predictive Numerics for Deep Learning",
  crossref =     "Tenca:2018:PIS",
  pages =        "1--4",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464801",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Deep learning has been undergoing rapid growth in
                 recent years thanks to its state-of-the-art performance
                 across a wide range of real-world applications.
                 Traditionally neural networks were trained in IEEE-754
                 binary64 or binary32 format, a common practice in
                 general scientific computing. However, the unique
                 computational requirements of deep neural network
                 training workloads allow for much more efficient and
                 inexpensive alternatives, unleashing a new wave of
                 numerical innovations powering specialized computing
                 hardware. We previously presented Flexpoint, a blocked
                 fixed-point data type combined with a novel predictive
                 exponent management algorithm designed to support
                 training of deep networks without modifications, aiming
                 at a seamless replacement of the binary32 widely in
                 practice today. We showed that Flexpoint with 16-bit
                 mantissa and 5-bit shared exponent (flex16+S) achieved
                 numerical parity to binary32 in training a number of
                 convolutional neural networks. In the current paper we
                 review the continuing trend of predictive numerics
                 enhancing deep neural network training in specialized
                 computing devices such as the Intel Nervana Neural
                 Network Processor.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-25; blocked fixed-point data type; convolution;
                 convolutional neural networks; deep learning; Deep
                 Learning; deep neural network training; feedforward
                 neural nets; Flexpoint; floating point arithmetic;
                 general scientific computing; Hardware; learning
                 (artificial intelligence); Machine learning; Market
                 research; Neural networks; Neural Networks; Prediction
                 algorithms; predictive exponent management algorithm;
                 Tensile stress; Training",
}


bibtype: article
filename: fparith.bib
label: Radford:2018:FIF
author: Peter Radford
title: A ``Feature'' of IBM 360 Floating Point
journal: Resurrection: The Journal of the Computer Conservation Society
number: 82
pages: ??--??
month: Summer
year: 2018
ISSN: 0958-7403 OR 09587403
ISSNL: 0958-7403 OR 09587403
bibdate: Mon Jul 27 18:19:06 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.07.27 18:19:06 ???
URL: https://computerconservationsociety.org/resurrection/res82.htm#f
acknowledgement: ack-nhfb
rawauthor: Peter Radford
rawtitle: A {``Feature''} of {IBM 360} Floating Point
remark:
The short article discusses the impact of hexadecimal normalization on representation of decimal input values, and ends with the statement: ``32-bit floating point remains an elephant trap for programmers to this day.''.

entry:
@Article{Radford:2018:FIF,
  author =       "Peter Radford",
  title =        "A {``Feature''} of {IBM 360} Floating Point",
  journal =      "Resurrection: The Journal of the Computer Conservation
                 Society",
  volume =       "??",
  number =       "82",
  pages =        "??--??",
  month =        "Summer",
  year =         "2018",
  ISSN =         "0958-7403",
  ISSN-L =       "0958-7403",
  bibdate =      "Mon Jul 27 18:19:06 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://computerconservationsociety.org/resurrection/res82.htm#f",
  acknowledgement = ack-nhfb,
  remark =       "The short article discusses the impact of hexadecimal
                 normalization on representation of decimal input
                 values, and ends with the statement: ``32-bit floating
                 point remains an elephant trap for programmers to this
                 day.''.",
}


bibtype: inproceedings
filename: fparith.bib
label: Ram:2018:FVF
author: Ravi Ram and Adam Elkins and Adnan Pratama and Sasa Stamenkovic and Sven Beyer and Sergio Marchese
booktitle: Proceedings of DVCon US 2018
title: Formal Verification of Floating-Point Hardware with Assertion-Based VIP
pages: 1--9
day: 5
month: jun
monthnumber: 6
year: 2018
bibdate: Fri Sep 28 06:20:43 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.09.28 06:20:43 ???
acknowledgement: ack-nhfb
rawauthor: Ravi Ram and Adam Elkins and Adnan Pratama and Sasa Stamenkovic and Sven Beyer and Sergio Marchese
rawbooktitle: Proceedings of {DVCon US 2018}
rawtitle: Formal Verification of Floating-Point Hardware with Assertion-Based {VIP}
URL:
https://www.onespin.com/fileadmin/user_upload/pdf/whitepapers/Formal_Verification_of_Floating_Point_Hardware.pdf

abstract:
Hardware for integer or fixed-point arithmetic is relatively simple to design, at least at the register-transfer level. If the range of values and precision that can be represented with these formats is not sufficient for the target application, floating-point hardware might be required. Unfortunately, floating-point units are complex to design, and notoriously challenging to verify. Since the famous 1994 Intel Pentium bug, many companies have investigated and successfully applied formal methods to this task. However, solutions often rely on a mix of the following: hard-to-use formal tools; highly specialized engineering skills; availability of a suitable executable model of the hardware; and significant, design-specific engineering effort. In this paper, we present an alternative floating-point hardware verification approach based on a reusable, IEEE 754 compliant SystemVerilog arithmetic library. While not addressing all verification challenges, this method enables engineers to set up a formal testbench and uncover deep corner-case bugs with minimal effort. Results from industrial applications are reported.

rawabstract:
Hardware for integer or fixed-point arithmetic is relatively simple to design, at least at the register-transfer level. If the range of values and precision that can be represented with these formats is not sufficient for the target application, floating-point hardware might be required. Unfortunately, floating-point units are complex to design, and notoriously challenging to verify. Since the famous 1994 Intel Pentium bug, many companies have investigated and successfully applied formal methods to this task. However, solutions often rely on a mix of the following: hard-to-use formal tools; highly specialized engineering skills; availability of a suitable executable model of the hardware; and significant, design-specific engineering effort. In this paper, we present an alternative floating-point hardware verification approach based on a reusable, IEEE 754 compliant SystemVerilog arithmetic library. While not addressing all verification challenges, this method enables engineers to set up a formal testbench and uncover deep corner-case bugs with minimal effort. Results from industrial applications are reported.

entry:
@InProceedings{Ram:2018:FVF,
  author =       "Ravi Ram and Adam Elkins and Adnan Pratama and Sasa
                 Stamenkovic and Sven Beyer and Sergio Marchese",
  editor =       "????",
  booktitle =    "Proceedings of {DVCon US 2018}",
  title =        "Formal Verification of Floating-Point Hardware with
                 Assertion-Based {VIP}",
  publisher =    "????",
  address =      "????",
  pages =        "1--9",
  day =          "5",
  month =        jun,
  year =         "2018",
  bibdate =      "Fri Sep 28 06:20:43 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.onespin.com/fileadmin/user_upload/pdf/whitepapers/Formal_Verification_of_Floating_Point_Hardware.pdf",
  abstract =     "Hardware for integer or fixed-point arithmetic is
                 relatively simple to design, at least at the
                 register-transfer level. If the range of values and
                 precision that can be represented with these formats is
                 not sufficient for the target application,
                 floating-point hardware might be required.
                 Unfortunately, floating-point units are complex to
                 design, and notoriously challenging to verify. Since
                 the famous 1994 Intel Pentium bug, many companies have
                 investigated and successfully applied formal methods to
                 this task. However, solutions often rely on a mix of
                 the following: hard-to-use formal tools; highly
                 specialized engineering skills; availability of a
                 suitable executable model of the hardware; and
                 significant, design-specific engineering effort. In
                 this paper, we present an alternative floating-point
                 hardware verification approach based on a reusable,
                 IEEE 754 compliant SystemVerilog arithmetic library.
                 While not addressing all verification challenges, this
                 method enables engineers to set up a formal testbench
                 and uncover deep corner-case bugs with minimal effort.
                 Results from industrial applications are reported.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Reddy:2018:DAD
author: K. Manikantta Reddy and M. H. Vasantha and Y. B. Nithin Kumar and Devesh Dwivedi
booktitle: 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
title: Design of Approximate Dividers for Error Tolerant Applications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--9
month: aug
monthnumber: 8
year: 2018
DOI: https://doi.org/10.1109/mwscas.2018.8623909
bibdate: Wed Dec 20 07:39:14 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 07:39:14 ???
acknowledgement: ack-nhfb
rawauthor: K. Manikantta Reddy and M. H. Vasantha and Y. B. Nithin Kumar and Devesh Dwivedi
rawbooktitle: {2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)}
rawtitle: Design of Approximate Dividers for Error Tolerant Applications
entry:
@InProceedings{Reddy:2018:DAD,
  author =       "K. Manikantta Reddy and M. H. Vasantha and Y. B.
                 Nithin Kumar and Devesh Dwivedi",
  booktitle =    "{2018 IEEE 61st International Midwest Symposium on
                 Circuits and Systems (MWSCAS)}",
  title =        "Design of Approximate Dividers for Error Tolerant
                 Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  month =        aug,
  year =         "2018",
  DOI =          "https://doi.org/10.1109/mwscas.2018.8623909",
  bibdate =      "Wed Dec 20 07:39:14 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Reyhani-Masoleh:2018:NAR
author: Arash Reyhani-Masoleh and Mostafa Taha and Doaa Ashmawy
title: New Area Record for the AES Combined S-Box / Inverse S-Box
crossref: Tenca:2018:PIS
pages: 145--152
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464780
bibdate: Fri Jan 31 08:05:31 2020
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Arash Reyhani-Masoleh and Mostafa Taha and Doaa Ashmawy
rawtitle: New Area Record for the {AES} Combined {S}-Box\slash Inverse {S}-Box
abstract:
The AES combined S-box/inverse S-box is a single construction that is shared between the encryption and decryption data paths of the AES. The currently most compact implementation of the AES combined S-box/inverse S-box is Canright's design, introduced back in 2005. Since then, the research community has introduced several optimizations over the S-box only, however the combined S-boxlinverse S-box received little attention. In this paper, we propose a new AES combined S-boxlinverse S-box design that is both smaller and faster than Canright's design. We achieve this goal by proposing to use new tower field and optimizing each and every block inside the combined architecture for this field. Our complexity analysis and ASIC implementation results in the CMOS STM 65nm and NanGate 15nm technologies show that our design outperforms the counterparts in terms of area and speed.

keywords:
AES combined S-box-inverse S-box; application specific integrated circuits; ARITH-25; Canright design; circuit optimisation; CMOS STM; Complexity theory; Computer architecture; cryptography; decryption data paths; Encryption; encryption data paths; Generators; Logic gates; Multiplexing; NanGate; Poles and towers; size 15.0 nm; size 65.0 nm

rawabstract:
The AES combined S-box/inverse S-box is a single construction that is shared between the encryption and decryption data paths of the AES. The currently most compact implementation of the AES combined S-box/inverse S-box is Canright's design, introduced back in 2005. Since then, the research community has introduced several optimizations over the S-box only, however the combined S-boxlinverse S-box received little attention. In this paper, we propose a new AES combined S-boxlinverse S-box design that is both smaller and faster than Canright's design. We achieve this goal by proposing to use new tower field and optimizing each and every block inside the combined architecture for this field. Our complexity analysis and ASIC implementation results in the CMOS STM 65nm and NanGate 15nm technologies show that our design outperforms the counterparts in terms of area and speed.

entry:
@InProceedings{Reyhani-Masoleh:2018:NAR,
  author =       "Arash Reyhani-Masoleh and Mostafa Taha and Doaa
                 Ashmawy",
  title =        "New Area Record for the {AES} Combined {S}-Box\slash
                 Inverse {S}-Box",
  crossref =     "Tenca:2018:PIS",
  pages =        "145--152",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464780",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The AES combined S-box/inverse S-box is a single
                 construction that is shared between the encryption and
                 decryption data paths of the AES. The currently most
                 compact implementation of the AES combined
                 S-box/inverse S-box is Canright's design, introduced
                 back in 2005. Since then, the research community has
                 introduced several optimizations over the S-box only,
                 however the combined S-boxlinverse S-box received
                 little attention. In this paper, we propose a new AES
                 combined S-boxlinverse S-box design that is both
                 smaller and faster than Canright's design. We achieve
                 this goal by proposing to use new tower field and
                 optimizing each and every block inside the combined
                 architecture for this field. Our complexity analysis
                 and ASIC implementation results in the CMOS STM 65nm
                 and NanGate 15nm technologies show that our design
                 outperforms the counterparts in terms of area and
                 speed.",
  acknowledgement = ack-nhfb,
  keywords =     "AES combined S-box-inverse S-box; application specific
                 integrated circuits; ARITH-25; Canright design; circuit
                 optimisation; CMOS STM; Complexity theory; Computer
                 architecture; cryptography; decryption data paths;
                 Encryption; encryption data paths; Generators; Logic
                 gates; Multiplexing; NanGate; Poles and towers; size
                 15.0 nm; size 65.0 nm",
}


bibtype: inproceedings
filename: fparith.bib
label: Riedy:2018:AAO
author: Jason Riedy and James Demmel
title: Augmented Arithmetic Operations Proposed for IEEE-754 2018
crossref: Tenca:2018:PIS
pages: 45--52
year: 2018
DOI: https://doi.org/10.1109/ARITH.2018.8464813
bibdate: Fri Jan 31 08:05:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:05:31 ???
acknowledgement: ack-nhfb
rawauthor: Jason Riedy and James Demmel
rawtitle: Augmented Arithmetic Operations Proposed for {IEEE-754 2018}
abstract:
Algorithms for extending arithmetic precision through compensated summation or arithmetics like double-double rely on operations commonly called twoSum and twoProduct. The current draft of the IEEE 754 standard specifies these operations under the names augmentedAddition and augmentedMultiplication. These operations were included after three decades of experience because of a motivating new use: bitwise reproducible arithmetic. Standardizing the operations provides a hardware acceleration target that can provide at least a 33% speed improvements in reproducible dot product, placing reproducible dot product almost within a factor of two of common dot product. This paper provides history and motivation for standardizing these operations. We also define the operations, explain the rationale for all the specific choices, and provide parameterized test cases for new boundary behaviors.

keywords:
Acceleration; ARITH-25; arithmetic precision; augmented arithmetic operations; bitwise reproducible arithmetic; common dot product; floating point arithmetic; Hardware; hardware acceleration target; History; IEEE 754 standard; IEEE standards; IEEE-754 2018; Libraries; Magnetic heads; reproducible dot product; Software; Standards

rawabstract:
Algorithms for extending arithmetic precision through compensated summation or arithmetics like double-double rely on operations commonly called twoSum and twoProduct. The current draft of the IEEE 754 standard specifies these operations under the names augmentedAddition and augmentedMultiplication. These operations were included after three decades of experience because of a motivating new use: bitwise reproducible arithmetic. Standardizing the operations provides a hardware acceleration target that can provide at least a 33\% speed improvements in reproducible dot product, placing reproducible dot product almost within a factor of two of common dot product. This paper provides history and motivation for standardizing these operations. We also define the operations, explain the rationale for all the specific choices, and provide parameterized test cases for new boundary behaviors.

entry:
@InProceedings{Riedy:2018:AAO,
  author =       "Jason Riedy and James Demmel",
  title =        "Augmented Arithmetic Operations Proposed for {IEEE-754
                 2018}",
  crossref =     "Tenca:2018:PIS",
  pages =        "45--52",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ARITH.2018.8464813",
  bibdate =      "Fri Jan 31 08:05:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Algorithms for extending arithmetic precision through
                 compensated summation or arithmetics like double-double
                 rely on operations commonly called twoSum and
                 twoProduct. The current draft of the IEEE 754 standard
                 specifies these operations under the names
                 augmentedAddition and augmentedMultiplication. These
                 operations were included after three decades of
                 experience because of a motivating new use: bitwise
                 reproducible arithmetic. Standardizing the operations
                 provides a hardware acceleration target that can
                 provide at least a 33\% speed improvements in
                 reproducible dot product, placing reproducible dot
                 product almost within a factor of two of common dot
                 product. This paper provides history and motivation for
                 standardizing these operations. We also define the
                 operations, explain the rationale for all the specific
                 choices, and provide parameterized test cases for new
                 boundary behaviors.",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; ARITH-25; arithmetic precision;
                 augmented arithmetic operations; bitwise reproducible
                 arithmetic; common dot product; floating point
                 arithmetic; Hardware; hardware acceleration target;
                 History; IEEE 754 standard; IEEE standards; IEEE-754
                 2018; Libraries; Magnetic heads; reproducible dot
                 product; Software; Standards",
}


bibtype: article
filename: fparith.bib
label: Rodriguez-Henriquez:2018:SIH
author: Francisco Rodriguez-Henriquez and Erkay Savas
title: Special issue in honor of Peter Lawrence Montgomery
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 185--187
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0168-3
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Francisco Rodr{\'\i}guez-Henr{\'\i}quez and Erkay Savas
rawtitle: Special issue in honor of {Peter Lawrence Montgomery}
URL:
http://link.springer.com/article/10.1007/s13389-017-0168-3; https://link.springer.com/content/pdf/10.1007/s13389-017-0168-3.pdf

entry:
@Article{Rodriguez-Henriquez:2018:SIH,
  author =       "Francisco Rodr{\'\i}guez-Henr{\'\i}quez and Erkay
                 Savas",
  title =        "Special issue in honor of {Peter Lawrence
                 Montgomery}",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "185--187",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0168-3",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0168-3;
                 https://link.springer.com/content/pdf/10.1007/s13389-017-0168-3.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Saadat:2018:MBM
author: Hassaan Saadat and Haseeb Bokhari and Sri Parameswaran
title: Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication
journal: j-IEEE-TRANS-CAD-ICS
volume: 37
number: 11
pages: 2623--2635
month: nov
monthnumber: 11
year: 2018
CODEN: ITCSDI
DOI: https://doi.org/10.1109/tcad.2018.2857262
ISSN: 0278-0070 (print), 1937-4151 (electronic) OR 02780070 (print), 19374151 (electronic)
ISSNL: 0278-0070 OR 02780070
bibdate: Wed Dec 20 07:46:25 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 07:46:25 ???
fjournal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43
rawauthor: Hassaan Saadat and Haseeb Bokhari and Sri Parameswaran
rawtitle: Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication
entry:
@Article{Saadat:2018:MBM,
  author =       "Hassaan Saadat and Haseeb Bokhari and Sri
                 Parameswaran",
  title =        "Minimally Biased Multipliers for Approximate Integer
                 and Floating-Point Multiplication",
  journal =      j-IEEE-TRANS-CAD-ICS,
  volume =       "37",
  number =       "11",
  pages =        "2623--2635",
  month =        nov,
  year =         "2018",
  CODEN =        "ITCSDI",
  DOI =          "https://doi.org/10.1109/tcad.2018.2857262",
  ISSN =         "0278-0070 (print), 1937-4151 (electronic)",
  ISSN-L =       "0278-0070",
  bibdate =      "Wed Dec 20 07:46:25 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computer-Aided Design of
                 Integrated Circuits and Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43",
}


bibtype: article
filename: fparith.bib
label: Sanchez-Stern:2018:FRC
author: Alex Sanchez-Stern and Pavel Panchekha and Sorin Lerner and Zachary Tatlock
title: Finding root causes of floating point error
journal: j-SIGPLAN
volume: 53
number: 4
pages: 256--269
month: apr
monthnumber: 4
year: 2018
CODEN: SINODQ
DOI: https://doi.org/10.1145/3296979.3192411
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Wed Oct 16 14:12:57 MDT 2019
bibtimestamp: 2019.10.16 14:12:57 MDT
fjournal: ACM SIGPLAN Notices
remark: PLDI '18 proceedings.
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Alex Sanchez-Stern and Pavel Panchekha and Sorin Lerner and Zachary Tatlock
rawtitle: Finding root causes of floating point error
abstract:
Floating-point arithmetic plays a central role in science, engineering, and finance by enabling developers to approximate real arithmetic. To address numerical issues in large floating-point applications, developers must identify root causes, which is difficult because floating-point errors are generally non-local, non-compositional, and non-uniform. This paper presents Herbgrind, a tool to help developers identify and address root causes in numerical code written in low-level languages like C/C++ and Fortran. Herbgrind dynamically tracks dependencies between operations and program outputs to avoid false positives and abstracts erroneous computations to simplified program fragments whose improvement can reduce output error. We perform several case studies applying Herbgrind to large, expert-crafted numerical programs and show that it scales to applications spanning hundreds of thousands of lines, correctly handling the low-level details of modern floating point hardware and mathematical libraries and tracking error across function boundaries and through the heap.

rawabstract:
Floating-point arithmetic plays a central role in science, engineering, and finance by enabling developers to approximate real arithmetic. To address numerical issues in large floating-point applications, developers must identify root causes, which is difficult because floating-point errors are generally non-local, non-compositional, and non-uniform. This paper presents Herbgrind, a tool to help developers identify and address root causes in numerical code written in low-level languages like C/C++ and Fortran. Herbgrind dynamically tracks dependencies between operations and program outputs to avoid false positives and abstracts erroneous computations to simplified program fragments whose improvement can reduce output error. We perform several case studies applying Herbgrind to large, expert-crafted numerical programs and show that it scales to applications spanning hundreds of thousands of lines, correctly handling the low-level details of modern floating point hardware and mathematical libraries and tracking error across function boundaries and through the heap.

entry:
@Article{Sanchez-Stern:2018:FRC,
  author =       "Alex Sanchez-Stern and Pavel Panchekha and Sorin
                 Lerner and Zachary Tatlock",
  title =        "Finding root causes of floating point error",
  journal =      j-SIGPLAN,
  volume =       "53",
  number =       "4",
  pages =        "256--269",
  month =        apr,
  year =         "2018",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/3296979.3192411",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Wed Oct 16 14:12:57 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  abstract =     "Floating-point arithmetic plays a central role in
                 science, engineering, and finance by enabling
                 developers to approximate real arithmetic. To address
                 numerical issues in large floating-point applications,
                 developers must identify root causes, which is
                 difficult because floating-point errors are generally
                 non-local, non-compositional, and non-uniform. This
                 paper presents Herbgrind, a tool to help developers
                 identify and address root causes in numerical code
                 written in low-level languages like C/C++ and Fortran.
                 Herbgrind dynamically tracks dependencies between
                 operations and program outputs to avoid false positives
                 and abstracts erroneous computations to simplified
                 program fragments whose improvement can reduce output
                 error. We perform several case studies applying
                 Herbgrind to large, expert-crafted numerical programs
                 and show that it scales to applications spanning
                 hundreds of thousands of lines, correctly handling the
                 low-level details of modern floating point hardware and
                 mathematical libraries and tracking error across
                 function boundaries and through the heap.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  remark =       "PLDI '18 proceedings.",
}


bibtype: article
filename: fparith.bib
label: Savas:2018:MI
author: Erkay Savas and Cetin Kaya Koc
title: Montgomery inversion
journal: j-J-CRYPTO-ENG
volume: 8
number: 3
pages: 201--210
month: sep
monthnumber: 9
year: 2018
DOI: https://doi.org/10.1007/s13389-017-0161-x
ISSN: 2190-8508 (print), 2190-8516 (electronic) OR 21908508 (print), 21908516 (electronic)
ISSNL: 2190-8508 OR 21908508
bibdate: Wed Oct 2 11:24:50 MDT 2019
bibtimestamp: 2019.10.02 11:24:50 MDT
URL: http://link.springer.com/article/10.1007/s13389-017-0161-x
fjournal: Journal of Cryptographic Engineering
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/13389
rawauthor: Erkay Savas and {\c{C}}etin Kaya Ko{\c{c}}
rawtitle: {Montgomery} inversion
entry:
@Article{Savas:2018:MI,
  author =       "Erkay Savas and {\c{C}}etin Kaya Ko{\c{c}}",
  title =        "{Montgomery} inversion",
  journal =      j-J-CRYPTO-ENG,
  volume =       "8",
  number =       "3",
  pages =        "201--210",
  month =        sep,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-017-0161-x",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Wed Oct 2 11:24:50 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib",
  URL =          "http://link.springer.com/article/10.1007/s13389-017-0161-x",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}


bibtype: article
filename: fparith.bib
label: Schneider:2018:USS
author: D. Schneider
title: U.S. supercomputing strikes back
journal: j-IEEE-SPECTRUM
volume: 55
number: 1
pages: 52--53
month: jan
monthnumber: 1
year: 2018
CODEN: IEESAM
DOI: https://doi.org/10.1109/MSPEC.2018.8241739
ISSN: 0018-9235 (print), 1939-9340 (electronic) OR 00189235 (print), 19399340 (electronic)
ISSNL: 0018-9235 OR 00189235
bibdate: Sat Jan 18 07:02:09 2020
bibtimestamp: 2020.01.18 07:02:09 ???
fjournal: IEEE Spectrum
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6
rawauthor: D. Schneider
rawtitle: {U.S.} supercomputing strikes back
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeespectrum2010.bib; https://www.math.utah.edu/pub/tex/bib/super.bib

keywords:
Companies; Computational modeling; floating-point operations; Games; Hardware; parallel machines; Payloads; petaflops; Rockets; Supercomputers; Titan machine; U.S. high-performance computing community; U.S. supercomputing

entry:
@Article{Schneider:2018:USS,
  author =       "D. Schneider",
  title =        "{U.S.} supercomputing strikes back",
  journal =      j-IEEE-SPECTRUM,
  volume =       "55",
  number =       "1",
  pages =        "52--53",
  month =        jan,
  year =         "2018",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/MSPEC.2018.8241739",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Sat Jan 18 07:02:09 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeespectrum2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/super.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
  keywords =     "Companies; Computational modeling; floating-point
                 operations; Games; Hardware; parallel machines;
                 Payloads; petaflops; Rockets; Supercomputers; Titan
                 machine; U.S. high-performance computing community;
                 U.S. supercomputing",
}


bibtype: article
filename: fparith.bib
label: Seo:2018:FBM
author: Jungjoo Seo and Kunsoo Park
title: Fast batch modular exponentiation with common-multiplicand multiplication
journal: j-INFO-PROC-LETT
volume: 129
pages: 5--10
month: jan
monthnumber: 1
year: 2018
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Mon Oct 30 08:48:26 MDT 2017
bibtimestamp: 2017.10.30 08:48:26 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0020019017301527
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: Jungjoo Seo and Kunsoo Park
rawtitle: Fast batch modular exponentiation with common-multiplicand multiplication
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/infoproc2010.bib

entry:
@Article{Seo:2018:FBM,
  author =       "Jungjoo Seo and Kunsoo Park",
  title =        "Fast batch modular exponentiation with
                 common-multiplicand multiplication",
  journal =      j-INFO-PROC-LETT,
  volume =       "129",
  number =       "??",
  pages =        "5--10",
  month =        jan,
  year =         "2018",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Mon Oct 30 08:48:26 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/infoproc2010.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0020019017301527",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
}


bibtype: misc
filename: fparith.bib
label: Trader:2018:ICS
author: Tiffany Trader
title: Inventor Claims to Have Solved Floating Point Error Problem
pages: 5--10
day: 17
month: jan
monthnumber: 1
year: 2018
bibdate: Fri Mar 23 19:13:03 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.03.23 19:13:03 ???
URL: https://www.hpcwire.com/2018/01/17/inventor-claims-solved-floating-point-error-problem/
acknowledgement: ack-nhfb
howpublished: HPC Web site.
rawauthor: Tiffany Trader
rawtitle: Inventor Claims to Have Solved Floating Point Error Problem
note:
From the HPC editor: ``After this article was published, a number of readers raised concerns about the originality of Jorgensen's techniques, noting the existence of prior art going back years. Specifically, there is precedent in John Gustafson's work on unums and interval arithmetic both at Sun and in his 2015 book, booktitle The End of Error, which was published 19 months before Jorgensen's patent application was filed. ''

rawnote:
From the HPC editor: ``After this article was published, a number of readers raised concerns about the originality of Jorgensen's techniques, noting the existence of prior art going back years. Specifically, there is precedent in John Gustafson's work on unums and interval arithmetic both at Sun and in his 2015 book, \booktitle{The End of Error}, which was published 19 months before Jorgensen's patent application was filed. ''

entry:
@Misc{Trader:2018:ICS,
  author =       "Tiffany Trader",
  title =        "Inventor Claims to Have Solved Floating Point Error
                 Problem",
  howpublished = "HPC Web site.",
  day =          "17",
  month =        jan,
  year =         "2018",
  bibdate =      "Fri Mar 23 19:13:03 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "From the HPC editor: ``After this article was
                 published, a number of readers raised concerns about
                 the originality of Jorgensen's techniques, noting the
                 existence of prior art going back years. Specifically,
                 there is precedent in John Gustafson's work on unums
                 and interval arithmetic both at Sun and in his 2015
                 book, \booktitle{The End of Error}, which was published
                 19 months before Jorgensen's patent application was
                 filed. ''",
  URL =          "https://www.hpcwire.com/2018/01/17/inventor-claims-solved-floating-point-error-problem/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Villalba-Moreno:2018:FHF
author: Julio Villalba-Moreno and Javier Hormigo and Sonia Gonzalez-Navarro
title: Fast HUB Floating-point Adder for FPGA
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 66
number: 6
pages: 1028--1032
month: jun
monthnumber: 6
year: 2018
DOI: https://doi.org/10.1109/TCSII.2018.2873194
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Mon Feb 10 08:25:14 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 08:25:14 ???
URL: https://ieeexplore.ieee.org/document/8477084
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
keywords: HUB (Half-Unit-Biased) floating-point format
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Circuits Syst., II Express Briefs
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Julio Villalba-Moreno and Javier Hormigo and Sonia Gonz{\'a}lez-Navarro
rawtitle: Fast {HUB} Floating-point Adder for {FPGA}
entry:
@Article{Villalba-Moreno:2018:FHF,
  author =       "Julio Villalba-Moreno and Javier Hormigo and Sonia
                 Gonz{\'a}lez-Navarro",
  title =        "Fast {HUB} Floating-point Adder for {FPGA}",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "66",
  number =       "6",
  pages =        "1028--1032",
  month =        jun,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/TCSII.2018.2873194",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Mon Feb 10 08:25:14 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/document/8477084",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Circuits Syst., II Express Briefs",
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
  keywords =     "HUB (Half-Unit-Biased) floating-point format",
}


bibtype: article
filename: fparith.bib
label: Villalba-Moreno:2018:URH
author: Julio Villalba-Moreno and Javier Hormigo and Sonia Gonzalez-Navarro
title: Unbiased Rounding for HUB Floating-Point Addition
journal: j-IEEE-TRANS-COMPUT
volume: 67
number: 9
pages: 1359--1365
month: sep
monthnumber: 9
year: 2018
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2807429
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Mar 15 08:10:13 2019
bibtimestamp: 2019.03.15 08:10:13 ???
URL: https://ieeexplore.ieee.org/document/8300633/
fjournal: IEEE Transactions on Computers
keywords: HUB (Half-Unit-Biased) floating-point format
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Julio Villalba-Moreno and Javier Hormigo and Sonia Gonz{\'a}lez-Navarro
rawtitle: Unbiased Rounding for {HUB} Floating-Point Addition
entry:
@Article{Villalba-Moreno:2018:URH,
  author =       "Julio Villalba-Moreno and Javier Hormigo and Sonia
                 Gonz{\'a}lez-Navarro",
  title =        "Unbiased Rounding for {HUB} Floating-Point Addition",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "67",
  number =       "9",
  pages =        "1359--1365",
  month =        sep,
  year =         "2018",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2807429",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Mar 15 08:10:13 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "https://ieeexplore.ieee.org/document/8300633/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "HUB (Half-Unit-Biased) floating-point format",
}


bibtype: article
filename: fparith.bib
label: Walczyk:2018:IAF
author: Cezary J. Walczyk and Leonid V. Moroz and Jan L. Cieslinski
title: Improving the accuracy of the fast inverse square root algorithm
journal: arXiv.org
pages: 1--21
day: 17
month: feb
monthnumber: 2
year: 2018
DOI: https://doi.org/10.48550/arXiv.1802.06302
bibdate: Wed Dec 20 07:55:45 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 07:55:45 ???
URL: https://arxiv.org/abs/1802.06302
acknowledgement: ack-nhfb
rawauthor: Cezary J. Walczyk and Leonid V. Moroz and Jan L. Cie{\'s}li{\'n}ski
rawtitle: Improving the accuracy of the fast inverse square root algorithm
abstract:
We present improved algorithms for fast calculation of the inverse square root for single-precision floating-point numbers. The algorithms are much more accurate than the famous fast inverse square root algorithm and have the same or similar computational cost. The main idea of our work consists in modifying the Newton-Raphson method and demanding that the maximal error is as small as possible. Such modification is possible when the distribution of Newton-Raphson corrections is not symmetric (e.g., if they are non-positive functions).

rawabstract:
We present improved algorithms for fast calculation of the inverse square root for single-precision floating-point numbers. The algorithms are much more accurate than the famous fast inverse square root algorithm and have the same or similar computational cost. The main idea of our work consists in modifying the Newton-Raphson method and demanding that the maximal error is as small as possible. Such modification is possible when the distribution of Newton-Raphson corrections is not symmetric (e.g., if they are non-positive functions).

entry:
@Article{Walczyk:2018:IAF,
  author =       "Cezary J. Walczyk and Leonid V. Moroz and Jan L.
                 Cie{\'s}li{\'n}ski",
  title =        "Improving the accuracy of the fast inverse square root
                 algorithm",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--21",
  day =          "17",
  month =        feb,
  year =         "2018",
  DOI =          "https://doi.org/10.48550/arXiv.1802.06302",
  bibdate =      "Wed Dec 20 07:55:45 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1802.06302",
  abstract =     "We present improved algorithms for fast calculation of
                 the inverse square root for single-precision
                 floating-point numbers. The algorithms are much more
                 accurate than the famous fast inverse square root
                 algorithm and have the same or similar computational
                 cost. The main idea of our work consists in modifying
                 the Newton-Raphson method and demanding that the
                 maximal error is as small as possible. Such
                 modification is possible when the distribution of
                 Newton-Raphson corrections is not symmetric (e.g., if
                 they are non-positive functions).",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Wang:2018:TDN
author: Naigang Wang and Jungwook Choi and Daniel Brand and Chia-Yu Chen and Kailash Gopalakrishnan
editor: S. Bengio and others
title: Training Deep Neural Networks with 8-bit Floating Point Numbers
publisher: Curran Associates, Inc.
pages: 7675--7684
year: 2018
bibdate: Wed Dec 19 19:17:48 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.12.19 19:17:48 ???
acknowledgement: ack-nhfb
rawauthor: Naigang Wang and Jungwook Choi and Daniel Brand and Chia-Yu Chen and Kailash Gopalakrishnan
raweditor: S. Bengio and others
rawtitle: Training {Deep Neural Networks} with 8-bit Floating Point Numbers
booktitle:
Proceedings of the 32nd Conference on Neural Information Processing Systems (NeurIPS 2018), Montreal, Canada

URL:
https://arxiv.org/abs/1812.08011; https://papers.nips.cc/paper/7994-training-deep-neural-networks-with-8-bit-floating-point-numbers.pdf

abstract:
The state-of-the-art hardware platforms for training Deep Neural Networks (DNNs) are moving from traditional single precision (32-bit) computations towards 16 bits of precision in large part due to the high energy efficiency and smaller bit storage associated with using reduced-precision representations. However, unlike inference, training with numbers represented with less than 16 bits has been challenging due to the need to maintain fidelity of the gradient computations during back-propagation. Here we demonstrate, for the first time, the successful training of DNNs using 8-bit floating point numbers while fully maintaining the accuracy on a spectrum of Deep Learning models and datasets. In addition to reducing the data and computation precision to 8 bits, we also successfully reduce the arithmetic precision for additions (used in partial product accumulation and weight updates) from 32 bits to 16 bits through the introduction of a number of key ideas including chunk-based accumulation and floating point stochastic rounding. The use of these novel techniques lays the foundation for a new generation of hardware training platforms with the potential for 2--4 $ times $ improved throughput over today's systems.

remark:
The 8-bit floating-point format, FP8, has 1 sign bit, 5 exponent bits, and 2 significand bits (1,5,2); the 16-bit format, FP16, has 1 sign bit, 6 exponent bits, and 9 significand bits (1,6,9). There is no mention of Infinity, NaN, signed zeros, or FMA operations

rawabstract:
The state-of-the-art hardware platforms for training Deep Neural Networks (DNNs) are moving from traditional single precision (32-bit) computations towards 16 bits of precision in large part due to the high energy efficiency and smaller bit storage associated with using reduced-precision representations. However, unlike inference, training with numbers represented with less than 16 bits has been challenging due to the need to maintain fidelity of the gradient computations during back-propagation. Here we demonstrate, for the first time, the successful training of DNNs using 8-bit floating point numbers while fully maintaining the accuracy on a spectrum of Deep Learning models and datasets. In addition to reducing the data and computation precision to 8 bits, we also successfully reduce the arithmetic precision for additions (used in partial product accumulation and weight updates) from 32 bits to 16 bits through the introduction of a number of key ideas including chunk-based accumulation and floating point stochastic rounding. The use of these novel techniques lays the foundation for a new generation of hardware training platforms with the potential for 2--4 $ \times $ improved throughput over today's systems.

rawbooktitle:
{Proceedings of the 32nd Conference on Neural Information Processing Systems (NeurIPS 2018), Montr{\'e}al, Canada}

entry:
@InProceedings{Wang:2018:TDN,
  author =       "Naigang Wang and Jungwook Choi and Daniel Brand and
                 Chia-Yu Chen and Kailash Gopalakrishnan",
  editor =       "S. Bengio and others",
  booktitle =    "{Proceedings of the 32nd Conference on Neural
                 Information Processing Systems (NeurIPS 2018),
                 Montr{\'e}al, Canada}",
  title =        "Training {Deep Neural Networks} with 8-bit Floating
                 Point Numbers",
  publisher =    "Curran Associates, Inc.",
  address =      "????",
  pages =        "7675--7684",
  year =         "2018",
  bibdate =      "Wed Dec 19 19:17:48 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1812.08011;
                 https://papers.nips.cc/paper/7994-training-deep-neural-networks-with-8-bit-floating-point-numbers.pdf",
  abstract =     "The state-of-the-art hardware platforms for training
                 Deep Neural Networks (DNNs) are moving from traditional
                 single precision (32-bit) computations towards 16 bits
                 of precision in large part due to the high energy
                 efficiency and smaller bit storage associated with
                 using reduced-precision representations. However,
                 unlike inference, training with numbers represented
                 with less than 16 bits has been challenging due to the
                 need to maintain fidelity of the gradient computations
                 during back-propagation. Here we demonstrate, for the
                 first time, the successful training of DNNs using 8-bit
                 floating point numbers while fully maintaining the
                 accuracy on a spectrum of Deep Learning models and
                 datasets. In addition to reducing the data and
                 computation precision to 8 bits, we also successfully
                 reduce the arithmetic precision for additions (used in
                 partial product accumulation and weight updates) from
                 32 bits to 16 bits through the introduction of a number
                 of key ideas including chunk-based accumulation and
                 floating point stochastic rounding. The use of these
                 novel techniques lays the foundation for a new
                 generation of hardware training platforms with the
                 potential for 2--4 $ \times $ improved throughput over
                 today's systems.",
  acknowledgement = ack-nhfb,
  remark =       "The 8-bit floating-point format, FP8, has 1 sign bit,
                 5 exponent bits, and 2 significand bits (1,5,2); the
                 16-bit format, FP16, has 1 sign bit, 6 exponent bits,
                 and 9 significand bits (1,6,9). There is no mention of
                 Infinity, NaN, signed zeros, or FMA operations",
  xxpages =      "1--10",
}


bibtype: inproceedings
filename: fparith.bib
label: Yang:2018:OMP
editor: IEEE
booktitle: 2018 IEEE International Conference on Intelligence and Safety for Robotics (ISR)
title: An Omnidirectional and Movable Palletizing Robot based on Computer Vision Positing
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 423--428
year: 2018
DOI: https://doi.org/10.1109/IISR.2018.8535688
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawbooktitle: {2018 IEEE International Conference on Intelligence and Safety for Robotics (ISR)}
raweditor: {IEEE}
rawtitle: An Omnidirectional and Movable Palletizing Robot based on Computer Vision Positing
author:
Xiong Yang and Hongbin Zhang and Tianyou Cheng and Xuebin Ni and Chenhao Wu and Huaizhi Zong and Haojian Lu and Zhiguo Lu and Yajing Shen

rawauthor:
Xiong Yang and Hongbin Zhang and Tianyou Cheng and Xuebin Ni and Chenhao Wu and Huaizhi Zong and Haojian Lu and Zhiguo Lu and Yajing Shen

entry:
@InProceedings{Yang:2018:OMP,
  author =       "Xiong Yang and Hongbin Zhang and Tianyou Cheng and
                 Xuebin Ni and Chenhao Wu and Huaizhi Zong and Haojian
                 Lu and Zhiguo Lu and Yajing Shen",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE International Conference on Intelligence
                 and Safety for Robotics (ISR)}",
  title =        "An Omnidirectional and Movable Palletizing Robot based
                 on Computer Vision Positing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "423--428",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/IISR.2018.8535688",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Adams:2019:RRP
author: Ulf Adams
title: Ryu revisited: tt printf floating point conversion
journal: j-PACMPL
volume: 3
number: OOPSLA
pages: 169:1--169:23
month: oct
monthnumber: 10
year: 2019
DOI: https://doi.org/10.1145/3360595
ISSN: 2475-1421 OR 24751421
bibdate: Fri Aug 7 19:22:30 MDT 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pacmpl.bib
bibtimestamp: 2020.08.07 19:22:30 MDT
URL: https://dl.acm.org/doi/abs/10.1145/3360595
fjournal: Proceedings of the ACM on Programming Languages
keywords: base conversion
acknowledgement: ack-nhfb
articleno: 169
journalURL: https://pacmpl.acm.org/
rawauthor: Ulf Adams
rawtitle: {Ry{\=u}} revisited: {\tt printf} floating point conversion
abstract:
Ryu Printf is a new algorithm to convert floating-point numbers to decimal strings according to the tt printf tt %f, tt %e, and tt %g formats: tt %f generates `full' output (integer part of the input, dot, configurable number of digits), tt %e generates scientific output (one leading digit, dot, configurable number of digits, exponent), and tt %g generates the shorter of the two. Ryu's Printf is based on the Ryu algorithm, which converts binary floating-point numbers to the shortest equivalent decimal floating-point representation. We provide quantitative evidence that Ryu Printf is between 3.8 and 55 times faster than existing tt printf implementations.par Furthermore, we show that both Ryu and Ryu Printf generalize to arbitrary number bases. This finding implies the existence of a fast algorithm to convert from base-10 to base-2, as long as the maximum precision of the input is known a priori.

rawabstract:
Ry{\=u} Printf is a new algorithm to convert floating-point numbers to decimal strings according to the {\tt printf} {\tt \%f}, {\tt \%e}, and {\tt \%g} formats: {\tt \%f} generates `full' output (integer part of the input, dot, configurable number of digits), {\tt \%e} generates scientific output (one leading digit, dot, configurable number of digits, exponent), and {\tt \%g} generates the shorter of the two. Ry{\=u}'s Printf is based on the Ry{\=u} algorithm, which converts binary floating-point numbers to the shortest equivalent decimal floating-point representation. We provide quantitative evidence that Ry{\=u} Printf is between 3.8 and 55 times faster than existing {\tt printf} implementations.\par Furthermore, we show that both Ry{\=u} and Ry{\=u} Printf generalize to arbitrary number bases. This finding implies the existence of a fast algorithm to convert from base-10 to base-2, as long as the maximum precision of the input is known a priori.

entry:
@Article{Adams:2019:RRP,
  author =       "Ulf Adams",
  title =        "{Ry{\=u}} revisited: {\tt printf} floating point
                 conversion",
  journal =      j-PACMPL,
  volume =       "3",
  number =       "OOPSLA",
  pages =        "169:1--169:23",
  month =        oct,
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3360595",
  ISSN =         "2475-1421",
  bibdate =      "Fri Aug 7 19:22:30 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pacmpl.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3360595",
  abstract =     "Ry{\=u} Printf is a new algorithm to convert
                 floating-point numbers to decimal strings according to
                 the {\tt printf} {\tt \%f}, {\tt \%e}, and {\tt \%g}
                 formats: {\tt \%f} generates `full' output (integer
                 part of the input, dot, configurable number of digits),
                 {\tt \%e} generates scientific output (one leading
                 digit, dot, configurable number of digits, exponent),
                 and {\tt \%g} generates the shorter of the two.
                 Ry{\=u}'s Printf is based on the Ry{\=u} algorithm,
                 which converts binary floating-point numbers to the
                 shortest equivalent decimal floating-point
                 representation. We provide quantitative evidence that
                 Ry{\=u} Printf is between 3.8 and 55 times faster than
                 existing {\tt printf} implementations.\par

                 Furthermore, we show that both Ry{\=u} and Ry{\=u}
                 Printf generalize to arbitrary number bases. This
                 finding implies the existence of a fast algorithm to
                 convert from base-10 to base-2, as long as the maximum
                 precision of the input is known a priori.",
  acknowledgement = ack-nhfb,
  articleno =    "169",
  fjournal =     "Proceedings of the ACM on Programming Languages",
  journal-URL =  "https://pacmpl.acm.org/",
  keywords =     "base conversion",
}


bibtype: misc
filename: fparith.bib
label: Adams:2019:URP
title: ulfjack/ryu: Printf Support
pages: 169:1--169:23
day: 12
month: aug
monthnumber: 8
year: 2019
DOI: https://doi.org/10.5281/zenodo.3366212
bibdate: Sun Aug 16 18:37:00 2020
bibtimestamp: 2020.08.16 18:37:00 ???
URL: https://github.com/ulfjack/ryu/tree/v2.0; https://zenodo.org/record/3366212
acknowledgement: ack-nhfb
howpublished: Web site
rawtitle: {ulfjack/ryu}: Printf Support
author:
Ulf Adams and Stephan T. Lavavej and Alexander Bolz and Vinnie Falco and David Tolnay and Mitchell Blank, Jr. and Mara Bos and Caleb Spare and Alexander Iljin

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/java2010.bib

abstract:
This project contains C and Java implementation of Ryu, as well as a C implementation of Ryu Printf. Ryu converts a floating point number to its shortest decimal representation, whereas Ryu Printf converts a floating point number according to the printf %f or %e format. At the time of this writing, these are the fastest known float-to-string conversion algorithms. We have tested the code on Ubuntu 19.04, MacOS Mojave, and Windows 10.

rawabstract:
This project contains C and Java implementation of Ryu, as well as a C implementation of Ryu Printf. Ryu converts a floating point number to its shortest decimal representation, whereas Ryu Printf converts a floating point number according to the printf \%f or \%e format. At the time of this writing, these are the fastest known float-to-string conversion algorithms. We have tested the code on Ubuntu 19.04, MacOS Mojave, and Windows 10.

rawauthor:
Ulf Adams and Stephan T. Lavavej and Alexander Bolz and Vinnie Falco and David Tolnay and Mitchell {Blank, Jr.} and Mara Bos and Caleb Spare and Alexander Iljin

entry:
@Misc{Adams:2019:URP,
  author =       "Ulf Adams and Stephan T. Lavavej and Alexander Bolz
                 and Vinnie Falco and David Tolnay and Mitchell {Blank,
                 Jr.} and Mara Bos and Caleb Spare and Alexander Iljin",
  title =        "{ulfjack/ryu}: Printf Support",
  howpublished = "Web site",
  day =          "12",
  month =        aug,
  year =         "2019",
  DOI =          "https://doi.org/10.5281/zenodo.3366212",
  bibdate =      "Sun Aug 16 18:37:00 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/java2010.bib",
  URL =          "https://github.com/ulfjack/ryu/tree/v2.0;
                 https://zenodo.org/record/3366212",
  abstract =     "This project contains C and Java implementation of
                 Ryu, as well as a C implementation of Ryu Printf. Ryu
                 converts a floating point number to its shortest
                 decimal representation, whereas Ryu Printf converts a
                 floating point number according to the printf \%f or
                 \%e format. At the time of this writing, these are the
                 fastest known float-to-string conversion algorithms. We
                 have tested the code on Ubuntu 19.04, MacOS Mojave, and
                 Windows 10.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Agrawal:2019:DBF
title: DLFloat: A 16-b Floating Point Format Designed for Deep Learning Training and Inference
crossref: Takagi:2019:ISC
pages: 92--95
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00023
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawtitle: {DLFloat}: A 16-b Floating Point Format Designed for Deep Learning Training and Inference
author:
Ankur Agrawal and Silvia M. Mueller and Bruce M. Fleischer and Xiao Sun and Naigang Wang and Jungwook Choi and Kailash Gopalakrishnan

abstract:
The resilience of Deep Learning (DL) training and inference workloads to low-precision computations, coupled with the demand for power-and area-efficient hardware accelerators for these workloads, has led to the emergence of 16-bit floating point formats as the precision of choice for DL hardware accelerators. This paper describes our optimized 16-bit format that has 6 exponent bits and 9 fraction bits, derived from a study of the range of values encountered in DL applications. We demonstrate that our format preserves the accuracy of DL networks, and we compare its ease-of-use for DL against IEEE-754 half-precision (5 exponent bits and 10 fraction bits) and bfloat16 (8 exponent bits and 7 fraction bits). Further, our format eliminated sub-normals and simplifies rounding modes and handling of corner cases. This streamlines floating-point unit logic and enables realization of a compact power-efficient computation engine.

keywords:
16-b floating point format; 16-bit floating point formats; Adders; ARITH-26; compact power-efficient computation engine; Deep learning; deep learning training; DL hardware accelerators; Dynamic range; Engines; floating point arithmetic; floating-point unit logic; Hardware; IEEE-754 half-precision; Image recognition; learning (artificial intelligence); low-precision computations; neural nets; power-and area-efficient hardware accelerators; reduced precision computation, floating point, machine learning, deep learning; streamlines floating-point unit logic; Training

remark:
The DLFloat format has a 1-bit sign, 6-bit exponent, and 10-bit normalized significand including the hidden leading one-bit. Subnormals are not supported, and underflows flush to zero. Infinity and NaN are fused into a single value with the largest exponent and significand; other significands with that exponent are normal numbers. Zero and Inf-NaN are considered to be unsigned. There is only one rounding mode: round-nearest-up. Fused multiply-add (FMA) is supported.

rawabstract:
The resilience of Deep Learning (DL) training and inference workloads to low-precision computations, coupled with the demand for power-and area-efficient hardware accelerators for these workloads, has led to the emergence of 16-bit floating point formats as the precision of choice for DL hardware accelerators. This paper describes our optimized 16-bit format that has 6 exponent bits and 9 fraction bits, derived from a study of the range of values encountered in DL applications. We demonstrate that our format preserves the accuracy of DL networks, and we compare its ease-of-use for DL against IEEE-754 half-precision (5 exponent bits and 10 fraction bits) and bfloat16 (8 exponent bits and 7 fraction bits). Further, our format eliminated sub-normals and simplifies rounding modes and handling of corner cases. This streamlines floating-point unit logic and enables realization of a compact power-efficient computation engine.

rawauthor:
Ankur Agrawal and Silvia M. Mueller and Bruce M. Fleischer and Xiao Sun and Naigang Wang and Jungwook Choi and Kailash Gopalakrishnan

entry:
@InProceedings{Agrawal:2019:DBF,
  author =       "Ankur Agrawal and Silvia M. Mueller and Bruce M.
                 Fleischer and Xiao Sun and Naigang Wang and Jungwook
                 Choi and Kailash Gopalakrishnan",
  title =        "{DLFloat}: A 16-b Floating Point Format Designed for
                 Deep Learning Training and Inference",
  crossref =     "Takagi:2019:ISC",
  pages =        "92--95",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00023",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The resilience of Deep Learning (DL) training and
                 inference workloads to low-precision computations,
                 coupled with the demand for power-and area-efficient
                 hardware accelerators for these workloads, has led to
                 the emergence of 16-bit floating point formats as the
                 precision of choice for DL hardware accelerators. This
                 paper describes our optimized 16-bit format that has 6
                 exponent bits and 9 fraction bits, derived from a study
                 of the range of values encountered in DL applications.
                 We demonstrate that our format preserves the accuracy
                 of DL networks, and we compare its ease-of-use for DL
                 against IEEE-754 half-precision (5 exponent bits and 10
                 fraction bits) and bfloat16 (8 exponent bits and 7
                 fraction bits). Further, our format eliminated
                 sub-normals and simplifies rounding modes and handling
                 of corner cases. This streamlines floating-point unit
                 logic and enables realization of a compact
                 power-efficient computation engine.",
  acknowledgement = ack-nhfb,
  keywords =     "16-b floating point format; 16-bit floating point
                 formats; Adders; ARITH-26; compact power-efficient
                 computation engine; Deep learning; deep learning
                 training; DL hardware accelerators; Dynamic range;
                 Engines; floating point arithmetic; floating-point unit
                 logic; Hardware; IEEE-754 half-precision; Image
                 recognition; learning (artificial intelligence);
                 low-precision computations; neural nets; power-and
                 area-efficient hardware accelerators; reduced precision
                 computation, floating point, machine learning, deep
                 learning; streamlines floating-point unit logic;
                 Training",
  remark =       "The DLFloat format has a 1-bit sign, 6-bit exponent,
                 and 10-bit normalized significand including the hidden
                 leading one-bit. Subnormals are not supported, and
                 underflows flush to zero. Infinity and NaN are fused
                 into a single value with the largest exponent and
                 significand; other significands with that exponent are
                 normal numbers. Zero and Inf-NaN are considered to be
                 unsigned. There is only one rounding mode:
                 round-nearest-up. Fused multiply-add (FMA) is
                 supported.",
}


bibtype: inproceedings
filename: fparith.bib
label: Anderson:2019:SAM
author: Andrew Anderson and Michael Doyle and David Gregg
title: Scalar Arithmetic Multiple Data: Customizable Precision for Deep Neural Networks
crossref: Takagi:2019:ISC
pages: 61--68
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00018
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Andrew Anderson and Michael Doyle and David Gregg
rawtitle: Scalar Arithmetic Multiple Data: Customizable Precision for Deep Neural Networks
abstract:
Quantization of weights and activations in Deep Neural Networks (DNNs) is a powerful technique for network compression, and has enjoyed significant attention and success. However, much of the inference-time benefit of quantization is accessible only through customized hardware accelerators or with an FPGA implementation of quantized arithmetic. Building on prior work, we show how to construct very fast implementations of arbitrary bit-precise signed and unsigned integer operations using a software technique which logically embeds a vector architecture with custom bit-width lanes in fixed-width scalar arithmetic. At the strongest level of quantization, our approach yields a maximum speedup of $ approx 6 % $ on an x86 platform, and $ approx 10 % $ on an ARM platform versus quantization to native 8-bit integers.

keywords:
ARITH-26; bit-width lanes; Computer architecture; Custom Arithmetic; Deep Neural Networks; digital arithmetic; Field programmable gate arrays; field programmable gate arrays; fixed-width scalar arithmetic; FPGA implementation; Hardware; hardware accelerators; Machine Learning; network compression; neural nets; Program processors; quantisation (signal); quantization; Quantization (signal); quantized arithmetic; Registers; scalar arithmetic multiple data; Software Performance; software technique; vectors

rawabstract:
Quantization of weights and activations in Deep Neural Networks (DNNs) is a powerful technique for network compression, and has enjoyed significant attention and success. However, much of the inference-time benefit of quantization is accessible only through customized hardware accelerators or with an FPGA implementation of quantized arithmetic. Building on prior work, we show how to construct very fast implementations of arbitrary bit-precise signed and unsigned integer operations using a software technique which logically embeds a vector architecture with custom bit-width lanes in fixed-width scalar arithmetic. At the strongest level of quantization, our approach yields a maximum speedup of $ \approx 6 \% $ on an x86 platform, and $ \approx 10 \% $ on an ARM platform versus quantization to native 8-bit integers.

entry:
@InProceedings{Anderson:2019:SAM,
  author =       "Andrew Anderson and Michael Doyle and David Gregg",
  title =        "Scalar Arithmetic Multiple Data: Customizable
                 Precision for Deep Neural Networks",
  crossref =     "Takagi:2019:ISC",
  pages =        "61--68",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00018",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Quantization of weights and activations in Deep Neural
                 Networks (DNNs) is a powerful technique for network
                 compression, and has enjoyed significant attention and
                 success. However, much of the inference-time benefit of
                 quantization is accessible only through customized
                 hardware accelerators or with an FPGA implementation of
                 quantized arithmetic. Building on prior work, we show
                 how to construct very fast implementations of arbitrary
                 bit-precise signed and unsigned integer operations
                 using a software technique which logically embeds a
                 vector architecture with custom bit-width lanes in
                 fixed-width scalar arithmetic. At the strongest level
                 of quantization, our approach yields a maximum speedup
                 of $ \approx 6 \% $ on an x86 platform, and $ \approx
                 10 \% $ on an ARM platform versus quantization to
                 native 8-bit integers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; bit-width lanes; Computer architecture;
                 Custom Arithmetic; Deep Neural Networks; digital
                 arithmetic; Field programmable gate arrays; field
                 programmable gate arrays; fixed-width scalar
                 arithmetic; FPGA implementation; Hardware; hardware
                 accelerators; Machine Learning; network compression;
                 neural nets; Program processors; quantisation (signal);
                 quantization; Quantization (signal); quantized
                 arithmetic; Registers; scalar arithmetic multiple data;
                 Software Performance; software technique; vectors",
}


bibtype: inproceedings
filename: fparith.bib
label: Andrlon:2019:OBF
author: Mak Andrlon and Peter Schachte and Harald Sondergaard and Peter J. Stuckey
title: Optimal Bounds for Floating-Point Addition in Constant Time
crossref: Takagi:2019:ISC
pages: 159--166
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00038
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Mak Andrlon and Peter Schachte and Harald S{\o}ndergaard and Peter J. Stuckey
rawtitle: Optimal Bounds for Floating-Point Addition in Constant Time
abstract:
Reasoning about floating-point numbers is notoriously difficult, owing to the lack of convenient algebraic properties such as associativity. This poses a substantial challenge for program analysis and verification tools which rely on precise floating-point constraint solving. Currently, interval methods in this domain often exhibit slow convergence even on simple examples. We present a new theorem supporting efficient computation of exact bounds of the intersection of a rectangle with the preimage of an interval under floating-point addition, in any radix or rounding mode. We thus give an efficient method of deducing optimal bounds on the components of an addition, solving the convergence problem.

keywords:
addition; arbitrary radix; ARITH-26; Australia; bound analysis; constant time; constraint handling; convenient algebraic properties; Convergence; Digital arithmetic; exact bounds; floating point arithmetic; floating-point addition; Floating-point arithmetic; floating-point numbers; Information systems; interval methods; optimal bounds; precise floating-point constraint solving; program analysis; radix mode; rounding mode; Software; Standards

rawabstract:
Reasoning about floating-point numbers is notoriously difficult, owing to the lack of convenient algebraic properties such as associativity. This poses a substantial challenge for program analysis and verification tools which rely on precise floating-point constraint solving. Currently, interval methods in this domain often exhibit slow convergence even on simple examples. We present a new theorem supporting efficient computation of exact bounds of the intersection of a rectangle with the preimage of an interval under floating-point addition, in any radix or rounding mode. We thus give an efficient method of deducing optimal bounds on the components of an addition, solving the convergence problem.

entry:
@InProceedings{Andrlon:2019:OBF,
  author =       "Mak Andrlon and Peter Schachte and Harald
                 S{\o}ndergaard and Peter J. Stuckey",
  title =        "Optimal Bounds for Floating-Point Addition in Constant
                 Time",
  crossref =     "Takagi:2019:ISC",
  pages =        "159--166",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00038",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Reasoning about floating-point numbers is notoriously
                 difficult, owing to the lack of convenient algebraic
                 properties such as associativity. This poses a
                 substantial challenge for program analysis and
                 verification tools which rely on precise floating-point
                 constraint solving. Currently, interval methods in this
                 domain often exhibit slow convergence even on simple
                 examples. We present a new theorem supporting efficient
                 computation of exact bounds of the intersection of a
                 rectangle with the preimage of an interval under
                 floating-point addition, in any radix or rounding mode.
                 We thus give an efficient method of deducing optimal
                 bounds on the components of an addition, solving the
                 convergence problem.",
  acknowledgement = ack-nhfb,
  keywords =     "addition; arbitrary radix; ARITH-26; Australia; bound
                 analysis; constant time; constraint handling;
                 convenient algebraic properties; Convergence; Digital
                 arithmetic; exact bounds; floating point arithmetic;
                 floating-point addition; Floating-point arithmetic;
                 floating-point numbers; Information systems; interval
                 methods; optimal bounds; precise floating-point
                 constraint solving; program analysis; radix mode;
                 rounding mode; Software; Standards",
}


bibtype: article
filename: fparith.bib
label: Anonymous:2019:CPC
author: Anonymous
title: Computational `pathology' could hamper climate and fusion simulations
journal: j-PHYS-WORLD
pages: 159--166
day: 26
month: sep
monthnumber: 9
year: 2019
CODEN: PHWOEW
ISSN: 0953-8585 (print), 2058-7058 (electronic) OR 09538585 (print), 20587058 (electronic)
bibdate: Mon Sep 30 11:21:38 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.30 11:21:38 ???
note: See cite Boghosian:2019:NPS.
URL: https://physicsworld.com/a/computational-pathology-could-hamper-climate-and-fusion-simulations/
fjournal: Physics World
acknowledgement: ack-nhfb
journalURL: http://physicsworldarchive.iop.org/
rawauthor: Anonymous
rawnote: See \cite{Boghosian:2019:NPS}.
rawtitle: Computational `pathology' could hamper climate and fusion simulations
entry:
@Article{Anonymous:2019:CPC,
  author =       "Anonymous",
  title =        "Computational `pathology' could hamper climate and
                 fusion simulations",
  journal =      j-PHYS-WORLD,
  day =          "26",
  month =        sep,
  year =         "2019",
  CODEN =        "PHWOEW",
  ISSN =         "0953-8585 (print), 2058-7058 (electronic)",
  bibdate =      "Mon Sep 30 11:21:38 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Boghosian:2019:NPS}.",
  URL =          "https://physicsworld.com/a/computational-pathology-could-hamper-climate-and-fusion-simulations/",
  acknowledgement = ack-nhfb,
  fjournal =     "Physics World",
  journal-URL =  "http://physicsworldarchive.iop.org/",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2019:MCT
author: Anonymous
title: Multiprecision Computing Toolbox for MATLAB
pages: 159--166
day: 26
month: sep
monthnumber: 9
year: 2019
bibdate: Tue Nov 05 15:46:16 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib
bibtimestamp: 2019.11.05 15:46:16 ???
URL: https://www.advanpix.com/
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Anonymous
rawtitle: Multiprecision Computing Toolbox for {MATLAB}
entry:
@Misc{Anonymous:2019:MCT,
  author =       "Anonymous",
  title =        "Multiprecision Computing Toolbox for {MATLAB}",
  howpublished = "Web site",
  day =          "26",
  month =        sep,
  year =         "2019",
  bibdate =      "Tue Nov 05 15:46:16 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib",
  URL =          "https://www.advanpix.com/",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2019:RMV
author: Anonymous
title: Realtime Math v1.0 Open Sourced
pages: 159--166
day: 19
month: jan
monthnumber: 1
year: 2019
bibdate: Tue Jan 22 16:00:13 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.01.22 16:00:13 ???
URL: https://www.gamedev.net/news/realtime-math-v10-open-sourced-r740/
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Anonymous
rawtitle: {Realtime Math v1.0} Open Sourced
remark:
From the Web site: ``Realtime Math ldots consists entirely of C++11 headers, it runs almost everywhere, it supports 64 bit floating point arithmetic, and it sports a very permissive MIT license.''

entry:
@Misc{Anonymous:2019:RMV,
  author =       "Anonymous",
  title =        "{Realtime Math v1.0} Open Sourced",
  howpublished = "Web site",
  day =          "19",
  month =        jan,
  year =         "2019",
  bibdate =      "Tue Jan 22 16:00:13 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.gamedev.net/news/realtime-math-v10-open-sourced-r740/",
  acknowledgement = ack-nhfb,
  remark =       "From the Web site: ``Realtime Math \ldots{} consists
                 entirely of C++11 headers, it runs almost everywhere,
                 it supports 64 bit floating point arithmetic, and it
                 sports a very permissive MIT license.''",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2019:SOL
author: Anonymous
title: SiSoftware Official Live Ranker: Top Processor Arithmetic Ranks
pages: 159--166
year: 2019
bibdate: Fri May 24 07:49:33 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.05.24 07:49:33 ???
note: Floating-point performance ranking of more than 94,500 CPU models.
remark: In May 2019, the top 15 entries were Intel Xeon X-3175X and AMD Ryzen Threadripper CPUs.
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Anonymous
rawnote: Floating-point performance ranking of more than 94,500 CPU models.
rawtitle: {SiSoftware} Official Live Ranker: Top Processor Arithmetic Ranks
entry:
@Misc{Anonymous:2019:SOL,
  author =       "Anonymous",
  title =        "{SiSoftware} Official Live Ranker: Top Processor
                 Arithmetic Ranks",
  howpublished = "Web site",
  year =         "2019",
  bibdate =      "Fri May 24 07:49:33 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Floating-point performance ranking of more than 94,500
                 CPU models.",
  acknowledgement = ack-nhfb,
  remark =       "In May 2019, the top 15 entries were Intel Xeon
                 X-3175X and AMD Ryzen Threadripper CPUs.",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2019:UFP
author: Anonymous
pages: 136
day: 14
month: aug
monthnumber: 8
year: 2019
bibdate: Fri Aug 30 07:24:55 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.08.30 07:24:55 ???
acknowledgement: ack-nhfb
howpublished: Attorney Docket No. 6324-5986
rawauthor: Anonymous
title:
Universal floating-point instruction set architecture, method, and language for computing directly with decimal character sequences and binary formats in any combination

URL:
https://drive.google.com/file/d/1-gx_P5vBRppa6T3rdv8h6RNXz2Q_ILwg/view; https://drive.google.com/file/d/1fOhVAwdhiebumKkgljKfLqyOaFpUDhQL/view

abstract:
A universal floating-point Instruction Set Architecture (ISA) and associated method and language. Using a single instruction, the universal floating-point ISA has the ability, in hardware, to compute directly with dual decimal character sequences up to IEEE 754-2008 ``H'' in length, without first having to explicitly perform a conversion-to-binary-format process in software before computing with these human-readable floating-point or integer representations. The ISA does not employ opcodes, but rather pushes and pulls ``gobs'' of data without the encumbering opcode fetch, decode, and execute bottleneck. Instead, the ISA employs stand-alone, memory-mapped operators, complete with their own pipeline that is completely decoupled from the processor's primary push-pull pipeline. The ISA employs special three-port, 1024-bit wide SRAMS; a special dual asymmetric system stack; memory-mapped stand-alone hardware operators with private result buffers having simultaneously readable side-A and side-B read ports; and dual hardware HconvertFromDecimalCharacter conversion operators.

rawabstract:
A universal floating-point Instruction Set Architecture (ISA) and associated method and language. Using a single instruction, the universal floating-point ISA has the ability, in hardware, to compute directly with dual decimal character sequences up to IEEE 754-2008 ``H'' in length, without first having to explicitly perform a conversion-to-binary-format process in software before computing with these human-readable floating-point or integer representations. The ISA does not employ opcodes, but rather pushes and pulls ``gobs'' of data without the encumbering opcode fetch, decode, and execute bottleneck. Instead, the ISA employs stand-alone, memory-mapped operators, complete with their own pipeline that is completely decoupled from the processor's primary push-pull pipeline. The ISA employs special three-port, 1024-bit wide SRAMS; a special dual asymmetric system stack; memory-mapped stand-alone hardware operators with private result buffers having simultaneously readable side-A and side-B read ports; and dual hardware HconvertFromDecimalCharacter conversion operators.

rawtitle:
Universal floating-point instruction set architecture, method, and language for computing directly with decimal character sequences and binary formats in any combination

entry:
@Misc{Anonymous:2019:UFP,
  author =       "Anonymous",
  title =        "Universal floating-point instruction set architecture,
                 method, and language for computing directly with
                 decimal character sequences and binary formats in any
                 combination",
  howpublished = "Attorney Docket No. 6324-5986",
  pages =        "136",
  day =          "14",
  month =        aug,
  year =         "2019",
  bibdate =      "Fri Aug 30 07:24:55 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://drive.google.com/file/d/1-gx_P5vBRppa6T3rdv8h6RNXz2Q_ILwg/view;
                 https://drive.google.com/file/d/1fOhVAwdhiebumKkgljKfLqyOaFpUDhQL/view",
  abstract =     "A universal floating-point Instruction Set
                 Architecture (ISA) and associated method and language.
                 Using a single instruction, the universal
                 floating-point ISA has the ability, in hardware, to
                 compute directly with dual decimal character sequences
                 up to IEEE 754-2008 ``H'' in length, without first
                 having to explicitly perform a
                 conversion-to-binary-format process in software before
                 computing with these human-readable floating-point or
                 integer representations. The ISA does not employ
                 opcodes, but rather pushes and pulls ``gobs'' of data
                 without the encumbering opcode fetch, decode, and
                 execute bottleneck. Instead, the ISA employs
                 stand-alone, memory-mapped operators, complete with
                 their own pipeline that is completely decoupled from
                 the processor's primary push-pull pipeline. The ISA
                 employs special three-port, 1024-bit wide SRAMS; a
                 special dual asymmetric system stack; memory-mapped
                 stand-alone hardware operators with private result
                 buffers having simultaneously readable side-A and
                 side-B read ports; and dual hardware
                 HconvertFromDecimalCharacter conversion operators.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2019:YAF
author: Anonymous
title: Yet another floating point tutorial
pages: 136
year: 2019
bibdate: Fri May 17 07:24:35 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.05.17 07:24:35 ???
URL: https://wordsandbuttons.online/yet_another_floating_point_tutorial.html
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Anonymous
rawtitle: Yet another floating point tutorial
entry:
@Misc{Anonymous:2019:YAF,
  author =       "Anonymous",
  title =        "Yet another floating point tutorial",
  howpublished = "Web site",
  year =         "2019",
  bibdate =      "Fri May 17 07:24:35 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://wordsandbuttons.online/yet_another_floating_point_tutorial.html",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Arnold:2019:UOD
author: Mark G. Arnold and Ioannis Kouretas and Vassilis Paliouras and John R. Cowles
title: Under- and Overflow Detection in the Residue Logarithmic Number System
crossref: Takagi:2019:ISC
pages: 112--115
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00030
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Mark G. Arnold and Ioannis Kouretas and Vassilis Paliouras and John R. Cowles
rawtitle: Under- and Overflow Detection in the Residue Logarithmic Number System
abstract:
The Residue Number System (RNS) offers fast and cheap carry-free integer arithmetic but has slow and expensive overflow detection. The Logarithmic Number System (LNS) offers fast real multiplication, division and powers with floating-point-like relative precision. The Residue Logarithmic Number System (RLNS) is a combination of the two systems that offers advantages for moderate-precision real applications where a-priori analysis allows under-and overflow to be ignored. An arithmetic hardware generator is essential because of the mathematical obscurity of combining RNS and LNS. Unfortunately, real applications often underflow. We consider options to deal with under-and overflow using the RLNSTool generator as a foundation.

keywords:
ARITH-26; Arithmetic Generator; carry-free integer arithmetic; Computational modeling; Delays; Digital arithmetic; dividing circuits; expensive overflow detection; fast carry-free integer arithmetic; floating point arithmetic; floating-point-like relative precision; Generators; Hardware; Hardware design languages; LNS; moderate-precision real applications; multiplying circuits; number theory; Overflow; Residue Logarithmic Number System; residue number systems; RNS; Wires

rawabstract:
The Residue Number System (RNS) offers fast and cheap carry-free integer arithmetic but has slow and expensive overflow detection. The Logarithmic Number System (LNS) offers fast real multiplication, division and powers with floating-point-like relative precision. The Residue Logarithmic Number System (RLNS) is a combination of the two systems that offers advantages for moderate-precision real applications where a-priori analysis allows under-and overflow to be ignored. An arithmetic hardware generator is essential because of the mathematical obscurity of combining RNS and LNS. Unfortunately, real applications often underflow. We consider options to deal with under-and overflow using the RLNSTool generator as a foundation.

entry:
@InProceedings{Arnold:2019:UOD,
  author =       "Mark G. Arnold and Ioannis Kouretas and Vassilis
                 Paliouras and John R. Cowles",
  title =        "Under- and Overflow Detection in the Residue
                 Logarithmic Number System",
  crossref =     "Takagi:2019:ISC",
  pages =        "112--115",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00030",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Residue Number System (RNS) offers fast and cheap
                 carry-free integer arithmetic but has slow and
                 expensive overflow detection. The Logarithmic Number
                 System (LNS) offers fast real multiplication, division
                 and powers with floating-point-like relative precision.
                 The Residue Logarithmic Number System (RLNS) is a
                 combination of the two systems that offers advantages
                 for moderate-precision real applications where a-priori
                 analysis allows under-and overflow to be ignored. An
                 arithmetic hardware generator is essential because of
                 the mathematical obscurity of combining RNS and LNS.
                 Unfortunately, real applications often underflow. We
                 consider options to deal with under-and overflow using
                 the RLNSTool generator as a foundation.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Arithmetic Generator; carry-free integer
                 arithmetic; Computational modeling; Delays; Digital
                 arithmetic; dividing circuits; expensive overflow
                 detection; fast carry-free integer arithmetic; floating
                 point arithmetic; floating-point-like relative
                 precision; Generators; Hardware; Hardware design
                 languages; LNS; moderate-precision real applications;
                 multiplying circuits; number theory; Overflow; Residue
                 Logarithmic Number System; residue number systems; RNS;
                 Wires",
}


bibtype: inproceedings
filename: fparith.bib
label: Arzelier:2019:EAE
author: Denis Arzelier and Florent Brehard and Mioara Joldes
title: Exchange Algorithm for Evaluation and Approximation Error-Optimized Polynomials
crossref: Takagi:2019:ISC
pages: 30--37
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00014
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Denis Arzelier and Florent Br{\'e}hard and Mioara Joldes
rawtitle: Exchange Algorithm for Evaluation and Approximation Error-Optimized Polynomials
abstract:
Machine implementation of mathematical functions often relies on polynomial approximations. The particularity is that rounding errors occur both when representing the polynomial coefficients on a finite number of bits, and when evaluating it in finite precision. Hence, for finding the best polynomial (for a given fixed degree, norm and interval), one has to consider both types of errors: approximation and evaluation. While efficient algorithms were already developed for taking into account the approximation error, the evaluation part is usually a posteriori handled, in an ad-hoc manner. Here, we formulate a semi-infinite linear optimization problem whose solution is the best polynomial with respect to the supremum norm of the sum of both errors. This problem is then solved with an iterative exchange algorithm, which can be seen as an extension of the well-known Remez algorithm. A discussion and comparison of the obtained results on different examples are finally presented.

keywords:
Approximation algorithms; Approximation error; approximation error; approximation error-optimized polynomials; ARITH-26; Digital arithmetic; evaluation error; exchange algorithm; function approximation; Indexes; Input variables; iterative exchange algorithm; iterative methods; learning (artificial intelligence); libm; linear programming; machine implementation; mathematical functions; mathematics computing; optimisation; Optimization; polynomial approximation; polynomial approximations; polynomial coefficients; Programming; remez algorithm; Remez algorithm; semi-infinite programming; semiinfinite linear optimization problem

rawabstract:
Machine implementation of mathematical functions often relies on polynomial approximations. The particularity is that rounding errors occur both when representing the polynomial coefficients on a finite number of bits, and when evaluating it in finite precision. Hence, for finding the best polynomial (for a given fixed degree, norm and interval), one has to consider both types of errors: approximation and evaluation. While efficient algorithms were already developed for taking into account the approximation error, the evaluation part is usually a posteriori handled, in an ad-hoc manner. Here, we formulate a semi-infinite linear optimization problem whose solution is the best polynomial with respect to the supremum norm of the sum of both errors. This problem is then solved with an iterative exchange algorithm, which can be seen as an extension of the well-known Remez algorithm. A discussion and comparison of the obtained results on different examples are finally presented.

entry:
@InProceedings{Arzelier:2019:EAE,
  author =       "Denis Arzelier and Florent Br{\'e}hard and Mioara
                 Joldes",
  title =        "Exchange Algorithm for Evaluation and Approximation
                 Error-Optimized Polynomials",
  crossref =     "Takagi:2019:ISC",
  pages =        "30--37",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00014",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Machine implementation of mathematical functions often
                 relies on polynomial approximations. The particularity
                 is that rounding errors occur both when representing
                 the polynomial coefficients on a finite number of bits,
                 and when evaluating it in finite precision. Hence, for
                 finding the best polynomial (for a given fixed degree,
                 norm and interval), one has to consider both types of
                 errors: approximation and evaluation. While efficient
                 algorithms were already developed for taking into
                 account the approximation error, the evaluation part is
                 usually a posteriori handled, in an ad-hoc manner.
                 Here, we formulate a semi-infinite linear optimization
                 problem whose solution is the best polynomial with
                 respect to the supremum norm of the sum of both errors.
                 This problem is then solved with an iterative exchange
                 algorithm, which can be seen as an extension of the
                 well-known Remez algorithm. A discussion and comparison
                 of the obtained results on different examples are
                 finally presented.",
  acknowledgement = ack-nhfb,
  keywords =     "Approximation algorithms; Approximation error;
                 approximation error; approximation error-optimized
                 polynomials; ARITH-26; Digital arithmetic; evaluation
                 error; exchange algorithm; function approximation;
                 Indexes; Input variables; iterative exchange algorithm;
                 iterative methods; learning (artificial intelligence);
                 libm; linear programming; machine implementation;
                 mathematical functions; mathematics computing;
                 optimisation; Optimization; polynomial approximation;
                 polynomial approximations; polynomial coefficients;
                 Programming; remez algorithm; Remez algorithm;
                 semi-infinite programming; semiinfinite linear
                 optimization problem",
}


bibtype: misc
filename: fparith.bib
label: Bailey:2019:AM
author: David H. Bailey
title: An $ n log (n) $ algorithm for multiplication
pages: 30--37
day: 12
month: apr
monthnumber: 4
year: 2019
bibdate: Fri Apr 12 14:14:40 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.04.12 14:14:40 ???
URL: https://mathscholar.org/2019/04/an-n-log-n-algorithm-for-multiplication/
remark: Description of research in cite Harvey:2019:IMT.
acknowledgement: ack-nhfb
howpublished: Math Scholar blog
rawauthor: David H. Bailey
rawtitle: An $ n \log (n) $ algorithm for multiplication
entry:
@Misc{Bailey:2019:AM,
  author =       "David H. Bailey",
  title =        "An $ n \log (n) $ algorithm for multiplication",
  howpublished = "Math Scholar blog",
  day =          "12",
  month =        apr,
  year =         "2019",
  bibdate =      "Fri Apr 12 14:14:40 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://mathscholar.org/2019/04/an-n-log-n-algorithm-for-multiplication/",
  acknowledgement = ack-nhfb,
  remark =       "Description of research in \cite{Harvey:2019:IMT}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Barthel:2019:SAM
author: Moritz Barthel and Pascal Seidel and Jochen Rust and Steffen Paul
booktitle: 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)
title: SORN Arithmetic for MIMO Symbol Detection --- Exploration of the Type-2 Unum Format
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--4
year: 2019
DOI: https://doi.org/10.1109/NEWCAS44328.2019.8961226
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawauthor: Moritz B{\"a}rthel and Pascal Seidel and Jochen Rust and Steffen Paul
rawbooktitle: {2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)}
rawtitle: {SORN} Arithmetic for {MIMO} Symbol Detection --- Exploration of the {Type-2} Unum Format
entry:
@InProceedings{Barthel:2019:SAM,
  author =       "Moritz B{\"a}rthel and Pascal Seidel and Jochen Rust
                 and Steffen Paul",
  booktitle =    "{2019 17th IEEE International New Circuits and Systems
                 Conference (NEWCAS)}",
  title =        "{SORN} Arithmetic for {MIMO} Symbol Detection ---
                 Exploration of the {Type-2} Unum Format",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/NEWCAS44328.2019.8961226",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Beame:2019:TVN
author: Paul Beame and Vincent Liew
title: Toward Verifying Nonlinear Integer Arithmetic
journal: j-J-ACM
volume: 66
number: 3
pages: 22:1--22:??
month: jun
monthnumber: 6
year: 2019
CODEN: JACOAH
DOI: https://doi.org/10.1145/3319396
ISSN: 0004-5411 (print), 1557-735X (electronic) OR 00045411 (print), 1557735X (electronic)
ISSNL: 0004-5411 OR 00045411
bibdate: Wed Oct 23 06:51:06 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jacm.bib
bibtimestamp: 2019.10.23 06:51:06 MDT
URL: https://dl.acm.org/ft_gateway.cfm?id=3319396
fjournal: Journal of the ACM
acknowledgement: ack-nhfb
articleno: 22
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J401
rawauthor: Paul Beame and Vincent Liew
rawtitle: Toward Verifying Nonlinear Integer Arithmetic
abstract:
We eliminate a key roadblock to efficient verification of nonlinear integer arithmetic using CDCL SAT solvers, by showing how to construct short resolution proofs for many properties of the most widely used multiplier circuits. Such short proofs were conjectured not to exist. More precisely, we give $ n^O (1) $ size regular resolution proofs for arbitrary degree $2$ identities on array, diagonal, and Booth multipliers and $ n^O(log n)$ size proofs for these identities on Wallace tree multipliers.

rawabstract:
We eliminate a key roadblock to efficient verification of nonlinear integer arithmetic using CDCL SAT solvers, by showing how to construct short resolution proofs for many properties of the most widely used multiplier circuits. Such short proofs were conjectured not to exist. More precisely, we give $ n^{O (1)} $ size regular resolution proofs for arbitrary degree $2$ identities on array, diagonal, and Booth multipliers and $ n^{O(\log n)}$ size proofs for these identities on Wallace tree multipliers.

entry:
@Article{Beame:2019:TVN,
  author =       "Paul Beame and Vincent Liew",
  title =        "Toward Verifying Nonlinear Integer Arithmetic",
  journal =      j-J-ACM,
  volume =       "66",
  number =       "3",
  pages =        "22:1--22:??",
  month =        jun,
  year =         "2019",
  CODEN =        "JACOAH",
  DOI =          "https://doi.org/10.1145/3319396",
  ISSN =         "0004-5411 (print), 1557-735X (electronic)",
  ISSN-L =       "0004-5411",
  bibdate =      "Wed Oct 23 06:51:06 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jacm.bib",
  URL =          "https://dl.acm.org/ft_gateway.cfm?id=3319396",
  abstract =     "We eliminate a key roadblock to efficient verification
                 of nonlinear integer arithmetic using CDCL SAT solvers,
                 by showing how to construct short resolution proofs for
                 many properties of the most widely used multiplier
                 circuits. Such short proofs were conjectured not to
                 exist. More precisely, we give $ n^{O (1)} $ size
                 regular resolution proofs for arbitrary degree $2$
                 identities on array, diagonal, and Booth multipliers
                 and $ n^{O(\log n)}$ size proofs for these identities
                 on Wallace tree multipliers.",
  acknowledgement = ack-nhfb,
  articleno =    "22",
  fjournal =     "Journal of the ACM",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J401",
}


bibtype: article
filename: fparith.bib
label: Bellal:2019:IAA
author: R. Bellal and E. Lamini and H. Belbachir and S. Tagzout and A. Belouchrani
title: Improved Affine Arithmetic-Based Precision Analysis for Polynomial Function Evaluation
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 5
pages: 702--712
month: may
monthnumber: 5
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2882537
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: R. Bellal and E. Lamini and H. Belbachir and S. Tagzout and A. Belouchrani
rawtitle: Improved Affine Arithmetic-Based Precision Analysis for Polynomial Function Evaluation
keywords:
affine arithmetic; affine arithmetic-based precision analysis; Compounds; degree-n polynomial Horner's rule; design phase; enhanced precision analysis; error propagating formula; fixed point arithmetic; Fixed-point arithmetic; fixed-point numbers; Hardware; hardware function evaluation; hardware implementations; hardware resources; Interpolation; iterative methods; optimisation; Optimization; polynomial approximation; polynomial function evaluation; polynomials; precision analysis; quantisation (signal); Quantization (signal); quantization error; Resource management; table lookup; tighter upper bound error; Upper bound; VLSI systems; word-length allocation; word-length optimization

entry:
@Article{Bellal:2019:IAA,
  author =       "R. Bellal and E. Lamini and H. Belbachir and S.
                 Tagzout and A. Belouchrani",
  title =        "Improved Affine Arithmetic-Based Precision Analysis
                 for Polynomial Function Evaluation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "5",
  pages =        "702--712",
  month =        may,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2882537",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "affine arithmetic; affine arithmetic-based precision
                 analysis; Compounds; degree-n polynomial Horner's rule;
                 design phase; enhanced precision analysis; error
                 propagating formula; fixed point arithmetic;
                 Fixed-point arithmetic; fixed-point numbers; Hardware;
                 hardware function evaluation; hardware implementations;
                 hardware resources; Interpolation; iterative methods;
                 optimisation; Optimization; polynomial approximation;
                 polynomial function evaluation; polynomials; precision
                 analysis; quantisation (signal); Quantization (signal);
                 quantization error; Resource management; table lookup;
                 tighter upper bound error; Upper bound; VLSI systems;
                 word-length allocation; word-length optimization",
}


bibtype: techreport
filename: fparith.bib
label: Blanchard:2019:MPB
author: Pierre Blanchard and Nicholas J. Higham and Florent Lopez and Theo Mary and Srikara Pranesh
title: Mixed Precision Block Fused Multiply-Add: Error Analysis and Application to GPU Tensor Cores
type: MIMS EPrint
number: 2019.18
institution: Manchester Institute for Mathematical Sciences, School of Mathematics, The University of Manchester
address: Manchester, UK
pages: 702--712
day: 24
month: sep
monthnumber: 9
year: 2019
ISSN: 1749-9097 OR 17499097
bibdate: Thu Dec 05 10:14:37 2019
bibtimestamp: 2019.12.05 10:14:37 ???
acknowledgement: ack-nhfb
rawauthor: Pierre Blanchard and Nicholas J. Higham and Florent Lopez and Theo Mary and Srikara Pranesh
rawtitle: Mixed Precision Block Fused Multiply-Add: Error Analysis and Application to {GPU} Tensor Cores
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://eprints.maths.manchester.ac.uk/2733/; https://en.wikipedia.org/wiki/Bfloat16_floating-point_format

abstract:
Computing units that carry out a fused multiply-add (FMA) operation with matrix arguments, referred to as tensor units by some vendors, have great potential for use in scientific computing. However, these units are inherently mixed precision and existing rounding error analyses do not support them. We consider a mixed precision block FMA that generalizes both the usual scalar FMA and existing tensor units. We describe how to exploit such a block FMA in the numerical linear algebra kernels of matrix multiplication and LU factorization and give rounding error analyses of both kernels. An important application is to GMRES-based iterative refinement with block FMAs, for which our analysis provides new insight. Our framework is applicable to the tensor core units in the NVIDIA Volta and Turing GPUs. For these we compare matrix multiplication and LU factorization with TC16 and TC32 forms of FMA, which differ in the precision used for the output of the tensor cores. Our experiments on an NVDIA V100 GPU confirm the predictions of the analysis that the TC32 variant is much more accurate than the TC16 one, while achieving almost the same performance.

keywords:
floating-point arithmetic; fused multiply-add; LU factorization; matrix multiplication; rounding error analysis, NVIDIA GPU; tensor cores

rawabstract:
Computing units that carry out a fused multiply-add (FMA) operation with matrix arguments, referred to as tensor units by some vendors, have great potential for use in scientific computing. However, these units are inherently mixed precision and existing rounding error analyses do not support them. We consider a mixed precision block FMA that generalizes both the usual scalar FMA and existing tensor units. We describe how to exploit such a block FMA in the numerical linear algebra kernels of matrix multiplication and LU factorization and give rounding error analyses of both kernels. An important application is to GMRES-based iterative refinement with block FMAs, for which our analysis provides new insight. Our framework is applicable to the tensor core units in the NVIDIA Volta and Turing GPUs. For these we compare matrix multiplication and LU factorization with TC16 and TC32 forms of FMA, which differ in the precision used for the output of the tensor cores. Our experiments on an NVDIA V100 GPU confirm the predictions of the analysis that the TC32 variant is much more accurate than the TC16 one, while achieving almost the same performance.

entry:
@TechReport{Blanchard:2019:MPB,
  author =       "Pierre Blanchard and Nicholas J. Higham and Florent
                 Lopez and Theo Mary and Srikara Pranesh",
  title =        "Mixed Precision Block Fused Multiply-Add: Error
                 Analysis and Application to {GPU} Tensor Cores",
  type =         "MIMS EPrint",
  number =       "2019.18",
  institution =  "Manchester Institute for Mathematical Sciences, School
                 of Mathematics, The University of Manchester",
  address =      "Manchester, UK",
  day =          "24",
  month =        sep,
  year =         "2019",
  ISSN =         "1749-9097",
  bibdate =      "Thu Dec 05 10:14:37 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://eprints.maths.manchester.ac.uk/2733/;
                 https://en.wikipedia.org/wiki/Bfloat16_floating-point_format",
  abstract =     "Computing units that carry out a fused multiply-add
                 (FMA) operation with matrix arguments, referred to as
                 tensor units by some vendors, have great potential for
                 use in scientific computing. However, these units are
                 inherently mixed precision and existing rounding error
                 analyses do not support them. We consider a mixed
                 precision block FMA that generalizes both the usual
                 scalar FMA and existing tensor units. We describe how
                 to exploit such a block FMA in the numerical linear
                 algebra kernels of matrix multiplication and LU
                 factorization and give rounding error analyses of both
                 kernels. An important application is to GMRES-based
                 iterative refinement with block FMAs, for which our
                 analysis provides new insight. Our framework is
                 applicable to the tensor core units in the NVIDIA Volta
                 and Turing GPUs. For these we compare matrix
                 multiplication and LU factorization with TC16 and TC32
                 forms of FMA, which differ in the precision used for
                 the output of the tensor cores. Our experiments on an
                 NVDIA V100 GPU confirm the predictions of the analysis
                 that the TC32 variant is much more accurate than the
                 TC16 one, while achieving almost the same
                 performance.",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point arithmetic; fused multiply-add; LU
                 factorization; matrix multiplication; rounding error
                 analysis, NVIDIA GPU; tensor cores",
}


bibtype: inproceedings
filename: fparith.bib
label: Bocco:2019:BAF
booktitle: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
title: Byte-Aware Floating-point Operations through a UNUM Computing Unit
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 323--328
year: 2019
DOI: https://doi.org/10.1109/VLSI-SoC.2019.8920387
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)}
rawtitle: Byte-Aware Floating-point Operations through a {UNUM} Computing Unit
author:
Andrea Bocco and Tiago T. Jost and Albert Cohen and Florent de Dinechin and Yves Durand and Christian Fabre

rawauthor:
Andrea Bocco and Tiago T. Jost and Albert Cohen and Florent de Dinechin and Yves Durand and Christian Fabre

entry:
@InProceedings{Bocco:2019:BAF,
  author =       "Andrea Bocco and Tiago T. Jost and Albert Cohen and
                 Florent de Dinechin and Yves Durand and Christian
                 Fabre",
  booktitle =    "{2019 IFIP/IEEE 27th International Conference on Very
                 Large Scale Integration (VLSI-SoC)}",
  title =        "Byte-Aware Floating-point Operations through a {UNUM}
                 Computing Unit",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "323--328",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/VLSI-SoC.2019.8920387",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Bocco:2019:DPN
author: Andrea Bocco and Yves Durand and Florent de Dinechin
title: Dynamic Precision Numerics Using a Variable-Precision UNUM Type I HW Coprocessor
crossref: Takagi:2019:ISC
pages: 104--107
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00028
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Andrea Bocco and Yves Durand and Florent de Dinechin
rawtitle: Dynamic Precision Numerics Using a Variable-Precision {UNUM Type I HW} Coprocessor
abstract:
A very large internal accumulation register has been proposed to increase the accuracy of scientific code. However, there is a general class of iterative kernels where a vector of high-precision data must be saved from one iteration to the next. Saving the large internal accumulator to memory is impractical in such cases. This work proposes a Variable Precision (VP) Floating Point (FP) arithmetic co-processor architecture based on RISC-V, which 1/ supports legacy IEEE formats for input and output variables, 2/ uses variable length internal registers (up to 512 bits of mantissa) for inner loop multiply-add and 3/ supports loads and stores of intermediate results to cache memory with a dynamically adjustable precision (up to 256 bits of mantissa). It exploits the UNUM type I floating point format, proposing solutions to address some of its pitfalls such as the variable latency of the internal operation, and the variable memory footprint of the intermediate variables. This work is integrated on FPGA and demonstrated on a representative example.

keywords:
ARITH-26; Arrays; cache storage; Computational modeling; coprocessors; Coprocessors; dynamic Precision numerics; field programmable gate arrays; floating point arithmetic; floating point arithmetic co-processor architecture; FPGA; internal accumulation register; iterative kernels; iterative methods; Kernel; Programming; reduced instruction set computing; Registers; RISC-V; Variable Precision; Variable precision, Floating-point, UNUM, Scientific computing, Instruction set design, Hardware architecture, RISC-V, Coprocessor, Multiple precision, FPGA, ASIC; variable-precision UNUM Type I HW coprocessor

rawabstract:
A very large internal accumulation register has been proposed to increase the accuracy of scientific code. However, there is a general class of iterative kernels where a vector of high-precision data must be saved from one iteration to the next. Saving the large internal accumulator to memory is impractical in such cases. This work proposes a Variable Precision (VP) Floating Point (FP) arithmetic co-processor architecture based on RISC-V, which 1/ supports legacy IEEE formats for input and output variables, 2/ uses variable length internal registers (up to 512 bits of mantissa) for inner loop multiply-add and 3/ supports loads and stores of intermediate results to cache memory with a dynamically adjustable precision (up to 256 bits of mantissa). It exploits the UNUM type I floating point format, proposing solutions to address some of its pitfalls such as the variable latency of the internal operation, and the variable memory footprint of the intermediate variables. This work is integrated on FPGA and demonstrated on a representative example.

entry:
@InProceedings{Bocco:2019:DPN,
  author =       "Andrea Bocco and Yves Durand and Florent de Dinechin",
  title =        "Dynamic Precision Numerics Using a Variable-Precision
                 {UNUM Type I HW} Coprocessor",
  crossref =     "Takagi:2019:ISC",
  pages =        "104--107",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00028",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A very large internal accumulation register has been
                 proposed to increase the accuracy of scientific code.
                 However, there is a general class of iterative kernels
                 where a vector of high-precision data must be saved
                 from one iteration to the next. Saving the large
                 internal accumulator to memory is impractical in such
                 cases. This work proposes a Variable Precision (VP)
                 Floating Point (FP) arithmetic co-processor
                 architecture based on RISC-V, which 1/ supports legacy
                 IEEE formats for input and output variables, 2/ uses
                 variable length internal registers (up to 512 bits of
                 mantissa) for inner loop multiply-add and 3/ supports
                 loads and stores of intermediate results to cache
                 memory with a dynamically adjustable precision (up to
                 256 bits of mantissa). It exploits the UNUM type I
                 floating point format, proposing solutions to address
                 some of its pitfalls such as the variable latency of
                 the internal operation, and the variable memory
                 footprint of the intermediate variables. This work is
                 integrated on FPGA and demonstrated on a representative
                 example.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Arrays; cache storage; Computational
                 modeling; coprocessors; Coprocessors; dynamic Precision
                 numerics; field programmable gate arrays; floating
                 point arithmetic; floating point arithmetic
                 co-processor architecture; FPGA; internal accumulation
                 register; iterative kernels; iterative methods; Kernel;
                 Programming; reduced instruction set computing;
                 Registers; RISC-V; Variable Precision; Variable
                 precision, Floating-point, UNUM, Scientific computing,
                 Instruction set design, Hardware architecture, RISC-V,
                 Coprocessor, Multiple precision, FPGA, ASIC;
                 variable-precision UNUM Type I HW coprocessor",
}


bibtype: inproceedings
filename: fparith.bib
label: Bocco:2019:SSM
author: Andrea Bocco and Yves Durand and Florent de Dinechin
title: SMURF: Scalar Multiple-precision Unum RISC-V Floating-point Accelerator for Scientific Computing
crossref: Gustafson:2019:CPC
pages: 1:1--1:8
year: 2019
DOI: https://doi.org/10.1145/3316279.3316280
bibdate: Mon Feb 10 09:31:49 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2020.02.10 09:31:49 ???
URL: https://hal.inria.fr/hal-02087098
acknowledgement: ack-nhfb
articleno: 1
rawauthor: Andrea Bocco and Yves Durand and Florent de Dinechin
abstract:
This paper proposes an innovative Floating Point (FP) architecture for Variable Precision (VP) computation suitable for high precision FP computing, based on a refined version of the UNUM type I format. This architecture supports VP FP intervals where each interval endpoint can have up to 512 bits of mantissa. The proposed hardware architecture is pipelined and has an internal word-size of 64 bits. Computations on longer mantissas are performed iteratively on the existing hardware. The prototype is integrated in a RISC-V environment, it is exposed to the user through an instruction set extension. The paper we provide an example of software usage. The system has been prototyped on a FPGA (Field-Programmable Gate Array) platform and also synthesized for a 28nm FDSOI process technology. The respective working frequency of FPGA and ASIC implementations are 50MHz and 600MHz. The estimated chip area is 1.5mm 2 and the estimated power consumption is 95mW. The flops performance of this architecture remains within the range of a regular fixed-precision IEEE FPU while enabling arbitrary precision computation at reasonable cost.

keywords:
ASIC, UNUM, Floating-point, RISC-V, Coprocessor, Instruction set design, Variable precision, Scientific computing, Hardware architecture, Multiple precision, FPGA

rawabstract:
This paper proposes an innovative Floating Point (FP) architecture for Variable Precision (VP) computation suitable for high precision FP computing, based on a refined version of the UNUM type I format. This architecture supports VP FP intervals where each interval endpoint can have up to 512 bits of mantissa. The proposed hardware architecture is pipelined and has an internal word-size of 64 bits. Computations on longer mantissas are performed iteratively on the existing hardware. The prototype is integrated in a RISC-V environment, it is exposed to the user through an instruction set extension. The paper we provide an example of software usage. The system has been prototyped on a FPGA (Field-Programmable Gate Array) platform and also synthesized for a 28nm FDSOI process technology. The respective working frequency of FPGA and ASIC implementations are 50MHz and 600MHz. The estimated chip area is 1.5mm 2 and the estimated power consumption is 95mW. The flops performance of this architecture remains within the range of a regular fixed-precision IEEE FPU while enabling arbitrary precision computation at reasonable cost.

rawtitle:
{SMURF}: {Scalar Multiple-precision Unum RISC-V Floating-point} Accelerator for Scientific Computing

entry:
@InProceedings{Bocco:2019:SSM,
  author =       "Andrea Bocco and Yves Durand and Florent de Dinechin",
  title =        "{SMURF}: {Scalar Multiple-precision Unum RISC-V
                 Floating-point} Accelerator for Scientific Computing",
  crossref =     "Gustafson:2019:CPC",
  pages =        "1:1--1:8",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316280",
  bibdate =      "Mon Feb 10 09:31:49 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://hal.inria.fr/hal-02087098",
  abstract =     "This paper proposes an innovative Floating Point (FP)
                 architecture for Variable Precision (VP) computation
                 suitable for high precision FP computing, based on a
                 refined version of the UNUM type I format. This
                 architecture supports VP FP intervals where each
                 interval endpoint can have up to 512 bits of mantissa.
                 The proposed hardware architecture is pipelined and has
                 an internal word-size of 64 bits. Computations on
                 longer mantissas are performed iteratively on the
                 existing hardware. The prototype is integrated in a
                 RISC-V environment, it is exposed to the user through
                 an instruction set extension. The paper we provide an
                 example of software usage. The system has been
                 prototyped on a FPGA (Field-Programmable Gate Array)
                 platform and also synthesized for a 28nm FDSOI process
                 technology. The respective working frequency of FPGA
                 and ASIC implementations are 50MHz and 600MHz. The
                 estimated chip area is 1.5mm 2 and the estimated power
                 consumption is 95mW. The flops performance of this
                 architecture remains within the range of a regular
                 fixed-precision IEEE FPU while enabling arbitrary
                 precision computation at reasonable cost.",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  keywords =     "ASIC, UNUM, Floating-point, RISC-V, Coprocessor,
                 Instruction set design, Variable precision, Scientific
                 computing, Hardware architecture, Multiple precision,
                 FPGA",
}


bibtype: article
filename: fparith.bib
label: Boghosian:2019:NPS
author: Bruce M. Boghosian and Peter V. Coveney and Hongyan Wang
title: A New Pathology in the Simulation of Chaotic Dynamical Systems on Digital Computers
journal: j-ADV-THEORY-SIMUL
pages: 1900125
month: sep
monthnumber: 9
year: 2019
CODEN: ATSDCW
DOI: https://doi.org/10.1002/adts.201900125
ISSN: 2513-0390 OR 25130390
bibdate: Tue Sep 24 05:31:42 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.24 05:31:42 ???
URL: https://onlinelibrary.wiley.com/journal/25130390
fjournal: Advanced Theory and Simulations
acknowledgement: ack-nhfb
ajournal: Adv. Theory Simul.
journalURL: https://onlinelibrary.wiley.com/journal/25130390
rawauthor: Bruce M. Boghosian and Peter V. Coveney and Hongyan Wang
rawtitle: A New Pathology in the Simulation of Chaotic Dynamical Systems on Digital Computers
note:
See also news releases cite Caygill:2019:NLH,Caygill:2019:DCF,Silver:2019:CCN,Anonymous:2019:CPC,Dockrill:2019:CMH,Grossman:2019:CSC.

abstract:
Systematic distortions are uncovered in the statistical properties of chaotic dynamical systems when represented and simulated on digital computers using standard IEEE floating-point numbers. This is done by studying a model chaotic dynamical system with a single free parameter $ beta $, known as the generalized Bernoulli map, many of whose exact properties are known. Much of the structure of the dynamical system is lost in the floating-point representation. For even integer values of the parameter, the long time behaviour is completely wrong, subsuming the known anomalous behaviour for $ beta = 2 $. For non-integer $ beta $, relative errors in observables can reach 14%. For odd integer values of $ beta $, floating-point results are more accurate, but still produce relative errors two orders of magnitude larger than those attributable to roundoff. The analysis indicates that the pathology described, which cannot be mitigated by increasing the precision of the floating point numbers, is a representative example of a deeper problem in the computation of expectation values for chaotic systems. The findings sound a warning about the uncritical application of numerical methods in studies of the statistical properties of chaotic dynamical systems, such as are routinely performed throughout computational science, including turbulence and molecular dynamics.

remark:
This study demonstrates the perils of computing with too few significant digits in the floating-point representation. However, the authors report: ``Though the root of this problem resides in the use of finite-precision floating-point arithmetic, it cannot be mitigated by increasing the precision of the floating-point representation. Our analysis strongly suggests that the pathology we describe will exhibit for mantissa and exponent fields of any finite length whatsoever, and for floating-point numbers encoded in any radix whatsoever. Indeed, there is every reason to anticipate that this anomalous behaviour is generic in dissipative chaotic systems of the kind encountered in turbulence and molecular dynamics, and that it is entirely possible that many published results of numerical simulation are substantially inaccurate for this reason.''

rawabstract:
Systematic distortions are uncovered in the statistical properties of chaotic dynamical systems when represented and simulated on digital computers using standard IEEE floating-point numbers. This is done by studying a model chaotic dynamical system with a single free parameter $ \beta $, known as the generalized Bernoulli map, many of whose exact properties are known. Much of the structure of the dynamical system is lost in the floating-point representation. For even integer values of the parameter, the long time behaviour is completely wrong, subsuming the known anomalous behaviour for $ \beta = 2 $. For non-integer $ \beta $, relative errors in observables can reach 14\%. For odd integer values of $ \beta $, floating-point results are more accurate, but still produce relative errors two orders of magnitude larger than those attributable to roundoff. The analysis indicates that the pathology described, which cannot be mitigated by increasing the precision of the floating point numbers, is a representative example of a deeper problem in the computation of expectation values for chaotic systems. The findings sound a warning about the uncritical application of numerical methods in studies of the statistical properties of chaotic dynamical systems, such as are routinely performed throughout computational science, including turbulence and molecular dynamics.

rawnote:
See also news releases \cite{Caygill:2019:NLH,Caygill:2019:DCF,Silver:2019:CCN,Anonymous:2019:CPC,Dockrill:2019:CMH,Grossman:2019:CSC}.

entry:
@Article{Boghosian:2019:NPS,
  author =       "Bruce M. Boghosian and Peter V. Coveney and Hongyan
                 Wang",
  title =        "A New Pathology in the Simulation of Chaotic Dynamical
                 Systems on Digital Computers",
  journal =      j-ADV-THEORY-SIMUL,
  pages =        "1900125",
  month =        sep,
  year =         "2019",
  CODEN =        "ATSDCW",
  DOI =          "https://doi.org/10.1002/adts.201900125",
  ISSN =         "2513-0390",
  bibdate =      "Tue Sep 24 05:31:42 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See also news releases
                 \cite{Caygill:2019:NLH,Caygill:2019:DCF,Silver:2019:CCN,Anonymous:2019:CPC,Dockrill:2019:CMH,Grossman:2019:CSC}.",
  URL =          "https://onlinelibrary.wiley.com/journal/25130390",
  abstract =     "Systematic distortions are uncovered in the
                 statistical properties of chaotic dynamical systems
                 when represented and simulated on digital computers
                 using standard IEEE floating-point numbers. This is
                 done by studying a model chaotic dynamical system with
                 a single free parameter $ \beta $, known as the
                 generalized Bernoulli map, many of whose exact
                 properties are known. Much of the structure of the
                 dynamical system is lost in the floating-point
                 representation. For even integer values of the
                 parameter, the long time behaviour is completely wrong,
                 subsuming the known anomalous behaviour for $ \beta = 2
                 $. For non-integer $ \beta $, relative errors in
                 observables can reach 14\%. For odd integer values of $
                 \beta $, floating-point results are more accurate, but
                 still produce relative errors two orders of magnitude
                 larger than those attributable to roundoff. The
                 analysis indicates that the pathology described, which
                 cannot be mitigated by increasing the precision of the
                 floating point numbers, is a representative example of
                 a deeper problem in the computation of expectation
                 values for chaotic systems. The findings sound a
                 warning about the uncritical application of numerical
                 methods in studies of the statistical properties of
                 chaotic dynamical systems, such as are routinely
                 performed throughout computational science, including
                 turbulence and molecular dynamics.",
  acknowledgement = ack-nhfb,
  ajournal =     "Adv. Theory Simul.",
  fjournal =     "Advanced Theory and Simulations",
  journal-URL =  "https://onlinelibrary.wiley.com/journal/25130390",
  remark =       "This study demonstrates the perils of computing with
                 too few significant digits in the floating-point
                 representation. However, the authors report: ``Though
                 the root of this problem resides in the use of
                 finite-precision floating-point arithmetic, it cannot
                 be mitigated by increasing the precision of the
                 floating-point representation. Our analysis strongly
                 suggests that the pathology we describe will exhibit
                 for mantissa and exponent fields of any finite length
                 whatsoever, and for floating-point numbers encoded in
                 any radix whatsoever. Indeed, there is every reason to
                 anticipate that this anomalous behaviour is generic in
                 dissipative chaotic systems of the kind encountered in
                 turbulence and molecular dynamics, and that it is
                 entirely possible that many published results of
                 numerical simulation are substantially inaccurate for
                 this reason.''",
}


bibtype: article
filename: fparith.bib
label: Borges:2019:IAH
author: Carlos F. Borges
title: An Improved Algorithm for tt hypot(a,b)
journal: arXiv.org
pages: 1--15
day: 14
month: jun
monthnumber: 6
year: 2019
bibdate: Fri Apr 19 05:40:55 2024
bibtimestamp: 2024.04.19 05:40:55 ???
URL: https://arxiv.org/abs/1904.09481
acknowledgement: ack-nhfb
rawauthor: Carlos F. Borges
rawtitle: An Improved Algorithm for {\tt hypot(a,b)}
abstract:
We develop a fast and accurate algorithm for evaluating $ sqrt x^2 + y^2 $ for two floating point numbers $a$ and $b$. Library functions that perform this computation are generally named tt hypot(a,b). We will compare four approaches that we will develop in this paper to the current resident library function that is delivered with Julia 1.1 and to the code that has been distributed with the C math library for decades. We will demonstrate the performance of our algorithms by simulation.

rawabstract:
We develop a fast and accurate algorithm for evaluating $ \sqrt {x^2 + y^2} $ for two floating point numbers $a$ and $b$. Library functions that perform this computation are generally named {\tt hypot(a,b)}. We will compare four approaches that we will develop in this paper to the current resident library function that is delivered with Julia 1.1 and to the code that has been distributed with the C math library for decades. We will demonstrate the performance of our algorithms by simulation.

entry:
@Article{Borges:2019:IAH,
  author =       "Carlos F. Borges",
  title =        "An Improved Algorithm for {\tt hypot(a,b)}",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--15",
  day =          "14",
  month =        jun,
  year =         "2019",
  bibdate =      "Fri Apr 19 05:40:55 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1904.09481",
  abstract =     "We develop a fast and accurate algorithm for
                 evaluating $ \sqrt {x^2 + y^2} $ for two floating point
                 numbers $a$ and $b$. Library functions that perform
                 this computation are generally named {\tt hypot(a,b)}.
                 We will compare four approaches that we will develop in
                 this paper to the current resident library function
                 that is delivered with Julia 1.1 and to the code that
                 has been distributed with the C math library for
                 decades. We will demonstrate the performance of our
                 algorithms by simulation.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Bos:2019:ACI
author: J. W. Bos and S. J. Friedberger
title: Arithmetic Considerations for Isogeny-Based Cryptography
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 7
pages: 979--990
month: jul
monthnumber: 7
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2851238
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. W. Bos and S. J. Friedberger
rawtitle: Arithmetic Considerations for Isogeny-Based Cryptography
bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib

keywords:
arithmetic; arithmetic considerations; arithmetic techniques; Computer architecture; cryptographic protocols; curve models; digital arithmetic; efficient addition-subtraction chains; efficient arithmetic modulo; efficient chains; elliptic curve scalar multiplication; Elliptic curves; isogeny-based cryptography; Montgomery curves; Montgomery reduction; NIST; Optimization; post-quantum public-key arena; Protocols; Public key cryptography; quadratic extension field; scalar multiplication arithmetic; SIDH setting; special shape; supersingular isogeny Diffie-Hellman key-exchange protocol; systematic overview; twisted Edwards curves

entry:
@Article{Bos:2019:ACI,
  author =       "J. W. Bos and S. J. Friedberger",
  title =        "Arithmetic Considerations for Isogeny-Based
                 Cryptography",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "7",
  pages =        "979--990",
  month =        jul,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2851238",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "arithmetic; arithmetic considerations; arithmetic
                 techniques; Computer architecture; cryptographic
                 protocols; curve models; digital arithmetic; efficient
                 addition-subtraction chains; efficient arithmetic
                 modulo; efficient chains; elliptic curve scalar
                 multiplication; Elliptic curves; isogeny-based
                 cryptography; Montgomery curves; Montgomery reduction;
                 NIST; Optimization; post-quantum public-key arena;
                 Protocols; Public key cryptography; quadratic extension
                 field; scalar multiplication arithmetic; SIDH setting;
                 special shape; supersingular isogeny Diffie-Hellman
                 key-exchange protocol; systematic overview; twisted
                 Edwards curves",
}


bibtype: misc
filename: fparith.bib
label: Bright:2019:CEN
author: Peter Bright
pages: 979--990
day: 7
month: mar
monthnumber: 3
year: 2019
bibdate: Fri Mar 08 07:46:06 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.03.08 07:46:06 ???
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Peter Bright
title:
tt calc.exe is now open source; there's surprising depth in its ancient code. The actual calculation engine is more than 20 years old

URL:
https://arstechnica.com/gadgets/2019/03/calc-exe-is-now-open-source-theres-surprising-depth-in-its-ancient-code/; https://github.com/Microsoft/calculator

abstract:
Microsoft's embrace and adoption of open source software has continued with the surprising decision to publish the code for Windows Calculator and release it on GitHub under the permissive MIT license.

rawabstract:
Microsoft's embrace and adoption of open source software has continued with the surprising decision to publish the code for Windows Calculator and release it on GitHub under the permissive MIT license.

rawtitle:
{\tt calc.exe} is now open source; there's surprising depth in its ancient code. {The} actual calculation engine is more than 20 years old

entry:
@Misc{Bright:2019:CEN,
  author =       "Peter Bright",
  title =        "{\tt calc.exe} is now open source; there's surprising
                 depth in its ancient code. {The} actual calculation
                 engine is more than 20 years old",
  howpublished = "Web site",
  day =          "7",
  month =        mar,
  year =         "2019",
  bibdate =      "Fri Mar 08 07:46:06 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arstechnica.com/gadgets/2019/03/calc-exe-is-now-open-source-theres-surprising-depth-in-its-ancient-code/;
                 https://github.com/Microsoft/calculator",
  abstract =     "Microsoft's embrace and adoption of open source
                 software has continued with the surprising decision to
                 publish the code for Windows Calculator and release it
                 on GitHub under the permissive MIT license.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Brown:2019:RCF
author: Erin Clare Brown
title: Rust and C++ on Floating-point Intensive Code
pages: 979--990
day: 19
month: oct
monthnumber: 10
year: 2019
bibdate: Fri Oct 25 06:25:15 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.25 06:25:15 ???
URL: https://upshed.com/2019/10/24/rust-and-c-on-floating-point-intensive-code/
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Erin Clare Brown
rawtitle: {Rust} and {C++} on Floating-point Intensive Code
entry:
@Misc{Brown:2019:RCF,
  author =       "Erin Clare Brown",
  title =        "{Rust} and {C++} on Floating-point Intensive Code",
  howpublished = "Web site.",
  day =          "19",
  month =        oct,
  year =         "2019",
  bibdate =      "Fri Oct 25 06:25:15 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://upshed.com/2019/10/24/rust-and-c-on-floating-point-intensive-code/",
  acknowledgement = ack-nhfb,
}


