# bibtab

bibtype: article
filename: fparith.bib
label: Sherman:2019:SRS
author: Benjamin Sherman and Jesse Michel and Michael Carbin
title: Sound and robust solid modeling via exact real arithmetic and continuity
journal: j-PACMPL
volume: 3
number: ICFP
pages: 99:1--99:29
month: jul
monthnumber: 7
year: 2019
DOI: https://doi.org/10.1145/3341703
ISSN: 2475-1421 OR 24751421
bibdate: Fri Aug 7 19:22:28 MDT 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pacmpl.bib
bibtimestamp: 2020.08.07 19:22:28 MDT
URL: https://dl.acm.org/doi/abs/10.1145/3341703
fjournal: Proceedings of the ACM on Programming Languages
acknowledgement: ack-nhfb
articleno: 99
journalURL: https://pacmpl.acm.org/
rawauthor: Benjamin Sherman and Jesse Michel and Michael Carbin
rawtitle: Sound and robust solid modeling via exact real arithmetic and continuity
abstract:
Algorithms for solid modeling, i.e., Computer-Aided Design (CAD) and computer graphics, are often specified on real numbers and then implemented with finite-precision arithmetic, such as floating-point. The result is that these implementations do not soundly compute the results that are expected from their specifications.par We present a new library, StoneWorks, that provides sound and robust solid modeling primitives. We implement StoneWorks in MarshallB, a pure functional programming language for exact real arithmetic in which types denote topological spaces and functions denote continuous maps, ensuring that all programs are sound and robust. We developed MarshallB as an extension of the Marshall language.par We also define a new shape representation, compact representation (K-rep), that enables constructions such as Minkowski sum and analyses such as Hausdorff distance that are not possible with traditional representations. K-rep is a nondeterminism monad for describing all the points in a shape.par With our library, language, and representation together, we show that short StoneWorks programs can specify and execute sound and robust solid modeling algorithms and tasks.

rawabstract:
Algorithms for solid modeling, i.e., Computer-Aided Design (CAD) and computer graphics, are often specified on real numbers and then implemented with finite-precision arithmetic, such as floating-point. The result is that these implementations do not soundly compute the results that are expected from their specifications.\par We present a new library, StoneWorks, that provides sound and robust solid modeling primitives. We implement StoneWorks in MarshallB, a pure functional programming language for exact real arithmetic in which types denote topological spaces and functions denote continuous maps, ensuring that all programs are sound and robust. We developed MarshallB as an extension of the Marshall language.\par We also define a new shape representation, compact representation (K-rep), that enables constructions such as Minkowski sum and analyses such as Hausdorff distance that are not possible with traditional representations. K-rep is a nondeterminism monad for describing all the points in a shape.\par With our library, language, and representation together, we show that short StoneWorks programs can specify and execute sound and robust solid modeling algorithms and tasks.

entry:
@Article{Sherman:2019:SRS,
  author =       "Benjamin Sherman and Jesse Michel and Michael Carbin",
  title =        "Sound and robust solid modeling via exact real
                 arithmetic and continuity",
  journal =      j-PACMPL,
  volume =       "3",
  number =       "ICFP",
  pages =        "99:1--99:29",
  month =        jul,
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3341703",
  ISSN =         "2475-1421",
  bibdate =      "Fri Aug 7 19:22:28 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pacmpl.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3341703",
  abstract =     "Algorithms for solid modeling, i.e., Computer-Aided
                 Design (CAD) and computer graphics, are often specified
                 on real numbers and then implemented with
                 finite-precision arithmetic, such as floating-point.
                 The result is that these implementations do not soundly
                 compute the results that are expected from their
                 specifications.\par

                 We present a new library, StoneWorks, that provides
                 sound and robust solid modeling primitives. We
                 implement StoneWorks in MarshallB, a pure functional
                 programming language for exact real arithmetic in which
                 types denote topological spaces and functions denote
                 continuous maps, ensuring that all programs are sound
                 and robust. We developed MarshallB as an extension of
                 the Marshall language.\par

                 We also define a new shape representation, compact
                 representation (K-rep), that enables constructions such
                 as Minkowski sum and analyses such as Hausdorff
                 distance that are not possible with traditional
                 representations. K-rep is a nondeterminism monad for
                 describing all the points in a shape.\par

                 With our library, language, and representation
                 together, we show that short StoneWorks programs can
                 specify and execute sound and robust solid modeling
                 algorithms and tasks.",
  acknowledgement = ack-nhfb,
  articleno =    "99",
  fjournal =     "Proceedings of the ACM on Programming Languages",
  journal-URL =  "https://pacmpl.acm.org/",
}


bibtype: misc
filename: fparith.bib
label: Silver:2019:CCN
author: Mike Silver and Kalimah Redd Knight
title: Cutting Corners on Numbers
pages: 99:1--99:29
day: 24
month: sep
monthnumber: 9
year: 2019
bibdate: Wed Sep 25 10:47:09 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.25 10:47:09 ???
note: See cite Boghosian:2019:NPS.
URL: https://now.tufts.edu/articles/cutting-corners-numbers-computation
acknowledgement: ack-nhfb
howpublished: TuftsNow Web site.
rawauthor: Mike Silver and Kalimah Redd Knight
rawnote: See \cite{Boghosian:2019:NPS}.
rawtitle: Cutting Corners on Numbers
abstract:
Tufts mathematicians find the way we represent numbers in computers can lead to large computational errors, especially for modeling dynamical systems.

rawabstract:
Tufts mathematicians find the way we represent numbers in computers can lead to large computational errors, especially for modeling dynamical systems.

entry:
@Misc{Silver:2019:CCN,
  author =       "Mike Silver and Kalimah Redd Knight",
  title =        "Cutting Corners on Numbers",
  howpublished = "TuftsNow Web site.",
  day =          "24",
  month =        sep,
  year =         "2019",
  bibdate =      "Wed Sep 25 10:47:09 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Boghosian:2019:NPS}.",
  URL =          "https://now.tufts.edu/articles/cutting-corners-numbers-computation",
  abstract =     "Tufts mathematicians find the way we represent numbers
                 in computers can lead to large computational errors,
                 especially for modeling dynamical systems.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Singh:2019:LPP
booktitle: Embedded Computer Systems: Architectures, Modeling, and Simulation
title: Low Precision Processing for High Order Stencil Computations
publisher: pub-SV
address: pub-SV:adr
pages: 403--415
year: 2019
DOI: https://doi.org/10.1007/978-3-030-27562-4_29
ISBN: 3-030-27562-0 OR 3030275620
ISBN13: 978-3-030-27562-4 OR 9783030275624
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawbooktitle: Embedded Computer Systems: Architectures, Modeling, and Simulation
rawtitle: Low Precision Processing for High Order Stencil Computations
author:
Gagandeep Singh and Dionysios Diamantopoulos and Sander Stuijk and Christoph Hagleitner and Henk Corporaal

rawauthor:
Gagandeep Singh and Dionysios Diamantopoulos and Sander Stuijk and Christoph Hagleitner and Henk Corporaal

entry:
@InProceedings{Singh:2019:LPP,
  author =       "Gagandeep Singh and Dionysios Diamantopoulos and
                 Sander Stuijk and Christoph Hagleitner and Henk
                 Corporaal",
  booktitle =    "Embedded Computer Systems: Architectures, Modeling,
                 and Simulation",
  title =        "Low Precision Processing for High Order Stencil
                 Computations",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "403--415",
  year =         "2019",
  DOI =          "https://doi.org/10.1007/978-3-030-27562-4_29",
  ISBN =         "3-030-27562-0",
  ISBN-13 =      "978-3-030-27562-4",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Solovyev:2019:REF
title: Rigorous Estimation of Floating-Point Round-Off Errors with Symbolic Taylor Expansions
journal: j-TOPLAS
volume: 41
number: 1
pages: 2:1--2:??
month: mar
monthnumber: 3
year: 2019
CODEN: ATPSDT
DOI: https://doi.org/10.1145/3230733
ISSN: 0164-0925 (print), 1558-4593 (electronic) OR 01640925 (print), 15584593 (electronic)
ISSNL: 0164-0925 OR 01640925
bibdate: Mon Mar 4 08:35:09 MST 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toplas.bib
bibtimestamp: 2019.03.04 08:35:09 MST
URL: https://dl.acm.org/ft_gateway.cfm?id=3230733
fjournal: ACM Transactions on Programming Languages and Systems
acknowledgement: ack-nhfb
articleno: 2
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J783
rawtitle: Rigorous Estimation of Floating-Point Round-Off Errors with Symbolic {Taylor} Expansions
author:
Alexey Solovyev and Marek S. Baranowski and Ian Briggs and Charles Jacobsen and Zvonimir Rakamaric and Ganesh Gopalakrishnan

abstract:
Rigorous estimation of maximum floating-point round-off errors is an important capability central to many formal verification tools. Unfortunately, available techniques for this task often provide very pessimistic overestimates, causing unnecessary verification failure. We have developed a new approach called Symbolic Taylor Expansions that avoids these problems, and implemented a new tool called FPTaylor embodying this approach. Key to our approach is the use of rigorous global optimization, instead of the more familiar interval arithmetic, affine arithmetic, and/or SMT solvers. FPTaylor emits per-instance analysis certificates in the form of HOL Light proofs that can be machine checked. In this article, we present the basic ideas behind Symbolic Taylor Expansions in detail. We also survey as well as thoroughly evaluate six tool families, namely, Gappa (two tool options studied), Fluctuat, PRECiSA, Real2Float, Rosa, and FPTaylor (two tool options studied) on 24 examples, running on the same machine, and taking care to find the best options for running each of these tools. This study demonstrates that FPTaylor estimates round-off errors within much tighter bounds compared to other tools on a significant number of case studies. We also release FPTaylor along with our benchmarks, thus contributing to future studies and tool development in this area.

rawabstract:
Rigorous estimation of maximum floating-point round-off errors is an important capability central to many formal verification tools. Unfortunately, available techniques for this task often provide very pessimistic overestimates, causing unnecessary verification failure. We have developed a new approach called Symbolic Taylor Expansions that avoids these problems, and implemented a new tool called FPTaylor embodying this approach. Key to our approach is the use of rigorous global optimization, instead of the more familiar interval arithmetic, affine arithmetic, and/or SMT solvers. FPTaylor emits per-instance analysis certificates in the form of HOL Light proofs that can be machine checked. In this article, we present the basic ideas behind Symbolic Taylor Expansions in detail. We also survey as well as thoroughly evaluate six tool families, namely, Gappa (two tool options studied), Fluctuat, PRECiSA, Real2Float, Rosa, and FPTaylor (two tool options studied) on 24 examples, running on the same machine, and taking care to find the best options for running each of these tools. This study demonstrates that FPTaylor estimates round-off errors within much tighter bounds compared to other tools on a significant number of case studies. We also release FPTaylor along with our benchmarks, thus contributing to future studies and tool development in this area.

rawauthor:
Alexey Solovyev and Marek S. Baranowski and Ian Briggs and Charles Jacobsen and Zvonimir Rakamari{\'c} and Ganesh Gopalakrishnan

entry:
@Article{Solovyev:2019:REF,
  author =       "Alexey Solovyev and Marek S. Baranowski and Ian Briggs
                 and Charles Jacobsen and Zvonimir Rakamari{\'c} and
                 Ganesh Gopalakrishnan",
  title =        "Rigorous Estimation of Floating-Point Round-Off Errors
                 with Symbolic {Taylor} Expansions",
  journal =      j-TOPLAS,
  volume =       "41",
  number =       "1",
  pages =        "2:1--2:??",
  month =        mar,
  year =         "2019",
  CODEN =        "ATPSDT",
  DOI =          "https://doi.org/10.1145/3230733",
  ISSN =         "0164-0925 (print), 1558-4593 (electronic)",
  ISSN-L =       "0164-0925",
  bibdate =      "Mon Mar 4 08:35:09 MST 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toplas.bib",
  URL =          "https://dl.acm.org/ft_gateway.cfm?id=3230733",
  abstract =     "Rigorous estimation of maximum floating-point
                 round-off errors is an important capability central to
                 many formal verification tools. Unfortunately,
                 available techniques for this task often provide very
                 pessimistic overestimates, causing unnecessary
                 verification failure. We have developed a new approach
                 called Symbolic Taylor Expansions that avoids these
                 problems, and implemented a new tool called FPTaylor
                 embodying this approach. Key to our approach is the use
                 of rigorous global optimization, instead of the more
                 familiar interval arithmetic, affine arithmetic, and/or
                 SMT solvers. FPTaylor emits per-instance analysis
                 certificates in the form of HOL Light proofs that can
                 be machine checked. In this article, we present the
                 basic ideas behind Symbolic Taylor Expansions in
                 detail. We also survey as well as thoroughly evaluate
                 six tool families, namely, Gappa (two tool options
                 studied), Fluctuat, PRECiSA, Real2Float, Rosa, and
                 FPTaylor (two tool options studied) on 24 examples,
                 running on the same machine, and taking care to find
                 the best options for running each of these tools. This
                 study demonstrates that FPTaylor estimates round-off
                 errors within much tighter bounds compared to other
                 tools on a significant number of case studies. We also
                 release FPTaylor along with our benchmarks, thus
                 contributing to future studies and tool development in
                 this area.",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Transactions on Programming Languages and
                 Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J783",
}


bibtype: misc
filename: fparith.bib
label: Stephens:2019:BPN
author: Nigel Stephens
title: BFloat16 processing for Neural Networks on Armv8-A
pages: 2:1--2:??
day: 29
month: aug
monthnumber: 8
year: 2019
bibdate: Mon Sep 23 07:25:21 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.23 07:25:21 ???
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Nigel Stephens
rawtitle: {BFloat16} processing for Neural Networks on {Armv8-A}
URL:
https://community.arm.com/developer/ip-products/processors/b/ml-ip-blog/posts/bfloat16-processing-for-neural-networks-on-armv8_2d00_a

remark:
From the article: ``The next revision of the Armv8-A architecture will introduce Neon and SVE vector instructions designed to accelerate certain computations using the BFloat16 (BF16) floating-point number format. BF16 has recently emerged as a format tailored specifically to high-performance processing of Neural Networks (NNs). BF16 is a truncated form of the IEEE 754 [ieee754-2008] single-precision representation (IEEE-FP32), which has only 7 fraction bits, instead of 23.'' IEEE FP16 has 1-bit sign, 5-bit exponent, and 10-bit significand. BF16 has 1-bit sign, 8-bit exponent, and 7-bit significand. [This disagrees with cite Verheyde:2019:BDD, which says 5-bit exponent, and 10-bit significand.] The article also says that two instructions, BFDOT and BFMMLA have only one rounding mode: Round to Odd, one type of NaN, and flush-to-zero on underflow.

entry:
@Misc{Stephens:2019:BPN,
  author =       "Nigel Stephens",
  title =        "{BFloat16} processing for Neural Networks on
                 {Armv8-A}",
  howpublished = "Web site.",
  day =          "29",
  month =        aug,
  year =         "2019",
  bibdate =      "Mon Sep 23 07:25:21 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://community.arm.com/developer/ip-products/processors/b/ml-ip-blog/posts/bfloat16-processing-for-neural-networks-on-armv8_2d00_a",
  acknowledgement = ack-nhfb,
  remark =       "From the article: ``The next revision of the Armv8-A
                 architecture will introduce Neon and SVE vector
                 instructions designed to accelerate certain
                 computations using the BFloat16 (BF16) floating-point
                 number format. BF16 has recently emerged as a format
                 tailored specifically to high-performance processing of
                 Neural Networks (NNs). BF16 is a truncated form of the
                 IEEE 754 [ieee754-2008] single-precision representation
                 (IEEE-FP32), which has only 7 fraction bits, instead of
                 23.'' IEEE FP16 has 1-bit sign, 5-bit exponent, and
                 10-bit significand. BF16 has 1-bit sign, 8-bit
                 exponent, and 7-bit significand. [This disagrees with
                 \cite{Verheyde:2019:BDD}, which says 5-bit exponent,
                 and 10-bit significand.] The article also says that two
                 instructions, BFDOT and BFMMLA have only one rounding
                 mode: Round to Odd, one type of NaN, and flush-to-zero
                 on underflow.",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:AI
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Author Index
crossref: Takagi:2019:ISC
pages: 219--220
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00051
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Presents an index of the authors whose articles are published in the conference proceedings record.
keywords: ARITH-26
acknowledgement: ack-nhfb
rawabstract: Presents an index of the authors whose articles are published in the conference proceedings record.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Author Index
entry:
@InProceedings{Takagi:2019:AI,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Author Index",
  crossref =     "Takagi:2019:ISC",
  pages =        "219--220",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00051",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents an index of the authors whose articles are
                 published in the conference proceedings record.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:CN
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: [Copyright notice]
crossref: Takagi:2019:ISC
pages: 4--4
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00003
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Presents the copyright information for the conference. May include reprint permission information.
keywords: ARITH-26
acknowledgement: ack-nhfb
rawabstract: Presents the copyright information for the conference. May include reprint permission information.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: {[Copyright} notice]
entry:
@InProceedings{Takagi:2019:CN,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "{[Copyright} notice]",
  crossref =     "Takagi:2019:ISC",
  pages =        "4--4",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00003",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the copyright information for the conference.
                 May include reprint permission information.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:CO
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Conference Organization
crossref: Takagi:2019:ISC
pages: 11--11
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00006
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Provides a listing of current committee members and society officers.
keywords: ARITH-26
acknowledgement: ack-nhfb
rawabstract: Provides a listing of current committee members and society officers.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Conference Organization
entry:
@InProceedings{Takagi:2019:CO,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Conference Organization",
  crossref =     "Takagi:2019:ISC",
  pages =        "11--11",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00006",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Provides a listing of current committee members and
                 society officers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:F
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Foreword
crossref: Takagi:2019:ISC
pages: 10--10
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00005
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
keywords: ARITH-26
acknowledgement: ack-nhfb
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Foreword
abstract:
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.

entry:
@InProceedings{Takagi:2019:F,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Foreword",
  crossref =     "Takagi:2019:ISC",
  pages =        "10--10",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00005",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the introductory welcome message from the
                 conference proceedings. May include the conference
                 officers' congratulations to all involved with the
                 conference event and publication of the proceedings
                 record.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:PC
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Program Committee
crossref: Takagi:2019:ISC
pages: 12--12
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00007
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Provides a listing of current committee members and society officers.
keywords: ARITH-26
acknowledgement: ack-nhfb
rawabstract: Provides a listing of current committee members and society officers.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Program Committee
entry:
@InProceedings{Takagi:2019:PC,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Program Committee",
  crossref =     "Takagi:2019:ISC",
  pages =        "12--12",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00007",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Provides a listing of current committee members and
                 society officers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:Sa
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Sponsors
crossref: Takagi:2019:ISC
pages: 14--14
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00009
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: The conference organizers greatly appreciate the support of the various corporate sponsors listed.
keywords: ARITH-26
acknowledgement: ack-nhfb
rawabstract: The conference organizers greatly appreciate the support of the various corporate sponsors listed.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Sponsors
entry:
@InProceedings{Takagi:2019:Sa,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Sponsors",
  crossref =     "Takagi:2019:ISC",
  pages =        "14--14",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00009",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The conference organizers greatly appreciate the
                 support of the various corporate sponsors listed.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:Sb
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Supporters
crossref: Takagi:2019:ISC
pages: 15--15
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00010
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: The conference organizers greatly appreciate the support of the various corporate sponsors listed.
keywords: ARITH-26
acknowledgement: ack-nhfb
rawabstract: The conference organizers greatly appreciate the support of the various corporate sponsors listed.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Supporters
entry:
@InProceedings{Takagi:2019:Sb,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Supporters",
  crossref =     "Takagi:2019:ISC",
  pages =        "15--15",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00010",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The conference organizers greatly appreciate the
                 support of the various corporate sponsors listed.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:SC
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Steering Committee
crossref: Takagi:2019:ISC
pages: 13--13
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00008
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Provides a listing of current committee members and society officers.
keywords: ARITH-26
acknowledgement: ack-nhfb
rawabstract: Provides a listing of current committee members and society officers.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Steering Committee
entry:
@InProceedings{Takagi:2019:SC,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Steering Committee",
  crossref =     "Takagi:2019:ISC",
  pages =        "13--13",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00008",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Provides a listing of current committee members and
                 society officers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:TC
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: Table of contents
crossref: Takagi:2019:ISC
pages: 5--9
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00004
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Presents the table of contents/splash page of the proceedings record.
keywords: ARITH-26
acknowledgement: ack-nhfb
rawabstract: Presents the table of contents/splash page of the proceedings record.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: Table of contents
entry:
@InProceedings{Takagi:2019:TC,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "Table of contents",
  crossref =     "Takagi:2019:ISC",
  pages =        "5--9",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00004",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the table of contents/splash page of the
                 proceedings record.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Takagi:2019:TPI
author: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
title: [Title page iii]
crossref: Takagi:2019:ISC
pages: 3--3
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00002
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
abstract: Presents the title page of the proceedings record.
keywords: ARITH-26
acknowledgement: ack-nhfb
rawabstract: Presents the title page of the proceedings record.
rawauthor: Naofumi Takagi and Sylvie Boldo and Martin Langhammer
rawtitle: {[Title} page iii]
entry:
@InProceedings{Takagi:2019:TPI,
  author =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  title =        "{[Title} page iii]",
  crossref =     "Takagi:2019:ISC",
  pages =        "3--3",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00002",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the title page of the proceedings record.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26",
}


bibtype: inproceedings
filename: fparith.bib
label: Thibault:2019:OWL
author: Hilaire Thibault and Hacene Ouzia and Benoit Lopez
title: Optimal Word-Length Allocation for the Fixed-Point Implementation of Linear Filters and Controllers
crossref: Takagi:2019:ISC
pages: 175--182
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00040
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Hilaire Thibault and Hacene Ouzia and Benoit Lopez
rawtitle: Optimal Word-Length Allocation for the Fixed-Point Implementation of Linear Filters and Controllers
abstract:
This article presents a word-length optimization problem under accuracy constraints for the hardware implementation of linear signal processing systems with fixed-point arithmetic. For State-Space systems (describing a linear filter or a controller), a complete error analysis is exhibited, where the final output error bound depends on the word-lengths and the fixed-point formats chosen for each variable. The Most Significant Bit of each one can be determined in order to guarantee that no overflow occurs. Thus, it is possible to obtain a hardware implementation minimizing resource use. This leads to a convex nonlinear integer optimization problem where the resources to minimize and the accuracy constraints depend on the internal word-lengths. This problem can then be solved with appropriate heuristics. Finally, a global approach is proposed and illustrated by some examples.

keywords:
ARITH-26; convex nonlinear integer optimization problem; convex programming; error analysis; filters; fixed point arithmetic; fixed-point arithmetic; Hardware; hardware implementation; integer programming; linear filter; linear signal processing systems; nonlinear programming; optimal word-length allocation; Optimization; Quantization (signal); Roundoff errors; signal processing; Signal processing algorithms; state-space methods; state-space systems; word length optimization; word-length optimization problem; worst case MSB

rawabstract:
This article presents a word-length optimization problem under accuracy constraints for the hardware implementation of linear signal processing systems with fixed-point arithmetic. For State-Space systems (describing a linear filter or a controller), a complete error analysis is exhibited, where the final output error bound depends on the word-lengths and the fixed-point formats chosen for each variable. The Most Significant Bit of each one can be determined in order to guarantee that no overflow occurs. Thus, it is possible to obtain a hardware implementation minimizing resource use. This leads to a convex nonlinear integer optimization problem where the resources to minimize and the accuracy constraints depend on the internal word-lengths. This problem can then be solved with appropriate heuristics. Finally, a global approach is proposed and illustrated by some examples.

entry:
@InProceedings{Thibault:2019:OWL,
  author =       "Hilaire Thibault and Hacene Ouzia and Benoit Lopez",
  title =        "Optimal Word-Length Allocation for the Fixed-Point
                 Implementation of Linear Filters and Controllers",
  crossref =     "Takagi:2019:ISC",
  pages =        "175--182",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00040",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This article presents a word-length optimization
                 problem under accuracy constraints for the hardware
                 implementation of linear signal processing systems with
                 fixed-point arithmetic. For State-Space systems
                 (describing a linear filter or a controller), a
                 complete error analysis is exhibited, where the final
                 output error bound depends on the word-lengths and the
                 fixed-point formats chosen for each variable. The Most
                 Significant Bit of each one can be determined in order
                 to guarantee that no overflow occurs. Thus, it is
                 possible to obtain a hardware implementation minimizing
                 resource use. This leads to a convex nonlinear integer
                 optimization problem where the resources to minimize
                 and the accuracy constraints depend on the internal
                 word-lengths. This problem can then be solved with
                 appropriate heuristics. Finally, a global approach is
                 proposed and illustrated by some examples.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; convex nonlinear integer optimization
                 problem; convex programming; error analysis; filters;
                 fixed point arithmetic; fixed-point arithmetic;
                 Hardware; hardware implementation; integer programming;
                 linear filter; linear signal processing systems;
                 nonlinear programming; optimal word-length allocation;
                 Optimization; Quantization (signal); Roundoff errors;
                 signal processing; Signal processing algorithms;
                 state-space methods; state-space systems; word length
                 optimization; word-length optimization problem; worst
                 case MSB",
}


bibtype: inproceedings
filename: fparith.bib
label: Thomas:2019:CTG
author: David B. Thomas
title: Compile-Time Generation of Custom-Precision Floating-Point IP using HLS Tools
crossref: Takagi:2019:ISC
pages: 192--193
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00044
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: David B. Thomas
rawtitle: Compile-Time Generation of Custom-Precision Floating-Point {IP} using {HLS} Tools
abstract:
High-Level Synthesis (HLS) tools usually treat floating-point operators as black-box IP cores, and then schedule them as primitives when synthesising code to circuits. This approach relies on a library of IP blocks for chosen floating-point formats, which are pre-characterised to determine latency and area properties needed at compilation time. Two weaknesses of this approach are that it limits the number of floating-point formats - typically to half, single, and double - and that it requires conservative per-cycle scheduling of operators. Modern HLS tools have sophisticated intra-cycle scheduling of integer primitives, as well as C++ front-ends that can execute substantial algorithms at compile-time. This has enabled the creation of platform-independent C++ floating-point libraries which generate custom-precision operators at compile-time, while providing similar or better results as vendor-supplied IP blocks. However, certain problems and questions related to compilation performance and verification remain, so it is not yet clear how widely applicable this technique is.

keywords:
ARITH-26; black-box IP cores; C++; C++ languages; chosen floating-point formats; compilation performance; compilation time; Compile time IP; compile-time generation; custom-precision floating-point IP; custom-precision operators; field programmable gate arrays; Field programmable gate arrays; Floating point; floating point arithmetic; floating-point libraries; floating-point operators; FPGA; High Level Synthesis; high level synthesis; High-Level Synthesis tools; HLS; intra-cycle scheduling; IP networks; Libraries; Meta programming; modern HLS tools; Pipelines; Schedules; Templates; Tools; vendor-supplied IP blocks

rawabstract:
High-Level Synthesis (HLS) tools usually treat floating-point operators as black-box IP cores, and then schedule them as primitives when synthesising code to circuits. This approach relies on a library of IP blocks for chosen floating-point formats, which are pre-characterised to determine latency and area properties needed at compilation time. Two weaknesses of this approach are that it limits the number of floating-point formats - typically to half, single, and double - and that it requires conservative per-cycle scheduling of operators. Modern HLS tools have sophisticated intra-cycle scheduling of integer primitives, as well as C++ front-ends that can execute substantial algorithms at compile-time. This has enabled the creation of platform-independent C++ floating-point libraries which generate custom-precision operators at compile-time, while providing similar or better results as vendor-supplied IP blocks. However, certain problems and questions related to compilation performance and verification remain, so it is not yet clear how widely applicable this technique is.

entry:
@InProceedings{Thomas:2019:CTG,
  author =       "David B. Thomas",
  title =        "Compile-Time Generation of Custom-Precision
                 Floating-Point {IP} using {HLS} Tools",
  crossref =     "Takagi:2019:ISC",
  pages =        "192--193",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00044",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "High-Level Synthesis (HLS) tools usually treat
                 floating-point operators as black-box IP cores, and
                 then schedule them as primitives when synthesising code
                 to circuits. This approach relies on a library of IP
                 blocks for chosen floating-point formats, which are
                 pre-characterised to determine latency and area
                 properties needed at compilation time. Two weaknesses
                 of this approach are that it limits the number of
                 floating-point formats - typically to half, single, and
                 double - and that it requires conservative per-cycle
                 scheduling of operators. Modern HLS tools have
                 sophisticated intra-cycle scheduling of integer
                 primitives, as well as C++ front-ends that can execute
                 substantial algorithms at compile-time. This has
                 enabled the creation of platform-independent C++
                 floating-point libraries which generate
                 custom-precision operators at compile-time, while
                 providing similar or better results as vendor-supplied
                 IP blocks. However, certain problems and questions
                 related to compilation performance and verification
                 remain, so it is not yet clear how widely applicable
                 this technique is.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; black-box IP cores; C++; C++ languages;
                 chosen floating-point formats; compilation performance;
                 compilation time; Compile time IP; compile-time
                 generation; custom-precision floating-point IP;
                 custom-precision operators; field programmable gate
                 arrays; Field programmable gate arrays; Floating point;
                 floating point arithmetic; floating-point libraries;
                 floating-point operators; FPGA; High Level Synthesis;
                 high level synthesis; High-Level Synthesis tools; HLS;
                 intra-cycle scheduling; IP networks; Libraries; Meta
                 programming; modern HLS tools; Pipelines; Schedules;
                 Templates; Tools; vendor-supplied IP blocks",
}


bibtype: article
filename: fparith.bib
label: Tiwari:2019:PPE
author: Sugandha Tiwari and Neel Gala and Chester Rebeiro and V. Kamakoti
title: PERI: A Posit Enabled RISC-V Core
journal: arXiv.org
pages: 1--14
month: nov
monthnumber: 11
year: 2019
bibdate: Thu Apr 09 15:06:39 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.04.09 15:06:39 ???
URL: https://arxiv.org/pdf/1908.01466.pdf
keywords: floating-point; IEEE-754; Posit; processor; RISC-V
acknowledgement: ack-nhfb
rawauthor: Sugandha Tiwari and Neel Gala and Chester Rebeiro and V. Kamakoti
rawtitle: {PERI}: A Posit Enabled {RISC-V} Core
abstract:
Owing to the failure of Dennard's scaling the last decade has seen a steep growth of prominent new paradigms leveraging opportunities in computer architecture. Two technologies of interest are Posit and RISC-V. Posit was introduced in mid-2017 as a viable alternative to IEEE 754-2008. Posit promises more accuracy, higher dynamic range and fewer unused states along with simpler hardware designs as compared to IEEE 754- 2008. RISC-V, on the other hand, provides a commercial-grade open-source ISA. It is not only elegant and simple but also highly extensible and customizable, thereby facilitating novel micro-architectural research and exploration. In this paper, we bring these two technologies together and propose the first Posit Enabled RISC-V core. The paper provides insights on how the current 'F' extension and the custom op-code space of RISCV can be leveraged/modified to support Posit arithmetic. We also present implementation details of a parameterized and feature-complete Posit FPU which is integrated with the RISC-V compliant SHAKTI C-class core either as an execution unit or as an accelerator. To fully leverage the potential of Posit, we further enhance our Posit FPU, with minimal overheads, to support two different exponent sizes (with posit-size being 32-bits). This allows applications to switch from high-accuracy computation mode to a mode with higher dynamic-range at run-time. In the absence of viable software tool-chain to enable porting of applications in the Posit domain, we present a workaround on how certain applications can be modified minimally to exploit the existing RISC-V tool-chain. We also provide examples of applications which can perform better with Posit as compared to IEEE 754-2008. The proposed Posit FPU consumes 3507 slice LUTs and 1294 slice registers on an Artix-7-100T Xilinx FPGA while capable of operating at 100 MHz.

rawabstract:
Owing to the failure of Dennard's scaling the last decade has seen a steep growth of prominent new paradigms leveraging opportunities in computer architecture. Two technologies of interest are Posit and RISC-V. Posit was introduced in mid-2017 as a viable alternative to IEEE 754-2008. Posit promises more accuracy, higher dynamic range and fewer unused states along with simpler hardware designs as compared to IEEE 754- 2008. RISC-V, on the other hand, provides a commercial-grade open-source ISA. It is not only elegant and simple but also highly extensible and customizable, thereby facilitating novel micro-architectural research and exploration. In this paper, we bring these two technologies together and propose the first Posit Enabled RISC-V core. The paper provides insights on how the current 'F' extension and the custom op-code space of RISCV can be leveraged/modified to support Posit arithmetic. We also present implementation details of a parameterized and feature-complete Posit FPU which is integrated with the RISC-V compliant SHAKTI C-class core either as an execution unit or as an accelerator. To fully leverage the potential of Posit, we further enhance our Posit FPU, with minimal overheads, to support two different exponent sizes (with posit-size being 32-bits). This allows applications to switch from high-accuracy computation mode to a mode with higher dynamic-range at run-time. In the absence of viable software tool-chain to enable porting of applications in the Posit domain, we present a workaround on how certain applications can be modified minimally to exploit the existing RISC-V tool-chain. We also provide examples of applications which can perform better with Posit as compared to IEEE 754-2008. The proposed Posit FPU consumes 3507 slice LUTs and 1294 slice registers on an Artix-7-100T Xilinx FPGA while capable of operating at 100 MHz.

entry:
@Article{Tiwari:2019:PPE,
  author =       "Sugandha Tiwari and Neel Gala and Chester Rebeiro and
                 V. Kamakoti",
  title =        "{PERI}: A Posit Enabled {RISC-V} Core",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--14",
  month =        nov,
  year =         "2019",
  bibdate =      "Thu Apr 09 15:06:39 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/pdf/1908.01466.pdf",
  abstract =     "Owing to the failure of Dennard's scaling the last
                 decade has seen a steep growth of prominent new
                 paradigms leveraging opportunities in computer
                 architecture. Two technologies of interest are Posit
                 and RISC-V. Posit was introduced in mid-2017 as a
                 viable alternative to IEEE 754-2008. Posit promises
                 more accuracy, higher dynamic range and fewer unused
                 states along with simpler hardware designs as compared
                 to IEEE 754- 2008. RISC-V, on the other hand, provides
                 a commercial-grade open-source ISA. It is not only
                 elegant and simple but also highly extensible and
                 customizable, thereby facilitating novel
                 micro-architectural research and exploration. In this
                 paper, we bring these two technologies together and
                 propose the first Posit Enabled RISC-V core. The paper
                 provides insights on how the current 'F' extension and
                 the custom op-code space of RISCV can be
                 leveraged/modified to support Posit arithmetic. We also
                 present implementation details of a parameterized and
                 feature-complete Posit FPU which is integrated with the
                 RISC-V compliant SHAKTI C-class core either as an
                 execution unit or as an accelerator. To fully leverage
                 the potential of Posit, we further enhance our Posit
                 FPU, with minimal overheads, to support two different
                 exponent sizes (with posit-size being 32-bits). This
                 allows applications to switch from high-accuracy
                 computation mode to a mode with higher dynamic-range at
                 run-time. In the absence of viable software tool-chain
                 to enable porting of applications in the Posit domain,
                 we present a workaround on how certain applications can
                 be modified minimally to exploit the existing RISC-V
                 tool-chain. We also provide examples of applications
                 which can perform better with Posit as compared to IEEE
                 754-2008. The proposed Posit FPU consumes 3507 slice
                 LUTs and 1294 slice registers on an Artix-7-100T Xilinx
                 FPGA while capable of operating at 100 MHz.",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point; IEEE-754; Posit; processor; RISC-V",
}


bibtype: inproceedings
filename: fparith.bib
label: Uguen:2019:EHC
author: Yohann Uguen and Luc Forget and Florent de Dinechin
editor: IEEE
booktitle: 2019 29th International Conference on Field Programmable Logic and Applications (FPL)
title: Evaluating the Hardware Cost of the Posit Number System
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 106--113
year: 2019
DOI: https://doi.org/10.1109/FPL.2019.00026
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Yohann Uguen and Luc Forget and Florent de Dinechin
rawbooktitle: {2019 29th International Conference on Field Programmable Logic and Applications (FPL)}
raweditor: {IEEE}
rawtitle: Evaluating the Hardware Cost of the Posit Number System
entry:
@InProceedings{Uguen:2019:EHC,
  author =       "Yohann Uguen and Luc Forget and Florent de Dinechin",
  editor =       "{IEEE}",
  booktitle =    "{2019 29th International Conference on Field
                 Programmable Logic and Applications (FPL)}",
  title =        "Evaluating the Hardware Cost of the Posit Number
                 System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "106--113",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/FPL.2019.00026",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: vanDam:2019:APA
author: Laurens van Dam and Johan Peltenburg and Zaid Al-Ars and H. Peter Hofstee
title: An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM
crossref: Gustafson:2019:CPC
pages: 5:1--5:10
year: 2019
DOI: https://doi.org/10.1145/3316279.3316284
bibdate: Mon Feb 10 12:11:16 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 12:11:16 ???
keywords: pair-HMM, BLAS, decimal accuracy, arithmetic, unum-III, accelerator, posit, unum, FPGA
acknowledgement: ack-nhfb
articleno: 5
rawauthor: Laurens van Dam and Johan Peltenburg and Zaid Al-Ars and H. Peter Hofstee
rawtitle: An Accelerator for Posit Arithmetic Targeting Posit Level 1 {BLAS} Routines and {Pair-HMM}
entry:
@InProceedings{vanDam:2019:APA,
  author =       "Laurens van Dam and Johan Peltenburg and Zaid Al-Ars
                 and H. Peter Hofstee",
  title =        "An Accelerator for Posit Arithmetic Targeting Posit
                 Level 1 {BLAS} Routines and {Pair-HMM}",
  crossref =     "Gustafson:2019:CPC",
  pages =        "5:1--5:10",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316284",
  bibdate =      "Mon Feb 10 12:11:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  keywords =     "pair-HMM, BLAS, decimal accuracy, arithmetic,
                 unum-III, accelerator, posit, unum, FPGA",
  location =     "Singapore, Singapore",
  numpages =     "10",
}


bibtype: article
filename: fparith.bib
label: vanWyk:2019:RVT
author: Leonard van Wyk
title: Rounding versus truncation estimates in difference calculations
journal: j-MATH-GAZ
volume: 103
number: 557
pages: 285--292
month: jul
monthnumber: 7
year: 2019
CODEN: MAGAAS
DOI: https://doi.org/10.1017/mag.2019.60
ISSN: 0025-5572 (print), 2056-6328 (electronic) OR 00255572 (print), 20566328 (electronic)
ISSNL: 0025-5572 OR 00255572
bibdate: Mon Jul 22 08:44:42 MDT 2019
bibtimestamp: 2019.07.22 08:44:42 MDT
fjournal: The Mathematical Gazette
acknowledgement: ack-nhfb
ajournal: Math. Gaz.
onlinedate: 06 June 2019
rawauthor: Leonard van Wyk
rawtitle: Rounding versus truncation estimates in difference calculations
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathgaz2010.bib

URL:
https://www.cambridge.org/core/journals/mathematical-gazette/article/rounding-versus-truncation-estimates-in-difference-calculations/57BD92568C03F0FCDE63BBBDB5E6FF6D

abstract:
Two common methods of approximating difference problems are by rounding or truncating the minuend and the subtrahend before calculating the difference. Since rounding generally gives a better approximation of a number than truncation, one might expect that rounding also generally gives a better approximation in difference problems. We show that intuition to be false.

journalURL:
http://journals.cambridge.org/action/displayIssue?jid=MAG; http://www.m-a.org.uk/jsp/index.jsp?lnk=620

rawabstract:
Two common methods of approximating difference problems are by rounding or truncating the minuend and the subtrahend before calculating the difference. Since rounding generally gives a better approximation of a number than truncation, one might expect that rounding also generally gives a better approximation in difference problems. We show that intuition to be false.

entry:
@Article{vanWyk:2019:RVT,
  author =       "Leonard van Wyk",
  title =        "Rounding versus truncation estimates in difference
                 calculations",
  journal =      j-MATH-GAZ,
  volume =       "103",
  number =       "557",
  pages =        "285--292",
  month =        jul,
  year =         "2019",
  CODEN =        "MAGAAS",
  DOI =          "https://doi.org/10.1017/mag.2019.60",
  ISSN =         "0025-5572 (print), 2056-6328 (electronic)",
  ISSN-L =       "0025-5572",
  bibdate =      "Mon Jul 22 08:44:42 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathgaz2010.bib",
  URL =          "https://www.cambridge.org/core/journals/mathematical-gazette/article/rounding-versus-truncation-estimates-in-difference-calculations/57BD92568C03F0FCDE63BBBDB5E6FF6D",
  abstract =     "Two common methods of approximating difference
                 problems are by rounding or truncating the minuend and
                 the subtrahend before calculating the difference. Since
                 rounding generally gives a better approximation of a
                 number than truncation, one might expect that rounding
                 also generally gives a better approximation in
                 difference problems. We show that intuition to be
                 false.",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Gaz.",
  fjournal =     "The Mathematical Gazette",
  journal-URL =  "http://journals.cambridge.org/action/displayIssue?jid=MAG;
                 http://www.m-a.org.uk/jsp/index.jsp?lnk=620",
  onlinedate =   "06 June 2019",
}


bibtype: inproceedings
filename: fparith.bib
label: Vazquez:2019:NPT
author: Alvaro Vazquez and Elisardo Antelo
title: New $3$D Projection Transformation for Point Clouds
crossref: Takagi:2019:ISC
pages: 77--83
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00020
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Alvaro V{\'a}zquez and Elisardo Antelo
rawtitle: New {$3$D} Projection Transformation for Point Clouds
abstract:
3D Computer Graphics based on clouds of points is an alternative of interest for high quality rendering of complex scenes. For high quality graphics, the computational requirements are significantly higher than in the case of conventional front-end vertex processing. One of the key computations in the graphics pipeline is the projection transformation. Conventional computation of the point-based projection using current vertex processors might not be the best option for scalable, high quality 3D graphics based on point clouds. In this work we propose a new scalable method that takes advantage of the special characteristics of the point rendering model. The number of reciprocal/division computations for perspective correction is reduced, using instead more effective multiply-accumulate operations. This is done by performing a linear approximation of the reciprocal at the cost of introducing an error in the pixel value. There is a trade-off in the error introduced and the exactness of the computation (linear approximation instead of reciprocal).

keywords:
3D computer graphics; 3D projection transformation; ARITH-26; Cameras; complex geometry; computational geometry; graphics processor; high quality 3D graphics; Linear approximation; Point based rendering; point clouds; point rendering model; point-based projection; projection transform; Rendering (computer graphics); rendering (computer graphics); rendering quality; Three-dimensional displays; Upper bound; vertex processing; VLSI graphis hardware; Zirconium

rawabstract:
3D Computer Graphics based on clouds of points is an alternative of interest for high quality rendering of complex scenes. For high quality graphics, the computational requirements are significantly higher than in the case of conventional front-end vertex processing. One of the key computations in the graphics pipeline is the projection transformation. Conventional computation of the point-based projection using current vertex processors might not be the best option for scalable, high quality 3D graphics based on point clouds. In this work we propose a new scalable method that takes advantage of the special characteristics of the point rendering model. The number of reciprocal/division computations for perspective correction is reduced, using instead more effective multiply-accumulate operations. This is done by performing a linear approximation of the reciprocal at the cost of introducing an error in the pixel value. There is a trade-off in the error introduced and the exactness of the computation (linear approximation instead of reciprocal).

entry:
@InProceedings{Vazquez:2019:NPT,
  author =       "Alvaro V{\'a}zquez and Elisardo Antelo",
  title =        "New {$3$D} Projection Transformation for Point
                 Clouds",
  crossref =     "Takagi:2019:ISC",
  pages =        "77--83",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00020",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "3D Computer Graphics based on clouds of points is an
                 alternative of interest for high quality rendering of
                 complex scenes. For high quality graphics, the
                 computational requirements are significantly higher
                 than in the case of conventional front-end vertex
                 processing. One of the key computations in the graphics
                 pipeline is the projection transformation. Conventional
                 computation of the point-based projection using current
                 vertex processors might not be the best option for
                 scalable, high quality 3D graphics based on point
                 clouds. In this work we propose a new scalable method
                 that takes advantage of the special characteristics of
                 the point rendering model. The number of
                 reciprocal/division computations for perspective
                 correction is reduced, using instead more effective
                 multiply-accumulate operations. This is done by
                 performing a linear approximation of the reciprocal at
                 the cost of introducing an error in the pixel value.
                 There is a trade-off in the error introduced and the
                 exactness of the computation (linear approximation
                 instead of reciprocal).",
  acknowledgement = ack-nhfb,
  keywords =     "3D computer graphics; 3D projection transformation;
                 ARITH-26; Cameras; complex geometry; computational
                 geometry; graphics processor; high quality 3D graphics;
                 Linear approximation; Point based rendering; point
                 clouds; point rendering model; point-based projection;
                 projection transform; Rendering (computer graphics);
                 rendering (computer graphics); rendering quality;
                 Three-dimensional displays; Upper bound; vertex
                 processing; VLSI graphis hardware; Zirconium",
}


bibtype: article
filename: fparith.bib
label: Venkatachalam:2019:DAA
author: S. Venkatachalam and E. Adams and H. J. Lee and S. Ko
title: Design and Analysis of Area and Power Efficient Approximate Booth Multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 11
pages: 1697--1703
month: nov
monthnumber: 11
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2926275
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Oct 29 11:08:44 2019
bibtimestamp: 2019.10.29 11:08:44 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Venkatachalam and E. Adams and H. J. Lee and S. Ko
rawtitle: Design and Analysis of Area and Power Efficient Approximate {Booth} Multipliers
keywords:
Adders; Approximate Booth arithmetic; Complexity theory; Computational modeling; Digital signal processing; Encoding; Generators; inexact computing; Integrated circuit modeling; radix-4 partial product generators

entry:
@Article{Venkatachalam:2019:DAA,
  author =       "S. Venkatachalam and E. Adams and H. J. Lee and S.
                 Ko",
  title =        "Design and Analysis of Area and Power Efficient
                 Approximate {Booth} Multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "11",
  pages =        "1697--1703",
  month =        nov,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2926275",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Oct 29 11:08:44 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adders; Approximate Booth arithmetic; Complexity
                 theory; Computational modeling; Digital signal
                 processing; Encoding; Generators; inexact computing;
                 Integrated circuit modeling; radix-4 partial product
                 generators",
}


bibtype: misc
filename: fparith.bib
label: Verheyde:2019:BDD
author: Arne Verheyde
title: BFloat16 Deep Dive: ARM Brings BF16 Deep Learning Data Format to ARMv8-A
pages: 1697--1703
day: 21
month: sep
monthnumber: 9
year: 2019
bibdate: Mon Sep 23 07:15:36 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.23 07:15:36 ???
URL: https://www.tomshardware.com/news/bfloat16-deep-dive-arm-bf16-support-armv8-a,40305.html
acknowledgement: ack-nhfb
howpublished: Tom's Hardware Web site.
rawauthor: Arne Verheyde
rawtitle: {BFloat16} Deep Dive: {ARM} Brings {BF16} Deep Learning Data Format to {ARMv8-A}
abstract:
RM will be adding BFloat16 support in the next revision of the ARMv8-A architecture under its Project Trillium ML platform. It marks a new major milestone in the widespread adoption of the young data format that is taking the deep learning community by storm. In this article, we'll dive into the origins and benefits of the format.

remark:
The BFloat16 format has 1-bit sign, 5-bit exponent, and 10-bit significand. From the article: ``ldots hardware area (number of transistors) scales roughly with the square of the mantissa width. So having just three fewer mantissa bits (7 instead of 10) means that a bfloat16 multiplier takes up about half the area of a conventional FP16 unit. Compared to an FP32 multiplier, its size is eight times smaller, with an equivalent reduction in power consumption as well. Or conversely, within the same silicon area more useful hardware can be put to achieve higher performance. ldots Bfloat16 is called Brain Floating Point Format in full (or BF16 in short), as it is named after the Google Brain research group where it was conceived. As Jeff Dean, Senior Fellow of Google AI, explained in a series of Twitter posts, Google started using the format since the early days of TensorFlow. More specifically, it was supported in hardware since the second version of its Tensor Processing Units (TPUs), the TPU v2 in 2017. ldots Intel showed that an integer multiplier costs less than half the area of a floating point multiplier of the same number of bits. Though less relevant, the difference is even larger for addition: while an integer adder scales linearly with the number of bits, a floating point adder scales quadratically, ldots ''

rawabstract:
RM will be adding BFloat16 support in the next revision of the ARMv8-A architecture under its Project Trillium ML platform. It marks a new major milestone in the widespread adoption of the young data format that is taking the deep learning community by storm. In this article, we'll dive into the origins and benefits of the format.

entry:
@Misc{Verheyde:2019:BDD,
  author =       "Arne Verheyde",
  title =        "{BFloat16} Deep Dive: {ARM} Brings {BF16} Deep
                 Learning Data Format to {ARMv8-A}",
  howpublished = "Tom's Hardware Web site.",
  day =          "21",
  month =        sep,
  year =         "2019",
  bibdate =      "Mon Sep 23 07:15:36 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.tomshardware.com/news/bfloat16-deep-dive-arm-bf16-support-armv8-a,40305.html",
  abstract =     "RM will be adding BFloat16 support in the next
                 revision of the ARMv8-A architecture under its Project
                 Trillium ML platform. It marks a new major milestone in
                 the widespread adoption of the young data format that
                 is taking the deep learning community by storm. In this
                 article, we'll dive into the origins and benefits of
                 the format.",
  acknowledgement = ack-nhfb,
  remark =       "The BFloat16 format has 1-bit sign, 5-bit exponent,
                 and 10-bit significand. From the article: ``\ldots{}
                 hardware area (number of transistors) scales roughly
                 with the square of the mantissa width. So having just
                 three fewer mantissa bits (7 instead of 10) means that
                 a bfloat16 multiplier takes up about half the area of a
                 conventional FP16 unit. Compared to an FP32 multiplier,
                 its size is eight times smaller, with an equivalent
                 reduction in power consumption as well. Or conversely,
                 within the same silicon area more useful hardware can
                 be put to achieve higher performance. \ldots{} Bfloat16
                 is called Brain Floating Point Format in full (or BF16
                 in short), as it is named after the Google Brain
                 research group where it was conceived. As Jeff Dean,
                 Senior Fellow of Google AI, explained in a series of
                 Twitter posts, Google started using the format since
                 the early days of TensorFlow. More specifically, it was
                 supported in hardware since the second version of its
                 Tensor Processing Units (TPUs), the TPU v2 in 2017.
                 \ldots{} Intel showed that an integer multiplier costs
                 less than half the area of a floating point multiplier
                 of the same number of bits. Though less relevant, the
                 difference is even larger for addition: while an
                 integer adder scales linearly with the number of bits,
                 a floating point adder scales quadratically,
                 \ldots{}''",
}


bibtype: inproceedings
filename: fparith.bib
label: Villa:2019:NDB
author: Oreste Villa and Mark Stephenson and David Nellans and Stephen W. Keckler
editor: IEEE / ACM
title: Nvbit: A dynamic binary instrumentation framework for NVIDIA GPUs
publisher: pub-ACM
address: pub-ACM:adr
pages: 372--383
year: 2019
ISBN: 1-4503-6938-3 OR 1450369383
ISBN13: 978-1-4503-6938-1 OR 9781450369381
LCCN: QA76.6 .A568
bibdate: Mon Sep 11 07:23:59 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 07:23:59 ???
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1145/3352460
bookpages: 1104
rawauthor: Oreste Villa and Mark Stephenson and David Nellans and Stephen W. Keckler
raweditor: {IEEE\slash ACM}
rawtitle: {Nvbit}: A dynamic binary instrumentation framework for {NVIDIA GPUs}
booktitle:
MICRO '52: Proceedings of the 52nd Annual IEEE / ACM International Symposium on Microarchitecture, Columbus OH, USA, October 12--16, 2019

rawbooktitle:
{MICRO '52: Proceedings of the 52nd Annual IEEE\slash ACM International Symposium on Microarchitecture, Columbus OH, USA, October 12--16, 2019}

entry:
@InProceedings{Villa:2019:NDB,
  author =       "Oreste Villa and Mark Stephenson and David Nellans and
                 Stephen W. Keckler",
  editor =       "{IEEE\slash ACM}",
  booktitle =    "{MICRO '52: Proceedings of the 52nd Annual IEEE\slash
                 ACM International Symposium on Microarchitecture,
                 Columbus OH, USA, October 12--16, 2019}",
  title =        "{Nvbit}: A dynamic binary instrumentation framework
                 for {NVIDIA GPUs}",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  bookpages =    "1104",
  pages =        "372--383",
  year =         "2019",
  ISBN =         "1-4503-6938-3",
  ISBN-13 =      "978-1-4503-6938-1",
  LCCN =         "QA76.6 .A568",
  bibdate =      "Mon Sep 11 07:23:59 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1145/3352460",
}


bibtype: inproceedings
filename: fparith.bib
label: Villalba-Moreno:2019:RSU
author: Julio Villalba-Moreno and Javier Hormigo and Francisco Jaime
title: Reproducible Summation Under HUB Format
crossref: Takagi:2019:ISC
pages: 38--45
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00015
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Julio Villalba-Moreno and Javier Hormigo and Francisco Jaime
rawtitle: Reproducible Summation Under {HUB} Format
abstract:
Floating point reproducibility is a property claimed by programmers and end users. Half-Unit-Biased (HUB) is a new representation format in which the round to nearest is carried out by truncation, preventing any carry propagation and saving time and area. In this paper we study the reproducible summation of HUB numbers by using a error-free vector transformation technique, providing both a specific architecture and the usage of combined HUB/Standard floating point adders to achieve a reproducible result.

keywords:
adders; Adders; ARITH-26; carry propagation; Computer architecture; Computer science; Delays; Digital arithmetic; end users; error-free vector transformation technique; floating point arithmetic; Half-Unit-Biased; HUB (Half-Unit-Biased) floating-point format; HUB format; HUB numbers; point adders; point reproducibility; representation format; reproducible summation; Reproducible summation, HUB format; Standards; Terminology

rawabstract:
Floating point reproducibility is a property claimed by programmers and end users. Half-Unit-Biased (HUB) is a new representation format in which the round to nearest is carried out by truncation, preventing any carry propagation and saving time and area. In this paper we study the reproducible summation of HUB numbers by using a error-free vector transformation technique, providing both a specific architecture and the usage of combined HUB/Standard floating point adders to achieve a reproducible result.

entry:
@InProceedings{Villalba-Moreno:2019:RSU,
  author =       "Julio Villalba-Moreno and Javier Hormigo and Francisco
                 Jaime",
  title =        "Reproducible Summation Under {HUB} Format",
  crossref =     "Takagi:2019:ISC",
  pages =        "38--45",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00015",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Floating point reproducibility is a property claimed
                 by programmers and end users. Half-Unit-Biased (HUB) is
                 a new representation format in which the round to
                 nearest is carried out by truncation, preventing any
                 carry propagation and saving time and area. In this
                 paper we study the reproducible summation of HUB
                 numbers by using a error-free vector transformation
                 technique, providing both a specific architecture and
                 the usage of combined HUB/Standard floating point
                 adders to achieve a reproducible result.",
  acknowledgement = ack-nhfb,
  keywords =     "adders; Adders; ARITH-26; carry propagation; Computer
                 architecture; Computer science; Delays; Digital
                 arithmetic; end users; error-free vector transformation
                 technique; floating point arithmetic; Half-Unit-Biased;
                 HUB (Half-Unit-Biased) floating-point format; HUB
                 format; HUB numbers; point adders; point
                 reproducibility; representation format; reproducible
                 summation; Reproducible summation, HUB format;
                 Standards; Terminology",
}


bibtype: inproceedings
filename: fparith.bib
label: Volkova:2019:SAI
author: Anastasia Volkova and Jean-Michel Muller
title: Semi-Automatic Implementation of the Complementary Error Function
crossref: Takagi:2019:ISC
pages: 167--174
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00039
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Anastasia Volkova and Jean-Michel Muller
rawtitle: Semi-Automatic Implementation of the Complementary Error Function
abstract:
The normal and complementary error functions are ubiquitous special functions for any mathematical library. They have a wide range of applications. Practical applications call for customized implementations that have strict accuracy requirements. Accurate numerical implementation of these functions is, however, non-trivial. In particular, the complementary error function erfc for large positive arguments heavily suffers from cancellation, which is largely due to its asymptotic behavior. We provide a semi-automatic code generator for the erfc function which is parameterized by the user-given bound on the relative error. Our solution exploits the asymptotic expression of erfc and leverages the automatic code generator Metalibm that provides accurate polynomial approximations. A fine-grained a priori error analysis provides a libm developer with the required accuracy for each step of the evaluation. In critical parts, we exploit double-word arithmetic to achieve implementations that are fast, yet accurate up to 50 bits, even for large input arguments. We demonstrate that for high required accuracies the automatically generated code has performance comparable to that of the standard libm and for lower ones our code demonstrated roughly 25% speedup.

keywords:
a priori error analysis; ARITH-26; asymptotic behavior; asymptotic expression; complementary error functions; Digital arithmetic; Error analysis; error analysis; error function; floating-point arithmetic; Generators; Libraries; Lips; mathematical library; Metalibm; normal error functions; polynomial approximation; polynomial approximations; program compilers; semi-automated code generation; semiautomatic code generator; semiautomatic implementation; Standards; Tools; ubiquitous special functions

rawabstract:
The normal and complementary error functions are ubiquitous special functions for any mathematical library. They have a wide range of applications. Practical applications call for customized implementations that have strict accuracy requirements. Accurate numerical implementation of these functions is, however, non-trivial. In particular, the complementary error function erfc for large positive arguments heavily suffers from cancellation, which is largely due to its asymptotic behavior. We provide a semi-automatic code generator for the erfc function which is parameterized by the user-given bound on the relative error. Our solution exploits the asymptotic expression of erfc and leverages the automatic code generator Metalibm that provides accurate polynomial approximations. A fine-grained a priori error analysis provides a libm developer with the required accuracy for each step of the evaluation. In critical parts, we exploit double-word arithmetic to achieve implementations that are fast, yet accurate up to 50 bits, even for large input arguments. We demonstrate that for high required accuracies the automatically generated code has performance comparable to that of the standard libm and for lower ones our code demonstrated roughly 25\% speedup.

entry:
@InProceedings{Volkova:2019:SAI,
  author =       "Anastasia Volkova and Jean-Michel Muller",
  title =        "Semi-Automatic Implementation of the Complementary
                 Error Function",
  crossref =     "Takagi:2019:ISC",
  pages =        "167--174",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00039",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The normal and complementary error functions are
                 ubiquitous special functions for any mathematical
                 library. They have a wide range of applications.
                 Practical applications call for customized
                 implementations that have strict accuracy requirements.
                 Accurate numerical implementation of these functions
                 is, however, non-trivial. In particular, the
                 complementary error function erfc for large positive
                 arguments heavily suffers from cancellation, which is
                 largely due to its asymptotic behavior. We provide a
                 semi-automatic code generator for the erfc function
                 which is parameterized by the user-given bound on the
                 relative error. Our solution exploits the asymptotic
                 expression of erfc and leverages the automatic code
                 generator Metalibm that provides accurate polynomial
                 approximations. A fine-grained a priori error analysis
                 provides a libm developer with the required accuracy
                 for each step of the evaluation. In critical parts, we
                 exploit double-word arithmetic to achieve
                 implementations that are fast, yet accurate up to 50
                 bits, even for large input arguments. We demonstrate
                 that for high required accuracies the automatically
                 generated code has performance comparable to that of
                 the standard libm and for lower ones our code
                 demonstrated roughly 25\% speedup.",
  acknowledgement = ack-nhfb,
  keywords =     "a priori error analysis; ARITH-26; asymptotic
                 behavior; asymptotic expression; complementary error
                 functions; Digital arithmetic; Error analysis; error
                 analysis; error function; floating-point arithmetic;
                 Generators; Libraries; Lips; mathematical library;
                 Metalibm; normal error functions; polynomial
                 approximation; polynomial approximations; program
                 compilers; semi-automated code generation;
                 semiautomatic code generator; semiautomatic
                 implementation; Standards; Tools; ubiquitous special
                 functions",
}


bibtype: article
filename: fparith.bib
label: Walther:2019:VNR
author: Christoph Walther
title: Verified Newton--Raphson Iteration for Multiplicative Inverses Modulo Powers of Any Base
journal: j-TOMS
volume: 45
number: 1
pages: 9:1--9:7
month: mar
monthnumber: 3
year: 2019
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3301317
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Mon May 6 18:23:42 MDT 2019
bibtimestamp: 2019.05.06 18:23:42 MDT
note: See cite Dumas:2014:NRI.
URL: https://dl.acm.org/citation.cfm?id=3301317
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 9
journalURL: https://dl.acm.org/loi/toms
rawauthor: Christoph Walther
rawnote: See \cite{Dumas:2014:NRI}.
rawtitle: Verified {Newton--Raphson} Iteration for Multiplicative Inverses Modulo Powers of Any Base
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

abstract:
We identify two faults in a published algorithm for fast computation of multiplicative inverses modulo prime powers. We patch the algorithm and present machine-assisted proofs of correctness of the repair. Our formal proofs also reveal that being prime is an unnecessary demand for the power base, thus attributing a wider scope of applications to the repaired algorithm.

rawabstract:
We identify two faults in a published algorithm for fast computation of multiplicative inverses modulo prime powers. We patch the algorithm and present machine-assisted proofs of correctness of the repair. Our formal proofs also reveal that being prime is an unnecessary demand for the power base, thus attributing a wider scope of applications to the repaired algorithm.

entry:
@Article{Walther:2019:VNR,
  author =       "Christoph Walther",
  title =        "Verified {Newton--Raphson} Iteration for
                 Multiplicative Inverses Modulo Powers of Any Base",
  journal =      j-TOMS,
  volume =       "45",
  number =       "1",
  pages =        "9:1--9:7",
  month =        mar,
  year =         "2019",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3301317",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Mon May 6 18:23:42 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  note =         "See \cite{Dumas:2014:NRI}.",
  URL =          "https://dl.acm.org/citation.cfm?id=3301317",
  abstract =     "We identify two faults in a published algorithm for
                 fast computation of multiplicative inverses modulo
                 prime powers. We patch the algorithm and present
                 machine-assisted proofs of correctness of the repair.
                 Our formal proofs also reveal that being prime is an
                 unnecessary demand for the power base, thus attributing
                 a wider scope of applications to the repaired
                 algorithm.",
  acknowledgement = ack-nhfb,
  articleno =    "9",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: misc
filename: fparith.bib
label: Wang:2019:BSH
author: Shibo Wang and Pankaj Kanwar
title: BFloat16: The secret to high performance on Cloud TPUs
pages: 9:1--9:7
day: 23
month: aug
monthnumber: 8
year: 2019
bibdate: Fri Apr 03 09:12:39 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.04.03 09:12:39 ???
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Shibo Wang and Pankaj Kanwar
rawtitle: {BFloat16}: The secret to high performance on Cloud {TPUs}
URL:
https://cloud.google.com/blog/products/ai-machine-learning/bfloat16-the-secret-to-high-performance-on-cloud-tpus

entry:
@Misc{Wang:2019:BSH,
  author =       "Shibo Wang and Pankaj Kanwar",
  title =        "{BFloat16}: The secret to high performance on Cloud
                 {TPUs}",
  howpublished = "Web site",
  day =          "23",
  month =        aug,
  year =         "2019",
  bibdate =      "Fri Apr 03 09:12:39 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://cloud.google.com/blog/products/ai-machine-learning/bfloat16-the-secret-to-high-performance-on-cloud-tpus",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Wang:2019:PAA
author: Shouxiang Wang and Kai Wang and Lei Wu and Chengshan Wang
journal: j-TOMS
volume: 45
number: 1
pages: 6:1--6:29
month: mar
monthnumber: 3
year: 2019
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3274659
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Mon May 6 18:23:42 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2019.05.06 18:23:42 MDT
URL: https://dl.acm.org/citation.cfm?id=3274659
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 6
journalURL: https://dl.acm.org/loi/toms
rawauthor: Shouxiang Wang and Kai Wang and Lei Wu and Chengshan Wang
title:
Polar Affine Arithmetic: Optimal Affine Approximation and Operation Development for Computation in Polar Form Under Uncertainty

abstract:
Uncertainties practically arise from numerous factors, such as ambiguous information, inaccurate model, and environment disturbance. Interval arithmetic has emerged to solve problems with uncertain parameters, especially in the computational process where only the upper and lower bounds of parameters can be ascertained. In rectangular coordinate systems, the basic interval operations and improved interval algorithms have been developed in the numerical analysis. However, in polar coordinate systems, interval arithmetic still suffers from issues of complex computation and overestimation. This article defines a polar affine variable and develops a polar affine arithmetic (PAA) that extends affine arithmetic to the polar coordinate systems, which performs better in many aspects than the corresponding polar interval arithmetic (PIA). Basic arithmetic operations are developed based on the complex affine arithmetic. The Chebyshev approximation theory and the min-range approximation theory are used to identify the best affine approximation. PAA can accurately keep track of the interdependency among multiple variables throughout the calculation procedure, which prominently reduces the solution conservativeness. Numerical examples implemented in MATLAB programs show that, compared with benchmark results from the Monte Carlo method, the proposed PAA ensures completeness of the exact solution and presents a more compact solution region than PIA when dependency exists in the calculation process. Meanwhile, a comparison of affine arithmetic in polar and rectangular coordinates is presented. An application of PAA in circuit analysis is quantitatively presented and potential applications in other research fields involving complex variables in polar form will be gradually developed.

rawabstract:
Uncertainties practically arise from numerous factors, such as ambiguous information, inaccurate model, and environment disturbance. Interval arithmetic has emerged to solve problems with uncertain parameters, especially in the computational process where only the upper and lower bounds of parameters can be ascertained. In rectangular coordinate systems, the basic interval operations and improved interval algorithms have been developed in the numerical analysis. However, in polar coordinate systems, interval arithmetic still suffers from issues of complex computation and overestimation. This article defines a polar affine variable and develops a polar affine arithmetic (PAA) that extends affine arithmetic to the polar coordinate systems, which performs better in many aspects than the corresponding polar interval arithmetic (PIA). Basic arithmetic operations are developed based on the complex affine arithmetic. The Chebyshev approximation theory and the min-range approximation theory are used to identify the best affine approximation. PAA can accurately keep track of the interdependency among multiple variables throughout the calculation procedure, which prominently reduces the solution conservativeness. Numerical examples implemented in MATLAB programs show that, compared with benchmark results from the Monte Carlo method, the proposed PAA ensures completeness of the exact solution and presents a more compact solution region than PIA when dependency exists in the calculation process. Meanwhile, a comparison of affine arithmetic in polar and rectangular coordinates is presented. An application of PAA in circuit analysis is quantitatively presented and potential applications in other research fields involving complex variables in polar form will be gradually developed.

rawtitle:
Polar Affine Arithmetic: Optimal Affine Approximation and Operation Development for Computation in Polar Form Under Uncertainty

entry:
@Article{Wang:2019:PAA,
  author =       "Shouxiang Wang and Kai Wang and Lei Wu and Chengshan
                 Wang",
  title =        "Polar Affine Arithmetic: Optimal Affine Approximation
                 and Operation Development for Computation in Polar Form
                 Under Uncertainty",
  journal =      j-TOMS,
  volume =       "45",
  number =       "1",
  pages =        "6:1--6:29",
  month =        mar,
  year =         "2019",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3274659",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Mon May 6 18:23:42 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3274659",
  abstract =     "Uncertainties practically arise from numerous factors,
                 such as ambiguous information, inaccurate model, and
                 environment disturbance. Interval arithmetic has
                 emerged to solve problems with uncertain parameters,
                 especially in the computational process where only the
                 upper and lower bounds of parameters can be
                 ascertained. In rectangular coordinate systems, the
                 basic interval operations and improved interval
                 algorithms have been developed in the numerical
                 analysis. However, in polar coordinate systems,
                 interval arithmetic still suffers from issues of
                 complex computation and overestimation. This article
                 defines a polar affine variable and develops a polar
                 affine arithmetic (PAA) that extends affine arithmetic
                 to the polar coordinate systems, which performs better
                 in many aspects than the corresponding polar interval
                 arithmetic (PIA). Basic arithmetic operations are
                 developed based on the complex affine arithmetic. The
                 Chebyshev approximation theory and the min-range
                 approximation theory are used to identify the best
                 affine approximation. PAA can accurately keep track of
                 the interdependency among multiple variables throughout
                 the calculation procedure, which prominently reduces
                 the solution conservativeness. Numerical examples
                 implemented in MATLAB programs show that, compared with
                 benchmark results from the Monte Carlo method, the
                 proposed PAA ensures completeness of the exact solution
                 and presents a more compact solution region than PIA
                 when dependency exists in the calculation process.
                 Meanwhile, a comparison of affine arithmetic in polar
                 and rectangular coordinates is presented. An
                 application of PAA in circuit analysis is
                 quantitatively presented and potential applications in
                 other research fields involving complex variables in
                 polar form will be gradually developed.",
  acknowledgement = ack-nhfb,
  articleno =    "6",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Ye:2019:NCA
author: T. Ye and Y. Wei and W. Meier
title: A New Cube Attack on MORUS by Using Division Property
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 12
pages: 1731--1740
month: dec
monthnumber: 12
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2929137
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Nov 7 11:20:24 2019
bibtimestamp: 2019.11.07 11:20:24 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: T. Ye and Y. Wei and W. Meier
rawtitle: A New Cube Attack on {MORUS} by Using Division Property
keywords:
Authenticated encryption algorithm; Boolean functions; cube attack; division property; Encryption; mixed integer linear programming; MORUS; Software algorithms; Time complexity; time complexity

entry:
@Article{Ye:2019:NCA,
  author =       "T. Ye and Y. Wei and W. Meier",
  title =        "A New Cube Attack on {MORUS} by Using Division
                 Property",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "12",
  pages =        "1731--1740",
  month =        dec,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2929137",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Nov 7 11:20:24 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Authenticated encryption algorithm; Boolean functions;
                 cube attack; division property; Encryption; mixed
                 integer linear programming; MORUS; Software algorithms;
                 Time complexity; time complexity",
}


bibtype: article
filename: fparith.bib
label: Zhang:2019:EMP
author: H. Zhang and D. Chen and S. Ko
title: Efficient Multiple-Precision Floating-Point Fused Multiply-Add with Mixed-Precision Support
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 7
pages: 1035--1048
month: jul
monthnumber: 7
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2895031
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: H. Zhang and D. Chen and S. Ko
rawtitle: Efficient Multiple-Precision Floating-Point Fused Multiply-Add with Mixed-Precision Support
keywords:
Adders; Clocks; Computer architecture; Deep learning; double-precision operations; efficiency 10.6 percent; efficiency 6.5 percent; floating point arithmetic; floating-point arithmetics; floating-point operations; FMA architecture; Fused multiply-add; half-precision FMA operations; Hardware; logic design; mixed-precision arithmetics; mixed-precision dot-product operations; mixed-precision FMA operations; mixed-precision operations; mixed-precision support; multiple-precision arithmetics; multiple-precision floating-point; multiple-precision FMA design; multiple-precision FMA unit; multiplying circuits; normal FMA operations; parallel half-precision operations; Pipelines; quadruple-precision operation; single-precision operations; Standards

entry:
@Article{Zhang:2019:EMP,
  author =       "H. Zhang and D. Chen and S. Ko",
  title =        "Efficient Multiple-Precision Floating-Point Fused
                 Multiply-Add with Mixed-Precision Support",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "7",
  pages =        "1035--1048",
  month =        jul,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2895031",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adders; Clocks; Computer architecture; Deep learning;
                 double-precision operations; efficiency 10.6 percent;
                 efficiency 6.5 percent; floating point arithmetic;
                 floating-point arithmetics; floating-point operations;
                 FMA architecture; Fused multiply-add; half-precision
                 FMA operations; Hardware; logic design; mixed-precision
                 arithmetics; mixed-precision dot-product operations;
                 mixed-precision FMA operations; mixed-precision
                 operations; mixed-precision support; multiple-precision
                 arithmetics; multiple-precision floating-point;
                 multiple-precision FMA design; multiple-precision FMA
                 unit; multiplying circuits; normal FMA operations;
                 parallel half-precision operations; Pipelines;
                 quadruple-precision operation; single-precision
                 operations; Standards",
}


bibtype: inproceedings
filename: fparith.bib
label: Zhang:2019:EPM
author: Hao Zhang and Jiongrui He and Seok-Bum Ko
editor: IEEE
booktitle: 2019 IEEE International Symposium on Circuits and Systems (ISCAS)
title: Efficient Posit Multiply-Accumulate Unit Generator for Deep Learning Applications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
month: may
monthnumber: 5
year: 2019
DOI: https://doi.org/10.1109/iscas.2019.8702349
bibdate: Thu Dec 14 18:03:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.14 18:03:31 ???
acknowledgement: ack-nhfb
rawauthor: Hao Zhang and Jiongrui He and Seok-Bum Ko
rawbooktitle: {2019 IEEE International Symposium on Circuits and Systems (ISCAS)}
raweditor: IEEE
rawtitle: Efficient Posit Multiply-Accumulate Unit Generator for Deep Learning Applications
entry:
@InProceedings{Zhang:2019:EPM,
  author =       "Hao Zhang and Jiongrui He and Seok-Bum Ko",
  editor =       "IEEE",
  booktitle =    "{2019 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Efficient Posit Multiply-Accumulate Unit Generator for
                 Deep Learning Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  month =        may,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/iscas.2019.8702349",
  bibdate =      "Thu Dec 14 18:03:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Zorn:2019:SPD
author: Bill Zorn and Dan Grossman and Zach Tatlock
title: Sinking Point: Dynamic Precision Tracking for Floating-Point
crossref: Gustafson:2019:CPC
pages: 4:1--4:8
year: 2019
DOI: https://doi.org/10.1145/3316279.3316283
bibdate: Mon Feb 10 12:11:16 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 12:11:16 ???
keywords: Floating point, numerical analysis
acknowledgement: ack-nhfb
articleno: 4
rawauthor: Bill Zorn and Dan Grossman and Zach Tatlock
rawtitle: Sinking Point: Dynamic Precision Tracking for Floating-Point
entry:
@InProceedings{Zorn:2019:SPD,
  author =       "Bill Zorn and Dan Grossman and Zach Tatlock",
  title =        "Sinking Point: Dynamic Precision Tracking for
                 Floating-Point",
  crossref =     "Gustafson:2019:CPC",
  pages =        "4:1--4:8",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316283",
  bibdate =      "Mon Feb 10 12:11:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  keywords =     "Floating point, numerical analysis",
  location =     "Singapore, Singapore",
  numpages =     "8",
}


bibtype: inproceedings
filename: fparith.bib
label: Abdelfattah:2020:IBF
author: Ahmad Abdelfattah and Stan Tomov and Jack Dongarra
crossref: Krzhizhanovskaya:2020:CSI
pages: 237--250
year: 2020
DOI: https://doi.org/10.1007/978-3-030-50417-5_18
bibdate: Thu Jun 25 08:49:09 2020
bibtimestamp: 2020.06.25 08:49:09 ???
acknowledgement: ack-nhfb
rawauthor: Ahmad Abdelfattah and Stan Tomov and Jack Dongarra
title:
Investigating the Benefit of FP16-Enabled Mixed-Precision Solvers for Symmetric Positive Definite Matrices Using GPUs

bibsource:
https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
Investigating the Benefit of {FP16}-Enabled Mixed-Precision Solvers for Symmetric Positive Definite Matrices Using {GPUs}

entry:
@InProceedings{Abdelfattah:2020:IBF,
  author =       "Ahmad Abdelfattah and Stan Tomov and Jack Dongarra",
  title =        "Investigating the Benefit of {FP16}-Enabled
                 Mixed-Precision Solvers for Symmetric Positive Definite
                 Matrices Using {GPUs}",
  crossref =     "Krzhizhanovskaya:2020:CSI",
  pages =        "237--250",
  year =         "2020",
  DOI =          "https://doi.org/10.1007/978-3-030-50417-5_18",
  bibdate =      "Thu Jun 25 08:49:09 2020",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Abdelfattah:2020:MMB
author: Ahmad Abdelfattah and Stanimire Tomov and Jack Dongarra
title: Matrix multiplication on batches of small matrices in half and half-complex precisions
journal: j-J-PAR-DIST-COMP
volume: 145
pages: 188--201
month: nov
monthnumber: 11
year: 2020
CODEN: JPDCER
DOI: https://doi.org/10.1016/j.jpdc.2020.07.001
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Wed May 26 16:11:03 MDT 2021
bibtimestamp: 2021.05.26 16:11:03 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0743731520303300
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07437315
rawauthor: Ahmad Abdelfattah and Stanimire Tomov and Jack Dongarra
rawtitle: Matrix multiplication on batches of small matrices in half and half-complex precisions
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jpardistcomp.bib

entry:
@Article{Abdelfattah:2020:MMB,
  author =       "Ahmad Abdelfattah and Stanimire Tomov and Jack
                 Dongarra",
  title =        "Matrix multiplication on batches of small matrices in
                 half and half-complex precisions",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "145",
  number =       "??",
  pages =        "188--201",
  month =        nov,
  year =         "2020",
  CODEN =        "JPDCER",
  DOI =          "https://doi.org/10.1016/j.jpdc.2020.07.001",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Wed May 26 16:11:03 MDT 2021",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jpardistcomp.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0743731520303300",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
}


bibtype: article
filename: fparith.bib
label: Adams:2020:ARD
author: E. Adams and S. Venkatachalam and S. Ko
title: Approximate Restoring Dividers Using Inexact Cells and Estimation From Partial Remainders
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 4
pages: 468--474
month: apr
monthnumber: 4
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2953751
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Mar 12 16:58:27 2020
bibtimestamp: 2020.03.12 16:58:27 ???
fjournal: IEEE Transactions on Computers
keywords: Approximate computing; error analysis; image processing applications; low-power; restoring division
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: E. Adams and S. Venkatachalam and S. Ko
rawtitle: Approximate Restoring Dividers Using Inexact Cells and Estimation From Partial Remainders
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib

entry:
@Article{Adams:2020:ARD,
  author =       "E. Adams and S. Venkatachalam and S. Ko",
  title =        "Approximate Restoring Dividers Using Inexact Cells and
                 Estimation From Partial Remainders",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "4",
  pages =        "468--474",
  month =        apr,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2953751",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Mar 12 16:58:27 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Approximate computing; error analysis; image
                 processing applications; low-power; restoring
                 division",
}


bibtype: inproceedings
filename: fparith.bib
label: Agrawal:2020:FAH
author: Rashmi Agrawal and Lake Bu and Michel A. Kinsy
title: Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 206--206
year: 2020
DOI: https://doi.org/10.1109/FCCM48280.2020.00037
bibdate: Fri Sep 22 08:05:37 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 08:05:37 ???
acknowledgement: ack-nhfb
rawauthor: Rashmi Agrawal and Lake Bu and Michel A. Kinsy
rawtitle: Fast Arithmetic Hardware Library For {RLWE-Based} Homomorphic Encryption
booktitle:
2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

rawbooktitle:
{2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}

entry:
@InProceedings{Agrawal:2020:FAH,
  author =       "Rashmi Agrawal and Lake Bu and Michel A. Kinsy",
  booktitle =    "{2020 IEEE 28th Annual International Symposium on
                 Field-Programmable Custom Computing Machines (FCCM)}",
  title =        "Fast Arithmetic Hardware Library For {RLWE-Based}
                 Homomorphic Encryption",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "206--206",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/FCCM48280.2020.00037",
  bibdate =      "Fri Sep 22 08:05:37 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Ahrens:2020:AER
author: Peter Ahrens and James Demmel and Hong Diep Nguyen
title: Algorithms for Efficient Reproducible Floating Point Summation
journal: j-TOMS
volume: 46
number: 3
pages: 22:1--22:49
month: sep
monthnumber: 9
year: 2020
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3389360
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Sat Sep 26 07:28:19 MDT 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2020.09.26 07:28:19 MDT
URL: https://dl.acm.org/doi/10.1145/3389360
fjournal: ACM Transactions on Mathematical Software (TOMS)
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
articleno: 22
journalURL: https://dl.acm.org/loi/toms
rawauthor: Peter Ahrens and James Demmel and Hong Diep Nguyen
rawtitle: Algorithms for Efficient Reproducible Floating Point Summation
abstract:
We define ``reproducibility'' as getting bitwise identical results from multiple runs of the same program, perhaps with different hardware resources or other changes that should not affect the answer. Many users depend on reproducibility for debugging or correctness. However, dynamic scheduling of parallel computing resources, combined with nonassociative floating point addition, makes reproducibility challenging even for summation, or operations like the BLAS. We describe a ``reproducible accumulator'' data structure (the ``binned number'') and associated algorithms to reproducibly sum binary floating point numbers, independent of summation order. We use a subset of the IEEE Floating Point Standard 754-2008 and bitwise operations on the standard representations in memory. Our approach requires only one read-only pass over the data, and one reduction in parallel, using a 6-word reproducible accumulator (more words can be used for higher accuracy), enabling standard tiling optimization techniques. Summing $n$ words with a 6-word reproducible accumulator requires approximately $ 9 n$ floating point operations (arithmetic, comparison, and absolute value) and approximately $ 3 n$ bitwise operations. The final error bound with a 6-word reproducible accumulator and our default settings can be up to 229 times smaller than the error bound for conventional (recursive) summation on ill-conditioned double-precision inputs

rawabstract:
We define ``reproducibility'' as getting bitwise identical results from multiple runs of the same program, perhaps with different hardware resources or other changes that should not affect the answer. Many users depend on reproducibility for debugging or correctness. However, dynamic scheduling of parallel computing resources, combined with nonassociative floating point addition, makes reproducibility challenging even for summation, or operations like the BLAS. We describe a ``reproducible accumulator'' data structure (the ``binned number'') and associated algorithms to reproducibly sum binary floating point numbers, independent of summation order. We use a subset of the IEEE Floating Point Standard 754-2008 and bitwise operations on the standard representations in memory. Our approach requires only one read-only pass over the data, and one reduction in parallel, using a 6-word reproducible accumulator (more words can be used for higher accuracy), enabling standard tiling optimization techniques. Summing $n$ words with a 6-word reproducible accumulator requires approximately $ 9 n$ floating point operations (arithmetic, comparison, and absolute value) and approximately $ 3 n$ bitwise operations. The final error bound with a 6-word reproducible accumulator and our default settings can be up to 229 times smaller than the error bound for conventional (recursive) summation on ill-conditioned double-precision inputs

entry:
@Article{Ahrens:2020:AER,
  author =       "Peter Ahrens and James Demmel and Hong Diep Nguyen",
  title =        "Algorithms for Efficient Reproducible Floating Point
                 Summation",
  journal =      j-TOMS,
  volume =       "46",
  number =       "3",
  pages =        "22:1--22:49",
  month =        sep,
  year =         "2020",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3389360",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Sat Sep 26 07:28:19 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3389360",
  abstract =     "We define ``reproducibility'' as getting bitwise
                 identical results from multiple runs of the same
                 program, perhaps with different hardware resources or
                 other changes that should not affect the answer. Many
                 users depend on reproducibility for debugging or
                 correctness. However, dynamic scheduling of parallel
                 computing resources, combined with nonassociative
                 floating point addition, makes reproducibility
                 challenging even for summation, or operations like the
                 BLAS. We describe a ``reproducible accumulator'' data
                 structure (the ``binned number'') and associated
                 algorithms to reproducibly sum binary floating point
                 numbers, independent of summation order. We use a
                 subset of the IEEE Floating Point Standard 754-2008 and
                 bitwise operations on the standard representations in
                 memory. Our approach requires only one read-only pass
                 over the data, and one reduction in parallel, using a
                 6-word reproducible accumulator (more words can be used
                 for higher accuracy), enabling standard tiling
                 optimization techniques. Summing $n$ words with a
                 6-word reproducible accumulator requires approximately
                 $ 9 n$ floating point operations (arithmetic,
                 comparison, and absolute value) and approximately $ 3
                 n$ bitwise operations. The final error bound with a
                 6-word reproducible accumulator and our default
                 settings can be up to 229 times smaller than the error
                 bound for conventional (recursive) summation on
                 ill-conditioned double-precision inputs",
  acknowledgement = ack-nhfb,
  articleno =    "22",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "accurate floating-point summation",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:ACa
author: Anonymous
title: ARITH 2020 Committees
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00006
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Provides a listing of current committee members and society officers.
acknowledgement: ack-nhfb
rawabstract: Provides a listing of current committee members and society officers.
rawauthor: Anonymous
rawtitle: {ARITH 2020} Committees
entry:
@InProceedings{Anonymous:2020:ACa,
  author =       "Anonymous",
  title =        "{ARITH 2020} Committees",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00006",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Provides a listing of current committee members and
                 society officers.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:ACb
author: Anonymous
title: ARITH 2020 Committees
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00007
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Provides a listing of current committee members and society officers.
acknowledgement: ack-nhfb
rawabstract: Provides a listing of current committee members and society officers.
rawauthor: Anonymous
rawtitle: {ARITH 2020} Committees
entry:
@InProceedings{Anonymous:2020:ACb,
  author =       "Anonymous",
  title =        "{ARITH 2020} Committees",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00007",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Provides a listing of current committee members and
                 society officers.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:ACN
author: Anonymous
title: [ARITH 2020 Copyright notice]
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00003
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Presents the copyright information for the conference. May include reprint permission information.
acknowledgement: ack-nhfb
rawabstract: Presents the copyright information for the conference. May include reprint permission information.
rawauthor: Anonymous
rawtitle: [{ARITH 2020} Copyright notice]
entry:
@InProceedings{Anonymous:2020:ACN,
  author =       "Anonymous",
  title =        "[{ARITH 2020} Copyright notice]",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00003",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the copyright information for the conference.
                 May include reprint permission information.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:AI
author: Anonymous
title: ARITH 2020 Index
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00030
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Presents an index of the authors whose articles are published in the conference proceedings record.
acknowledgement: ack-nhfb
rawabstract: Presents an index of the authors whose articles are published in the conference proceedings record.
rawauthor: Anonymous
rawtitle: {ARITH 2020} Index
entry:
@InProceedings{Anonymous:2020:AI,
  author =       "Anonymous",
  title =        "{ARITH 2020} Index",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00030",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents an index of the authors whose articles are
                 published in the conference proceedings record.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:ALR
author: Anonymous
title: ARITH 2020 List Reviewer Page
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00008
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: The conference offers a note of thanks and lists its reviewers.
acknowledgement: ack-nhfb
rawabstract: The conference offers a note of thanks and lists its reviewers.
rawauthor: Anonymous
rawtitle: {ARITH 2020} List Reviewer Page
entry:
@InProceedings{Anonymous:2020:ALR,
  author =       "Anonymous",
  title =        "{ARITH 2020} List Reviewer Page",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00008",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The conference offers a note of thanks and lists its
                 reviewers.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2020:RVE
author: Anonymous
title: RISC-V embedded variant RV32E now fully supported by SEGGER's Floating-Point library
pages: i--i
day: 21
month: sep
monthnumber: 9
year: 2020
bibdate: Thu Jan 28 18:02:53 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.01.28 18:02:53 ???
URL: https://www.design-reuse.com/news/48672/segger-s-floating-point-library-risc-v-rv32e.html
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Anonymous
rawtitle: {RISC-V} embedded variant {RV32E} now fully supported by {SEGGER}'s Floating-Point library
remark:
The story reports a significant code size reduction, and speedup, over the GNU floating-point library.

entry:
@Misc{Anonymous:2020:RVE,
  author =       "Anonymous",
  title =        "{RISC-V} embedded variant {RV32E} now fully supported
                 by {SEGGER}'s Floating-Point library",
  howpublished = "Web site",
  day =          "21",
  month =        sep,
  year =         "2020",
  bibdate =      "Thu Jan 28 18:02:53 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.design-reuse.com/news/48672/segger-s-floating-point-library-risc-v-rv32e.html",
  acknowledgement = ack-nhfb,
  remark =       "The story reports a significant code size reduction,
                 and speedup, over the GNU floating-point library.",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:SA
author: Anonymous
title: Sponsors ARITH 2020
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00009
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: The conference organizers greatly appreciate the support of the various corporate sponsors listed.
acknowledgement: ack-nhfb
rawabstract: The conference organizers greatly appreciate the support of the various corporate sponsors listed.
rawauthor: Anonymous
rawtitle: Sponsors {ARITH 2020}
entry:
@InProceedings{Anonymous:2020:SA,
  author =       "Anonymous",
  title =        "Sponsors {ARITH 2020}",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00009",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The conference organizers greatly appreciate the
                 support of the various corporate sponsors listed.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:TC
author: Anonymous
title: Table of Contents
crossref: Cornea:2020:ISC
pages: i--iii
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00004
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Presents the table of contents/splash page of the proceedings record.
acknowledgement: ack-nhfb
rawabstract: Presents the table of contents/splash page of the proceedings record.
rawauthor: Anonymous
rawtitle: Table of Contents
entry:
@InProceedings{Anonymous:2020:TC,
  author =       "Anonymous",
  title =        "Table of Contents",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--iii",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00004",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the table of contents/splash page of the
                 proceedings record.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:TPa
author: Anonymous
title: [Title page]
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00001
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Presents the title page of the proceedings record.
acknowledgement: ack-nhfb
rawabstract: Presents the title page of the proceedings record.
rawauthor: Anonymous
rawtitle: {[Title} page]
entry:
@InProceedings{Anonymous:2020:TPa,
  author =       "Anonymous",
  title =        "{[Title} page]",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00001",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the title page of the proceedings record.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2020:TPb
author: Anonymous
title: [Title page]
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00002
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
abstract: Presents the title page of the proceedings record.
acknowledgement: ack-nhfb
rawabstract: Presents the title page of the proceedings record.
rawauthor: Anonymous
rawtitle: {[Title} page]
entry:
@InProceedings{Anonymous:2020:TPb,
  author =       "Anonymous",
  title =        "{[Title} page]",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00002",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Presents the title page of the proceedings record.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Arnold:2020:IRL
author: M. G. Arnold and V. Paliouras and I. Kouretas
title: Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 12
pages: 1719--1732
month: dec
monthnumber: 12
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2930514
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Nov 24 09:42:22 2020
bibtimestamp: 2020.11.24 09:42:22 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. G. Arnold and V. Paliouras and I. Kouretas
rawtitle: Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib

entry:
@Article{Arnold:2020:IRL,
  author =       "M. G. Arnold and V. Paliouras and I. Kouretas",
  title =        "Implementing the Residue Logarithmic Number System
                 Using Interpolation and Cotransformation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "12",
  pages =        "1719--1732",
  month =        dec,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2930514",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Nov 24 09:42:22 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Bajard:2020:AFV
author: Jean-Claude Bajard and Julien Eynard and Paulo Martins and Leonel Sousa and Vincent Zucca
title: An asymptotically faster version of FV supported on HPR
crossref: Cornea:2020:ISC
pages: 80--87
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00020
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Jean-Claude Bajard and Julien Eynard and Paulo Martins and Leonel Sousa and Vincent Zucca
rawtitle: An asymptotically faster version of {FV} supported on {HPR}
abstract:
State-of-the-art implementations of homomorphic encryption exploit the Fan and Vercauteren (FV) scheme and the Residue Number System (RNS). While the RNS breaks down large integer arithmetic into smaller independent channels, its non-positional nature makes operations such as division and rounding hard to implement, and makes the representation of small values inefficient. In this work, we propose the application of the Hybrid Position-Residues Number System representation to the FV scheme. This is a positional representation of large radix where the digits are represented in RNS. It inherits the benefits from RNS and allows to accelerate the critical division and rounding operations while also making the representation of smaller values more compact. This directly benefits the decryption and the homomorphic multiplication procedures, reducing their asymptotic complexity, in dimension n, from O(n2 log n) to O(n log n) and from O(n3 log n) to O(n3), respectively and has resulted in noticeable speedups when experimentally compared to related art RNS implementations.

keywords:
Acceleration; Art; Complexity theory; Encryption; Fan-Vercauteren scheme; Fans; Homomorphic Encryption; Indexes; Residue Number System

rawabstract:
State-of-the-art implementations of homomorphic encryption exploit the Fan and Vercauteren (FV) scheme and the Residue Number System (RNS). While the RNS breaks down large integer arithmetic into smaller independent channels, its non-positional nature makes operations such as division and rounding hard to implement, and makes the representation of small values inefficient. In this work, we propose the application of the Hybrid Position-Residues Number System representation to the FV scheme. This is a positional representation of large radix where the digits are represented in RNS. It inherits the benefits from RNS and allows to accelerate the critical division and rounding operations while also making the representation of smaller values more compact. This directly benefits the decryption and the homomorphic multiplication procedures, reducing their asymptotic complexity, in dimension n, from O(n2 log n) to O(n log n) and from O(n3 log n) to O(n3), respectively and has resulted in noticeable speedups when experimentally compared to related art RNS implementations.

entry:
@InProceedings{Bajard:2020:AFV,
  author =       "Jean-Claude Bajard and Julien Eynard and Paulo Martins
                 and Leonel Sousa and Vincent Zucca",
  title =        "An asymptotically faster version of {FV} supported on
                 {HPR}",
  crossref =     "Cornea:2020:ISC",
  pages =        "80--87",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00020",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "State-of-the-art implementations of homomorphic
                 encryption exploit the Fan and Vercauteren (FV) scheme
                 and the Residue Number System (RNS). While the RNS
                 breaks down large integer arithmetic into smaller
                 independent channels, its non-positional nature makes
                 operations such as division and rounding hard to
                 implement, and makes the representation of small values
                 inefficient. In this work, we propose the application
                 of the Hybrid Position-Residues Number System
                 representation to the FV scheme. This is a positional
                 representation of large radix where the digits are
                 represented in RNS. It inherits the benefits from RNS
                 and allows to accelerate the critical division and
                 rounding operations while also making the
                 representation of smaller values more compact. This
                 directly benefits the decryption and the homomorphic
                 multiplication procedures, reducing their asymptotic
                 complexity, in dimension n, from O(n2 log n) to O(n log
                 n) and from O(n3 log n) to O(n3), respectively and has
                 resulted in noticeable speedups when experimentally
                 compared to related art RNS implementations.",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; Art; Complexity theory; Encryption;
                 Fan-Vercauteren scheme; Fans; Homomorphic Encryption;
                 Indexes; Residue Number System",
}


bibtype: inproceedings
filename: fparith.bib
label: Barthel:2020:ASA
author: Moritz Barthel and Jochen Rust and Steffen Paul
booktitle: 2020 IEEE International Symposium on Circuits and Systems (ISCAS)
title: Application-Specific Analysis of Different SORN Datatypes for Unum Type-2-Based Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2020
DOI: https://doi.org/10.1109/ISCAS45731.2020.9181182
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawauthor: Moritz B{\"a}rthel and Jochen Rust and Steffen Paul
rawbooktitle: {2020 IEEE International Symposium on Circuits and Systems (ISCAS)}
rawtitle: Application-Specific Analysis of Different {SORN} Datatypes for Unum Type-2-Based Arithmetic
entry:
@InProceedings{Barthel:2020:ASA,
  author =       "Moritz B{\"a}rthel and Jochen Rust and Steffen Paul",
  booktitle =    "{2020 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Application-Specific Analysis of Different {SORN}
                 Datatypes for Unum Type-2-Based Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ISCAS45731.2020.9181182",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Boldo:2020:CRF
author: Sylvie Boldo and Diane Gallois-Wong and Thibault Hilaire
title: A Correctly-Rounded Fixed-Point-Arithmetic Dot-Product Algorithm
crossref: Cornea:2020:ISC
pages: 9--16
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00011
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo and Diane Gallois-Wong and Thibault Hilaire
rawtitle: A Correctly-Rounded Fixed-Point-Arithmetic Dot-Product Algorithm
abstract:
Dot products (also called sums of products) are ubiquitous in matrix computations, for instance in signal processing. We are especially interested in digital filters, where they are the core operation. We therefore focus on fixed-point arithmetic, used in embedded systems for time and energy efficiency. Common dot product algorithms ensure faithful rounding. For the sake of accuracy and reproducibility, we want to ensure correct rounding. This article describes an algorithm that computes a correctly-rounded sum of products from inputs whose format is known in advance. This algorithm relies on odd rounding (that is easily implemented in hardware) and comes with a careful proof and some cost analysis.

keywords:
Correct Rounding; Dot Product; Embedded systems; Fixed-point arithmetic; Fixed-Point Arithmetic; floating-point arithmetic; Hardware; Odd Rounding; Runtime; Signal processing; Signal processing algorithms; Sorting; Sum-of-Products

rawabstract:
Dot products (also called sums of products) are ubiquitous in matrix computations, for instance in signal processing. We are especially interested in digital filters, where they are the core operation. We therefore focus on fixed-point arithmetic, used in embedded systems for time and energy efficiency. Common dot product algorithms ensure faithful rounding. For the sake of accuracy and reproducibility, we want to ensure correct rounding. This article describes an algorithm that computes a correctly-rounded sum of products from inputs whose format is known in advance. This algorithm relies on odd rounding (that is easily implemented in hardware) and comes with a careful proof and some cost analysis.

entry:
@InProceedings{Boldo:2020:CRF,
  author =       "Sylvie Boldo and Diane Gallois-Wong and Thibault
                 Hilaire",
  title =        "A Correctly-Rounded Fixed-Point-Arithmetic Dot-Product
                 Algorithm",
  crossref =     "Cornea:2020:ISC",
  pages =        "9--16",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00011",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Dot products (also called sums of products) are
                 ubiquitous in matrix computations, for instance in
                 signal processing. We are especially interested in
                 digital filters, where they are the core operation. We
                 therefore focus on fixed-point arithmetic, used in
                 embedded systems for time and energy efficiency. Common
                 dot product algorithms ensure faithful rounding. For
                 the sake of accuracy and reproducibility, we want to
                 ensure correct rounding. This article describes an
                 algorithm that computes a correctly-rounded sum of
                 products from inputs whose format is known in advance.
                 This algorithm relies on odd rounding (that is easily
                 implemented in hardware) and comes with a careful proof
                 and some cost analysis.",
  acknowledgement = ack-nhfb,
  keywords =     "Correct Rounding; Dot Product; Embedded systems;
                 Fixed-point arithmetic; Fixed-Point Arithmetic;
                 floating-point arithmetic; Hardware; Odd Rounding;
                 Runtime; Signal processing; Signal processing
                 algorithms; Sorting; Sum-of-Products",
}


bibtype: inproceedings
filename: fparith.bib
label: Bottcher:2020:HDL
author: Andreas Bottcher and Keanu Kullmann and Martin Kumm
title: Heuristics for the Design of Large Multipliers for FPGAs
crossref: Cornea:2020:ISC
pages: 17--24
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00012
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Andreas B{\"o}ttcher and Keanu Kullmann and Martin Kumm
rawtitle: Heuristics for the Design of Large Multipliers for {FPGAs}
abstract:
The following topics are dealt with: floating point arithmetic; cryptography; field programmable gate arrays; computational complexity; embedded systems; public key cryptography; optimisation; probability; fixed point arithmetic; and digital signal processing chips.

keywords:
Complexity theory; computer arithmetic; Digital arithmetic; Field programmable gate arrays; heuristics; Integer linear programming; Karatsuba multiplier; large multiplier; Optimization; post quantum cryptography; Shape; Table lookup; tiling

rawabstract:
The following topics are dealt with: floating point arithmetic; cryptography; field programmable gate arrays; computational complexity; embedded systems; public key cryptography; optimisation; probability; fixed point arithmetic; and digital signal processing chips.

entry:
@InProceedings{Bottcher:2020:HDL,
  author =       "Andreas B{\"o}ttcher and Keanu Kullmann and Martin
                 Kumm",
  title =        "Heuristics for the Design of Large Multipliers for
                 {FPGAs}",
  crossref =     "Cornea:2020:ISC",
  pages =        "17--24",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00012",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The following topics are dealt with: floating point
                 arithmetic; cryptography; field programmable gate
                 arrays; computational complexity; embedded systems;
                 public key cryptography; optimisation; probability;
                 fixed point arithmetic; and digital signal processing
                 chips.",
  acknowledgement = ack-nhfb,
  keywords =     "Complexity theory; computer arithmetic; Digital
                 arithmetic; Field programmable gate arrays; heuristics;
                 Integer linear programming; Karatsuba multiplier; large
                 multiplier; Optimization; post quantum cryptography;
                 Shape; Table lookup; tiling",
}


bibtype: article
filename: fparith.bib
label: Brisebarre:2020:EAS
author: Nicolas Brisebarre and Mioara Joldes and Jean-Michel Muller and Ana-Maria Nanes and Joris Picot
title: Error Analysis of Some Operations Involved in the Cooley--Tukey Fast Fourier Transform
journal: j-TOMS
volume: 46
number: 2
pages: 11:1--11:27
month: jun
monthnumber: 6
year: 2020
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3368619
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Fri Jun 12 07:37:53 MDT 2020
bibtimestamp: 2020.06.12 07:37:53 MDT
URL: https://dl.acm.org/doi/abs/10.1145/3368619
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 11
journalURL: https://dl.acm.org/loi/toms
rawauthor: Nicolas Brisebarre and Mioara Joldes and Jean-Michel Muller and Ana-Maria Nanes and Joris Picot
rawtitle: Error Analysis of Some Operations Involved in the {Cooley--Tukey Fast Fourier Transform}
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/t/tukey-john-w.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

abstract:
We are interested in obtaining error bounds for the classical Cooley--Tukey fast Fourier transform algorithm in floating-point arithmetic, for the 2-norm as well as for the infinity norm. For that purpose, we also give some results on the relative error of the complex multiplication by a root of unity, and on the largest value that can take the real or imaginary part of one term of the fast Fourier transform of a vector $x$, assuming that all terms of $x$ have real and imaginary parts less than some value $b$.

rawabstract:
We are interested in obtaining error bounds for the classical Cooley--Tukey fast Fourier transform algorithm in floating-point arithmetic, for the 2-norm as well as for the infinity norm. For that purpose, we also give some results on the relative error of the complex multiplication by a root of unity, and on the largest value that can take the real or imaginary part of one term of the fast Fourier transform of a vector $x$, assuming that all terms of $x$ have real and imaginary parts less than some value $b$.

entry:
@Article{Brisebarre:2020:EAS,
  author =       "Nicolas Brisebarre and Mioara Joldes and Jean-Michel
                 Muller and Ana-Maria Nanes and Joris Picot",
  title =        "Error Analysis of Some Operations Involved in the
                 {Cooley--Tukey Fast Fourier Transform}",
  journal =      j-TOMS,
  volume =       "46",
  number =       "2",
  pages =        "11:1--11:27",
  month =        jun,
  year =         "2020",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3368619",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Fri Jun 12 07:37:53 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/t/tukey-john-w.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3368619",
  abstract =     "We are interested in obtaining error bounds for the
                 classical Cooley--Tukey fast Fourier transform
                 algorithm in floating-point arithmetic, for the 2-norm
                 as well as for the infinity norm. For that purpose, we
                 also give some results on the relative error of the
                 complex multiplication by a root of unity, and on the
                 largest value that can take the real or imaginary part
                 of one term of the fast Fourier transform of a vector
                 $x$, assuming that all terms of $x$ have real and
                 imaginary parts less than some value $b$.",
  acknowledgement = ack-nhfb,
  articleno =    "11",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Bruguera:2020:LLF
author: J. D. Bruguera
title: Low Latency Floating-Point Division and Square Root Unit
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 2
pages: 274--287
month: feb
monthnumber: 2
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2947899
ISSN: 2326-3814 OR 23263814
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jan 22 06:44:09 2020
bibtimestamp: 2020.01.22 06:44:09 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. D. Bruguera
rawtitle: Low Latency Floating-Point Division and Square Root Unit
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib

keywords:
Computer architecture; Convergence; Digit-recurrence algorithms; Estimation; floating-point division, and square root; Iterative methods; Organizations; Registers; Timing

entry:
@Article{Bruguera:2020:LLF,
  author =       "J. D. Bruguera",
  title =        "Low Latency Floating-Point Division and Square Root
                 Unit",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "2",
  pages =        "274--287",
  month =        feb,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2947899",
  ISSN =         "2326-3814",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jan 22 06:44:09 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Computer architecture; Convergence; Digit-recurrence
                 algorithms; Estimation; floating-point division, and
                 square root; Iterative methods; Organizations;
                 Registers; Timing",
}


bibtype: inproceedings
filename: fparith.bib
label: Brunie:2020:TFP
author: Hugo Brunie and Costin Iancu and Khaled Z. Ibrahim and Philip Brisk and Brandon Cook
title: Tuning floating-point precision using dynamic program information and temporal locality
crossref: IEEE:2020:SPI
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--14
year: 2020
bibdate: Mon Sep 11 08:19:28 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 08:19:28 ???
acknowledgement: ack-nhfb
articleno: 50
rawauthor: Hugo Brunie and Costin Iancu and Khaled Z. Ibrahim and Philip Brisk and Brandon Cook
rawtitle: Tuning floating-point precision using dynamic program information and temporal locality
abstract:
We present a methodology for precision tuning of full applications. These techniques must select a search space composed of either variables or instructions and provide a scalable search strategy. In full application settings one cannot assume compiler support for practical reasons. Thus, an additional important challenge is enabling code refactoring. We argue for an instruction-based search space and we show: (1) how to exploit dynamic program information based on call stacks; and (2) how to exploit the iterative nature of scientific codes, combined with temporal locality. We applied the methodology to tune the implementation of scientific codes written in a combination of Python, CUDA, C++ and Fortran, tuning calls to math exp library functions. The iterative search refinement always reduces the search complexity and the number of steps to solution. Dynamic program information increases search efficacy. Using this approach, we obtain application runtime performance improvements up to 27%.

rawabstract:
We present a methodology for precision tuning of full applications. These techniques must select a search space composed of either variables or instructions and provide a scalable search strategy. In full application settings one cannot assume compiler support for practical reasons. Thus, an additional important challenge is enabling code refactoring. We argue for an instruction-based search space and we show: (1) how to exploit dynamic program information based on call stacks; and (2) how to exploit the iterative nature of scientific codes, combined with temporal locality. We applied the methodology to tune the implementation of scientific codes written in a combination of Python, CUDA, C++ and Fortran, tuning calls to math exp library functions. The iterative search refinement always reduces the search complexity and the number of steps to solution. Dynamic program information increases search efficacy. Using this approach, we obtain application runtime performance improvements up to 27\%.

entry:
@InProceedings{Brunie:2020:TFP,
  author =       "Hugo Brunie and Costin Iancu and Khaled Z. Ibrahim and
                 Philip Brisk and Brandon Cook",
  title =        "Tuning floating-point precision using dynamic program
                 information and temporal locality",
  crossref =     "IEEE:2020:SPI",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--14",
  year =         "2020",
  bibdate =      "Mon Sep 11 08:19:28 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a methodology for precision tuning of full
                 applications. These techniques must select a search
                 space composed of either variables or instructions and
                 provide a scalable search strategy. In full application
                 settings one cannot assume compiler support for
                 practical reasons. Thus, an additional important
                 challenge is enabling code refactoring. We argue for an
                 instruction-based search space and we show: (1) how to
                 exploit dynamic program information based on call
                 stacks; and (2) how to exploit the iterative nature of
                 scientific codes, combined with temporal locality. We
                 applied the methodology to tune the implementation of
                 scientific codes written in a combination of Python,
                 CUDA, C++ and Fortran, tuning calls to math exp library
                 functions. The iterative search refinement always
                 reduces the search complexity and the number of steps
                 to solution. Dynamic program information increases
                 search efficacy. Using this approach, we obtain
                 application runtime performance improvements up to
                 27\%.",
  acknowledgement = ack-nhfb,
  articleno =    "50",
}


bibtype: inproceedings
filename: fparith.bib
label: Buoncristiani:2020:ENS
author: Nicholas Buoncristiani and Sanjana Shah and David Donofrio and John Shalf
editor: IEEE
booktitle: 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)
title: Evaluating the Numerical Stability of Posit Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 612--621
year: 2020
DOI: https://doi.org/10.1109/IPDPS47924.2020.00069
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Nicholas Buoncristiani and Sanjana Shah and David Donofrio and John Shalf
rawbooktitle: {2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}
raweditor: {IEEE}
rawtitle: Evaluating the Numerical Stability of Posit Arithmetic
entry:
@InProceedings{Buoncristiani:2020:ENS,
  author =       "Nicholas Buoncristiani and Sanjana Shah and David
                 Donofrio and John Shalf",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE International Parallel and Distributed
                 Processing Symposium (IPDPS)}",
  title =        "Evaluating the Numerical Stability of Posit
                 Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "612--621",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/IPDPS47924.2020.00069",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Calligo:2020:PNU
author: Calligo Technologies
title: Posit Numeric Unit (PNU-IP)
pages: 612--621
year: 2020
bibdate: Sat Dec 16 15:24:16 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.16 15:24:16 ???
URL: https://calligotech.com/posit-numeric-unit-pnu-ip
keywords: posit arithmetic
acknowledgement: ack-nhfb
howpublished: Web software.
rawauthor: {Calligo Technologies}
rawtitle: Posit Numeric Unit ({PNU-IP})
entry:
@Misc{Calligo:2020:PNU,
  author =       "{Calligo Technologies}",
  title =        "Posit Numeric Unit ({PNU-IP})",
  howpublished = "Web software.",
  year =         "2020",
  bibdate =      "Sat Dec 16 15:24:16 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://calligotech.com/posit-numeric-unit-pnu-ip",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Cavalcante:2020:AGS
author: Matheus Cavalcante and Fabian Schuiki and Florian Zaruba and Michael Schaffner and Luca Benini
journal: j-IEEE-TRANS-VLSI-SYST
volume: 28
number: 2
pages: 530--543
year: 2020
CODEN: IEVSE9
DOI: https://doi.org/10.1109/TVLSI.2019.2950087
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: Matheus Cavalcante and Fabian Schuiki and Florian Zaruba and Michael Schaffner and Luca Benini
title:
Ara: a 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI

rawtitle:
{Ara}: a {1-GHz+} Scalable and Energy-Efficient {RISC-V} Vector Processor With Multiprecision Floating-Point Support in 22-nm {FD-SOI}

entry:
@Article{Cavalcante:2020:AGS,
  author =       "Matheus Cavalcante and Fabian Schuiki and Florian
                 Zaruba and Michael Schaffner and Luca Benini",
  title =        "{Ara}: a {1-GHz+} Scalable and Energy-Efficient
                 {RISC-V} Vector Processor With Multiprecision
                 Floating-Point Support in 22-nm {FD-SOI}",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "28",
  number =       "2",
  pages =        "530--543",
  year =         "2020",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2019.2950087",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}


bibtype: article
filename: fparith.bib
label: Cherubin:2020:TRP
author: Stefano Cherubin and Giovanni Agosta
title: Tools for Reduced Precision Computation: a Survey
journal: j-COMP-SURV
volume: 53
number: 2
pages: 33:1--33:35
month: jul
monthnumber: 7
year: 2020
CODEN: CMSVAN
DOI: https://doi.org/10.1145/3381039
ISSN: 0360-0300 (print), 1557-7341 (electronic) OR 03600300 (print), 15577341 (electronic)
ISSNL: 0360-0300 OR 03600300
bibdate: Wed Jul 8 17:24:43 MDT 2020
bibtimestamp: 2020.07.08 17:24:43 MDT
URL: https://dl.acm.org/doi/abs/10.1145/3381039
fjournal: ACM Computing Surveys
acknowledgement: ack-nhfb
articleno: 33
journalURL: https://dl.acm.org/loi/csur
rawauthor: Stefano Cherubin and Giovanni Agosta
rawtitle: Tools for Reduced Precision Computation: a Survey
bibsource:
https://www.math.utah.edu/pub/tex/bib/compsurv.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
The use of reduced precision to improve performance metrics such as computation latency and power consumption is a common practice in the embedded systems field. This practice is emerging as a new trend in High Performance Computing (HPC), especially when new error-tolerant applications are considered. However, standard compiler frameworks do not support automated precision customization, and manual tuning and code transformation is the approach usually adopted in most domains. In recent years, research have been studying ways to improve the automation of this process. This article surveys this body of work, identifying the critical steps of this process, the most advanced tools available, and the open challenges in this research area. We conclude that, while several mature tools exist, there is still a gap to close, especially for tools based on static analysis rather than profiling, as well as for integration within mainstream, industry-strength compiler frameworks.

rawabstract:
The use of reduced precision to improve performance metrics such as computation latency and power consumption is a common practice in the embedded systems field. This practice is emerging as a new trend in High Performance Computing (HPC), especially when new error-tolerant applications are considered. However, standard compiler frameworks do not support automated precision customization, and manual tuning and code transformation is the approach usually adopted in most domains. In recent years, research have been studying ways to improve the automation of this process. This article surveys this body of work, identifying the critical steps of this process, the most advanced tools available, and the open challenges in this research area. We conclude that, while several mature tools exist, there is still a gap to close, especially for tools based on static analysis rather than profiling, as well as for integration within mainstream, industry-strength compiler frameworks.

entry:
@Article{Cherubin:2020:TRP,
  author =       "Stefano Cherubin and Giovanni Agosta",
  title =        "Tools for Reduced Precision Computation: a Survey",
  journal =      j-COMP-SURV,
  volume =       "53",
  number =       "2",
  pages =        "33:1--33:35",
  month =        jul,
  year =         "2020",
  CODEN =        "CMSVAN",
  DOI =          "https://doi.org/10.1145/3381039",
  ISSN =         "0360-0300 (print), 1557-7341 (electronic)",
  ISSN-L =       "0360-0300",
  bibdate =      "Wed Jul 8 17:24:43 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compsurv.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3381039",
  abstract =     "The use of reduced precision to improve performance
                 metrics such as computation latency and power
                 consumption is a common practice in the embedded
                 systems field. This practice is emerging as a new trend
                 in High Performance Computing (HPC), especially when
                 new error-tolerant applications are considered.
                 However, standard compiler frameworks do not support
                 automated precision customization, and manual tuning
                 and code transformation is the approach usually adopted
                 in most domains. In recent years, research have been
                 studying ways to improve the automation of this
                 process. This article surveys this body of work,
                 identifying the critical steps of this process, the
                 most advanced tools available, and the open challenges
                 in this research area. We conclude that, while several
                 mature tools exist, there is still a gap to close,
                 especially for tools based on static analysis rather
                 than profiling, as well as for integration within
                 mainstream, industry-strength compiler frameworks.",
  acknowledgement = ack-nhfb,
  articleno =    "33",
  fjournal =     "ACM Computing Surveys",
  journal-URL =  "https://dl.acm.org/loi/csur",
}


bibtype: inproceedings
filename: fparith.bib
label: Chien:2020:PNA
author: Steven W. D. Chien and Ivy B. Peng and Stefano Markidis
title: Posit NPB: Assessing the Precision Improvement in HPC Scientific Applications
crossref: Wyrzykowski:2020:PPA
pages: 301--310
year: 2020
DOI: https://doi.org/10.1007/978-3-030-43229-4_26
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Steven W. D. Chien and Ivy B. Peng and Stefano Markidis
rawtitle: Posit {NPB}: Assessing the Precision Improvement in {HPC} Scientific Applications
entry:
@InProceedings{Chien:2020:PNA,
  author =       "Steven W. D. Chien and Ivy B. Peng and Stefano
                 Markidis",
  title =        "Posit {NPB}: Assessing the Precision Improvement in
                 {HPC} Scientific Applications",
  crossref =     "Wyrzykowski:2020:PPA",
  pages =        "301--310",
  year =         "2020",
  DOI =          "https://doi.org/10.1007/978-3-030-43229-4_26",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Chowdhary:2020:DDN
author: Sangeeta Chowdhary and Jay P. Lim and Santosh Nagarakatte
title: Debugging and detecting numerical errors in computation with posits
publisher: pub-ACM
address: pub-ACM:adr
pages: 731--746
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1145/3385412.3386004
bibdate: Sat Dec 9 08:43:53 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.09 08:43:53 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Sangeeta Chowdhary and Jay P. Lim and Santosh Nagarakatte
rawtitle: Debugging and detecting numerical errors in computation with posits
booktitle:
PLDI 2020: Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation

rawbooktitle:
{PLDI 2020: Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation}

entry:
@InProceedings{Chowdhary:2020:DDN,
  author =       "Sangeeta Chowdhary and Jay P. Lim and Santosh
                 Nagarakatte",
  booktitle =    "{PLDI 2020: Proceedings of the 41st ACM SIGPLAN
                 Conference on Programming Language Design and
                 Implementation}",
  title =        "Debugging and detecting numerical errors in
                 computation with posits",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "731--746",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1145/3385412.3386004",
  bibdate =      "Sat Dec 9 08:43:53 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Cococcioni:2020:FAH
author: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
booktitle: Applications in Electronics Pervading Industry, Environment and Society
publisher: pub-SV
address: pub-SV:adr
pages: 213--221
year: 2020
DOI: https://doi.org/10.1007/978-3-030-37277-4_25
ISBN: 3-030-37277-4 OR 3030372774
ISBN13: 978-3-030-37277-4 OR 9783030372774
ISSN: 1876-1119 OR 18761119
ISSNL: 1876-1100 OR 18761100
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
rawbooktitle: Applications in Electronics Pervading Industry, Environment and Society
title:
A Fast Approximation of the Hyperbolic Tangent When Using Posit Numbers and Its Application to Deep Neural Networks

rawtitle:
A Fast Approximation of the Hyperbolic Tangent When Using Posit Numbers and Its Application to Deep Neural Networks

entry:
@InProceedings{Cococcioni:2020:FAH,
  author =       "Marco Cococcioni and Federico Rossi and Emanuele
                 Ruffaldi and Sergio Saponara",
  booktitle =    "Applications in Electronics Pervading Industry,
                 Environment and Society",
  title =        "A Fast Approximation of the Hyperbolic Tangent When
                 Using Posit Numbers and Its Application to Deep Neural
                 Networks",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "213--221",
  year =         "2020",
  DOI =          "https://doi.org/10.1007/978-3-030-37277-4_25",
  ISBN =         "3-030-37277-4",
  ISBN-13 =      "978-3-030-37277-4",
  ISSN =         "1876-1119",
  ISSN-L =       "1876-1100",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: article
filename: fparith.bib
label: Cococcioni:2020:FDN
author: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
title: Fast deep neural networks for image processing using posits and ARM scalable vector extension
journal: Journal of Real-Time Image Processing
volume: 17
number: 3
publisher: pub-SV
address: pub-SV:adr
pages: 759--771
month: may
monthnumber: 5
year: 2020
DOI: https://doi.org/10.1007/s11554-020-00984-x
ISSN: 1861-8219 OR 18618219
ISSNL: 1861-8200 OR 18618200
bibdate: Fri Dec 15 11:31:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:31:31 ???
keywords: posit arithmetic
acknowledgement: ack-nhfb
rawauthor: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
rawtitle: Fast deep neural networks for image processing using posits and {ARM} scalable vector extension
entry:
@Article{Cococcioni:2020:FDN,
  author =       "Marco Cococcioni and Federico Rossi and Emanuele
                 Ruffaldi and Sergio Saponara",
  title =        "Fast deep neural networks for image processing using
                 posits and {ARM} scalable vector extension",
  journal =      "Journal of Real-Time Image Processing",
  volume =       "17",
  number =       "3",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "759--771",
  month =        may,
  year =         "2020",
  DOI =          "https://doi.org/10.1007/s11554-020-00984-x",
  ISSN =         "1861-8219",
  ISSN-L =       "1861-8200",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Cococcioni:2020:NPB
author: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
editor: IEEE
booktitle: 2020 IEEE International Conference on Smart Computing (SMARTCOMP)
title: A Novel Posit-based Fast Approximation of ELU Activation Function for Deep Neural Networks
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 244--246
year: 2020
DOI: https://doi.org/10.1109/SMARTCOMP50058.2020.00053
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Marco Cococcioni and Federico Rossi and Emanuele Ruffaldi and Sergio Saponara
rawbooktitle: {2020 IEEE International Conference on Smart Computing (SMARTCOMP)}
raweditor: {IEEE}
rawtitle: A Novel Posit-based Fast Approximation of {ELU} Activation Function for Deep Neural Networks
entry:
@InProceedings{Cococcioni:2020:NPB,
  author =       "Marco Cococcioni and Federico Rossi and Emanuele
                 Ruffaldi and Sergio Saponara",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE International Conference on Smart Computing
                 (SMARTCOMP)}",
  title =        "A Novel Posit-based Fast Approximation of {ELU}
                 Activation Function for Deep Neural Networks",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "244--246",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/SMARTCOMP50058.2020.00053",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Cornea:2020:FA
author: Marius Cornea and Weiqiang Liu and Arnaud Tisserand
title: Foreword ARITH 2020
crossref: Cornea:2020:ISC
pages: i--i
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00005
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Marius Cornea and Weiqiang Liu and Arnaud Tisserand
rawtitle: Foreword {ARITH 2020}
abstract:
The 27th IEEE Symposium on Computer Arithmetic, ARITH-2020, was initially planned to be held in Portland, Oregon, USA on Jun 7-10, 2020. Due to the COVID-19 crisis all around the world in 2020, the face-to-face meeting has been canceled. The paper selection process was completed, and the accepted papers have been included in the ARITH-2020 proceedings. For ARITH-2020, 73 anonymous submissions have been submitted at the beginning of February. Following the peer-review practice of this symposium, each paper was blind-reviewed by at least three, and up to five, Program Committee members, and a final decision was made by the committee in mid-April. 40 PC members and some external reviewers were involved in this process. The technical program of ARITH- 2020 includes 16 regular papers (8 pages) and 4 short papers (4 pages).

rawabstract:
The 27th IEEE Symposium on Computer Arithmetic, ARITH-2020, was initially planned to be held in Portland, Oregon, USA on Jun 7-10, 2020. Due to the COVID-19 crisis all around the world in 2020, the face-to-face meeting has been canceled. The paper selection process was completed, and the accepted papers have been included in the ARITH-2020 proceedings. For ARITH-2020, 73 anonymous submissions have been submitted at the beginning of February. Following the peer-review practice of this symposium, each paper was blind-reviewed by at least three, and up to five, Program Committee members, and a final decision was made by the committee in mid-April. 40 PC members and some external reviewers were involved in this process. The technical program of ARITH- 2020 includes 16 regular papers (8 pages) and 4 short papers (4 pages).

entry:
@InProceedings{Cornea:2020:FA,
  author =       "Marius Cornea and Weiqiang Liu and Arnaud Tisserand",
  title =        "Foreword {ARITH 2020}",
  crossref =     "Cornea:2020:ISC",
  pages =        "i--i",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00005",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The 27th IEEE Symposium on Computer Arithmetic,
                 ARITH-2020, was initially planned to be held in
                 Portland, Oregon, USA on Jun 7-10, 2020. Due to the
                 COVID-19 crisis all around the world in 2020, the
                 face-to-face meeting has been canceled. The paper
                 selection process was completed, and the accepted
                 papers have been included in the ARITH-2020
                 proceedings. For ARITH-2020, 73 anonymous submissions
                 have been submitted at the beginning of February.
                 Following the peer-review practice of this symposium,
                 each paper was blind-reviewed by at least three, and up
                 to five, Program Committee members, and a final
                 decision was made by the committee in mid-April. 40 PC
                 members and some external reviewers were involved in
                 this process. The technical program of ARITH- 2020
                 includes 16 regular papers (8 pages) and 4 short papers
                 (4 pages).",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Coward:2020:ADS
author: Samuel Coward and Theo Drane and Yoav Harel
title: Automatic Design Space Exploration for an Error Tolerant Application
crossref: Cornea:2020:ISC
pages: 117--120
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00025
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Samuel Coward and Theo Drane and Yoav Harel
rawtitle: Automatic Design Space Exploration for an Error Tolerant Application
abstract:
Creating optimized hardware for error tolerant applications presents significant challenges as well as opportunities. Many algorithms in computer graphics & vision are error tolerant, as their application level correctness ultimately rests on human perception. This error tolerance can be exploited in reducing hardware implementation cost. The challenge is how to explore the space of application level correct designs to determine the optimized hardware architecture. This paper puts forward an approach to automatically explore the space which maximally exploits the acceptable error to minimize hardware cost for a particular graphics algorithm --- Level-Of-Detail. Results, so far, have shown a 26% hardware area improvement.

keywords:
accuracy hardware tradeoffs; approximate computing; computer graphics; Computer graphics; Delays; design automation; floating-point; Hardware; Logic gates; Minimization; multiple-precision; numerical analysis; power-efficient; Space exploration

rawabstract:
Creating optimized hardware for error tolerant applications presents significant challenges as well as opportunities. Many algorithms in computer graphics & vision are error tolerant, as their application level correctness ultimately rests on human perception. This error tolerance can be exploited in reducing hardware implementation cost. The challenge is how to explore the space of application level correct designs to determine the optimized hardware architecture. This paper puts forward an approach to automatically explore the space which maximally exploits the acceptable error to minimize hardware cost for a particular graphics algorithm --- Level-Of-Detail. Results, so far, have shown a 26\% hardware area improvement.

entry:
@InProceedings{Coward:2020:ADS,
  author =       "Samuel Coward and Theo Drane and Yoav Harel",
  title =        "Automatic Design Space Exploration for an Error
                 Tolerant Application",
  crossref =     "Cornea:2020:ISC",
  pages =        "117--120",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00025",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Creating optimized hardware for error tolerant
                 applications presents significant challenges as well as
                 opportunities. Many algorithms in computer graphics &
                 vision are error tolerant, as their application level
                 correctness ultimately rests on human perception. This
                 error tolerance can be exploited in reducing hardware
                 implementation cost. The challenge is how to explore
                 the space of application level correct designs to
                 determine the optimized hardware architecture. This
                 paper puts forward an approach to automatically explore
                 the space which maximally exploits the acceptable error
                 to minimize hardware cost for a particular graphics
                 algorithm --- Level-Of-Detail. Results, so far, have
                 shown a 26\% hardware area improvement.",
  acknowledgement = ack-nhfb,
  keywords =     "accuracy hardware tradeoffs; approximate computing;
                 computer graphics; Computer graphics; Delays; design
                 automation; floating-point; Hardware; Logic gates;
                 Minimization; multiple-precision; numerical analysis;
                 power-efficient; Space exploration",
}


bibtype: inproceedings
filename: fparith.bib
label: Das:2020:SYR
author: Arnab Das and Ian Briggs and Ganesh Gopalakrishnan and Sriram Krishnamoorthy and Pavel Panchekha
title: Scalable yet Rigorous Floating-Point Error Analysis
crossref: IEEE:2020:SPI
pages: 1--14
year: 2020
bibdate: Mon Sep 11 06:40:11 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 06:40:11 ???
acknowledgement: ack-nhfb
articleno: 51
rawauthor: Arnab Das and Ian Briggs and Ganesh Gopalakrishnan and Sriram Krishnamoorthy and Pavel Panchekha
rawtitle: Scalable yet Rigorous Floating-Point Error Analysis
abstract:
Automated techniques for rigorous floating-point round-off error analysis are a prerequisite to placing important activities in HPC such as precision allocation, verification, and code optimization on a formal footing. Yet existing techniques cannot provide tight bounds for expressions beyond a few dozen operators --- barely enough for HPC. In this work, we offer an approach embedded in a new tool called Satire that scales error analysis by four orders of magnitude compared to today's best-of-class tools. We explain how three key ideas underlying Satire helps it attain such scale: path strength reduction, bound optimization, and abstraction. Satire provides tight bounds and rigorous guarantees on significantly larger expressions with well over a hundred thousand operators, covering important examples including FFT, matrix multiplication, and PDE stencils.

rawabstract:
Automated techniques for rigorous floating-point round-off error analysis are a prerequisite to placing important activities in HPC such as precision allocation, verification, and code optimization on a formal footing. Yet existing techniques cannot provide tight bounds for expressions beyond a few dozen operators --- barely enough for HPC. In this work, we offer an approach embedded in a new tool called Satire that scales error analysis by four orders of magnitude compared to today's best-of-class tools. We explain how three key ideas underlying Satire helps it attain such scale: path strength reduction, bound optimization, and abstraction. Satire provides tight bounds and rigorous guarantees on significantly larger expressions with well over a hundred thousand operators, covering important examples including FFT, matrix multiplication, and PDE stencils.

entry:
@InProceedings{Das:2020:SYR,
  author =       "Arnab Das and Ian Briggs and Ganesh Gopalakrishnan and
                 Sriram Krishnamoorthy and Pavel Panchekha",
  title =        "Scalable yet Rigorous Floating-Point Error Analysis",
  crossref =     "IEEE:2020:SPI",
  pages =        "1--14",
  year =         "2020",
  bibdate =      "Mon Sep 11 06:40:11 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Automated techniques for rigorous floating-point
                 round-off error analysis are a prerequisite to placing
                 important activities in HPC such as precision
                 allocation, verification, and code optimization on a
                 formal footing. Yet existing techniques cannot provide
                 tight bounds for expressions beyond a few dozen
                 operators --- barely enough for HPC. In this work, we
                 offer an approach embedded in a new tool called Satire
                 that scales error analysis by four orders of magnitude
                 compared to today's best-of-class tools. We explain how
                 three key ideas underlying Satire helps it attain such
                 scale: path strength reduction, bound optimization, and
                 abstraction. Satire provides tight bounds and rigorous
                 guarantees on significantly larger expressions with
                 well over a hundred thousand operators, covering
                 important examples including FFT, matrix
                 multiplication, and PDE stencils.",
  acknowledgement = ack-nhfb,
  articleno =    "51",
}


bibtype: article
filename: fparith.bib
label: deCamargo:2020:REA
author: Andre Pierro de Camargo
journal: j-NUMER-ALGORITHMS
volume: 85
number: 2
pages: 591--606
month: oct
monthnumber: 10
year: 2020
CODEN: NUALEG
DOI: https://doi.org/10.1007/s11075-019-00828-1
ISSN: 1017-1398 (print), 1572-9265 (electronic) OR 10171398 (print), 15729265 (electronic)
ISSNL: 1017-1398 OR 10171398
bibdate: Thu Sep 10 11:29:47 MDT 2020
bibtimestamp: 2020.09.10 11:29:47 MDT
URL: http://link.springer.com/article/10.1007/s11075-019-00828-1
fjournal: Numerical Algorithms
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11075
rawauthor: Andr{\'e} Pierro de Camargo
title:
Rounding error analysis of divided differences schemes: Newton's divided differences; Neville's algorithm; Richardson extrapolation; Romberg quadrature; etc.

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/numeralgorithms.bib

rawtitle:
Rounding error analysis of divided differences schemes: {Newton}'s divided differences; {Neville}'s algorithm; {Richardson} extrapolation; {Romberg} quadrature; etc.

entry:
@Article{deCamargo:2020:REA,
  author =       "Andr{\'e} Pierro de Camargo",
  title =        "Rounding error analysis of divided differences
                 schemes: {Newton}'s divided differences; {Neville}'s
                 algorithm; {Richardson} extrapolation; {Romberg}
                 quadrature; etc.",
  journal =      j-NUMER-ALGORITHMS,
  volume =       "85",
  number =       "2",
  pages =        "591--606",
  month =        oct,
  year =         "2020",
  CODEN =        "NUALEG",
  DOI =          "https://doi.org/10.1007/s11075-019-00828-1",
  ISSN =         "1017-1398 (print), 1572-9265 (electronic)",
  ISSN-L =       "1017-1398",
  bibdate =      "Thu Sep 10 11:29:47 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/numeralgorithms.bib",
  URL =          "http://link.springer.com/article/10.1007/s11075-019-00828-1",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerical Algorithms",
  journal-URL =  "http://link.springer.com/journal/11075",
}


bibtype: inproceedings
filename: fparith.bib
label: Defour:2020:CPM
author: David Defour and Pablo de Oliveira Castro and Matei Istoan and Eric Petit
title: Custom-Precision Mathematical Library Explorations for Code Profiling and Optimization
crossref: Cornea:2020:ISC
pages: 121--124
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00026
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: David Defour and Pablo de Oliveira Castro and Matei I{\c{s}}toan and Eric Petit
rawtitle: Custom-Precision Mathematical Library Explorations for Code Profiling and Optimization
abstract:
The typical processors used for scientific computing have fixed-width data-paths. This implies that mathematical libraries were specifically developed to target each of these fixed precisions (binary16, binary32, binary64). However, to address the increasing energy consumption and throughput requirements of scientific applications, library and hardware designers are moving beyond this one-size-fits-all approach. In this article we propose to study the effects and benefits of using user-defined floating-point formats and target accuracies in calculations involving mathematical functions. Our tool collects input-data profiles and iteratively explores lower precisions for each call-site of a mathematical function in user applications. This profiling data will be a valuable asset for specializing and fine-tuning mathematical function implementations for a given application. We demonstrate the tool's capabilities on SGP4, a satellite tracking application. The profile data shows the potential for specialization and provides insight into answering where it is useful to provide variable-precision designs for elementary function evaluation.

keywords:
custom-precision; floating-point; Hardware; HPC; libm; Libraries; Mathematical model; Optimization; optimization; Satellites; specialization; Standards; Tools

rawabstract:
The typical processors used for scientific computing have fixed-width data-paths. This implies that mathematical libraries were specifically developed to target each of these fixed precisions (binary16, binary32, binary64). However, to address the increasing energy consumption and throughput requirements of scientific applications, library and hardware designers are moving beyond this one-size-fits-all approach. In this article we propose to study the effects and benefits of using user-defined floating-point formats and target accuracies in calculations involving mathematical functions. Our tool collects input-data profiles and iteratively explores lower precisions for each call-site of a mathematical function in user applications. This profiling data will be a valuable asset for specializing and fine-tuning mathematical function implementations for a given application. We demonstrate the tool's capabilities on SGP4, a satellite tracking application. The profile data shows the potential for specialization and provides insight into answering where it is useful to provide variable-precision designs for elementary function evaluation.

entry:
@InProceedings{Defour:2020:CPM,
  author =       "David Defour and Pablo de Oliveira Castro and Matei
                 I{\c{s}}toan and Eric Petit",
  title =        "Custom-Precision Mathematical Library Explorations for
                 Code Profiling and Optimization",
  crossref =     "Cornea:2020:ISC",
  pages =        "121--124",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00026",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The typical processors used for scientific computing
                 have fixed-width data-paths. This implies that
                 mathematical libraries were specifically developed to
                 target each of these fixed precisions (binary16,
                 binary32, binary64). However, to address the increasing
                 energy consumption and throughput requirements of
                 scientific applications, library and hardware designers
                 are moving beyond this one-size-fits-all approach. In
                 this article we propose to study the effects and
                 benefits of using user-defined floating-point formats
                 and target accuracies in calculations involving
                 mathematical functions. Our tool collects input-data
                 profiles and iteratively explores lower precisions for
                 each call-site of a mathematical function in user
                 applications. This profiling data will be a valuable
                 asset for specializing and fine-tuning mathematical
                 function implementations for a given application. We
                 demonstrate the tool's capabilities on SGP4, a
                 satellite tracking application. The profile data shows
                 the potential for specialization and provides insight
                 into answering where it is useful to provide
                 variable-precision designs for elementary function
                 evaluation.",
  acknowledgement = ack-nhfb,
  keywords =     "custom-precision; floating-point; Hardware; HPC; libm;
                 Libraries; Mathematical model; Optimization;
                 optimization; Satellites; specialization; Standards;
                 Tools",
}


bibtype: inproceedings
filename: fparith.bib
label: Dinda:2020:SFP
author: Peter Dinda and Alex Bernat and Conor Hetland
title: Spying on the floating point behavior of existing, unmodified scientific applications
pages: 5--16
year: 2020
bibdate: Mon Sep 11 06:53:07 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 06:53:07 ???
acknowledgement: ack-nhfb
rawauthor: Peter Dinda and Alex Bernat and Conor Hetland
rawtitle: Spying on the floating point behavior of existing, unmodified scientific applications
booktitle:
Proceedings of the 29th International Symposium on High-Performance Parallel and Distributed Computing

rawbooktitle:
Proceedings of the 29th International Symposium on High-Performance Parallel and Distributed Computing

entry:
@InProceedings{Dinda:2020:SFP,
  author =       "Peter Dinda and Alex Bernat and Conor Hetland",
  editor =       "????",
  booktitle =    "Proceedings of the 29th International Symposium on
                 High-Performance Parallel and Distributed Computing",
  title =        "Spying on the floating point behavior of existing,
                 unmodified scientific applications",
  publisher =    "????",
  address =      "????",
  pages =        "5--16",
  year =         "2020",
  bibdate =      "Mon Sep 11 06:53:07 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Dolgov:2020:PCI
author: Sergey Dolgov and Dmitry Savostyanov
title: Parallel cross interpolation for high-precision calculation of high-dimensional integrals
journal: j-COMP-PHYS-COMM
volume: 246
pages: Article 106869
month: jan
monthnumber: 1
year: 2020
CODEN: CPHCBZ
DOI: https://doi.org/10.1016/j.cpc.2019.106869
ISSN: 0010-4655 (print), 1879-2944 (electronic) OR 00104655 (print), 18792944 (electronic)
ISSNL: 0010-4655 OR 00104655
bibdate: Tue Oct 29 14:07:57 MDT 2019
bibtimestamp: 2019.10.29 14:07:57 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0010465519302565
fjournal: Computer Physics Communications
remark: See cite Bailey:2006:IIC,Bailey:2015:HPA.
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00104655
rawauthor: Sergey Dolgov and Dmitry Savostyanov
rawtitle: Parallel cross interpolation for high-precision calculation of high-dimensional integrals
ORCID: Bailey, David H./0000-0002-7574-8342; Borwein, Jonathan/0000-0002-1263-0646
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/b/borwein-jonathan-m.bib; https://www.math.utah.edu/pub/tex/bib/compphyscomm2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
Cross interpolation; High precision; High-dimensional integration; Ising integrals; Ising model; Monte Carlo integration; Parallel algorithms; quasi Monte Carlo integration; Tensor train format

entry:
@Article{Dolgov:2020:PCI,
  author =       "Sergey Dolgov and Dmitry Savostyanov",
  title =        "Parallel cross interpolation for high-precision
                 calculation of high-dimensional integrals",
  journal =      j-COMP-PHYS-COMM,
  volume =       "246",
  number =       "??",
  pages =        "Article 106869",
  month =        jan,
  year =         "2020",
  CODEN =        "CPHCBZ",
  DOI =          "https://doi.org/10.1016/j.cpc.2019.106869",
  ISSN =         "0010-4655 (print), 1879-2944 (electronic)",
  ISSN-L =       "0010-4655",
  bibdate =      "Tue Oct 29 14:07:57 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/b/borwein-jonathan-m.bib;
                 https://www.math.utah.edu/pub/tex/bib/compphyscomm2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0010465519302565",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Physics Communications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00104655",
  keywords =     "Cross interpolation; High precision; High-dimensional
                 integration; Ising integrals; Ising model; Monte Carlo
                 integration; Parallel algorithms; quasi Monte Carlo
                 integration; Tensor train format",
  ORCID-numbers = "Bailey, David H./0000-0002-7574-8342; Borwein,
                 Jonathan/0000-0002-1263-0646",
  remark =       "See \cite{Bailey:2006:IIC,Bailey:2015:HPA}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Elkhatib:2020:HOM
author: Rami Elkhatib and Reza Azarderakhsh and Mehran Mozaffari-Kermani
title: Highly Optimized Montgomery Multiplier for SIKE Primes on FPGA
crossref: Cornea:2020:ISC
pages: 64--71
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00018
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Rami Elkhatib and Reza Azarderakhsh and Mehran Mozaffari-Kermani
rawtitle: Highly Optimized {Montgomery} Multiplier for {SIKE} Primes on {FPGA}
abstract:
New primes were proposed for Supersingular Isogeny Key Encapsulation (SIKE) in NIST standardization process of Round 2 after further cryptanalysis research showed that the security levels of the initial primes chosen were overestimated [1], [2]. In this paper, we develop a highly optimized Ep Montgomery multiplication algorithm and architecture that further utilizes the special form of SIKE prime compared to previous implementations available in the literature. We then implement SIKE for all Round 2 NIST security levels (SIKEp434 for NIST security level 1, SIKEp503 for NIST security level 2, SIKEp610 for NIST security level 3, and SIKEp751 for NIST security level 5) on Xilinx Virtex 7 using the proposed multiplier. Our best implementation (NIST security level 1) runs 29% faster and occupies 30% less hardware resources in comparison to the leading counterpart available in the literature [3] and implementations for other security levels achieved similar improvement.

keywords:
Computer architecture; Elliptic curve cryptography; Hardware; hardware architectures; isogeny-based cryptography; Montgomery multiplication; NIST; post-quantum cryptography; SIKE

rawabstract:
New primes were proposed for Supersingular Isogeny Key Encapsulation (SIKE) in NIST standardization process of Round 2 after further cryptanalysis research showed that the security levels of the initial primes chosen were overestimated [1], [2]. In this paper, we develop a highly optimized Ep Montgomery multiplication algorithm and architecture that further utilizes the special form of SIKE prime compared to previous implementations available in the literature. We then implement SIKE for all Round 2 NIST security levels (SIKEp434 for NIST security level 1, SIKEp503 for NIST security level 2, SIKEp610 for NIST security level 3, and SIKEp751 for NIST security level 5) on Xilinx Virtex 7 using the proposed multiplier. Our best implementation (NIST security level 1) runs 29\% faster and occupies 30\% less hardware resources in comparison to the leading counterpart available in the literature [3] and implementations for other security levels achieved similar improvement.

entry:
@InProceedings{Elkhatib:2020:HOM,
  author =       "Rami Elkhatib and Reza Azarderakhsh and Mehran
                 Mozaffari-Kermani",
  title =        "Highly Optimized {Montgomery} Multiplier for {SIKE}
                 Primes on {FPGA}",
  crossref =     "Cornea:2020:ISC",
  pages =        "64--71",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00018",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "New primes were proposed for Supersingular Isogeny Key
                 Encapsulation (SIKE) in NIST standardization process of
                 Round 2 after further cryptanalysis research showed
                 that the security levels of the initial primes chosen
                 were overestimated [1], [2]. In this paper, we develop
                 a highly optimized Ep Montgomery multiplication
                 algorithm and architecture that further utilizes the
                 special form of SIKE prime compared to previous
                 implementations available in the literature. We then
                 implement SIKE for all Round 2 NIST security levels
                 (SIKEp434 for NIST security level 1, SIKEp503 for NIST
                 security level 2, SIKEp610 for NIST security level 3,
                 and SIKEp751 for NIST security level 5) on Xilinx
                 Virtex 7 using the proposed multiplier. Our best
                 implementation (NIST security level 1) runs 29\% faster
                 and occupies 30\% less hardware resources in comparison
                 to the leading counterpart available in the literature
                 [3] and implementations for other security levels
                 achieved similar improvement.",
  acknowledgement = ack-nhfb,
  keywords =     "Computer architecture; Elliptic curve cryptography;
                 Hardware; hardware architectures; isogeny-based
                 cryptography; Montgomery multiplication; NIST;
                 post-quantum cryptography; SIKE",
}


bibtype: misc
filename: fparith.bib
label: Erickson:2020:GNF
author: Jack Erickson
title: Generate Native Floating-Point FPGA Implementations for Field-Oriented Control of Motors
pages: 64--71
day: 17
month: feb
monthnumber: 2
year: 2020
bibdate: Mon Feb 17 10:32:39 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.17 10:32:39 ???
acknowledgement: ack-nhfb
howpublished: MathWorks Web site.
rawauthor: Jack Erickson
rawtitle: Generate Native Floating-Point {FPGA} Implementations for Field-Oriented Control of Motors
URL:
https://www.mathworks.com/videos/generate-native-floating-point-fpga-implementations-for-field-oriented-control-of-motors.html

abstract:
HDL Coder now supports native floating-point code generation, where you can implement your high-dynamic range operations in single-precision floating point, and generate VHDL or Verilog code directly without converting to fixed-point types and operations.

rawabstract:
HDL Coder now supports native floating-point code generation, where you can implement your high-dynamic range operations in single-precision floating point, and generate VHDL or Verilog code directly without converting to fixed-point types and operations.

entry:
@Misc{Erickson:2020:GNF,
  author =       "Jack Erickson",
  title =        "Generate Native Floating-Point {FPGA} Implementations
                 for Field-Oriented Control of Motors",
  howpublished = "MathWorks Web site.",
  day =          "17",
  month =        feb,
  year =         "2020",
  bibdate =      "Mon Feb 17 10:32:39 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.mathworks.com/videos/generate-native-floating-point-fpga-implementations-for-field-oriented-control-of-motors.html",
  abstract =     "HDL Coder now supports native floating-point code
                 generation, where you can implement your high-dynamic
                 range operations in single-precision floating point,
                 and generate VHDL or Verilog code directly without
                 converting to fixed-point types and operations.",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Fog:2020:FPE
author: Agner Fog
title: Floating point exception tracking and NAN propagation
type: Report
institution: Technical University of Denmark
address: Lyngby, Denmark
pages: 10
day: 27
month: apr
monthnumber: 4
year: 2020
bibdate: Wed May 17 11:52:28 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.05.17 11:52:28 ???
URL: https://www.agner.org/optimize/nan_propagation.pdf
acknowledgement: ack-nhfb
rawauthor: Agner Fog
rawtitle: Floating point exception tracking and {NAN} propagation
abstract:
The most common methods for detecting floating point errors are based on exception trapping or a global status register. These methods are inefficient in modern systems that use out-of-order parallelism and single-instruction-multiple-data (SIMD) parallelism for improving performance. It is argued that a method based on NAN propagation is more efficient and deterministic. Problems with NAN propagation in current systems are discussed. Examples of implementation in the C++ vector class library and in an experimental instruction set named ForwardCom are presented. The IEEE-754 standard for floating point arithmetic may need adjustment to accommodate the needs of modern forms of parallelism.

rawabstract:
The most common methods for detecting floating point errors are based on exception trapping or a global status register. These methods are inefficient in modern systems that use out-of-order parallelism and single-instruction-multiple-data (SIMD) parallelism for improving performance. It is argued that a method based on NAN propagation is more efficient and deterministic. Problems with NAN propagation in current systems are discussed. Examples of implementation in the C++ vector class library and in an experimental instruction set named ForwardCom are presented. The IEEE-754 standard for floating point arithmetic may need adjustment to accommodate the needs of modern forms of parallelism.

entry:
@TechReport{Fog:2020:FPE,
  author =       "Agner Fog",
  title =        "Floating point exception tracking and {NAN}
                 propagation",
  type =         "Report",
  institution =  "Technical University of Denmark",
  address =      "Lyngby, Denmark",
  pages =        "10",
  day =          "27",
  month =        apr,
  year =         "2020",
  bibdate =      "Wed May 17 11:52:28 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.agner.org/optimize/nan_propagation.pdf",
  abstract =     "The most common methods for detecting floating point
                 errors are based on exception trapping or a global
                 status register. These methods are inefficient in
                 modern systems that use out-of-order parallelism and
                 single-instruction-multiple-data (SIMD) parallelism for
                 improving performance. It is argued that a method based
                 on NAN propagation is more efficient and deterministic.
                 Problems with NAN propagation in current systems are
                 discussed. Examples of implementation in the C++ vector
                 class library and in an experimental instruction set
                 named ForwardCom are presented. The IEEE-754 standard
                 for floating point arithmetic may need adjustment to
                 accommodate the needs of modern forms of parallelism.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Gallois-Wong:2020:OIP
author: Diane Gallois-Wong and Sylvie Boldo and Pascal Cuoq
title: Optimal inverse projection of floating-point addition
journal: j-NUMER-ALGORITHMS
volume: 83
number: 3
pages: 957--986
month: mar
monthnumber: 3
year: 2020
CODEN: NUALEG
DOI: https://doi.org/10.1007/s11075-019-00711-z
ISSN: 1017-1398 (print), 1572-9265 (electronic) OR 10171398 (print), 15729265 (electronic)
ISSNL: 1017-1398 OR 10171398
bibdate: Tue Feb 18 08:09:21 MST 2020
bibtimestamp: 2020.02.18 08:09:21 MST
fjournal: Numerical Algorithms
keywords: floating-point arithmetic; interval arithmetic
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11075
rawauthor: Diane Gallois-Wong and Sylvie Boldo and Pascal Cuoq
rawtitle: Optimal inverse projection of floating-point addition
bibsource:
http://link.springer.com/journal/11075/83/3; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/numeralgorithms.bib

entry:
@Article{Gallois-Wong:2020:OIP,
  author =       "Diane Gallois-Wong and Sylvie Boldo and Pascal Cuoq",
  title =        "Optimal inverse projection of floating-point
                 addition",
  journal =      j-NUMER-ALGORITHMS,
  volume =       "83",
  number =       "3",
  pages =        "957--986",
  month =        mar,
  year =         "2020",
  CODEN =        "NUALEG",
  DOI =          "https://doi.org/10.1007/s11075-019-00711-z",
  ISSN =         "1017-1398 (print), 1572-9265 (electronic)",
  ISSN-L =       "1017-1398",
  bibdate =      "Tue Feb 18 08:09:21 MST 2020",
  bibsource =    "http://link.springer.com/journal/11075/83/3;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/numeralgorithms.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerical Algorithms",
  journal-URL =  "http://link.springer.com/journal/11075",
  keywords =     "floating-point arithmetic; interval arithmetic",
}


bibtype: article
filename: fparith.bib
label: Godunov:2020:ACC
author: A. Godunov
title: Algorithms for Calculating Correctly Rounded Exponential Function in Double-Precision Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 9
pages: 1388--1400
month: sep
monthnumber: 9
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2020.2972901
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Aug 12 14:58:16 2020
bibtimestamp: 2020.08.12 14:58:16 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Godunov
rawtitle: Algorithms for Calculating Correctly Rounded Exponential Function in Double-Precision Arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib

abstract:
Correct rounding provides the best approximation of the exponential function by double-precision numbers. To obtain the correctly rounded exponential of some arguments, the exponential should be calculated with high accuracy. For small arguments, even higher accuracy is required. This article presents simple and very fast algorithms for small arguments. Yet another algorithm presented here demonstrates a good maximum execution time, which may be important for critical applications. This algorithm can be combined with some other already existing algorithms to achieve the best maximum and average execution times. All proposed algorithms calculate the correctly rounded exponential function for all rounding modes and use only double-precision arithmetic for computation. In the argument reduction step, precalculated tables are used. Test implementations of these algorithms were developed in C language and are portable. Full proofs are presented either in this article itself or in its appendices.

rawabstract:
Correct rounding provides the best approximation of the exponential function by double-precision numbers. To obtain the correctly rounded exponential of some arguments, the exponential should be calculated with high accuracy. For small arguments, even higher accuracy is required. This article presents simple and very fast algorithms for small arguments. Yet another algorithm presented here demonstrates a good maximum execution time, which may be important for critical applications. This algorithm can be combined with some other already existing algorithms to achieve the best maximum and average execution times. All proposed algorithms calculate the correctly rounded exponential function for all rounding modes and use only double-precision arithmetic for computation. In the argument reduction step, precalculated tables are used. Test implementations of these algorithms were developed in C language and are portable. Full proofs are presented either in this article itself or in its appendices.

entry:
@Article{Godunov:2020:ACC,
  author =       "A. Godunov",
  title =        "Algorithms for Calculating Correctly Rounded
                 Exponential Function in Double-Precision Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "9",
  pages =        "1388--1400",
  month =        sep,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2020.2972901",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Aug 12 14:58:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  abstract =     "Correct rounding provides the best approximation of
                 the exponential function by double-precision numbers.
                 To obtain the correctly rounded exponential of some
                 arguments, the exponential should be calculated with
                 high accuracy. For small arguments, even higher
                 accuracy is required. This article presents simple and
                 very fast algorithms for small arguments. Yet another
                 algorithm presented here demonstrates a good maximum
                 execution time, which may be important for critical
                 applications. This algorithm can be combined with some
                 other already existing algorithms to achieve the best
                 maximum and average execution times. All proposed
                 algorithms calculate the correctly rounded exponential
                 function for all rounding modes and use only
                 double-precision arithmetic for computation. In the
                 argument reduction step, precalculated tables are used.
                 Test implementations of these algorithms were developed
                 in C language and are portable. Full proofs are
                 presented either in this article itself or in its
                 appendices.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Gonzalez-Navarro:2020:NRN
author: S. Gonzalez-Navarro and J. Hormigo
title: New Results on Non-Normalized Floating-Point Formats
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 12
pages: 1733--1744
month: dec
monthnumber: 12
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2929039
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Nov 24 09:42:22 2020
bibtimestamp: 2020.11.24 09:42:22 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Gonz{\'a}lez-Navarro and J. Hormigo
rawtitle: New Results on Non-Normalized Floating-Point Formats
entry:
@Article{Gonzalez-Navarro:2020:NRN,
  author =       "S. Gonz{\'a}lez-Navarro and J. Hormigo",
  title =        "New Results on Non-Normalized Floating-Point Formats",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "12",
  pages =        "1733--1744",
  month =        dec,
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2929039",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Nov 24 09:42:22 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Goualard:2020:GRF
author: Frederic Goualard
title: Generating Random Floating-Point Numbers by Dividing Integers: a Case Study
crossref: Krzhizhanovskaya:2020:CSI
pages: 15--28
year: 2020
DOI: https://doi.org/10.1007/978-3-030-50417-5_2
bibdate: Thu Jun 25 07:31:47 2020
bibtimestamp: 2020.06.25 07:31:47 ???
acknowledgement: ack-nhfb
rawauthor: Fr{\'e}d{\'e}ric Goualard
rawtitle: Generating Random Floating-Point Numbers by Dividing Integers: a Case Study
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/julia.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib; https://www.math.utah.edu/pub/tex/bib/prng.bib

keywords:
error analysis; floating-point number; GMP; Julia; Matlab; Mersenne Twister; PRNG; pseudo-random numbers; random number

entry:
@InProceedings{Goualard:2020:GRF,
  author =       "Fr{\'e}d{\'e}ric Goualard",
  title =        "Generating Random Floating-Point Numbers by Dividing
                 Integers: a Case Study",
  crossref =     "Krzhizhanovskaya:2020:CSI",
  pages =        "15--28",
  year =         "2020",
  DOI =          "https://doi.org/10.1007/978-3-030-50417-5_2",
  bibdate =      "Thu Jun 25 07:31:47 2020",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/julia.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib;
                 https://www.math.utah.edu/pub/tex/bib/prng.bib",
  acknowledgement = ack-nhfb,
  keywords =     "error analysis; floating-point number; GMP; Julia;
                 Matlab; Mersenne Twister; PRNG; pseudo-random numbers;
                 random number",
}


bibtype: inproceedings
filename: fparith.bib
label: Graillat:2020:ASF
author: Stef Graillat and Vincent Lefevre and Jean-Michel Muller
title: Alternative Split Functions and Dekker's Product
crossref: Cornea:2020:ISC
pages: 41--47
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00015
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Stef Graillat and Vincent Lef{\`e}vre and Jean-Michel Muller
rawtitle: Alternative Split Functions and {Dekker}'s Product
abstract:
We introduce algorithms for splitting a positive binary floating-point number into two numbers of around half the system precision, using arithmetic operations all rounded either toward $-$ or toward $+$. We use these algorithms to compute exact products (i.e., to express the product of two floating-point numbers as the unevaluated sum of two floating-point numbers, the rounded product and an error term). This is similar to the classical Dekker product, adapted here to directed roundings.

keywords:
accurate products; Approximation algorithms; Cognition; Digital arithmetic; Floating-point arithmetic; Indexes; Lips; split functions; Standards; Switches

rawabstract:
We introduce algorithms for splitting a positive binary floating-point number into two numbers of around half the system precision, using arithmetic operations all rounded either toward $-$ or toward $+$. We use these algorithms to compute exact products (i.e., to express the product of two floating-point numbers as the unevaluated sum of two floating-point numbers, the rounded product and an error term). This is similar to the classical Dekker product, adapted here to directed roundings.

entry:
@InProceedings{Graillat:2020:ASF,
  author =       "Stef Graillat and Vincent Lef{\`e}vre and Jean-Michel
                 Muller",
  title =        "Alternative Split Functions and {Dekker}'s Product",
  crossref =     "Cornea:2020:ISC",
  pages =        "41--47",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00015",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We introduce algorithms for splitting a positive
                 binary floating-point number into two numbers of around
                 half the system precision, using arithmetic operations
                 all rounded either toward $-$ or toward $+$. We use
                 these algorithms to compute exact products (i.e., to
                 express the product of two floating-point numbers as
                 the unevaluated sum of two floating-point numbers, the
                 rounded product and an error term). This is similar to
                 the classical Dekker product, adapted here to directed
                 roundings.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate products; Approximation algorithms;
                 Cognition; Digital arithmetic; Floating-point
                 arithmetic; Indexes; Lips; split functions; Standards;
                 Switches",
}


bibtype: article
filename: fparith.bib
label: Grutzmacher:2020:APC
author: Thomas Grutzmacher and Terry Cojean and Goran Flegar and Hartwig Anzt and Enrique S. Quintana-Orti
title: Acceleration of PageRank with Customized Precision Based on Mantissa Segmentation
journal: j-TOPC
volume: 7
number: 1
pages: 4:1--4:19
month: apr
monthnumber: 4
year: 2020
DOI: https://doi.org/10.1145/3380934
ISSN: 2329-4949 (print), 2329-4957 (electronic) OR 23294949 (print), 23294957 (electronic)
ISSNL: 2329-4949 OR 23294949
bibdate: Mon Apr 6 08:56:55 MDT 2020
bibtimestamp: 2020.04.06 08:56:55 MDT
URL: https://dl.acm.org/doi/abs/10.1145/3380934
fjournal: ACM Transactions on Parallel Computing
acknowledgement: ack-nhfb
articleno: 4
journalURL: https://dl.acm.org/loi/topc
rawtitle: Acceleration of {PageRank} with Customized Precision Based on Mantissa Segmentation
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/pagerank.bib; https://www.math.utah.edu/pub/tex/bib/topc.bib

abstract:
We describe the application of a communication-reduction technique for the PageRank algorithm that dynamically adapts the precision of the data access to the numerical requirements of the algorithm as the iteration converges. Our variable-precision strategy, using a customized precision format based on mantissa segmentation (CPMS), abandons the IEEE 754 single- and double-precision number representation formats employed in the standard implementation of PageRank, and instead handles the data in memory using a customized floating-point format. The customized format enables fast data access in different accuracy, prevents overflow/underflow by preserving the IEEE 754 double-precision exponent, and efficiently avoids data duplication, since all bits of the original IEEE 754 double-precision mantissa are preserved in memory, but re-organized for efficient reduced precision access. With this approach, the truncated values (omitting significand bits), as well as the original IEEE double-precision values, can be retrieved without duplicating the data in different formats.par Our numerical experiments on an NVIDIA V100 GPU (Volta architecture) and a server equipped with two Intel Xeon Platinum 8168 CPUs (48 cores in total) expose that, compared with a standard IEEE double-precision implementation, the CPMS-based PageRank completes about 10% faster if high-accuracy output is needed, and about 30% faster if reduced output accuracy is acceptable.

rawabstract:
We describe the application of a communication-reduction technique for the PageRank algorithm that dynamically adapts the precision of the data access to the numerical requirements of the algorithm as the iteration converges. Our variable-precision strategy, using a customized precision format based on mantissa segmentation (CPMS), abandons the IEEE 754 single- and double-precision number representation formats employed in the standard implementation of PageRank, and instead handles the data in memory using a customized floating-point format. The customized format enables fast data access in different accuracy, prevents overflow/underflow by preserving the IEEE 754 double-precision exponent, and efficiently avoids data duplication, since all bits of the original IEEE 754 double-precision mantissa are preserved in memory, but re-organized for efficient reduced precision access. With this approach, the truncated values (omitting significand bits), as well as the original IEEE double-precision values, can be retrieved without duplicating the data in different formats.\par Our numerical experiments on an NVIDIA V100 GPU (Volta architecture) and a server equipped with two Intel Xeon Platinum 8168 CPUs (48 cores in total) expose that, compared with a standard IEEE double-precision implementation, the CPMS-based PageRank completes about 10\% faster if high-accuracy output is needed, and about 30\% faster if reduced output accuracy is acceptable.

rawauthor:
Thomas Gr{\"u}tzmacher and Terry Cojean and Goran Flegar and Hartwig Anzt and Enrique S. Quintana-Ort{\'\i}

entry:
@Article{Grutzmacher:2020:APC,
  author =       "Thomas Gr{\"u}tzmacher and Terry Cojean and Goran
                 Flegar and Hartwig Anzt and Enrique S.
                 Quintana-Ort{\'\i}",
  title =        "Acceleration of {PageRank} with Customized Precision
                 Based on Mantissa Segmentation",
  journal =      j-TOPC,
  volume =       "7",
  number =       "1",
  pages =        "4:1--4:19",
  month =        apr,
  year =         "2020",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3380934",
  ISSN =         "2329-4949 (print), 2329-4957 (electronic)",
  ISSN-L =       "2329-4949",
  bibdate =      "Mon Apr 6 08:56:55 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/pagerank.bib;
                 https://www.math.utah.edu/pub/tex/bib/topc.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3380934",
  abstract =     "We describe the application of a
                 communication-reduction technique for the PageRank
                 algorithm that dynamically adapts the precision of the
                 data access to the numerical requirements of the
                 algorithm as the iteration converges. Our
                 variable-precision strategy, using a customized
                 precision format based on mantissa segmentation (CPMS),
                 abandons the IEEE 754 single- and double-precision
                 number representation formats employed in the standard
                 implementation of PageRank, and instead handles the
                 data in memory using a customized floating-point
                 format. The customized format enables fast data access
                 in different accuracy, prevents overflow/underflow by
                 preserving the IEEE 754 double-precision exponent, and
                 efficiently avoids data duplication, since all bits of
                 the original IEEE 754 double-precision mantissa are
                 preserved in memory, but re-organized for efficient
                 reduced precision access. With this approach, the
                 truncated values (omitting significand bits), as well
                 as the original IEEE double-precision values, can be
                 retrieved without duplicating the data in different
                 formats.\par

                 Our numerical experiments on an NVIDIA V100 GPU (Volta
                 architecture) and a server equipped with two Intel Xeon
                 Platinum 8168 CPUs (48 cores in total) expose that,
                 compared with a standard IEEE double-precision
                 implementation, the CPMS-based PageRank completes about
                 10\% faster if high-accuracy output is needed, and
                 about 30\% faster if reduced output accuracy is
                 acceptable.",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Transactions on Parallel Computing",
  journal-URL =  "https://dl.acm.org/loi/topc",
}


bibtype: inproceedings
filename: fparith.bib
label: Gu:2020:NMM
author: Zhen Gu and Shuguo Li
title: A Novel Method of Modular Multiplication Based on Karatsuba-like Multiplication
crossref: Cornea:2020:ISC
pages: 33--40
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00014
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Zhen Gu and Shuguo Li
rawtitle: A Novel Method of Modular Multiplication Based on {Karatsuba}-like Multiplication
abstract:
In this paper, we propose a novel method of modular multiplication which embeds the modular reduction in the evaluation and interpolation parts of the Karatsuba-like multiplication. Before, the modular reduction can only be performed independently between multiplication. However, applying our method, the interpolation of the previous multiplication, modular reduction and evaluation of the next multiplication are merged as a whole step, which leads to the simplification of computations and improvement of parallelism. This method can be applied to the modular multiplication with simple moduli like NIST primes, and for general moduli, we can apply this method by using Montgomery modular multiplication instead.

keywords:
Digital arithmetic; Interpolation; Karatsuba-like multiplication; Microelectronics; Modular multiplication; Montgomery modular multiplication; NIST; Public key cryptography; Transforms

rawabstract:
In this paper, we propose a novel method of modular multiplication which embeds the modular reduction in the evaluation and interpolation parts of the Karatsuba-like multiplication. Before, the modular reduction can only be performed independently between multiplication. However, applying our method, the interpolation of the previous multiplication, modular reduction and evaluation of the next multiplication are merged as a whole step, which leads to the simplification of computations and improvement of parallelism. This method can be applied to the modular multiplication with simple moduli like NIST primes, and for general moduli, we can apply this method by using Montgomery modular multiplication instead.

entry:
@InProceedings{Gu:2020:NMM,
  author =       "Zhen Gu and Shuguo Li",
  title =        "A Novel Method of Modular Multiplication Based on
                 {Karatsuba}-like Multiplication",
  crossref =     "Cornea:2020:ISC",
  pages =        "33--40",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00014",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper, we propose a novel method of modular
                 multiplication which embeds the modular reduction in
                 the evaluation and interpolation parts of the
                 Karatsuba-like multiplication. Before, the modular
                 reduction can only be performed independently between
                 multiplication. However, applying our method, the
                 interpolation of the previous multiplication, modular
                 reduction and evaluation of the next multiplication are
                 merged as a whole step, which leads to the
                 simplification of computations and improvement of
                 parallelism. This method can be applied to the modular
                 multiplication with simple moduli like NIST primes, and
                 for general moduli, we can apply this method by using
                 Montgomery modular multiplication instead.",
  acknowledgement = ack-nhfb,
  keywords =     "Digital arithmetic; Interpolation; Karatsuba-like
                 multiplication; Microelectronics; Modular
                 multiplication; Montgomery modular multiplication;
                 NIST; Public key cryptography; Transforms",
}


bibtype: inproceedings
filename: fparith.bib
label: Guo:2020:EGE
author: Hui Guo and Cindy Rubio-Gonzalez
booktitle: Proceedings of the ACM/IEEE 42nd International Conference on Software Engineering
title: Efficient generation of error-inducing floating-point inputs via symbolic execution
publisher: pub-ACM
address: pub-ACM:adr
pages: 33--40
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1145/3377811.3380359
bibdate: Sat Dec 9 08:57:26 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.09 08:57:26 ???
acknowledgement: ack-nhfb
rawauthor: Hui Guo and Cindy Rubio-Gonz{\'a}lez
rawbooktitle: Proceedings of the {ACM/IEEE 42nd International Conference on Software Engineering}
rawtitle: Efficient generation of error-inducing floating-point inputs via symbolic execution
abstract:
Floating point is widely used in software to emulate arithmetic over reals. Unfortunately, floating point leads to rounding errors that propagate and accumulate during execution. Generating inputs to maximize the numerical error is critical when evaluating the accuracy of floating-point code. In this paper, we formulate the problem of generating high error-inducing floating-point inputs as a code coverage maximization problem solved using symbolic execution. Specifically, we define inaccuracy checks to detect large precision loss and cancellation. We inject these checks at strategic program locations to construct specialized branches that, when covered by a given input, are likely to lead to large errors in the result. We apply symbolic execution to generate inputs that exercise these specialized branches, and describe optimizations that make our approach practical. We implement a tool named FPGen and present an evaluation on 21 numerical programs including matrix computation and statistics libraries. We show that FPGen exposes errors for 20 of these programs and triggers errors that are, on average, over 2 orders of magnitude larger than the state of the art.

rawabstract:
Floating point is widely used in software to emulate arithmetic over reals. Unfortunately, floating point leads to rounding errors that propagate and accumulate during execution. Generating inputs to maximize the numerical error is critical when evaluating the accuracy of floating-point code. In this paper, we formulate the problem of generating high error-inducing floating-point inputs as a code coverage maximization problem solved using symbolic execution. Specifically, we define inaccuracy checks to detect large precision loss and cancellation. We inject these checks at strategic program locations to construct specialized branches that, when covered by a given input, are likely to lead to large errors in the result. We apply symbolic execution to generate inputs that exercise these specialized branches, and describe optimizations that make our approach practical. We implement a tool named FPGen and present an evaluation on 21 numerical programs including matrix computation and statistics libraries. We show that FPGen exposes errors for 20 of these programs and triggers errors that are, on average, over 2 orders of magnitude larger than the state of the art.

entry:
@InProceedings{Guo:2020:EGE,
  author =       "Hui Guo and Cindy Rubio-Gonz{\'a}lez",
  booktitle =    "Proceedings of the {ACM/IEEE 42nd International
                 Conference on Software Engineering}",
  title =        "Efficient generation of error-inducing floating-point
                 inputs via symbolic execution",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1145/3377811.3380359",
  bibdate =      "Sat Dec 9 08:57:26 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Floating point is widely used in software to emulate
                 arithmetic over reals. Unfortunately, floating point
                 leads to rounding errors that propagate and accumulate
                 during execution. Generating inputs to maximize the
                 numerical error is critical when evaluating the
                 accuracy of floating-point code. In this paper, we
                 formulate the problem of generating high error-inducing
                 floating-point inputs as a code coverage maximization
                 problem solved using symbolic execution. Specifically,
                 we define inaccuracy checks to detect large precision
                 loss and cancellation. We inject these checks at
                 strategic program locations to construct specialized
                 branches that, when covered by a given input, are
                 likely to lead to large errors in the result. We apply
                 symbolic execution to generate inputs that exercise
                 these specialized branches, and describe optimizations
                 that make our approach practical. We implement a tool
                 named FPGen and present an evaluation on 21 numerical
                 programs including matrix computation and statistics
                 libraries. We show that FPGen exposes errors for 20 of
                 these programs and triggers errors that are, on
                 average, over 2 orders of magnitude larger than the
                 state of the art.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Guo:2020:PIL
author: Hui Guo and Ignacio Laguna and Cindy Rubio-Gonzalez
title: pLiner: isolating lines of floating-point code for compiler-induced variability
crossref: IEEE:2020:SPI
pages: 1--14
year: 2020
bibdate: Mon Sep 11 08:22:13 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 08:22:13 ???
acknowledgement: ack-nhfb
articleno: 49
rawauthor: Hui Guo and Ignacio Laguna and Cindy Rubio-Gonz{\'a}lez
rawtitle: {pLiner}: isolating lines of floating-point code for compiler-induced variability
abstract:
Scientific applications are often impacted by numerical inconsistencies when using different compilers or when a compiler is used with different optimization levels; such inconsistencies hinder reproducibility and can be hard to diagnose. We present pLiner, a tool to automatically pinpoint code lines that trigger compiler-induced variability. pLiner uses a novel approach to enhance floating-point precision at different levels of code granularity, and performs a guided search to identify locations affected by numerical inconsistencies. We demonstrate pLiner on a real-world numerical inconsistency that required weeks to diagnose, which pLiner isolates in minutes. We also evaluate pLiner on 100 synthetic programs, and the NAS Parallel Benchmarks (NPB). On the synthetic programs, pLiner detects the affected lines of code 87% of the time while the state-of-the-art approach only detects the affected lines 6% of the time. Furthermore, pLiner successfully isolates all numerical inconsistencies found in the NPB.

rawabstract:
Scientific applications are often impacted by numerical inconsistencies when using different compilers or when a compiler is used with different optimization levels; such inconsistencies hinder reproducibility and can be hard to diagnose. We present pLiner, a tool to automatically pinpoint code lines that trigger compiler-induced variability. pLiner uses a novel approach to enhance floating-point precision at different levels of code granularity, and performs a guided search to identify locations affected by numerical inconsistencies. We demonstrate pLiner on a real-world numerical inconsistency that required weeks to diagnose, which pLiner isolates in minutes. We also evaluate pLiner on 100 synthetic programs, and the NAS Parallel Benchmarks (NPB). On the synthetic programs, pLiner detects the affected lines of code 87\% of the time while the state-of-the-art approach only detects the affected lines 6\% of the time. Furthermore, pLiner successfully isolates all numerical inconsistencies found in the NPB.

entry:
@InProceedings{Guo:2020:PIL,
  author =       "Hui Guo and Ignacio Laguna and Cindy
                 Rubio-Gonz{\'a}lez",
  title =        "{pLiner}: isolating lines of floating-point code for
                 compiler-induced variability",
  crossref =     "IEEE:2020:SPI",
  pages =        "1--14",
  year =         "2020",
  bibdate =      "Mon Sep 11 08:22:13 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Scientific applications are often impacted by
                 numerical inconsistencies when using different
                 compilers or when a compiler is used with different
                 optimization levels; such inconsistencies hinder
                 reproducibility and can be hard to diagnose. We present
                 pLiner, a tool to automatically pinpoint code lines
                 that trigger compiler-induced variability. pLiner uses
                 a novel approach to enhance floating-point precision at
                 different levels of code granularity, and performs a
                 guided search to identify locations affected by
                 numerical inconsistencies. We demonstrate pLiner on a
                 real-world numerical inconsistency that required weeks
                 to diagnose, which pLiner isolates in minutes. We also
                 evaluate pLiner on 100 synthetic programs, and the NAS
                 Parallel Benchmarks (NPB). On the synthetic programs,
                 pLiner detects the affected lines of code 87\% of the
                 time while the state-of-the-art approach only detects
                 the affected lines 6\% of the time. Furthermore, pLiner
                 successfully isolates all numerical inconsistencies
                 found in the NPB.",
  acknowledgement = ack-nhfb,
  articleno =    "49",
}


bibtype: techreport
filename: fparith.bib
label: Harvey:2020:IMT
author: David Harvey and Joris van der Hoeven
title: Integer multiplication in time $ O(n log n) $
type: Report
number: hal-02070778
institution: School of Mathematics and Statistics, University of New South Wales
address: Sydney NSW 2052, Australia
pages: 45
day: 28
month: nov
monthnumber: 11
year: 2020
bibdate: Thu May 16 15:51:09 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.16 15:51:09 ???
URL: https://hal.science/hal-02070778v2
acknowledgement: ack-nhfb
rawauthor: David Harvey and Joris van der Hoeven
rawtitle: Integer multiplication in time {$ O(n \log n) $}
abstract:
We present an algorithm that computes the product of two $n$-bit integers in $ O(n log n)$ bit operations, thus con rming a conjecture of Schonhage and Strassen from 1971. Our complexity analysis takes place in the multitape Turing machine model, with integers encoded in the usual binary representation. Central to the new algorithm is a novel Gaussian resampling technique that enables us to reduce the integer multiplication problem to a collection of multidimensional discrete Fourier transforms over the complex numbers, whose dimensions are all powers of two. These transforms may then be evaluated rapidly by means of Nussbaumer's fast polynomial transforms.

rawabstract:
We present an algorithm that computes the product of two $n$-bit integers in $ O(n \log n)$ bit operations, thus con rming a conjecture of Sch{\"o}nhage and Strassen from 1971. Our complexity analysis takes place in the multitape Turing machine model, with integers encoded in the usual binary representation. Central to the new algorithm is a novel Gaussian resampling technique that enables us to reduce the integer multiplication problem to a collection of multidimensional discrete Fourier transforms over the complex numbers, whose dimensions are all powers of two. These transforms may then be evaluated rapidly by means of Nussbaumer's fast polynomial transforms.

entry:
@TechReport{Harvey:2020:IMT,
  author =       "David Harvey and Joris van der Hoeven",
  title =        "Integer multiplication in time {$ O(n \log n) $}",
  type =         "Report",
  number =       "hal-02070778",
  institution =  "School of Mathematics and Statistics, University of
                 New South Wales",
  address =      "Sydney NSW 2052, Australia",
  pages =        "45",
  day =          "28",
  month =        nov,
  year =         "2020",
  bibdate =      "Thu May 16 15:51:09 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.science/hal-02070778v2",
  abstract =     "We present an algorithm that computes the product of
                 two $n$-bit integers in $ O(n \log n)$ bit operations,
                 thus con rming a conjecture of Sch{\"o}nhage and
                 Strassen from 1971. Our complexity analysis takes place
                 in the multitape Turing machine model, with integers
                 encoded in the usual binary representation. Central to
                 the new algorithm is a novel Gaussian resampling
                 technique that enables us to reduce the integer
                 multiplication problem to a collection of
                 multidimensional discrete Fourier transforms over the
                 complex numbers, whose dimensions are all powers of
                 two. These transforms may then be evaluated rapidly by
                 means of Nussbaumer's fast polynomial transforms.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Hickmann:2020:INN
title: Intel Nervana Neural Network Processor-T (NNP-T) Fused Floating Point Many-Term Dot Product
crossref: Cornea:2020:ISC
pages: 133--136
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00029
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawtitle: {Intel Nervana Neural Network Processor-T (NNP-T)} Fused Floating Point Many-Term Dot Product
author:
Brian Hickmann and Jieasheng Chen and Michael Rotzin and Andrew Yang and Maciej Urbanski and Sasikanth Avancha

abstract:
Intel's Nervana Neural Network Processor for Training (NNP-T) contains at its core an advanced floating point dot product design to accelerate the matrix multiplication operations found in many AI applications. Each Matrix Processing Unit (MPU) on the Intel NNP-T can process a 32x32 BFloat16 matrix multiplication every 32 cycles, accumulating the result in single precision (FP32). To reduce hardware costs, the MPU uses a fused many-term floating point dot product design with block alignment of the many input terms during addition, resulting in a unique datapath with several interesting design trade-offs. In this paper, we describe the details of the MPU pipeline, discuss the trade-offs made in the design, and present information on the accuracy of the computation as compared to traditional FMA implementations.

keywords:
Adders; Artificial neural networks; deep learning; floating point dot product; Hardware; Machine learning; matrix multiplication; Tensile stress; tensor; Training

rawabstract:
Intel's Nervana Neural Network Processor for Training (NNP-T) contains at its core an advanced floating point dot product design to accelerate the matrix multiplication operations found in many AI applications. Each Matrix Processing Unit (MPU) on the Intel NNP-T can process a 32x32 BFloat16 matrix multiplication every 32 cycles, accumulating the result in single precision (FP32). To reduce hardware costs, the MPU uses a fused many-term floating point dot product design with block alignment of the many input terms during addition, resulting in a unique datapath with several interesting design trade-offs. In this paper, we describe the details of the MPU pipeline, discuss the trade-offs made in the design, and present information on the accuracy of the computation as compared to traditional FMA implementations.

rawauthor:
Brian Hickmann and Jieasheng Chen and Michael Rotzin and Andrew Yang and Maciej Urbanski and Sasikanth Avancha

entry:
@InProceedings{Hickmann:2020:INN,
  author =       "Brian Hickmann and Jieasheng Chen and Michael Rotzin
                 and Andrew Yang and Maciej Urbanski and Sasikanth
                 Avancha",
  title =        "{Intel Nervana Neural Network Processor-T (NNP-T)}
                 Fused Floating Point Many-Term Dot Product",
  crossref =     "Cornea:2020:ISC",
  pages =        "133--136",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00029",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Intel's Nervana Neural Network Processor for Training
                 (NNP-T) contains at its core an advanced floating point
                 dot product design to accelerate the matrix
                 multiplication operations found in many AI
                 applications. Each Matrix Processing Unit (MPU) on the
                 Intel NNP-T can process a 32x32 BFloat16 matrix
                 multiplication every 32 cycles, accumulating the result
                 in single precision (FP32). To reduce hardware costs,
                 the MPU uses a fused many-term floating point dot
                 product design with block alignment of the many input
                 terms during addition, resulting in a unique datapath
                 with several interesting design trade-offs. In this
                 paper, we describe the details of the MPU pipeline,
                 discuss the trade-offs made in the design, and present
                 information on the accuracy of the computation as
                 compared to traditional FMA implementations.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; Artificial neural networks; deep learning;
                 floating point dot product; Hardware; Machine learning;
                 matrix multiplication; Tensile stress; tensor;
                 Training",
}


bibtype: article
filename: fparith.bib
label: Hopkins:2020:SRR
author: Michael Hopkins and Mantas Mikaitis and Dave R. Lester and Steve Furber
journal: j-PHILOS-TRANS-R-SOC-LOND-SER-A
volume: 378
number: 2166
pages: 20190052
month: jan
monthnumber: 1
year: 2020
CODEN: PTRMAD, PTMSFB
DOI: https://doi.org/10.1098/rsta.2019.0052
ISSN: 1364-503X (print), 1471-2962 (electronic) OR 1364503X (print), 14712962 (electronic)
ISSNL: 1364-503X OR 1364503X
bibdate: Fri Sep 22 17:51:44 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 17:51:44 ???
fjournal: Philosophical Transactions of the Royal Society A: Mathematical, Physical, and Engineering Sciences
acknowledgement: ack-nhfb
journalURL: http://rsta.royalsocietypublishing.org/
rawauthor: Michael Hopkins and Mantas Mikaitis and Dave R. Lester and Steve Furber
title:
Stochastic rounding and reduced-precision fixed-point arithmetic for solving neural ordinary differential equations

rawtitle:
Stochastic rounding and reduced-precision fixed-point arithmetic for solving neural ordinary differential equations

entry:
@Article{Hopkins:2020:SRR,
  author =       "Michael Hopkins and Mantas Mikaitis and Dave R. Lester
                 and Steve Furber",
  title =        "Stochastic rounding and reduced-precision fixed-point
                 arithmetic for solving neural ordinary differential
                 equations",
  journal =      j-PHILOS-TRANS-R-SOC-LOND-SER-A,
  volume =       "378",
  number =       "2166",
  pages =        "20190052",
  month =        jan,
  year =         "2020",
  CODEN =        "PTRMAD, PTMSFB",
  DOI =          "https://doi.org/10.1098/rsta.2019.0052",
  ISSN =         "1364-503X (print), 1471-2962 (electronic)",
  ISSN-L =       "1364-503X",
  bibdate =      "Fri Sep 22 17:51:44 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Philosophical Transactions of the Royal Society A:
                 Mathematical, Physical, and Engineering Sciences",
  journal-URL =  "http://rsta.royalsocietypublishing.org/",
}


bibtype: inproceedings
filename: fparith.bib
label: Hormigo:2020:FPF
author: Javier Hormigo and Julio Villalba-Moreno and Sonia Gonzalez-Navarro
title: Floating Point Fused Multiply Add under HUB Format
crossref: Cornea:2020:ISC
pages: 1--8
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00010
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Javier Hormigo and Julio Villalba-Moreno and Sonia Gonzalez-Navarro
rawtitle: Floating Point Fused Multiply Add under {HUB} Format
abstract:
The Half-Unit-Biased (HUB) format has interesting advantages for implementing floating-point arithmetic which has been proved for the four basic arithmetic operations as well as square root. Nevertheless, although Floating-point Fused Multiply-add (FMA) operation ($ A times B + C$) is one of the most important and complex arithmetic instructions in modern processors, FMA operation for HUB numbers has not been confronted yet. In this paper, we present a design to deal with this operation under HUB format. The key points to turn the conventional FMA architecture into a HUB unit are explained. Comparing the ASIC implementation of a HUB FMA unit with the conventional one, the former reduces the required area and power up to 38% and 35%, respectively, for single-precision. For BFloat16, the HUB FMA increases the speed a 15%, and even then, reduces the area and power by 26% and 12%, respectively.

keywords:
Computer architecture; Deep-learning; Delays; Digital arithmetic; DSP applications; Fused multiplication-addition; Hardware; HUB format; Inverters; Program processors; Standards

rawabstract:
The Half-Unit-Biased (HUB) format has interesting advantages for implementing floating-point arithmetic which has been proved for the four basic arithmetic operations as well as square root. Nevertheless, although Floating-point Fused Multiply-add (FMA) operation ($ A \times B + C$) is one of the most important and complex arithmetic instructions in modern processors, FMA operation for HUB numbers has not been confronted yet. In this paper, we present a design to deal with this operation under HUB format. The key points to turn the conventional FMA architecture into a HUB unit are explained. Comparing the ASIC implementation of a HUB FMA unit with the conventional one, the former reduces the required area and power up to 38\% and 35\%, respectively, for single-precision. For BFloat16, the HUB FMA increases the speed a 15\%, and even then, reduces the area and power by 26\% and 12\%, respectively.

entry:
@InProceedings{Hormigo:2020:FPF,
  author =       "Javier Hormigo and Julio Villalba-Moreno and Sonia
                 Gonzalez-Navarro",
  title =        "Floating Point Fused Multiply Add under {HUB} Format",
  crossref =     "Cornea:2020:ISC",
  pages =        "1--8",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00010",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Half-Unit-Biased (HUB) format has interesting
                 advantages for implementing floating-point arithmetic
                 which has been proved for the four basic arithmetic
                 operations as well as square root. Nevertheless,
                 although Floating-point Fused Multiply-add (FMA)
                 operation ($ A \times B + C$) is one of the most
                 important and complex arithmetic instructions in modern
                 processors, FMA operation for HUB numbers has not been
                 confronted yet. In this paper, we present a design to
                 deal with this operation under HUB format. The key
                 points to turn the conventional FMA architecture into a
                 HUB unit are explained. Comparing the ASIC
                 implementation of a HUB FMA unit with the conventional
                 one, the former reduces the required area and power up
                 to 38\% and 35\%, respectively, for single-precision.
                 For BFloat16, the HUB FMA increases the speed a 15\%,
                 and even then, reduces the area and power by 26\% and
                 12\%, respectively.",
  acknowledgement = ack-nhfb,
  keywords =     "Computer architecture; Deep-learning; Delays; Digital
                 arithmetic; DSP applications; Fused
                 multiplication-addition; Hardware; HUB format;
                 Inverters; Program processors; Standards",
}


bibtype: article
filename: fparith.bib
label: Hrycak:2020:ELP
author: Tomasz Hrycak and Sebastian Schmutzhard
title: Evaluation of Legendre polynomials by a three-term recurrence in floating-point arithmetic
journal: j-IMA-J-NUMER-ANAL
volume: 40
number: 1
pages: 587--605
month: jan
monthnumber: 1
year: 2020
CODEN: IJNADH
DOI: https://doi.org/10.1093/imanum/dry079
ISSN: 0272-4979 (print), 1464-3642 (electronic) OR 02724979 (print), 14643642 (electronic)
ISSNL: 0272-4979 OR 02724979
bibdate: Sat Feb 29 14:22:43 MST 2020
bibtimestamp: 2020.02.29 14:22:43 MST
URL: http://academic.oup.com/imajna/article/40/1/587/5162990
fjournal: IMA Journal of Numerical Analysis
acknowledgement: ack-nhfb
journalURL: http://imajna.oxfordjournals.org/content/by/year
rawauthor: Tomasz Hrycak and Sebastian Schmutzhard
rawtitle: Evaluation of {Legendre} polynomials by a three-term recurrence in floating-point arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/imajnumeranal.bib

entry:
@Article{Hrycak:2020:ELP,
  author =       "Tomasz Hrycak and Sebastian Schmutzhard",
  title =        "Evaluation of {Legendre} polynomials by a three-term
                 recurrence in floating-point arithmetic",
  journal =      j-IMA-J-NUMER-ANAL,
  volume =       "40",
  number =       "1",
  pages =        "587--605",
  month =        jan,
  year =         "2020",
  CODEN =        "IJNADH",
  DOI =          "https://doi.org/10.1093/imanum/dry079",
  ISSN =         "0272-4979 (print), 1464-3642 (electronic)",
  ISSN-L =       "0272-4979",
  bibdate =      "Sat Feb 29 14:22:43 MST 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/imajnumeranal.bib",
  URL =          "http://academic.oup.com/imajna/article/40/1/587/5162990",
  acknowledgement = ack-nhfb,
  fjournal =     "IMA Journal of Numerical Analysis",
  journal-URL =  "http://imajna.oxfordjournals.org/content/by/year",
}


bibtype: article
filename: fparith.bib
label: Ipsen:2020:PEA
author: Ilse C. F. Ipsen and Hua Zhou
title: Probabilistic Error Analysis for Inner Products
journal: j-SIAM-J-MAT-ANA-APPL
volume: 41
number: 4
pages: 1726--1741
year: 2020
CODEN: SJMAEL
DOI: https://doi.org/10.1137/19M1270434
ISSN: 0895-4798 (print), 1095-7162 (electronic) OR 08954798 (print), 10957162 (electronic)
ISSNL: 0895-4798 OR 08954798
bibdate: Fri Mar 12 10:18:05 MST 2021
bibtimestamp: 2021.03.12 10:18:05 MST
fjournal: SIAM Journal on Matrix Analysis and Applications
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/simax
onlinedate: January 2020
rawauthor: Ilse C. F. Ipsen and Hua Zhou
rawtitle: Probabilistic Error Analysis for Inner Products
bibsource:
http://epubs.siam.org/sam-bin/dbq/toc/SIMAX/41/4; https://www.math.utah.edu/pub/bibnet/authors/i/ipsen-ilse-c-f.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjmatanaappl.bib

entry:
@Article{Ipsen:2020:PEA,
  author =       "Ilse C. F. Ipsen and Hua Zhou",
  title =        "Probabilistic Error Analysis for Inner Products",
  journal =      j-SIAM-J-MAT-ANA-APPL,
  volume =       "41",
  number =       "4",
  pages =        "1726--1741",
  month =        "????",
  year =         "2020",
  CODEN =        "SJMAEL",
  DOI =          "https://doi.org/10.1137/19M1270434",
  ISSN =         "0895-4798 (print), 1095-7162 (electronic)",
  ISSN-L =       "0895-4798",
  bibdate =      "Fri Mar 12 10:18:05 MST 2021",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SIMAX/41/4;
                 https://www.math.utah.edu/pub/bibnet/authors/i/ipsen-ilse-c-f.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjmatanaappl.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Matrix Analysis and Applications",
  journal-URL =  "http://epubs.siam.org/simax",
  onlinedate =   "January 2020",
}


bibtype: book
filename: fparith.bib
label: ISO:2020:III
author: ISO
publisher: pub-ISO
address: pub-ISO:adr
pages: 74
year: 2020
bibdate: Thu Jan 28 07:09:28 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/isostd.bib
bibtimestamp: 2021.01.28 07:09:28 ???
URL: https://www.iso.org/standard/80985.html
remark: This is the international version of IEEE 754-2019. It replaces ISO/IEC/IEEE 60559:2011.
acknowledgement: ack-nhfb
rawauthor: {ISO}
title:
ISO / IEC 60559:2020 Information technology --- Microprocessor Systems --- Floating-Point arithmetic

rawtitle:
{ISO\slash IEC 60559:2020} Information technology --- Microprocessor Systems --- Floating-Point arithmetic

entry:
@Book{ISO:2020:III,
  author =       "{ISO}",
  title =        "{ISO\slash IEC 60559:2020} Information technology ---
                 Microprocessor Systems --- Floating-Point arithmetic",
  publisher =    pub-ISO,
  address =      pub-ISO:adr,
  pages =        "74",
  year =         "2020",
  bibdate =      "Thu Jan 28 07:09:28 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/isostd.bib",
  URL =          "https://www.iso.org/standard/80985.html",
  abstract =     "This standard specifies interchange and arithmetic
                 formats and methods for binary and decimal
                 floating-point arithmetic in computer programming
                 environments. This standard specifies exception
                 conditions and their default handling. An
                 implementation of a floating-point system conforming to
                 this standard may be realized entirely in software,
                 entirely in hardware, or in any combination of software
                 and hardware. For operations specified in the normative
                 part of this standard, numerical results and exceptions
                 are uniquely determined by the values of the input
                 data, sequence of operations, and destination formats,
                 all under user control.",
  acknowledgement = ack-nhfb,
  remark =       "This is the international version of IEEE 754-2019. It
                 replaces ISO/IEC/IEEE 60559:2011.",
}


bibtype: article
filename: fparith.bib
label: Isupov:2020:DIM
author: Konstantin Isupov and Vladimir Knyazkov and Alexander Kuvaev
journal: j-J-PAR-DIST-COMP
volume: 140
pages: 25--36
month: jun
monthnumber: 6
year: 2020
CODEN: JPDCER
DOI: https://doi.org/10.1016/j.jpdc.2020.02.006
ISSN: 0743-7315 (print), 1096-0848 (electronic) OR 07437315 (print), 10960848 (electronic)
ISSNL: 0743-7315 OR 07437315
bibdate: Wed May 26 16:11:01 MDT 2021
bibtimestamp: 2021.05.26 16:11:01 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0743731519303302
fjournal: Journal of Parallel and Distributed Computing
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07437315
rawauthor: Konstantin Isupov and Vladimir Knyazkov and Alexander Kuvaev
title:
Design and implementation of multiple-precision BLAS Level 1 functions for graphics processing units

rawtitle:
Design and implementation of multiple-precision {BLAS Level 1} functions for graphics processing units

entry:
@Article{Isupov:2020:DIM,
  author =       "Konstantin Isupov and Vladimir Knyazkov and Alexander
                 Kuvaev",
  title =        "Design and implementation of multiple-precision {BLAS
                 Level 1} functions for graphics processing units",
  journal =      j-J-PAR-DIST-COMP,
  volume =       "140",
  number =       "??",
  pages =        "25--36",
  month =        jun,
  year =         "2020",
  CODEN =        "JPDCER",
  DOI =          "https://doi.org/10.1016/j.jpdc.2020.02.006",
  ISSN =         "0743-7315 (print), 1096-0848 (electronic)",
  ISSN-L =       "0743-7315",
  bibdate =      "Wed May 26 16:11:01 MDT 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jpardistcomp.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0743731519303302",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Parallel and Distributed Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07437315",
}


bibtype: misc
filename: fparith.bib
label: Isupov:2020:MPB
author: Konstantin Isupov and Vladimir Knyazkov
title: Multiple-Precision BLAS Library for Graphics Processing Units
pages: 25--36
day: 30
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.36227/techrxiv.12580301.v1
bibdate: Fri Sep 29 14:30:54 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 14:30:54 ???
remark: Preprint submitted to Russian Supercomputing Days 2020.
acknowledgement: ack-nhfb
howpublished: TechRxiv preprint.
rawauthor: Konstantin Isupov and Vladimir Knyazkov
rawtitle: Multiple-Precision {BLAS} Library for Graphics Processing Units
abstract:
The binary32 and binary64 floating-point formats provide good performance on current hardware, but also introduce a rounding error in almost every arithmetic operation. Consequently, the accumulation of rounding errors in large computations can cause accuracy issues. One way to prevent these issues is to use multiple-precision floating-point arithmetic. This preprint, submitted to Russian Supercomputing Days 2020, presents a new library of basic linear algebra operations with multiple precision for graphics processing units. The library is written in CUDA C/C++ and uses the residue number system to represent multiple-precision significands of floating-point numbers. The supported data types, memory layout, and main features of the library are considered. Experimental results are presented showing the performance of the library.

rawabstract:
The binary32 and binary64 floating-point formats provide good performance on current hardware, but also introduce a rounding error in almost every arithmetic operation. Consequently, the accumulation of rounding errors in large computations can cause accuracy issues. One way to prevent these issues is to use multiple-precision floating-point arithmetic. This preprint, submitted to Russian Supercomputing Days 2020, presents a new library of basic linear algebra operations with multiple precision for graphics processing units. The library is written in CUDA C/C++ and uses the residue number system to represent multiple-precision significands of floating-point numbers. The supported data types, memory layout, and main features of the library are considered. Experimental results are presented showing the performance of the library.

entry:
@Misc{Isupov:2020:MPB,
  author =       "Konstantin Isupov and Vladimir Knyazkov",
  title =        "Multiple-Precision {BLAS} Library for Graphics
                 Processing Units",
  howpublished = "TechRxiv preprint.",
  day =          "30",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.36227/techrxiv.12580301.v1",
  bibdate =      "Fri Sep 29 14:30:54 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The binary32 and binary64 floating-point formats
                 provide good performance on current hardware, but also
                 introduce a rounding error in almost every arithmetic
                 operation. Consequently, the accumulation of rounding
                 errors in large computations can cause accuracy issues.
                 One way to prevent these issues is to use
                 multiple-precision floating-point arithmetic. This
                 preprint, submitted to Russian Supercomputing Days
                 2020, presents a new library of basic linear algebra
                 operations with multiple precision for graphics
                 processing units. The library is written in CUDA C/C++
                 and uses the residue number system to represent
                 multiple-precision significands of floating-point
                 numbers. The supported data types, memory layout, and
                 main features of the library are considered.
                 Experimental results are presented showing the
                 performance of the library.",
  acknowledgement = ack-nhfb,
  remark =       "Preprint submitted to Russian Supercomputing Days
                 2020.",
}


bibtype: article
filename: fparith.bib
label: Jeannerod:2020:RAX
author: Claude-Pierre Jeannerod
title: The relative accuracy of $ (x + y) * (x - y) $
journal: j-J-COMPUT-APPL-MATH
volume: 369
pages: Article 112613
day: 1
month: may
monthnumber: 5
year: 2020
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Wed May 13 06:58:31 MDT 2020
bibtimestamp: 2020.05.13 06:58:31 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0377042719306181
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Claude-Pierre Jeannerod
rawtitle: The relative accuracy of $ (x + y) * (x - y) $
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2020.bib

entry:
@Article{Jeannerod:2020:RAX,
  author =       "Claude-Pierre Jeannerod",
  title =        "The relative accuracy of $ (x + y) * (x - y) $",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "369",
  number =       "??",
  pages =        "Article 112613",
  day =          "1",
  month =        may,
  year =         "2020",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Wed May 13 06:58:31 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2020.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042719306181",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: article
filename: fparith.bib
label: Johnson:2020:EAHa
author: Jeff Johnson
title: Efficient, arbitrarily high precision hardware logarithmic arithmetic for linear algebra
journal: arxiv.org
pages: 1--8
day: 14
month: may
monthnumber: 5
year: 2020
bibdate: Tue Jul 06 18:17:13 2021
bibtimestamp: 2021.07.06 18:17:13 ???
URL: https://arxiv.org/pdf/2004.09313.pdf
remark: Published in cite Johnson:2020:EAHb.
acknowledgement: ack-nhfb
rawauthor: Jeff Johnson
rawtitle: Efficient, arbitrarily high precision hardware logarithmic arithmetic for linear algebra
abstract:
The logarithmic number system (LNS) is arguably not broadly used due to exponential circuit overheads for summation tables relative to arithmetic precision. Methods to reduce this overhead have been proposed, yet still yield designs with high chip area and power requirements. Use remains limited to lower precision or high multiply/add ratio cases, while much of linear algebra (near 1:1 multiply/add ratio) does not qualify.par We present a dual-base approximate logarithmic arithmetic comparable to floating point in use, yet unlike LNS it is easily fully pipelined, extendable to arbitrary precision with $ O(n^2) $ overhead, and energy efficient at a 1:1 multiply/add ratio.Compared to float32 or float64 vector inner product with FMA, our design is respectively $ 2.3 times $ and $ 4.6 times $ more energy efficient in 7 nm CMOS. It depends on exp and log evaluation $ 5.4 times $ and $ 3.2 times $ more energy efficient, at $ 0.23 times $ and $ 0.37 times $ the chip area for equivalent accuracy versus standard hyperbolic CORDIC using shift-and-add and approximated ODE integration in the style of Revol and Yakoubsohn. This technique is a novel alternative for low power, high precision hardened linear algebra in computer vision, graphics and machine learning applications.

keywords:
approximate arithmetic; elementary function evaluation; hardware linear algebra; logarithmic arithmetic

rawabstract:
The logarithmic number system (LNS) is arguably not broadly used due to exponential circuit overheads for summation tables relative to arithmetic precision. Methods to reduce this overhead have been proposed, yet still yield designs with high chip area and power requirements. Use remains limited to lower precision or high multiply/add ratio cases, while much of linear algebra (near 1:1 multiply/add ratio) does not qualify.\par We present a dual-base approximate logarithmic arithmetic comparable to floating point in use, yet unlike LNS it is easily fully pipelined, extendable to arbitrary precision with $ O(n^2) $ overhead, and energy efficient at a 1:1 multiply/add ratio.Compared to float32 or float64 vector inner product with FMA, our design is respectively $ 2.3 \times $ and $ 4.6 \times $ more energy efficient in 7 nm CMOS. It depends on exp and log evaluation $ 5.4 \times $ and $ 3.2 \times $ more energy efficient, at $ 0.23 \times $ and $ 0.37 \times $ the chip area for equivalent accuracy versus standard hyperbolic CORDIC using shift-and-add and approximated ODE integration in the style of Revol and Yakoubsohn. This technique is a novel alternative for low power, high precision hardened linear algebra in computer vision, graphics and machine learning applications.

entry:
@Article{Johnson:2020:EAHa,
  author =       "Jeff Johnson",
  title =        "Efficient, arbitrarily high precision hardware
                 logarithmic arithmetic for linear algebra",
  journal =      "arxiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--8",
  day =          "14",
  month =        may,
  year =         "2020",
  bibdate =      "Tue Jul 06 18:17:13 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/pdf/2004.09313.pdf",
  abstract =     "The logarithmic number system (LNS) is arguably not
                 broadly used due to exponential circuit overheads for
                 summation tables relative to arithmetic precision.
                 Methods to reduce this overhead have been proposed, yet
                 still yield designs with high chip area and power
                 requirements. Use remains limited to lower precision or
                 high multiply/add ratio cases, while much of linear
                 algebra (near 1:1 multiply/add ratio) does not
                 qualify.\par

                 We present a dual-base approximate logarithmic
                 arithmetic comparable to floating point in use, yet
                 unlike LNS it is easily fully pipelined, extendable to
                 arbitrary precision with $ O(n^2) $ overhead, and
                 energy efficient at a 1:1 multiply/add ratio.Compared
                 to float32 or float64 vector inner product with FMA,
                 our design is respectively $ 2.3 \times $ and $ 4.6
                 \times $ more energy efficient in 7 nm CMOS. It depends
                 on exp and log evaluation $ 5.4 \times $ and $ 3.2
                 \times $ more energy efficient, at $ 0.23 \times $ and
                 $ 0.37 \times $ the chip area for equivalent accuracy
                 versus standard hyperbolic CORDIC using shift-and-add
                 and approximated ODE integration in the style of Revol
                 and Yakoubsohn. This technique is a novel alternative
                 for low power, high precision hardened linear algebra
                 in computer vision, graphics and machine learning
                 applications.",
  acknowledgement = ack-nhfb,
  keywords =     "approximate arithmetic; elementary function
                 evaluation; hardware linear algebra; logarithmic
                 arithmetic",
  remark =       "Published in \cite{Johnson:2020:EAHb}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Johnson:2020:EAHb
author: Jeff Johnson
title: Efficient, arbitrarily high precision hardware logarithmic arithmetic for linear algebra
crossref: Cornea:2020:ISC
pages: 25--32
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00013
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Jeff Johnson
rawtitle: Efficient, arbitrarily high precision hardware logarithmic arithmetic for linear algebra
abstract:
The logarithmic number system (LNS) is arguably not broadly used due to exponential circuit overheads for summation tables relative to arithmetic precision. Methods to reduce this overhead have been proposed, yet still yield designs with high chip area and power requirements. Use remains limited to lower precision or high multiply/add ratio cases, while much of linear algebra (near 1:1 multiply/add ratio) does not qualify. We present a dual-base approximate logarithmic arithmetic comparable to floating point in use, yet unlike LNS it is easily fully pipelined, extendable to arbitrary precision with $ O(n^2) $ overhead, and energy efficient at a 1:1 multiply/add ratio. Compared to float32 or float64 vector inner product with FMA, our design is respectively $ 2.3 times $ and $ 4.6 times $ more energy efficient in 7 nm CMOS. It depends on exp and log evaluation 5.4 and $ 3.2 times $ more energy efficient, at $ 0.23 times $ and $ 0.37 times $ the chip area for equivalent accuracy versus standard hyperbolic CORDIC using shift-and-add and approximated ODE integration in the style of Revol and Yakoubsohn. This technique is a novel alternative for low power, high precision hardened linear algebra in computer vision, graphics and machine learning applications.

keywords:
Adders; approximate arithmetic; Clocks; elementary function evaluation; Hardware; hardware linear algebra; Linear algebra; logarithmic arithmetic; Pipeline processing; Read only memory; Switches

rawabstract:
The logarithmic number system (LNS) is arguably not broadly used due to exponential circuit overheads for summation tables relative to arithmetic precision. Methods to reduce this overhead have been proposed, yet still yield designs with high chip area and power requirements. Use remains limited to lower precision or high multiply/add ratio cases, while much of linear algebra (near 1:1 multiply/add ratio) does not qualify. We present a dual-base approximate logarithmic arithmetic comparable to floating point in use, yet unlike LNS it is easily fully pipelined, extendable to arbitrary precision with $ O(n^2) $ overhead, and energy efficient at a 1:1 multiply/add ratio. Compared to float32 or float64 vector inner product with FMA, our design is respectively $ 2.3 \times $ and $ 4.6 \times $ more energy efficient in 7 nm CMOS. It depends on exp and log evaluation 5.4 and $ 3.2 \times $ more energy efficient, at $ 0.23 \times $ and $ 0.37 \times $ the chip area for equivalent accuracy versus standard hyperbolic CORDIC using shift-and-add and approximated ODE integration in the style of Revol and Yakoubsohn. This technique is a novel alternative for low power, high precision hardened linear algebra in computer vision, graphics and machine learning applications.

entry:
@InProceedings{Johnson:2020:EAHb,
  author =       "Jeff Johnson",
  title =        "Efficient, arbitrarily high precision hardware
                 logarithmic arithmetic for linear algebra",
  crossref =     "Cornea:2020:ISC",
  pages =        "25--32",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00013",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The logarithmic number system (LNS) is arguably not
                 broadly used due to exponential circuit overheads for
                 summation tables relative to arithmetic precision.
                 Methods to reduce this overhead have been proposed, yet
                 still yield designs with high chip area and power
                 requirements. Use remains limited to lower precision or
                 high multiply/add ratio cases, while much of linear
                 algebra (near 1:1 multiply/add ratio) does not qualify.
                 We present a dual-base approximate logarithmic
                 arithmetic comparable to floating point in use, yet
                 unlike LNS it is easily fully pipelined, extendable to
                 arbitrary precision with $ O(n^2) $ overhead, and
                 energy efficient at a 1:1 multiply/add ratio. Compared
                 to float32 or float64 vector inner product with FMA,
                 our design is respectively $ 2.3 \times $ and $ 4.6
                 \times $ more energy efficient in 7 nm CMOS. It depends
                 on exp and log evaluation 5.4 and $ 3.2 \times $ more
                 energy efficient, at $ 0.23 \times $ and $ 0.37 \times
                 $ the chip area for equivalent accuracy versus standard
                 hyperbolic CORDIC using shift-and-add and approximated
                 ODE integration in the style of Revol and Yakoubsohn.
                 This technique is a novel alternative for low power,
                 high precision hardened linear algebra in computer
                 vision, graphics and machine learning applications.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; approximate arithmetic; Clocks; elementary
                 function evaluation; Hardware; hardware linear algebra;
                 Linear algebra; logarithmic arithmetic; Pipeline
                 processing; Read only memory; Switches",
}


bibtype: inproceedings
filename: fparith.bib
label: Joldes:2020:AMQ
author: Mioara Joldes and Jean-Michel Muller
title: Algorithms for Manipulating Quaternions in Floating-Point Arithmetic
crossref: Cornea:2020:ISC
pages: 48--55
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00016
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Mioara Jolde{\c{s}} and Jean-Michel Muller
rawtitle: Algorithms for Manipulating Quaternions in Floating-Point Arithmetic
abstract:
Quaternions form a set of four global but not unique parameters, which can represent three-dimensional rotations in a non-singular way. They are frequently used in computer graphics, drone and aerospace vehicle control. Floating-point quaternion operations (addition, multiplication, reciprocal, norm) are often implemented by the book . Although all usual implementations are algebraically equivalent, their numerical behavior can be quite different. For instance, the arithmetic operations on quaternions as well as conversion algorithms to/from rotation matrices are subject to spurious under/overflow (an intermediate calculation underflows or overflows, making the computed final result irrelevant, although the exact result is in the domain of the representable numbers). The goal of this paper is to analyze and then propose workarounds and better accuracy alternatives for such algorithms.

keywords:
Aerospace control; Algebra; Computer graphics; Drones; Error analysis; Floating-point arithmetic; Quaternions; quaternions; rounding error analysis; Standards

rawabstract:
Quaternions form a set of four global but not unique parameters, which can represent three-dimensional rotations in a non-singular way. They are frequently used in computer graphics, drone and aerospace vehicle control. Floating-point quaternion operations (addition, multiplication, reciprocal, norm) are often implemented by the book . Although all usual implementations are algebraically equivalent, their numerical behavior can be quite different. For instance, the arithmetic operations on quaternions as well as conversion algorithms to/from rotation matrices are subject to spurious under/overflow (an intermediate calculation underflows or overflows, making the computed final result irrelevant, although the exact result is in the domain of the representable numbers). The goal of this paper is to analyze and then propose workarounds and better accuracy alternatives for such algorithms.

entry:
@InProceedings{Joldes:2020:AMQ,
  author =       "Mioara Jolde{\c{s}} and Jean-Michel Muller",
  title =        "Algorithms for Manipulating Quaternions in
                 Floating-Point Arithmetic",
  crossref =     "Cornea:2020:ISC",
  pages =        "48--55",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00016",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Quaternions form a set of four global but not unique
                 parameters, which can represent three-dimensional
                 rotations in a non-singular way. They are frequently
                 used in computer graphics, drone and aerospace vehicle
                 control. Floating-point quaternion operations
                 (addition, multiplication, reciprocal, norm) are often
                 implemented by the book . Although all usual
                 implementations are algebraically equivalent, their
                 numerical behavior can be quite different. For
                 instance, the arithmetic operations on quaternions as
                 well as conversion algorithms to/from rotation matrices
                 are subject to spurious under/overflow (an intermediate
                 calculation underflows or overflows, making the
                 computed final result irrelevant, although the exact
                 result is in the domain of the representable numbers).
                 The goal of this paper is to analyze and then propose
                 workarounds and better accuracy alternatives for such
                 algorithms.",
  acknowledgement = ack-nhfb,
  keywords =     "Aerospace control; Algebra; Computer graphics; Drones;
                 Error analysis; Floating-point arithmetic; Quaternions;
                 quaternions; rounding error analysis; Standards",
}


bibtype: inproceedings
filename: fparith.bib
label: Jugade:2020:FEM
author: Chaitanya Jugade and Deepak Ingole and Dayaram Sonawane and Michal Kvasnica and John Gustafson
editor: IEEE
booktitle: 2020 59th IEEE Conference on Decision and Control (CDC)
title: A Framework for Embedded Model Predictive Control using Posits
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 2509--2514
year: 2020
DOI: https://doi.org/10.1109/CDC42340.2020.9304262
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Chaitanya Jugade and Deepak Ingole and Dayaram Sonawane and Michal Kvasnica and John Gustafson
rawbooktitle: {2020 59th IEEE Conference on Decision and Control (CDC)}
raweditor: {IEEE}
rawtitle: A Framework for Embedded Model Predictive Control using Posits
entry:
@InProceedings{Jugade:2020:FEM,
  author =       "Chaitanya Jugade and Deepak Ingole and Dayaram
                 Sonawane and Michal Kvasnica and John Gustafson",
  editor =       "{IEEE}",
  booktitle =    "{2020 59th IEEE Conference on Decision and Control
                 (CDC)}",
  title =        "A Framework for Embedded Model Predictive Control
                 using Posits",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2509--2514",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/CDC42340.2020.9304262",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Klarreich:2020:NMH
author: Erica Klarreich
title: News: Multiplication hits the speed limit
journal: j-CACM
volume: 63
number: 1
pages: 11--13
month: jan
monthnumber: 1
year: 2020
CODEN: CACMA2
DOI: https://doi.org/10.1145/3371387
ISSN: 0001-0782 (print), 1557-7317 (electronic) OR 00010782 (print), 15577317 (electronic)
ISSNL: 0001-0782 OR 00010782
bibdate: Thu Jan 2 16:41:05 MST 2020
bibtimestamp: 2020.01.02 16:41:05 MST
URL: https://dl.acm.org/doi/abs/10.1145/3371387
abstract: A problem ``around since antiquity'' may have been resolved by a new algorithm.
fjournal: Communications of the ACM
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/cacm
rawabstract: A problem ``around since antiquity'' may have been resolved by a new algorithm.
rawauthor: Erica Klarreich
rawtitle: News: Multiplication hits the speed limit
bibsource:
https://www.math.utah.edu/pub/tex/bib/cacm2020.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Klarreich:2020:NMH,
  author =       "Erica Klarreich",
  title =        "News: Multiplication hits the speed limit",
  journal =      j-CACM,
  volume =       "63",
  number =       "1",
  pages =        "11--13",
  month =        jan,
  year =         "2020",
  CODEN =        "CACMA2",
  DOI =          "https://doi.org/10.1145/3371387",
  ISSN =         "0001-0782 (print), 1557-7317 (electronic)",
  ISSN-L =       "0001-0782",
  bibdate =      "Thu Jan 2 16:41:05 MST 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cacm2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3371387",
  abstract =     "A problem ``around since antiquity'' may have been
                 resolved by a new algorithm.",
  acknowledgement = ack-nhfb,
  fjournal =     "Communications of the ACM",
  journal-URL =  "https://dl.acm.org/loi/cacm",
}


bibtype: article
filename: fparith.bib
label: Klower:2020:NFE
author: Milan Klower and Peter D. Duben and Tim N. Palmer
journal: j-J-ADV-MODEL-EARTH-SYST
volume: 12
number: 10
pages: 1--17
month: oct
monthnumber: 10
year: 2020
DOI: https://doi.org/10.1029/2020MS002246
ISSN: 1942-2466 (print), 1942-2466 (electronic) OR 19422466 (print), 19422466 (electronic)
ISSNL: 1942-2466 OR 19422466
bibdate: Fri Dec 15 11:03:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 11:03:12 ???
fjournal: Journal of Advances in Modeling Earth Systems
acknowledgement: ack-nhfb
ajournal: J. Adv. Model. Earth Syst. [JAMES]
journalURL: https://agupubs.onlinelibrary.wiley.com/journal/19422466
rawauthor: Milan Kl{\"o}wer and Peter D. D{\"u}ben and Tim N. Palmer
title:
Number Formats, Error Mitigation, and Scope for 16-Bit Arithmetics in Weather and Climate Modeling Analyzed With a Shallow Water Model

rawtitle:
Number Formats, Error Mitigation, and Scope for 16-Bit Arithmetics in Weather and Climate Modeling Analyzed With a Shallow Water Model

entry:
@Article{Klower:2020:NFE,
  author =       "Milan Kl{\"o}wer and Peter D. D{\"u}ben and Tim N.
                 Palmer",
  title =        "Number Formats, Error Mitigation, and Scope for 16-Bit
                 Arithmetics in Weather and Climate Modeling Analyzed
                 With a Shallow Water Model",
  journal =      j-J-ADV-MODEL-EARTH-SYST,
  volume =       "12",
  number =       "10",
  pages =        "1--17",
  month =        oct,
  year =         "2020",
  DOI =          "https://doi.org/10.1029/2020MS002246",
  ISSN =         "1942-2466 (print), 1942-2466 (electronic)",
  ISSN-L =       "1942-2466",
  bibdate =      "Fri Dec 15 11:03:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Adv. Model. Earth Syst. [JAMES]",
  fjournal =     "Journal of Advances in Modeling Earth Systems",
  journal-URL =  "https://agupubs.onlinelibrary.wiley.com/journal/19422466",
}


bibtype: inproceedings
filename: fparith.bib
label: Knobbe:2020:CRS
author: Simon Knobbe and Moritz Barthel and Steffen Paul and Jochen Rust
booktitle: 2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST)
title: Complexity Reduction for Sphere Decoding using Unum-Type-II-Based SORN-Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--4
year: 2020
DOI: https://doi.org/10.1109/MOCAST49295.2020.9200263
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawauthor: Simon Knobbe and Moritz B{\"a}rthel and Steffen Paul and Jochen Rust
rawbooktitle: {2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST)}
rawtitle: Complexity Reduction for Sphere Decoding using {Unum-Type-II}-Based {SORN}-Arithmetic
entry:
@InProceedings{Knobbe:2020:CRS,
  author =       "Simon Knobbe and Moritz B{\"a}rthel and Steffen Paul
                 and Jochen Rust",
  booktitle =    "{2020 9th International Conference on Modern Circuits
                 and Systems Technologies (MOCAST)}",
  title =        "Complexity Reduction for Sphere Decoding using
                 {Unum-Type-II}-Based {SORN}-Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/MOCAST49295.2020.9200263",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Koc:2020:AIM
author: Cetin Kaya Koc
title: Algorithms for Inversion Mod $ p^k $
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 6
pages: 907--913
year: 2020
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2020.2970411
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 23 16:03:24 2020
bibtimestamp: 2020.07.23 16:03:24 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: {\c{C}}etin Kaya Ko{\c{c}}
rawtitle: Algorithms for Inversion Mod $ p^k $
abstract:
This article describes and analyzes all existing algorithms for computing $ x = a^-1 (bmod p^k) $ for a prime $p$, and also introduces a new algorithm based on the exact solution of linear equations using $p$-adic expansions. The algorithm starts with the initial value $ c = a^-1 (bmod p)$ and iteratively computes the digits of the inverse $ x = a^-1 (bmod p^k)$ in base $p$. The $ bmod 2$ version of the algorithm is more efficient than all existing algorithms for small values of $k$. Moreover, it stands out as being the only one that works for any $p$, any $k$, and digit-by-digit. While the new algorithm is asymptotically worse off, it requires the minimal number of arithmetic operations (just a single addition) per step, as compared to all existing algorithms.

rawabstract:
This article describes and analyzes all existing algorithms for computing $ x = a^{-1} (\bmod p^k) $ for a prime $p$, and also introduces a new algorithm based on the exact solution of linear equations using $p$-adic expansions. The algorithm starts with the initial value $ c = a^{-1} (\bmod p)$ and iteratively computes the digits of the inverse $ x = a^{-1} (\bmod p^k)$ in base $p$. The $ \bmod 2$ version of the algorithm is more efficient than all existing algorithms for small values of $k$. Moreover, it stands out as being the only one that works for any $p$, any $k$, and digit-by-digit. While the new algorithm is asymptotically worse off, it requires the minimal number of arithmetic operations (just a single addition) per step, as compared to all existing algorithms.

entry:
@Article{Koc:2020:AIM,
  author =       "{\c{C}}etin Kaya Ko{\c{c}}",
  title =        "Algorithms for Inversion Mod $ p^k $",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "6",
  pages =        "907--913",
  year =         "2020",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2020.2970411",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 23 16:03:24 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  abstract =     "This article describes and analyzes all existing
                 algorithms for computing $ x = a^{-1} (\bmod p^k) $ for
                 a prime $p$, and also introduces a new algorithm based
                 on the exact solution of linear equations using
                 $p$-adic expansions. The algorithm starts with the
                 initial value $ c = a^{-1} (\bmod p)$ and iteratively
                 computes the digits of the inverse $ x = a^{-1} (\bmod
                 p^k)$ in base $p$. The $ \bmod 2$ version of the
                 algorithm is more efficient than all existing
                 algorithms for small values of $k$. Moreover, it stands
                 out as being the only one that works for any $p$, any
                 $k$, and digit-by-digit. While the new algorithm is
                 asymptotically worse off, it requires the minimal
                 number of arithmetic operations (just a single
                 addition) per step, as compared to all existing
                 algorithms.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Lange:2020:FRF
author: Marko Lange and Siegfried M. Rump
title: Faithfully Rounded Floating-point Computations
journal: j-TOMS
volume: 46
number: 3
pages: 21:1--21:20
month: sep
monthnumber: 9
year: 2020
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3290955
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Sat Sep 26 07:28:19 MDT 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2020.09.26 07:28:19 MDT
URL: https://dl.acm.org/doi/10.1145/3290955
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 21
journalURL: https://dl.acm.org/loi/toms
rawauthor: Marko Lange and Siegfried M. Rump
rawtitle: Faithfully Rounded Floating-point Computations
abstract:
We present a pair arithmetic for the four basic operations and square root. It can be regarded as a simplified, more-efficient double-double arithmetic. The central assumption on the underlying arithmetic is the first standard model for error analysis for operations on a discrete set of real numbers. Neither do we require a floating-point grid nor a rounding to nearest property. Based on that, we define a relative rounding error unit $u$ and prove rigorous error bounds for the computed result of an arbitrary arithmetic expression depending on $u$, the size of the expression, and possibly a condition measure. In the second part of this note, we extend the error analysis by examining requirements to ensure faithfully rounded outputs and apply our results to IEEE 754 standard conform floating-point systems. For a class of mathematical expressions, using an IEEE 754 standard conform arithmetic with base $ beta $, the result is proved to be faithfully rounded for up to $ 1 / sqrt beta u - 2$ operations. Our findings cover a number of previously published algorithms to compute faithfully rounded results, among them Horner's scheme, products, sums, dot products, or Euclidean norm. Beyond that, several other problems can be analyzed, such as polynomial interpolation, orientation problems, Householder transformations, or the smallest singular value of Hilbert matrices of large size.

rawabstract:
We present a pair arithmetic for the four basic operations and square root. It can be regarded as a simplified, more-efficient double-double arithmetic. The central assumption on the underlying arithmetic is the first standard model for error analysis for operations on a discrete set of real numbers. Neither do we require a floating-point grid nor a rounding to nearest property. Based on that, we define a relative rounding error unit $u$ and prove rigorous error bounds for the computed result of an arbitrary arithmetic expression depending on $u$, the size of the expression, and possibly a condition measure. In the second part of this note, we extend the error analysis by examining requirements to ensure faithfully rounded outputs and apply our results to IEEE 754 standard conform floating-point systems. For a class of mathematical expressions, using an IEEE 754 standard conform arithmetic with base $ \beta $, the result is proved to be faithfully rounded for up to $ 1 / \sqrt {\beta u - 2}$ operations. Our findings cover a number of previously published algorithms to compute faithfully rounded results, among them Horner's scheme, products, sums, dot products, or Euclidean norm. Beyond that, several other problems can be analyzed, such as polynomial interpolation, orientation problems, Householder transformations, or the smallest singular value of Hilbert matrices of large size.

entry:
@Article{Lange:2020:FRF,
  author =       "Marko Lange and Siegfried M. Rump",
  title =        "Faithfully Rounded Floating-point Computations",
  journal =      j-TOMS,
  volume =       "46",
  number =       "3",
  pages =        "21:1--21:20",
  month =        sep,
  year =         "2020",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3290955",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Sat Sep 26 07:28:19 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3290955",
  abstract =     "We present a pair arithmetic for the four basic
                 operations and square root. It can be regarded as a
                 simplified, more-efficient double-double arithmetic.
                 The central assumption on the underlying arithmetic is
                 the first standard model for error analysis for
                 operations on a discrete set of real numbers. Neither
                 do we require a floating-point grid nor a rounding to
                 nearest property. Based on that, we define a relative
                 rounding error unit $u$ and prove rigorous error bounds
                 for the computed result of an arbitrary arithmetic
                 expression depending on $u$, the size of the
                 expression, and possibly a condition measure. In the
                 second part of this note, we extend the error analysis
                 by examining requirements to ensure faithfully rounded
                 outputs and apply our results to IEEE 754 standard
                 conform floating-point systems. For a class of
                 mathematical expressions, using an IEEE 754 standard
                 conform arithmetic with base $ \beta $, the result is
                 proved to be faithfully rounded for up to $ 1 / \sqrt
                 {\beta u - 2}$ operations. Our findings cover a number
                 of previously published algorithms to compute
                 faithfully rounded results, among them Horner's scheme,
                 products, sums, dot products, or Euclidean norm. Beyond
                 that, several other problems can be analyzed, such as
                 polynomial interpolation, orientation problems,
                 Householder transformations, or the smallest singular
                 value of Hilbert matrices of large size.",
  acknowledgement = ack-nhfb,
  articleno =    "21",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Lange:2020:NDF
author: Marko Lange and Shin'ichi Oishi
title: A note on Dekker's FastTwoSum algorithm
journal: j-NUM-MATH
volume: 145
number: 2
pages: 383--403
month: jun
monthnumber: 6
year: 2020
CODEN: NUMMA7
DOI: https://doi.org/10.1007/s00211-020-01114-2
ISSN: 0029-599X (print), 0945-3245 (electronic) OR 0029599X (print), 09453245 (electronic)
ISSNL: 0029-599X OR 0029599X
bibdate: Thu Jun 4 12:18:54 MDT 2020
bibtimestamp: 2020.06.04 12:18:54 MDT
note: See correction cite Lange:2021:CND.
URL: https://link.springer.com/article/10.1007/s00211-020-01114-2
fjournal: Numerische Mathematik
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/211
rawauthor: Marko Lange and Shin'ichi Oishi
rawnote: See correction \cite{Lange:2021:CND}.
rawtitle: A note on {Dekker}'s {FastTwoSum} algorithm
bibsource:
http://link.springer.com/journal/211/145/2; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/nummath2020.bib

entry:
@Article{Lange:2020:NDF,
  author =       "Marko Lange and Shin'ichi Oishi",
  title =        "A note on {Dekker}'s {FastTwoSum} algorithm",
  journal =      j-NUM-MATH,
  volume =       "145",
  number =       "2",
  pages =        "383--403",
  month =        jun,
  year =         "2020",
  CODEN =        "NUMMA7",
  DOI =          "https://doi.org/10.1007/s00211-020-01114-2",
  ISSN =         "0029-599X (print), 0945-3245 (electronic)",
  ISSN-L =       "0029-599X",
  bibdate =      "Thu Jun 4 12:18:54 MDT 2020",
  bibsource =    "http://link.springer.com/journal/211/145/2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/nummath2020.bib",
  note =         "See correction \cite{Lange:2021:CND}.",
  URL =          "https://link.springer.com/article/10.1007/s00211-020-01114-2",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerische Mathematik",
  journal-URL =  "http://link.springer.com/journal/211",
}


bibtype: inproceedings
filename: fparith.bib
label: Langroudi:2020:APP
author: Hamed F. Langroudi and Vedant Karia and John L. Gustafson and Dhireesha Kudithipudi
editor: IEEE
booktitle: 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW)
title: Adaptive Posit: Parameter aware numerical format for deep learning inference on the edge
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 3123--3131
year: 2020
DOI: https://doi.org/10.1109/CVPRW50498.2020.00371
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Hamed F. Langroudi and Vedant Karia and John L. Gustafson and Dhireesha Kudithipudi
rawbooktitle: {2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW)}
raweditor: {IEEE}
rawtitle: Adaptive Posit: Parameter aware numerical format for deep learning inference on the edge
entry:
@InProceedings{Langroudi:2020:APP,
  author =       "Hamed F. Langroudi and Vedant Karia and John L.
                 Gustafson and Dhireesha Kudithipudi",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE/CVF Conference on Computer Vision and
                 Pattern Recognition Workshops (CVPRW)}",
  title =        "Adaptive Posit: Parameter aware numerical format for
                 deep learning inference on the edge",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "3123--3131",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/CVPRW50498.2020.00371",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lauter:2020:FSA
author: Christoph Lauter and Anastasia Volkova
title: A Framework for Semi-Automatic Precision and Accuracy Analysis for Fast and Rigorous Deep Learning
crossref: Cornea:2020:ISC
pages: 103--110
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00023
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Christoph Lauter and Anastasia Volkova
rawtitle: A Framework for Semi-Automatic Precision and Accuracy Analysis for Fast and Rigorous Deep Learning
abstract:
Deep Neural Networks (DNN) represent a performance-hungry application. Floating-Point (FP) and custom floating-point-like arithmetic satisfies this hunger. While there is need for speed, inference in DNNs does not seem to have any need for precision. Many papers experimentally observe that DNNs can successfully run at almost ridiculously low precision. The aim of this paper is two-fold: first, to shed some theoretical light upon why a DNN's FP accuracy stays high for low FP precision. We observe that the loss of relative accuracy in the convolutional steps is recovered by the activation layers, which are extremely well-conditioned. We give an interpretation for the link between precision and accuracy in DNNs. Second, the paper presents a software framework for semi-automatic FP error analysis for the inference phase of deep-learning. Compatible with common Tensorflow/Keras models, it leverages the frugally-deep Python/C++ library to transform a neural network into C++ code in order to analyze the network's need for precision. This rigorous analysis is based an Interval and Affine arithmetics to compute absolute and relative error bounds for a DNN. We demonstrate our tool with several examples.

keywords:
affine arithmetic; Analytical models; Biological neural networks; Computational modeling; deep learning; Digital arithmetic; error analysis; floating-point arithmetic; interval arithmetic; Machine learning; Neurons; Tools

rawabstract:
Deep Neural Networks (DNN) represent a performance-hungry application. Floating-Point (FP) and custom floating-point-like arithmetic satisfies this hunger. While there is need for speed, inference in DNNs does not seem to have any need for precision. Many papers experimentally observe that DNNs can successfully run at almost ridiculously low precision. The aim of this paper is two-fold: first, to shed some theoretical light upon why a DNN's FP accuracy stays high for low FP precision. We observe that the loss of relative accuracy in the convolutional steps is recovered by the activation layers, which are extremely well-conditioned. We give an interpretation for the link between precision and accuracy in DNNs. Second, the paper presents a software framework for semi-automatic FP error analysis for the inference phase of deep-learning. Compatible with common Tensorflow/Keras models, it leverages the frugally-deep Python/C++ library to transform a neural network into C++ code in order to analyze the network's need for precision. This rigorous analysis is based an Interval and Affine arithmetics to compute absolute and relative error bounds for a DNN. We demonstrate our tool with several examples.

entry:
@InProceedings{Lauter:2020:FSA,
  author =       "Christoph Lauter and Anastasia Volkova",
  title =        "A Framework for Semi-Automatic Precision and Accuracy
                 Analysis for Fast and Rigorous Deep Learning",
  crossref =     "Cornea:2020:ISC",
  pages =        "103--110",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00023",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Deep Neural Networks (DNN) represent a
                 performance-hungry application. Floating-Point (FP) and
                 custom floating-point-like arithmetic satisfies this
                 hunger. While there is need for speed, inference in
                 DNNs does not seem to have any need for precision. Many
                 papers experimentally observe that DNNs can
                 successfully run at almost ridiculously low precision.
                 The aim of this paper is two-fold: first, to shed some
                 theoretical light upon why a DNN's FP accuracy stays
                 high for low FP precision. We observe that the loss of
                 relative accuracy in the convolutional steps is
                 recovered by the activation layers, which are extremely
                 well-conditioned. We give an interpretation for the
                 link between precision and accuracy in DNNs. Second,
                 the paper presents a software framework for
                 semi-automatic FP error analysis for the inference
                 phase of deep-learning. Compatible with common
                 Tensorflow/Keras models, it leverages the frugally-deep
                 Python/C++ library to transform a neural network into
                 C++ code in order to analyze the network's need for
                 precision. This rigorous analysis is based an Interval
                 and Affine arithmetics to compute absolute and relative
                 error bounds for a DNN. We demonstrate our tool with
                 several examples.",
  acknowledgement = ack-nhfb,
  keywords =     "affine arithmetic; Analytical models; Biological
                 neural networks; Computational modeling; deep learning;
                 Digital arithmetic; error analysis; floating-point
                 arithmetic; interval arithmetic; Machine learning;
                 Neurons; Tools",
}


bibtype: inproceedings
filename: fparith.bib
label: Lindstrom:2020:VRC
author: Peter Lindstrom
title: Variable-Radix Coding of the Reals
crossref: Cornea:2020:ISC
pages: 111--116
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00024
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Peter Lindstrom
rawtitle: Variable-Radix Coding of the Reals
abstract:
Recently proposed real number systems like Posits and Elias codes make use of tapered accuracy resulting from variable-length coding of exponents and significands. Several quite different interpretations of these number systems have been provided, though most often these rely on some combination of fixed- and variable-length codes for exponent and significand. We provide a new perspective on these number systems that unifies known representations while suggesting new ones. Our framework is based on multibit radix representations that encode the exponent in unary, the leading nonzero digit in a variable-length code, and the remaining digits in fixed-length binary code. We show how Posits, the various Elias codes, and IEEE 754 like representations can be expressed in this framework. Moreover, we show that Posits and the Elias and codes represent the leading digit using the canonical Huffman code for a probability distribution given by Benford's law, which governs the probability of leading digits. We further show that Posits correspond to the use of a fixed radix while Elias and codes are based on simple sequences of increasing radix. Our approach provides for an intuitive and uniform framework for representing numbers that reveals a visual mapping between codewords and the binary representation of real numbers obscured by prior frameworks. This new interpretation suggests a generalization of Posits and other number systems and provides simple rules for designing information-theoretically optimal codes.

keywords:
Benford's law; Binary codes; Digital arithmetic; Elias codes; Encoding; floating point; Huffman code; Indexes; posits; Probability distribution; Proposals; real number systems; tapered accuracy; Visualization

rawabstract:
Recently proposed real number systems like Posits and Elias codes make use of tapered accuracy resulting from variable-length coding of exponents and significands. Several quite different interpretations of these number systems have been provided, though most often these rely on some combination of fixed- and variable-length codes for exponent and significand. We provide a new perspective on these number systems that unifies known representations while suggesting new ones. Our framework is based on multibit radix representations that encode the exponent in unary, the leading nonzero digit in a variable-length code, and the remaining digits in fixed-length binary code. We show how Posits, the various Elias codes, and IEEE 754 like representations can be expressed in this framework. Moreover, we show that Posits and the Elias and codes represent the leading digit using the canonical Huffman code for a probability distribution given by Benford's law, which governs the probability of leading digits. We further show that Posits correspond to the use of a fixed radix while Elias and codes are based on simple sequences of increasing radix. Our approach provides for an intuitive and uniform framework for representing numbers that reveals a visual mapping between codewords and the binary representation of real numbers obscured by prior frameworks. This new interpretation suggests a generalization of Posits and other number systems and provides simple rules for designing information-theoretically optimal codes.

entry:
@InProceedings{Lindstrom:2020:VRC,
  author =       "Peter Lindstrom",
  title =        "Variable-Radix Coding of the Reals",
  crossref =     "Cornea:2020:ISC",
  pages =        "111--116",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00024",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/benfords-law.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Recently proposed real number systems like Posits and
                 Elias codes make use of tapered accuracy resulting from
                 variable-length coding of exponents and significands.
                 Several quite different interpretations of these number
                 systems have been provided, though most often these
                 rely on some combination of fixed- and variable-length
                 codes for exponent and significand. We provide a new
                 perspective on these number systems that unifies known
                 representations while suggesting new ones. Our
                 framework is based on multibit radix representations
                 that encode the exponent in unary, the leading nonzero
                 digit in a variable-length code, and the remaining
                 digits in fixed-length binary code. We show how Posits,
                 the various Elias codes, and IEEE 754 like
                 representations can be expressed in this framework.
                 Moreover, we show that Posits and the Elias and codes
                 represent the leading digit using the canonical Huffman
                 code for a probability distribution given by Benford's
                 law, which governs the probability of leading digits.
                 We further show that Posits correspond to the use of a
                 fixed radix while Elias and codes are based on simple
                 sequences of increasing radix. Our approach provides
                 for an intuitive and uniform framework for representing
                 numbers that reveals a visual mapping between codewords
                 and the binary representation of real numbers obscured
                 by prior frameworks. This new interpretation suggests a
                 generalization of Posits and other number systems and
                 provides simple rules for designing
                 information-theoretically optimal codes.",
  acknowledgement = ack-nhfb,
  keywords =     "Benford's law; Binary codes; Digital arithmetic; Elias
                 codes; Encoding; floating point; Huffman code; Indexes;
                 posits; Probability distribution; Proposals; real
                 number systems; tapered accuracy; Visualization",
}


bibtype: article
filename: fparith.bib
label: Luo:2020:ADN
author: Y. Luo and S. Yu
journal: j-IEEE-TRANS-COMPUT
volume: 69
number: 8
pages: 1113--1127
year: 2020
CODEN: ITCOB4
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 23 16:03:24 2020
bibtimestamp: 2020.07.23 16:03:24 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Y. Luo and S. Yu
title:
Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses

rawtitle:
Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses

entry:
@Article{Luo:2020:ADN,
  author =       "Y. Luo and S. Yu",
  title =        "Accelerating Deep Neural Network In-Situ Training With
                 Non-Volatile and Volatile Memory Based Hybrid Precision
                 Synapses",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "69",
  number =       "8",
  pages =        "1113--1127",
  year =         "2020",
  CODEN =        "ITCOB4",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 23 16:03:24 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Marquer:2020:HLI
author: Yoann Marquer and Tania Richmond
title: A Hole in the Ladder: Interleaved Variables in Iterative Conditional Branching
crossref: Cornea:2020:ISC
pages: 56--63
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00017
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Yoann Marquer and Tania Richmond
rawtitle: A Hole in the Ladder: Interleaved Variables in Iterative Conditional Branching
abstract:
The modular exponentiation is crucial to the RSA cryptographic protocol, and variants inspired by the Montgomery ladder have been studied to provide more secure algorithms. In this paper, we abstract away the iterative conditional branching used in the Montgomery ladder, and formalize systems of equations necessary to obtain what we call the semi-interleaved and fully-interleaved ladder properties. In particular, we design fault-injection attacks able to obtain bits of the secret against semi-interleaved ladders, including the Montgomery ladder, but not against fully-interleaved ladders that are more secure. We also apply these equations to extend the Montgomery ladder for both the semi- and fully-interleaved cases, thus proposing novel and more secure algorithms to compute the modular exponentiation.

keywords:
Countermeasures (computer); Cryptography; Fault detection; Iterative algorithms; Mathematical model; Public-key cryptography; Registers; Security; Side-channel attacks; Space exploration

rawabstract:
The modular exponentiation is crucial to the RSA cryptographic protocol, and variants inspired by the Montgomery ladder have been studied to provide more secure algorithms. In this paper, we abstract away the iterative conditional branching used in the Montgomery ladder, and formalize systems of equations necessary to obtain what we call the semi-interleaved and fully-interleaved ladder properties. In particular, we design fault-injection attacks able to obtain bits of the secret against semi-interleaved ladders, including the Montgomery ladder, but not against fully-interleaved ladders that are more secure. We also apply these equations to extend the Montgomery ladder for both the semi- and fully-interleaved cases, thus proposing novel and more secure algorithms to compute the modular exponentiation.

entry:
@InProceedings{Marquer:2020:HLI,
  author =       "Yoann Marquer and Tania Richmond",
  title =        "A Hole in the Ladder: Interleaved Variables in
                 Iterative Conditional Branching",
  crossref =     "Cornea:2020:ISC",
  pages =        "56--63",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00017",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The modular exponentiation is crucial to the RSA
                 cryptographic protocol, and variants inspired by the
                 Montgomery ladder have been studied to provide more
                 secure algorithms. In this paper, we abstract away the
                 iterative conditional branching used in the Montgomery
                 ladder, and formalize systems of equations necessary to
                 obtain what we call the semi-interleaved and
                 fully-interleaved ladder properties. In particular, we
                 design fault-injection attacks able to obtain bits of
                 the secret against semi-interleaved ladders, including
                 the Montgomery ladder, but not against
                 fully-interleaved ladders that are more secure. We also
                 apply these equations to extend the Montgomery ladder
                 for both the semi- and fully-interleaved cases, thus
                 proposing novel and more secure algorithms to compute
                 the modular exponentiation.",
  acknowledgement = ack-nhfb,
  keywords =     "Countermeasures (computer); Cryptography; Fault
                 detection; Iterative algorithms; Mathematical model;
                 Public-key cryptography; Registers; Security;
                 Side-channel attacks; Space exploration",
}


bibtype: techreport
filename: fparith.bib
label: Meurant:2020:PFM
author: Gerard Meurant
title: pkg FLOATP_toolbox, Matlab software, variable precision floating point arithmetic.
type: Report
institution: Commissariat a l'Energie Atomique (CEA)
address: ????, France
pages: 56--63
year: 2020
bibdate: Sat Dec 23 12:13:27 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib
bibtimestamp: 2023.12.23 12:13:27 ???
URL: https://gerard-meurant.pagesperso-orange.fr/soft_meurant_n.html
remark: URL links to almost-empty home page.
acknowledgement: ack-nhfb
rawauthor: G{\'e}rard Meurant
rawtitle: \pkg{FLOATP\_toolbox}, {Matlab} software, variable precision floating point arithmetic.
entry:
@TechReport{Meurant:2020:PFM,
  author =       "G{\'e}rard Meurant",
  title =        "\pkg{FLOATP\_toolbox}, {Matlab} software, variable
                 precision floating point arithmetic.",
  type =         "Report",
  number =       "????",
  institution =  "Commissariat a l'{\'E}nergie Atomique (CEA)",
  address =      "????, France",
  year =         "2020",
  bibdate =      "Sat Dec 23 12:13:27 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib",
  URL =          "https://gerard-meurant.pagesperso-orange.fr/soft_meurant_n.html",
  acknowledgement = ack-nhfb,
  remark =       "URL links to almost-empty home page.",
}


bibtype: inproceedings
filename: fparith.bib
label: Mikaitis:2020:IRG
author: Mantas Mikaitis
crossref: Cornea:2020:ISC
pages: 129--132
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00028
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/gnu.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Mantas Mikaitis
title:
Issues with rounding in the GCC implementation of the ISO 18037:2008 standard fixed-point arithmetic

abstract:
We describe various issues caused by the lack of round-to-nearest mode in the gcc compiler implementation of the fixed-point arithmetic data types and operations. We demonstrate that round-to-nearest is not performed in the conversion of constants, conversion from one numerical type to a less precise type and results of multiplications. Furthermore, we show that mixed-precision operations in fixed-point arithmetic lose precision on arguments, even before carrying out arithmetic operations. The ISO 18037:2008 standard was created to standardize C language extensions, including fixed-point arithmetic, for embedded systems. Embedded systems are usually based on ARM processors, of which approximately 100 billion have been manufactured by now. Therefore, the observations about numerical issues that we discuss in this paper can be rather dangerous and are important to address, given the wide ranging type of applications that these embedded systems are running.

keywords:
Computer languages; Embedded systems; fixed-point arithmetic; Hardware; ISO 18037:2008; ISO Standards; Libraries; Program processors; rounding

rawabstract:
We describe various issues caused by the lack of round-to-nearest mode in the gcc compiler implementation of the fixed-point arithmetic data types and operations. We demonstrate that round-to-nearest is not performed in the conversion of constants, conversion from one numerical type to a less precise type and results of multiplications. Furthermore, we show that mixed-precision operations in fixed-point arithmetic lose precision on arguments, even before carrying out arithmetic operations. The ISO 18037:2008 standard was created to standardize C language extensions, including fixed-point arithmetic, for embedded systems. Embedded systems are usually based on ARM processors, of which approximately 100 billion have been manufactured by now. Therefore, the observations about numerical issues that we discuss in this paper can be rather dangerous and are important to address, given the wide ranging type of applications that these embedded systems are running.

rawtitle:
Issues with rounding in the {GCC} implementation of the {ISO 18037:2008} standard fixed-point arithmetic

entry:
@InProceedings{Mikaitis:2020:IRG,
  author =       "Mantas Mikaitis",
  title =        "Issues with rounding in the {GCC} implementation of
                 the {ISO 18037:2008} standard fixed-point arithmetic",
  crossref =     "Cornea:2020:ISC",
  pages =        "129--132",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00028",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/gnu.bib",
  abstract =     "We describe various issues caused by the lack of
                 round-to-nearest mode in the gcc compiler
                 implementation of the fixed-point arithmetic data types
                 and operations. We demonstrate that round-to-nearest is
                 not performed in the conversion of constants,
                 conversion from one numerical type to a less precise
                 type and results of multiplications. Furthermore, we
                 show that mixed-precision operations in fixed-point
                 arithmetic lose precision on arguments, even before
                 carrying out arithmetic operations. The ISO 18037:2008
                 standard was created to standardize C language
                 extensions, including fixed-point arithmetic, for
                 embedded systems. Embedded systems are usually based on
                 ARM processors, of which approximately 100 billion have
                 been manufactured by now. Therefore, the observations
                 about numerical issues that we discuss in this paper
                 can be rather dangerous and are important to address,
                 given the wide ranging type of applications that these
                 embedded systems are running.",
  acknowledgement = ack-nhfb,
  keywords =     "Computer languages; Embedded systems; fixed-point
                 arithmetic; Hardware; ISO 18037:2008; ISO Standards;
                 Libraries; Program processors; rounding",
}


bibtype: article
filename: fparith.bib
label: Muller:2020:EFA
author: Jean-Michel Muller
title: Elementary Functions and Approximate Computing
journal: j-PROC-IEEE
volume: 108
number: 12
pages: 2136--2149
month: dec
monthnumber: 12
year: 2020
CODEN: IEEPAD
DOI: https://doi.org/10.1109/jproc.2020.2991885
ISSN: 0018-9219 (print), 1558-2256 (electronic) OR 00189219 (print), 15582256 (electronic)
ISSNL: 0018-9219 OR 00189219
bibdate: Fri Sep 29 10:23:28 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 10:23:28 ???
fjournal: Proceedings of the IEEE
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5
rawauthor: Jean-Michel Muller
rawtitle: Elementary Functions and Approximate Computing
abstract:
In this article, we review some of the classical methods used for quickly obtaining low-precision approximations to the elementary functions. Then, for each of the three main classes of elementary function algorithms (shift-and-add algorithms, polynomial or rational approximations, and table-based methods) and for the additional, specific to approximate computing, ``bit-manipulation'' techniques, we examine what can be done for obtaining very fast estimates of a function, at the cost of a (controlled) loss in terms of accuracy.

rawabstract:
In this article, we review some of the classical methods used for quickly obtaining low-precision approximations to the elementary functions. Then, for each of the three main classes of elementary function algorithms (shift-and-add algorithms, polynomial or rational approximations, and table-based methods) and for the additional, specific to approximate computing, ``bit-manipulation'' techniques, we examine what can be done for obtaining very fast estimates of a function, at the cost of a (controlled) loss in terms of accuracy.

entry:
@Article{Muller:2020:EFA,
  author =       "Jean-Michel Muller",
  title =        "Elementary Functions and Approximate Computing",
  journal =      j-PROC-IEEE,
  volume =       "108",
  number =       "12",
  pages =        "2136--2149",
  month =        dec,
  year =         "2020",
  CODEN =        "IEEPAD",
  DOI =          "https://doi.org/10.1109/jproc.2020.2991885",
  ISSN =         "0018-9219 (print), 1558-2256 (electronic)",
  ISSN-L =       "0018-9219",
  bibdate =      "Fri Sep 29 10:23:28 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this article, we review some of the classical
                 methods used for quickly obtaining low-precision
                 approximations to the elementary functions. Then, for
                 each of the three main classes of elementary function
                 algorithms (shift-and-add algorithms, polynomial or
                 rational approximations, and table-based methods) and
                 for the additional, specific to approximate computing,
                 ``bit-manipulation'' techniques, we examine what can be
                 done for obtaining very fast estimates of a function,
                 at the cost of a (controlled) loss in terms of
                 accuracy.",
  acknowledgement = ack-nhfb,
  fjournal =     "Proceedings of the IEEE",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5",
}


bibtype: inproceedings
filename: fparith.bib
label: Murillo:2020:CPA
author: Raul Murillo and Alberto A. Del Barrio and Guillermo Botella
editor: IEEE
booktitle: IEEE International Symposium on Circuits and Systems (ISCAS): Seville, Spain, October 11--14, 2020
title: Customized Posit Adders and Multipliers using the FloPoCo Core Generator
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--5
year: 2020
DOI: https://doi.org/10.1109/ISCAS45731.2020.9180771
ISBN: 1-72813-320-3 OR 1728133203
ISBN13: 978-1-72813-320-1 OR 9781728133201
ISSN: 0271-4302 (print), 2158-1525 (electronic) OR 02714302 (print), 21581525 (electronic)
ISSNL: 0271-4302 OR 02714302
bibdate: Thu Dec 14 17:18:33 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.14 17:18:33 ???
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1109/ISCAS45731.2020
rawauthor: Raul Murillo and Alberto A. {Del Barrio} and Guillermo Botella
raweditor: {IEEE}
rawtitle: Customized Posit Adders and Multipliers using the {FloPoCo} Core Generator
rawbooktitle:
{IEEE International Symposium on Circuits and Systems (ISCAS): Seville, Spain, October 11--14, 2020}

entry:
@InProceedings{Murillo:2020:CPA,
  author =       "Raul Murillo and Alberto A. {Del Barrio} and Guillermo
                 Botella",
  editor =       "{IEEE}",
  booktitle =    "{IEEE International Symposium on Circuits and Systems
                 (ISCAS): Seville, Spain, October 11--14, 2020}",
  title =        "Customized Posit Adders and Multipliers using the
                 {FloPoCo} Core Generator",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ISCAS45731.2020.9180771",
  ISBN =         "1-72813-320-3",
  ISBN-13 =      "978-1-72813-320-1",
  ISSN =         "0271-4302 (print), 2158-1525 (electronic)",
  ISSN-L =       "0271-4302",
  bibdate =      "Thu Dec 14 17:18:33 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1109/ISCAS45731.2020",
}


bibtype: article
filename: fparith.bib
label: Murillo:2020:DPD
author: R. Murillo and A. A. Del Barrio and G. Botella
title: Deep PeNSieve: a deep learning framework based on the posit number system
journal: j-DIGIT-SIGNAL-PROCESS
volume: 102
pages: 1--8
month: jul
monthnumber: 7
year: 2020
CODEN: DSPREJ
DOI: https://doi.org/10.1016/j.dsp.2020.102762
ISSN: 1051-2004 (print), 1095-4333 (electronic) OR 10512004 (print), 10954333 (electronic)
ISSNL: 1051-2004 OR 10512004
bibdate: Thu Dec 14 17:04:34 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.14 17:04:34 ???
URL: https://www.sciencedirect.com/science/article/pii/S105120042030107X
fjournal: Digital Signal Processing
acknowledgement: ack-nhfb
articleno: 102762
journalURL: https://www.sciencedirect.com/journal/digital-signal-processing
rawauthor: R. Murillo and A. A. {Del Barrio} and G. Botella
rawtitle: {Deep PeNSieve}: a deep learning framework based on the posit number system
entry:
@Article{Murillo:2020:DPD,
  author =       "R. Murillo and A. A. {Del Barrio} and G. Botella",
  title =        "{Deep PeNSieve}: a deep learning framework based on
                 the posit number system",
  journal =      j-DIGIT-SIGNAL-PROCESS,
  volume =       "102",
  pages =        "1--8",
  month =        jul,
  year =         "2020",
  CODEN =        "DSPREJ",
  DOI =          "https://doi.org/10.1016/j.dsp.2020.102762",
  ISSN =         "1051-2004 (print), 1095-4333 (electronic)",
  ISSN-L =       "1051-2004",
  bibdate =      "Thu Dec 14 17:04:34 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.sciencedirect.com/science/article/pii/S105120042030107X",
  acknowledgement = ack-nhfb,
  articleno =    "102762",
  fjournal =     "Digital Signal Processing",
  journal-URL =  "https://www.sciencedirect.com/journal/digital-signal-processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Nannarelli:2020:VPB
author: Alberto Nannarelli
title: Variable Precision 16-Bit Floating-Point Vector Unit for Embedded Processors
crossref: Cornea:2020:ISC
pages: 96--102
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00022
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Alberto Nannarelli
rawtitle: Variable Precision 16-Bit Floating-Point Vector Unit for Embedded Processors
abstract:
The increasing demand of computation at the edge and the tight power budgets push designers to migrate double and single-precision calculations to formats of reduced precision and dynamic range for applications that can tolerate some inaccuracy.In this context, we introduce a variable format for reduced precision floating-point with storage limited to 16 bits. This format is suitable for applications in signal processing, machine learning and other applications in embedded systems. We present the hardware implementations for multiplication and division units that can sustain a throughput of one result per clock cycle designed for vector processing. We also show some examples of applications that can benefit from the proposed format.

keywords:
Adders; customizable bias; Dynamic range; Encoding; Floating-point; Hardware; Program processors; Signal processing; Standards; variable precision

rawabstract:
The increasing demand of computation at the edge and the tight power budgets push designers to migrate double and single-precision calculations to formats of reduced precision and dynamic range for applications that can tolerate some inaccuracy.In this context, we introduce a variable format for reduced precision floating-point with storage limited to 16 bits. This format is suitable for applications in signal processing, machine learning and other applications in embedded systems. We present the hardware implementations for multiplication and division units that can sustain a throughput of one result per clock cycle designed for vector processing. We also show some examples of applications that can benefit from the proposed format.

entry:
@InProceedings{Nannarelli:2020:VPB,
  author =       "Alberto Nannarelli",
  title =        "Variable Precision 16-Bit Floating-Point Vector Unit
                 for Embedded Processors",
  crossref =     "Cornea:2020:ISC",
  pages =        "96--102",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00022",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The increasing demand of computation at the edge and
                 the tight power budgets push designers to migrate
                 double and single-precision calculations to formats of
                 reduced precision and dynamic range for applications
                 that can tolerate some inaccuracy.In this context, we
                 introduce a variable format for reduced precision
                 floating-point with storage limited to 16 bits. This
                 format is suitable for applications in signal
                 processing, machine learning and other applications in
                 embedded systems. We present the hardware
                 implementations for multiplication and division units
                 that can sustain a throughput of one result per clock
                 cycle designed for vector processing. We also show some
                 examples of applications that can benefit from the
                 proposed format.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; customizable bias; Dynamic range; Encoding;
                 Floating-point; Hardware; Program processors; Signal
                 processing; Standards; variable precision",
}


bibtype: misc
filename: fparith.bib
label: Nass:2020:GUL
author: Rich Nass
title: GreenWaves Ultra-Low Power GAP9 IoT Apps Processor Suits Intelligence at the Edge
pages: 96--102
day: 21
month: jan
monthnumber: 1
year: 2020
bibdate: Wed Jan 22 07:07:03 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.22 07:07:03 ???
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Rich Nass
rawtitle: {GreenWaves} Ultra-Low Power {GAP9} {IoT} Apps Processor Suits Intelligence at the Edge
note:
GAP9 offers vectorized 2-bit and 4-bit fixed-point arithmetic, and 8-, 16-, and 32-bit floating-point arithmetic.

URL:
https://www.embedded-computing.com/guest-blogs/greenwaves-ultra-low-power-gap9-iot-apps-processor-suits-intelligence-at-the-edge

rawnote:
GAP9 offers vectorized 2-bit and 4-bit fixed-point arithmetic, and 8-, 16-, and 32-bit floating-point arithmetic.

entry:
@Misc{Nass:2020:GUL,
  author =       "Rich Nass",
  title =        "{GreenWaves} Ultra-Low Power {GAP9} {IoT} Apps
                 Processor Suits Intelligence at the Edge",
  howpublished = "Web site",
  day =          "21",
  month =        jan,
  year =         "2020",
  bibdate =      "Wed Jan 22 07:07:03 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "GAP9 offers vectorized 2-bit and 4-bit fixed-point
                 arithmetic, and 8-, 16-, and 32-bit floating-point
                 arithmetic.",
  URL =          "https://www.embedded-computing.com/guest-blogs/greenwaves-ultra-low-power-gap9-iot-apps-processor-suits-intelligence-at-the-edge",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Neves:2020:DFM
author: Nuno Neves and Pedro Tomas and Nuno Roma
editor: IEEE
booktitle: 2020 IEEE Workshop on Signal Processing Systems (SiPS)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2020
DOI: https://doi.org/10.1109/SiPS50750.2020.9195256
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Nuno Neves and Pedro Tom{\'a}s and Nuno Roma
rawbooktitle: {2020 IEEE Workshop on Signal Processing Systems (SiPS)}
raweditor: {IEEE}
title:
Dynamic Fused Multiply-Accumulate Posit Unit with Variable Exponent Size for Low-Precision DSP Applications

rawtitle:
Dynamic Fused Multiply-Accumulate Posit Unit with Variable Exponent Size for Low-Precision {DSP} Applications

entry:
@InProceedings{Neves:2020:DFM,
  author =       "Nuno Neves and Pedro Tom{\'a}s and Nuno Roma",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE Workshop on Signal Processing Systems
                 (SiPS)}",
  title =        "Dynamic Fused Multiply-Accumulate Posit Unit with
                 Variable Exponent Size for Low-Precision {DSP}
                 Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/SiPS50750.2020.9195256",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Neves:2020:RSB
author: Nuno Neves and Pedro Tomas and Nuno Roma
editor: IEEE
title: Reconfigurable Stream-based Tensor Unit with Variable-Precision Posit Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 149--156
year: 2020
DOI: https://doi.org/10.1109/ASAP49362.2020.00033
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Nuno Neves and Pedro Tom{\'a}s and Nuno Roma
raweditor: {IEEE}
rawtitle: Reconfigurable Stream-based Tensor Unit with Variable-Precision Posit Arithmetic
booktitle:
2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP)

rawbooktitle:
{2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP)}

entry:
@InProceedings{Neves:2020:RSB,
  author =       "Nuno Neves and Pedro Tom{\'a}s and Nuno Roma",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 31st International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP)}",
  title =        "Reconfigurable Stream-based Tensor Unit with
                 Variable-Precision Posit Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "149--156",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ASAP49362.2020.00033",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Niasar:2020:FSA
author: Mojtaba Bisheh Niasar and Rami El Khatib and Reza Azarderakhsh and Mehran Mozaffari-Kermani
title: Fast, Small, and Area-Time Efficient Architectures for Key-Exchange on Curve25519
crossref: Cornea:2020:ISC
pages: 72--79
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00019
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Mojtaba Bisheh Niasar and Rami {El Khatib} and Reza Azarderakhsh and Mehran Mozaffari-Kermani
rawtitle: Fast, Small, and Area-Time Efficient Architectures for Key-Exchange on {Curve25519}
abstract:
This paper demonstrates fast and compact implementations of Elliptic Curve Cryptography (ECC) for efficient key agreement over Curve25519. Curve25519 has been recently adopted as a key exchange method for several applications and included in the National Institute of Standards and Technology (NIST) recommendations for public key cryptography. This paper presents three different performance level designs including lightweight, area-time efficient, and high-performance architectures. Lightweight hardware implementations are used for several Internet of Things (IoT) applications due to their resources being at premium. Our lightweight architecture utilizes 90% less resources compared to the best previous work while it is still more optimized in term of A $ cdot $ T (area $ times $ time). For efficient implementation from either time or utilized resources, our area-time efficient architecture can establish almost 7,000 key sessions per second which is 64% faster than the previous works. The area-time efficient architecture uses well scheduled interleaved multiplication combined with a reduction algorithm. Additionally, we offer a fast architecture for high performance applications based on the 4-level Karatsuba method and Carry-Compact Addition (CCA). Our high-performance architecture also outperforms previous work in terms of A middot; T. The results show 9% and 29% improvement in A middot; T and Admiddot; T (DSP_count $ times $ time), respectively. All architectures are variable-base-point implemented on the Xilinx Zynq-7020 FPGA family where performance and implementation metrics are reported and compared. Finally, various side-channel attack countermeasures are embedded in the proposed architectures.

keywords:
Computer architecture; Curve25519; Elliptic curve cryptography; elliptic curve Diffie-Hellman (ECDH); Elliptic curves; Field programmable gate arrays; field-programmable gate array (FPGA); Hardware; NIST; point multiplication; Random access memory

rawabstract:
This paper demonstrates fast and compact implementations of Elliptic Curve Cryptography (ECC) for efficient key agreement over Curve25519. Curve25519 has been recently adopted as a key exchange method for several applications and included in the National Institute of Standards and Technology (NIST) recommendations for public key cryptography. This paper presents three different performance level designs including lightweight, area-time efficient, and high-performance architectures. Lightweight hardware implementations are used for several Internet of Things (IoT) applications due to their resources being at premium. Our lightweight architecture utilizes 90\% less resources compared to the best previous work while it is still more optimized in term of A $ \cdot $ T (area $ \times $ time). For efficient implementation from either time or utilized resources, our area-time efficient architecture can establish almost 7,000 key sessions per second which is 64\% faster than the previous works. The area-time efficient architecture uses well scheduled interleaved multiplication combined with a reduction algorithm. Additionally, we offer a fast architecture for high performance applications based on the 4-level Karatsuba method and Carry-Compact Addition (CCA). Our high-performance architecture also outperforms previous work in terms of A middot; T. The results show 9\% and 29\% improvement in A middot; T and Admiddot; T (DSP\_count $ \times $ time), respectively. All architectures are variable-base-point implemented on the Xilinx Zynq-7020 FPGA family where performance and implementation metrics are reported and compared. Finally, various side-channel attack countermeasures are embedded in the proposed architectures.

entry:
@InProceedings{Niasar:2020:FSA,
  author =       "Mojtaba Bisheh Niasar and Rami {El Khatib} and Reza
                 Azarderakhsh and Mehran Mozaffari-Kermani",
  title =        "Fast, Small, and Area-Time Efficient Architectures for
                 Key-Exchange on {Curve25519}",
  crossref =     "Cornea:2020:ISC",
  pages =        "72--79",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00019",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper demonstrates fast and compact
                 implementations of Elliptic Curve Cryptography (ECC)
                 for efficient key agreement over Curve25519. Curve25519
                 has been recently adopted as a key exchange method for
                 several applications and included in the National
                 Institute of Standards and Technology (NIST)
                 recommendations for public key cryptography. This paper
                 presents three different performance level designs
                 including lightweight, area-time efficient, and
                 high-performance architectures. Lightweight hardware
                 implementations are used for several Internet of Things
                 (IoT) applications due to their resources being at
                 premium. Our lightweight architecture utilizes 90\%
                 less resources compared to the best previous work while
                 it is still more optimized in term of A $ \cdot $ T
                 (area $ \times $ time). For efficient implementation
                 from either time or utilized resources, our area-time
                 efficient architecture can establish almost 7,000 key
                 sessions per second which is 64\% faster than the
                 previous works. The area-time efficient architecture
                 uses well scheduled interleaved multiplication combined
                 with a reduction algorithm. Additionally, we offer a
                 fast architecture for high performance applications
                 based on the 4-level Karatsuba method and Carry-Compact
                 Addition (CCA). Our high-performance architecture also
                 outperforms previous work in terms of A middot; T. The
                 results show 9\% and 29\% improvement in A middot; T
                 and Admiddot; T (DSP\_count $ \times $ time),
                 respectively. All architectures are variable-base-point
                 implemented on the Xilinx Zynq-7020 FPGA family where
                 performance and implementation metrics are reported and
                 compared. Finally, various side-channel attack
                 countermeasures are embedded in the proposed
                 architectures.",
  acknowledgement = ack-nhfb,
  keywords =     "Computer architecture; Curve25519; Elliptic curve
                 cryptography; elliptic curve Diffie-Hellman (ECDH);
                 Elliptic curves; Field programmable gate arrays;
                 field-programmable gate array (FPGA); Hardware; NIST;
                 point multiplication; Random access memory",
}


bibtype: inproceedings
filename: fparith.bib
label: Papachatzopoulos:2020:MDM
author: Kleanthis Papachatzopoulos and Vassilis Paliouras
title: Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations
crossref: Cornea:2020:ISC
pages: 88--95
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00021
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawauthor: Kleanthis Papachatzopoulos and Vassilis Paliouras
rawtitle: Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations
abstract:
This paper introduces a delay modeling formulation for several Parallel-Prefix Adders in the presence of threshold voltage variability. A path-based model is derived for the delay variability of Kogge-Stone, Knowles, Sklansky, Brent-Kung, Han-Carlson, Ladner-Fischer, and New Adder architectures. The delay model accuracy is evaluated for the specific adders on the basis of SPICE Monte-Carlo Simulations at 45 nm and 16 nm nodes. The presented analysis reveals that the proposed path-based model estimates the maximum delay Probability Density Function of the particular adder architectures with sufficient accuracy, assuming 3 intra-die threshold voltage variations as high as 10% of nominal value. Delay yield estimations produced by the proposed model are found to agree with those of Monte-Carlo Simulations for a number of highly probable critical paths, presenting an error less than 2%. For the particular adders and technology nodes, an approximately 10-fold reduction in simulation time is obtained when exploiting the proposed model. The particular observation indicates that the computational time for delay yield estimation of Parallel-Prefix Adders can be exponentially reduced with negligible accuracy loss when the analysis focuses solely on the Nominal-Maximum Delay critical path. Finally, a quantitative comparison of prefix adders to the Borrow-Save Adder is offered, in terms of complexity and susceptibility to variations.

keywords:
Adders; critical path; delay yield; Delays; Gaussian distribution; Monte Carlo methods; parallel-prefix adders; SPICE; Threshold voltage; threshold voltage variations; variability

rawabstract:
This paper introduces a delay modeling formulation for several Parallel-Prefix Adders in the presence of threshold voltage variability. A path-based model is derived for the delay variability of Kogge-Stone, Knowles, Sklansky, Brent-Kung, Han-Carlson, Ladner-Fischer, and New Adder architectures. The delay model accuracy is evaluated for the specific adders on the basis of SPICE Monte-Carlo Simulations at 45 nm and 16 nm nodes. The presented analysis reveals that the proposed path-based model estimates the maximum delay Probability Density Function of the particular adder architectures with sufficient accuracy, assuming 3 intra-die threshold voltage variations as high as 10\% of nominal value. Delay yield estimations produced by the proposed model are found to agree with those of Monte-Carlo Simulations for a number of highly probable critical paths, presenting an error less than 2\%. For the particular adders and technology nodes, an approximately 10-fold reduction in simulation time is obtained when exploiting the proposed model. The particular observation indicates that the computational time for delay yield estimation of Parallel-Prefix Adders can be exponentially reduced with negligible accuracy loss when the analysis focuses solely on the Nominal-Maximum Delay critical path. Finally, a quantitative comparison of prefix adders to the Borrow-Save Adder is offered, in terms of complexity and susceptibility to variations.

entry:
@InProceedings{Papachatzopoulos:2020:MDM,
  author =       "Kleanthis Papachatzopoulos and Vassilis Paliouras",
  title =        "Maximum Delay Models for Parallel-Prefix Adders in the
                 Presence of Threshold Voltage Variations",
  crossref =     "Cornea:2020:ISC",
  pages =        "88--95",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00021",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper introduces a delay modeling formulation for
                 several Parallel-Prefix Adders in the presence of
                 threshold voltage variability. A path-based model is
                 derived for the delay variability of Kogge-Stone,
                 Knowles, Sklansky, Brent-Kung, Han-Carlson,
                 Ladner-Fischer, and New Adder architectures. The delay
                 model accuracy is evaluated for the specific adders on
                 the basis of SPICE Monte-Carlo Simulations at 45 nm and
                 16 nm nodes. The presented analysis reveals that the
                 proposed path-based model estimates the maximum delay
                 Probability Density Function of the particular adder
                 architectures with sufficient accuracy, assuming 3
                 intra-die threshold voltage variations as high as 10\%
                 of nominal value. Delay yield estimations produced by
                 the proposed model are found to agree with those of
                 Monte-Carlo Simulations for a number of highly probable
                 critical paths, presenting an error less than 2\%. For
                 the particular adders and technology nodes, an
                 approximately 10-fold reduction in simulation time is
                 obtained when exploiting the proposed model. The
                 particular observation indicates that the computational
                 time for delay yield estimation of Parallel-Prefix
                 Adders can be exponentially reduced with negligible
                 accuracy loss when the analysis focuses solely on the
                 Nominal-Maximum Delay critical path. Finally, a
                 quantitative comparison of prefix adders to the
                 Borrow-Save Adder is offered, in terms of complexity
                 and susceptibility to variations.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; critical path; delay yield; Delays; Gaussian
                 distribution; Monte Carlo methods; parallel-prefix
                 adders; SPICE; Threshold voltage; threshold voltage
                 variations; variability",
}


bibtype: inproceedings
filename: fparith.bib
label: Payer:2020:SMF
title: SIMD Multi Format Floating-Point Unit on the IBM z15
crossref: Cornea:2020:ISC
pages: 125--128
month: jun
monthnumber: 6
year: 2020
DOI: https://doi.org/10.1109/ARITH48897.2020.00027
ISSN: 2576-2265 OR 25762265
bibdate: Wed Jul 7 06:24:52 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.07.07 06:24:52 ???
acknowledgement: ack-nhfb
rawtitle: {SIMD} Multi Format Floating-Point Unit on the {IBM z15}
author:
Stefan Payer and Cedric Lichtenau and Michael Klein and Kerstin Schelm and Petra Leber and Nicol Hofmann and Tina Babinsky

abstract:
The IBM z Systems(TM) is the backbone of the insurance, banking, and retail industry. Innovation in these markets is driving the demand for new and additional applications to better serve the customers. These workloads like machine learning, data analytics, AI, etc. require a rapidly increasing number of computations in smaller precision formats. With IBM z15(TM) we completely redesigned the binary and hexadecimal floating-point unit to efficiently implement SIMD operations at 5.2GHz while maintaining the industry leading reliability, availability and serviceability standard. This paper describes the new design and special techniques used to achieve these goals like reusing the existing double precision unit pipeline for lower precision parallel SIMD, new approaches to formally verify the design, and improving error detection for the 14nm technology node.

keywords:
AI; Binary; Digital arithmetic; Floating Point Unit; Formal Verification; Hafnium; Hexadecimal; IBM z15(TM); Machine Learning; Multi Format; SIMD

rawabstract:
The IBM z Systems(TM) is the backbone of the insurance, banking, and retail industry. Innovation in these markets is driving the demand for new and additional applications to better serve the customers. These workloads like machine learning, data analytics, AI, etc. require a rapidly increasing number of computations in smaller precision formats. With IBM z15(TM) we completely redesigned the binary and hexadecimal floating-point unit to efficiently implement SIMD operations at 5.2GHz while maintaining the industry leading reliability, availability and serviceability standard. This paper describes the new design and special techniques used to achieve these goals like reusing the existing double precision unit pipeline for lower precision parallel SIMD, new approaches to formally verify the design, and improving error detection for the 14nm technology node.

rawauthor:
Stefan Payer and Cedric Lichtenau and Michael Klein and Kerstin Schelm and Petra Leber and Nicol Hofmann and Tina Babinsky

entry:
@InProceedings{Payer:2020:SMF,
  author =       "Stefan Payer and Cedric Lichtenau and Michael Klein
                 and Kerstin Schelm and Petra Leber and Nicol Hofmann
                 and Tina Babinsky",
  title =        "{SIMD} Multi Format Floating-Point Unit on the {IBM
                 z15}",
  crossref =     "Cornea:2020:ISC",
  pages =        "125--128",
  month =        jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ARITH48897.2020.00027",
  ISSN =         "2576-2265",
  bibdate =      "Wed Jul 7 06:24:52 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The IBM z Systems(TM) is the backbone of the
                 insurance, banking, and retail industry. Innovation in
                 these markets is driving the demand for new and
                 additional applications to better serve the customers.
                 These workloads like machine learning, data analytics,
                 AI, etc. require a rapidly increasing number of
                 computations in smaller precision formats. With IBM
                 z15(TM) we completely redesigned the binary and
                 hexadecimal floating-point unit to efficiently
                 implement SIMD operations at 5.2GHz while maintaining
                 the industry leading reliability, availability and
                 serviceability standard. This paper describes the new
                 design and special techniques used to achieve these
                 goals like reusing the existing double precision unit
                 pipeline for lower precision parallel SIMD, new
                 approaches to formally verify the design, and improving
                 error detection for the 14nm technology node.",
  acknowledgement = ack-nhfb,
  keywords =     "AI; Binary; Digital arithmetic; Floating Point Unit;
                 Formal Verification; Hafnium; Hexadecimal; IBM z15(TM);
                 Machine Learning; Multi Format; SIMD",
}


bibtype: inproceedings
filename: fparith.bib
label: Raveendran:2020:NPF
author: Aneesh Raveendran and Sandra Jean and J. Mervin and D. Vivian and David Selvakumar
editor: IEEE
title: A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 207--212
month: jan
monthnumber: 1
year: 2020
DOI: https://doi.org/10.1109/vlsid49098.2020.00053
ISBN: 1-72815-701-3 OR 1728157013
ISBN13: 978-1-72815-701-6 OR 9781728157016
ISSN: 1063-9667 (print), 2380-6923 (electronic) OR 10639667 (print), 23806923 (electronic)
ISSNL: 1063-9667 OR 10639667
bibdate: Fri Dec 15 07:29:26 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:29:26 ???
acknowledgement: ack-nhfb
rawauthor: Aneesh Raveendran and Sandra Jean and J. Mervin and D. Vivian and David Selvakumar
raweditor: {IEEE}
rawtitle: A Novel Parametrized Fused Division and Square-Root {POSIT} Arithmetic Architecture
booktitle:
2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), Bengaluru, India, 4--8 January 2020

rawbooktitle:
{2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), Bengaluru, India, 4--8 January 2020}

entry:
@InProceedings{Raveendran:2020:NPF,
  author =       "Aneesh Raveendran and Sandra Jean and J. Mervin and D.
                 Vivian and David Selvakumar",
  editor =       "{IEEE}",
  booktitle =    "{2020 33rd International Conference on VLSI Design and
                 2020 19th International Conference on Embedded Systems
                 (VLSID), Bengaluru, India, 4--8 January 2020}",
  title =        "A Novel Parametrized Fused Division and Square-Root
                 {POSIT} Arithmetic Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "207--212",
  month =        jan,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/vlsid49098.2020.00053",
  ISBN =         "1-72815-701-3",
  ISBN-13 =      "978-1-72815-701-6",
  ISSN =         "1063-9667 (print), 2380-6923 (electronic)",
  ISSN-L =       "1063-9667",
  bibdate =      "Fri Dec 15 07:29:26 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Saadat:2020:WWC
author: Hassaan Saadat and Haris Javaid and Aleksandar Ignjatovic and Sri Parameswaran
booktitle: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)
title: WEID: Worst-case Error Improvement in Approximate Dividers
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 8D-1--8D-6
month: jan
monthnumber: 1
year: 2020
DOI: https://doi.org/10.1109/asp-dac47756.2020.9045504
bibdate: Wed Dec 20 08:02:22 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.20 08:02:22 ???
acknowledgement: ack-nhfb
rawauthor: Hassaan Saadat and Haris Javaid and Aleksandar Ignjatovic and Sri Parameswaran
rawbooktitle: {2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)}
rawtitle: {WEID}: Worst-case Error Improvement in Approximate Dividers
abstract:
Approximate integer dividers suffer from unreasonably high worst-case relative errors (such as 50% or 100%), which can adversely affect the application-level output. In this paper, we propose WEID, which is a novel lightweight method to improve the worst-case relative errors in approximate integer dividers. We first present an in-depth analysis to gain insights into the cause of the high worst-case relative error. Based on our insights, we propose a novel method to detect when an error occurs in an approximate divider, and modify the output to reduce the error. Further, we present the hardware realization of WEID method and demonstrate that it can be generically coupled with several state-of-the-art approximate dividers. Our results show that for 32-by-16 dividers, WEID reduces worst-case relative errors from 100% to $ approx 20 $ %, while still achieving $ approx 80 % $ and $ approx 70 % $ reduction in delay and energy compared to an accurate array divider.

rawabstract:
Approximate integer dividers suffer from unreasonably high worst-case relative errors (such as 50\% or 100\%), which can adversely affect the application-level output. In this paper, we propose WEID, which is a novel lightweight method to improve the worst-case relative errors in approximate integer dividers. We first present an in-depth analysis to gain insights into the cause of the high worst-case relative error. Based on our insights, we propose a novel method to detect when an error occurs in an approximate divider, and modify the output to reduce the error. Further, we present the hardware realization of WEID method and demonstrate that it can be generically coupled with several state-of-the-art approximate dividers. Our results show that for 32-by-16 dividers, WEID reduces worst-case relative errors from 100\% to $ \approx 20 $ \%, while still achieving $ \approx 80 \% $ and $ \approx 70 \% $ reduction in delay and energy compared to an accurate array divider.

entry:
@InProceedings{Saadat:2020:WWC,
  author =       "Hassaan Saadat and Haris Javaid and Aleksandar
                 Ignjatovic and Sri Parameswaran",
  booktitle =    "{2020 25th Asia and South Pacific Design Automation
                 Conference (ASP-DAC)}",
  title =        "{WEID}: Worst-case Error Improvement in Approximate
                 Dividers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "8D-1--8D-6",
  month =        jan,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/asp-dac47756.2020.9045504",
  bibdate =      "Wed Dec 20 08:02:22 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Approximate integer dividers suffer from unreasonably
                 high worst-case relative errors (such as 50\% or
                 100\%), which can adversely affect the
                 application-level output. In this paper, we propose
                 WEID, which is a novel lightweight method to improve
                 the worst-case relative errors in approximate integer
                 dividers. We first present an in-depth analysis to gain
                 insights into the cause of the high worst-case relative
                 error. Based on our insights, we propose a novel method
                 to detect when an error occurs in an approximate
                 divider, and modify the output to reduce the error.
                 Further, we present the hardware realization of WEID
                 method and demonstrate that it can be generically
                 coupled with several state-of-the-art approximate
                 dividers. Our results show that for 32-by-16 dividers,
                 WEID reduces worst-case relative errors from 100\% to $
                 \approx 20 $ \%, while still achieving $ \approx 80 \%
                 $ and $ \approx 70 \% $ reduction in delay and energy
                 compared to an accurate array divider.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: SEGGER:2020:SFP
author: SEGGER Microcontroller
title: SEGGER Floating-Point Library
pages: 8D-1--8D-6
month: jan
monthnumber: 1
year: 2020
bibdate: Fri Feb 07 06:02:26 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.07 06:02:26 ???
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: {SEGGER Microcontroller}
rawtitle: {SEGGER} Floating-Point Library
URL:
https://www.segger.com/products/development-tools/runtime-library/technology/floating-point-library/

abstract:
The floating-point library contains complete, fully optimized and verified floating point functionality, which is required for devices without an FPU. The floating-point emulator, a crucial part of the floating-point library, of the Arm and RISC-V variants are written in assembly language, optimized either for small code size or increased execution speed. For other processor architectures the library has a portable C implementation. ldots The SEGGER Floating-Point Library is delivered in source code, with optional rights for redistribution in object code form. All source files, a mix of C code and assembly, are fully commented. The floating-point emulator, providing the low-level functions, is entirely written in assembly. Higher level functions are implemented as a mix of primarily C code with some assembly routines. The code can be compiled with any ANSO-compliant C compiler, such as GCC, Clang, or IAR.

rawabstract:
The floating-point library contains complete, fully optimized and verified floating point functionality, which is required for devices without an FPU. The floating-point emulator, a crucial part of the floating-point library, of the Arm and RISC-V variants are written in assembly language, optimized either for small code size or increased execution speed. For other processor architectures the library has a portable C implementation. \ldots{} The SEGGER Floating-Point Library is delivered in source code, with optional rights for redistribution in object code form. All source files, a mix of C code and assembly, are fully commented. The floating-point emulator, providing the low-level functions, is entirely written in assembly. Higher level functions are implemented as a mix of primarily C code with some assembly routines. The code can be compiled with any ANSO-compliant C compiler, such as GCC, Clang, or IAR.

entry:
@Misc{SEGGER:2020:SFP,
  author =       "{SEGGER Microcontroller}",
  title =        "{SEGGER} Floating-Point Library",
  howpublished = "Web site.",
  month =        jan,
  year =         "2020",
  bibdate =      "Fri Feb 07 06:02:26 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.segger.com/products/development-tools/runtime-library/technology/floating-point-library/",
  abstract =     "The floating-point library contains complete, fully
                 optimized and verified floating point functionality,
                 which is required for devices without an FPU. The
                 floating-point emulator, a crucial part of the
                 floating-point library, of the Arm and RISC-V variants
                 are written in assembly language, optimized either for
                 small code size or increased execution speed. For other
                 processor architectures the library has a portable C
                 implementation. \ldots{} The SEGGER Floating-Point
                 Library is delivered in source code, with optional
                 rights for redistribution in object code form. All
                 source files, a mix of C code and assembly, are fully
                 commented. The floating-point emulator, providing the
                 low-level functions, is entirely written in assembly.
                 Higher level functions are implemented as a mix of
                 primarily C code with some assembly routines. The code
                 can be compiled with any ANSO-compliant C compiler,
                 such as GCC, Clang, or IAR.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Sharma:2020:CRV
title: CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism
journal: arXiv.org
pages: 1--20
day: 30
month: may
monthnumber: 5
year: 2020
DOI: https://doi.org/10.48550/arXiv.2006.00364
bibdate: Sat Dec 16 10:27:27 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 10:27:27 ???
URL: https://arxiv.org/abs/2006.00364
acknowledgement: ack-nhfb
rawtitle: {CLARINET}: A {RISC-V} Based Framework for Posit Arithmetic Empiricism
author:
Niraj Sharma and Riya Jain and Madhumita Mohan and Sachin Patkar and Rainer Leupers and Nikhil Rishiyur and Farhad Merchant

abstract:
Many engineering and scientific applications require high precision arithmetic. IEEE~754-2008 compliant (floating-point) arithmetic is the de facto standard for performing these computations. Recently, posit arithmetic has been proposed as a drop-in replacement for floating-point arithmetic. The positTM data representation and arithmetic claim several absolute advantages over the floating-point format and arithmetic, including higher dynamic range, better accuracy, and superior performance-area trade-offs. However, there does not exist any accessible, holistic framework that facilitates the validation of these claims of posit arithmetic, especially when the claims involve long accumulations (quire).par In this paper, we present a consolidated general-purpose processor-based framework to support posit arithmetic empiricism. The end-users of the framework have the liberty to seamlessly experiment with their applications using posit and floating-point arithmetic since the framework is designed for the two number systems to coexist. Melodica is a posit arithmetic core that implements parametric fused operations that uniquely involve the quire data type. Clarinet is a Melodica-enabled processor based on the RISC-V ISA. To the best of our knowledge, this is the first-ever integration of quire with a RISC-V core. To show the effectiveness of the Clarinet platform, we perform an extensive application study and benchmark some of the common linear algebra and computer vision kernels. We emulate Clarinet on a Xilinx FPGA and present utilization and timing data. Clarinet and Melodica remain actively under development and are available in open-source for posit arithmetic empiricism.

rawabstract:
Many engineering and scientific applications require high precision arithmetic. IEEE~754-2008 compliant (floating-point) arithmetic is the de facto standard for performing these computations. Recently, posit arithmetic has been proposed as a drop-in replacement for floating-point arithmetic. The posit{\TM} data representation and arithmetic claim several absolute advantages over the floating-point format and arithmetic, including higher dynamic range, better accuracy, and superior performance-area trade-offs. However, there does not exist any accessible, holistic framework that facilitates the validation of these claims of posit arithmetic, especially when the claims involve long accumulations (quire).\par In this paper, we present a consolidated general-purpose processor-based framework to support posit arithmetic empiricism. The end-users of the framework have the liberty to seamlessly experiment with their applications using posit and floating-point arithmetic since the framework is designed for the two number systems to coexist. Melodica is a posit arithmetic core that implements parametric fused operations that uniquely involve the quire data type. Clarinet is a Melodica-enabled processor based on the RISC-V ISA. To the best of our knowledge, this is the first-ever integration of quire with a RISC-V core. To show the effectiveness of the Clarinet platform, we perform an extensive application study and benchmark some of the common linear algebra and computer vision kernels. We emulate Clarinet on a Xilinx FPGA and present utilization and timing data. Clarinet and Melodica remain actively under development and are available in open-source for posit arithmetic empiricism.

rawauthor:
Niraj Sharma and Riya Jain and Madhumita Mohan and Sachin Patkar and Rainer Leupers and Nikhil Rishiyur and Farhad Merchant

entry:
@Article{Sharma:2020:CRV,
  author =       "Niraj Sharma and Riya Jain and Madhumita Mohan and
                 Sachin Patkar and Rainer Leupers and Nikhil Rishiyur
                 and Farhad Merchant",
  title =        "{CLARINET}: A {RISC-V} Based Framework for Posit
                 Arithmetic Empiricism",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--20",
  day =          "30",
  month =        may,
  year =         "2020",
  DOI =          "https://doi.org/10.48550/arXiv.2006.00364",
  bibdate =      "Sat Dec 16 10:27:27 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://arxiv.org/abs/2006.00364",
  abstract =     "Many engineering and scientific applications require
                 high precision arithmetic. IEEE~754-2008 compliant
                 (floating-point) arithmetic is the de facto standard
                 for performing these computations. Recently, posit
                 arithmetic has been proposed as a drop-in replacement
                 for floating-point arithmetic. The posit{\TM} data
                 representation and arithmetic claim several absolute
                 advantages over the floating-point format and
                 arithmetic, including higher dynamic range, better
                 accuracy, and superior performance-area trade-offs.
                 However, there does not exist any accessible, holistic
                 framework that facilitates the validation of these
                 claims of posit arithmetic, especially when the claims
                 involve long accumulations (quire).\par

                 In this paper, we present a consolidated
                 general-purpose processor-based framework to support
                 posit arithmetic empiricism. The end-users of the
                 framework have the liberty to seamlessly experiment
                 with their applications using posit and floating-point
                 arithmetic since the framework is designed for the two
                 number systems to coexist. Melodica is a posit
                 arithmetic core that implements parametric fused
                 operations that uniquely involve the quire data type.
                 Clarinet is a Melodica-enabled processor based on the
                 RISC-V ISA. To the best of our knowledge, this is the
                 first-ever integration of quire with a RISC-V core. To
                 show the effectiveness of the Clarinet platform, we
                 perform an extensive application study and benchmark
                 some of the common linear algebra and computer vision
                 kernels. We emulate Clarinet on a Xilinx FPGA and
                 present utilization and timing data. Clarinet and
                 Melodica remain actively under development and are
                 available in open-source for posit arithmetic
                 empiricism.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Shibata:2020:SPV
author: Naoki Shibata and Francesco Petrogalli
title: SLEEF: A Portable Vectorized Library of C Standard Mathematical Functions
journal: j-IEEE-TRANS-PAR-DIST-SYS
volume: 31
number: 6
pages: 1316--1327
month: jun
monthnumber: 6
year: 2020
CODEN: ITDSEO
DOI: https://doi.org/10.1109/TPDS.2019.2960333
ISSN: 1045-9219 (print), 1558-2183 (electronic) OR 10459219 (print), 15582183 (electronic)
ISSNL: 1045-9219 OR 10459219
bibdate: Thu Feb 20 10:08:58 2020
bibtimestamp: 2020.02.20 10:08:58 ???
fjournal: IEEE Transactions on Parallel and Distributed Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=71
rawauthor: Naoki Shibata and Francesco Petrogalli
rawtitle: {SLEEF}: A Portable Vectorized Library of {C} Standard Mathematical Functions
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranspardistsys.bib

keywords:
elementary functions; floating-point arithmetic; Parallel and vector implementations; SIMD processors

entry:
@Article{Shibata:2020:SPV,
  author =       "Naoki Shibata and Francesco Petrogalli",
  title =        "{SLEEF}: A Portable Vectorized Library of {C} Standard
                 Mathematical Functions",
  journal =      j-IEEE-TRANS-PAR-DIST-SYS,
  volume =       "31",
  number =       "6",
  pages =        "1316--1327",
  month =        jun,
  year =         "2020",
  CODEN =        "ITDSEO",
  DOI =          "https://doi.org/10.1109/TPDS.2019.2960333",
  ISSN =         "1045-9219 (print), 1558-2183 (electronic)",
  ISSN-L =       "1045-9219",
  bibdate =      "Thu Feb 20 10:08:58 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranspardistsys.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Parallel and Distributed
                 Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=71",
  keywords =     "elementary functions; floating-point arithmetic;
                 Parallel and vector implementations; SIMD processors",
}


bibtype: misc
filename: fparith.bib
label: Smith:2020:HMC
author: Ernie Smith
pages: 1316--1327
day: 14
month: sep
monthnumber: 9
year: 2020
bibdate: Thu Jan 28 17:58:10 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.01.28 17:58:10 ???
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Ernie Smith
title:
How a Minor Calculation Error Cost Intel Half a Billion Dollars: How one of the most famous computer bugs of all time, the Intel Pentium floating-point division glitch, blew out of proportion into a PR crisis

URL:
https://www.vice.com/en/article/dyzqdj/how-a-minor-calculation-error-cost-intel-half-a-billion-dollars

remark:
This is a retrospective on the infamous Pentium divide flaw of the 1990s. Near the end, it remarks about the discoverer of the bug ``[Thomas] Nicely, who died last year and was largely seen as legendary by his peers, spent roughly three decades at the University of Lynchburg before retiring in 2000.''

rawtitle:
How a Minor Calculation Error Cost {Intel} Half a Billion Dollars: How one of the most famous computer bugs of all time, the {Intel Pentium} floating-point division glitch, blew out of proportion into a {PR} crisis

entry:
@Misc{Smith:2020:HMC,
  author =       "Ernie Smith",
  title =        "How a Minor Calculation Error Cost {Intel} Half a
                 Billion Dollars: How one of the most famous computer
                 bugs of all time, the {Intel Pentium} floating-point
                 division glitch, blew out of proportion into a {PR}
                 crisis",
  howpublished = "Web site.",
  day =          "14",
  month =        sep,
  year =         "2020",
  bibdate =      "Thu Jan 28 17:58:10 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.vice.com/en/article/dyzqdj/how-a-minor-calculation-error-cost-intel-half-a-billion-dollars",
  acknowledgement = ack-nhfb,
  remark =       "This is a retrospective on the infamous Pentium divide
                 flaw of the 1990s. Near the end, it remarks about the
                 discoverer of the bug ``[Thomas] Nicely, who died last
                 year and was largely seen as legendary by his peers,
                 spent roughly three decades at the University of
                 Lynchburg before retiring in 2000.''",
}


