# bibtab

bibtype: techreport
filename: fparith.bib
label: Fousse:2004:FPD
author: Laurent Fousse and Paul Zimmermann
title: A Formal Proof of Demmel and Hida's Accurate Summation Algorithm
type: Technical Report
institution: inst-LORIA-INRIA-LORRAINE
address: inst-LORIA-INRIA-LORRAINE:adr
pages: 12
month: jan
monthnumber: 1
year: 2004
bibdate: Sun Sep 10 07:58:09 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.09.10 07:58:09 ???
URL: http://www.loria.fr/~zimmerma/papers/tcs.ps.gz
keywords: accurate floating-point summation; bounded error; floating-point arithmetic; formal proof
acknowledgement: ack-nhfb
rawauthor: Laurent Fousse and Paul Zimmermann
rawtitle: A Formal Proof of {Demmel} and {Hida}'s Accurate Summation Algorithm
abstract:
A new proof of the ``accurate summation'' algorithm proposed by Demmel and Hida is presented. The main part of that proof has been written in the Coq language and verified by the Coq proof assistant.

rawabstract:
A new proof of the ``accurate summation'' algorithm proposed by Demmel and Hida is presented. The main part of that proof has been written in the Coq language and verified by the Coq proof assistant.

entry:
@TechReport{Fousse:2004:FPD,
  author =       "Laurent Fousse and Paul Zimmermann",
  title =        "A Formal Proof of {Demmel} and {Hida}'s Accurate
                 Summation Algorithm",
  type =         "Technical Report",
  institution =  inst-LORIA-INRIA-LORRAINE,
  address =      inst-LORIA-INRIA-LORRAINE:adr,
  pages =        "12",
  month =        jan,
  year =         "2004",
  bibdate =      "Sun Sep 10 07:58:09 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.loria.fr/~zimmerma/papers/tcs.ps.gz",
  abstract =     "A new proof of the ``accurate summation'' algorithm
                 proposed by Demmel and Hida is presented. The main part
                 of that proof has been written in the Coq language and
                 verified by the Coq proof assistant.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation; bounded error;
                 floating-point arithmetic; formal proof",
}


bibtype: inproceedings
filename: fparith.bib
label: Frougny:2004:ICR
author: Christiane Frougny
title: Introduction: [6th conference on Real Numbers and Computers]
crossref: Frougny:2004:RCR
pages: 1--4
year: 2004
bibdate: Fri Nov 17 07:00:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.17 07:00:31 ???
URL: http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_00_intro.pdf
acknowledgement: ack-nhfb
rawauthor: Christiane Frougny
rawtitle: Introduction: [6th conference on Real Numbers and Computers]
entry:
@InProceedings{Frougny:2004:ICR,
  author =       "Christiane Frougny",
  title =        "Introduction: [6th conference on Real Numbers and
                 Computers]",
  crossref =     "Frougny:2004:RCR",
  pages =        "1--4",
  year =         "2004",
  bibdate =      "Fri Nov 17 07:00:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_00_intro.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Fuchssteiner:2004:ILN
author: Benno Fuchssteiner
crossref: Frougny:2004:RCR
pages: 5--5
year: 2004
bibdate: Fri Nov 17 07:00:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.17 07:00:31 ???
URL: http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_01_fuchssteiner.pdf
acknowledgement: ack-nhfb
rawauthor: Benno Fuchssteiner
title:
Invited Lecture: New ideas and results for solving Differential equations symbolically [abstract only]

abstract:
The lecture is a report on current research activities of the MuPAD group in the area of symbolic and numeric solutions of ODE (ordinary differential equations).par Based on a unification of Lie-point-symmetries and Lie--Backlund-symmetries the results of classical Lie-symmetry approaches (for example Liouville--Arnold) to ODE are generalized thus opening new avenues for using integrability (around initial values) for wider classes of differential equations.par Applications and numerical consequences of these results will be discussed and plans how to extend current solution methods, numerical as well as symbolical, to wider classes of transcendents (i.e. Painleve transcendents) will be presented

rawabstract:
The lecture is a report on current research activities of the MuPAD group in the area of symbolic and numeric solutions of ODE (ordinary differential equations).\par Based on a unification of Lie-point-symmetries and Lie--B{\"a}cklund-symmetries the results of classical Lie-symmetry approaches (for example Liouville--Arnold) to ODE are generalized thus opening new avenues for using integrability (around initial values) for wider classes of differential equations.\par Applications and numerical consequences of these results will be discussed and plans how to extend current solution methods, numerical as well as symbolical, to wider classes of transcendents (i.e. Painlev{\'e} transcendents) will be presented

rawtitle:
Invited Lecture: New ideas and results for solving Differential equations symbolically [abstract only]

entry:
@InProceedings{Fuchssteiner:2004:ILN,
  author =       "Benno Fuchssteiner",
  title =        "Invited Lecture: New ideas and results for solving
                 Differential equations symbolically [abstract only]",
  crossref =     "Frougny:2004:RCR",
  pages =        "5--5",
  year =         "2004",
  bibdate =      "Fri Nov 17 07:00:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_01_fuchssteiner.pdf",
  abstract =     "The lecture is a report on current research activities
                 of the MuPAD group in the area of symbolic and numeric
                 solutions of ODE (ordinary differential
                 equations).\par

                 Based on a unification of Lie-point-symmetries and
                 Lie--B{\"a}cklund-symmetries the results of classical
                 Lie-symmetry approaches (for example Liouville--Arnold)
                 to ODE are generalized thus opening new avenues for
                 using integrability (around initial values) for wider
                 classes of differential equations.\par

                 Applications and numerical consequences of these
                 results will be discussed and plans how to extend
                 current solution methods, numerical as well as
                 symbolical, to wider classes of transcendents (i.e.
                 Painlev{\'e} transcendents) will be presented",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Gaffar:2004:UBW
author: A. A. Gaffar and O. Mencer and W. Luk
title: Unifying bit-width optimisation for fixed-point and floating-point designs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 79--88
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: A. A. Gaffar and O. Mencer and W. Luk
rawtitle: Unifying bit-width optimisation for fixed-point and floating-point designs
booktitle:
FCCM 2004. 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 20--23 April 2004

abstract:
This paper presents a method that offers a uniform treatment for bit-width optimisation of both fixed-point and floating-point designs. Our work utilises automatic differentiation to compute the sensitivities of outputs to the bit-width of the various operands in the design. ldots 

rawabstract:
This paper presents a method that offers a uniform treatment for bit-width optimisation of both fixed-point and floating-point designs. Our work utilises automatic differentiation to compute the sensitivities of outputs to the bit-width of the various operands in the design. \ldots{}

rawbooktitle:
{FCCM 2004}. 12th Annual {IEEE} Symposium on Field-Programmable Custom Computing Machines, 20--23 April 2004

entry:
@InProceedings{Gaffar:2004:UBW,
  author =       "A. A. Gaffar and O. Mencer and W. Luk",
  booktitle =    "{FCCM 2004}. 12th Annual {IEEE} Symposium on
                 Field-Programmable Custom Computing Machines, 20--23
                 April 2004",
  title =        "Unifying bit-width optimisation for fixed-point and
                 floating-point designs",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "79--88",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents a method that offers a uniform
                 treatment for bit-width optimisation of both
                 fixed-point and floating-point designs. Our work
                 utilises automatic differentiation to compute the
                 sensitivities of outputs to the bit-width of the
                 various operands in the design. \ldots{}",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Gebali:2004:EAF
author: Fayez Gebali and Mohamed Watheq El-Kharashi
title: ERL: an algorithm for fast evaluation of exponential, reciprocal, and logarithmic functions
crossref: Wahdan:2004:IHE
pages: 269--272
year: 2004
bibdate: Sat Jul 16 18:04:58 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 18:04:58 MDT
acknowledgement: ack-nhfb
rawauthor: Fayez Gebali and Mohamed Watheq El-Kharashi
rawtitle: {ERL}: an algorithm for fast evaluation of exponential, reciprocal, and logarithmic functions
abstract:
A fast algorithm (ERL) is proposed for evaluating Exponential, Reciprocal, and Logarithmic functions. The algorithm requires two to three iterations to complete using simple operations such as multiply, accumulate, and table lookup. The algorithm is independent of the number format used by the machine. Thus it can be implemented using the IEEE 754 floating-point standard or any other special format used by special-purpose processors. The dynamic range of the algorithm is limited only by the dynamic range of the machine on which it is implemented Numerical simulations are performed which verifies the speed and accuracy of the algorithm.

rawabstract:
A fast algorithm (ERL) is proposed for evaluating Exponential, Reciprocal, and Logarithmic functions. The algorithm requires two to three iterations to complete using simple operations such as multiply, accumulate, and table lookup. The algorithm is independent of the number format used by the machine. Thus it can be implemented using the IEEE 754 floating-point standard or any other special format used by special-purpose processors. The dynamic range of the algorithm is limited only by the dynamic range of the machine on which it is implemented Numerical simulations are performed which verifies the speed and accuracy of the algorithm.

entry:
@InProceedings{Gebali:2004:EAF,
  author =       "Fayez Gebali and Mohamed Watheq El-Kharashi",
  title =        "{ERL}: an algorithm for fast evaluation of
                 exponential, reciprocal, and logarithmic functions",
  crossref =     "Wahdan:2004:IHE",
  pages =        "269--272",
  year =         "2004",
  bibdate =      "Sat Jul 16 18:04:58 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A fast algorithm (ERL) is proposed for evaluating
                 Exponential, Reciprocal, and Logarithmic functions. The
                 algorithm requires two to three iterations to complete
                 using simple operations such as multiply, accumulate,
                 and table lookup. The algorithm is independent of the
                 number format used by the machine. Thus it can be
                 implemented using the IEEE 754 floating-point standard
                 or any other special format used by special-purpose
                 processors. The dynamic range of the algorithm is
                 limited only by the dynamic range of the machine on
                 which it is implemented Numerical simulations are
                 performed which verifies the speed and accuracy of the
                 algorithm.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Gemignani:2004:REA
author: Luca Gemignani and Grazia Lotti
title: Rounding Error Analysis in Solving $M$-Matrix Linear Systems of Block Hessenberg Form
journal: j-NUMER-ALGORITHMS
volume: 36
number: 2
pages: 157--168
month: jun
monthnumber: 6
year: 2004
CODEN: NUALEG
ISSN: 1017-1398 (print), 1572-9265 (electronic) OR 10171398 (print), 15729265 (electronic)
ISSNL: 1017-1398 OR 10171398
bibdate: Mon Dec 6 07:00:32 MST 2004
bibsource: http://www.kluweronline.com/issn/1017-1398; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.12.06 07:00:32 MST
URL: http://ipsapp009.kluweronline.com/IPS/content/ext/x/J/5058/I/54/A/4/abstract.htm
fjournal: Numerical Algorithms
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11075
rawauthor: Luca Gemignani and Grazia Lotti
rawtitle: Rounding Error Analysis in Solving {$M$}-Matrix Linear Systems of Block {Hessenberg} Form
entry:
@Article{Gemignani:2004:REA,
  author =       "Luca Gemignani and Grazia Lotti",
  title =        "Rounding Error Analysis in Solving {$M$}-Matrix Linear
                 Systems of Block {Hessenberg} Form",
  journal =      j-NUMER-ALGORITHMS,
  volume =       "36",
  number =       "2",
  pages =        "157--168",
  month =        jun,
  year =         "2004",
  CODEN =        "NUALEG",
  ISSN =         "1017-1398 (print), 1572-9265 (electronic)",
  ISSN-L =       "1017-1398",
  bibdate =      "Mon Dec 6 07:00:32 MST 2004",
  bibsource =    "http://www.kluweronline.com/issn/1017-1398;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ipsapp009.kluweronline.com/IPS/content/ext/x/J/5058/I/54/A/4/abstract.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerical Algorithms",
  journal-URL =  "http://link.springer.com/journal/11075",
}


bibtype: article
filename: fparith.bib
label: Gerwig:2004:IEZ
title: The IBM eServer z990 floating-point unit
journal: j-IBM-JRD
volume: 48
number: 3/4
pages: 311--322
year: 2004
CODEN: IBMJAE
DOI: https://doi.org/10.1147/rd.483.0311
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Tue Sep 28 06:50:40 MDT 2004
bibsource: http://www.research.ibm.com/journal/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.09.28 06:50:40 MDT
fjournal: IBM Journal of Research and Development
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawtitle: The {IBM eServer z990} floating-point unit
author:
G. Gerwig and H. Wetter and E. M. Schwarz and J. Haess and C. A. Krygowski and B. M. Fleischer and M. Kroener

URL:
http://www.research.ibm.com/journal/rd/483/gerwig.html; http://www.research.ibm.com/journal/rd/483/gerwig.pdf

abstract:
The floating-point unit (FPU) of the IBM z990 eServer is the first one in an IBM mainframe with a fused multiply-add dataflow. It also represents the first time that an SRT divide algorithm (named after Sweeney, Robertson, and Tocher, who independently proposed the algorithm) was used in an IBM mainframe. The FPU supports dual architectures: the zSeries hexadecimal floating-point architecture and the IEEE 754 binary floating-point architecture. Six floating-point formats including short, long, and extended operands are supported in hardware. The throughput of this FPU is one multiply-add operation per cycle. The instructions are executed in five pipeline steps, and there are multiple provisions to avoid stalls in case of data dependencies. It is able to handle denormalized input operands and denormalized results without a stall (except for architectural program exceptions). It has a new extended-precision divide and square-root dataflow. This dataflow uses a radix-4 SRT algorithm (radix-2 for square root) and is able to handle divides and square-root operations in multiple floating-point and fixed-point formats. For fixed-point divisions, a new mechanism improves the performance by using an algorithm with which the number of divide iterations depends on the effective number of quotient bits.

rawabstract:
The floating-point unit (FPU) of the IBM z990 eServer is the first one in an IBM mainframe with a fused multiply-add dataflow. It also represents the first time that an SRT divide algorithm (named after Sweeney, Robertson, and Tocher, who independently proposed the algorithm) was used in an IBM mainframe. The FPU supports dual architectures: the zSeries hexadecimal floating-point architecture and the IEEE 754 binary floating-point architecture. Six floating-point formats including short, long, and extended operands are supported in hardware. The throughput of this FPU is one multiply-add operation per cycle. The instructions are executed in five pipeline steps, and there are multiple provisions to avoid stalls in case of data dependencies. It is able to handle denormalized input operands and denormalized results without a stall (except for architectural program exceptions). It has a new extended-precision divide and square-root dataflow. This dataflow uses a radix-4 SRT algorithm (radix-2 for square root) and is able to handle divides and square-root operations in multiple floating-point and fixed-point formats. For fixed-point divisions, a new mechanism improves the performance by using an algorithm with which the number of divide iterations depends on the effective number of quotient bits.

rawauthor:
G. Gerwig and H. Wetter and E. M. Schwarz and J. Haess and C. A. Krygowski and B. M. Fleischer and M. Kroener

entry:
@Article{Gerwig:2004:IEZ,
  author =       "G. Gerwig and H. Wetter and E. M. Schwarz and J. Haess
                 and C. A. Krygowski and B. M. Fleischer and M.
                 Kroener",
  title =        "The {IBM eServer z990} floating-point unit",
  journal =      j-IBM-JRD,
  volume =       "48",
  number =       "3/4",
  pages =        "311--322",
  month =        "????",
  year =         "2004",
  CODEN =        "IBMJAE",
  DOI =          "https://doi.org/10.1147/rd.483.0311",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Tue Sep 28 06:50:40 MDT 2004",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.research.ibm.com/journal/rd/483/gerwig.html;
                 http://www.research.ibm.com/journal/rd/483/gerwig.pdf",
  abstract =     "The floating-point unit (FPU) of the IBM z990 eServer
                 is the first one in an IBM mainframe with a fused
                 multiply-add dataflow. It also represents the first
                 time that an SRT divide algorithm (named after Sweeney,
                 Robertson, and Tocher, who independently proposed the
                 algorithm) was used in an IBM mainframe. The FPU
                 supports dual architectures: the zSeries hexadecimal
                 floating-point architecture and the IEEE 754 binary
                 floating-point architecture. Six floating-point formats
                 including short, long, and extended operands are
                 supported in hardware. The throughput of this FPU is
                 one multiply-add operation per cycle. The instructions
                 are executed in five pipeline steps, and there are
                 multiple provisions to avoid stalls in case of data
                 dependencies. It is able to handle denormalized input
                 operands and denormalized results without a stall
                 (except for architectural program exceptions). It has a
                 new extended-precision divide and square-root dataflow.
                 This dataflow uses a radix-4 SRT algorithm (radix-2 for
                 square root) and is able to handle divides and
                 square-root operations in multiple floating-point and
                 fixed-point formats. For fixed-point divisions, a new
                 mechanism improves the performance by using an
                 algorithm with which the number of divide iterations
                 depends on the effective number of quotient bits.",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "decimal floating-point arithmetic",
  ordernumber =  "G322-0240",
}


bibtype: article
filename: fparith.bib
label: Geyer:2004:DFD
author: Christina Lynn Geyer and Patricia Pepple Williamson
title: Detecting fraud in data sets using Benford's Law
journal: j-COMMUN-STAT-SIMUL-COMPUT
volume: B33
number: 1
pages: 229--246
year: 2004
CODEN: CSSCDB
DOI: https://doi.org/10.1081/SAC-120028442
ISSN: 0361-0918 OR 03610918
ISSNL: 0361-0918 OR 03610918
MRclass: 62-07
MRnumber: 2044866
bibdate: Sat Nov 12 09:13:23 2011
bibtimestamp: 2011.11.12 09:13:23 ???
fjournal: Communications in Statistics: Simulation and Computation
keywords: Benford's Law; Law of Anomalous Numbers; Zipf's Law
acknowledgement: ack-nhfb
ajournal: Comm. Statist. Simulation Comput.
journalURL: http://www.tandfonline.com/loi/lssp20
rawauthor: Christina Lynn Geyer and Patricia Pepple Williamson
rawtitle: Detecting fraud in data sets using {Benford's Law}
entry:
@Article{Geyer:2004:DFD,
  author =       "Christina Lynn Geyer and Patricia Pepple Williamson",
  title =        "Detecting fraud in data sets using {Benford's Law}",
  journal =      j-COMMUN-STAT-SIMUL-COMPUT,
  volume =       "B33",
  number =       "1",
  pages =        "229--246",
  month =        "????",
  year =         "2004",
  CODEN =        "CSSCDB",
  DOI =          "https://doi.org/10.1081/SAC-120028442",
  ISSN =         "0361-0918",
  ISSN-L =       "0361-0918",
  MRclass =      "62-07",
  MRnumber =     "2044866",
  bibdate =      "Sat Nov 12 09:13:23 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/benfords-law.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "Comm. Statist. Simulation Comput.",
  fjournal =     "Communications in Statistics: Simulation and
                 Computation",
  journal-URL =  "http://www.tandfonline.com/loi/lssp20",
  keywords =     "Benford's Law; Law of Anomalous Numbers; Zipf's Law",
}


bibtype: inproceedings
filename: fparith.bib
label: Gok:2004:DSP
author: M. Gok and M. J. Schulte and S. Krithivasan
booktitle: Proceedings of the Workshop on Application Specific Processors, Stockholm, Sweden, August, 2004
title: Designs for Subword-Parallel Multiplications and Dot Product Operations
pages: 27--31
year: 2004
bibdate: Sun Mar 04 20:51:24 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 20:51:24 ???
acknowledgement: ack-nhfb
rawauthor: M. Gok and M. J. Schulte and S. Krithivasan
rawbooktitle: Proceedings of the Workshop on Application Specific Processors, Stockholm, Sweden, August, 2004
rawtitle: Designs for Subword-Parallel Multiplications and Dot Product Operations
entry:
@InProceedings{Gok:2004:DSP,
  author =       "M. Gok and M. J. Schulte and S. Krithivasan",
  editor =       "????",
  booktitle =    "Proceedings of the Workshop on Application Specific
                 Processors, Stockholm, Sweden, August, 2004",
  title =        "Designs for Subword-Parallel Multiplications and Dot
                 Product Operations",
  publisher =    "????",
  address =      "????",
  pages =        "27--31",
  year =         "2004",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Sun Mar 04 20:51:24 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Govindu:2004:AHP
author: Gokul Govindu and L. Zhuo and S. Choi and V. Prasanna
booktitle: Proceedings. 18th International Parallel and Distributed Processing Symposium, 26--30 April 2004
title: Analysis of high-performance floating-point arithmetic on FPGAs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 149--149
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: Gokul Govindu and L. Zhuo and S. Choi and V. Prasanna
rawbooktitle: Proceedings. 18th International Parallel and Distributed Processing Symposium, 26--30 April 2004
rawtitle: Analysis of high-performance floating-point arithmetic on {FPGAs}
entry:
@InProceedings{Govindu:2004:AHP,
  author =       "Gokul Govindu and L. Zhuo and S. Choi and V.
                 Prasanna",
  booktitle =    "Proceedings. 18th International Parallel and
                 Distributed Processing Symposium, 26--30 April 2004",
  title =        "Analysis of high-performance floating-point arithmetic
                 on {FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "149--149",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Govindu:2004:HPE
author: G. Govindu and S. Choi and V. Prasanna and V. Daga and S. Gangadharpalli and V. Sridhar
booktitle: Proceedings. 18th International Parallel and Distributed Processing Symposium, 26--30 April 2004
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 149--149
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: G. Govindu and S. Choi and V. Prasanna and V. Daga and S. Gangadharpalli and V. Sridhar
rawbooktitle: Proceedings. 18th International Parallel and Distributed Processing Symposium, 26--30 April 2004
title:
A high-performance and energy-efficient architecture for floating-point based LU decomposition on FPGAs

rawtitle:
A high-performance and energy-efficient architecture for floating-point based {LU} decomposition on {FPGAs}

entry:
@InProceedings{Govindu:2004:HPE,
  author =       "G. Govindu and S. Choi and V. Prasanna and V. Daga and
                 S. Gangadharpalli and V. Sridhar",
  booktitle =    "Proceedings. 18th International Parallel and
                 Distributed Processing Symposium, 26--30 April 2004",
  title =        "A high-performance and energy-efficient architecture
                 for floating-point based {LU} decomposition on
                 {FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "149--149",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Graillat:2004:CRC
author: Stef Graillat and Philippe Langlois
title: A comparison of real and complex pseudozero sets for polynomials with real coefficients
crossref: Frougny:2004:RCR
pages: 103--112
year: 2004
MRclass: 65F35 68W30
bibdate: Fri Nov 17 07:00:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.17 07:00:31 ???
URL: http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_09_graillat.pdf
keywords: perturbation; polynomial root; pseudozero set; uncertainty
acknowledgement: ack-nhfb
rawauthor: Stef Graillat and Philippe Langlois
rawtitle: A comparison of real and complex pseudozero sets for polynomials with real coefficients
abstract:
Pseudozeros are useful to describe how perturbations of polynomial coefficients affect its zeros. We compare two types of pseudozero sets: the complex and the real pseudozero sets. These sets differ with respect to the type of perturbations. The first set --- complex perturbations of a complex polynomial --- has been intensively studied while the second one --- real perturbations of a real polynomial --- seems to have received no attention. We present a computable formula for the real pseudozero set and a comparison between these two pseudozero sets. We conclude that the complex pseudozero sets have to be preferred except when the perturbed real polynomials admit non-real zeros.

rawabstract:
Pseudozeros are useful to describe how perturbations of polynomial coefficients affect its zeros. We compare two types of pseudozero sets: the complex and the real pseudozero sets. These sets differ with respect to the type of perturbations. The first set --- complex perturbations of a complex polynomial --- has been intensively studied while the second one --- real perturbations of a real polynomial --- seems to have received no attention. We present a computable formula for the real pseudozero set and a comparison between these two pseudozero sets. We conclude that the complex pseudozero sets have to be preferred except when the perturbed real polynomials admit non-real zeros.

entry:
@InProceedings{Graillat:2004:CRC,
  author =       "Stef Graillat and Philippe Langlois",
  title =        "A comparison of real and complex pseudozero sets for
                 polynomials with real coefficients",
  crossref =     "Frougny:2004:RCR",
  pages =        "103--112",
  year =         "2004",
  MRclass =      "65F35 68W30",
  bibdate =      "Fri Nov 17 07:00:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_09_graillat.pdf",
  abstract =     "Pseudozeros are useful to describe how perturbations
                 of polynomial coefficients affect its zeros. We compare
                 two types of pseudozero sets: the complex and the real
                 pseudozero sets. These sets differ with respect to the
                 type of perturbations. The first set --- complex
                 perturbations of a complex polynomial --- has been
                 intensively studied while the second one --- real
                 perturbations of a real polynomial --- seems to have
                 received no attention. We present a computable formula
                 for the real pseudozero set and a comparison between
                 these two pseudozero sets. We conclude that the complex
                 pseudozero sets have to be preferred except when the
                 perturbed real polynomials admit non-real zeros.",
  acknowledgement = ack-nhfb,
  keywords =     "perturbation; polynomial root; pseudozero set;
                 uncertainty",
}


bibtype: manual
filename: fparith.bib
label: Granlund:2004:GMG
title: GNU MP: The GNU Multiple Precision Arithmetic Library
organization: pub-FSF
address: pub-FSF:adr
edition: Version 4.1.4
pages: iv + 127
day: 21
month: sep
monthnumber: 9
year: 2004
bibdate: Wed Nov 24 08:41:48 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.24 08:41:48 ???
URL: ftp://ftp.gnu.org/gnu/gmp/gmp-4.1.4.tar.gz; http://www.swox.se/gmp/
acknowledgement: ack-nhfb
rawtitle: {GNU MP}: The {GNU} Multiple Precision Arithmetic Library
author:
Torbjorn Granlund and Gunnar Sjodin and Hans Riesel and Richard Stallman and Brian Beuning and Doug Lea and John Amanatides and Paul Zimmermann and Ken Weber and Per Bothner and Joachim Hollman and Bennet Yee and Andreas Schwab and Robert Harley and David Seal and Robert Harley and Torsten Ekedahl and Paul Zimmermann and Linus Nordberg and Kent Boortz and Kevin Ryde and Steve Root and Gerardo Ballabio and Hans Thorsen

note:
GNUP MP development began in 1991. Earler versions are 1.0 (8-Aug-1991), 2.0 (24-Apr-1996), 3.0 (17-Apr-2000), and 4.0 (1-Dec-2001).

rawauthor:
Torbj{\"o}rn Granlund and Gunnar Sj{\"o}din and Hans Riesel and Richard Stallman and Brian Beuning and Doug Lea and John Amanatides and Paul Zimmermann and Ken Weber and Per Bothner and Joachim Hollman and Bennet Yee and Andreas Schwab and Robert Harley and David Seal and Robert Harley and Torsten Ekedahl and Paul Zimmermann and Linus Nordberg and Kent Boortz and Kevin Ryde and Steve Root and Gerardo Ballabio and Hans Thorsen

rawnote:
GNUP MP development began in 1991. Earler versions are 1.0 (8-Aug-1991), 2.0 (24-Apr-1996), 3.0 (17-Apr-2000), and 4.0 (1-Dec-2001).

entry:
@Manual{Granlund:2004:GMG,
  author =       "Torbj{\"o}rn Granlund and Gunnar Sj{\"o}din and Hans
                 Riesel and Richard Stallman and Brian Beuning and Doug
                 Lea and John Amanatides and Paul Zimmermann and Ken
                 Weber and Per Bothner and Joachim Hollman and Bennet
                 Yee and Andreas Schwab and Robert Harley and David Seal
                 and Robert Harley and Torsten Ekedahl and Paul
                 Zimmermann and Linus Nordberg and Kent Boortz and Kevin
                 Ryde and Steve Root and Gerardo Ballabio and Hans
                 Thorsen",
  title =        "{GNU MP}: The {GNU} Multiple Precision Arithmetic
                 Library",
  organization = pub-FSF,
  address =      pub-FSF:adr,
  edition =      "Version 4.1.4",
  pages =        "iv + 127",
  day =          "21",
  month =        sep,
  year =         "2004",
  bibdate =      "Wed Nov 24 08:41:48 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "GNUP MP development began in 1991. Earler versions are
                 1.0 (8-Aug-1991), 2.0 (24-Apr-1996), 3.0 (17-Apr-2000),
                 and 4.0 (1-Dec-2001).",
  URL =          "ftp://ftp.gnu.org/gnu/gmp/gmp-4.1.4.tar.gz;
                 http://www.swox.se/gmp/",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Groza:2004:DIS
author: V. Groza and M. Debski and D. Ionescu
title: Design and implementation of a self-calibrating floating-point analog-to-digital converter
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 707--710
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: V. Groza and M. Debski and D. Ionescu
rawtitle: Design and implementation of a self-calibrating floating-point analog-to-digital converter
booktitle:
IMTC 04. Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, 18--20 May 2004

abstract:
Floating point analog-to-digital converters (FP-ADC) are characterized by a high relative precision, but, in some applications, their absolute precision had to be traded off for speed. This paper presents the architecture, design and implementation of a self-calibrating differential predictive floating point analog-to-digital converter which is characterized by high conversion rates while its precision is kept at high values by additional hardware that periodically performs calibration cycles.ldots 

rawabstract:
Floating point analog-to-digital converters (FP-ADC) are characterized by a high relative precision, but, in some applications, their absolute precision had to be traded off for speed. This paper presents the architecture, design and implementation of a self-calibrating differential predictive floating point analog-to-digital converter which is characterized by high conversion rates while its precision is kept at high values by additional hardware that periodically performs calibration cycles.\ldots{}

rawbooktitle:
{IMTC 04}. Proceedings of the 21st {IEEE} Instrumentation and Measurement Technology Conference, 18--20 May 2004

entry:
@InProceedings{Groza:2004:DIS,
  author =       "V. Groza and M. Debski and D. Ionescu",
  booktitle =    "{IMTC 04}. Proceedings of the 21st {IEEE}
                 Instrumentation and Measurement Technology Conference,
                 18--20 May 2004",
  title =        "Design and implementation of a self-calibrating
                 floating-point analog-to-digital converter",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "707--710",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Floating point analog-to-digital converters (FP-ADC)
                 are characterized by a high relative precision, but, in
                 some applications, their absolute precision had to be
                 traded off for speed. This paper presents the
                 architecture, design and implementation of a
                 self-calibrating differential predictive floating point
                 analog-to-digital converter which is characterized by
                 high conversion rates while its precision is kept at
                 high values by additional hardware that periodically
                 performs calibration cycles.\ldots{}",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Hack:2004:IPR
author: Michel Hack
crossref: Frougny:2004:RCR
pages: 113--134
year: 2004
bibdate: Thu Apr 28 05:55:01 2022
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2022.04.28 05:55:01 ???
URL: http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_10_hack.pdf
remark: Improvement on cite Abbott:1999:ASS.
acknowledgement: ack-nhfb
rawauthor: Michel Hack
title:
On Intermediate Precision Required for Correctly-Rounding Decimal-to-Binary Floating-Point Conversion

abstract:
The algorithms developed ten years ago in preparation for IBM's support of IEEE Floating-Point on its mainframe S/390 processors use an overly conservative intermediate precision to guarantee correctly-rounded results across the entire exponent range. Here we study the minimal requirement for both bounded and unbounded precision on the decimal side (converting to machine precision on the binary side). An interesting new theorem on Continued Fraction expansions is offered, as well as an open problem on the growth of partial quotients for ratios of powers of two and five.

keywords:
base conversion; Continued Fractions; correct rounding; decimal floating-point arithmetic; Floating-Point conversion

rawabstract:
The algorithms developed ten years ago in preparation for IBM's support of IEEE Floating-Point on its mainframe S/390 processors use an overly conservative intermediate precision to guarantee correctly-rounded results across the entire exponent range. Here we study the minimal requirement for both bounded and unbounded precision on the decimal side (converting to machine precision on the binary side). An interesting new theorem on Continued Fraction expansions is offered, as well as an open problem on the growth of partial quotients for ratios of powers of two and five.

rawtitle:
On Intermediate Precision Required for Correctly-Rounding Decimal-to-Binary Floating-Point Conversion

entry:
@InProceedings{Hack:2004:IPR,
  author =       "Michel Hack",
  title =        "On Intermediate Precision Required for
                 Correctly-Rounding Decimal-to-Binary Floating-Point
                 Conversion",
  crossref =     "Frougny:2004:RCR",
  pages =        "113--134",
  year =         "2004",
  bibdate =      "Thu Apr 28 05:55:01 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_10_hack.pdf",
  abstract =     "The algorithms developed ten years ago in preparation
                 for IBM's support of IEEE Floating-Point on its
                 mainframe S/390 processors use an overly conservative
                 intermediate precision to guarantee correctly-rounded
                 results across the entire exponent range. Here we study
                 the minimal requirement for both bounded and unbounded
                 precision on the decimal side (converting to machine
                 precision on the binary side). An interesting new
                 theorem on Continued Fraction expansions is offered, as
                 well as an open problem on the growth of partial
                 quotients for ratios of powers of two and five.",
  acknowledgement = ack-nhfb,
  keywords =     "base conversion; Continued Fractions; correct
                 rounding; decimal floating-point arithmetic;
                 Floating-Point conversion",
  remark =       "Improvement on \cite{Abbott:1999:ASS}.",
}


bibtype: article
filename: fparith.bib
label: Hanrot:2004:MPA
author: Guillaume Hanrot and Michel Quercia and Paul Zimmermann
title: The Middle Product Algorithm I. Speeding up the division and square root of power series
journal: j-APPL-ALGEBRA-ENG-COMMUN-COMPUT
volume: 14
number: 6
pages: 415--438
month: mar
monthnumber: 3
year: 2004
CODEN: AAECEW
DOI: https://doi.org/10.1007/s00200-003-0144-2
ISSN: 0938-1279 (print), 1432-0622 (electronic) OR 09381279 (print), 14320622 (electronic)
ISSNL: 0938-1279 OR 09381279
bibdate: Sun Sep 10 08:12:01 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.09.10 08:12:01 ???
URL: http://springerlink.metapress.com/content/57p2fta5k71085wm/fulltext.pdf
fjournal: Applicable algebra in engineering, communication and computing
acknowledgement: ack-nhfb
rawauthor: Guillaume Hanrot and Michel Quercia and Paul Zimmermann
rawtitle: The Middle Product Algorithm {I}. Speeding up the division and square root of power series
abstract:
We present new algorithms for the inverse, division, and square root of power series. The key trick is a new algorithm --- MiddleProduct or, for short, MP --- computing the $n$ middle coefficients of a $ (2 n - 1) times n $ full product in the same number of multiplications as a full $ n times n $ product. This improves previous work of Brent, Mulders, Karp and Markstein, Burnikel and Ziegler. These results apply both to series and polynomials.

rawabstract:
We present new algorithms for the inverse, division, and square root of power series. The key trick is a new algorithm --- MiddleProduct or, for short, MP --- computing the $n$ middle coefficients of a $ (2 n - 1) \times n $ full product in the same number of multiplications as a full $ n \times n $ product. This improves previous work of Brent, Mulders, Karp and Markstein, Burnikel and Ziegler. These results apply both to series and polynomials.

entry:
@Article{Hanrot:2004:MPA,
  author =       "Guillaume Hanrot and Michel Quercia and Paul
                 Zimmermann",
  title =        "The Middle Product Algorithm {I}. Speeding up the
                 division and square root of power series",
  journal =      j-APPL-ALGEBRA-ENG-COMMUN-COMPUT,
  volume =       "14",
  number =       "6",
  pages =        "415--438",
  month =        mar,
  year =         "2004",
  CODEN =        "AAECEW",
  DOI =          "https://doi.org/10.1007/s00200-003-0144-2",
  ISSN =         "0938-1279 (print), 1432-0622 (electronic)",
  ISSN-L =       "0938-1279",
  bibdate =      "Sun Sep 10 08:12:01 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://springerlink.metapress.com/content/57p2fta5k71085wm/fulltext.pdf",
  abstract =     "We present new algorithms for the inverse, division,
                 and square root of power series. The key trick is a new
                 algorithm --- MiddleProduct or, for short, MP ---
                 computing the $n$ middle coefficients of a $ (2 n - 1)
                 \times n $ full product in the same number of
                 multiplications as a full $ n \times n $ product. This
                 improves previous work of Brent, Mulders, Karp and
                 Markstein, Burnikel and Ziegler. These results apply
                 both to series and polynomials.",
  acknowledgement = ack-nhfb,
  fjournal =     "Applicable algebra in engineering, communication and
                 computing",
}


bibtype: techreport
filename: fparith.bib
label: Hanrot:2004:NIR
author: Guillaume Hanrot and Paul Zimmermann
title: Newton Iteration Revisited
type: Technical Report
institution: inst-LORIA-INRIA-LORRAINE
address: inst-LORIA-INRIA-LORRAINE:adr
pages: 2
month: mar
monthnumber: 3
year: 2004
bibdate: Sun Sep 10 07:46:53 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.09.10 07:46:53 ???
note: See cite Bernstein:2004:RRH.
URL: http://www.loria.fr/~zimmerma/papers/fastnewton.ps.gz
acknowledgement: ack-nhfb
rawauthor: Guillaume Hanrot and Paul Zimmermann
rawnote: See \cite{Bernstein:2004:RRH}.
rawtitle: {Newton} Iteration Revisited
abstract:
On March 10, 2004, Dan Bernstein announced a revised draft of his paper em Removing redundancy in high-precision Newton iteration (path =http://cr.yp.to/fastnewton.html=) with algorithms that compute a reciprocal of order $n$ over $ C[[x]] 1.5 + o(1) $ times longer than a product; a quotient or logarithm $ 2.16666 ldots + o(1) $ times longer; a square root $ 1.83333 ldots + o(1) $ times longer; an exponential $ 2.83333 ldots + o(1) $ times longer. We give better algorithms.

remark:
Note added on March 24, 2004: the $ 1.5 + o(1) $ reciprocal algorithm was already published by Schonhage (tm Information Processing Letters 74, 2000, pp. 41--46).

rawabstract:
On March 10, 2004, Dan Bernstein announced a revised draft of his paper {\em Removing redundancy in high-precision Newton iteration} (\path=http://cr.yp.to/fastnewton.html=) with algorithms that compute a reciprocal of order $n$ over $ C[[x]] 1.5 + o(1) $ times longer than a product; a quotient or logarithm $ 2.16666 \ldots {} + o(1) $ times longer; a square root $ 1.83333 \ldots {} + o(1) $ times longer; an exponential $ 2.83333 \ldots {} + o(1) $ times longer. We give better algorithms.

entry:
@TechReport{Hanrot:2004:NIR,
  author =       "Guillaume Hanrot and Paul Zimmermann",
  title =        "{Newton} Iteration Revisited",
  type =         "Technical Report",
  institution =  inst-LORIA-INRIA-LORRAINE,
  address =      inst-LORIA-INRIA-LORRAINE:adr,
  pages =        "2",
  month =        mar,
  year =         "2004",
  bibdate =      "Sun Sep 10 07:46:53 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Bernstein:2004:RRH}.",
  URL =          "http://www.loria.fr/~zimmerma/papers/fastnewton.ps.gz",
  abstract =     "On March 10, 2004, Dan Bernstein announced a revised
                 draft of his paper {\em Removing redundancy in
                 high-precision Newton iteration}
                 (\path=http://cr.yp.to/fastnewton.html=) with
                 algorithms that compute a reciprocal of order $n$ over
                 $ C[[x]] 1.5 + o(1) $ times longer than a product; a
                 quotient or logarithm $ 2.16666 \ldots {} + o(1) $
                 times longer; a square root $ 1.83333 \ldots {} + o(1)
                 $ times longer; an exponential $ 2.83333 \ldots {} +
                 o(1) $ times longer. We give better algorithms.",
  acknowledgement = ack-nhfb,
  remark =       "Note added on March 24, 2004: the $ 1.5 + o(1) $
                 reciprocal algorithm was already published by
                 Sch{\"o}nhage ({\tm Information Processing Letters} 74,
                 2000, pp. 41--46).",
}


bibtype: article
filename: fparith.bib
label: Herbst:2004:RWS
author: Klaus-Dieter Herbst
title: Rezension: booktitle Wilhelm Schickard --- Briefwechsel von Friedrich Seck
journal: j-BER-WISSENSCHAFTGESCH
volume: 27
number: 4
pages: 315--317
month: dec
monthnumber: 12
year: 2004
CODEN: BEWID8
DOI: https://doi.org/10.1002/bewi.200490037
ISSN: 0170-6233 (print), 1522-2365 (electronic) OR 01706233 (print), 15222365 (electronic)
ISSNL: 0170-6233 OR 01706233
bibdate: Sun Aug 4 10:12:45 MDT 2013
bibtimestamp: 2013.08.04 10:12:45 MDT
fjournal: Berichte zur Wissenschaftsgeschichte
language: German
acknowledgement: ack-nhfb
ajournal: Ber. Wissenschaftgesch.
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1522-2365/
onlinedate: 3 Jan 2005
rawauthor: Klaus-Dieter Herbst
rawtitle: {Rezension: \booktitle{Wilhelm Schickard --- Briefwechsel} von Friedrich Seck}
bibsource:
https://www.math.utah.edu/pub/tex/bib/berwissenschaftgesch.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Herbst:2004:RWS,
  author =       "Klaus-Dieter Herbst",
  title =        "{Rezension: \booktitle{Wilhelm Schickard ---
                 Briefwechsel} von Friedrich Seck}",
  journal =      j-BER-WISSENSCHAFTGESCH,
  volume =       "27",
  number =       "4",
  pages =        "315--317",
  month =        dec,
  year =         "2004",
  CODEN =        "BEWID8",
  DOI =          "https://doi.org/10.1002/bewi.200490037",
  ISSN =         "0170-6233 (print), 1522-2365 (electronic)",
  ISSN-L =       "0170-6233",
  bibdate =      "Sun Aug 4 10:12:45 MDT 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/berwissenschaftgesch.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "{Ber. Wissenschaftgesch.}",
  fjournal =     "{Berichte zur Wissenschaftsgeschichte}",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1522-2365/",
  language =     "German",
  onlinedate =   "3 Jan 2005",
}


bibtype: article
filename: fparith.bib
label: Hiasat:2004:SFR
author: Ahmad A. Hiasat
journal: j-COMP-J
volume: 47
number: 1
pages: 93--??
month: jan
monthnumber: 1
year: 2004
CODEN: CMPJA6
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Thu Feb 26 06:22:27 2004
bibtimestamp: 2004.02.26 06:22:27 ???
fjournal: The Computer Journal
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
rawauthor: Ahmad A. Hiasat
title:
A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form $ (2 n - (2 p pm 1)) $

bibsource:
http://www3.oup.co.uk/computer_journal/hdb/Volume_47/Issue_01/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://www3.oup.co.uk/computer_journal/hdb/Volume_47/Issue_01/470093.sgm.abs.html; http://www3.oup.co.uk/computer_journal/hdb/Volume_47/Issue_01/pdf/470093.pdf

rawtitle:
A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form $ (2 n - (2 p \pm 1)) $

entry:
@Article{Hiasat:2004:SFR,
  author =       "Ahmad A. Hiasat",
  title =        "A Suggestion for a Fast Residue Multiplier for a
                 Family of Moduli of the Form $ (2 n - (2 p \pm 1)) $",
  journal =      j-COMP-J,
  volume =       "47",
  number =       "1",
  pages =        "93--??",
  month =        jan,
  year =         "2004",
  CODEN =        "CMPJA6",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Thu Feb 26 06:22:27 2004",
  bibsource =    "http://www3.oup.co.uk/computer_journal/hdb/Volume_47/Issue_01/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www3.oup.co.uk/computer_journal/hdb/Volume_47/Issue_01/470093.sgm.abs.html;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_47/Issue_01/pdf/470093.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
}


bibtype: article
filename: fparith.bib
label: Hormigo:2004:CPV
author: Javier Hormigo and Julio Villalba and Emilio L. Zapata
title: CORDIC Processor for Variable-Precision Interval Arithmetic
journal: j-J-VLSI-SIGNAL-PROC
volume: 37
number: 1
pages: 21--39
month: may
monthnumber: 5
year: 2004
CODEN: JVSPED
DOI: https://doi.org/10.1023/B:VLSI.0000017001.88149.f4
ISSN: 0922-5773 (print), 1573-109x (electronic) OR 09225773 (print), 1573109x (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Thu Aug 07 19:16:20 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 19:16:20 ???
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
rawauthor: Javier Hormigo and Julio Villalba and Emilio L. Zapata
rawtitle: {CORDIC} Processor for Variable-Precision Interval Arithmetic
abstract:
In this paper we present a specific CORDIC processor for variable-precision coordinates. This system allows us to specify the precision to perform the CORDIC operation, and control the accuracy of the result, in such a way that re-computation of inaccurate results can be carried out with higher precision. It permits a reliable and accurate evaluation of a wide range of elementary functions. The specific architecture designed greatly improves the computational time of previous solutions based on classic polynomial approximation. For controlling error in numerical computation (where intervals are normally narrow) the proposed design performs an interval operation in a time close to that of a point operation.

rawabstract:
In this paper we present a specific CORDIC processor for variable-precision coordinates. This system allows us to specify the precision to perform the CORDIC operation, and control the accuracy of the result, in such a way that re-computation of inaccurate results can be carried out with higher precision. It permits a reliable and accurate evaluation of a wide range of elementary functions. The specific architecture designed greatly improves the computational time of previous solutions based on classic polynomial approximation. For controlling error in numerical computation (where intervals are normally narrow) the proposed design performs an interval operation in a time close to that of a point operation.

entry:
@Article{Hormigo:2004:CPV,
  author =       "Javier Hormigo and Julio Villalba and Emilio L.
                 Zapata",
  title =        "{CORDIC} Processor for Variable-Precision Interval
                 Arithmetic",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "37",
  number =       "1",
  pages =        "21--39",
  month =        may,
  year =         "2004",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1023/B:VLSI.0000017001.88149.f4",
  ISSN =         "0922-5773 (print), 1573-109x (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Thu Aug 07 19:16:20 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper we present a specific CORDIC processor
                 for variable-precision coordinates. This system allows
                 us to specify the precision to perform the CORDIC
                 operation, and control the accuracy of the result, in
                 such a way that re-computation of inaccurate results
                 can be carried out with higher precision. It permits a
                 reliable and accurate evaluation of a wide range of
                 elementary functions. The specific architecture
                 designed greatly improves the computational time of
                 previous solutions based on classic polynomial
                 approximation. For controlling error in numerical
                 computation (where intervals are normally narrow) the
                 proposed design performs an interval operation in a
                 time close to that of a point operation.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of VLSI Signal Processing",
}


bibtype: manual
filename: fparith.bib
label: IBM:2004:ZAP
author: IBM
title: z/Architecture Principles of Operation
organization: IBM Corporation
address: Department 55JA Mail Station P384, 2455 South Road Poughkeepsie, NY, 12601-5400, USA
edition: Fourth
pages: xxvi + 1124
month: may
monthnumber: 5
year: 2004
bibdate: Sat Mar 11 17:19:27 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.03.11 17:19:27 ???
note: IBM order number SA22-7832-03.
URL: http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/download/DZ9ZR003.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: {IBM}
rawnote: IBM order number SA22-7832-03.
rawtitle: {z/Architecture} Principles of Operation
remark:
This manual continues a tradition of that began with the publication in 1964 of the IBM System/360 Principles of Operation, long considered a classic and a landmark description of the oldest computer architecture in continuous use. Chapter 9 provides an overview of the floating-point support, Chapter 18 describes the hexadecimal floating-point instructions, and Chapter 19 the binary (IEEE 754) floating-point instructions. Both hexadecimal and binary sets support 32-bit, 64-bit, and 128-bit formats, all in hardware on the IBM G5 processors. However, the recently-implemented decimal floating-point arithmetic is not described in this edition.

entry:
@Manual{IBM:2004:ZAP,
  author =       "{IBM}",
  title =        "{z/Architecture} Principles of Operation",
  organization = "IBM Corporation",
  address =      "Department 55JA Mail Station P384, 2455 South Road
                 Poughkeepsie, NY, 12601-5400, USA",
  edition =      "Fourth",
  pages =        "xxvi + 1124",
  month =        may,
  year =         "2004",
  bibdate =      "Sat Mar 11 17:19:27 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "IBM order number SA22-7832-03.",
  URL =          "http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/download/DZ9ZR003.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
  remark =       "This manual continues a tradition of that began with
                 the publication in 1964 of the IBM System/360
                 Principles of Operation, long considered a classic and
                 a landmark description of the oldest computer
                 architecture in continuous use. Chapter 9 provides an
                 overview of the floating-point support, Chapter 18
                 describes the hexadecimal floating-point instructions,
                 and Chapter 19 the binary (IEEE 754) floating-point
                 instructions. Both hexadecimal and binary sets support
                 32-bit, 64-bit, and 128-bit formats, all in hardware on
                 the IBM G5 processors. However, the
                 recently-implemented decimal floating-point arithmetic
                 is not described in this edition.",
}


bibtype: article
filename: fparith.bib
label: Jeong:2004:CEP
author: Jong-Chul Jeong and Woo-Chan Park and Woong Jeong and Tack-Don Han and Moon-Key Lee
title: A cost-effective pipelined divider with a small lookup table
journal: j-IEEE-TRANS-COMPUT
volume: 53
number: 4
pages: 489--495
month: apr
monthnumber: 4
year: 2004
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2004.1268407
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 08:12:35 MDT 2011
bibtimestamp: 2011.07.05 08:12:35 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1268407
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Jong-Chul Jeong and Woo-Chan Park and Woong Jeong and Tack-Don Han and Moon-Key Lee
rawtitle: A cost-effective pipelined divider with a small lookup table
entry:
@Article{Jeong:2004:CEP,
  author =       "Jong-Chul Jeong and Woo-Chan Park and Woong Jeong and
                 Tack-Don Han and Moon-Key Lee",
  title =        "A cost-effective pipelined divider with a small lookup
                 table",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "53",
  number =       "4",
  pages =        "489--495",
  month =        apr,
  year =         "2004",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2004.1268407",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 08:12:35 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1268407",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: misc
filename: fparith.bib
label: Kahan:2004:CFP
author: W. Kahan
title: On the Cost of Floating-Point Computation Without Extra-Precise Arithmetic
pages: 21
day: 20
month: nov
monthnumber: 11
year: 2004
bibdate: Mon Apr 25 17:44:03 2005
bibtimestamp: 2005.04.25 17:44:03 ???
URL: http://www.cs.berkeley.edu/~wkahan/Qdrtcs.pdf
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: W. Kahan
rawtitle: On the Cost of Floating-Point Computation Without Extra-Precise Arithmetic
note:
See cite Boldo:2009:KAC for a proof of this algorithm for accurate computation of the discriminant needed for the solution of quadratic equations.

rawnote:
See \cite{Boldo:2009:KAC} for a proof of this algorithm for accurate computation of the discriminant needed for the solution of quadratic equations.

entry:
@Misc{Kahan:2004:CFP,
  author =       "W. Kahan",
  title =        "On the Cost of Floating-Point Computation Without
                 Extra-Precise Arithmetic",
  howpublished = "World-Wide Web document",
  pages =        "21",
  day =          "20",
  month =        nov,
  year =         "2004",
  bibdate =      "Mon Apr 25 17:44:03 2005",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Boldo:2009:KAC} for a proof of this
                 algorithm for accurate computation of the discriminant
                 needed for the solution of quadratic equations.",
  URL =          "http://www.cs.berkeley.edu/~wkahan/Qdrtcs.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Kahan:2004:HFM
author: W. Kahan
title: How Futile are Mindless Assessments of Roundoff in Floating-Point Computation?
pages: 37
day: 1
month: nov
monthnumber: 11
year: 2004
bibdate: Mon Apr 25 17:41:28 2005
bibtimestamp: 2005.04.25 17:41:28 ???
URL: http://www.cs.berkeley.edu/~wkahan/Mind1ess.pdf; http://www.cs.berkeley.edu/~wkahan/Mindless.pdf
keywords: floating-point arithmetic; rounding errors
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: W. Kahan
rawtitle: How Futile are Mindless Assessments of Roundoff in Floating-Point Computation?
entry:
@Misc{Kahan:2004:HFM,
  author =       "W. Kahan",
  title =        "How Futile are Mindless Assessments of Roundoff in
                 Floating-Point Computation?",
  howpublished = "World-Wide Web document",
  pages =        "37",
  day =          "1",
  month =        nov,
  year =         "2004",
  bibdate =      "Mon Apr 25 17:41:28 2005",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.berkeley.edu/~wkahan/Mind1ess.pdf;
                 http://www.cs.berkeley.edu/~wkahan/Mindless.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point arithmetic; rounding errors",
}


bibtype: misc
filename: fparith.bib
label: Kahan:2004:SSR
author: W. Kahan
title: $ 128 $ Squares of $ 128 $ Square Roots
pages: 3
day: 29
month: jan
monthnumber: 1
year: 2004
bibdate: Mon Apr 25 18:25:57 2005
bibtimestamp: 2005.04.25 18:25:57 ???
note: Lecture notes for Math 128.
URL: http://www.cs.berkeley.edu/~wkahan/Math128/SqSqrts.pdf
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: W. Kahan
rawnote: Lecture notes for Math 128.
rawtitle: $ 128 $ Squares of $ 128 $ Square Roots
entry:
@Misc{Kahan:2004:SSR,
  author =       "W. Kahan",
  title =        "$ 128 $ Squares of $ 128 $ Square Roots",
  howpublished = "World-Wide Web document",
  pages =        "3",
  day =          "29",
  month =        jan,
  year =         "2004",
  bibdate =      "Mon Apr 25 18:25:57 2005",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Lecture notes for Math 128.",
  URL =          "http://www.cs.berkeley.edu/~wkahan/Math128/SqSqrts.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kahn:2004:CEA
author: Ken Kahn
title: The child-engineering of arithmetic in ToonTalk
crossref: Druin:2004:IDC
pages: 141--142
year: 2004
DOI: https://doi.org/10.1145/1017833.1017860
bibdate: Fri Aug 08 09:04:34 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.08 09:04:34 ???
acknowledgement: ack-nhfb
rawauthor: Ken Kahn
rawtitle: The child-engineering of arithmetic in {ToonTalk}
abstract:
Providing a child-appropriate interface to an arithmetic package with large numbers and exact fractions is surprisingly challenging. We discuss solutions to problems ranging from how to present fractions such as 1/3 to how to deal with numbers with tens of thousands of digits. As with other objects in ToonTalk, we strive to make the enhanced numbers work in a concrete and playful manner.

rawabstract:
Providing a child-appropriate interface to an arithmetic package with large numbers and exact fractions is surprisingly challenging. We discuss solutions to problems ranging from how to present fractions such as 1/3 to how to deal with numbers with tens of thousands of digits. As with other objects in ToonTalk, we strive to make the enhanced numbers work in a concrete and playful manner.

entry:
@InProceedings{Kahn:2004:CEA,
  author =       "Ken Kahn",
  title =        "The child-engineering of arithmetic in {ToonTalk}",
  crossref =     "Druin:2004:IDC",
  pages =        "141--142",
  year =         "2004",
  DOI =          "https://doi.org/10.1145/1017833.1017860",
  bibdate =      "Fri Aug 08 09:04:34 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Providing a child-appropriate interface to an
                 arithmetic package with large numbers and exact
                 fractions is surprisingly challenging. We discuss
                 solutions to problems ranging from how to present
                 fractions such as 1/3 to how to deal with numbers with
                 tens of thousands of digits. As with other objects in
                 ToonTalk, we strive to make the enhanced numbers work
                 in a concrete and playful manner.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kenney:2004:HFD
author: R. D. Kenney and M. J. Schulte and M. A. Erle
title: A high-frequency decimal multiplier
crossref: IEEE:2004:IICa
pages: 26--29
year: 2004
bibdate: Fri Mar 25 05:54:22 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.03.25 05:54:22 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2004-05.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: R. D. Kenney and M. J. Schulte and M. A. Erle
rawtitle: A high-frequency decimal multiplier
abstract:
Decimal arithmetic is regaining popularity in the computing community due to the growing importance of commercial, financial, and Internet-based applications, which process decimal data. This paper presents an iterative decimal multiplier, which is operates at high clock frequencies and scales well to large operand sizes. The multiplier uses a new decimal representation for intermediate products, which allows for a very fast two- stage iterative multiplier design. Decimal multipliers, which are synthesized using a 0.11 micron CMOS standard cell library, operate at clock frequencies close to 2 GHz. The latency of the proposed design to multiply two n-digit BCD operands is $ (n + 8) $ cycles with a new multiplication able to begin every $ (n + 1) $ cycles.

rawabstract:
Decimal arithmetic is regaining popularity in the computing community due to the growing importance of commercial, financial, and Internet-based applications, which process decimal data. This paper presents an iterative decimal multiplier, which is operates at high clock frequencies and scales well to large operand sizes. The multiplier uses a new decimal representation for intermediate products, which allows for a very fast two- stage iterative multiplier design. Decimal multipliers, which are synthesized using a 0.11 micron CMOS standard cell library, operate at clock frequencies close to 2 GHz. The latency of the proposed design to multiply two n-digit BCD operands is $ (n + 8) $ cycles with a new multiplication able to begin every $ (n + 1) $ cycles.

entry:
@InProceedings{Kenney:2004:HFD,
  author =       "R. D. Kenney and M. J. Schulte and M. A. Erle",
  title =        "A high-frequency decimal multiplier",
  crossref =     "IEEE:2004:IICa",
  pages =        "26--29",
  year =         "2004",
  bibdate =      "Fri Mar 25 05:54:22 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2004-05.pdf",
  abstract =     "Decimal arithmetic is regaining popularity in the
                 computing community due to the growing importance of
                 commercial, financial, and Internet-based applications,
                 which process decimal data. This paper presents an
                 iterative decimal multiplier, which is operates at high
                 clock frequencies and scales well to large operand
                 sizes. The multiplier uses a new decimal representation
                 for intermediate products, which allows for a very fast
                 two- stage iterative multiplier design. Decimal
                 multipliers, which are synthesized using a 0.11 micron
                 CMOS standard cell library, operate at clock
                 frequencies close to 2 GHz. The latency of the proposed
                 design to multiply two n-digit BCD operands is $ (n +
                 8) $ cycles with a new multiplication able to begin
                 every $ (n + 1) $ cycles.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Kenney:2004:MDA
author: Robert D. Kenney and Michael J. Schulte and Mark A. Erle
title: Multioperand Decimal Addition
crossref: Smailagic:2004:ETV
pages: 251--253
year: 2004
bibdate: Wed May 04 07:51:51 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.05.04 07:51:51 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2004-07.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Robert D. Kenney and Michael J. Schulte and Mark A. Erle
rawtitle: Multioperand Decimal Addition
abstract:
This paper introduces and analyzes four techniques for performing fast decimal addition on multiple binary coded decimal (BCD) operands. Three of the techniques speculate BCD correction values and use chaining to correct intermediate results. The first speculates over one addition. The second speculates over two additions. The third employs multiple instances of the second technique in parallel and then merges the results. The fourth technique uses a binary carry-save adder tree and produces a binary sum. Combinational logic is then used to correct the sum and determine the carry into the next digit. Multioperand adder designs are constructed and synthesized for four to sixteen input operands. Analyses are performed on the synthesis results and the merits of each technique are discussed. Finally, these techniques are compared to previous attempts made at speeding up decimal addition.

rawabstract:
This paper introduces and analyzes four techniques for performing fast decimal addition on multiple binary coded decimal (BCD) operands. Three of the techniques speculate BCD correction values and use chaining to correct intermediate results. The first speculates over one addition. The second speculates over two additions. The third employs multiple instances of the second technique in parallel and then merges the results. The fourth technique uses a binary carry-save adder tree and produces a binary sum. Combinational logic is then used to correct the sum and determine the carry into the next digit. Multioperand adder designs are constructed and synthesized for four to sixteen input operands. Analyses are performed on the synthesis results and the merits of each technique are discussed. Finally, these techniques are compared to previous attempts made at speeding up decimal addition.

entry:
@InProceedings{Kenney:2004:MDA,
  author =       "Robert D. Kenney and Michael J. Schulte and Mark A.
                 Erle",
  title =        "Multioperand Decimal Addition",
  crossref =     "Smailagic:2004:ETV",
  pages =        "251--253",
  year =         "2004",
  bibdate =      "Wed May 04 07:51:51 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2004-07.pdf",
  abstract =     "This paper introduces and analyzes four techniques for
                 performing fast decimal addition on multiple binary
                 coded decimal (BCD) operands. Three of the techniques
                 speculate BCD correction values and use chaining to
                 correct intermediate results. The first speculates over
                 one addition. The second speculates over two additions.
                 The third employs multiple instances of the second
                 technique in parallel and then merges the results. The
                 fourth technique uses a binary carry-save adder tree
                 and produces a binary sum. Combinational logic is then
                 used to correct the sum and determine the carry into
                 the next digit. Multioperand adder designs are
                 constructed and synthesized for four to sixteen input
                 operands. Analyses are performed on the synthesis
                 results and the merits of each technique are discussed.
                 Finally, these techniques are compared to previous
                 attempts made at speeding up decimal addition.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
  pagecount =    "10",
}


bibtype: article
filename: fparith.bib
label: Kim:2004:AAA
author: Hyun-Sung Kim and Kee-Young Yoo
title: AOP arithmetic architectures over $ mathrm GF(2^m) $
journal: j-APPL-MATH-COMP
volume: 158
number: 1
pages: 7--18
day: 25
month: oct
monthnumber: 10
year: 2004
CODEN: AMHCBQ
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Mon Jul 4 09:15:36 MDT 2005
bibtimestamp: 2005.07.04 09:15:36 MDT
fjournal: Applied Mathematics and Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: Hyun-Sung Kim and Kee-Young Yoo
rawtitle: {AOP} arithmetic architectures over {$ \mathrm {GF}(2^m) $}
bibsource:
http://www.sciencedirect.com/science/journal/00963003; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Kim:2004:AAA,
  author =       "Hyun-Sung Kim and Kee-Young Yoo",
  title =        "{AOP} arithmetic architectures over {$ \mathrm
                 {GF}(2^m) $}",
  journal =      j-APPL-MATH-COMP,
  volume =       "158",
  number =       "1",
  pages =        "7--18",
  day =          "25",
  month =        oct,
  year =         "2004",
  CODEN =        "AMHCBQ",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Mon Jul 4 09:15:36 MDT 2005",
  bibsource =    "http://www.sciencedirect.com/science/journal/00963003;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
}


bibtype: article
filename: fparith.bib
label: Ko:2004:CCF
author: Sangho Ko and Robert R. Bitmead
title: Covariance calculation for floating-point state-space realizations
journal: j-IEEE-TRANS-SIG-PROC
volume: 52
number: 12
pages: 3370--3377
month: dec
monthnumber: 12
year: 2004
CODEN: ITPRED
ISSN: 1053-587X (print), 1941-0476 (electronic) OR 1053587X (print), 19410476 (electronic)
ISSNL: 1053-587X OR 1053587X
MRclass: 93B15 (94A12)
MRnumber: MR2107918 (2005h:93033)
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Signal Processing
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78
rawauthor: Sangho Ko and Robert R. Bitmead
rawtitle: Covariance calculation for floating-point state-space realizations
abstract:
This paper provides a new method for analyzing floating-point roundoff error for digital filters by using ``finite signal-to-noise'' models whose noise sources have variances proportional to the variance or power of the corrupted signals.

rawabstract:
This paper provides a new method for analyzing floating-point roundoff error for digital filters by using ``finite signal-to-noise'' models whose noise sources have variances proportional to the variance or power of the corrupted signals.

entry:
@Article{Ko:2004:CCF,
  author =       "Sangho Ko and Robert R. Bitmead",
  title =        "Covariance calculation for floating-point state-space
                 realizations",
  journal =      j-IEEE-TRANS-SIG-PROC,
  volume =       "52",
  number =       "12",
  pages =        "3370--3377",
  month =        dec,
  year =         "2004",
  CODEN =        "ITPRED",
  ISSN =         "1053-587X (print), 1941-0476 (electronic)",
  ISSN-L =       "1053-587X",
  MRclass =      "93B15 (94A12)",
  MRnumber =     "MR2107918 (2005h:93033)",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper provides a new method for analyzing
                 floating-point roundoff error for digital filters by
                 using ``finite signal-to-noise'' models whose noise
                 sources have variances proportional to the variance or
                 power of the corrupted signals.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Signal Processing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=78",
  summary =      "This paper provides a new method for analyzing
                 floating-point roundoff error for digital filters by
                 using ``finite signal-to-noise'' models whose noise
                 sources have variances proportional to the variance or
                 power of the corrupted signals. With this model
                 \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Kobayashi:2004:SHC
author: S. Kobayashi and I. Kozuka and W. H. Tang and D. Landmann
title: A software / hardware codesigned hands free system on a ``resizable'' block-floating-point DSP
crossref: IEEE:2004:IICc
volume: 5
pages: V-149--V-152
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: S. Kobayashi and I. Kozuka and W. H. Tang and D. Landmann
rawtitle:
A software\slash hardware codesigned hands free system on a ``resizable'' block-floating-point {DSP}

entry:
@InProceedings{Kobayashi:2004:SHC,
  author =       "S. Kobayashi and I. Kozuka and W. H. Tang and D.
                 Landmann",
  title =        "A software\slash hardware codesigned hands free system
                 on a ``resizable'' block-floating-point {DSP}",
  crossref =     "IEEE:2004:IICc",
  volume =       "5",
  pages =        "V-149--V-152",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Kornerup:2004:RCN
author: Peter Kornerup and Jean-Michel Muller
title: RN-coding of numbers: definition and some properties
type: Research Report
number: RR2004-43
institution: Ecole Normale Superieure de Lyon
address: 69364 Lyon Cedex 07, France
pages: 2 + 9
month: sep
monthnumber: 9
year: 2004
bibdate: Mon Dec 06 11:09:46 2004
bibsource: http://www.ens-lyon.fr/LIP/Pub/rr2004.php; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.12.06 11:09:46 ???
URL: http://www.ens-lyon.fr/LIP/Pub/Rapports/RR/RR2004/RR2004-43.pdf
keywords: Computer arithmetic; number systems
acknowledgement: ack-nhfb
rawauthor: Peter Kornerup and Jean-Michel Muller
rawtitle: {RN}-coding of numbers: definition and some properties
abstract:
We define RN-codings as radix-$ beta $ signed representations of numbers for which rounding to the nearest is always identical to truncation. After giving characterizations of such representations, we investigate some of their properties, and we suggest algorithms for conversion to and from these codings.

rawabstract:
We define RN-codings as radix-$ \beta $ signed representations of numbers for which rounding to the nearest is always identical to truncation. After giving characterizations of such representations, we investigate some of their properties, and we suggest algorithms for conversion to and from these codings.

entry:
@TechReport{Kornerup:2004:RCN,
  author =       "Peter Kornerup and Jean-Michel Muller",
  title =        "{RN}-coding of numbers: definition and some
                 properties",
  type =         "Research Report",
  number =       "RR2004-43",
  institution =  "{\'E}cole Normale Sup{\'e}rieure de Lyon",
  address =      "69364 Lyon Cedex 07, France",
  pages =        "2 + 9",
  month =        sep,
  year =         "2004",
  bibdate =      "Mon Dec 06 11:09:46 2004",
  bibsource =    "http://www.ens-lyon.fr/LIP/Pub/rr2004.php;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.ens-lyon.fr/LIP/Pub/Rapports/RR/RR2004/RR2004-43.pdf",
  abstract =     "We define RN-codings as radix-$ \beta $ signed
                 representations of numbers for which rounding to the
                 nearest is always identical to truncation. After giving
                 characterizations of such representations, we
                 investigate some of their properties, and we suggest
                 algorithms for conversion to and from these codings.",
  acknowledgement = ack-nhfb,
  keywords =     "Computer arithmetic; number systems",
}


bibtype: inproceedings
filename: fparith.bib
label: Krithivasan:2004:SPM
author: S. Krithivasan and M. J. Schulte and J. Glossner
title: A Subword-Parallel Multiplication and Sum-of-Squares Unit
crossref: Smailagic:2004:ETV
pages: 273--274
year: 2004
bibdate: Sun Mar 04 20:59:11 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 20:59:11 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2004-03.pdf
acknowledgement: ack-nhfb
rawauthor: S. Krithivasan and M. J. Schulte and J. Glossner
rawtitle: A Subword-Parallel Multiplication and Sum-of-Squares Unit
entry:
@InProceedings{Krithivasan:2004:SPM,
  author =       "S. Krithivasan and M. J. Schulte and J. Glossner",
  title =        "A Subword-Parallel Multiplication and Sum-of-Squares
                 Unit",
  crossref =     "Smailagic:2004:ETV",
  pages =        "273--274",
  year =         "2004",
  bibdate =      "Sun Mar 04 20:59:11 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2004-03.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Krueger:2004:DLI
author: S. D. Krueger and P.-M. Seidel
title: Design of an on-line IEEE floating-point addition unit for FPGAs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 239--246
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: S. D. Krueger and P.-M. Seidel
rawtitle: Design of an on-line {IEEE} floating-point addition unit for {FPGAs}
booktitle:
FCCM 2004. 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 20--23 April 2004

abstract:
We present the design of an on-line IEEE floating-point (FP) adder. In on-line arithmetic a result is computed as a digit serial output stream from digit serial input streams. The result digits begin to be produced a short delay after the first input arrive and before all the input digits have been received. ldots 

rawabstract:
We present the design of an on-line IEEE floating-point (FP) adder. In on-line arithmetic a result is computed as a digit serial output stream from digit serial input streams. The result digits begin to be produced a short delay after the first input arrive and before all the input digits have been received. \ldots{}

rawbooktitle:
{FCCM 2004}. 12th Annual {IEEE} Symposium on Field-Programmable Custom Computing Machines, 20--23 April 2004

entry:
@InProceedings{Krueger:2004:DLI,
  author =       "S. D. Krueger and P.-M. Seidel",
  booktitle =    "{FCCM 2004}. 12th Annual {IEEE} Symposium on
                 Field-Programmable Custom Computing Machines, 20--23
                 April 2004",
  title =        "Design of an on-line {IEEE} floating-point addition
                 unit for {FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "239--246",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present the design of an on-line IEEE
                 floating-point (FP) adder. In on-line arithmetic a
                 result is computed as a digit serial output stream from
                 digit serial input streams. The result digits begin to
                 be produced a short delay after the first input arrive
                 and before all the input digits have been received.
                 \ldots{}",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kwon:2004:SMI
author: Taek-Jun Kwon and Joong-Seok Moon and J. Sondeen and J. Draper
booktitle: ISCAS '04. Proceedings of the 2004 International Symposium on Circuits and Systems, 23--26 May 2004
title: A 0.18 /spl $ mu $ /m implementation of a floating-point unit for a processing-in-memory system
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: II-453--II-456
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: Taek-Jun Kwon and Joong-Seok Moon and J. Sondeen and J. Draper
rawtitle: A 0.18 /spl $ \mu $ /m implementation of a floating-point unit for a processing-in-memory system
rawbooktitle:
{ISCAS '04}. Proceedings of the 2004 International Symposium on Circuits and Systems, 23--26 May 2004

entry:
@InProceedings{Kwon:2004:SMI,
  author =       "Taek-Jun Kwon and Joong-Seok Moon and J. Sondeen and
                 J. Draper",
  booktitle =    "{ISCAS '04}. Proceedings of the 2004 International
                 Symposium on Circuits and Systems, 23--26 May 2004",
  title =        "A 0.18 /spl $ \mu $ /m implementation of a
                 floating-point unit for a processing-in-memory system",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "II-453--II-456",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Lang:2004:FPM
author: T. Lang and J. D. Bruguera
title: Floating-point multiply-add-fused with reduced latency
journal: j-IEEE-TRANS-COMPUT
volume: 53
number: 8
pages: 988--1003
month: aug
monthnumber: 8
year: 2004
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2004.44
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 08:12:40 MDT 2011
bibtimestamp: 2011.07.05 08:12:40 MDT
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: T. Lang and J. D. Bruguera
rawtitle: Floating-point multiply-add-fused with reduced latency
URL:
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1306992; http://www.ac.usc.es/arquivos/articulos/2004/gac2004-j06.ps

abstract:
We propose architecture for the computation of the double-precision floating-point multiply-add-fused (MAP) operation $ A + (B times C) $. This architecture is based on the combined addition and rounding (using a dual adder) and in the anticipation of the normalization step before the addition. Because the normalization is performed before the addition, it is not possible to overlap the leading-zero-anticipator with the adder. Consequently, to avoid the increase in delay, we modify the design of the LZA so that the leading bits of its output are produced first and can be used to begin the normalization. Moreover, parts of the addition are also anticipated. We have estimated the delay of the resulting architecture considering the load introduced by long connections, and we estimate a delay reduction of between 15 percent and 20 percent, with respect to previous implementations.

rawabstract:
We propose architecture for the computation of the double-precision floating-point multiply-add-fused (MAP) operation $ A + (B \times C) $. This architecture is based on the combined addition and rounding (using a dual adder) and in the anticipation of the normalization step before the addition. Because the normalization is performed before the addition, it is not possible to overlap the leading-zero-anticipator with the adder. Consequently, to avoid the increase in delay, we modify the design of the LZA so that the leading bits of its output are produced first and can be used to begin the normalization. Moreover, parts of the addition are also anticipated. We have estimated the delay of the resulting architecture considering the load introduced by long connections, and we estimate a delay reduction of between 15 percent and 20 percent, with respect to previous implementations.

entry:
@Article{Lang:2004:FPM,
  author =       "T. Lang and J. D. Bruguera",
  title =        "Floating-point multiply-add-fused with reduced
                 latency",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "53",
  number =       "8",
  pages =        "988--1003",
  month =        aug,
  year =         "2004",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2004.44",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 08:12:40 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1306992;
                 http://www.ac.usc.es/arquivos/articulos/2004/gac2004-j06.ps",
  abstract =     "We propose architecture for the computation of the
                 double-precision floating-point multiply-add-fused
                 (MAP) operation $ A + (B \times C) $. This architecture
                 is based on the combined addition and rounding (using a
                 dual adder) and in the anticipation of the
                 normalization step before the addition. Because the
                 normalization is performed before the addition, it is
                 not possible to overlap the leading-zero-anticipator
                 with the adder. Consequently, to avoid the increase in
                 delay, we modify the design of the LZA so that the
                 leading bits of its output are produced first and can
                 be used to begin the normalization. Moreover, parts of
                 the addition are also anticipated. We have estimated
                 the delay of the resulting architecture considering the
                 load introduced by long connections, and we estimate a
                 delay reduction of between 15 percent and 20 percent,
                 with respect to previous implementations.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "We propose architecture for the computation of the
                 double-precision floating-point multiply-add-fused
                 (MAP) operation A + (B $\times$ C). This architecture
                 is based on the combined addition and rounding (using a
                 dual adder) and in the anticipation \ldots{}",
}


bibtype: techreport
filename: fparith.bib
label: Lefevre:2004:AFF
author: Vincent Lefevre and Paul Zimmermann
title: Arithmetique flottante. (French) [Floating-point arithmetic]
type: Technical Report
institution: inst-LORIA-INRIA-LORRAINE
address: inst-LORIA-INRIA-LORRAINE:adr
pages: 60
month: feb
monthnumber: 2
year: 2004
bibdate: Sun Sep 10 08:03:11 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.09.10 08:03:11 ???
keywords: arbitrary precision; correct rounding; fixed precision; floating-point number; IEEE 754 standard
language: French
acknowledgement: ack-nhfb
rawauthor: Vincent Lef{\`e}vre and Paul Zimmermann
rawtitle: Arithm{\'e}tique flottante. ({French}) [{Floating-point} arithmetic]
URL:
ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-5105.pdf; ftp://ftp.inria.fr/INRIA/publication/publi-ps-gz/RR/RR-5105.ps.gz

abstract:
This document releases lecture notes given during 2003 at University Henri Poincare (Nancy, France). These notes are mainly based on the book em Elementary Functions. Algorithms and Implementation by Jean-Michel Muller.

rawabstract:
This document releases lecture notes given during 2003 at University Henri Poincar{\'e} (Nancy, France). These notes are mainly based on the book {\em Elementary Functions. Algorithms and Implementation\/} by Jean-Michel Muller.

entry:
@TechReport{Lefevre:2004:AFF,
  author =       "Vincent Lef{\`e}vre and Paul Zimmermann",
  title =        "Arithm{\'e}tique flottante. ({French})
                 [{Floating-point} arithmetic]",
  type =         "Technical Report",
  institution =  inst-LORIA-INRIA-LORRAINE,
  address =      inst-LORIA-INRIA-LORRAINE:adr,
  pages =        "60",
  month =        feb,
  year =         "2004",
  bibdate =      "Sun Sep 10 08:03:11 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-5105.pdf;
                 ftp://ftp.inria.fr/INRIA/publication/publi-ps-gz/RR/RR-5105.ps.gz",
  abstract =     "This document releases lecture notes given during 2003
                 at University Henri Poincar{\'e} (Nancy, France). These
                 notes are mainly based on the book {\em Elementary
                 Functions. Algorithms and Implementation\/} by
                 Jean-Michel Muller.",
  acknowledgement = ack-nhfb,
  keywords =     "arbitrary precision; correct rounding; fixed
                 precision; floating-point number; IEEE 754 standard",
  language =     "French",
}


bibtype: inproceedings
filename: fparith.bib
label: Lefevre:2004:GMP
author: Vincent Lefevre
title: The Generic Multiple-Precision Floating-Point Addition With Exact Rounding (as in the MPFR Library)
crossref: Frougny:2004:RCR
pages: 135--145
year: 2004
bibdate: Fri Nov 17 07:00:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.17 07:00:31 ???
URL: http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_11_lefevre.pdf
keywords: addition; exact rounding; floating point; multiple precision
acknowledgement: ack-nhfb
rawauthor: Vincent Lef{\`e}vre
abstract:
We study the multiple-precision addition of two positive floating-point numbers in base 2, with exact rounding, as specified in the MPFR library, i.e. where each number has its own precision. We show how the best possible complexity (up to a constant factor that depends on the implementation) can be obtain.

rawabstract:
We study the multiple-precision addition of two positive floating-point numbers in base 2, with exact rounding, as specified in the MPFR library, i.e. where each number has its own precision. We show how the best possible complexity (up to a constant factor that depends on the implementation) can be obtain.

rawtitle:
The Generic Multiple-Precision Floating-Point Addition With Exact Rounding (as in the {MPFR} Library)

entry:
@InProceedings{Lefevre:2004:GMP,
  author =       "Vincent Lef{\`e}vre",
  title =        "The Generic Multiple-Precision Floating-Point Addition
                 With Exact Rounding (as in the {MPFR} Library)",
  crossref =     "Frougny:2004:RCR",
  pages =        "135--145",
  year =         "2004",
  bibdate =      "Fri Nov 17 07:00:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_11_lefevre.pdf",
  abstract =     "We study the multiple-precision addition of two
                 positive floating-point numbers in base 2, with exact
                 rounding, as specified in the MPFR library, i.e. where
                 each number has its own precision. We show how the best
                 possible complexity (up to a constant factor that
                 depends on the implementation) can be obtain.",
  acknowledgement = ack-nhfb,
  keywords =     "addition; exact rounding; floating point; multiple
                 precision",
}


bibtype: inproceedings
filename: fparith.bib
label: Leyva:2004:GHS
author: G. Leyva and G. Caffarena and C. Carreras and O. Nieto-Taladriz
title: A generator of high-speed floating-point modules
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 306--307
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: G. Leyva and G. Caffarena and C. Carreras and O. Nieto-Taladriz
rawtitle: A generator of high-speed floating-point modules
abstract:
Hardware implementation of arithmetic modules is a time-consuming task. Consequently, there is a demand for CAD tools that help the designer in reducing design times. This paper presents a floating-point module generator that allows user specification of the mantissa, exponent bit-width and clock period. ldots 

rawabstract:
Hardware implementation of arithmetic modules is a time-consuming task. Consequently, there is a demand for CAD tools that help the designer in reducing design times. This paper presents a floating-point module generator that allows user specification of the mantissa, exponent bit-width and clock period. \ldots{}

entry:
@InProceedings{Leyva:2004:GHS,
  author =       "G. Leyva and G. Caffarena and C. Carreras and O.
                 Nieto-Taladriz",
  booktitle =    "{FCCM 2004}. 12th Annual {IEEE} Symposium on
                 Field-Programmable Custom Computing Machines, 20--23
                 April 2004",
  title =        "A generator of high-speed floating-point modules",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "306--307",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Hardware implementation of arithmetic modules is a
                 time-consuming task. Consequently, there is a demand
                 for CAD tools that help the designer in reducing design
                 times. This paper presents a floating-point module
                 generator that allows user specification of the
                 mantissa, exponent bit-width and clock period.
                 \ldots{}",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lin:2004:SFP
booktitle: ISCAS '04. Proceedings of the 2004 International Symposium on Circuits and Systems, 23--26 May 2004
title: Static floating-point unit with implicit exponent tracking for embedded DSP
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: II-821--II-824
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawtitle: Static floating-point unit with implicit exponent tracking for embedded {DSP}
author:
Hung-Yueh Lin and Tay-Jyi Lin and Chie-Min Chao and Yen-Chin Liao and Chih-Wei Liu and Chein-Wei Jen

rawauthor:
Hung-Yueh Lin and Tay-Jyi Lin and Chie-Min Chao and Yen-Chin Liao and Chih-Wei Liu and Chein-Wei Jen

rawbooktitle:
{ISCAS '04}. Proceedings of the 2004 International Symposium on Circuits and Systems, 23--26 May 2004

entry:
@InProceedings{Lin:2004:SFP,
  author =       "Hung-Yueh Lin and Tay-Jyi Lin and Chie-Min Chao and
                 Yen-Chin Liao and Chih-Wei Liu and Chein-Wei Jen",
  booktitle =    "{ISCAS '04}. Proceedings of the 2004 International
                 Symposium on Circuits and Systems, 23--26 May 2004",
  title =        "Static floating-point unit with implicit exponent
                 tracking for embedded {DSP}",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "II-821--II-824",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: Lu:2004:ALC
author: Mi Lu
title: Arithmetic and logic in computer systems
volume: 169
publisher: pub-WILEY-INTERSCIENCE
address: pub-WILEY-INTERSCIENCE:adr
pages: xxi + 246
year: 2004
ISBN: 0-471-46945-9 (cloth) OR 0471469459 (cloth)
ISBN13: 978-0-471-46945-2 (cloth) OR 9780471469452 (cloth)
LCCN: QA76.9.C62 L8 2004
bibdate: Thu Nov 18 08:57:10 MST 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; z3950.loc.gov:7090/Voyager
bibtimestamp: 2010.11.18 08:57:10 MST
series: iley Series in Microwave and Optical Engineering
subject: Computer arithmetic; Logic programming
acknowledgement: ack-nhfb
rawauthor: Mi Lu
rawtitle: Arithmetic and logic in computer systems
URL:
http://www.loc.gov/catdir/bios/wiley046/2003062036.html; http://www.loc.gov/catdir/description/wiley041/2003062036.html; http://www.loc.gov/catdir/toc/wiley041/2003062036.html

TOC:
Addition and Subtraction 29 High-Speed Adder 53 Sequential Multiplication 77 Parallel Multiplication 103 Sequential Division 135 Fast Array Dividers 167 Floating Point Operations 183 Residue Number Operations 199 Operations through Logarithms 221 Signed-Digit Number Operations 235 Index 245

rawTOC:
Addition and Subtraction 29 \\ High-Speed Adder 53 \\ Sequential Multiplication 77 \\ Parallel Multiplication 103 \\ Sequential Division 135 \\ Fast Array Dividers 167 \\ Floating Point Operations 183 \\ Residue Number Operations 199 \\ Operations through Logarithms 221 \\ Signed-Digit Number Operations 235 \\ Index 245

entry:
@Book{Lu:2004:ALC,
  author =       "Mi Lu",
  title =        "Arithmetic and logic in computer systems",
  volume =       "169",
  publisher =    pub-WILEY-INTERSCIENCE,
  address =      pub-WILEY-INTERSCIENCE:adr,
  pages =        "xxi + 246",
  year =         "2004",
  ISBN =         "0-471-46945-9 (cloth)",
  ISBN-13 =      "978-0-471-46945-2 (cloth)",
  LCCN =         "QA76.9.C62 L8 2004",
  bibdate =      "Thu Nov 18 08:57:10 MST 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 z3950.loc.gov:7090/Voyager",
  series =       "iley Series in Microwave and Optical Engineering",
  URL =          "http://www.loc.gov/catdir/bios/wiley046/2003062036.html;
                 http://www.loc.gov/catdir/description/wiley041/2003062036.html;
                 http://www.loc.gov/catdir/toc/wiley041/2003062036.html",
  acknowledgement = ack-nhfb,
  subject =      "Computer arithmetic; Logic programming",
  tableofcontents = "Addition and Subtraction 29 \\
                 High-Speed Adder 53 \\
                 Sequential Multiplication 77 \\
                 Parallel Multiplication 103 \\
                 Sequential Division 135 \\
                 Fast Array Dividers 167 \\
                 Floating Point Operations 183 \\
                 Residue Number Operations 199 \\
                 Operations through Logarithms 221 \\
                 Signed-Digit Number Operations 235 \\
                 Index 245",
}


bibtype: inproceedings
filename: fparith.bib
label: Lutz:2004:NFP
author: D. R. Lutz and C. N. Hinds
title: A new floating-point architecture for wireless $3$D graphics
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1879--1883
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: D. R. Lutz and C. N. Hinds
rawtitle: A new floating-point architecture for wireless {$3$D} graphics
booktitle:
Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, Nov. 7--10, 2004

rawbooktitle:
Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, Nov. 7--10, 2004

entry:
@InProceedings{Lutz:2004:NFP,
  author =       "D. R. Lutz and C. N. Hinds",
  booktitle =    "Conference Record of the Thirty-Eighth Asilomar
                 Conference on Signals, Systems and Computers, Nov.
                 7--10, 2004",
  title =        "A new floating-point architecture for wireless {$3$D}
                 graphics",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1879--1883",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Madhukumar:2004:EAR
author: A. S. Madhukumar and F. Chin
title: Enhanced architecture for residue number system-based CDMA for high-rate data transmission
journal: j-IEEE-TRANS-WIREL-COMMUN
volume: 3
number: 5
pages: 1363--1368
month: sep
monthnumber: 9
year: 2004
CODEN: ITWCAX
DOI: https://doi.org/10.1109/TWC.2004.833509
ISSN: 1536-1276 (print), 1558-2248 (electronic) OR 15361276 (print), 15582248 (electronic)
ISSNL: 1536-1276 OR 15361276
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=29589
fjournal: IEEE Transactions on Wireless Communications
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Wirel. Commun.
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=7693
rawauthor: A. S. Madhukumar and F. Chin
rawtitle: Enhanced architecture for residue number system-based {CDMA} for high-rate data transmission
entry:
@Article{Madhukumar:2004:EAR,
  author =       "A. S. Madhukumar and F. Chin",
  title =        "Enhanced architecture for residue number system-based
                 {CDMA} for high-rate data transmission",
  journal =      j-IEEE-TRANS-WIREL-COMMUN,
  volume =       "3",
  number =       "5",
  pages =        "1363--1368",
  month =        sep,
  year =         "2004",
  CODEN =        "ITWCAX",
  DOI =          "https://doi.org/10.1109/TWC.2004.833509",
  ISSN =         "1536-1276 (print), 1558-2248 (electronic)",
  ISSN-L =       "1536-1276",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=29589",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Wirel. Commun.",
  fjournal =     "IEEE Transactions on Wireless Communications",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=7693",
  keywords =     "residue arithmetic; residue number system",
  summary =      "This paper presents an advanced architecture for
                 residue number system (RNS)-based code-division
                 multiple-access (CDMA) system for high-rate data
                 transmission by combining RNS representation, phase
                 shift keying/quadrature amplitude modulation (PSK/
                 \ldots{})",
}


bibtype: inproceedings
filename: fparith.bib
label: Marcus:2004:FSS
author: G. Marcus and P. Hinojosa and A. Avila and J. Nolazco-Flores
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 319--323
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: G. Marcus and P. Hinojosa and A. Avila and J. Nolazco-Flores
booktitle:
Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, November 3--5, 2004

title:
A fully synthesizable single-precision, floating-point adder / subtractor and multiplier in VHDL for general and educational use

rawbooktitle:
Proceedings of the Fifth {IEEE} International Caracas Conference on Devices, Circuits and Systems, November 3--5, 2004

rawtitle:
A fully synthesizable single-precision, floating-point adder\slash subtractor and multiplier in {VHDL} for general and educational use

entry:
@InProceedings{Marcus:2004:FSS,
  author =       "G. Marcus and P. Hinojosa and A. Avila and J.
                 Nolazco-Flores",
  booktitle =    "Proceedings of the Fifth {IEEE} International Caracas
                 Conference on Devices, Circuits and Systems, November
                 3--5, 2004",
  title =        "A fully synthesizable single-precision, floating-point
                 adder\slash subtractor and multiplier in {VHDL} for
                 general and educational use",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "319--323",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Markov:2004:SAA
author: Svetoslav Markov and Rene Alt
title: Stochastic arithmetic: Addition and multiplication by scalars
journal: j-APPL-NUM-MATH
volume: 50
number: 3--4
pages: 475--488
month: sep
monthnumber: 9
year: 2004
CODEN: ANMAEL
ISSN: 0168-9274 (print), 1873-5460 (electronic) OR 01689274 (print), 18735460 (electronic)
ISSNL: 0168-9274 OR 01689274
bibdate: Sat May 14 10:50:47 MDT 2005
bibtimestamp: 2005.05.14 10:50:47 MDT
fjournal: Applied Numerical Mathematics: Transactions of IMACS
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/01689274
rawauthor: Svetoslav Markov and Rene Alt
rawtitle: Stochastic arithmetic: Addition and multiplication by scalars
bibsource:
http://www.sciencedirect.com/science/journal/01689274; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Markov:2004:SAA,
  author =       "Svetoslav Markov and Rene Alt",
  title =        "Stochastic arithmetic: Addition and multiplication by
                 scalars",
  journal =      j-APPL-NUM-MATH,
  volume =       "50",
  number =       "3--4",
  pages =        "475--488",
  month =        sep,
  year =         "2004",
  CODEN =        "ANMAEL",
  ISSN =         "0168-9274 (print), 1873-5460 (electronic)",
  ISSN-L =       "0168-9274",
  bibdate =      "Sat May 14 10:50:47 MDT 2005",
  bibsource =    "http://www.sciencedirect.com/science/journal/01689274;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Numerical Mathematics: Transactions of IMACS",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01689274",
}


bibtype: article
filename: fparith.bib
label: Markov:2004:SAS
author: Svetoslav Markov and Rene Alt and Jean-Luc Lamotte
title: Stochastic Arithmetic: $s$-spaces and Some Applications
journal: j-NUMER-ALGORITHMS
volume: 37
number: 1--4
pages: 275--284
month: dec
monthnumber: 12
year: 2004
CODEN: NUALEG
ISSN: 1017-1398 (print), 1572-9265 (electronic) OR 10171398 (print), 15729265 (electronic)
ISSNL: 1017-1398 OR 10171398
bibdate: Mon Dec 6 07:00:28 MST 2004
bibsource: http://www.kluweronline.com/issn/1017-1398; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.12.06 07:00:28 MST
URL: http://ipsapp009.kluweronline.com/IPS/content/ext/x/J/5058/I/58/A/22/abstract.htm
fjournal: Numerical Algorithms
remark: Special Issue: SCAN'2002 International Conference (Guest Editors: Ren e Alt and Jean-Luc Lamotte)
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11075
rawauthor: Svetoslav Markov and Rene Alt and Jean-Luc Lamotte
rawtitle: Stochastic Arithmetic: $s$-spaces and Some Applications
entry:
@Article{Markov:2004:SAS,
  author =       "Svetoslav Markov and Rene Alt and Jean-Luc Lamotte",
  title =        "Stochastic Arithmetic: $s$-spaces and Some
                 Applications",
  journal =      j-NUMER-ALGORITHMS,
  volume =       "37",
  number =       "1--4",
  pages =        "275--284",
  month =        dec,
  year =         "2004",
  CODEN =        "NUALEG",
  ISSN =         "1017-1398 (print), 1572-9265 (electronic)",
  ISSN-L =       "1017-1398",
  bibdate =      "Mon Dec 6 07:00:28 MST 2004",
  bibsource =    "http://www.kluweronline.com/issn/1017-1398;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ipsapp009.kluweronline.com/IPS/content/ext/x/J/5058/I/58/A/22/abstract.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerical Algorithms",
  journal-URL =  "http://link.springer.com/journal/11075",
  remark =       "Special Issue: SCAN'2002 International Conference
                 (Guest Editors: Ren {\'e} Alt and Jean-Luc Lamotte)",
}


bibtype: inproceedings
filename: fparith.bib
label: Markstein:2004:SDS
author: Peter Markstein
title: Software Division and Square Root Using Goldschmidt's Algorithms
crossref: Frougny:2004:RCR
pages: 146--157
year: 2004
bibdate: Fri Nov 17 07:00:31 2023
bibtimestamp: 2023.11.17 07:00:31 ???
URL: http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_12_markstein.pdf
keywords: correct rounding; division; floating-point arithmetic; Goldschmidt; square root
acknowledgement: ack-nhfb
rawauthor: Peter Markstein
rawtitle: Software Division and Square Root Using {Goldschmidt}'s Algorithms
abstract:
Goldschmidt's Algorithms for division and square root are often characterized as being useful for hardware implementation, and lacking self-correction. A reexamination of these algorithms show that there are good software counterparts that retain the speed advantage of Goldschmidt's Algorithm over the Newton--Raphson iteration. A final step is needed, however, to get the last bit rounded correctly.

rawabstract:
Goldschmidt's Algorithms for division and square root are often characterized as being useful for hardware implementation, and lacking self-correction. A reexamination of these algorithms show that there are good software counterparts that retain the speed advantage of Goldschmidt's Algorithm over the Newton--Raphson iteration. A final step is needed, however, to get the last bit rounded correctly.

entry:
@InProceedings{Markstein:2004:SDS,
  author =       "Peter Markstein",
  title =        "Software Division and Square Root Using
                 {Goldschmidt}'s Algorithms",
  crossref =     "Frougny:2004:RCR",
  pages =        "146--157",
  year =         "2004",
  bibdate =      "Fri Nov 17 07:00:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_12_markstein.pdf",
  abstract =     "Goldschmidt's Algorithms for division and square root
                 are often characterized as being useful for hardware
                 implementation, and lacking self-correction. A
                 reexamination of these algorithms show that there are
                 good software counterparts that retain the speed
                 advantage of Goldschmidt's Algorithm over the
                 Newton--Raphson iteration. A final step is needed,
                 however, to get the last bit rounded correctly.",
  acknowledgement = ack-nhfb,
  keywords =     "correct rounding; division; floating-point arithmetic;
                 Goldschmidt; square root",
}


bibtype: article
filename: fparith.bib
label: McIvor:2004:IMM
author: C. McIvor and M. McLoone and J. V. McCanny
title: Improved Montgomery modular inverse algorithm
journal: j-ELECT-LETTERS
volume: 40
number: 18
pages: 1110--1112
day: 2
month: sep
monthnumber: 9
year: 2004
CODEN: ELLEAK
DOI: https://doi.org/10.1049/el:20045610
ISSN: 0013-5194 (print), 1350-911X (electronic) OR 00135194 (print), 1350911X (electronic)
ISSNL: 0013-5194 OR 00135194
bibdate: Wed Dec 28 18:13:01 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/prng.bib
bibtimestamp: 2011.12.28 18:13:01 ???
URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1335002
fjournal: Electronics Letters
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220
rawauthor: C. McIvor and M. McLoone and J. V. McCanny
rawtitle: Improved {Montgomery} modular inverse algorithm
entry:
@Article{McIvor:2004:IMM,
  author =       "C. McIvor and M. McLoone and J. V. McCanny",
  title =        "Improved {Montgomery} modular inverse algorithm",
  journal =      j-ELECT-LETTERS,
  volume =       "40",
  number =       "18",
  pages =        "1110--1112",
  day =          "2",
  month =        sep,
  year =         "2004",
  CODEN =        "ELLEAK",
  DOI =          "https://doi.org/10.1049/el:20045610",
  ISSN =         "0013-5194 (print), 1350-911X (electronic)",
  ISSN-L =       "0013-5194",
  bibdate =      "Wed Dec 28 18:13:01 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/prng.bib",
  URL =          "http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1335002",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronics Letters",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220",
}


bibtype: article
filename: fparith.bib
label: McKenzie:2004:ACP
author: Pierre McKenzie and Heribert Vollmer and Klaus W. Wagner
title: Arithmetic Circuits and Polynomial Replacement Systems
journal: j-SIAM-J-COMPUT
volume: 33
number: 6
pages: 1513--1531
month: dec
monthnumber: 12
year: 2004
CODEN: SMJCAT
ISSN: 0097-5397 (print), 1095-7111 (electronic) OR 00975397 (print), 10957111 (electronic)
ISSNL: 0097-5397 OR 00975397
bibdate: Sat Apr 16 10:19:28 MDT 2005
bibtimestamp: 2005.04.16 10:19:28 MDT
URL: http://epubs.siam.org/sam-bin/dbq/article/39207
fjournal: SIAM Journal on Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sicomp
rawauthor: Pierre McKenzie and Heribert Vollmer and Klaus W. Wagner
rawtitle: Arithmetic Circuits and Polynomial Replacement Systems
bibsource:
http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/33/6; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{McKenzie:2004:ACP,
  author =       "Pierre McKenzie and Heribert Vollmer and Klaus W.
                 Wagner",
  title =        "Arithmetic Circuits and Polynomial Replacement
                 Systems",
  journal =      j-SIAM-J-COMPUT,
  volume =       "33",
  number =       "6",
  pages =        "1513--1531",
  month =        dec,
  year =         "2004",
  CODEN =        "SMJCAT",
  ISSN =         "0097-5397 (print), 1095-7111 (electronic)",
  ISSN-L =       "0097-5397",
  bibdate =      "Sat Apr 16 10:19:28 MDT 2005",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/33/6;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://epubs.siam.org/sam-bin/dbq/article/39207",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Computing",
  journal-URL =  "http://epubs.siam.org/sicomp",
}


bibtype: article
filename: fparith.bib
label: McLaughlin:2004:NFM
author: Philip B. McLaughlin, Jr.
title: New frameworks for Montgomery's modular multiplication method
journal: j-MATH-COMPUT
volume: 73
number: 246
pages: 899--906
month: apr
monthnumber: 4
year: 2004
CODEN: MCMPAF
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Wed Aug 11 08:23:05 MDT 2004
bibsource: http://www.ams.org/mcom/2004-73-246; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.08.11 08:23:05 MDT
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Philip B. {McLaughlin, Jr.}
rawtitle: New frameworks for {Montgomery}'s modular multiplication method
URL:
http://www.ams.org/mcom/2004-73-246/S0025-5718-03-01543-6/home.html; http://www.ams.org/mcom/2004-73-246/S0025-5718-03-01543-6/S0025-5718-03-01543-6.dvi; http://www.ams.org/mcom/2004-73-246/S0025-5718-03-01543-6/S0025-5718-03-01543-6.pdf; http://www.ams.org/mcom/2004-73-246/S0025-5718-03-01543-6/S0025-5718-03-01543-6.ps; http://www.ams.org/mcom/2004-73-246/S0025-5718-03-01543-6/S0025-5718-03-01543-6.tex

entry:
@Article{McLaughlin:2004:NFM,
  author =       "Philip B. {McLaughlin, Jr.}",
  title =        "New frameworks for {Montgomery}'s modular
                 multiplication method",
  journal =      j-MATH-COMPUT,
  volume =       "73",
  number =       "246",
  pages =        "899--906",
  month =        apr,
  year =         "2004",
  CODEN =        "MCMPAF",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Wed Aug 11 08:23:05 MDT 2004",
  bibsource =    "http://www.ams.org/mcom/2004-73-246;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.ams.org/mcom/2004-73-246/S0025-5718-03-01543-6/home.html;
                 http://www.ams.org/mcom/2004-73-246/S0025-5718-03-01543-6/S0025-5718-03-01543-6.dvi;
                 http://www.ams.org/mcom/2004-73-246/S0025-5718-03-01543-6/S0025-5718-03-01543-6.pdf;
                 http://www.ams.org/mcom/2004-73-246/S0025-5718-03-01543-6/S0025-5718-03-01543-6.ps;
                 http://www.ams.org/mcom/2004-73-246/S0025-5718-03-01543-6/S0025-5718-03-01543-6.tex",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
}


bibtype: article
filename: fparith.bib
label: Mitra:2004:NAB
author: A. Mitra and M. Chakraborty
title: The NLMS algorithm in block floating-point format
journal: j-IEEE-SIGNAL-PROCESS-LETT
volume: 11
number: 3
pages: 301--304
month: mar
monthnumber: 3
year: 2004
CODEN: ISPLEM
ISSN: 1070-9908 (print), 1558-2361 (electronic) OR 10709908 (print), 15582361 (electronic)
ISSNL: 1070-9908 OR 10709908
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Signal Processing Letters
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=97
rawauthor: A. Mitra and M. Chakraborty
rawtitle: The {NLMS} algorithm in block floating-point format
abstract:
We present a novel scheme to implement the normalized least mean square algorithm in block floating-point (BFP) format, which permits processing of data over a wide dynamic range, at a cost significantly less than that of a floating-point processor.

rawabstract:
We present a novel scheme to implement the normalized least mean square algorithm in block floating-point (BFP) format, which permits processing of data over a wide dynamic range, at a cost significantly less than that of a floating-point processor.

entry:
@Article{Mitra:2004:NAB,
  author =       "A. Mitra and M. Chakraborty",
  title =        "The {NLMS} algorithm in block floating-point format",
  journal =      j-IEEE-SIGNAL-PROCESS-LETT,
  volume =       "11",
  number =       "3",
  pages =        "301--304",
  month =        mar,
  year =         "2004",
  CODEN =        "ISPLEM",
  ISSN =         "1070-9908 (print), 1558-2361 (electronic)",
  ISSN-L =       "1070-9908",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a novel scheme to implement the normalized
                 least mean square algorithm in block floating-point
                 (BFP) format, which permits processing of data over a
                 wide dynamic range, at a cost significantly less than
                 that of a floating-point processor.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Signal Processing Letters",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=97",
  summary =      "We present a novel scheme to implement the normalized
                 least mean square algorithm in block floating-point
                 (BFP) format, which permits processing of data over a
                 wide dynamic range, at a cost significantly less than
                 that of a floating-point processor. \ldots{}",
}


bibtype: manual
filename: fparith.bib
label: MPFRTeam:2004:MMP
author: The MPFR Team
title: MPFR: The Multiple Precision Floating-Point Reliable Library: Edition 2.1.0: November 2004
pages: ii + 35
year: 2004
bibdate: Thu Dec 15 18:49:26 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.12.15 18:49:26 ???
URL: http://www.mpfr.org/mpfr-current/mpfr.pdf
acknowledgement: ack-nhfb
rawauthor: {The MPFR Team}
rawtitle: {MPFR}: {The} {Multiple Precision Floating-Point Reliable Library}: Edition 2.1.0: {November 2004}
entry:
@Manual{MPFRTeam:2004:MMP,
  author =       "{The MPFR Team}",
  title =        "{MPFR}: {The} {Multiple Precision Floating-Point
                 Reliable Library}: Edition 2.1.0: {November 2004}",
  pages =        "ii + 35",
  year =         "2004",
  bibdate =      "Thu Dec 15 18:49:26 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.mpfr.org/mpfr-current/mpfr.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Muller:2004:CSR
author: Siguna Muller
title: On the Computation of Square Roots in Finite Fields
journal: j-DESIGNS-CODES-CRYPTOGR
volume: 31
number: 3
pages: 301--312
month: mar
monthnumber: 3
year: 2004
CODEN: DCCREC
ISSN: 0925-1022 (print), 1573-7586 (electronic) OR 09251022 (print), 15737586 (electronic)
ISSNL: 0925-1022 OR 09251022
bibdate: Tue Aug 3 16:38:18 MDT 2004
bibsource: http://www.wkap.nl/jrnltoc.htm/0925-1022; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.08.03 16:38:18 MDT
URL: http://ipsapp008.kluweronline.com/IPS/content/ext/x/J/4630/I/61/A/8/abstract.htm
fjournal: Designs, codes, and cryptography
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10623
rawauthor: Siguna M{\"u}ller
rawtitle: On the Computation of Square Roots in Finite Fields
entry:
@Article{Muller:2004:CSR,
  author =       "Siguna M{\"u}ller",
  title =        "On the Computation of Square Roots in Finite Fields",
  journal =      j-DESIGNS-CODES-CRYPTOGR,
  volume =       "31",
  number =       "3",
  pages =        "301--312",
  month =        mar,
  year =         "2004",
  CODEN =        "DCCREC",
  ISSN =         "0925-1022 (print), 1573-7586 (electronic)",
  ISSN-L =       "0925-1022",
  bibdate =      "Tue Aug 3 16:38:18 MDT 2004",
  bibsource =    "http://www.wkap.nl/jrnltoc.htm/0925-1022;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ipsapp008.kluweronline.com/IPS/content/ext/x/J/4630/I/61/A/8/abstract.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "Designs, codes, and cryptography",
  journal-URL =  "http://link.springer.com/journal/10623",
}


bibtype: techreport
filename: fparith.bib
label: Muller:2004:DCS
author: Jean-Michel Muller and A. Tisserand and B. Dupont de Dinechin and C. Monat
title: Division by Constant for the ST100 DSP Microprocessor
type: Research Report
number: RR2004-45
institution: Ecole Normale Superieure de Lyon
address: 69364 Lyon Cedex 07, France
pages: 2 + 10
month: oct
monthnumber: 10
year: 2004
bibdate: Mon Dec 06 11:14:04 2004
bibsource: http://www.ens-lyon.fr/LIP/Pub/rr2004.php; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.12.06 11:14:04 ???
URL: http://www.ens-lyon.fr/LIP/Pub/Rapports/RR/RR2004/RR2004-45.ps.gz
keywords: Compiler; Computer Arithmetic; Division by Constant; DSP; Euclidean Division; Software Division
acknowledgement: ack-nhfb
rawauthor: Jean-Michel Muller and A. Tisserand and B. Dupont de Dinechin and C. Monat
rawtitle: Division by Constant for the {ST100} {DSP} Microprocessor
abstract:
Algorithms for Euclidean (i.e., integer) division by a constant operation are presented. They allow fast computation for some values of the divisor (known at compile time) or also when both quotient and modulus are required. These algorithms are based on the multiply-accumulate instruction and the 40-bit arithmetic available in many DSPs. The results are demonstrated on the ST100 DSP from STMicroelectronics in the case of standard speech coding applications.

rawabstract:
Algorithms for Euclidean (i.e., integer) division by a constant operation are presented. They allow fast computation for some values of the divisor (known at compile time) or also when both quotient and modulus are required. These algorithms are based on the multiply-accumulate instruction and the 40-bit arithmetic available in many DSPs. The results are demonstrated on the ST100 DSP from STMicroelectronics in the case of standard speech coding applications.

entry:
@TechReport{Muller:2004:DCS,
  author =       "Jean-Michel Muller and A. Tisserand and B. Dupont de
                 Dinechin and C. Monat",
  title =        "Division by Constant for the {ST100} {DSP}
                 Microprocessor",
  type =         "Research Report",
  number =       "RR2004-45",
  institution =  "{\'E}cole Normale Sup{\'e}rieure de Lyon",
  address =      "69364 Lyon Cedex 07, France",
  pages =        "2 + 10",
  month =        oct,
  year =         "2004",
  bibdate =      "Mon Dec 06 11:14:04 2004",
  bibsource =    "http://www.ens-lyon.fr/LIP/Pub/rr2004.php;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.ens-lyon.fr/LIP/Pub/Rapports/RR/RR2004/RR2004-45.ps.gz",
  abstract =     "Algorithms for Euclidean (i.e., integer) division by a
                 constant operation are presented. They allow fast
                 computation for some values of the divisor (known at
                 compile time) or also when both quotient and modulus
                 are required. These algorithms are based on the
                 multiply-accumulate instruction and the 40-bit
                 arithmetic available in many DSPs. The results are
                 demonstrated on the ST100 DSP from STMicroelectronics
                 in the case of standard speech coding applications.",
  acknowledgement = ack-nhfb,
  keywords =     "Compiler; Computer Arithmetic; Division by Constant;
                 DSP; Euclidean Division; Software Division",
}


bibtype: article
filename: fparith.bib
label: Nguyen:2004:LDL
author: P. Nguyen and D. Stehle
title: Low-dimensional lattice basis reduction revisited (extended abstract)
journal: j-LECT-NOTES-COMP-SCI
volume: 3076
pages: 338--357
year: 2004
CODEN: LNCSD9
DOI: https://doi.org/10.1007/b98210
ISBN: 3-540-22156-5 OR 3540221565
ISBN13: 978-3-540-22156-2 OR 9783540221562
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Fri Jun 24 14:49:07 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 14:49:07 ???
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: P. Nguyen and D. Stehle
rawtitle: Low-dimensional lattice basis reduction revisited (extended abstract)
entry:
@Article{Nguyen:2004:LDL,
  author =       "P. Nguyen and D. Stehle",
  title =        "Low-dimensional lattice basis reduction revisited
                 (extended abstract)",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "3076",
  pages =        "338--357",
  year =         "2004",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/b98210",
  ISBN =         "3-540-22156-5",
  ISBN-13 =      "978-3-540-22156-2",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Fri Jun 24 14:49:07 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Nievergelt:2004:AAP
author: Yves Nievergelt
title: Analysis and applications of Priest's distillation
journal: j-TOMS
volume: 30
number: 4
pages: 402--433
month: dec
monthnumber: 12
year: 2004
CODEN: ACMSCU
DOI: https://doi.org/10.1145/1039813.1039815
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Tue Apr 12 06:34:31 MDT 2005
bibsource: http://www.acm.org/pubs/contents/journals/toms/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.12 06:34:31 MDT
fjournal: ACM Transactions on Mathematical Software (TOMS)
keywords: accurate floating-point summation; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/toms
rawauthor: Yves Nievergelt
rawtitle: Analysis and applications of {Priest}'s distillation
abstract:
Correcting an infinite loop in Douglas M. Priest's renormalization algorithm, the theory proved here supports streamlined algorithms to resolve the tablemaker's dilemma for the floating-point computation of real and complex sums and dot-products, properly rounded to the ultimate digit. Applications include computations of areas, volumes, and intersections.

rawabstract:
Correcting an infinite loop in Douglas M. Priest's renormalization algorithm, the theory proved here supports streamlined algorithms to resolve the tablemaker's dilemma for the floating-point computation of real and complex sums and dot-products, properly rounded to the ultimate digit. Applications include computations of areas, volumes, and intersections.

entry:
@Article{Nievergelt:2004:AAP,
  author =       "Yves Nievergelt",
  title =        "Analysis and applications of {Priest}'s distillation",
  journal =      j-TOMS,
  volume =       "30",
  number =       "4",
  pages =        "402--433",
  month =        dec,
  year =         "2004",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/1039813.1039815",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Tue Apr 12 06:34:31 MDT 2005",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toms/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Correcting an infinite loop in Douglas M. Priest's
                 renormalization algorithm, the theory proved here
                 supports streamlined algorithms to resolve the
                 tablemaker's dilemma for the floating-point computation
                 of real and complex sums and dot-products, properly
                 rounded to the ultimate digit. Applications include
                 computations of areas, volumes, and intersections.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "accurate floating-point summation; correct rounding;
                 floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Ogasawara:2004:OPO
author: Takeshi Ogasawara and Hideaki Komatsu and Toshio Nakatani
title: Optimizing precision overhead for x86 processors
journal: j-SPE
volume: 34
number: 9
pages: 875--893
day: 25
month: jul
monthnumber: 7
year: 2004
CODEN: SPEXBL
DOI: https://doi.org/10.1002/spe.596
ISSN: 0038-0644 (print), 1097-024X (electronic) OR 00380644 (print), 1097024X (electronic)
ISSNL: 0038-0644 OR 00380644
bibdate: Sat Apr 16 07:26:31 MDT 2005
bibtimestamp: 2005.04.16 07:26:31 MDT
fjournal: Software---Practice and Experience
keywords: floating-point operations; Java; precision control; x86 processors
acknowledgement: ack-nhfb
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X
onlinedate: 27 Apr 2004
rawauthor: Takeshi Ogasawara and Hideaki Komatsu and Toshio Nakatani
rawtitle: Optimizing precision overhead for x86 processors
bibsource:
http://www.interscience.wiley.com/jpages/0038-0644; http://www3.interscience.wiley.com/journalfinder.html; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
It is a major challenge for a Java JIT compiler to perform single-precision floating-point operations efficiently for the x86 processors. In previous research, the double-precision mode is set as the default precision mode when methods are invoked. Sophisticated approaches then use heuristic approaches to optimization by considering the trade-offs between roundings and mode switches. However, this convention introduces redundant mode switches across method boundaries. Furthermore, methods that include both single- and double-precision operations cannot switch the mode, even if single-precision operations are dominant. We propose a new approach to these problems. We eliminate redundant mode switches by ignoring the default precision mode and calling a method in the same precision mode as the caller. For methods that include both single- and double-precision methods, we reduce the overhead of rounding by isolating code segments of a given method that should be executed in the single-precision mode. We implemented our approach in IBM's Just-in-Time compiler, and obtained experimental results demonstrating that, in SPECjvm98, it consistently shows the best performance in any configuration of benchmark programs, inline policies, and processor architectures compared with previous research approaches.

rawabstract:
It is a major challenge for a Java JIT compiler to perform single-precision floating-point operations efficiently for the x86 processors. In previous research, the double-precision mode is set as the default precision mode when methods are invoked. Sophisticated approaches then use heuristic approaches to optimization by considering the trade-offs between roundings and mode switches. However, this convention introduces redundant mode switches across method boundaries. Furthermore, methods that include both single- and double-precision operations cannot switch the mode, even if single-precision operations are dominant. We propose a new approach to these problems. We eliminate redundant mode switches by ignoring the default precision mode and calling a method in the same precision mode as the caller. For methods that include both single- and double-precision methods, we reduce the overhead of rounding by isolating code segments of a given method that should be executed in the single-precision mode. We implemented our approach in IBM's Just-in-Time compiler, and obtained experimental results demonstrating that, in SPECjvm98, it consistently shows the best performance in any configuration of benchmark programs, inline policies, and processor architectures compared with previous research approaches.

entry:
@Article{Ogasawara:2004:OPO,
  author =       "Takeshi Ogasawara and Hideaki Komatsu and Toshio
                 Nakatani",
  title =        "Optimizing precision overhead for x86 processors",
  journal =      j-SPE,
  volume =       "34",
  number =       "9",
  pages =        "875--893",
  day =          "25",
  month =        jul,
  year =         "2004",
  CODEN =        "SPEXBL",
  DOI =          "https://doi.org/10.1002/spe.596",
  ISSN =         "0038-0644 (print), 1097-024X (electronic)",
  ISSN-L =       "0038-0644",
  bibdate =      "Sat Apr 16 07:26:31 MDT 2005",
  bibsource =    "http://www.interscience.wiley.com/jpages/0038-0644;
                 http://www3.interscience.wiley.com/journalfinder.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "It is a major challenge for a Java JIT compiler to
                 perform single-precision floating-point operations
                 efficiently for the x86 processors. In previous
                 research, the double-precision mode is set as the
                 default precision mode when methods are invoked.
                 Sophisticated approaches then use heuristic approaches
                 to optimization by considering the trade-offs between
                 roundings and mode switches. However, this convention
                 introduces redundant mode switches across method
                 boundaries. Furthermore, methods that include both
                 single- and double-precision operations cannot switch
                 the mode, even if single-precision operations are
                 dominant. We propose a new approach to these problems.
                 We eliminate redundant mode switches by ignoring the
                 default precision mode and calling a method in the same
                 precision mode as the caller. For methods that include
                 both single- and double-precision methods, we reduce
                 the overhead of rounding by isolating code segments of
                 a given method that should be executed in the
                 single-precision mode. We implemented our approach in
                 IBM's Just-in-Time compiler, and obtained experimental
                 results demonstrating that, in SPECjvm98, it
                 consistently shows the best performance in any
                 configuration of benchmark programs, inline policies,
                 and processor architectures compared with previous
                 research approaches.",
  acknowledgement = ack-nhfb,
  fjournal =     "Software---Practice and Experience",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X",
  keywords =     "floating-point operations; Java; precision control;
                 x86 processors",
  onlinedate =   "27 Apr 2004",
}


bibtype: techreport
filename: fparith.bib
label: Ogita:2004:ASDa
author: Takeshi Ogita and Siegfried M. Rump and Shin'ichi Oishi
title: Accurate Sum and Dot Product
type: Technical Report
number: 04.1
institution: Forschungsschwerpunkt Informations- und Kommunikationstechnik, Technical University Hamburg-Harburg
address: Hamburg, Germany
pages: 4
year: 2004
bibdate: Fri Nov 26 15:58:09 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.26 15:58:09 ???
keywords: accurate floating-point summation; distillation
acknowledgement: ack-nhfb
rawauthor: Takeshi Ogita and Siegfried M. Rump and Shin'ichi Oishi
rawtitle: Accurate Sum and Dot Product
entry:
@TechReport{Ogita:2004:ASDa,
  author =       "Takeshi Ogita and Siegfried M. Rump and Shin'ichi
                 Oishi",
  title =        "Accurate Sum and Dot Product",
  type =         "Technical Report",
  number =       "04.1",
  institution =  "Forschungsschwerpunkt Informations- und
                 Kommunikationstechnik, Technical University
                 Hamburg-Harburg",
  address =      "Hamburg, Germany",
  pages =        "4",
  year =         "2004",
  bibdate =      "Fri Nov 26 15:58:09 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation; distillation",
}


bibtype: inproceedings
filename: fparith.bib
label: Ogita:2004:ASDb
author: Takeshi Ogita and Siegfried M. Rump and Shin'ichi Oishi
title: Accurate Sum and Dot Product with Applications
crossref: IEEE:2004:IIS
pages: 152--155
year: 2004
bibdate: Fri Nov 26 15:55:22 2004
bibtimestamp: 2004.11.26 15:55:22 ???
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
rawauthor: Takeshi Ogita and Siegfried M. Rump and Shin'ichi Oishi
rawtitle: Accurate Sum and Dot Product with Applications
bibsource:
http://www.oishi.info.waseda.ac.jp/~ogita/index.html; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://citeseer.ist.psu.edu/cache/papers/cs2/255/http:zSzzSzwww.oishi.info.waseda.ac.jpzSz~ogitazSzdoczSzsum040921.pdf/accurate-sum-and-dot.pdf; http://www.ti3.tu-harburg.de/paper/rump/OgRuOi04a.pdf

abstract:
In a recent paper the authors presented a new and very fast algorithm for accurate computation and inclusion of the sum and dot product of floating point numbers. In this paper we show that the algorithms can be used to compute a very accurate inclusion of the solution of systems of linear equations. As a basic building block, accurate solution of linear equations has applications in very many areas.

rawabstract:
In a recent paper the authors presented a new and very fast algorithm for accurate computation and inclusion of the sum and dot product of floating point numbers. In this paper we show that the algorithms can be used to compute a very accurate inclusion of the solution of systems of linear equations. As a basic building block, accurate solution of linear equations has applications in very many areas.

entry:
@InProceedings{Ogita:2004:ASDb,
  author =       "Takeshi Ogita and Siegfried M. Rump and Shin'ichi
                 Oishi",
  title =        "Accurate Sum and Dot Product with Applications",
  crossref =     "IEEE:2004:IIS",
  pages =        "152--155",
  year =         "2004",
  bibdate =      "Fri Nov 26 15:55:22 2004",
  bibsource =    "http://www.oishi.info.waseda.ac.jp/~ogita/index.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://citeseer.ist.psu.edu/cache/papers/cs2/255/http:zSzzSzwww.oishi.info.waseda.ac.jpzSz~ogitazSzdoczSzsum040921.pdf/accurate-sum-and-dot.pdf;
                 http://www.ti3.tu-harburg.de/paper/rump/OgRuOi04a.pdf",
  abstract =     "In a recent paper the authors presented a new and very
                 fast algorithm for accurate computation and inclusion
                 of the sum and dot product of floating point numbers.
                 In this paper we show that the algorithms can be used
                 to compute a very accurate inclusion of the solution of
                 systems of linear equations. As a basic building block,
                 accurate solution of linear equations has applications
                 in very many areas.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation",
}


bibtype: inproceedings
filename: fparith.bib
label: Olausson:2004:RFP
author: M. Olausson and A. Ehliar and J. Eilert and D. Liu
booktitle: ISCAS '04. Proceedings of the 2004 International Symposium on Circuits and Systems, 23--26 May 2004
title: Reduced floating point for MPEG1/2 layer III decoding
volume: 5
publisher: pub-IEEE
address: pub-IEEE:adr
pages: V-209--V-212
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: M. Olausson and A. Ehliar and J. Eilert and D. Liu
rawtitle: Reduced floating point for {MPEG1/2} layer {III} decoding
abstract:
A new approach to decode MPEG 1/2-layer III, mp3, is presented. Instead of converting the algorithm to fixed point, we propose a 16-bit floating point implementation. These 16 bits include 1 sign bit and 15 bits of both mantissa and exponent. ldots 

rawabstract:
A new approach to decode MPEG 1/2-layer III, mp3, is presented. Instead of converting the algorithm to fixed point, we propose a 16-bit floating point implementation. These 16 bits include 1 sign bit and 15 bits of both mantissa and exponent. \ldots{}

rawbooktitle:
{ISCAS '04}. Proceedings of the 2004 International Symposium on Circuits and Systems, 23--26 May 2004

entry:
@InProceedings{Olausson:2004:RFP,
  author =       "M. Olausson and A. Ehliar and J. Eilert and D. Liu",
  booktitle =    "{ISCAS '04}. Proceedings of the 2004 International
                 Symposium on Circuits and Systems, 23--26 May 2004",
  title =        "Reduced floating point for {MPEG1/2} layer {III}
                 decoding",
  volume =       "5",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "V-209--V-212",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A new approach to decode MPEG 1/2-layer III, mp3, is
                 presented. Instead of converting the algorithm to fixed
                 point, we propose a 16-bit floating point
                 implementation. These 16 bits include 1 sign bit and 15
                 bits of both mantissa and exponent. \ldots{}",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Ortiz:2004:SPI
author: I. Ortiz and M. Jimenez
booktitle: MWSCAS '04. The 2004 47th Midwest Symposium on Circuits and Systems. 25--28 July 2004
title: Scalable pipeline insertion in floating-point division and square root units
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: II-225--II-228
year: 2004
bibdate: Sat Jul 16 15:28:14 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:14 MDT
acknowledgement: ack-nhfb
rawauthor: I. Ortiz and M. Jimenez
rawbooktitle: {MWSCAS '04}. The 2004 47th Midwest Symposium on Circuits and Systems. 25--28 July 2004
rawtitle: Scalable pipeline insertion in floating-point division and square root units
abstract:
Division and square root are important operations in a number of data processing algorithms. They are inherently time consuming operations and can require a significant amount of resources when implemented in hardware. This work reports the development of scalable, floating-point (FP) division and square root operators with adjustable precision, range, and pipeline granularity. An algorithm for pipeline insertion was used for both operators, enabling speeds up to 204MFLOPS when implemented on a Xilinx Virtex II FPGA.

rawabstract:
Division and square root are important operations in a number of data processing algorithms. They are inherently time consuming operations and can require a significant amount of resources when implemented in hardware. This work reports the development of scalable, floating-point (FP) division and square root operators with adjustable precision, range, and pipeline granularity. An algorithm for pipeline insertion was used for both operators, enabling speeds up to 204MFLOPS when implemented on a Xilinx Virtex II FPGA.

entry:
@InProceedings{Ortiz:2004:SPI,
  author =       "I. Ortiz and M. Jimenez",
  booktitle =    "{MWSCAS '04}. The 2004 47th Midwest Symposium on
                 Circuits and Systems. 25--28 July 2004",
  title =        "Scalable pipeline insertion in floating-point division
                 and square root units",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "II-225--II-228",
  year =         "2004",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:14 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Division and square root are important operations in a
                 number of data processing algorithms. They are
                 inherently time consuming operations and can require a
                 significant amount of resources when implemented in
                 hardware. This work reports the development of
                 scalable, floating-point (FP) division and square root
                 operators with adjustable precision, range, and
                 pipeline granularity. An algorithm for pipeline
                 insertion was used for both operators, enabling speeds
                 up to 204MFLOPS when implemented on a Xilinx Virtex II
                 FPGA.",
  acknowledgement = ack-nhfb,
  summary =      "Division and square root are important operations in a
                 number of data processing algorithms. They are
                 inherently time consuming operations and can require a
                 significant amount of resources when implemented in
                 hardware. This work reports the \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Pace:2004:ERL
author: L. Pace and A. Salvan and L. Ventura
title: The Effects of Rounding on Likelihood Procedures
journal: j-J-APPL-STAT
volume: 31
number: 1
pages: 29--48
month: jan
monthnumber: 1
year: 2004
ISSN: 0266-4763 (print), 1360-0532 (electronic) OR 02664763 (print), 13600532 (electronic)
ISSNL: 0266-4763 OR 02664763
bibdate: Sat Dec 4 12:10:37 MST 2004
bibtimestamp: 2004.12.04 12:10:37 MST
fjournal: Journal of Applied Statistics
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/cjas20
rawauthor: L. Pace and A. Salvan and L. Ventura
rawtitle: The Effects of Rounding on Likelihood Procedures
entry:
@Article{Pace:2004:ERL,
  author =       "L. Pace and A. Salvan and L. Ventura",
  title =        "The Effects of Rounding on Likelihood Procedures",
  journal =      j-J-APPL-STAT,
  volume =       "31",
  number =       "1",
  pages =        "29--48",
  month =        jan,
  year =         "2004",
  CODEN =        "????",
  ISSN =         "0266-4763 (print), 1360-0532 (electronic)",
  ISSN-L =       "0266-4763",
  bibdate =      "Sat Dec 4 12:10:37 MST 2004",
  bibsource =    "http://www.tandf.co.uk/journals/routledge/02664763.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Applied Statistics",
  journal-URL =  "http://www.tandfonline.com/loi/cjas20",
}


bibtype: article
filename: fparith.bib
label: Page:2004:PCA
author: D. Page and N. P. Smart
title: Parallel cryptographic arithmetic using a redundant Montgomery representation
journal: j-IEEE-TRANS-COMPUT
volume: 53
number: 11
pages: 1474--1482
month: nov
monthnumber: 11
year: 2004
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2004.100
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 08:12:46 MDT 2011
bibtimestamp: 2011.07.05 08:12:46 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1336767
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: D. Page and N. P. Smart
rawtitle: Parallel cryptographic arithmetic using a redundant {Montgomery} representation
entry:
@Article{Page:2004:PCA,
  author =       "D. Page and N. P. Smart",
  title =        "Parallel cryptographic arithmetic using a redundant
                 {Montgomery} representation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "53",
  number =       "11",
  pages =        "1474--1482",
  month =        nov,
  year =         "2004",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2004.100",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 08:12:46 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1336767",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Paul:2004:SMR
author: L. J. Paul and P. H. Bauer and C. Lorand and K. Premaratne
booktitle: MWSCAS '04. The 2004 47th Midwest Symposium on Circuits and Systems, 25--28 July 2004
title: Stabilizing mantissa rates in feedback systems with floating-point quantization
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: II-501--II-504
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: L. J. Paul and P. H. Bauer and C. Lorand and K. Premaratne
rawbooktitle: {MWSCAS '04}. The 2004 47th Midwest Symposium on Circuits and Systems, 25--28 July 2004
rawtitle: Stabilizing mantissa rates in feedback systems with floating-point quantization
entry:
@InProceedings{Paul:2004:SMR,
  author =       "L. J. Paul and P. H. Bauer and C. Lorand and K.
                 Premaratne",
  booktitle =    "{MWSCAS '04}. The 2004 47th Midwest Symposium on
                 Circuits and Systems, 25--28 July 2004",
  title =        "Stabilizing mantissa rates in feedback systems with
                 floating-point quantization",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "II-501--II-504",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Petkovic:2004:GCS
author: M. S. Petkovic and L. Rancic
title: On the guaranteed convergence of the square-root iteration method
journal: j-J-COMPUT-APPL-MATH
volume: 170
number: 1
pages: 169--179
day: 1
month: sep
monthnumber: 9
year: 2004
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:00:00 MST 2017
bibtimestamp: 2017.02.25 13:00:00 MST
URL: http://www.sciencedirect.com/science/article/pii/S0377042704000184
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: M. S. Petkovi{\'c} and L. Ranci{\'c}
rawtitle: On the guaranteed convergence of the square-root iteration method
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2000.bib

entry:
@Article{Petkovic:2004:GCS,
  author =       "M. S. Petkovi{\'c} and L. Ranci{\'c}",
  title =        "On the guaranteed convergence of the square-root
                 iteration method",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "170",
  number =       "1",
  pages =        "169--179",
  day =          "1",
  month =        sep,
  year =         "2004",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:00:00 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2000.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042704000184",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: article
filename: fparith.bib
label: Pineiro:2004:AAL
author: J. A. Pineiro and M. D. Ercegovac and J. D. Bruguera
title: Algorithm and Architecture for Logarithm, Exponential and Powering Computation
journal: j-IEEE-TRANS-COMPUT
volume: 53
number: 9
pages: 1085--1096
year: 2004
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2004.53
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jun 24 10:05:48 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 10:05:48 ???
URL: http://www.ac.usc.es/arquivos/articulos/2004/gac2004-j05.ps
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. A. Pi{\~n}eiro and M. D. Ercegovac and J. D. Bruguera
rawtitle: Algorithm and Architecture for Logarithm, Exponential and Powering Computation
entry:
@Article{Pineiro:2004:AAL,
  author =       "J. A. Pi{\~n}eiro and M. D. Ercegovac and J. D.
                 Bruguera",
  title =        "Algorithm and Architecture for Logarithm, Exponential
                 and Powering Computation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "53",
  number =       "9",
  pages =        "1085--1096",
  year =         "2004",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2004.53",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jun 24 10:05:48 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.ac.usc.es/arquivos/articulos/2004/gac2004-j05.ps",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Plouffe:2004:ILS
author: Simon Plouffe
title: Invited Lecture: A survey of Integer Relations algorithms and rational numbers [abstract only]
crossref: Frougny:2004:RCR
year: 2004
bibdate: Fri Nov 17 07:00:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.17 07:00:31 ???
URL: http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_02_plouffe.pdf
acknowledgement: ack-nhfb
rawauthor: Simon Plouffe
rawtitle: Invited Lecture: A survey of Integer Relations algorithms and rational numbers [abstract only]
abstract:
It is widely believed that Integer Relations algorithms such as LLL, Lattice reduction or PSLQ which are implemented in most computer algebra systems are generalizations of the Euclidian algorithm or the continued fraction algorithm.par We give simple examples of cases where the programs fails to find a solution and in general examples of problem that could hardly be solved using such tools.par Most of the examples are either large rational numbers or near rational numbers, the difference being so small that even very high precision do not guarantee to have results

keywords:
Algebraic numbers; Coordination sequences; Golden ratio; Integer Relations; Lattice Reduction; LLL; Pisot sequences; PSLQ; Zeolites

rawabstract:
It is widely believed that Integer Relations algorithms such as LLL, Lattice reduction or PSLQ which are implemented in most computer algebra systems are generalizations of the Euclidian algorithm or the continued fraction algorithm.\par We give simple examples of cases where the programs fails to find a solution and in general examples of problem that could hardly be solved using such tools.\par Most of the examples are either large rational numbers or near rational numbers, the difference being so small that even very high precision do not guarantee to have results

entry:
@InProceedings{Plouffe:2004:ILS,
  author =       "Simon Plouffe",
  title =        "Invited Lecture: A survey of Integer Relations
                 algorithms and rational numbers [abstract only]",
  crossref =     "Frougny:2004:RCR",
  pages =        "",
  year =         "2004",
  bibdate =      "Fri Nov 17 07:00:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_02_plouffe.pdf",
  abstract =     "It is widely believed that Integer Relations
                 algorithms such as LLL, Lattice reduction or PSLQ which
                 are implemented in most computer algebra systems are
                 generalizations of the Euclidian algorithm or the
                 continued fraction algorithm.\par

                 We give simple examples of cases where the programs
                 fails to find a solution and in general examples of
                 problem that could hardly be solved using such
                 tools.\par

                 Most of the examples are either large rational numbers
                 or near rational numbers, the difference being so small
                 that even very high precision do not guarantee to have
                 results",
  acknowledgement = ack-nhfb,
  keywords =     "Algebraic numbers; Coordination sequences; Golden
                 ratio; Integer Relations; Lattice Reduction; LLL; Pisot
                 sequences; PSLQ; Zeolites",
}


bibtype: article
filename: fparith.bib
label: Priest:2004:ESC
author: Douglas M. Priest
title: Efficient scaling for complex division
journal: j-TOMS
volume: 30
number: 4
pages: 389--401
month: dec
monthnumber: 12
year: 2004
CODEN: ACMSCU
DOI: https://doi.org/10.1145/1039813.1039814
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Tue Apr 12 06:34:31 MDT 2005
bibsource: http://www.acm.org/pubs/contents/journals/toms/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.12 06:34:31 MDT
fjournal: ACM Transactions on Mathematical Software (TOMS)
keywords: complex division
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/toms
rawauthor: Douglas M. Priest
rawtitle: Efficient scaling for complex division
abstract:
We develop a simple method for scaling to avoid overflow and harmful underflow in complex division. The method guarantees that no overflow will occur unless at least one component of the quotient must overflow, otherwise the normwise error in the computed result is at most a few units in the last place. Moreover, the scaling requires only four floating point multiplications and a small amount of integer arithmetic to compute the scale factor. Thus, on many modern CPUs, our method is both safer and faster than Smith's widely used algorithm.

rawabstract:
We develop a simple method for scaling to avoid overflow and harmful underflow in complex division. The method guarantees that no overflow will occur unless at least one component of the quotient must overflow, otherwise the normwise error in the computed result is at most a few units in the last place. Moreover, the scaling requires only four floating point multiplications and a small amount of integer arithmetic to compute the scale factor. Thus, on many modern CPUs, our method is both safer and faster than Smith's widely used algorithm.

entry:
@Article{Priest:2004:ESC,
  author =       "Douglas M. Priest",
  title =        "Efficient scaling for complex division",
  journal =      j-TOMS,
  volume =       "30",
  number =       "4",
  pages =        "389--401",
  month =        dec,
  year =         "2004",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/1039813.1039814",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Tue Apr 12 06:34:31 MDT 2005",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toms/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We develop a simple method for scaling to avoid
                 overflow and harmful underflow in complex division. The
                 method guarantees that no overflow will occur unless at
                 least one component of the quotient must overflow,
                 otherwise the normwise error in the computed result is
                 at most a few units in the last place. Moreover, the
                 scaling requires only four floating point
                 multiplications and a small amount of integer
                 arithmetic to compute the scale factor. Thus, on many
                 modern CPUs, our method is both safer and faster than
                 Smith's widely used algorithm.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "complex division",
}


bibtype: article
filename: fparith.bib
label: Putot:2004:SAB
author: Sylvie Putot and Eric Goubault and Matthieu Martel
title: Static Analysis-Based Validation of Floating-Point Computations
journal: j-LECT-NOTES-COMP-SCI
volume: 2991
pages: 306--313
year: 2004
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Wed Mar 10 06:51:00 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.03.10 06:51:00 ???
URL: http://www.springeronline.com/3-540-21260-4
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Sylvie Putot and Eric Goubault and Matthieu Martel
rawtitle: Static Analysis-Based Validation of Floating-Point Computations
entry:
@Article{Putot:2004:SAB,
  author =       "Sylvie Putot and Eric Goubault and Matthieu Martel",
  title =        "Static Analysis-Based Validation of Floating-Point
                 Computations",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2991",
  pages =        "306--313",
  year =         "2004",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Wed Mar 10 06:51:00 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springeronline.com/3-540-21260-4",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Quach:2004:SIR
author: N. T. Quach and N. Takagi and M. J. Flynn
title: Systematic IEEE rounding method for high-speed floating-point multipliers
journal: j-IEEE-TRANS-VLSI-SYST
volume: 12
number: 5
pages: 511--521
month: may
monthnumber: 5
year: 2004
CODEN: IEVSE9
DOI: https://doi.org/10.1109/TVLSI.2004.825860
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Sat Jul 16 11:25:05 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:05 MDT
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: N. T. Quach and N. Takagi and M. J. Flynn
rawtitle: Systematic {IEEE} rounding method for high-speed floating-point multipliers
abstract:
For performance reasons, many high-speed floating-point multipliers today precompute multiple significand values (SVs) in advance. The final normalization and rounding steps are then performed by selecting the appropriate SV. While having speed advantages, this integrated rounding method complicates the development of the rounding logic significantly, hence, requiring a systematic rounding method.

rawabstract:
For performance reasons, many high-speed floating-point multipliers today precompute multiple significand values (SVs) in advance. The final normalization and rounding steps are then performed by selecting the appropriate SV. While having speed advantages, this integrated rounding method complicates the development of the rounding logic significantly, hence, requiring a systematic rounding method.

entry:
@Article{Quach:2004:SIR,
  author =       "N. T. Quach and N. Takagi and M. J. Flynn",
  title =        "Systematic {IEEE} rounding method for high-speed
                 floating-point multipliers",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "12",
  number =       "5",
  pages =        "511--521",
  month =        may,
  year =         "2004",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2004.825860",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Jul 16 11:25:05 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "For performance reasons, many high-speed
                 floating-point multipliers today precompute multiple
                 significand values (SVs) in advance. The final
                 normalization and rounding steps are then performed by
                 selecting the appropriate SV. While having speed
                 advantages, this integrated rounding method complicates
                 the development of the rounding logic significantly,
                 hence, requiring a systematic rounding method.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
  summary =      "For performance reasons, many high-speed
                 floating-point multipliers today precompute multiple
                 significand values (SVs) in advance. The final
                 normalization and rounding steps are then performed by
                 selecting the appropriate SV. While having speed
                 advantages \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Radecka:2004:DVT
author: K. Radecka and Z. Zilic
title: Design verification by test vectors and arithmetic transform universal test set
journal: j-IEEE-TRANS-COMPUT
volume: 53
number: 5
pages: 628--640
month: may
monthnumber: 5
year: 2004
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2004.1275301
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 08:12:36 MDT 2011
bibtimestamp: 2011.07.05 08:12:36 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1275301
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: K. Radecka and Z. Zilic
rawtitle: Design verification by test vectors and arithmetic transform universal test set
entry:
@Article{Radecka:2004:DVT,
  author =       "K. Radecka and Z. Zilic",
  title =        "Design verification by test vectors and arithmetic
                 transform universal test set",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "53",
  number =       "5",
  pages =        "628--640",
  month =        may,
  year =         "2004",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2004.1275301",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 08:12:36 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1275301",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Rettinger:2004:FAJ
author: R. Rettinger
title: A Fast Algorithm for Julia Sets of Hyperbolic Rational Functions
crossref: Frougny:2004:RCR
pages: 158--171
year: 2004
bibdate: Fri Nov 17 07:00:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.17 07:00:31 ???
URL: http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_13_rettinger.pdf
keywords: Computational Complexity; Julia Sets
acknowledgement: ack-nhfb
rawauthor: R. Rettinger
rawtitle: A Fast Algorithm for {Julia} Sets of Hyperbolic Rational Functions
abstract:
Although numerous computer programs have been written to compute sets of points which claim to approximate Julia sets, no reliable high precision pictures of nontrivial Julia sets are currently known. Usually, no error estimates are added and even those algorithms which work reliable in theory, become unreliable in practice due to rounding errors and the use of fixed length floating point numbers.par In this paper we prove the existence of polynomial time algorithms to approximate the Julia sets of given hyperbolic rational functions. We will give a strict computable error estimation w.r.t. the Hausdorff metric on the complex sphere. This extends a result on polynomials $ z to z^2 + c $, where $ |c| < 1 / 4 $, in [RW03] and an earlier result in [Zho98] on the recursiveness of the Julia sets of hyperbolic polynomials.par The algorithm given in this paper computes Julia sets locally in time $ O(k cdot M(k)) $ (where $ M(k) $ denotes the time needed to multiply two $k$-bit numbers). Roughly speaking, the local time complexity is the number of Turing machine steps to decide a set of disks of spherical diameter $ 2^-k$ so that the union of these disks has Hausdorff distance at most $ 2^-k + 2$. This allows to give reliable pictures of Julia sets to arbitrary precision.

rawabstract:
Although numerous computer programs have been written to compute sets of points which claim to approximate Julia sets, no reliable high precision pictures of nontrivial Julia sets are currently known. Usually, no error estimates are added and even those algorithms which work reliable in theory, become unreliable in practice due to rounding errors and the use of fixed length floating point numbers.\par In this paper we prove the existence of polynomial time algorithms to approximate the Julia sets of given hyperbolic rational functions. We will give a strict computable error estimation w.r.t. the Hausdorff metric on the complex sphere. This extends a result on polynomials $ z \to z^2 + c $, where $ |c| < 1 / 4 $, in [RW03] and an earlier result in [Zho98] on the recursiveness of the Julia sets of hyperbolic polynomials.\par The algorithm given in this paper computes Julia sets locally in time $ O(k \cdot M(k)) $ (where $ M(k) $ denotes the time needed to multiply two $k$-bit numbers). Roughly speaking, the local time complexity is the number of Turing machine steps to decide a set of disks of spherical diameter $ 2^{-k}$ so that the union of these disks has Hausdorff distance at most $ 2^{-k + 2}$. This allows to give reliable pictures of Julia sets to arbitrary precision.

entry:
@InProceedings{Rettinger:2004:FAJ,
  author =       "R. Rettinger",
  title =        "A Fast Algorithm for {Julia} Sets of Hyperbolic
                 Rational Functions",
  crossref =     "Frougny:2004:RCR",
  pages =        "158--171",
  year =         "2004",
  bibdate =      "Fri Nov 17 07:00:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_13_rettinger.pdf",
  abstract =     "Although numerous computer programs have been written
                 to compute sets of points which claim to approximate
                 Julia sets, no reliable high precision pictures of
                 nontrivial Julia sets are currently known. Usually, no
                 error estimates are added and even those algorithms
                 which work reliable in theory, become unreliable in
                 practice due to rounding errors and the use of fixed
                 length floating point numbers.\par

                 In this paper we prove the existence of polynomial time
                 algorithms to approximate the Julia sets of given
                 hyperbolic rational functions. We will give a strict
                 computable error estimation w.r.t. the Hausdorff metric
                 on the complex sphere. This extends a result on
                 polynomials $ z \to z^2 + c $, where $ |c| < 1 / 4 $,
                 in [RW03] and an earlier result in [Zho98] on the
                 recursiveness of the Julia sets of hyperbolic
                 polynomials.\par

                 The algorithm given in this paper computes Julia sets
                 locally in time $ O(k \cdot M(k)) $ (where $ M(k) $
                 denotes the time needed to multiply two $k$-bit
                 numbers). Roughly speaking, the local time complexity
                 is the number of Turing machine steps to decide a set
                 of disks of spherical diameter $ 2^{-k}$ so that the
                 union of these disks has Hausdorff distance at most $
                 2^{-k + 2}$. This allows to give reliable pictures of
                 Julia sets to arbitrary precision.",
  acknowledgement = ack-nhfb,
  keywords =     "Computational Complexity; Julia Sets",
}


bibtype: article
filename: fparith.bib
label: Reyhani-Masoleh:2004:EDS
author: Arash Reyhani-Masoleh and M. Anwar Hasan
title: Efficient digit-serial normal basis multipliers over binary extension fields
journal: j-TECS
volume: 3
number: 3
pages: 575--592
month: aug
monthnumber: 8
year: 2004
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Fri Oct 29 06:35:47 MDT 2004
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.10.29 06:35:47 MDT
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?&idx=J840
rawauthor: Arash Reyhani-Masoleh and M. Anwar Hasan
rawtitle: Efficient digit-serial normal basis multipliers over binary extension fields
entry:
@Article{Reyhani-Masoleh:2004:EDS,
  author =       "Arash Reyhani-Masoleh and M. Anwar Hasan",
  title =        "Efficient digit-serial normal basis multipliers over
                 binary extension fields",
  journal =      j-TECS,
  volume =       "3",
  number =       "3",
  pages =        "575--592",
  month =        aug,
  year =         "2004",
  CODEN =        "????",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Fri Oct 29 06:35:47 MDT 2004",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?&idx=J840",
}


bibtype: article
filename: fparith.bib
label: Reyhani-Masoleh:2004:LCB
author: A. Reyhani-Masoleh and M. A. Hasan
title: Low complexity bit parallel architectures for polynomial basis multiplication over $ rm GF(2^m) $
journal: j-IEEE-TRANS-COMPUT
volume: 53
number: 8
pages: 945--959
month: aug
monthnumber: 8
year: 2004
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2004.47
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 08:12:40 MDT 2011
bibtimestamp: 2011.07.05 08:12:40 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1306989
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Reyhani-Masoleh and M. A. Hasan
rawtitle:
Low complexity bit parallel architectures for polynomial basis multiplication over {$ {\rm GF}(2^m) $}

entry:
@Article{Reyhani-Masoleh:2004:LCB,
  author =       "A. Reyhani-Masoleh and M. A. Hasan",
  title =        "Low complexity bit parallel architectures for
                 polynomial basis multiplication over {$ {\rm GF}(2^m)
                 $}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "53",
  number =       "8",
  pages =        "945--959",
  month =        aug,
  year =         "2004",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2004.47",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 08:12:40 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1306989",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Riley:2004:HAE
author: Joseph Riley and Michael J. Schulte
title: A Hardware Accelerator for Elliptic Curve Cryptography over $ mathrm GF(2^m) $
journal: j-INT-J-COMP-RESEARCH
pages: ??--??
year: 2004
ISSN: 1535-6698 OR 15356698
bibdate: Sun Mar 04 20:54:26 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 20:54:26 ???
note: Special Issue on Cryptographic Hardware and Embedded Systems
URL: http://mesa.ece.wisc.edu/publications/cp_2004-10.pdf
fjournal: International Journal of Computer Research
acknowledgement: ack-nhfb
rawauthor: Joseph Riley and Michael J. Schulte
rawnote: Special Issue on Cryptographic Hardware and Embedded Systems
rawtitle: A Hardware Accelerator for Elliptic Curve Cryptography over {$ \mathrm {GF}(2^m) $}
entry:
@Article{Riley:2004:HAE,
  author =       "Joseph Riley and Michael J. Schulte",
  title =        "A Hardware Accelerator for Elliptic Curve Cryptography
                 over {$ \mathrm {GF}(2^m) $}",
  journal =      j-INT-J-COMP-RESEARCH,
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  year =         "2004",
  ISSN =         "1535-6698",
  bibdate =      "Sun Mar 04 20:54:26 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Special Issue on Cryptographic Hardware and Embedded
                 Systems",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2004-10.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of Computer Research",
}


bibtype: inproceedings
filename: fparith.bib
label: Roy:2004:ACF
author: S. Roy and P. Banerjee
booktitle: Proceedings. 41st Design Automation Conference, June 7--11, 2004
title: An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 484--487
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: S. Roy and P. Banerjee
rawbooktitle: Proceedings. 41st Design Automation Conference, June 7--11, 2004
rawtitle:
An algorithm for converting floating-point computations to fixed-point in {MATLAB} based {FPGA} design

entry:
@InProceedings{Roy:2004:ACF,
  author =       "S. Roy and P. Banerjee",
  booktitle =    "Proceedings. 41st Design Automation Conference, June
                 7--11, 2004",
  title =        "An algorithm for converting floating-point
                 computations to fixed-point in {MATLAB} based {FPGA}
                 design",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "484--487",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Sadaghdar:2004:BFP
author: M. Sadaghdar and K. Iniewski and M. Syrzycki
booktitle: Canadian Conference on Electrical and Computer Engineering, 2--5 May 2004
title: 11-bit floating-point pipelined analog to digital converter in 0.18$ mu $ m CMOS
volume: 3
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1503--1506
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: M. Sadaghdar and K. Iniewski and M. Syrzycki
rawbooktitle: Canadian Conference on Electrical and Computer Engineering, 2--5 May 2004
rawtitle: 11-bit floating-point pipelined analog to digital converter in 0.18$ \mu $ m {CMOS}
entry:
@InProceedings{Sadaghdar:2004:BFP,
  author =       "M. Sadaghdar and K. Iniewski and M. Syrzycki",
  booktitle =    "Canadian Conference on Electrical and Computer
                 Engineering, 2--5 May 2004",
  title =        "11-bit floating-point pipelined analog to digital
                 converter in 0.18$ \mu $ m {CMOS}",
  volume =       "3",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1503--1506",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Schimmler:2004:BSF
author: Manfred Schimmler and Bertil Schmidt and Hans-Werner Lang
title: A bit-serial floating-point unit for a massively parallel system on a chip
journal: j-PARALLEL-ALGORITHMS-APPL
volume: 19
number: 2-3
pages: 79--95
year: 2004
CODEN: PAAPEC
ISSN: 1063-7192 OR 10637192
ISSNL: 1026-7689 OR 10267689
MRclass: Database Expansion Item
MRnumber: MR2113359
bibdate: Thu Nov 8 19:16:14 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 19:16:14 ???
fjournal: Parallel Algorithms and Applications
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/gpaa20
rawauthor: Manfred Schimmler and Bertil Schmidt and Hans-Werner Lang
rawtitle: A bit-serial floating-point unit for a massively parallel system on a chip
entry:
@Article{Schimmler:2004:BSF,
  author =       "Manfred Schimmler and Bertil Schmidt and Hans-Werner
                 Lang",
  title =        "A bit-serial floating-point unit for a massively
                 parallel system on a chip",
  journal =      j-PARALLEL-ALGORITHMS-APPL,
  volume =       "19",
  number =       "2-3",
  pages =        "79--95",
  year =         "2004",
  CODEN =        "PAAPEC",
  ISSN =         "1063-7192",
  ISSN-L =       "1026-7689",
  MRclass =      "Database Expansion Item",
  MRnumber =     "MR2113359",
  bibdate =      "Thu Nov 8 19:16:14 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Parallel Algorithms and Applications",
  journal-URL =  "http://www.tandfonline.com/loi/gpaa20",
}


bibtype: inproceedings
filename: fparith.bib
label: Schirra:2004:ILR
author: Stefan Schirra
title: Invited Lecture: Real Numbers and Robustness in Computational Geometry
crossref: Frougny:2004:RCR
pages: 7--21
year: 2004
bibdate: Fri Nov 17 07:00:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.17 07:00:31 ???
URL: http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_03_schirra.pdf
keywords: computational geometry; exact geometric computation; robustness
acknowledgement: ack-nhfb
rawauthor: Stefan Schirra
rawtitle: Invited Lecture: Real Numbers and Robustness in Computational Geometry
abstract:
Robustness issues due to imprecise arithmetic used in place of exact real number computation are a notorious problem in the implementation of geometric algorithms. We briefly address some robustness issues and discuss approaches to resolve them.

rawabstract:
Robustness issues due to imprecise arithmetic used in place of exact real number computation are a notorious problem in the implementation of geometric algorithms. We briefly address some robustness issues and discuss approaches to resolve them.

entry:
@InProceedings{Schirra:2004:ILR,
  author =       "Stefan Schirra",
  title =        "Invited Lecture: Real Numbers and Robustness in
                 Computational Geometry",
  crossref =     "Frougny:2004:RCR",
  pages =        "7--21",
  year =         "2004",
  bibdate =      "Fri Nov 17 07:00:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_03_schirra.pdf",
  abstract =     "Robustness issues due to imprecise arithmetic used in
                 place of exact real number computation are a notorious
                 problem in the implementation of geometric algorithms.
                 We briefly address some robustness issues and discuss
                 approaches to resolve them.",
  acknowledgement = ack-nhfb,
  keywords =     "computational geometry; exact geometric computation;
                 robustness",
}


bibtype: techreport
filename: fparith.bib
label: Schulte:2004:DED
author: Michael J. Schulte and Eric Schwarz
type: Technical report
institution: University of Wisconsin-Madison and IBM Systems and Technology Group
address: Madison, WI, USA
pages: 4
day: 11
month: mar
monthnumber: 3
year: 2004
bibdate: Sat Mar 03 19:24:05 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.03 19:24:05 ???
URL: http://domino.research.ibm.com/acas/w3www_acas.nsf/images/proposals_04.05/%24FILE/schulte.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Michael J. Schulte and Eric Schwarz
title:
Design Exploration for Decimal Floating-Point Arithmetic IBM University Partnership Program Proposal

rawtitle:
Design Exploration for Decimal Floating-Point Arithmetic {IBM} University Partnership Program Proposal

entry:
@TechReport{Schulte:2004:DED,
  author =       "Michael J. Schulte and Eric Schwarz",
  title =        "Design Exploration for Decimal Floating-Point
                 Arithmetic {IBM} University Partnership Program
                 Proposal",
  type =         "Technical report",
  institution =  "University of Wisconsin-Madison and IBM Systems and
                 Technology Group",
  address =      "Madison, WI, USA",
  pages =        "4",
  day =          "11",
  month =        mar,
  year =         "2004",
  bibdate =      "Sat Mar 03 19:24:05 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://domino.research.ibm.com/acas/w3www_acas.nsf/images/proposals_04.05/%24FILE/schulte.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:2004:LPC
title: A Low-Power Carry Skip Adder with Fast Saturation
crossref: IEEE:2004:IICb
pages: 269--279
year: 2004
bibdate: Sun Mar 04 20:56:38 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 20:56:38 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2004-11.pdf
acknowledgement: ack-nhfb
rawtitle: A Low-Power Carry Skip Adder with Fast Saturation
author:
M. J. Schulte and K. Chirca and J. Glossner and H. Wang and S. Mamidi and P. I. Balzola and S. Vassiliadis

rawauthor:
M. J. Schulte and K. Chirca and J. Glossner and H. Wang and S. Mamidi and P. I. Balzola and S. Vassiliadis

entry:
@InProceedings{Schulte:2004:LPC,
  author =       "M. J. Schulte and K. Chirca and J. Glossner and H.
                 Wang and S. Mamidi and P. I. Balzola and S.
                 Vassiliadis",
  title =        "A Low-Power Carry Skip Adder with Fast Saturation",
  crossref =     "IEEE:2004:IICb",
  pages =        "269--279",
  year =         "2004",
  bibdate =      "Sun Mar 04 20:56:38 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2004-11.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Seidel:2004:DOI
author: P.-M. Seidel and G. Even
title: Delay-optimized implementation of IEEE floating-point addition
journal: j-IEEE-TRANS-COMPUT
volume: 53
number: 2
pages: 97--113
month: feb
monthnumber: 2
year: 2004
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2004.1261822
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 08:12:30 MDT 2011
bibtimestamp: 2011.07.05 08:12:30 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261822
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: P.-M. Seidel and G. Even
rawtitle: Delay-optimized implementation of {IEEE} floating-point addition
abstract:
We present an IEEE floating-point adder (FP-adder) design. The adder accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly normalized rounded sum / difference in the format required by the IEEE Standard.

rawabstract:
We present an IEEE floating-point adder (FP-adder) design. The adder accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly normalized rounded sum\slash difference in the format required by the IEEE Standard.

entry:
@Article{Seidel:2004:DOI,
  author =       "P.-M. Seidel and G. Even",
  title =        "Delay-optimized implementation of {IEEE}
                 floating-point addition",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "53",
  number =       "2",
  pages =        "97--113",
  month =        feb,
  year =         "2004",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2004.1261822",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 08:12:30 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261822",
  abstract =     "We present an IEEE floating-point adder (FP-adder)
                 design. The adder accepts normalized numbers, supports
                 all four IEEE rounding modes, and outputs the correctly
                 normalized rounded sum\slash difference in the format
                 required by the IEEE Standard.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "We present an IEEE floating-point adder (FP-adder)
                 design. The adder accepts normalized numbers, supports
                 all four IEEE rounding modes, and outputs the correctly
                 normalized rounded sum/difference in the format
                 required by the IEEE Standard. The FP-adder \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Seidel:2004:LIF
author: P.-M. Seidel
title: On-line IEEE floating-point multiplication and division for reduced power dissipation
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 498--502
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: P.-M. Seidel
rawtitle: On-line {IEEE} floating-point multiplication and division for reduced power dissipation
booktitle:
Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, Nov. 7--10, 2004

entry:
@InProceedings{Seidel:2004:LIF,
  author =       "P.-M. Seidel",
  booktitle =    "Conference Record of the Thirty-Eighth Asilomar
                 Conference on Signals, Systems and Computers, Nov.
                 7--10, 2004",
  title =        "On-line {IEEE} floating-point multiplication and
                 division for reduced power dissipation",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "498--502",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Shi:2004:FPF
author: Changchun Shi and R. W. Brodersen
title: Floating-point to fixed-point conversion with decision errors due to quantization
crossref: IEEE:2004:IICc
volume: 5
publisher: pub-IEEE
address: pub-IEEE:adr
pages: V-41--V-44
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: Changchun Shi and R. W. Brodersen
rawtitle: Floating-point to fixed-point conversion with decision errors due to quantization
entry:
@InProceedings{Shi:2004:FPF,
  author =       "Changchun Shi and R. W. Brodersen",
  title =        "Floating-point to fixed-point conversion with decision
                 errors due to quantization",
  crossref =     "IEEE:2004:IICc",
  volume =       "5",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "V-41--V-44",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Steele:2004:RHP
author: Guy L. Steele Jr. and Jon L. White
title: Retrospective: How to Print Floating-Point Numbers Accurately
journal: j-SIGPLAN
volume: 39
number: 4
pages: 372--389
month: apr
monthnumber: 4
year: 2004
CODEN: SINODQ
DOI: https://doi.org/10.1145/989393.989431
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Tue Jun 15 10:00:43 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.06.15 10:00:43 ???
note: Best of PLDI 1979--1999. Reprint of, and retrospective on, cite Steele:1990:HPF.
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Guy L. {Steele Jr.} and Jon L. White
rawnote: Best of PLDI 1979--1999. Reprint of, and retrospective on, \cite{Steele:1990:HPF}.
rawtitle: Retrospective: How to Print Floating-Point Numbers Accurately
abstract:
We present algorithms for accurately converting floating-point numbers to decimal representation. The key idea is to carry along with the computation an explicit representation of the required rounding accuracy. We begin with the simpler problem of converting fixed-point fractions. A modification of the well-known algorithm for radix-conversion of fixed-point fractions by multiplication explicitly determines when to terminate the conversion process; a variable number of digits are produced. The algorithm has these properties: (*) No information is lost; the original fraction can be recovered from the output by rounding. (*) No ``garbage digits'' are produced. (*) The output is correctly rounded. (*) It is never necessary to propagate carries on rounding. We then derive two algorithms for free-format out-put of floating-point numbers. The first simply scales the given floating-point number to an appropriate fractional range and then applies the algorithm for fractions. This is quite fast and simple to code but has inaccuracies stemming from round-off errors and oversimplification. The second algorithm guarantees mathematical accuracy by using multiple-precision integer arithmetic and handling special cases. Both algorithms produce no more digits than necessary (intuitively, the ``1.3 prints as 1.2999999'' problem does not occur). Finally, we modify the free-format conversion algorithm for use in fixed-format applications. Information may be lost if the fixed format provides too few digit positions, but the output is always correctly rounded. On the other hand, no ``garbage digits'' are ever produced, even if the fixed format specifies too many digit positions (intuitively, the ``4/3 prints as 1.333333328366279602'' problem does not occur).

rawabstract:
We present algorithms for accurately converting floating-point numbers to decimal representation. The key idea is to carry along with the computation an explicit representation of the required rounding accuracy. We begin with the simpler problem of converting fixed-point fractions. A modification of the well-known algorithm for radix-conversion of fixed-point fractions by multiplication explicitly determines when to terminate the conversion process; a variable number of digits are produced. The algorithm has these properties: (*) No information is lost; the original fraction can be recovered from the output by rounding. (*) No ``garbage digits'' are produced. (*) The output is correctly rounded. (*) It is never necessary to propagate carries on rounding. We then derive two algorithms for free-format out-put of floating-point numbers. The first simply scales the given floating-point number to an appropriate fractional range and then applies the algorithm for fractions. This is quite fast and simple to code but has inaccuracies stemming from round-off errors and oversimplification. The second algorithm guarantees mathematical accuracy by using multiple-precision integer arithmetic and handling special cases. Both algorithms produce no more digits than necessary (intuitively, the ``1.3 prints as 1.2999999'' problem does not occur). Finally, we modify the free-format conversion algorithm for use in fixed-format applications. Information may be lost if the fixed format provides too few digit positions, but the output is always correctly rounded. On the other hand, no ``garbage digits'' are ever produced, even if the fixed format specifies too many digit positions (intuitively, the ``4/3 prints as 1.333333328366279602'' problem does not occur).

entry:
@Article{Steele:2004:RHP,
  author =       "Guy L. {Steele Jr.} and Jon L. White",
  title =        "Retrospective: How to Print Floating-Point Numbers
                 Accurately",
  journal =      j-SIGPLAN,
  volume =       "39",
  number =       "4",
  pages =        "372--389",
  month =        apr,
  year =         "2004",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/989393.989431",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Tue Jun 15 10:00:43 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Best of PLDI 1979--1999. Reprint of, and retrospective
                 on, \cite{Steele:1990:HPF}.",
  abstract =     "We present algorithms for accurately converting
                 floating-point numbers to decimal representation. The
                 key idea is to carry along with the computation an
                 explicit representation of the required rounding
                 accuracy. We begin with the simpler problem of
                 converting fixed-point fractions. A modification of the
                 well-known algorithm for radix-conversion of
                 fixed-point fractions by multiplication explicitly
                 determines when to terminate the conversion process; a
                 variable number of digits are produced. The algorithm
                 has these properties: (*) No information is lost; the
                 original fraction can be recovered from the output by
                 rounding. (*) No ``garbage digits'' are produced. (*)
                 The output is correctly rounded. (*) It is never
                 necessary to propagate carries on rounding. We then
                 derive two algorithms for free-format out-put of
                 floating-point numbers. The first simply scales the
                 given floating-point number to an appropriate
                 fractional range and then applies the algorithm for
                 fractions. This is quite fast and simple to code but
                 has inaccuracies stemming from round-off errors and
                 oversimplification. The second algorithm guarantees
                 mathematical accuracy by using multiple-precision
                 integer arithmetic and handling special cases. Both
                 algorithms produce no more digits than necessary
                 (intuitively, the ``1.3 prints as 1.2999999'' problem
                 does not occur). Finally, we modify the free-format
                 conversion algorithm for use in fixed-format
                 applications. Information may be lost if the fixed
                 format provides too few digit positions, but the output
                 is always correctly rounded. On the other hand, no
                 ``garbage digits'' are ever produced, even if the fixed
                 format specifies too many digit positions (intuitively,
                 the ``4/3 prints as 1.333333328366279602'' problem does
                 not occur).",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
}


bibtype: misc
filename: fparith.bib
label: Stehle:2004:GAT
author: D. Stehle and P. Zimmermann
title: Gal's Accurate Tables Method Revisited
pages: 372--389
year: 2004
bibdate: Fri Jun 24 14:56:03 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 14:56:03 ???
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: D. Stehl{\'e} and P. Zimmermann
rawtitle: {Gal}'s Accurate Tables Method Revisited
URL:
http://www.loria.fr/~stehle/downloads/2x-double.txt; http://www.loria.fr/~stehle/downloads/sincos-double.txt; http://www.loria.fr/~stehle/IMPROVEDGAL.html

abstract:
Gal's accurate tables algorithm aims at providing an efficient implementation of elementary functions with correct rounding as often as possible. This method requires an expensive pre-computation of a table made of the values taken by the function --- or by several related functions --- at some distinguished points. Our improvements of Gal's method are two-fold: on the one hand we describe what is the arguably best set of distinguished values and how it improves the efficiency and correctness of the implementation of the function, and on the other hand we give an algorithm which drastically decreases the cost of the pre-computation. These improvements are related to the worst cases for the correct rounding of mathematical functions and to the algorithms for finding them. We show that the whole method can be turned into practice by giving complete tables for $ 2^x $ and $ sin x $ for $x$ in $ [1 / 2, 1) $, in double precision.par Here are the two tables mentioned in the article: the $ sin x $ table and the $ 2^x $ table.par Erratum in the final version of the paper: in Section 4, the simultaneous worst case for sin and cos is t0 = 1f09c0c6cde5e3 and not t0 = 31a93fddd45e3.

rawabstract:
Gal's accurate tables algorithm aims at providing an efficient implementation of elementary functions with correct rounding as often as possible. This method requires an expensive pre-computation of a table made of the values taken by the function --- or by several related functions --- at some distinguished points. Our improvements of Gal's method are two-fold: on the one hand we describe what is the arguably best set of distinguished values and how it improves the efficiency and correctness of the implementation of the function, and on the other hand we give an algorithm which drastically decreases the cost of the pre-computation. These improvements are related to the worst cases for the correct rounding of mathematical functions and to the algorithms for finding them. We show that the whole method can be turned into practice by giving complete tables for $ 2^x $ and $ \sin x $ for $x$ in $ [1 / 2, 1) $, in double precision.\par Here are the two tables mentioned in the article: the $ \sin x $ table and the $ 2^x $ table.\par Erratum in the final version of the paper: in Section 4, the simultaneous worst case for sin and cos is t0 = 1f09c0c6cde5e3 and not t0 = 31a93fddd45e3.

entry:
@Misc{Stehle:2004:GAT,
  author =       "D. Stehl{\'e} and P. Zimmermann",
  title =        "{Gal}'s Accurate Tables Method Revisited",
  howpublished = "World-Wide Web document",
  year =         "2004",
  bibdate =      "Fri Jun 24 14:56:03 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.loria.fr/~stehle/downloads/2x-double.txt;
                 http://www.loria.fr/~stehle/downloads/sincos-double.txt;
                 http://www.loria.fr/~stehle/IMPROVEDGAL.html",
  abstract =     "Gal's accurate tables algorithm aims at providing an
                 efficient implementation of elementary functions with
                 correct rounding as often as possible. This method
                 requires an expensive pre-computation of a table made
                 of the values taken by the function --- or by several
                 related functions --- at some distinguished points. Our
                 improvements of Gal's method are two-fold: on the one
                 hand we describe what is the arguably best set of
                 distinguished values and how it improves the efficiency
                 and correctness of the implementation of the function,
                 and on the other hand we give an algorithm which
                 drastically decreases the cost of the pre-computation.
                 These improvements are related to the worst cases for
                 the correct rounding of mathematical functions and to
                 the algorithms for finding them. We show that the whole
                 method can be turned into practice by giving complete
                 tables for $ 2^x $ and $ \sin x $ for $x$ in $ [1 / 2,
                 1) $, in double precision.\par

                 Here are the two tables mentioned in the article: the $
                 \sin x $ table and the $ 2^x $ table.\par

                 Erratum in the final version of the paper: in Section
                 4, the simultaneous worst case for sin and cos is t0 =
                 1f09c0c6cde5e3 and not t0 = 31a93fddd45e3.",
  acknowledgement = ack-nhfb,
}


bibtype: book
filename: fparith.bib
label: Stine:2004:DCA
author: James E. Stine
title: Digital computer arithmetic datapath design using Verilog HDL
publisher: pub-KLUWER
address: pub-KLUWER:adr
pages: xi + 180
year: 2004
ISBN: 1-4020-7710-6 OR 1402077106
ISBN13: 978-1-4020-7710-4 OR 9781402077104
LCCN: TK7868.D5 S75 2004
bibdate: Thu Nov 18 09:03:42 MST 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; z3950.loc.gov:7090/Voyager
bibtimestamp: 2010.11.18 09:03:42 MST
subject: Digital electronics; Verilog (Computer hardware description language); Computer arithmetic
acknowledgement: ack-nhfb
rawauthor: James E. Stine
rawtitle: Digital computer arithmetic datapath design using {Verilog HDL}
URL:
http://www.loc.gov/catdir/enhancements/fy0820/2003064036-d.html; http://www.loc.gov/catdir/enhancements/fy0820/2003064036-t.html

keywords:
computer arithmetic; computers / cad-cam; computers / hardware / personal computers / general; computers / logic design; computers / programming languages / general; computers / systems architecture / general; digital electronics; mathematics / discrete mathematics; technology & engineering / electrical; technology & engineering / electronics / circuits / general; technology & engineering / electronics / digital; Verilog (computer hardware description language)

entry:
@Book{Stine:2004:DCA,
  author =       "James E. Stine",
  title =        "Digital computer arithmetic datapath design using
                 {Verilog HDL}",
  publisher =    pub-KLUWER,
  address =      pub-KLUWER:adr,
  pages =        "xi + 180",
  year =         "2004",
  ISBN =         "1-4020-7710-6",
  ISBN-13 =      "978-1-4020-7710-4",
  LCCN =         "TK7868.D5 S75 2004",
  bibdate =      "Thu Nov 18 09:03:42 MST 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 z3950.loc.gov:7090/Voyager",
  URL =          "http://www.loc.gov/catdir/enhancements/fy0820/2003064036-d.html;
                 http://www.loc.gov/catdir/enhancements/fy0820/2003064036-t.html",
  acknowledgement = ack-nhfb,
  keywords =     "computer arithmetic; computers / cad-cam; computers /
                 hardware / personal computers / general; computers /
                 logic design; computers / programming languages /
                 general; computers / systems architecture / general;
                 digital electronics; mathematics / discrete
                 mathematics; technology \& engineering / electrical;
                 technology \& engineering / electronics / circuits /
                 general; technology \& engineering / electronics /
                 digital; Verilog (computer hardware description
                 language)",
  subject =      "Digital electronics; Verilog (Computer hardware
                 description language); Computer arithmetic",
}


bibtype: misc
filename: fparith.bib
label: Sun:2004:LBR
author: Sun Microsystems, Inc.
pages: xi + 180
year: 2004
bibdate: Fri Jun 24 14:59:44 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 14:59:44 ???
URL: http://www.sun.com/download/products.xml?id=41797765
acknowledgement: ack-nhfb
howpublished: World-Wide Web software project archive
rawauthor: {Sun Microsystems, Inc.}
title:
Libmcr 0.9 beta: a reference correctly-rounded library of basic double-precision transcendental elementary functions

rawtitle:
Libmcr 0.9 beta: a reference correctly-rounded library of basic double-precision transcendental elementary functions

entry:
@Misc{Sun:2004:LBR,
  author =       "{Sun Microsystems, Inc.}",
  title =        "Libmcr 0.9 beta: a reference correctly-rounded library
                 of basic double-precision transcendental elementary
                 functions",
  howpublished = "World-Wide Web software project archive",
  year =         "2004",
  bibdate =      "Fri Jun 24 14:59:44 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sun.com/download/products.xml?id=41797765",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Sunar:2004:GMC
author: B. Sunar
title: A generalized method for constructing subquadratic complexity $ mathrm GF(2^k) $ multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 53
number: 9
pages: 1097--1105
month: sep
monthnumber: 9
year: 2004
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2004.52
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jun 24 21:17:30 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 21:17:30 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: B. Sunar
rawtitle: A generalized method for constructing subquadratic complexity {$ \mathrm {GF}(2^k) $} multipliers
entry:
@Article{Sunar:2004:GMC,
  author =       "B. Sunar",
  title =        "A generalized method for constructing subquadratic
                 complexity {$ \mathrm {GF}(2^k) $} multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "53",
  number =       "9",
  pages =        "1097--1105",
  month =        sep,
  year =         "2004",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2004.52",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jun 24 21:17:30 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Sypniewski:2004:IAU
author: M. Sypniewski and W. K. Gwarek
booktitle: 2004 IEEE MTT-S International Microwave Symposium Digest. 6--11 June 2004
title: On the influence of arithmetic underflow rounding standard on the speed of FDTD modeling
volume: 3
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1795--1798
year: 2004
bibdate: Sat Jul 16 11:25:06 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:06 MDT
acknowledgement: ack-nhfb
rawauthor: M. Sypniewski and W. K. Gwarek
rawbooktitle: 2004 {IEEE} {MTT-S} International Microwave Symposium Digest. 6--11 June 2004
rawtitle: On the influence of arithmetic underflow rounding standard on the speed of {FDTD} modeling
entry:
@InProceedings{Sypniewski:2004:IAU,
  author =       "M. Sypniewski and W. K. Gwarek",
  booktitle =    "2004 {IEEE} {MTT-S} International Microwave Symposium
                 Digest. 6--11 June 2004",
  title =        "On the influence of arithmetic underflow rounding
                 standard on the speed of {FDTD} modeling",
  volume =       "3",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1795--1798",
  year =         "2004",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:06 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "This paper presents the influence of arithmetic
                 underflow rounding operations on the speed of FDTD
                 analysis. It is shown that the underflow treatment
                 according to the IEEE standard 754 (commonly accepted
                 and implemented in modern arithmetic \ldots{}).",
}


bibtype: inproceedings
filename: fparith.bib
label: Tadaki:2004:ECH
author: Kohtaro Tadaki
crossref: Frougny:2004:RCR
pages: 172--191
year: 2004
bibdate: Fri Nov 17 07:00:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.17 07:00:31 ???
URL: http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_14_tadaki.pdf
acknowledgement: ack-nhfb
rawauthor: Kohtaro Tadaki
title:
An extension of Chaitin's halting probability $ Omega $ to measurement operator in infinite dimensional quantum system

abstract:
This paper proposes an extension of Chaitin's halting probability $ Omega $ to measurement operator in infinite dimensional quantum system. Chaitin's $ Omega $ is defined as the probability that the universal self-delimiting Turing machine $U$ halts, and plays a central role in the development of algorithmic information theory. In the theory, there are two equivalent ways to define the program-size complexity $ H(s)$ of a given finite binary string s. In the standard way, $ H(s)$ is defined as the length of the shortest input string for U to output s. In the other way, the so-called universal probability $m$ is introduced first, and then $ H(s)$ is defined as $ - log _2 m(s)$ without reference to the concept of program-size.par Mathematically, the statistics of outcomes in a quantum measurement are described by a positive operator-valued measure (POVM) in the most general setting. Based on the theory of computability structures on a Banach space developed by Pour-El and Richards, we extend the universal probability to an analogue of POVM in infinite dimensional quantum system, called universal semi-POVM. We also give another characterization of Chaitin's $ Omega $ numbers by universal probabilities. Then, based on this characterization, we propose to define an extension of $ Omega $ as a sum of the POVM elements of a universal semi-POVM. The validity of this definition is discussed.par In what follows, we introduce an operator version $ hat H(s)$ of $ H(s) $ in a Hilbert space of infinite dimension using universal semi-POVM, and study the properties of $ hat H(s)$.

keywords:
algorithmic information theory; Chaitin's $Omega $; computability in analysis; POVM; quantum measurement; universal probability

rawabstract:
This paper proposes an extension of Chaitin's halting probability $ \Omega $ to measurement operator in infinite dimensional quantum system. Chaitin's $ \Omega $ is defined as the probability that the universal self-delimiting Turing machine $U$ halts, and plays a central role in the development of algorithmic information theory. In the theory, there are two equivalent ways to define the program-size complexity $ H(s)$ of a given finite binary string s. In the standard way, $ H(s)$ is defined as the length of the shortest input string for U to output s. In the other way, the so-called universal probability $m$ is introduced first, and then $ H(s)$ is defined as $ - \log_2 m(s)$ without reference to the concept of program-size.\par Mathematically, the statistics of outcomes in a quantum measurement are described by a positive operator-valued measure (POVM) in the most general setting. Based on the theory of computability structures on a Banach space developed by Pour-El and Richards, we extend the universal probability to an analogue of POVM in infinite dimensional quantum system, called universal semi-POVM. We also give another characterization of Chaitin's $ \Omega $ numbers by universal probabilities. Then, based on this characterization, we propose to define an extension of $ \Omega $ as a sum of the POVM elements of a universal semi-POVM. The validity of this definition is discussed.\par In what follows, we introduce an operator version $ \hat {H}(s)$ of $ H(s) $ in a Hilbert space of infinite dimension using universal semi-POVM, and study the properties of $ \hat {H}(s)$.

rawtitle:
An extension of Chaitin's halting probability {$ \Omega $} to measurement operator in infinite dimensional quantum system

entry:
@InProceedings{Tadaki:2004:ECH,
  author =       "Kohtaro Tadaki",
  title =        "An extension of Chaitin's halting probability {$
                 \Omega $} to measurement operator in infinite
                 dimensional quantum system",
  crossref =     "Frougny:2004:RCR",
  pages =        "172--191",
  year =         "2004",
  bibdate =      "Fri Nov 17 07:00:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_14_tadaki.pdf",
  abstract =     "This paper proposes an extension of Chaitin's halting
                 probability $ \Omega $ to measurement operator in
                 infinite dimensional quantum system. Chaitin's $ \Omega
                 $ is defined as the probability that the universal
                 self-delimiting Turing machine $U$ halts, and plays a
                 central role in the development of algorithmic
                 information theory. In the theory, there are two
                 equivalent ways to define the program-size complexity $
                 H(s)$ of a given finite binary string s. In the
                 standard way, $ H(s)$ is defined as the length of the
                 shortest input string for U to output s. In the other
                 way, the so-called universal probability $m$ is
                 introduced first, and then $ H(s)$ is defined as $ -
                 \log_2 m(s)$ without reference to the concept of
                 program-size.\par

                 Mathematically, the statistics of outcomes in a quantum
                 measurement are described by a positive operator-valued
                 measure (POVM) in the most general setting. Based on
                 the theory of computability structures on a Banach
                 space developed by Pour-El and Richards, we extend the
                 universal probability to an analogue of POVM in
                 infinite dimensional quantum system, called universal
                 semi-POVM. We also give another characterization of
                 Chaitin's $ \Omega $ numbers by universal
                 probabilities. Then, based on this characterization, we
                 propose to define an extension of $ \Omega $ as a sum
                 of the POVM elements of a universal semi-POVM. The
                 validity of this definition is discussed.\par

                 In what follows, we introduce an operator version $
                 \hat {H}(s)$ of $ H(s) $ in a Hilbert space of infinite
                 dimension using universal semi-POVM, and study the
                 properties of $ \hat {H}(s)$.",
  acknowledgement = ack-nhfb,
  keywords =     "algorithmic information theory; Chaitin's $\Omega$;
                 computability in analysis; POVM; quantum measurement;
                 universal probability",
}


bibtype: techreport
filename: fparith.bib
label: Thomas:2004:LLF
author: James W. Thomas and Jon P. Okada and Peter Markstein and Ren-Cang Li
type: Technical report
institution: Hewlett--Packard Company
address: Palo Alto, CA, USA
pages: 26
day: 3
month: dec
monthnumber: 12
year: 2004
bibdate: Fri Jun 24 20:12:09 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 20:12:09 ???
URL: http://h21007.www2.hp.com/dspp/ddl/ddl_Download_File_TRX/1,1249,942,00.pdf
acknowledgement: ack-nhfb
rawauthor: James W. Thomas and Jon P. Okada and Peter Markstein and Ren-Cang Li
title:
The tt Libm Library and Floating-Point Arithmetic in HP-UX for Itanium-Based Systems: Updated for HP-UX 11i v2

abstract:
The HP-UX libm library provides mathematical functions for C, C++, and Fortran 90. The HP-UX libm library and compilers for Itanium-based systems provide a leading combination of functionality, quality, and performance.With inlining and software pipelining, commonly used math functions can achieve throughput comparable to hand-tuned vector routines without requiring user code to be written for a vector interface, and with no loss of accuracy or edge-case behavior: For example, the single precision exponential can exceed 400 million evaluations per second on a 1.5 GHz Itanium 2 system. The math API encompasses C99, X/Open, and other popular functionality and offers four fully supported IEEE floating types. The libm library and compilers provide features that facilitate programming techniques that have not been practical heretofore. The libm implementation for Itanium-based systems, introduced in 2001 in HP-UX B.11.20 (11i v1.5), has been upgraded in B.11.22 (11i v1.6), B.11.23 (11i v2), and most recently in B.11.23 AR1204 and the associated Math Library Cumulative Patch PHSS_31853 with improved performance and overall quality and with a few new functions. The AR1204 compilers are available as patches for B.11.22; the associated Math patch for B.11.22 is PHSS_32066. This paper (1) describes the latest libm library (including sequences the compilers inline) in terms of functionality, speed, accuracy, standards, and special-case behavior; (2) discusses programming techniques that exploit the floating-point capabilities of HP-UX on Itanium- based systems; and (3) describes motivations, goals, and development strategies for the libm library and the compiler floating-point facilities.

rawabstract:
The HP-UX libm library provides mathematical functions for C, C++, and Fortran 90. The HP-UX libm library and compilers for Itanium-based systems provide a leading combination of functionality, quality, and performance.With inlining and software pipelining, commonly used math functions can achieve throughput comparable to hand-tuned vector routines without requiring user code to be written for a vector interface, and with no loss of accuracy or edge-case behavior: For example, the single precision exponential can exceed 400 million evaluations per second on a 1.5 GHz Itanium 2 system. The math API encompasses C99, X/Open, and other popular functionality and offers four fully supported IEEE floating types. The libm library and compilers provide features that facilitate programming techniques that have not been practical heretofore. The libm implementation for Itanium-based systems, introduced in 2001 in HP-UX B.11.20 (11i v1.5), has been upgraded in B.11.22 (11i v1.6), B.11.23 (11i v2), and most recently in B.11.23 AR1204 and the associated Math Library Cumulative Patch PHSS_31853 with improved performance and overall quality and with a few new functions. The AR1204 compilers are available as patches for B.11.22; the associated Math patch for B.11.22 is PHSS_32066. This paper (1) describes the latest libm library (including sequences the compilers inline) in terms of functionality, speed, accuracy, standards, and special-case behavior; (2) discusses programming techniques that exploit the floating-point capabilities of HP-UX on Itanium- based systems; and (3) describes motivations, goals, and development strategies for the libm library and the compiler floating-point facilities.

rawtitle:
The {{\tt Libm}} Library and Floating-Point Arithmetic in {HP-UX} for {Itanium}-Based Systems: Updated for {HP-UX 11i v2}

entry:
@TechReport{Thomas:2004:LLF,
  author =       "James W. Thomas and Jon P. Okada and Peter Markstein
                 and Ren-Cang Li",
  title =        "The {{\tt Libm}} Library and Floating-Point Arithmetic
                 in {HP-UX} for {Itanium}-Based Systems: Updated for
                 {HP-UX 11i v2}",
  type =         "Technical report",
  institution =  "Hewlett--Packard Company",
  address =      "Palo Alto, CA, USA",
  pages =        "26",
  day =          "3",
  month =        dec,
  year =         "2004",
  bibdate =      "Fri Jun 24 20:12:09 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://h21007.www2.hp.com/dspp/ddl/ddl_Download_File_TRX/1,1249,942,00.pdf",
  abstract =     "The HP-UX libm library provides mathematical functions
                 for C, C++, and Fortran 90. The HP-UX libm library and
                 compilers for Itanium-based systems provide a leading
                 combination of functionality, quality, and
                 performance.With inlining and software pipelining,
                 commonly used math functions can achieve throughput
                 comparable to hand-tuned vector routines without
                 requiring user code to be written for a vector
                 interface, and with no loss of accuracy or edge-case
                 behavior: For example, the single precision exponential
                 can exceed 400 million evaluations per second on a 1.5
                 GHz Itanium 2 system. The math API encompasses C99,
                 X/Open, and other popular functionality and offers four
                 fully supported IEEE floating types. The libm library
                 and compilers provide features that facilitate
                 programming techniques that have not been practical
                 heretofore. The libm implementation for Itanium-based
                 systems, introduced in 2001 in HP-UX B.11.20 (11i
                 v1.5), has been upgraded in B.11.22 (11i v1.6), B.11.23
                 (11i v2), and most recently in B.11.23 AR1204 and the
                 associated Math Library Cumulative Patch PHSS_31853
                 with improved performance and overall quality and with
                 a few new functions. The AR1204 compilers are available
                 as patches for B.11.22; the associated Math patch for
                 B.11.22 is PHSS_32066. This paper (1) describes the
                 latest libm library (including sequences the compilers
                 inline) in terms of functionality, speed, accuracy,
                 standards, and special-case behavior; (2) discusses
                 programming techniques that exploit the floating-point
                 capabilities of HP-UX on Itanium- based systems; and
                 (3) describes motivations, goals, and development
                 strategies for the libm library and the compiler
                 floating-point facilities.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Thompson:2004:BDF
author: J. Thompson and N. Karra and M. J. Schulte
booktitle: Proceedings. IEEE Computer Society Annual Symposium on VLSI, 19--20 February 2004
title: A 64-bit decimal floating-point adder
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 297--298
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2004-08.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: J. Thompson and N. Karra and M. J. Schulte
rawbooktitle: Proceedings. {IEEE Computer Society Annual Symposium on VLSI, 19--20 February 2004}
rawtitle: A 64-bit decimal floating-point adder
abstract:
Due to rapid growth in financial, commercial, and Internet-based applications, there is an increasing desire to allow computers to operate on both binary and decimal floating-point numbers. Consequently, specifications for decimal floating-point support are being added to the IEEE-754 Standard for Floating-Point Arithmetic. In this paper, we present the design and implementation of a decimal floating-point adder that is compliant with the current draft revision of this standard. The adder supports operations on 64-bit (16-digit) decimal floating-point operands. We provide synthesis results indicating the estimated area and delay for our design when it is pipelined to various depths.

rawabstract:
Due to rapid growth in financial, commercial, and Internet-based applications, there is an increasing desire to allow computers to operate on both binary and decimal floating-point numbers. Consequently, specifications for decimal floating-point support are being added to the IEEE-754 Standard for Floating-Point Arithmetic. In this paper, we present the design and implementation of a decimal floating-point adder that is compliant with the current draft revision of this standard. The adder supports operations on 64-bit (16-digit) decimal floating-point operands. We provide synthesis results indicating the estimated area and delay for our design when it is pipelined to various depths.

entry:
@InProceedings{Thompson:2004:BDF,
  author =       "J. Thompson and N. Karra and M. J. Schulte",
  booktitle =    "Proceedings. {IEEE Computer Society Annual Symposium
                 on VLSI, 19--20 February 2004}",
  title =        "A 64-bit decimal floating-point adder",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "297--298",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2004-08.pdf",
  abstract =     "Due to rapid growth in financial, commercial, and
                 Internet-based applications, there is an increasing
                 desire to allow computers to operate on both binary and
                 decimal floating-point numbers. Consequently,
                 specifications for decimal floating-point support are
                 being added to the IEEE-754 Standard for Floating-Point
                 Arithmetic. In this paper, we present the design and
                 implementation of a decimal floating-point adder that
                 is compliant with the current draft revision of this
                 standard. The adder supports operations on 64-bit
                 (16-digit) decimal floating-point operands. We provide
                 synthesis results indicating the estimated area and
                 delay for our design when it is pipelined to various
                 depths.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: manual
filename: fparith.bib
label: TI:2004:TUG
title: TMS320C3x User's Guide
organization: Texas Instruments
address: Post Office box 655303, Dallas, TX 75265, USA
pages: 770
year: 2004
bibdate: Wed Nov 24 09:20:17 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.24 09:20:17 ???
note: Literature Number: SPRU031F 2558539-9761 revision L March 2004
URL: http://www-s.ti.com/sc/psheets/spru031f/spru031f.pdf
keywords: digital signal processor (DSP)
acknowledgement: ack-nhfb
rawnote: Literature Number: SPRU031F 2558539-9761 revision L March 2004
rawtitle: {TMS320C3x} User's Guide
entry:
@Manual{TI:2004:TUG,
  title =        "{TMS320C3x} User's Guide",
  organization = "Texas Instruments",
  address =      "Post Office box 655303, Dallas, TX 75265, USA",
  pages =        "770",
  year =         "2004",
  bibdate =      "Wed Nov 24 09:20:17 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Literature Number: SPRU031F 2558539-9761 revision L
                 March 2004",
  URL =          "http://www-s.ti.com/sc/psheets/spru031f/spru031f.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "digital signal processor (DSP)",
}


bibtype: inproceedings
filename: fparith.bib
label: Tsoi:2004:ALA
author: K. H. Tsoi and C. H. Ho and H. C. Yeung and P. H. W. Leong
title: An Arithmetic Library and its Application to the $N$-body Problem
crossref: Arnold:2004:PAI
pages: 68--78
year: 2004
DOI: https://doi.org/10.1109/FCCM.2004.14
bibdate: Sat Jun 25 12:45:15 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.25 12:45:15 ???
URL: http://www.cse.cuhk.edu.hk/~phwl/mt/public/archives/papers/cast_fccm04.pdf
acknowledgement: ack-nhfb
rawauthor: K. H. Tsoi and C. H. Ho and H. C. Yeung and P. H. W. Leong
rawtitle: An Arithmetic Library and its Application to the {$N$}-body Problem
abstract:
Computer arithmetic is a specialist field of study, and it is very difficult for designers to choose the most efficient method for implementing a given algorithm due to the large number of design choices available. In this paper, an object oriented arithmetic library is presented which can be used to simulate and generate designs which use fixed, floating, logarithmic and hybrid number representations. The advantages of this approach are that a user can explore tradeoffs concerning precision, accuracy and speed from single high level description. Furthermore, users need not be intimately familiar with the implementation details of the underlying libraries, thus allowing users to develop systems employing advanced computer arithmetic without detailed knowledge of its implementation. The application of this library to a coprocessor which implements the force pipeline for an N-body solver is described.

rawabstract:
Computer arithmetic is a specialist field of study, and it is very difficult for designers to choose the most efficient method for implementing a given algorithm due to the large number of design choices available. In this paper, an object oriented arithmetic library is presented which can be used to simulate and generate designs which use fixed, floating, logarithmic and hybrid number representations. The advantages of this approach are that a user can explore tradeoffs concerning precision, accuracy and speed from single high level description. Furthermore, users need not be intimately familiar with the implementation details of the underlying libraries, thus allowing users to develop systems employing advanced computer arithmetic without detailed knowledge of its implementation. The application of this library to a coprocessor which implements the force pipeline for an N-body solver is described.

entry:
@InProceedings{Tsoi:2004:ALA,
  author =       "K. H. Tsoi and C. H. Ho and H. C. Yeung and P. H. W.
                 Leong",
  title =        "An Arithmetic Library and its Application to the
                 {$N$}-body Problem",
  crossref =     "Arnold:2004:PAI",
  pages =        "68--78",
  year =         "2004",
  DOI =          "https://doi.org/10.1109/FCCM.2004.14",
  bibdate =      "Sat Jun 25 12:45:15 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cse.cuhk.edu.hk/~phwl/mt/public/archives/papers/cast_fccm04.pdf",
  abstract =     "Computer arithmetic is a specialist field of study,
                 and it is very difficult for designers to choose the
                 most efficient method for implementing a given
                 algorithm due to the large number of design choices
                 available. In this paper, an object oriented arithmetic
                 library is presented which can be used to simulate and
                 generate designs which use fixed, floating, logarithmic
                 and hybrid number representations. The advantages of
                 this approach are that a user can explore tradeoffs
                 concerning precision, accuracy and speed from single
                 high level description. Furthermore, users need not be
                 intimately familiar with the implementation details of
                 the underlying libraries, thus allowing users to
                 develop systems employing advanced computer arithmetic
                 without detailed knowledge of its implementation. The
                 application of this library to a coprocessor which
                 implements the force pipeline for an N-body solver is
                 described.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Underwood:2004:CGC
author: K. D. Underwood and K. S. Hemmert
title: Closing the gap: CPU and FPGA trends in sustainable floating-point BLAS performance
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 219--228
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: K. D. Underwood and K. S. Hemmert
rawtitle: Closing the gap: {CPU} and {FPGA} trends in sustainable floating-point {BLAS} performance
abstract:
Field programmable gate arrays (FPGAs) have long been an attractive alternative to microprocessors for computing tasks--as long as floating-point arithmetic is not required. Fueled by the advance of Moore's law, FPGAs are rapidly reaching sufficient densities to enhance peak floating-point performance as well. The question, however, is how much of this peak performance can be sustained. This paper examines three of the basic linear algebra subroutine (BLAS) functions: vector dot product, matrix-vector multiply, and matrix multiply. A comparison of microprocessors, FPGAs, and reconfigurable computing platforms is performed for each operation. The analysis highlights the amount of memory bandwidth and internal storage needed to sustain peak performance with FPGAs. This analysis considers the historical context of the last six years and is extrapolated for the next six years.

rawabstract:
Field programmable gate arrays (FPGAs) have long been an attractive alternative to microprocessors for computing tasks--as long as floating-point arithmetic is not required. Fueled by the advance of Moore's law, FPGAs are rapidly reaching sufficient densities to enhance peak floating-point performance as well. The question, however, is how much of this peak performance can be sustained. This paper examines three of the basic linear algebra subroutine (BLAS) functions: vector dot product, matrix-vector multiply, and matrix multiply. A comparison of microprocessors, FPGAs, and reconfigurable computing platforms is performed for each operation. The analysis highlights the amount of memory bandwidth and internal storage needed to sustain peak performance with FPGAs. This analysis considers the historical context of the last six years and is extrapolated for the next six years.

entry:
@InProceedings{Underwood:2004:CGC,
  author =       "K. D. Underwood and K. S. Hemmert",
  booktitle =    "{FCCM 2004}. 12th Annual {IEEE} Symposium on
                 Field-Programmable Custom Computing Machines, 20--23
                 April 2004",
  title =        "Closing the gap: {CPU} and {FPGA} trends in
                 sustainable floating-point {BLAS} performance",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "219--228",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Field programmable gate arrays (FPGAs) have long been
                 an attractive alternative to microprocessors for
                 computing tasks--as long as floating-point arithmetic
                 is not required. Fueled by the advance of Moore's law,
                 FPGAs are rapidly reaching sufficient densities to
                 enhance peak floating-point performance as well. The
                 question, however, is how much of this peak performance
                 can be sustained. This paper examines three of the
                 basic linear algebra subroutine (BLAS) functions:
                 vector dot product, matrix-vector multiply, and matrix
                 multiply. A comparison of microprocessors, FPGAs, and
                 reconfigurable computing platforms is performed for
                 each operation. The analysis highlights the amount of
                 memory bandwidth and internal storage needed to sustain
                 peak performance with FPGAs. This analysis considers
                 the historical context of the last six years and is
                 extrapolated for the next six years.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Underwood:2004:FVC
author: Keith D. Underwood
title: FPGAs vs. CPUs: Trends in peak floating-point performance
crossref: ACM:2004:FAS
publisher: pub-ACM
address: pub-ACM:adr
pages: 171--180
year: 2004
DOI: https://doi.org/10.1145/968280.968305
bibdate: Sat Oct 9 13:06:11 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 13:06:11 ???
acknowledgement: ack-nhfb
rawauthor: Keith D. Underwood
rawtitle: {FPGAs} vs. {CPUs}: Trends in peak floating-point performance
abstract:
Moore's Law states that the number of transistors on a device doubles every two years; however, it is often (mis)quoted based on its impact on CPU performance. This important corollary of Moore's Law states that improved clock frequency plus improved architecture yields a doubling of CPU performance every 18 months. This paper examines the impact of Moore's Law on the peak floating-point performance of FPGAs. Performance trends for individual operations are analyzed as well as the performance trend of a common instruction mix (multiply accumulate). The important result is that peak FPGA floating-point performance is growing significantly faster than peak floating-point performance for a CPU.

rawabstract:
Moore's Law states that the number of transistors on a device doubles every two years; however, it is often (mis)quoted based on its impact on CPU performance. This important corollary of Moore's Law states that improved clock frequency plus improved architecture yields a doubling of CPU performance every 18 months. This paper examines the impact of Moore's Law on the peak floating-point performance of FPGAs. Performance trends for individual operations are analyzed as well as the performance trend of a common instruction mix (multiply accumulate). The important result is that peak FPGA floating-point performance is growing significantly faster than peak floating-point performance for a CPU.

entry:
@InProceedings{Underwood:2004:FVC,
  author =       "Keith D. Underwood",
  title =        "{FPGAs} vs. {CPUs}: Trends in peak floating-point
                 performance",
  crossref =     "ACM:2004:FAS",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "171--180",
  year =         "2004",
  DOI =          "https://doi.org/10.1145/968280.968305",
  bibdate =      "Sat Oct 9 13:06:11 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Moore's Law states that the number of transistors on a
                 device doubles every two years; however, it is often
                 (mis)quoted based on its impact on CPU performance.
                 This important corollary of Moore's Law states that
                 improved clock frequency plus improved architecture
                 yields a doubling of CPU performance every 18 months.
                 This paper examines the impact of Moore's Law on the
                 peak floating-point performance of FPGAs. Performance
                 trends for individual operations are analyzed as well
                 as the performance trend of a common instruction mix
                 (multiply accumulate). The important result is that
                 peak FPGA floating-point performance is growing
                 significantly faster than peak floating-point
                 performance for a CPU.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Vignes:2004:DSA
author: Jean Vignes
title: Discrete Stochastic Arithmetic for Validating Results of Numerical Software
journal: j-NUMER-ALGORITHMS
volume: 37
number: 1--4
pages: 377--390
month: dec
monthnumber: 12
year: 2004
CODEN: NUALEG
ISSN: 1017-1398 (print), 1572-9265 (electronic) OR 10171398 (print), 15729265 (electronic)
ISSNL: 1017-1398 OR 10171398
bibdate: Mon Dec 6 07:00:28 MST 2004
bibsource: http://www.kluweronline.com/issn/1017-1398; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.12.06 07:00:28 MST
URL: http://ipsapp009.kluweronline.com/IPS/content/ext/x/J/5058/I/58/A/31/abstract.htm
fjournal: Numerical Algorithms
remark: Special Issue: SCAN'2002 International Conference (Guest Editors: Ren e Alt and Jean-Luc Lamotte).
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11075
rawauthor: Jean Vignes
rawtitle: Discrete Stochastic Arithmetic for Validating Results of Numerical Software
entry:
@Article{Vignes:2004:DSA,
  author =       "Jean Vignes",
  title =        "Discrete Stochastic Arithmetic for Validating Results
                 of Numerical Software",
  journal =      j-NUMER-ALGORITHMS,
  volume =       "37",
  number =       "1--4",
  pages =        "377--390",
  month =        dec,
  year =         "2004",
  CODEN =        "NUALEG",
  ISSN =         "1017-1398 (print), 1572-9265 (electronic)",
  ISSN-L =       "1017-1398",
  bibdate =      "Mon Dec 6 07:00:28 MST 2004",
  bibsource =    "http://www.kluweronline.com/issn/1017-1398;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ipsapp009.kluweronline.com/IPS/content/ext/x/J/5058/I/58/A/31/abstract.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerical Algorithms",
  journal-URL =  "http://link.springer.com/journal/11075",
  remark =       "Special Issue: SCAN'2002 International Conference
                 (Guest Editors: Ren {\'e} Alt and Jean-Luc Lamotte).",
}


bibtype: article
filename: fparith.bib
label: vonzurGathen:2004:FAG
author: J. Joachim von zur Gathen and Michael Nocker
title: Fast arithmetic with general Gauss periods
journal: j-THEOR-COMP-SCI
volume: 315
number: 2--3
pages: 419--452
day: 6
month: may
monthnumber: 5
year: 2004
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Thu Nov 4 10:19:15 MST 2004
bibtimestamp: 2004.11.04 10:19:15 MST
fjournal: Theoretical Computer Science
keywords: Efficient arithmetic; Exponentiation; Finite fields; Gauss period; Normal basis
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: J. Joachim von zur Gathen and Michael N{\"o}cker
rawtitle: Fast arithmetic with general {Gau{\ss}} periods
bibsource:
http://www.sciencedirect.com/science/journal/03043975; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
We show how to apply fast arithmetic in conjunction with general Gauss periods in finite fields. This is an essential ingredient for some efficient exponentiation algorithms.

rawabstract:
We show how to apply fast arithmetic in conjunction with general Gau{\ss} periods in finite fields. This is an essential ingredient for some efficient exponentiation algorithms.

entry:
@Article{vonzurGathen:2004:FAG,
  author =       "J. Joachim von zur Gathen and Michael N{\"o}cker",
  title =        "Fast arithmetic with general {Gau{\ss}} periods",
  journal =      j-THEOR-COMP-SCI,
  volume =       "315",
  number =       "2--3",
  pages =        "419--452",
  day =          "6",
  month =        may,
  year =         "2004",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Thu Nov 4 10:19:15 MST 2004",
  bibsource =    "http://www.sciencedirect.com/science/journal/03043975;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We show how to apply fast arithmetic in conjunction
                 with general Gau{\ss} periods in finite fields. This is
                 an essential ingredient for some efficient
                 exponentiation algorithms.",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
  keywords =     "Efficient arithmetic; Exponentiation; Finite fields;
                 Gau{\ss} period; Normal basis",
}


bibtype: inproceedings
filename: fparith.bib
label: Voronenko:2004:AGI
author: Y. Voronenko and M. Puschel
title: Automatic generation of implementations for DSP transforms on fused multiply-add architectures
crossref: IEEE:2004:IICc
volume: 5
pages: V-101--V-104
year: 2004
DOI: https://doi.org/10.1109/ICASSP.2004.1327057
bibdate: Sun Feb 20 10:05:45 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.20 10:05:45 ???
acknowledgement: ack-nhfb
rawauthor: Y. Voronenko and M. Puschel
rawtitle: Automatic generation of implementations for {DSP} transforms on fused multiply-add architectures
abstract:
Many modern computer architectures feature fused multiply-add (FMA) instructions, which offer potentially faster performance for numerical applications. For DSP transforms, compilers can only generate FMA code to a very limited extent because optimal use of FMAs requires modifying the chosen algorithm. In this paper, we present a framework for automatically generating FMA code for every linear DSP transform, which we implemented as an extension to the SPIRAL code generation system. We show that for many transforms and transform sizes, our generated FMA code matches the best-known hand-derived FMA algorithms in terms of arithmetic cost. Further, we present actual runtime results that show the speed-up obtained by using FMA instructions.

rawabstract:
Many modern computer architectures feature fused multiply-add (FMA) instructions, which offer potentially faster performance for numerical applications. For DSP transforms, compilers can only generate FMA code to a very limited extent because optimal use of FMAs requires modifying the chosen algorithm. In this paper, we present a framework for automatically generating FMA code for every linear DSP transform, which we implemented as an extension to the SPIRAL code generation system. We show that for many transforms and transform sizes, our generated FMA code matches the best-known hand-derived FMA algorithms in terms of arithmetic cost. Further, we present actual runtime results that show the speed-up obtained by using FMA instructions.

entry:
@InProceedings{Voronenko:2004:AGI,
  author =       "Y. Voronenko and M. Puschel",
  title =        "Automatic generation of implementations for {DSP}
                 transforms on fused multiply-add architectures",
  crossref =     "IEEE:2004:IICc",
  volume =       "5",
  pages =        "V-101--V-104",
  year =         "2004",
  DOI =          "https://doi.org/10.1109/ICASSP.2004.1327057",
  bibdate =      "Sun Feb 20 10:05:45 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Many modern computer architectures feature fused
                 multiply-add (FMA) instructions, which offer
                 potentially faster performance for numerical
                 applications. For DSP transforms, compilers can only
                 generate FMA code to a very limited extent because
                 optimal use of FMAs requires modifying the chosen
                 algorithm. In this paper, we present a framework for
                 automatically generating FMA code for every linear DSP
                 transform, which we implemented as an extension to the
                 SPIRAL code generation system. We show that for many
                 transforms and transform sizes, our generated FMA code
                 matches the best-known hand-derived FMA algorithms in
                 terms of arithmetic cost. Further, we present actual
                 runtime results that show the speed-up obtained by
                 using FMA instructions.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Walters:2004:TSC
author: E. G. Walters and M. J. Schulte and M. G. Arnold
title: Truncated Squarers with Constant and Variable Correction
crossref: Luk:2004:ASP
pages: V-101--V-104
year: 2004
bibdate: Sun Mar 04 20:49:55 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 20:49:55 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2004-14.pdf
acknowledgement: ack-nhfb
rawauthor: E. G. Walters and M. J. Schulte and M. G. Arnold
rawtitle: Truncated Squarers with Constant and Variable Correction
entry:
@InProceedings{Walters:2004:TSC,
  author =       "E. G. Walters and M. J. Schulte and M. G. Arnold",
  title =        "Truncated Squarers with Constant and Variable
                 Correction",
  crossref =     "Luk:2004:ASP",
  year =         "2004",
  bibdate =      "Sun Mar 04 20:49:55 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2004-14.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Wang:2004:DFP
author: Liang-Kai Wang and M. J. Schulte
title: Decimal floating-point division using Newton--Raphson iteration
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 84--95
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2004-06.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Liang-Kai Wang and M. J. Schulte
rawtitle: Decimal floating-point division using {Newton--Raphson} iteration
booktitle:
Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 27--29 Sept. 2004

abstract:
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid growth in financial, commercial, and Internet-based applications, hardware support for decimal floating-point arithmetic is now being considered by various computer manufacturers and specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic (IEEE-754R). This work presents an efficient arithmetic algorithm and hardware design for decimal floating-point division. ldots 

rawabstract:
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid growth in financial, commercial, and Internet-based applications, hardware support for decimal floating-point arithmetic is now being considered by various computer manufacturers and specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic (IEEE-754R). This work presents an efficient arithmetic algorithm and hardware design for decimal floating-point division. \ldots{}

rawbooktitle:
Proceedings. 15th {IEEE} International Conference on Application-Specific Systems, Architectures and Processors, 27--29 Sept. 2004

entry:
@InProceedings{Wang:2004:DFP,
  author =       "Liang-Kai Wang and M. J. Schulte",
  booktitle =    "Proceedings. 15th {IEEE} International Conference on
                 Application-Specific Systems, Architectures and
                 Processors, 27--29 Sept. 2004",
  title =        "Decimal floating-point division using
                 {Newton--Raphson} iteration",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "84--95",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2004-06.pdf",
  abstract =     "Decreasing feature sizes allow additional
                 functionality to be added to future microprocessors to
                 improve the performance of important application
                 domains. As a result of rapid growth in financial,
                 commercial, and Internet-based applications, hardware
                 support for decimal floating-point arithmetic is now
                 being considered by various computer manufacturers and
                 specifications for decimal floating-point arithmetic
                 have been added to the draft revision of the IEEE-754
                 Standard for Floating-Point Arithmetic (IEEE-754R).
                 This work presents an efficient arithmetic algorithm
                 and hardware design for decimal floating-point
                 division. \ldots{}",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Weaver:2004:MFD
author: B. J. Weaver and Y. V. Zakharov and T. C. Tozer
title: Multiplication-free division of complex numbers
crossref: Anonymous:2004:ICM
pages: 211--214
year: 2004
bibdate: Sat Dec 04 09:59:02 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.12.04 09:59:02 ???
acknowledgement: ack-nhfb
rawauthor: B. J. Weaver and Y. V. Zakharov and T. C. Tozer
rawtitle: Multiplication-free division of complex numbers
entry:
@InProceedings{Weaver:2004:MFD,
  author =       "B. J. Weaver and Y. V. Zakharov and T. C. Tozer",
  title =        "Multiplication-free division of complex numbers",
  crossref =     "Anonymous:2004:ICM",
  pages =        "211--214",
  year =         "2004",
  bibdate =      "Sat Dec 04 09:59:02 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Wu:2004:HSL
author: Chien-Hsing Wu and Chien-Ming Wu and Ming-Der Shieh and Yin-Tsung Hwang
journal: j-IEEE-TRANS-COMPUT
volume: 53
number: 3
pages: 375--380
month: mar
monthnumber: 3
year: 2004
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2004.1261843
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 08:12:33 MDT 2011
bibtimestamp: 2011.07.05 08:12:33 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261843
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Chien-Hsing Wu and Chien-Ming Wu and Ming-Der Shieh and Yin-Tsung Hwang
title:
High-speed, low-complexity systolic designs of novel iterative division algorithms in $ mathrm GF(2^m) $

rawtitle:
High-speed, low-complexity systolic designs of novel iterative division algorithms in {$ \mathrm {GF}(2^m) $}

entry:
@Article{Wu:2004:HSL,
  author =       "Chien-Hsing Wu and Chien-Ming Wu and Ming-Der Shieh
                 and Yin-Tsung Hwang",
  title =        "High-speed, low-complexity systolic designs of novel
                 iterative division algorithms in {$ \mathrm {GF}(2^m)
                 $}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "53",
  number =       "3",
  pages =        "375--380",
  month =        mar,
  year =         "2004",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2004.1261843",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 08:12:33 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261843",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Wu:2004:ORF
author: Jun Wu and Sheng Chen and James F. Whidborne and Jian Chu
journal: j-INT-J-CONTROL
volume: 77
number: 5
pages: 427--440
year: 2004
CODEN: IJCOAZ
ISSN: 0020-7179 (print), 1366-5820 (electronic) OR 00207179 (print), 13665820 (electronic)
ISSNL: 0020-7179 OR 00207179
MRclass: 93B15 (93C57)
MRnumber: MR2052876
bibdate: Thu Nov 8 19:16:14 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 19:16:14 ???
fjournal: International Journal of Control
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/tcon20
rawauthor: Jun Wu and Sheng Chen and James F. Whidborne and Jian Chu
title:
Optimal realizations of floating-point implemented digital controllers with finite word length considerations

rawtitle:
Optimal realizations of floating-point implemented digital controllers with finite word length considerations

entry:
@Article{Wu:2004:ORF,
  author =       "Jun Wu and Sheng Chen and James F. Whidborne and Jian
                 Chu",
  title =        "Optimal realizations of floating-point implemented
                 digital controllers with finite word length
                 considerations",
  journal =      j-INT-J-CONTROL,
  volume =       "77",
  number =       "5",
  pages =        "427--440",
  year =         "2004",
  CODEN =        "IJCOAZ",
  ISSN =         "0020-7179 (print), 1366-5820 (electronic)",
  ISSN-L =       "0020-7179",
  MRclass =      "93B15 (93C57)",
  MRnumber =     "MR2052876",
  bibdate =      "Thu Nov 8 19:16:14 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of Control",
  journal-URL =  "http://www.tandfonline.com/loi/tcon20",
}


bibtype: inproceedings
filename: fparith.bib
label: Yang:2004:EEP
author: Xiao Yang and S. K. Valia and M. J. Schulte and R. B. Lee
title: Exploration and evaluation of PLX floating-point instructions and implementations for $3$D graphics
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1873--1878
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2004-18.pdf
acknowledgement: ack-nhfb
rawauthor: Xiao Yang and S. K. Valia and M. J. Schulte and R. B. Lee
rawtitle:
Exploration and evaluation of {PLX} floating-point instructions and implementations for {$3$D} graphics

entry:
@InProceedings{Yang:2004:EEP,
  author =       "Xiao Yang and S. K. Valia and M. J. Schulte and R. B.
                 Lee",
  booktitle =    "Conference Record of the Thirty-Eighth Asilomar
                 Conference on Signals, Systems and Computers, Nov.
                 7--10, 2004",
  title =        "Exploration and evaluation of {PLX} floating-point
                 instructions and implementations for {$3$D} graphics",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1873--1878",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2004-18.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Yang:2004:PFE
author: Xiao Yang and R. B. Lee
booktitle: ICME '04. 2004 IEEE International Conference on Multimedia and Expo, 27--30 June 2004
title: PLX FP: an efficient floating-point instruction set for $3$D graphics
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 137--140
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: Xiao Yang and R. B. Lee
rawbooktitle: {ICME '04}. 2004 {IEEE} International Conference on Multimedia and Expo, 27--30 June 2004
rawtitle: {PLX FP}: an efficient floating-point instruction set for {$3$D} graphics
abstract:
3D graphics is an important component in the workload of today's computing platforms. Many ISA extensions for 3D graphics have been proposed and implemented. We describe PLX FP, a new floating-point extension to the PLX architecture, designed to support very efficiently the essential operations needed for the 3D graphics pipeline. Very high performance floating-point 3D graphics processing is achieved, using a low-cost PLX processor.

rawabstract:
3D graphics is an important component in the workload of today's computing platforms. Many ISA extensions for 3D graphics have been proposed and implemented. We describe PLX FP, a new floating-point extension to the PLX architecture, designed to support very efficiently the essential operations needed for the 3D graphics pipeline. Very high performance floating-point 3D graphics processing is achieved, using a low-cost PLX processor.

entry:
@InProceedings{Yang:2004:PFE,
  author =       "Xiao Yang and R. B. Lee",
  booktitle =    "{ICME '04}. 2004 {IEEE} International Conference on
                 Multimedia and Expo, 27--30 June 2004",
  title =        "{PLX FP}: an efficient floating-point instruction set
                 for {$3$D} graphics",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "137--140",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "3D graphics is an important component in the workload
                 of today's computing platforms. Many ISA extensions for
                 3D graphics have been proposed and implemented. We
                 describe PLX FP, a new floating-point extension to the
                 PLX architecture, designed to support very efficiently
                 the essential operations needed for the 3D graphics
                 pipeline. Very high performance floating-point 3D
                 graphics processing is achieved, using a low-cost PLX
                 processor.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Yoon:2004:IPT
author: Han-Ul Yoon and Kyoung-Taik Park and Kwee-Bo Sim
booktitle: IECON 2004, 30th Annual Conference of IEEE Industrial Electronics Society
title: Improvement of processing time using residue number system and sorting network in controller design
volume: 3
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 2046--2051
year: 2004
DOI: https://doi.org/10.1109/IECON.2004.1432111
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: Han-Ul Yoon and Kyoung-Taik Park and Kwee-Bo Sim
rawbooktitle: {IECON 2004}, 30th Annual Conference of {IEEE} Industrial Electronics Society
rawtitle: Improvement of processing time using residue number system and sorting network in controller design
entry:
@InProceedings{Yoon:2004:IPT,
  author =       "Han-Ul Yoon and Kyoung-Taik Park and Kwee-Bo Sim",
  booktitle =    "{IECON 2004}, 30th Annual Conference of {IEEE}
                 Industrial Electronics Society",
  title =        "Improvement of processing time using residue number
                 system and sorting network in controller design",
  volume =       "3",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2046--2051",
  year =         "2004",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/IECON.2004.1432111",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "This paper presents and proposes two approaches to
                 speed up for the controller unit. One is a residue
                 number system (RNS), the other is a sorting network.
                 Using an RNS reduces the total bit size of adder and
                 carry-propagation delays. Also, using \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Zhang:2004:PBL
author: W. Zhang and G. A. Jullien and V. S. Dimitrov
booktitle: Proceedings of the 2004 International Symposium on Circuits and Systems: ISCAS '04, 23--26 May 2004
title: A programmable base $2$D-LNS MAC with self-generated look-up tables
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: II-789--92
year: 2004
bibdate: Sat Jul 16 16:14:38 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 16:14:38 MDT
acknowledgement: ack-nhfb
rawauthor: W. Zhang and G. A. Jullien and V. S. Dimitrov
rawtitle: A programmable base {$2$D}-{LNS} {MAC} with self-generated look-up tables
rawbooktitle:
Proceedings of the 2004 International Symposium on Circuits and Systems: {ISCAS '04}, 23--26 May 2004

entry:
@InProceedings{Zhang:2004:PBL,
  author =       "W. Zhang and G. A. Jullien and V. S. Dimitrov",
  booktitle =    "Proceedings of the 2004 International Symposium on
                 Circuits and Systems: {ISCAS '04}, 23--26 May 2004",
  title =        "A programmable base {$2$D}-{LNS} {MAC} with
                 self-generated look-up tables",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "II-789--92",
  year =         "2004",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 16:14:38 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "This paper presents a new architecture for a
                 programmable second base 2-dimensional logarithmic
                 number system (2D LNS) Multiply Accumulator Cell (MAC)
                 using DRAMs to store the conversion look-up tables
                 (LUTs). It uses a direct mapping from non- \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Zheng:2004:HRN
author: Xizhong Zheng
title: On the Hierarchy of $ Delta _2^0 $-Real Numbers
crossref: Frougny:2004:RCR
pages: 192--215
year: 2004
bibdate: Fri Nov 17 07:00:31 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.11.17 07:00:31 ???
URL: http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_15_zheng.pdf
keywords: $ Delta _2^0 $-reals; Computably approximable reals; hierarchy
acknowledgement: ack-nhfb
rawauthor: Xizhong Zheng
rawtitle: On the Hierarchy of {$ \Delta_2^0 $}-Real Numbers
abstract:
A real number x is called $ Delta _2^0 $ if its binary expansion corresponds to a $ Delta _2^0 $-set of natural numbers. Such reals are just the limits of computable sequences of rational numbers and hence also called computably approximable. Depending on how fast the sequences converge, $ Delta _2^0 $-reals have different levels of effectiveness. This leads to various hierarchies of $ Delta _2^0 $ reals. In this paper we summarize several recent developments related to such kind of hierarchies

rawabstract:
A real number x is called $ \Delta_2^0 $ if its binary expansion corresponds to a $ \Delta_2^0 $-set of natural numbers. Such reals are just the limits of computable sequences of rational numbers and hence also called computably approximable. Depending on how fast the sequences converge, $ \Delta_2^0 $-reals have different levels of effectiveness. This leads to various hierarchies of $ \Delta_2^0 $ reals. In this paper we summarize several recent developments related to such kind of hierarchies

entry:
@InProceedings{Zheng:2004:HRN,
  author =       "Xizhong Zheng",
  title =        "On the Hierarchy of {$ \Delta_2^0 $}-Real Numbers",
  crossref =     "Frougny:2004:RCR",
  pages =        "192--215",
  year =         "2004",
  bibdate =      "Fri Nov 17 07:00:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.informatik.uni-trier.de/Reports/TR-08-2004/rnc6_15_zheng.pdf",
  abstract =     "A real number x is called $ \Delta_2^0 $ if its binary
                 expansion corresponds to a $ \Delta_2^0 $-set of
                 natural numbers. Such reals are just the limits of
                 computable sequences of rational numbers and hence also
                 called computably approximable. Depending on how fast
                 the sequences converge, $ \Delta_2^0 $-reals have
                 different levels of effectiveness. This leads to
                 various hierarchies of $ \Delta_2^0 $ reals. In this
                 paper we summarize several recent developments related
                 to such kind of hierarchies",
  acknowledgement = ack-nhfb,
  keywords =     "$ \Delta_2^0 $-reals; Computably approximable reals;
                 hierarchy",
}


bibtype: article
filename: fparith.bib
label: Zhu:2004:ISR
author: Hufei Zhu and Zhongding Lei and F. P. S. Chin
title: An improved square-root algorithm for BLAST
journal: j-IEEE-SIGNAL-PROCESS-LETT
volume: 11
number: 9
pages: 772--775
month: sep
monthnumber: 9
year: 2004
CODEN: ISPLEM
ISSN: 1070-9908 (print), 1558-2361 (electronic) OR 10709908 (print), 15582361 (electronic)
ISSNL: 1070-9908 OR 10709908
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
fjournal: IEEE Signal Processing Letters
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=97
rawauthor: Hufei Zhu and Zhongding Lei and F. P. S. Chin
rawtitle: An improved square-root algorithm for {BLAST}
entry:
@Article{Zhu:2004:ISR,
  author =       "Hufei Zhu and Zhongding Lei and F. P. S. Chin",
  title =        "An improved square-root algorithm for {BLAST}",
  journal =      j-IEEE-SIGNAL-PROCESS-LETT,
  volume =       "11",
  number =       "9",
  pages =        "772--775",
  month =        sep,
  year =         "2004",
  CODEN =        "ISPLEM",
  ISSN =         "1070-9908 (print), 1558-2361 (electronic)",
  ISSN-L =       "1070-9908",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Signal Processing Letters",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=97",
  summary =      "In this letter, an improved square-root algorithm for
                 Bell Labs Layered Space-Time (BLAST) system is
                 proposed. It speeds up the original square-root
                 algorithm by 36\% in terms of the number of
                 multiplications and additions. Compared with the
                 \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Zhuo:2004:SMA
author: L. Zhuo and V. K. Prasanna
booktitle: Proceedings. 18th International Parallel and Distributed Processing Symposium, 26--30 April 2004
title: Scalable and modular algorithms for floating-point matrix multiplication on FPGAs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 92--92
year: 2004
bibdate: Wed Apr 27 18:18:12 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.04.27 18:18:12 ???
acknowledgement: ack-nhfb
rawauthor: L. Zhuo and V. K. Prasanna
rawbooktitle: Proceedings. 18th International Parallel and Distributed Processing Symposium, 26--30 April 2004
rawtitle: Scalable and modular algorithms for floating-point matrix multiplication on {FPGAs}
entry:
@InProceedings{Zhuo:2004:SMA,
  author =       "L. Zhuo and V. K. Prasanna",
  booktitle =    "Proceedings. 18th International Parallel and
                 Distributed Processing Symposium, 26--30 April 2004",
  title =        "Scalable and modular algorithms for floating-point
                 matrix multiplication on {FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "92--92",
  year =         "2004",
  bibdate =      "Wed Apr 27 18:18:12 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Zimmerman:2004:DCI
author: T. Zimmerman and J. R. Hoff
title: The design of a charge-integrating modified floating-point ADC chip
journal: j-IEEE-J-SOLID-STATE-CIRCUITS
volume: 39
number: 6
pages: 895--905
month: jun
monthnumber: 6
year: 2004
CODEN: IJSCBC
ISSN: 0018-9200 (print), 1558-173X (electronic) OR 00189200 (print), 1558173X (electronic)
ISSNL: 0018-9200 OR 00189200
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Journal of Solid-State Circuits
acknowledgement: ack-nhfb
rawauthor: T. Zimmerman and J. R. Hoff
rawtitle: The design of a charge-integrating modified floating-point {ADC} chip
entry:
@Article{Zimmerman:2004:DCI,
  author =       "T. Zimmerman and J. R. Hoff",
  title =        "The design of a charge-integrating modified
                 floating-point {ADC} chip",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "39",
  number =       "6",
  pages =        "895--905",
  month =        jun,
  year =         "2004",
  CODEN =        "IJSCBC",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
  summary =      "One of the challenges posed by calorimeters in
                 high-energy physics experiments is digitizing wide
                 dynamic range charge signals at high rate to a
                 specified precision. One response to this challenge is
                 the development of the QIE (charge integrator and
                 \ldots{}).",
}


bibtype: article
filename: fparith.bib
label: Abdallah:2005:MRN
author: M. Abdallah and A. Skavantzos
title: On MultiModuli residue number systems with moduli of forms $ r^a $, $ r^b - 1 $, $ r^c + 1 $
journal: j-IEEE-TRANS-CIRCUITS-SYST-1
volume: 52
number: 7
pages: 1253--1266
month: jul
monthnumber: 7
year: 2005
DOI: https://doi.org/10.1109/TCSI.2005.851388
ISSNL: 1549-8328 OR 15498328
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=32002
fjournal: IEEE Transactions on Circuits and Systems I: Regular Papers
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919
rawauthor: M. Abdallah and A. Skavantzos
rawtitle: On {MultiModuli} residue number systems with moduli of forms $ r^a $, $ r^b - 1 $, $ r^c + 1 $
entry:
@Article{Abdallah:2005:MRN,
  author =       "M. Abdallah and A. Skavantzos",
  title =        "On {MultiModuli} residue number systems with moduli of
                 forms $ r^a $, $ r^b - 1 $, $ r^c + 1 $",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-1,
  volume =       "52",
  number =       "7",
  pages =        "1253--1266",
  month =        jul,
  year =         "2005",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/TCSI.2005.851388",
  ISSN =         "????",
  ISSN-L =       "1549-8328",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=32002",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I: Regular
                 Papers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919",
  keywords =     "residue arithmetic; residue number system",
  summary =      "The residue number system (RNS) is an integer system
                 appropriate for implementing fast digital signal
                 processors since it can support parallel, carry-free,
                 high-speed arithmetic. One of the most important
                 considerations when designing RNS systems is \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Abtahi:2005:CFR
author: M. Abtahi and P. Siy
title: Core function of an RNS number with no ambiguity
journal: j-COMPUT-MATH-APPL
volume: 50
number: 3--4
pages: 459--470
month: aug
monthnumber: 8
year: 2005
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 21:49:46 MST 2017
bibtimestamp: 2017.03.01 21:49:46 MST
URL: http://www.sciencedirect.com/science/article/pii/S0898122105002890
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: M. Abtahi and P. Siy
rawtitle: Core function of an {RNS} number with no ambiguity
entry:
@Article{Abtahi:2005:CFR,
  author =       "M. Abtahi and P. Siy",
  title =        "Core function of an {RNS} number with no ambiguity",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "50",
  number =       "3--4",
  pages =        "459--470",
  month =        aug,
  year =         "2005",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 21:49:46 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0898122105002890",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: inproceedings
filename: fparith.bib
label: Adharapurapu:2005:LSO
author: Pavan Adharapurapu and Milos Ercegovac
title: A Linear-System Operator based Scheme for Evaluation of Multinomials
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-178.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Pavan Adharapurapu and Milo{\v{s}} Ercegovac
rawtitle: A Linear-System Operator based Scheme for Evaluation of Multinomials
abstract:
We present a radix-2 online computational scheme for evaluating multinomials in a fixed-point number representation system. Its main advantage is that it can adapt to any evaluation graph representing the multinomial. Evaluation graphs are efficient representations of multinomials in a factored form. The proposed scheme maps subgraphs of the evaluation graph using linear-system operators. These operators transform the expressions represented by the subgraphs into systems of linear equations. The linear equations are then solved in an online, most-significant-digit-first fashion. The scheme produces, after an initial delay, one output digit per iteration for inputs within range. The iteration time is equal to the sum of the delays of a redundant adder, multiplexer, register and a selection unit and is independent of the size of the multinomial and the precision of the inputs/outputs. The initial delay is proportional to the diameter of the evaluation graph and the maximum number of children of any addition node in the graph. The proposed method lends itself to implementation using simple, highly regular hardware with serial interconnections between modules.

rawabstract:
We present a radix-2 online computational scheme for evaluating multinomials in a fixed-point number representation system. Its main advantage is that it can adapt to any evaluation graph representing the multinomial. Evaluation graphs are efficient representations of multinomials in a factored form. The proposed scheme maps subgraphs of the evaluation graph using linear-system operators. These operators transform the expressions represented by the subgraphs into systems of linear equations. The linear equations are then solved in an online, most-significant-digit-first fashion. The scheme produces, after an initial delay, one output digit per iteration for inputs within range. The iteration time is equal to the sum of the delays of a redundant adder, multiplexer, register and a selection unit and is independent of the size of the multinomial and the precision of the inputs/outputs. The initial delay is proportional to the diameter of the evaluation graph and the maximum number of children of any addition node in the graph. The proposed method lends itself to implementation using simple, highly regular hardware with serial interconnections between modules.

entry:
@InProceedings{Adharapurapu:2005:LSO,
  author =       "Pavan Adharapurapu and Milo{\v{s}} Ercegovac",
  title =        "A Linear-System Operator based Scheme for Evaluation
                 of Multinomials",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-178.pdf",
  abstract =     "We present a radix-2 online computational scheme for
                 evaluating multinomials in a fixed-point number
                 representation system. Its main advantage is that it
                 can adapt to any evaluation graph representing the
                 multinomial. Evaluation graphs are efficient
                 representations of multinomials in a factored form. The
                 proposed scheme maps subgraphs of the evaluation graph
                 using linear-system operators. These operators
                 transform the expressions represented by the subgraphs
                 into systems of linear equations. The linear equations
                 are then solved in an online,
                 most-significant-digit-first fashion. The scheme
                 produces, after an initial delay, one output digit per
                 iteration for inputs within range. The iteration time
                 is equal to the sum of the delays of a redundant adder,
                 multiplexer, register and a selection unit and is
                 independent of the size of the multinomial and the
                 precision of the inputs/outputs. The initial delay is
                 proportional to the diameter of the evaluation graph
                 and the maximum number of children of any addition node
                 in the graph. The proposed method lends itself to
                 implementation using simple, highly regular hardware
                 with serial interconnections between modules.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: inproceedings
filename: fparith.bib
label: Aharoni:2005:SCI
author: Merav Aharoni and Sigal Asaf and Ron Maharik and Ilan Nehama and Ilya Nikulshin and Abraham Ziv
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-136.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Merav Aharoni and Sigal Asaf and Ron Maharik and Ilan Nehama and Ilya Nikulshin and Abraham Ziv
title:
Solving Constraints on the Invisible Bits of the Intermediate Result for Floating-Point Verification

abstract:
Test generation for datapath floating-point verification involves targeting intricate corner cases, which can often be solved only through complex constraint solving.par In the process of calculating the result, we use an intermediate result whose significand comprises a finite number of bits and a sticky bit that is 0 if and only if the intermediate result is exact. We refer to all the bits beyond those represented in the final result as the invisible bits. We deal with corner cases that can only be defined via constraints on the intermediate result.par Our work investigates the following problem: Given a floating-point operation, and constraints on the invisible bits and the sticky bit, find two inputs for the operation that yield an intermediate result compatible with the constraints.par The paper supplies a deterministic solution for addition and subtraction, and probabilistic solutions for multiplication and division. It also discusses the application of these algorithms to the verification of floating-point implementations.

rawabstract:
Test generation for datapath floating-point verification involves targeting intricate corner cases, which can often be solved only through complex constraint solving.\par In the process of calculating the result, we use an intermediate result whose significand comprises a finite number of bits and a sticky bit that is 0 if and only if the intermediate result is exact. We refer to all the bits beyond those represented in the final result as the invisible bits. We deal with corner cases that can only be defined via constraints on the intermediate result.\par Our work investigates the following problem: Given a floating-point operation, and constraints on the invisible bits and the sticky bit, find two inputs for the operation that yield an intermediate result compatible with the constraints.\par The paper supplies a deterministic solution for addition and subtraction, and probabilistic solutions for multiplication and division. It also discusses the application of these algorithms to the verification of floating-point implementations.

rawtitle:
Solving Constraints on the Invisible Bits of the Intermediate Result for Floating-Point Verification

entry:
@InProceedings{Aharoni:2005:SCI,
  author =       "Merav Aharoni and Sigal Asaf and Ron Maharik and Ilan
                 Nehama and Ilya Nikulshin and Abraham Ziv",
  title =        "Solving Constraints on the Invisible Bits of the
                 Intermediate Result for Floating-Point Verification",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-136.pdf",
  abstract =     "Test generation for datapath floating-point
                 verification involves targeting intricate corner cases,
                 which can often be solved only through complex
                 constraint solving.\par

                 In the process of calculating the result, we use an
                 intermediate result whose significand comprises a
                 finite number of bits and a sticky bit that is 0 if and
                 only if the intermediate result is exact. We refer to
                 all the bits beyond those represented in the final
                 result as the invisible bits. We deal with corner cases
                 that can only be defined via constraints on the
                 intermediate result.\par

                 Our work investigates the following problem: Given a
                 floating-point operation, and constraints on the
                 invisible bits and the sticky bit, find two inputs for
                 the operation that yield an intermediate result
                 compatible with the constraints.\par

                 The paper supplies a deterministic solution for
                 addition and subtraction, and probabilistic solutions
                 for multiplication and division. It also discusses the
                 application of these algorithms to the verification of
                 floating-point implementations.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: article
filename: fparith.bib
label: Alvarez:2005:FMF
author: C. Alvarez and J. Corbal and M. Valero
title: Fuzzy Memoization for Floating-Point Multimedia Applications
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 7
pages: 922--927
month: jul
monthnumber: 7
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.119
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:17 MDT 2011
bibtimestamp: 2011.07.04 16:17:17 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1432675
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: C. Alvarez and J. Corbal and M. Valero
rawtitle: Fuzzy Memoization for Floating-Point Multimedia Applications
entry:
@Article{Alvarez:2005:FMF,
  author =       "C. Alvarez and J. Corbal and M. Valero",
  title =        "Fuzzy Memoization for Floating-Point Multimedia
                 Applications",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "7",
  pages =        "922--927",
  month =        jul,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.119",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:17 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1432675",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "Instruction memoization is a promising technique to
                 reduce the power consumption and increase the
                 performance of future low-end/mobile multimedia
                 systems. Power and performance efficiency can be
                 improved by reusing instances of an already executed
                 \ldots{}",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2005:HAP
author: Anonymous
title: How to Avoid Performance Penalties for Gradual-Underflow Behavior
pages: 922--927
year: 2005
bibdate: Fri Oct 14 17:01:56 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.10.14 17:01:56 ???
URL: http://www.intel.com/cd/ids/developer/asmo-na/eng/dc/pentium4/knowledgebase/90575.htm
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: Anonymous
rawtitle: How to Avoid Performance Penalties for Gradual-Underflow Behavior
abstract:
The Pentium 4 processor supports calculation involving sub-normals with special code stored in 'Read Only Memory', which is not pipelined as are calculations in the normalized range. In order to avoid the performance penalty, such processors often support an abrupt-underflow mode, where sub-normals are ``flushed'' immediately to zero. Where an Intel processor supports FTZ, it is possible to set the mode at run-time and to change it to suit the requirements of a program that may require full protection of accuracy in certain code sequences and fast execution in others.

remark:
Discusses mechanisms for selecting flush-to-zero behavior on Pentium 4 processors in Microsoft Windows and GNU/Linux.

rawabstract:
The Pentium 4 processor supports calculation involving sub-normals with special code stored in 'Read Only Memory', which is not pipelined as are calculations in the normalized range. In order to avoid the performance penalty, such processors often support an abrupt-underflow mode, where sub-normals are ``flushed'' immediately to zero. Where an Intel processor supports FTZ, it is possible to set the mode at run-time and to change it to suit the requirements of a program that may require full protection of accuracy in certain code sequences and fast execution in others.

entry:
@Misc{Anonymous:2005:HAP,
  author =       "Anonymous",
  title =        "How to Avoid Performance Penalties for
                 Gradual-Underflow Behavior",
  howpublished = "World-Wide Web document",
  year =         "2005",
  bibdate =      "Fri Oct 14 17:01:56 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.intel.com/cd/ids/developer/asmo-na/eng/dc/pentium4/knowledgebase/90575.htm",
  abstract =     "The Pentium 4 processor supports calculation involving
                 sub-normals with special code stored in 'Read Only
                 Memory', which is not pipelined as are calculations in
                 the normalized range. In order to avoid the performance
                 penalty, such processors often support an
                 abrupt-underflow mode, where sub-normals are
                 ``flushed'' immediately to zero. Where an Intel
                 processor supports FTZ, it is possible to set the mode
                 at run-time and to change it to suit the requirements
                 of a program that may require full protection of
                 accuracy in certain code sequences and fast execution
                 in others.",
  acknowledgement = ack-nhfb,
  remark =       "Discusses mechanisms for selecting flush-to-zero
                 behavior on Pentium 4 processors in Microsoft Windows
                 and GNU/Linux.",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2005:TMF
author: Anonymous
title: Test of Mathematical Functions of the Standard C Library
pages: 922--927
month: jun
monthnumber: 6
year: 2005
bibdate: Fri Jun 24 19:55:16 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 19:55:16 ???
URL: http://www.vinc17.org/research/testlibm/
acknowledgement: ack-nhfb
howpublished: World-Wide Web software project archive
rawauthor: Anonymous
rawtitle: Test of Mathematical Functions of the {Standard C Library}
abstract:
Some of the mathematical functions of the standard C library have been tested on worst cases for the exact rounding in double precision. The following table gives the ratio or the number of incorrect roundings for various machines, in the rounding to nearest mode.

rawabstract:
Some of the mathematical functions of the standard C library have been tested on worst cases for the exact rounding in double precision. The following table gives the ratio or the number of incorrect roundings for various machines, in the rounding to nearest mode.

entry:
@Misc{Anonymous:2005:TMF,
  author =       "Anonymous",
  title =        "Test of Mathematical Functions of the {Standard C
                 Library}",
  howpublished = "World-Wide Web software project archive",
  month =        jun,
  year =         "2005",
  bibdate =      "Fri Jun 24 19:55:16 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.vinc17.org/research/testlibm/",
  abstract =     "Some of the mathematical functions of the standard C
                 library have been tested on worst cases for the exact
                 rounding in double precision. The following table gives
                 the ratio or the number of incorrect roundings for
                 various machines, in the rounding to nearest mode.",
  acknowledgement = ack-nhfb,
  xxnote =       "LOOK AT THIS MORE!!!",
}


bibtype: article
filename: fparith.bib
label: Antelo:2005:DRD
author: E. Antelo and T. Lang and P. Montuschi and A. Nannarelli
title: Digit-recurrence dividers with reduced logical depth
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 7
pages: 837--851
month: jul
monthnumber: 7
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.115
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:17 MDT 2011
bibtimestamp: 2011.07.04 16:17:17 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1432667
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: E. Antelo and T. Lang and P. Montuschi and A. Nannarelli
rawtitle: Digit-recurrence dividers with reduced logical depth
entry:
@Article{Antelo:2005:DRD,
  author =       "E. Antelo and T. Lang and P. Montuschi and A.
                 Nannarelli",
  title =        "Digit-recurrence dividers with reduced logical depth",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "7",
  pages =        "837--851",
  month =        jul,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.115",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:17 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1432667",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Antelo:2005:LLD
author: Elisardo Antelo and Tomas Lang and Paolo Montuschi and Alberto Nannarelli
title: Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-116.pdf
keywords: ARITH-17; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Elisardo Antelo and Tom{\'a}s Lang and Paolo Montuschi and Alberto Nannarelli
rawtitle: Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture
abstract:
The reciprocal and square-root reciprocal operations are important in several applications. For the operations, we present algorithms that combine a digit-by-digit module and one iteration of a quadratic-convergence approximation. The latter is implemented by a digit-recurrence, which uses the digits produced by the digit-by-digit part. In this way, both parts execute in an overlapped manner, so that the total number of cycles is about half the number that would be required by the digit-by-digit part alone. Because of the approximation, correct rounding of the result cannot be obtained directly in all cases; we propose a variable-time implementation that produces the correctly rounded result with a small average overhead. Radix-4 implementations are described and have been synthesized. They achieve the same cycle time as the standard digit-by-digit implementation, resulting in a speed-up of about 2 and, because of the approximation part, the area factor is also about 2. We also show a combined implementation for both operations that has essentially the same complexity as that for square-root reciprocal alone.

rawabstract:
The reciprocal and square-root reciprocal operations are important in several applications. For the operations, we present algorithms that combine a digit-by-digit module and one iteration of a quadratic-convergence approximation. The latter is implemented by a digit-recurrence, which uses the digits produced by the digit-by-digit part. In this way, both parts execute in an overlapped manner, so that the total number of cycles is about half the number that would be required by the digit-by-digit part alone. Because of the approximation, correct rounding of the result cannot be obtained directly in all cases; we propose a variable-time implementation that produces the correctly rounded result with a small average overhead. Radix-4 implementations are described and have been synthesized. They achieve the same cycle time as the standard digit-by-digit implementation, resulting in a speed-up of about 2 and, because of the approximation part, the area factor is also about 2. We also show a combined implementation for both operations that has essentially the same complexity as that for square-root reciprocal alone.

entry:
@InProceedings{Antelo:2005:LLD,
  author =       "Elisardo Antelo and Tom{\'a}s Lang and Paolo Montuschi
                 and Alberto Nannarelli",
  title =        "Low Latency Digit-Recurrence Reciprocal and
                 Square-Root Reciprocal Algorithm and Architecture",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-116.pdf",
  abstract =     "The reciprocal and square-root reciprocal operations
                 are important in several applications. For the
                 operations, we present algorithms that combine a
                 digit-by-digit module and one iteration of a
                 quadratic-convergence approximation. The latter is
                 implemented by a digit-recurrence, which uses the
                 digits produced by the digit-by-digit part. In this
                 way, both parts execute in an overlapped manner, so
                 that the total number of cycles is about half the
                 number that would be required by the digit-by-digit
                 part alone. Because of the approximation, correct
                 rounding of the result cannot be obtained directly in
                 all cases; we propose a variable-time implementation
                 that produces the correctly rounded result with a small
                 average overhead. Radix-4 implementations are described
                 and have been synthesized. They achieve the same cycle
                 time as the standard digit-by-digit implementation,
                 resulting in a speed-up of about 2 and, because of the
                 approximation part, the area factor is also about 2. We
                 also show a combined implementation for both operations
                 that has essentially the same complexity as that for
                 square-root reciprocal alone.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17; correct rounding; floating-point
                 arithmetic",
  pagecount =    "8",
}


bibtype: inproceedings
filename: fparith.bib
label: Antelo:2005:LLP
author: Elisardo Antelo and Julio Villalba
title: Low Latency Pipelined Circular CORDIC
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-132.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Elisardo Antelo and Julio Villalba
rawtitle: Low Latency Pipelined Circular {CORDIC}
abstract:
The pipelined CORDIC with linear approximation to rotation has been proposed to achieve reductions in delay, power and area; however, the schemes for rotation (multiplication) and vectoring (division) complicate implementation in a single unit. In this work, we improve the linear approximation scheme, leading to a unified implementation for rotation and vectoring where fully parallel tree multipliers are used instead of the second half of CORDIC iterations. We also combine the linear approximation to rotation with the scale factor compensation so that the compensation is performed concurrently with the rotation process. Comparison with other designs is also provided.

rawabstract:
The pipelined CORDIC with linear approximation to rotation has been proposed to achieve reductions in delay, power and area; however, the schemes for rotation (multiplication) and vectoring (division) complicate implementation in a single unit. In this work, we improve the linear approximation scheme, leading to a unified implementation for rotation and vectoring where fully parallel tree multipliers are used instead of the second half of CORDIC iterations. We also combine the linear approximation to rotation with the scale factor compensation so that the compensation is performed concurrently with the rotation process. Comparison with other designs is also provided.

entry:
@InProceedings{Antelo:2005:LLP,
  author =       "Elisardo Antelo and Julio Villalba",
  title =        "Low Latency Pipelined Circular {CORDIC}",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-132.pdf",
  abstract =     "The pipelined CORDIC with linear approximation to
                 rotation has been proposed to achieve reductions in
                 delay, power and area; however, the schemes for
                 rotation (multiplication) and vectoring (division)
                 complicate implementation in a single unit. In this
                 work, we improve the linear approximation scheme,
                 leading to a unified implementation for rotation and
                 vectoring where fully parallel tree multipliers are
                 used instead of the second half of CORDIC iterations.
                 We also combine the linear approximation to rotation
                 with the scale factor compensation so that the
                 compensation is performed concurrently with the
                 rotation process. Comparison with other designs is also
                 provided.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: inproceedings
filename: fparith.bib
label: Arnold:2005:BIR
author: M. G. Arnold and J. Ruan
title: Bipartite Implementation of the Residue Logarithmic Number System
crossref: Luk:2005:ASP
pages: ??--??
year: 2005
bibdate: Fri Jun 24 18:11:43 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 18:11:43 ???
note: Accepted for publication.
acknowledgement: ack-nhfb
rawauthor: M. G. Arnold and J. Ruan
rawnote: Accepted for publication.
rawtitle: Bipartite Implementation of the Residue Logarithmic Number System
entry:
@InProceedings{Arnold:2005:BIR,
  author =       "M. G. Arnold and J. Ruan",
  title =        "Bipartite Implementation of the Residue Logarithmic
                 Number System",
  crossref =     "Luk:2005:ASP",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Fri Jun 24 18:11:43 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Accepted for publication.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Arnold:2005:RLN
author: Mark Arnold
title: The Residue Logarithmic Number System: Theory and Implementation
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-163.pdf; http://www.cse.lehigh.edu/~caar/rlns.pdf
keywords: ARITH-17; Logarithmic Number System; Residue Number System
acknowledgement: ack-nhfb
rawauthor: Mark Arnold
rawtitle: The Residue Logarithmic Number System: Theory and Implementation
abstract:
The Residue Logarithmic Number System (RLNS) represents real values as quantized logarithms which, in turn, are represented using the Residue Number System (RNS). Compared to the conventional Logarithmic Number System (LNS) in which quantized logarithms are represented as binary integers, RLNS offers faster multiplication and division times. RLNS and LNS use a table lookup involving all bits for addition. The width, dynamic range, precision and naive table size of RLNS (with careful moduli selection) is as good as those for conventional LNS.par Conventional LNS can be more efficient than naive addition lookup. First, commutativity allows interchanging arguments. Second, the addition function is often essentially zero, and does not have to be tabulated. In binary, comparisons are easy. In residue, comparisons are slow. Although RLNS inherently demands comparison, this paper shows a novel way comparisons can be performed in parallel to the lookup from a small table. This paper also describes a novel tool that generates synthesizable Verilog, making RLNS viable in practical applications that can benefit from shorter multiply and divide times.

rawabstract:
The Residue Logarithmic Number System (RLNS) represents real values as quantized logarithms which, in turn, are represented using the Residue Number System (RNS). Compared to the conventional Logarithmic Number System (LNS) in which quantized logarithms are represented as binary integers, RLNS offers faster multiplication and division times. RLNS and LNS use a table lookup involving all bits for addition. The width, dynamic range, precision and na{\"\i}ve table size of RLNS (with careful moduli selection) is as good as those for conventional LNS.\par Conventional LNS can be more efficient than na{\"\i}ve addition lookup. First, commutativity allows interchanging arguments. Second, the addition function is often essentially zero, and does not have to be tabulated. In binary, comparisons are easy. In residue, comparisons are slow. Although RLNS inherently demands comparison, this paper shows a novel way comparisons can be performed in parallel to the lookup from a small table. This paper also describes a novel tool that generates synthesizable Verilog, making RLNS viable in practical applications that can benefit from shorter multiply and divide times.

entry:
@InProceedings{Arnold:2005:RLN,
  author =       "Mark Arnold",
  title =        "The Residue Logarithmic Number System: Theory and
                 Implementation",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-163.pdf;
                 http://www.cse.lehigh.edu/~caar/rlns.pdf",
  abstract =     "The Residue Logarithmic Number System (RLNS)
                 represents real values as quantized logarithms which,
                 in turn, are represented using the Residue Number
                 System (RNS). Compared to the conventional Logarithmic
                 Number System (LNS) in which quantized logarithms are
                 represented as binary integers, RLNS offers faster
                 multiplication and division times. RLNS and LNS use a
                 table lookup involving all bits for addition. The
                 width, dynamic range, precision and na{\"\i}ve table
                 size of RLNS (with careful moduli selection) is as good
                 as those for conventional LNS.\par

                 Conventional LNS can be more efficient than na{\"\i}ve
                 addition lookup. First, commutativity allows
                 interchanging arguments. Second, the addition function
                 is often essentially zero, and does not have to be
                 tabulated. In binary, comparisons are easy. In residue,
                 comparisons are slow. Although RLNS inherently demands
                 comparison, this paper shows a novel way comparisons
                 can be performed in parallel to the lookup from a small
                 table. This paper also describes a novel tool that
                 generates synthesizable Verilog, making RLNS viable in
                 practical applications that can benefit from shorter
                 multiply and divide times.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17; Logarithmic Number System; Residue Number
                 System",
  pagecount =    "10",
}


bibtype: misc
filename: fparith.bib
label: Bailey:2005:DFDa
author: David H. Bailey
title: DDFUN90: Fortran-90 double-double package
pages: ??--??
day: 11
month: mar
monthnumber: 3
year: 2005
bibdate: Tue Nov 22 05:48:53 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.11.22 05:48:53 ???
URL: http://crd.lbl.gov/~dhbailey/mpdist/; http://crd.lbl.gov/~dhbailey/mpdist/ddfun90.tar.gz
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
howpublished: World-Wide Web site with software archives.
rawauthor: David H. Bailey
rawtitle: {DDFUN90}: {Fortran-90} double-double package
abstract:
This package contains software for performing double-double arithmetic (approximately 32 decimal digits). It is similar to the qd package above in functionality, and in fact, an application program written for one should be compatible with the other. However this is entirely written in Fortran-90.

rawabstract:
This package contains software for performing double-double arithmetic (approximately 32 decimal digits). It is similar to the qd package above in functionality, and in fact, an application program written for one should be compatible with the other. However this is entirely written in Fortran-90.

entry:
@Misc{Bailey:2005:DFDa,
  author =       "David H. Bailey",
  title =        "{DDFUN90}: {Fortran-90} double-double package",
  howpublished = "World-Wide Web site with software archives.",
  day =          "11",
  month =        mar,
  year =         "2005",
  bibdate =      "Tue Nov 22 05:48:53 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://crd.lbl.gov/~dhbailey/mpdist/;
                 http://crd.lbl.gov/~dhbailey/mpdist/ddfun90.tar.gz",
  abstract =     "This package contains software for performing
                 double-double arithmetic (approximately 32 decimal
                 digits). It is similar to the qd package above in
                 functionality, and in fact, an application program
                 written for one should be compatible with the other.
                 However this is entirely written in Fortran-90.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation",
}


bibtype: misc
filename: fparith.bib
label: Bailey:2005:DFDb
author: David H. Bailey
title: DSFUN90: Fortran-90 double-single package
pages: ??--??
day: 11
month: mar
monthnumber: 3
year: 2005
bibdate: Tue Nov 22 05:48:53 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.11.22 05:48:53 ???
URL: http://crd.lbl.gov/~dhbailey/mpdist/; http://crd.lbl.gov/~dhbailey/mpdist/dsfun90.tar.gz
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
howpublished: World-Wide Web site with software archives.
rawauthor: David H. Bailey
rawtitle: {DSFUN90}: {Fortran-90} double-single package
abstract:
This package contains software for performing double-single arithmetic (approximately 15 decimal digits). It is entirely written in Fortran-90. It is targeted to systems, such as game systems, that do not support IEEE 64-bit floating-point arithmetic.

rawabstract:
This package contains software for performing double-single arithmetic (approximately 15 decimal digits). It is entirely written in Fortran-90. It is targeted to systems, such as game systems, that do not support IEEE 64-bit floating-point arithmetic.

entry:
@Misc{Bailey:2005:DFDb,
  author =       "David H. Bailey",
  title =        "{DSFUN90}: {Fortran-90} double-single package",
  howpublished = "World-Wide Web site with software archives.",
  day =          "11",
  month =        mar,
  year =         "2005",
  bibdate =      "Tue Nov 22 05:48:53 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://crd.lbl.gov/~dhbailey/mpdist/;
                 http://crd.lbl.gov/~dhbailey/mpdist/dsfun90.tar.gz",
  abstract =     "This package contains software for performing
                 double-single arithmetic (approximately 15 decimal
                 digits). It is entirely written in Fortran-90. It is
                 targeted to systems, such as game systems, that do not
                 support IEEE 64-bit floating-point arithmetic.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation",
}


bibtype: article
filename: fparith.bib
label: Bailey:2005:HPF
author: David H. Bailey
title: High-Precision Floating-Point Arithmetic in Scientific Computation
journal: j-COMPUT-SCI-ENG
volume: 7
number: 3
pages: 54--61
month: may
monthnumber: 5
year: 2005
CODEN: CSENFA
DOI: https://doi.org/10.1109/MCSE.2005.52
ISSN: 1521-9615 (print), 1558-366X (electronic) OR 15219615 (print), 1558366X (electronic)
ISSNL: 1521-9615 OR 15219615
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: Computing in Science and Engineering
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5992
rawauthor: David H. Bailey
rawtitle: High-Precision Floating-Point Arithmetic in Scientific Computation
bibsource:
https://www.math.utah.edu/pub/tex/bib/computscieng.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://csdl.computer.org/comp/mags/cs/2005/03/c3054abs.htm; http://csdl.computer.org/dl/mags/cs/2005/03/c3054.pdf

entry:
@Article{Bailey:2005:HPF,
  author =       "David H. Bailey",
  title =        "High-Precision Floating-Point Arithmetic in Scientific
                 Computation",
  journal =      j-COMPUT-SCI-ENG,
  volume =       "7",
  number =       "3",
  pages =        "54--61",
  month =        may # "\slash " # jun,
  year =         "2005",
  CODEN =        "CSENFA",
  DOI =          "https://doi.org/10.1109/MCSE.2005.52",
  ISSN =         "1521-9615 (print), 1558-366X (electronic)",
  ISSN-L =       "1521-9615",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computscieng.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/mags/cs/2005/03/c3054abs.htm;
                 http://csdl.computer.org/dl/mags/cs/2005/03/c3054.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing in Science and Engineering",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5992",
  summary =      "IEEE 64-bit floating-point arithmetic is sufficient
                 for most scientific applications, but a rapidly growing
                 body of scientific computing applications requires a
                 higher level of numeric precision. Software packages
                 have yielded interesting scientific \ldots{}",
}


bibtype: misc
filename: fparith.bib
label: Bailey:2005:QDD
author: David H. Bailey
title: QD: double-double and quad double package
pages: 54--61
day: 24
month: aug
monthnumber: 8
year: 2005
bibdate: Tue Nov 22 05:48:53 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.11.22 05:48:53 ???
URL: http://crd.lbl.gov/~dhbailey/mpdist/; http://crd.lbl.gov/~dhbailey/mpdist/qd.tar.gz
acknowledgement: ack-nhfb
howpublished: World-Wide Web site with software archives.
rawauthor: David H. Bailey
rawtitle: {QD}: double-double and quad double package
abstract:
This package supports both a double-double datatype (approx. 32 decimal digits) and a quad-double datatype (approx. 64 decimal digits). The computational library is written in C++. Both C++ and Fortran-90 high-level language interfaces are provided to permit one to use convert an existing C++ or Fortran-90 program to use the library with only minor changes to the source code. In most cases only a few type statements and (for Fortran-90 programs) read / write statements need to be changed. PSLQ and numerical quadrature programs are included.

rawabstract:
This package supports both a double-double datatype (approx. 32 decimal digits) and a quad-double datatype (approx. 64 decimal digits). The computational library is written in C++. Both C++ and Fortran-90 high-level language interfaces are provided to permit one to use convert an existing C++ or Fortran-90 program to use the library with only minor changes to the source code. In most cases only a few type statements and (for Fortran-90 programs) read\slash write statements need to be changed. PSLQ and numerical quadrature programs are included.

entry:
@Misc{Bailey:2005:QDD,
  author =       "David H. Bailey",
  title =        "{QD}: double-double and quad double package",
  howpublished = "World-Wide Web site with software archives.",
  day =          "24",
  month =        aug,
  year =         "2005",
  bibdate =      "Tue Nov 22 05:48:53 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://crd.lbl.gov/~dhbailey/mpdist/;
                 http://crd.lbl.gov/~dhbailey/mpdist/qd.tar.gz",
  abstract =     "This package supports both a double-double datatype
                 (approx. 32 decimal digits) and a quad-double datatype
                 (approx. 64 decimal digits). The computational library
                 is written in C++. Both C++ and Fortran-90 high-level
                 language interfaces are provided to permit one to use
                 convert an existing C++ or Fortran-90 program to use
                 the library with only minor changes to the source code.
                 In most cases only a few type statements and (for
                 Fortran-90 programs) read\slash write statements need
                 to be changed. PSLQ and numerical quadrature programs
                 are included.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Bajard:2005:AOP
author: Jean-Claude Bajard and Laurent Imbert and Thomas Plantard
title: Arithmetic Operations in the Polynomial Modular Number System
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-168.pdf
keywords: ARITH-17; Lattice theory; Modular arithmetic; Number system; Table-based methods
acknowledgement: ack-nhfb
rawauthor: Jean-Claude Bajard and Laurent Imbert and Thomas Plantard
rawtitle: Arithmetic Operations in the Polynomial Modular Number System
abstract:
We propose a new number representation and arithmetic for the elements of the ring of integers modulo p. The so-called Polynomial Modular Number System (PMNS) allows for fast polynomial arithmetic and easy parallelization. The most important contribution of this paper is the fundamental theorem of a Modular Number System, which provides a bound for the coefficients of the polynomials used to represent the set $ mathbb Z_p $. However, we also propose a complete set of algorithms to perform the arithmetic operations over a PMNS, which make this system of practical interest for people concerned about efficient implementation of modular arithmetic.

rawabstract:
We propose a new number representation and arithmetic for the elements of the ring of integers modulo p. The so-called Polynomial Modular Number System (PMNS) allows for fast polynomial arithmetic and easy parallelization. The most important contribution of this paper is the fundamental theorem of a Modular Number System, which provides a bound for the coefficients of the polynomials used to represent the set $ \mathbb {Z}_p $. However, we also propose a complete set of algorithms to perform the arithmetic operations over a PMNS, which make this system of practical interest for people concerned about efficient implementation of modular arithmetic.

entry:
@InProceedings{Bajard:2005:AOP,
  author =       "Jean-Claude Bajard and Laurent Imbert and Thomas
                 Plantard",
  title =        "Arithmetic Operations in the Polynomial Modular Number
                 System",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-168.pdf",
  abstract =     "We propose a new number representation and arithmetic
                 for the elements of the ring of integers modulo p. The
                 so-called Polynomial Modular Number System (PMNS)
                 allows for fast polynomial arithmetic and easy
                 parallelization. The most important contribution of
                 this paper is the fundamental theorem of a Modular
                 Number System, which provides a bound for the
                 coefficients of the polynomials used to represent the
                 set $ \mathbb {Z}_p $. However, we also propose a
                 complete set of algorithms to perform the arithmetic
                 operations over a PMNS, which make this system of
                 practical interest for people concerned about efficient
                 implementation of modular arithmetic.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17; Lattice theory; Modular arithmetic; Number
                 system; Table-based methods",
  pagecount =    "8",
}


bibtype: inproceedings
filename: fparith.bib
label: Bajard:2005:PMM
author: Jean-Claude Bajard and Laurent Imbert and Graham Jullien
title: Parallel Montgomery Multiplication in $ mathrm GF(2^k) $ using Trinomial Residue Arithmetic
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-169.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Jean-Claude Bajard and Laurent Imbert and Graham Jullien
rawtitle: Parallel {Montgomery} Multiplication in {$ \mathrm {GF}(2^k) $} using Trinomial Residue Arithmetic
abstract:
We propose the first general multiplication algorithm in $ mathrm GF(2^k) $ with a subquadratic area complexity of $ mathcal O(k^8 / 5) = mathcal O(k^1.6) $. Using the Chinese Remainder Theorem, we represent the elements of $ mathrm GF(2^k) $; i.e., the polynomials in $ mathrm GF(2)[X] $ of degree at most $ k - 1 $, by the remainder modulo a set of $n$ pairwise prime trinomials, $ T_1, ldots , T_n $, of degree $d$ and such that $ n d geq k $. Our algorithm is based on Montgomery's multiplication applied to the ring formed by the direct product of the trinomials.

rawabstract:
We propose the first general multiplication algorithm in $ \mathrm {GF}(2^k) $ with a subquadratic area complexity of $ \mathcal {O}(k^{8 / 5}) = \mathcal {O}(k^{1.6}) $. Using the Chinese Remainder Theorem, we represent the elements of $ \mathrm {GF}(2^k) $; i.e., the polynomials in $ \mathrm {GF}(2)[X] $ of degree at most $ k - 1 $, by the remainder modulo a set of $n$ pairwise prime trinomials, $ T_1, \ldots {}, T_n $, of degree $d$ and such that $ n d \geq k $. Our algorithm is based on Montgomery's multiplication applied to the ring formed by the direct product of the trinomials.

entry:
@InProceedings{Bajard:2005:PMM,
  author =       "Jean-Claude Bajard and Laurent Imbert and Graham
                 Jullien",
  title =        "Parallel {Montgomery} Multiplication in {$ \mathrm
                 {GF}(2^k) $} using Trinomial Residue Arithmetic",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-169.pdf",
  abstract =     "We propose the first general multiplication algorithm
                 in $ \mathrm {GF}(2^k) $ with a subquadratic area
                 complexity of $ \mathcal {O}(k^{8 / 5}) = \mathcal
                 {O}(k^{1.6}) $. Using the Chinese Remainder Theorem, we
                 represent the elements of $ \mathrm {GF}(2^k) $; i.e.,
                 the polynomials in $ \mathrm {GF}(2)[X] $ of degree at
                 most $ k - 1 $, by the remainder modulo a set of $n$
                 pairwise prime trinomials, $ T_1, \ldots {}, T_n $, of
                 degree $d$ and such that $ n d \geq k $. Our algorithm
                 is based on Montgomery's multiplication applied to the
                 ring formed by the direct product of the trinomials.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: misc
filename: fparith.bib
label: Beebe:2005:MPA
author: Nelson H. F. Beebe
title: Multiple-precision arithmetic FAQ
pages: ??--??
month: sep
monthnumber: 9
year: 2005
bibdate: Wed Aug 30 17:46:43 2006
bibtimestamp: 2006.08.30 17:46:43 ???
note: This report is updated frequently.
URL: https://www.math.utah.edu/faq/mp/
acknowledgement: ack-nhfb
howpublished: World-Wide Web frequently-asked question document.
rawauthor: Nelson H. F. Beebe
rawnote: This report is updated frequently.
rawtitle: Multiple-precision arithmetic {FAQ}
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/b/beebe-nelson-h-f.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Misc{Beebe:2005:MPA,
  author =       "Nelson H. F. Beebe",
  title =        "Multiple-precision arithmetic {FAQ}",
  howpublished = "World-Wide Web frequently-asked question document.",
  month =        sep,
  year =         "2005",
  bibdate =      "Wed Aug 30 17:46:43 2006",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/b/beebe-nelson-h-f.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "This report is updated frequently.",
  URL =          "https://www.math.utah.edu/faq/mp/",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Beuchat:2005:MAR
author: Jean-Luc Beuchat and Jean-Michel Muller
editor: Stamatis Vassiliadis and Nikitas J. Dimopoulos and Sanjay Vishnu Rajopadhye
title: Multiplication algorithms for Radix-2 RN-codings and two's complement numbers
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 303--308
year: 2005
DOI: https://doi.org/10.1109/ASAP.2005.45
ISBN: 0-7695-2407-9 OR 0769524079
ISBN13: 978-0-7695-2407-8 OR 9780769524078
ISSN: 1063-6862 OR 10636862
bibdate: Sun Jun 19 14:52:45 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.06.19 14:52:45 ???
URL: http://ieeexplore.ieee.org/servlet/opac?punumber=10334
acknowledgement: ack-nhfb
bookpages: xiii + 419
rawauthor: Jean-Luc Beuchat and Jean-Michel Muller
raweditor: Stamatis Vassiliadis and Nikitas J. Dimopoulos and Sanjay Vishnu Rajopadhye
rawtitle: Multiplication algorithms for Radix-2 {RN}-codings and two's complement numbers
booktitle:
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23--25 July 2005, Samos, Greece

rawbooktitle:
{Proceedings of the 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23--25 July 2005, Samos, Greece}

entry:
@InProceedings{Beuchat:2005:MAR,
  author =       "Jean-Luc Beuchat and Jean-Michel Muller",
  editor =       "Stamatis Vassiliadis and Nikitas J. Dimopoulos and
                 Sanjay Vishnu Rajopadhye",
  booktitle =    "{Proceedings of the 16th IEEE International Conference
                 on Application-Specific Systems, Architectures, and
                 Processors (ASAP 2005), 23--25 July 2005, Samos,
                 Greece}",
  title =        "Multiplication algorithms for Radix-2 {RN}-codings and
                 two's complement numbers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  bookpages =    "xiii + 419",
  pages =        "303--308",
  year =         "2005",
  DOI =          "https://doi.org/10.1109/ASAP.2005.45",
  ISBN =         "0-7695-2407-9",
  ISBN-13 =      "978-0-7695-2407-8",
  ISSN =         "1063-6862",
  LCCN =         "",
  bibdate =      "Sun Jun 19 14:52:45 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/servlet/opac?punumber=10334",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Blanck:2005:EEC
author: J. Blanck
title: Efficient exact computation of iterated maps
journal: j-J-LOGIC-ALG-PROG
volume: 64
number: 1
pages: 41--59
month: jul
monthnumber: 7
year: 2005
DOI: https://doi.org/10.1016/j.jlap.2004.07.004
ISSN: 1567-8326 (print), 1873-5940 (electronic) OR 15678326 (print), 18735940 (electronic)
ISSNL: 1567-8326 OR 15678326
bibdate: Thu Oct 17 10:09:18 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 10:09:18 ???
fjournal: Journal of Logic and Algebraic Programming
remark: Special issue on Practical development of exact real number computation.
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/15678326
rawauthor: J. Blanck
rawtitle: Efficient exact computation of iterated maps
entry:
@Article{Blanck:2005:EEC,
  author =       "J. Blanck",
  title =        "Efficient exact computation of iterated maps",
  journal =      j-J-LOGIC-ALG-PROG,
  volume =       "64",
  number =       "1",
  pages =        "41--59",
  month =        jul,
  year =         "2005",
  DOI =          "https://doi.org/10.1016/j.jlap.2004.07.004",
  ISSN =         "1567-8326 (print), 1873-5940 (electronic)",
  ISSN-L =       "1567-8326",
  bibdate =      "Thu Oct 17 10:09:18 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Logic and Algebraic Programming",
  journal-URL =  "http://www.sciencedirect.com/science/journal/15678326",
  remark =       "Special issue on Practical development of exact real
                 number computation.",
}


bibtype: article
filename: fparith.bib
label: Boehm:2005:CRJ
author: Hans-J. Boehm
title: The constructive reals as a Java Library
journal: j-J-LOGIC-ALG-PROG
volume: 64
number: 1
pages: 3--11
month: jul
monthnumber: 7
year: 2005
DOI: https://doi.org/10.1016/j.jlap.2004.07.002
ISSN: 1567-8326 (print), 1873-5940 (electronic) OR 15678326 (print), 18735940 (electronic)
ISSNL: 1567-8326 OR 15678326
bibdate: Wed Oct 16 18:43:22 2019
bibtimestamp: 2019.10.16 18:43:22 ???
URL: https://www.sciencedirect.com/science/article/pii/S1567832604000736
fjournal: Journal of Logic and Algebraic Programming
remark: Special issue on Practical development of exact real number computation.
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/15678326
rawauthor: Hans-J. Boehm
rawtitle: The constructive reals as a {Java Library}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/java2000.bib

entry:
@Article{Boehm:2005:CRJ,
  author =       "Hans-J. Boehm",
  title =        "The constructive reals as a {Java Library}",
  journal =      j-J-LOGIC-ALG-PROG,
  volume =       "64",
  number =       "1",
  pages =        "3--11",
  month =        jul,
  year =         "2005",
  DOI =          "https://doi.org/10.1016/j.jlap.2004.07.002",
  ISSN =         "1567-8326 (print), 1873-5940 (electronic)",
  ISSN-L =       "1567-8326",
  bibdate =      "Wed Oct 16 18:43:22 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/java2000.bib",
  URL =          "https://www.sciencedirect.com/science/article/pii/S1567832604000736",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Logic and Algebraic Programming",
  journal-URL =  "http://www.sciencedirect.com/science/journal/15678326",
  remark =       "Special issue on Practical development of exact real
                 number computation.",
}


bibtype: inproceedings
filename: fparith.bib
label: Boldo:2005:SFC
author: Sylvie Boldo and Jean-Michel Muller
title: Some Functions Computable with a Fused-mac
crossref: Montuschi:2005:PIS
pages: 52--58
year: 2005
DOI: https://doi.org/10.1109/ARITH.2005.39
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-106.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo and Jean-Michel Muller
rawtitle: Some Functions Computable with a Fused-mac
abstract:
The fused multiply accumulate instruction (fused-mac) that is available on some current processors such as the Power PC or the Itanium eases some calculations. We give examples of some floating-point functions (such as ulp(x) or Nextafter(x, y)), or some useful tests, that are easily computable using a fused-mac. Then, we show that, with rounding to the nearest, the error of a fused-mac instruction is exactly representable as the sum of two floating-point numbers. We give an algorithm that computes that error.

rawabstract:
The fused multiply accumulate instruction (fused-mac) that is available on some current processors such as the Power PC or the Itanium eases some calculations. We give examples of some floating-point functions (such as ulp(x) or Nextafter(x, y)), or some useful tests, that are easily computable using a fused-mac. Then, we show that, with rounding to the nearest, the error of a fused-mac instruction is exactly representable as the sum of two floating-point numbers. We give an algorithm that computes that error.

entry:
@InProceedings{Boldo:2005:SFC,
  author =       "Sylvie Boldo and Jean-Michel Muller",
  title =        "Some Functions Computable with a Fused-mac",
  crossref =     "Montuschi:2005:PIS",
  pages =        "52--58",
  year =         "2005",
  DOI =          "https://doi.org/10.1109/ARITH.2005.39",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-106.pdf",
  abstract =     "The fused multiply accumulate instruction (fused-mac)
                 that is available on some current processors such as
                 the Power PC or the Itanium eases some calculations. We
                 give examples of some floating-point functions (such as
                 ulp(x) or Nextafter(x, y)), or some useful tests, that
                 are easily computable using a fused-mac. Then, we show
                 that, with rounding to the nearest, the error of a
                 fused-mac instruction is exactly representable as the
                 sum of two floating-point numbers. We give an algorithm
                 that computes that error.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "7",
}


bibtype: article
filename: fparith.bib
label: Bowman:2005:AVS
author: K. O. Bowman and L. R. Shenton
title: The asymptotic variance and skewness of maximum likelihood estimators using Maple
journal: j-J-STAT-COMPUT-SIMUL
volume: 75
number: 12
pages: 975--986
year: 2005
CODEN: JSCSAJ
DOI: https://doi.org/10.1080/00949650412331321142
ISSNL: 0094-9655 OR 00949655
bibdate: Tue Apr 22 09:12:30 MDT 2014
bibtimestamp: 2014.04.22 09:12:30 MDT
fjournal: Journal of Statistical Computation and Simulation
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/gscs20
rawauthor: K. O. Bowman and L. R. Shenton
rawtitle: The asymptotic variance and skewness of maximum likelihood estimators using {Maple}
ISSN:
0094-9655 (print), 1026-7778 (electronic), 1563-5163 OR 00949655 (print), 10267778 (electronic), 15635163

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jstatcomputsimul.bib; https://www.math.utah.edu/pub/tex/bib/maple-extract.bib

entry:
@Article{Bowman:2005:AVS,
  author =       "K. O. Bowman and L. R. Shenton",
  title =        "The asymptotic variance and skewness of maximum
                 likelihood estimators using {Maple}",
  journal =      j-J-STAT-COMPUT-SIMUL,
  volume =       "75",
  number =       "12",
  pages =        "975--986",
  year =         "2005",
  CODEN =        "JSCSAJ",
  DOI =          "https://doi.org/10.1080/00949650412331321142",
  ISSN =         "0094-9655 (print), 1026-7778 (electronic), 1563-5163",
  ISSN-L =       "0094-9655",
  bibdate =      "Tue Apr 22 09:12:30 MDT 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jstatcomputsimul.bib;
                 https://www.math.utah.edu/pub/tex/bib/maple-extract.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Statistical Computation and Simulation",
  journal-URL =  "http://www.tandfonline.com/loi/gscs20",
}


bibtype: inproceedings
filename: fparith.bib
label: Brisebarre:2005:CRM
author: Nicolas Brisebarre and Jean-Michel Muller
title: Correctly Rounded Multiplication by Arbitrary Precision Constants
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-122.pdf
keywords: ARITH-17; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Jean-Michel Muller
rawtitle: Correctly Rounded Multiplication by Arbitrary Precision Constants
abstract:
We introduce an algorithm for multiplying a floating-point number $x$ by a constant $C$ that is not exactly representable in floating-point arithmetic. Our algorithm uses a multiplication and a fused multiply and add instruction. We give methods for checking whether, for a given value of $C$ and a given floating-point format, our algorithm returns a correctly rounded result for any $x$. When it does not, our methods give the values $x$ for which it does not.

rawabstract:
We introduce an algorithm for multiplying a floating-point number $x$ by a constant $C$ that is not exactly representable in floating-point arithmetic. Our algorithm uses a multiplication and a fused multiply and add instruction. We give methods for checking whether, for a given value of $C$ and a given floating-point format, our algorithm returns a correctly rounded result for any $x$. When it does not, our methods give the values $x$ for which it does not.

entry:
@InProceedings{Brisebarre:2005:CRM,
  author =       "Nicolas Brisebarre and Jean-Michel Muller",
  title =        "Correctly Rounded Multiplication by Arbitrary
                 Precision Constants",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-122.pdf",
  abstract =     "We introduce an algorithm for multiplying a
                 floating-point number $x$ by a constant $C$ that is not
                 exactly representable in floating-point arithmetic. Our
                 algorithm uses a multiplication and a fused multiply
                 and add instruction. We give methods for checking
                 whether, for a given value of $C$ and a given
                 floating-point format, our algorithm returns a
                 correctly rounded result for any $x$. When it does not,
                 our methods give the values $x$ for which it does
                 not.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17; correct rounding; floating-point
                 arithmetic",
  pagecount =    "8",
}


bibtype: article
filename: fparith.bib
label: Brisebarre:2005:NRR
author: Nicolas Brisebarre and David Defour and Peter Kornerup and Jean-Michel Muller and Nathalie Revol
title: A New Range-Reduction Algorithm
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 331--339
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.36
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue May 30 12:14:00 MDT 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.30 12:14:00 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-16; range reduction
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Nicolas Brisebarre and David Defour and Peter Kornerup and Jean-Michel Muller and Nathalie Revol
rawtitle: A New Range-Reduction Algorithm
URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0331abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0331.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0331.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388197.pdf; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388197

abstract:
Range-reduction is a key point for getting accurate elementary function routines. We introduce a new algorithm that is fast for input arguments belonging to the most common domains, yet accurate over the full double-precision range.

rawabstract:
Range-reduction is a key point for getting accurate elementary function routines. We introduce a new algorithm that is fast for input arguments belonging to the most common domains, yet accurate over the full double-precision range.

entry:
@Article{Brisebarre:2005:NRR,
  author =       "Nicolas Brisebarre and David Defour and Peter Kornerup
                 and Jean-Michel Muller and Nathalie Revol",
  title =        "A New Range-Reduction Algorithm",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "331--339",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.36",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue May 30 12:14:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0331abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0331.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0331.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388197.pdf;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388197",
  abstract =     "Range-reduction is a key point for getting accurate
                 elementary function routines. We introduce a new
                 algorithm that is fast for input arguments belonging to
                 the most common domains, yet accurate over the full
                 double-precision range.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16; range reduction",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
}


bibtype: inproceedings
filename: fparith.bib
label: Bruguera:2005:FPF
author: Javier Bruguera and Tomas Lang
title: Floating-point Fused Multiply-Add: Reduced Latency for Floating-Point Addition
crossref: Montuschi:2005:PIS
pages: 42--51
year: 2005
DOI: https://doi.org/10.1109/ARITH.2005.22
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-102.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Javier Bruguera and Tom{\'a}s Lang
rawtitle: Floating-point Fused Multiply-Add: Reduced Latency for Floating-Point Addition
abstract:
In this paper we propose an architecture for the computation of the double precision floating point multiply add fused (MAF) operation $ A + (B times C) $ that permits to compute the floating point addition with lower latency than floating point multiplication and MAF. While previous MAF architectures compute the three operations with the same latency, the proposed architecture permits to skip the first pipeline stages, those related with the multiplication $ B times C $, in case of an addition. For instance, for a MAF unit pipelined into three or five stages, the latency of the floating point addition is reduced to two or three cycles, respectively. To achieve the latency reduction for floating-point addition, the alignment shifter, which in previous organizations is in parallel with the multiplication, is moved so that the multiplication can be bypassed. To avoid that this modification increases the critical path, a double-datapath organization is used, in which the alignment and normalization are in separate paths. Moreover, we use the techniques developed previously of combining the addition and the rounding and of performing the normalization before the addition.

rawabstract:
In this paper we propose an architecture for the computation of the double precision floating point multiply add fused (MAF) operation $ A + (B \times C) $ that permits to compute the floating point addition with lower latency than floating point multiplication and MAF. While previous MAF architectures compute the three operations with the same latency, the proposed architecture permits to skip the first pipeline stages, those related with the multiplication $ B \times C $, in case of an addition. For instance, for a MAF unit pipelined into three or five stages, the latency of the floating point addition is reduced to two or three cycles, respectively. To achieve the latency reduction for floating-point addition, the alignment shifter, which in previous organizations is in parallel with the multiplication, is moved so that the multiplication can be bypassed. To avoid that this modification increases the critical path, a double-datapath organization is used, in which the alignment and normalization are in separate paths. Moreover, we use the techniques developed previously of combining the addition and the rounding and of performing the normalization before the addition.

entry:
@InProceedings{Bruguera:2005:FPF,
  author =       "Javier Bruguera and Tom{\'a}s Lang",
  title =        "Floating-point Fused Multiply-Add: Reduced Latency for
                 Floating-Point Addition",
  crossref =     "Montuschi:2005:PIS",
  pages =        "42--51",
  year =         "2005",
  DOI =          "https://doi.org/10.1109/ARITH.2005.22",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-102.pdf",
  abstract =     "In this paper we propose an architecture for the
                 computation of the double precision floating point
                 multiply add fused (MAF) operation $ A + (B \times C) $
                 that permits to compute the floating point addition
                 with lower latency than floating point multiplication
                 and MAF. While previous MAF architectures compute the
                 three operations with the same latency, the proposed
                 architecture permits to skip the first pipeline stages,
                 those related with the multiplication $ B \times C $,
                 in case of an addition. For instance, for a MAF unit
                 pipelined into three or five stages, the latency of the
                 floating point addition is reduced to two or three
                 cycles, respectively. To achieve the latency reduction
                 for floating-point addition, the alignment shifter,
                 which in previous organizations is in parallel with the
                 multiplication, is moved so that the multiplication can
                 be bypassed. To avoid that this modification increases
                 the critical path, a double-datapath organization is
                 used, in which the alignment and normalization are in
                 separate paths. Moreover, we use the techniques
                 developed previously of combining the addition and the
                 rounding and of performing the normalization before the
                 addition.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "10",
}


bibtype: article
filename: fparith.bib
label: Burgess:2005:PRI
author: N. Burgess
title: Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder
journal: j-IEEE-TRANS-VLSI-SYST
volume: 13
number: 2
pages: 266--277
month: feb
monthnumber: 2
year: 2005
CODEN: IEVSE9
DOI: https://doi.org/10.1109/TVLSI.2004.840764
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: N. Burgess
rawtitle: Prenormalization rounding in {IEEE} floating-point operations using a flagged prefix adder
abstract:
This paper demonstrates how IEEE 754 floating-point standard compliant rounding can be merged with carry-propagate addition in floating-point unit (FPU) designs by using a novel adaptation of the prefix adder. The paper considers add/subtract, multiply, ldots 

rawabstract:
This paper demonstrates how IEEE 754 floating-point standard compliant rounding can be merged with carry-propagate addition in floating-point unit (FPU) designs by using a novel adaptation of the prefix adder. The paper considers add/subtract, multiply, \ldots{}

entry:
@Article{Burgess:2005:PRI,
  author =       "N. Burgess",
  title =        "Prenormalization rounding in {IEEE} floating-point
                 operations using a flagged prefix adder",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "13",
  number =       "2",
  pages =        "266--277",
  month =        feb,
  year =         "2005",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2004.840764",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper demonstrates how IEEE 754 floating-point
                 standard compliant rounding can be merged with
                 carry-propagate addition in floating-point unit (FPU)
                 designs by using a novel adaptation of the prefix
                 adder. The paper considers add/subtract, multiply,
                 \ldots{}",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
  summary =      "This paper demonstrates how IEEE 754 floating-point
                 standard compliant rounding can be merged with
                 carry-propagate addition in floating-point unit (FPU)
                 designs by using a novel adaptation of the prefix
                 adder. The paper considers add/subtract, multiply
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Chakraborty:2005:BFP
author: M. Chakraborty and A. Mitra
title: A block floating-point realization of the gradient adaptive lattice filter
journal: j-IEEE-SIGNAL-PROCESS-LETT
volume: 12
number: 4
pages: 265--268
month: apr
monthnumber: 4
year: 2005
CODEN: ISPLEM
ISSN: 1070-9908 (print), 1558-2361 (electronic) OR 10709908 (print), 15582361 (electronic)
ISSNL: 1070-9908 OR 10709908
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Signal Processing Letters
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=97
rawauthor: M. Chakraborty and A. Mitra
rawtitle: A block floating-point realization of the gradient adaptive lattice filter
entry:
@Article{Chakraborty:2005:BFP,
  author =       "M. Chakraborty and A. Mitra",
  title =        "A block floating-point realization of the gradient
                 adaptive lattice filter",
  journal =      j-IEEE-SIGNAL-PROCESS-LETT,
  volume =       "12",
  number =       "4",
  pages =        "265--268",
  month =        apr,
  year =         "2005",
  CODEN =        "ISPLEM",
  ISSN =         "1070-9908 (print), 1558-2361 (electronic)",
  ISSN-L =       "1070-9908",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Signal Processing Letters",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=97",
  summary =      "We present a novel scheme to implement the gradient
                 adaptive lattice (GAL) algorithm using block floating
                 point (BFP) arithmetic that permits processing of data
                 over a wide dynamic range at a cost significantly less
                 than that of a floating point (FP) \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Chang:2005:LCB
author: Ku-Young Chang and Dowon Hong and Hyun-Sook Cho
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 12
pages: 1628--1630
month: dec
monthnumber: 12
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.199
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:20 MDT 2011
bibtimestamp: 2011.07.04 16:17:20 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1524942
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Ku-Young Chang and Dowon Hong and Hyun-Sook Cho
title:
Low complexity bit-parallel multiplier for $ rm GF(2^m) $ defined by all-one polynomials using redundant representation

rawtitle:
Low complexity bit-parallel multiplier for {$ {\rm GF}(2^m) $} defined by all-one polynomials using redundant representation

entry:
@Article{Chang:2005:LCB,
  author =       "Ku-Young Chang and Dowon Hong and Hyun-Sook Cho",
  title =        "Low complexity bit-parallel multiplier for {$ {\rm
                 GF}(2^m) $} defined by all-one polynomials using
                 redundant representation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "12",
  pages =        "1628--1630",
  month =        dec,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.199",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:20 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1524942",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Chaniotakis:2005:LNB
author: Eleftherios Chaniotakis and Paraskevas Kalivas and Kiamal Pekmestzi
title: Long Number Bit-Serial Squarers
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-162.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Eleftherios Chaniotakis and Paraskevas Kalivas and Kiamal Pekmestzi
rawtitle: Long Number Bit-Serial Squarers
abstract:
New bit serial squarers for long numbers in LSB first form, are presented in this paper. The first presented scheme is a 50% operational efficient squarer than has the half number of cells compared to the traditional squarers. The second scheme is a 100% operational efficient squarer. In this scheme, the number of the cells remain unchanged compared to other proposed schemes but the number of the required registers is reduced significantly. Both schemes are presented in non-systolic and systolic form and are compared against other squarers presented in the bibliography from the aspect of hardware complexity.

rawabstract:
New bit serial squarers for long numbers in LSB first form, are presented in this paper. The first presented scheme is a 50\% operational efficient squarer than has the half number of cells compared to the traditional squarers. The second scheme is a 100\% operational efficient squarer. In this scheme, the number of the cells remain unchanged compared to other proposed schemes but the number of the required registers is reduced significantly. Both schemes are presented in non-systolic and systolic form and are compared against other squarers presented in the bibliography from the aspect of hardware complexity.

entry:
@InProceedings{Chaniotakis:2005:LNB,
  author =       "Eleftherios Chaniotakis and Paraskevas Kalivas and
                 Kiamal Pekmestzi",
  title =        "Long Number Bit-Serial Squarers",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-162.pdf",
  abstract =     "New bit serial squarers for long numbers in LSB first
                 form, are presented in this paper. The first presented
                 scheme is a 50\% operational efficient squarer than has
                 the half number of cells compared to the traditional
                 squarers. The second scheme is a 100\% operational
                 efficient squarer. In this scheme, the number of the
                 cells remain unchanged compared to other proposed
                 schemes but the number of the required registers is
                 reduced significantly. Both schemes are presented in
                 non-systolic and systolic form and are compared against
                 other squarers presented in the bibliography from the
                 aspect of hardware complexity.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "8",
}


bibtype: article
filename: fparith.bib
label: Chatterjee:2005:DEH
title: Design and exploitation of a high-performance SIMD floating-point unit for Blue Gene/L
journal: j-IBM-JRD
volume: 49
number: 2/3
pages: 377--391
year: 2005
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Wed Jun 1 08:14:41 MDT 2005
bibsource: http://www.research.ibm.com/journal/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.01 08:14:41 MDT
URL: http://www.research.ibm.com/journal/rd/492/chatterjee.pdf
fjournal: IBM Journal of Research and Development
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawtitle: Design and exploitation of a high-performance {SIMD} floating-point unit for {Blue Gene/L}
author:
S. Chatterjee and L. R. Bachega and P. Bergner and K. A. Dockser and J. A. Gunnels and M. Gupta and F. G. Gustavson and C. A. Lapkowski and G. K. Liu and M. Mendell and R. Nair and C. D. Wait and T. J. C. Ward and P. Wu

abstract:
We describe the design of a dual-issue single-instruction, multiple-data-like (SIMD-like) extension of the IBM PowerPC 440 floating-point unit (FPU) core and the compiler and algorithmic techniques to exploit it. This extended FPU is targeted at both the IBM massively parallel Blue Gene/L machine and the more pervasive embedded platforms. We discuss the hardware and software codesign that was essential in order to fully realize the performance benefits of the FPU when constrained by the memory bandwidth limitations and high penalties for misaligned data access imposed by the memory hierarchy on a Blue Gene/L node. Using both hand-optimized and compiled code for key linear algebraic kernels, we validate the architectural design choices, evaluate the success of the compiler, and quantify the effectiveness of the novel algorithm design techniques. Our measurements show that the combination of algorithm, compiler, and hardware delivers a significant fraction of peak floating-point performance for compute-bound-kernels, such as matrix multiplication, and delivers a significant fraction of peak memory bandwidth for memory-bound kernels, such as DAXPY, while remaining largely insensitive to data alignment.

rawabstract:
We describe the design of a dual-issue single-instruction, multiple-data-like (SIMD-like) extension of the IBM PowerPC 440 floating-point unit (FPU) core and the compiler and algorithmic techniques to exploit it. This extended FPU is targeted at both the IBM massively parallel Blue Gene/L machine and the more pervasive embedded platforms. We discuss the hardware and software codesign that was essential in order to fully realize the performance benefits of the FPU when constrained by the memory bandwidth limitations and high penalties for misaligned data access imposed by the memory hierarchy on a Blue Gene/L node. Using both hand-optimized and compiled code for key linear algebraic kernels, we validate the architectural design choices, evaluate the success of the compiler, and quantify the effectiveness of the novel algorithm design techniques. Our measurements show that the combination of algorithm, compiler, and hardware delivers a significant fraction of peak floating-point performance for compute-bound-kernels, such as matrix multiplication, and delivers a significant fraction of peak memory bandwidth for memory-bound kernels, such as DAXPY, while remaining largely insensitive to data alignment.

rawauthor:
S. Chatterjee and L. R. Bachega and P. Bergner and K. A. Dockser and J. A. Gunnels and M. Gupta and F. G. Gustavson and C. A. Lapkowski and G. K. Liu and M. Mendell and R. Nair and C. D. Wait and T. J. C. Ward and P. Wu

entry:
@Article{Chatterjee:2005:DEH,
  author =       "S. Chatterjee and L. R. Bachega and P. Bergner and K.
                 A. Dockser and J. A. Gunnels and M. Gupta and F. G.
                 Gustavson and C. A. Lapkowski and G. K. Liu and M.
                 Mendell and R. Nair and C. D. Wait and T. J. C. Ward
                 and P. Wu",
  title =        "Design and exploitation of a high-performance {SIMD}
                 floating-point unit for {Blue Gene/L}",
  journal =      j-IBM-JRD,
  volume =       "49",
  number =       "2/3",
  pages =        "377--391",
  month =        "????",
  year =         "2005",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Wed Jun 1 08:14:41 MDT 2005",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.research.ibm.com/journal/rd/492/chatterjee.pdf",
  abstract =     "We describe the design of a dual-issue
                 single-instruction, multiple-data-like (SIMD-like)
                 extension of the IBM PowerPC 440 floating-point unit
                 (FPU) core and the compiler and algorithmic techniques
                 to exploit it. This extended FPU is targeted at both
                 the IBM massively parallel Blue Gene/L machine and the
                 more pervasive embedded platforms. We discuss the
                 hardware and software codesign that was essential in
                 order to fully realize the performance benefits of the
                 FPU when constrained by the memory bandwidth
                 limitations and high penalties for misaligned data
                 access imposed by the memory hierarchy on a Blue Gene/L
                 node. Using both hand-optimized and compiled code for
                 key linear algebraic kernels, we validate the
                 architectural design choices, evaluate the success of
                 the compiler, and quantify the effectiveness of the
                 novel algorithm design techniques. Our measurements
                 show that the combination of algorithm, compiler, and
                 hardware delivers a significant fraction of peak
                 floating-point performance for compute-bound-kernels,
                 such as matrix multiplication, and delivers a
                 significant fraction of peak memory bandwidth for
                 memory-bound kernels, such as DAXPY, while remaining
                 largely insensitive to data alignment.",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  ordernumber =  "G322-0240",
}


bibtype: inproceedings
filename: fparith.bib
label: Choi:2005:PPA
author: Youngmoon Choi and Earl Swartzlander
title: Parallel Prefix Adder Design with Matrix Representation
crossref: Montuschi:2005:PIS
pages: ??--??
year: 2005
bibdate: Wed Jun 22 07:02:55 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.22 07:02:55 ???
URL: http://arith17.polito.it/final/paper-107.pdf
keywords: ARITH-17
acknowledgement: ack-nhfb
rawauthor: Youngmoon Choi and Earl Swartzlander
rawtitle: Parallel Prefix Adder Design with Matrix Representation
abstract:
This paper presents a one-shot batch process that generates a wide range of designs for a group of parallel prefix adders. The prefix adders are represented by two two-dimensional matrixes and two vectors. This matrix representation makes it possible to compose two functions for gate sizing which calculate the delay and the total transistor width of the carry propagation graph of adders. After gate sizing, the critical path net-lists of the carry propagation graph are generated from the matrix representation for spice delay calculation. The process is illustrated by generating sets of delay and total transistor width pairs for 32-bit and 64-bit cases.

rawabstract:
This paper presents a one-shot batch process that generates a wide range of designs for a group of parallel prefix adders. The prefix adders are represented by two two-dimensional matrixes and two vectors. This matrix representation makes it possible to compose two functions for gate sizing which calculate the delay and the total transistor width of the carry propagation graph of adders. After gate sizing, the critical path net-lists of the carry propagation graph are generated from the matrix representation for spice delay calculation. The process is illustrated by generating sets of delay and total transistor width pairs for 32-bit and 64-bit cases.

entry:
@InProceedings{Choi:2005:PPA,
  author =       "Youngmoon Choi and Earl Swartzlander",
  title =        "Parallel Prefix Adder Design with Matrix
                 Representation",
  crossref =     "Montuschi:2005:PIS",
  pages =        "??--??",
  year =         "2005",
  bibdate =      "Wed Jun 22 07:02:55 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arith17.polito.it/final/paper-107.pdf",
  abstract =     "This paper presents a one-shot batch process that
                 generates a wide range of designs for a group of
                 parallel prefix adders. The prefix adders are
                 represented by two two-dimensional matrixes and two
                 vectors. This matrix representation makes it possible
                 to compose two functions for gate sizing which
                 calculate the delay and the total transistor width of
                 the carry propagation graph of adders. After gate
                 sizing, the critical path net-lists of the carry
                 propagation graph are generated from the matrix
                 representation for spice delay calculation. The process
                 is illustrated by generating sets of delay and total
                 transistor width pairs for 32-bit and 64-bit cases.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-17",
  pagecount =    "9",
}


bibtype: article
filename: fparith.bib
label: Cotofana:2005:ARA
author: Sorin Cotofana and Casper Lageweg and Stamatis Vassiliadis
title: Addition Related Arithmetic Operations via Controlled Transport of Charge
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 243--256
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.40
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 16:17:15 MDT 2011
bibtimestamp: 2011.07.04 16:17:15 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-16
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Sorin Cotofana and Casper Lageweg and Stamatis Vassiliadis
rawtitle: Addition Related Arithmetic Operations via Controlled Transport of Charge
URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0243abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0243.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0243.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388190.pdf?isnumber=30205&prod=JNL&arnumber=1388190&arSt=+243&ared=+256&arAuthor=Cotofana%2C+S.%3B+Lageweg%2C+C.%3B+Vassiliadis%2C+S.; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388190&count=13&index=1; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388190

entry:
@Article{Cotofana:2005:ARA,
  author =       "Sorin Cotofana and Casper Lageweg and Stamatis
                 Vassiliadis",
  title =        "Addition Related Arithmetic Operations via Controlled
                 Transport of Charge",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "243--256",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.40",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 16:17:15 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0243abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0243.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0243.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388190.pdf?isnumber=30205&prod=JNL&arnumber=1388190&arSt=+243&ared=+256&arAuthor=Cotofana%2C+S.%3B+Lageweg%2C+C.%3B+Vassiliadis%2C+S.;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388190&count=13&index=1;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388190",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
}


bibtype: techreport
filename: fparith.bib
label: Cowlishaw:2005:GDA
author: Mike Cowlishaw
title: General Decimal Arithmetic Specification
type: Report
number: Version 1.50
institution: IBM UK Laboratories
address: Hursley, UK
pages: iii + 63
day: 9
month: dec
monthnumber: 12
year: 2005
bibdate: Thu Mar 02 10:58:02 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.03.02 10:58:02 ???
URL: http://www2.hursley.ibm.com/decimal/decarith.pdf; http://www2.hursley.ibm.com/decimal/decarith.ps
keywords: correct rounding; decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Mike Cowlishaw
rawtitle: General Decimal Arithmetic Specification
abstract:
This document defines a general purpose decimal arithmetic. A correct implementation of this specification is a decimal arithmetic which conforms to the requirements of the IEEE standard 854-1987, while supporting integer and unrounded floating-point arithmetic as subsets. Appendix A describes a simplified subset of the full arithmetic which implements the decimal floating-point arithmetic defined in ANSI Standard X3.274-1996 (the REXX programming language) (this provides the model for the unrounded floating-point rules). Appendix B summarizes the design concepts behind the decimal arithmetic. Appendix C lists the changes to this specification.

rawabstract:
This document defines a general purpose decimal arithmetic. A correct implementation of this specification is a decimal arithmetic which conforms to the requirements of the IEEE standard 854-1987, while supporting integer and unrounded floating-point arithmetic as subsets. Appendix A describes a simplified subset of the full arithmetic which implements the decimal floating-point arithmetic defined in ANSI Standard X3.274-1996 (the REXX programming language) (this provides the model for the unrounded floating-point rules). Appendix B summarizes the design concepts behind the decimal arithmetic. Appendix C lists the changes to this specification.

entry:
@TechReport{Cowlishaw:2005:GDA,
  author =       "Mike Cowlishaw",
  title =        "General Decimal Arithmetic Specification",
  type =         "Report",
  number =       "Version 1.50",
  institution =  "IBM UK Laboratories",
  address =      "Hursley, UK",
  pages =        "iii + 63",
  day =          "9",
  month =        dec,
  year =         "2005",
  bibdate =      "Thu Mar 02 10:58:02 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www2.hursley.ibm.com/decimal/decarith.pdf;
                 http://www2.hursley.ibm.com/decimal/decarith.ps",
  abstract =     "This document defines a general purpose decimal
                 arithmetic. A correct implementation of this
                 specification is a decimal arithmetic which conforms to
                 the requirements of the IEEE standard 854-1987, while
                 supporting integer and unrounded floating-point
                 arithmetic as subsets.

                 Appendix A describes a simplified subset of the full
                 arithmetic which implements the decimal floating-point
                 arithmetic defined in ANSI Standard X3.274-1996 (the
                 REXX programming language) (this provides the model for
                 the unrounded floating-point rules). Appendix B
                 summarizes the design concepts behind the decimal
                 arithmetic. Appendix C lists the changes to this
                 specification.",
  acknowledgement = ack-nhfb,
  keywords =     "correct rounding; decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Daneshbeh:2005:CUB
author: Amir K. Daneshbeh and M. Anwar Hasan
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 370--380
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.35
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue May 30 12:14:00 MDT 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.30 12:14:00 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-16
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Amir K. Daneshbeh and M. Anwar Hasan
title:
A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over $ mathrm GF(2^m) $

URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0370abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0370.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0370.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388201.pdf?isnumber=30205&prod=JNL&arnumber=1388201&arSt=+370&ared=+380&arAuthor=Daneshbeh%2C+A.K.%3B+Hasan%2C+M.A.; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388201&count=13&index=12; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388201

rawtitle:
A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over {$ \mathrm {GF}(2^m) $}

entry:
@Article{Daneshbeh:2005:CUB,
  author =       "Amir K. Daneshbeh and M. Anwar Hasan",
  title =        "A Class of Unidirectional Bit Serial Systolic
                 Architectures for Multiplicative Inversion and Division
                 over {$ \mathrm {GF}(2^m) $}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "370--380",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.35",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue May 30 12:14:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0370abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0370.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0370.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388201.pdf?isnumber=30205&prod=JNL&arnumber=1388201&arSt=+370&ared=+380&arAuthor=Daneshbeh%2C+A.K.%3B+Hasan%2C+M.A.;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388201&count=13&index=12;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388201",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
}


bibtype: article
filename: fparith.bib
label: Danysh:2005:AIV
author: Albert Danysh and Dimitri Tan
title: Architecture and Implementation of a Vector / SIMD Multiply-Accumulate Unit
journal: j-IEEE-TRANS-COMPUT
volume: 54
number: 3
pages: 284--293
month: mar
monthnumber: 3
year: 2005
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2005.41
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue May 30 12:14:00 MDT 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.30 12:14:00 MDT
fjournal: IEEE Transactions on Computers
keywords: ARITH-16
remark: Special issue on computer arithmetic: selected papers from ARITH-16.
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Albert Danysh and Dimitri Tan
rawtitle: Architecture and Implementation of a Vector\slash {SIMD} Multiply-Accumulate Unit
URL:
http://csdl.computer.org/comp/trans/tc/2005/03/t0284abs.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0284.htm; http://csdl.computer.org/dl/trans/tc/2005/03/t0284.pdf; http://ieeexplore.ieee.org/iel5/12/30205/01388193.pdf?isnumber=30205&prod=JNL&arnumber=1388193&arSt=+284&ared=+293&arAuthor=Danysh%2C+A.%3B+Tan%2C+D.; http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388193&count=13&index=4; http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388193

entry:
@Article{Danysh:2005:AIV,
  author =       "Albert Danysh and Dimitri Tan",
  title =        "Architecture and Implementation of a Vector\slash
                 {SIMD} Multiply-Accumulate Unit",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "54",
  number =       "3",
  pages =        "284--293",
  month =        mar,
  year =         "2005",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2005.41",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue May 30 12:14:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/trans/tc/2005/03/t0284abs.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0284.htm;
                 http://csdl.computer.org/dl/trans/tc/2005/03/t0284.pdf;
                 http://ieeexplore.ieee.org/iel5/12/30205/01388193.pdf?isnumber=30205&prod=JNL&arnumber=1388193&arSt=+284&ared=+293&arAuthor=Danysh%2C+A.%3B+Tan%2C+D.;
                 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=30205&arnumber=1388193&count=13&index=4;
                 http://ieeexplore.ieee.org/xpls/references.jsp?arnumber=1388193",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "ARITH-16",
  remark =       "Special issue on computer arithmetic: selected papers
                 from ARITH-16.",
}


