# bibtab

bibtype: article
filename: fparith.bib
label: Janhunen:2011:FFP
author: J. Janhunen and T. Pitkanen and O. Silven and M. Juntti
title: Fixed- and floating-point Processor Comparison for MIMO--OFDM Detector
journal: IEEE Journal of Selected Topics in Signal Processing
volume: 5
number: 8
pages: 1588--1598
month: dec
monthnumber: 12
year: 2011
DOI: https://doi.org/10.1109/JSTSP.2011.2165830
ISSN: 1932-4553 (print), 1941-0484 (electronic) OR 19324553 (print), 19410484 (electronic)
ISSNL: 1932-4553 OR 19324553
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5995137
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4200690
rawauthor: J. Janhunen and T. Pitkanen and O. Silven and M. Juntti
rawtitle: Fixed- and floating-point Processor Comparison for {MIMO--OFDM} Detector
entry:
@Article{Janhunen:2011:FFP,
  author =       "J. Janhunen and T. Pitkanen and O. Silven and M.
                 Juntti",
  title =        "Fixed- and floating-point Processor Comparison for
                 {MIMO--OFDM} Detector",
  journal =      "IEEE Journal of Selected Topics in Signal Processing",
  volume =       "5",
  number =       "8",
  pages =        "1588--1598",
  month =        dec,
  year =         "2011",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/JSTSP.2011.2165830",
  ISSN =         "1932-4553 (print), 1941-0484 (electronic)",
  ISSN-L =       "1932-4553",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5995137",
  acknowledgement = ack-nhfb,
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4200690",
}


bibtype: inproceedings
filename: fparith.bib
label: Janhunen:2011:FVF
author: J. Janhunen and P. Salmela and O. Silven and M. Juntti
booktitle: 2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)
title: Fixed- versus floating-point implementation of MIMO--OFDM detector
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 3276--3279
year: 2011
DOI: https://doi.org/10.1109/ICASSP.2011.5946721
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5946721
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5916934
rawauthor: J. Janhunen and P. Salmela and O. Silven and M. Juntti
rawbooktitle: {2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)}
rawtitle: Fixed- versus floating-point implementation of {MIMO--OFDM} detector
entry:
@InProceedings{Janhunen:2011:FVF,
  author =       "J. Janhunen and P. Salmela and O. Silven and M.
                 Juntti",
  booktitle =    "{2011 IEEE International Conference on Acoustics,
                 Speech and Signal Processing (ICASSP)}",
  title =        "Fixed- versus floating-point implementation of
                 {MIMO--OFDM} detector",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "3276--3279",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ICASSP.2011.5946721",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5946721",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5916934",
}


bibtype: article
filename: fparith.bib
label: Jeannerod:2011:CFP
author: Claude-Pierr Jeannerod and Herve Knochel and Christophe Monat and Guillaume Revy
title: Computing Floating-Point Square Roots via Bivariate Polynomial Evaluation
journal: j-IEEE-TRANS-COMPUT
volume: 60
number: 2
pages: 214--227
month: feb
monthnumber: 2
year: 2011
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2010.152
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sun Feb 20 19:15:33 2011
bibtimestamp: 2011.02.20 19:15:33 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Claude-Pierr Jeannerod and Herv{\'e} Knochel and Christophe Monat and Guillaume Revy
rawtitle: Computing Floating-Point Square Roots via Bivariate Polynomial Evaluation
abstract:
In this paper, we show how to reduce the computation of correctly rounded square roots of binary floating-point data to the fixed-point evaluation of some particular integer polynomials in two variables. By designing parallel and accurate evaluation schemes for such bivariate polynomials, we show further that this approach allows for high instruction-level parallelism (ILP) exposure, and thus, potentially low-latency implementations. Then, as an illustration, we detail a C implementation of our method in the case of IEEE 754-2008 binary32 floating-point data (formerly called single precision in the 1985 version of the IEEE 754 standard). This software implementation, which assumes 32-bit unsigned integer arithmetic only, is almost complete in the sense that it supports special operands, subnormal numbers, and all rounding-direction attributes, but not exception handling (that is, status flags are not set). Finally, we have carried out experiments with this implementation on the ST231, an integer processor from the STMicroelectronics' ST200 family, using the ST200 family VLIW compiler. The results obtained demonstrate the practical interest of our approach in that context: for all rounding-direction attributes, the generated assembly code is optimally scheduled and has indeed low latency (23 cycles).

rawabstract:
In this paper, we show how to reduce the computation of correctly rounded square roots of binary floating-point data to the fixed-point evaluation of some particular integer polynomials in two variables. By designing parallel and accurate evaluation schemes for such bivariate polynomials, we show further that this approach allows for high instruction-level parallelism (ILP) exposure, and thus, potentially low-latency implementations. Then, as an illustration, we detail a C implementation of our method in the case of IEEE 754-2008 binary32 floating-point data (formerly called single precision in the 1985 version of the IEEE 754 standard). This software implementation, which assumes 32-bit unsigned integer arithmetic only, is almost complete in the sense that it supports special operands, subnormal numbers, and all rounding-direction attributes, but not exception handling (that is, status flags are not set). Finally, we have carried out experiments with this implementation on the ST231, an integer processor from the STMicroelectronics' ST200 family, using the ST200 family VLIW compiler. The results obtained demonstrate the practical interest of our approach in that context: for all rounding-direction attributes, the generated assembly code is optimally scheduled and has indeed low latency (23 cycles).

entry:
@Article{Jeannerod:2011:CFP,
  author =       "Claude-Pierr Jeannerod and Herv{\'e} Knochel and
                 Christophe Monat and Guillaume Revy",
  title =        "Computing Floating-Point Square Roots via Bivariate
                 Polynomial Evaluation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "60",
  number =       "2",
  pages =        "214--227",
  month =        feb,
  year =         "2011",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2010.152",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sun Feb 20 19:15:33 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  abstract =     "In this paper, we show how to reduce the computation
                 of correctly rounded square roots of binary
                 floating-point data to the fixed-point evaluation of
                 some particular integer polynomials in two variables.
                 By designing parallel and accurate evaluation schemes
                 for such bivariate polynomials, we show further that
                 this approach allows for high instruction-level
                 parallelism (ILP) exposure, and thus, potentially
                 low-latency implementations. Then, as an illustration,
                 we detail a C implementation of our method in the case
                 of IEEE 754-2008 binary32 floating-point data (formerly
                 called single precision in the 1985 version of the IEEE
                 754 standard). This software implementation, which
                 assumes 32-bit unsigned integer arithmetic only, is
                 almost complete in the sense that it supports special
                 operands, subnormal numbers, and all rounding-direction
                 attributes, but not exception handling (that is, status
                 flags are not set). Finally, we have carried out
                 experiments with this implementation on the ST231, an
                 integer processor from the STMicroelectronics' ST200
                 family, using the ST200 family VLIW compiler. The
                 results obtained demonstrate the practical interest of
                 our approach in that context: for all
                 rounding-direction attributes, the generated assembly
                 code is optimally scheduled and has indeed low latency
                 (23 cycles).",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Jeannerod:2011:HSF
author: Claude-Pierre Jeannerod and Jingyan Jourdan-Lu and Christophe Monat and Guillaume Revy
title: How to Square Floats Accurately and Efficiently on the ST231 Integer Processor
crossref: Schwarz:2011:PIS
pages: 77--81
year: 2011
DOI: https://doi.org/10.1109/ARITH.2011.19
bibdate: Sat Aug 20 09:00:00 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.08.20 09:00:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992111
keywords: ARITH-20
acknowledgement: ack-nhfb
rawauthor: Claude-Pierre Jeannerod and Jingyan Jourdan-Lu and Christophe Monat and Guillaume Revy
rawtitle: How to Square Floats Accurately and Efficiently on the {ST231} Integer Processor
entry:
@InProceedings{Jeannerod:2011:HSF,
  author =       "Claude-Pierre Jeannerod and Jingyan Jourdan-Lu and
                 Christophe Monat and Guillaume Revy",
  title =        "How to Square Floats Accurately and Efficiently on the
                 {ST231} Integer Processor",
  crossref =     "Schwarz:2011:PIS",
  pages =        "77--81",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ARITH.2011.19",
  bibdate =      "Sat Aug 20 09:00:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992111",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-20",
}


bibtype: article
filename: fparith.bib
label: Jeannerod:2011:MEP
author: Claude-Pierre Jeannerod and Nicolas Louvet and Jean-Michel Muller and Adrien Panhaleux
title: Midpoints and Exact Points of Some Algebraic Functions in Floating-Point Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 60
number: 2
pages: 228--241
month: feb
monthnumber: 2
year: 2011
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2010.144
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sun Feb 20 19:15:33 2011
bibtimestamp: 2011.02.20 19:15:33 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Claude-Pierre Jeannerod and Nicolas Louvet and Jean-Michel Muller and Adrien Panhaleux
rawtitle: Midpoints and Exact Points of Some Algebraic Functions in Floating-Point Arithmetic
abstract:
When implementing a function $f$ in floating-point arithmetic, if we wish correct rounding and good performance, it is important to know if there are input floating-point values $x$ such that $ f(x) $ is either the middle of two consecutive floating-point numbers (assuming rounded-to-nearest arithmetic), or a floating-point number (assuming rounded toward $ pm infty $ or toward $0$ arithmetic). In the first case, we say that $ f(x) $ is a midpoint, and in the second case, we say that $ f(x) $ is an exact point. For some usual algebraic functions and various floating-point formats, we prove whether or not there exist midpoints or exact points. When there exist midpoints or exact points, we characterize them or list all of them (if there are not too many). The results and the techniques presented in this paper can be used in particular to deal with both the binary and the decimal formats defined in the IEEE 754-2008 standard for floating-point arithmetic.

rawabstract:
When implementing a function $f$ in floating-point arithmetic, if we wish correct rounding and good performance, it is important to know if there are input floating-point values $x$ such that $ f(x) $ is either the middle of two consecutive floating-point numbers (assuming rounded-to-nearest arithmetic), or a floating-point number (assuming rounded toward $ \pm \infty $ or toward $0$ arithmetic). In the first case, we say that $ f(x) $ is a midpoint, and in the second case, we say that $ f(x) $ is an exact point. For some usual algebraic functions and various floating-point formats, we prove whether or not there exist midpoints or exact points. When there exist midpoints or exact points, we characterize them or list all of them (if there are not too many). The results and the techniques presented in this paper can be used in particular to deal with both the binary and the decimal formats defined in the IEEE 754-2008 standard for floating-point arithmetic.

entry:
@Article{Jeannerod:2011:MEP,
  author =       "Claude-Pierre Jeannerod and Nicolas Louvet and
                 Jean-Michel Muller and Adrien Panhaleux",
  title =        "Midpoints and Exact Points of Some Algebraic Functions
                 in Floating-Point Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "60",
  number =       "2",
  pages =        "228--241",
  month =        feb,
  year =         "2011",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2010.144",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sun Feb 20 19:15:33 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  abstract =     "When implementing a function $f$ in floating-point
                 arithmetic, if we wish correct rounding and good
                 performance, it is important to know if there are input
                 floating-point values $x$ such that $ f(x) $ is either
                 the middle of two consecutive floating-point numbers
                 (assuming rounded-to-nearest arithmetic), or a
                 floating-point number (assuming rounded toward $ \pm
                 \infty $ or toward $0$ arithmetic). In the first case,
                 we say that $ f(x) $ is a midpoint, and in the second
                 case, we say that $ f(x) $ is an exact point. For some
                 usual algebraic functions and various floating-point
                 formats, we prove whether or not there exist midpoints
                 or exact points. When there exist midpoints or exact
                 points, we characterize them or list all of them (if
                 there are not too many). The results and the techniques
                 presented in this paper can be used in particular to
                 deal with both the binary and the decimal formats
                 defined in the IEEE 754-2008 standard for
                 floating-point arithmetic.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Jiang:2011:AEP
author: Hao Jiang and Roberto Barrio and Housen Li and Xiangke Liao and Lizhi Cheng and Fang Su
title: Accurate evaluation of a polynomial in Chebyshev form
journal: j-APPL-MATH-COMP
volume: 217
number: 23
pages: 9702--9716
day: 1
month: aug
monthnumber: 8
year: 2011
CODEN: AMHCBQ
DOI: https://doi.org/10.1016/j.amc.2011.04.054
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Tue Oct 25 12:05:42 MDT 2011
bibtimestamp: 2011.10.25 12:05:42 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0096300311006242
fjournal: Applied Mathematics and Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003/
rawauthor: Hao Jiang and Roberto Barrio and Housen Li and Xiangke Liao and Lizhi Cheng and Fang Su
rawtitle: Accurate evaluation of a polynomial in {Chebyshev} form
bibsource:
https://www.math.utah.edu/pub/tex/bib/applmathcomput2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Jiang:2011:AEP,
  author =       "Hao Jiang and Roberto Barrio and Housen Li and Xiangke
                 Liao and Lizhi Cheng and Fang Su",
  title =        "Accurate evaluation of a polynomial in {Chebyshev}
                 form",
  journal =      j-APPL-MATH-COMP,
  volume =       "217",
  number =       "23",
  pages =        "9702--9716",
  day =          "1",
  month =        aug,
  year =         "2011",
  CODEN =        "AMHCBQ",
  DOI =          "https://doi.org/10.1016/j.amc.2011.04.054",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Tue Oct 25 12:05:42 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/applmathcomput2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0096300311006242",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003/",
}


bibtype: article
filename: fparith.bib
label: Kainuma:2011:DIC
journal: j-IEEE-TRANS-APPL-SUPERCOND
volume: 21
number: 3
pages: 827--830
year: 2011
CODEN: ITASE9
DOI: https://doi.org/10.1109/TASC.2010.2096374
ISSN: 1051-8223 (print), 1558-2515 (electronic) OR 10518223 (print), 15582515 (electronic)
ISSNL: 1051-8223 OR 10518223
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5680618
fjournal: IEEE Transactions on Applied Superconductivity
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=77
author:
T. Kainuma and Y. Shimamura and F. Miyaoka and Y. Yamanashi and N. Yoshikawa and A. Fujimaki and K. Takagi and N. Takagi and S. Nagasawa

title:
Design and Implementation of Component Circuits of an SFQ Half-Precision floating-point Adder Using 10-kA / cm$^2$ Nb Process

rawauthor:
T. Kainuma and Y. Shimamura and F. Miyaoka and Y. Yamanashi and N. Yoshikawa and A. Fujimaki and K. Takagi and N. Takagi and S. Nagasawa

rawtitle:
Design and Implementation of Component Circuits of an {SFQ} Half-Precision floating-point Adder Using {10-kA\slash cm$^2$ Nb} Process

entry:
@Article{Kainuma:2011:DIC,
  author =       "T. Kainuma and Y. Shimamura and F. Miyaoka and Y.
                 Yamanashi and N. Yoshikawa and A. Fujimaki and K.
                 Takagi and N. Takagi and S. Nagasawa",
  title =        "Design and Implementation of Component Circuits of an
                 {SFQ} Half-Precision floating-point Adder Using
                 {10-kA\slash cm$^2$ Nb} Process",
  journal =      j-IEEE-TRANS-APPL-SUPERCOND,
  volume =       "21",
  number =       "3",
  pages =        "827--830",
  month =        "????",
  year =         "2011",
  CODEN =        "ITASE9",
  DOI =          "https://doi.org/10.1109/TASC.2010.2096374",
  ISSN =         "1051-8223 (print), 1558-2515 (electronic)",
  ISSN-L =       "1051-8223",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5680618",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=77",
  fjournal =     "IEEE Transactions on Applied Superconductivity",
}


bibtype: article
filename: fparith.bib
label: Kaivani:2011:DCR
author: Amir Kaivani and Ghassem Jaberipur
title: Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture
journal: j-COMP-J
volume: 54
number: 11
pages: 1798--1809
month: nov
monthnumber: 11
year: 2011
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/bxr012
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Fri Oct 28 10:35:35 MDT 2011
bibtimestamp: 2011.10.28 10:35:35 MDT
fjournal: Computer Journal
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
onlinedate: March 11, 2011
rawauthor: Amir Kaivani and Ghassem Jaberipur
rawtitle: Decimal {CORDIC} Rotation based on Selection by Rounding: Algorithm and Architecture
bibsource:
http://comjnl.oxfordjournals.org/content/54/11.toc; https://www.math.utah.edu/pub/tex/bib/compj2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
Hardware implementation of decimal floating-point arithmetic is a topic of great interest among the researchers in computer arithmetic and also the digital processor industry. Software packages for decimal arithmetic are actually being challenged by decimal hardware units. This spreading trend seems to include hardware implementation of elementary functions. The (Coordinate Rotation Digital Computer) CORDIC algorithm, due to its simplicity, is one of the most efficient methods for computing elementary functions. In this work, we develop a decimal CORDIC scheme with almost half number of equally long cycles with respect to the best previous design. This is achieved via retiming of the conventional CORDIC architecture and selection of the microrotation factors by rounding. However, the proposed design does not lead to a predetermined constant scaling factor. The solution that we use is to iteratively compute the logarithm of the scaling factor followed by a decimal exponentiation. The same CORDIC hardware is reused for performing the latter. The proposed CORDIC method requires $ 2 n + 3 $ cycles for $n$-digit decimal operands vs. $ 4 n $ cycles of the previous methods. Evaluations with 16-digit operands based on logical effort analysis conclude that the proposed architecture shows 82% speed advantage, at the cost of 60% more area and 2.5 KB more ROM.

rawabstract:
Hardware implementation of decimal floating-point arithmetic is a topic of great interest among the researchers in computer arithmetic and also the digital processor industry. Software packages for decimal arithmetic are actually being challenged by decimal hardware units. This spreading trend seems to include hardware implementation of elementary functions. The (Coordinate Rotation Digital Computer) CORDIC algorithm, due to its simplicity, is one of the most efficient methods for computing elementary functions. In this work, we develop a decimal CORDIC scheme with almost half number of equally long cycles with respect to the best previous design. This is achieved via retiming of the conventional CORDIC architecture and selection of the microrotation factors by rounding. However, the proposed design does not lead to a predetermined constant scaling factor. The solution that we use is to iteratively compute the logarithm of the scaling factor followed by a decimal exponentiation. The same CORDIC hardware is reused for performing the latter. The proposed CORDIC method requires $ 2 n + 3 $ cycles for $n$-digit decimal operands vs. $ 4 n $ cycles of the previous methods. Evaluations with 16-digit operands based on logical effort analysis conclude that the proposed architecture shows 82\% speed advantage, at the cost of 60\% more area and 2.5 KB more ROM.

entry:
@Article{Kaivani:2011:DCR,
  author =       "Amir Kaivani and Ghassem Jaberipur",
  title =        "Decimal {CORDIC} Rotation based on Selection by
                 Rounding: Algorithm and Architecture",
  journal =      j-COMP-J,
  volume =       "54",
  number =       "11",
  pages =        "1798--1809",
  month =        nov,
  year =         "2011",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/bxr012",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Fri Oct 28 10:35:35 MDT 2011",
  bibsource =    "http://comjnl.oxfordjournals.org/content/54/11.toc;
                 https://www.math.utah.edu/pub/tex/bib/compj2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Hardware implementation of decimal floating-point
                 arithmetic is a topic of great interest among the
                 researchers in computer arithmetic and also the digital
                 processor industry. Software packages for decimal
                 arithmetic are actually being challenged by decimal
                 hardware units. This spreading trend seems to include
                 hardware implementation of elementary functions. The
                 (Coordinate Rotation Digital Computer) CORDIC
                 algorithm, due to its simplicity, is one of the most
                 efficient methods for computing elementary functions.
                 In this work, we develop a decimal CORDIC scheme with
                 almost half number of equally long cycles with respect
                 to the best previous design. This is achieved via
                 retiming of the conventional CORDIC architecture and
                 selection of the microrotation factors by rounding.
                 However, the proposed design does not lead to a
                 predetermined constant scaling factor. The solution
                 that we use is to iteratively compute the logarithm of
                 the scaling factor followed by a decimal
                 exponentiation. The same CORDIC hardware is reused for
                 performing the latter. The proposed CORDIC method
                 requires $ 2 n + 3 $ cycles for $n$-digit decimal
                 operands vs. $ 4 n $ cycles of the previous methods.
                 Evaluations with 16-digit operands based on logical
                 effort analysis conclude that the proposed architecture
                 shows 82\% speed advantage, at the cost of 60\% more
                 area and 2.5 KB more ROM.",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  onlinedate =   "March 11, 2011",
}


bibtype: inproceedings
filename: fparith.bib
label: Kathiara:2011:AVS
author: J. Kathiara and M. Leeser
title: An Autonomous Vector / Scalar Floating Point Coprocessor for FPGAs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 33--36
year: 2011
DOI: https://doi.org/10.1109/FCCM.2011.14
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5771244
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5771180
rawauthor: J. Kathiara and M. Leeser
rawtitle: An Autonomous Vector\slash Scalar Floating Point Coprocessor for {FPGAs}
booktitle:
2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

rawbooktitle:
{2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}

entry:
@InProceedings{Kathiara:2011:AVS,
  author =       "J. Kathiara and M. Leeser",
  booktitle =    "{2011 IEEE 19th Annual International Symposium on
                 Field-Programmable Custom Computing Machines (FCCM)}",
  title =        "An Autonomous Vector\slash Scalar Floating Point
                 Coprocessor for {FPGAs}",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "33--36",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/FCCM.2011.14",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5771244",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5771180",
}


bibtype: article
filename: fparith.bib
label: Kim:2011:ZAS
author: SeongKi Kim and HaYoon Song and SangYong Han
title: ZipfAllocation: an algorithm for static allocation of movies in a cluster of video servers
journal: j-SPE
volume: 41
number: 6
pages: 695--716
month: may
monthnumber: 5
year: 2011
CODEN: SPEXBL
DOI: https://doi.org/10.1002/spe.1027
ISSN: 0038-0644 (print), 1097-024X (electronic) OR 00380644 (print), 1097024X (electronic)
ISSNL: 0038-0644 OR 00380644
bibdate: Tue Jun 21 17:09:57 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.06.21 17:09:57 MDT
fjournal: Software---Practice and Experience
acknowledgement: ack-nhfb
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X
onlinedate: 25 Nov 2010
rawauthor: SeongKi Kim and HaYoon Song and SangYong Han
rawtitle: {ZipfAllocation}: an algorithm for static allocation of movies in a cluster of video servers
entry:
@Article{Kim:2011:ZAS,
  author =       "SeongKi Kim and HaYoon Song and SangYong Han",
  title =        "{ZipfAllocation}: an algorithm for static allocation
                 of movies in a cluster of video servers",
  journal =      j-SPE,
  volume =       "41",
  number =       "6",
  pages =        "695--716",
  month =        may,
  year =         "2011",
  CODEN =        "SPEXBL",
  DOI =          "https://doi.org/10.1002/spe.1027",
  ISSN =         "0038-0644 (print), 1097-024X (electronic)",
  ISSN-L =       "0038-0644",
  bibdate =      "Tue Jun 21 17:09:57 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Software---Practice and Experience",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X",
  onlinedate =   "25 Nov 2010",
}


bibtype: article
filename: fparith.bib
label: Kong:2011:GDM
author: Inwook Kong and Earl E. Swartzlander
title: A Goldschmidt Division Method With Faster Than Quadratic Convergence
journal: j-IEEE-TRANS-VLSI-SYST
volume: 19
number: 4
pages: 696--700
month: apr
monthnumber: 4
year: 2011
CODEN: IEVSE9
DOI: https://doi.org/10.1109/tvlsi.2009.2036926
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Mon Dec 11 08:01:22 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.11 08:01:22 ???
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: Inwook Kong and Earl E. Swartzlander
rawtitle: A {Goldschmidt} Division Method With Faster Than Quadratic Convergence
abstract:
A new method to implement faster than quadratic convergence for Goldschmidt division using simple logic circuits is presented. While the approximate quotient converges quadratically in conventional Goldschmidt division, the new method achieves nearly cubic convergence. Although division with cubic convergence has been regarded as impractical due to its complexity, the proposed method reduces the logic complexity and the delay by using an approximate squarer with a simple logic implementation and a redundant binary Booth recoder. It is especially effective in a system that already has a radix-8 multiplier. As a result, the effective area for the reciprocal table can be reduced by 25.4%. The proposed method has been verified by SystemC and Verilog models. The final results are confirmed by simulation with both random double precision numbers and an exhaustive suite of 17-bit test vectors.

rawabstract:
A new method to implement faster than quadratic convergence for Goldschmidt division using simple logic circuits is presented. While the approximate quotient converges quadratically in conventional Goldschmidt division, the new method achieves nearly cubic convergence. Although division with cubic convergence has been regarded as impractical due to its complexity, the proposed method reduces the logic complexity and the delay by using an approximate squarer with a simple logic implementation and a redundant binary Booth recoder. It is especially effective in a system that already has a radix-8 multiplier. As a result, the effective area for the reciprocal table can be reduced by 25.4\%. The proposed method has been verified by SystemC and Verilog models. The final results are confirmed by simulation with both random double precision numbers and an exhaustive suite of 17-bit test vectors.

entry:
@Article{Kong:2011:GDM,
  author =       "Inwook Kong and Earl E. Swartzlander",
  title =        "A {Goldschmidt} Division Method With Faster Than
                 Quadratic Convergence",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "19",
  number =       "4",
  pages =        "696--700",
  month =        apr,
  year =         "2011",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/tvlsi.2009.2036926",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Mon Dec 11 08:01:22 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A new method to implement faster than quadratic
                 convergence for Goldschmidt division using simple logic
                 circuits is presented. While the approximate quotient
                 converges quadratically in conventional Goldschmidt
                 division, the new method achieves nearly cubic
                 convergence. Although division with cubic convergence
                 has been regarded as impractical due to its complexity,
                 the proposed method reduces the logic complexity and
                 the delay by using an approximate squarer with a simple
                 logic implementation and a redundant binary Booth
                 recoder. It is especially effective in a system that
                 already has a radix-8 multiplier. As a result, the
                 effective area for the reciprocal table can be reduced
                 by 25.4\%. The proposed method has been verified by
                 SystemC and Verilog models. The final results are
                 confirmed by simulation with both random double
                 precision numbers and an exhaustive suite of 17-bit
                 test vectors.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}


bibtype: article
filename: fparith.bib
label: Kornerup:2011:PAO
author: Peter Kornerup and Jean-Michel Muller and Adrien Panhaleux
title: Performing Arithmetic Operations on Round-to-Nearest Representations
journal: j-IEEE-TRANS-COMPUT
volume: 60
number: 2
pages: 282--291
month: feb
monthnumber: 2
year: 2011
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2010.134
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sun Feb 20 19:15:33 2011
bibtimestamp: 2011.02.20 19:15:33 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Peter Kornerup and Jean-Michel Muller and Adrien Panhaleux
rawtitle: Performing Arithmetic Operations on Round-to-Nearest Representations
abstract:
During any composite computation, there is a constant need for rounding intermediate results before they can participate in further processing. Recently, a class of number representations denoted RN-Codings were introduced, allowing an unbiased rounding-to-nearest to take place by a simple truncation, with the property that problems with double-roundings are avoided. In this paper, we first investigate a particular encoding of the binary representation. This encoding is generalized to any radix and digit set; however, radix complement representations for even values of the radix turn out to be particularly feasible. The encoding is essentially an ordinary radix complement representation with an appended round-bit, but still allowing rounding-to-nearest by truncation, and thus avoiding problems with double-roundings. Conversions from radix complement to these round-to-nearest representations can be performed in constant time, whereas conversion the other way, in general, takes at least logarithmic time. Not only is rounding-to-nearest a constant time operation, but so is also sign inversion, both of which are at best log-time operations on ordinary two's complement representations. Addition and multiplication on such fixed-point representations are first analyzed and defined in such a way that rounding information can be carried along in a meaningful way, at minimal cost. The analysis is carried through for a compact (canonical) encoding using two's complement representation, supplied with a round-bit. Based on the fixed-point encoding, it is shown possible to define floating-point representations, and a sketch of the implementation of an FPU is presented.

rawabstract:
During any composite computation, there is a constant need for rounding intermediate results before they can participate in further processing. Recently, a class of number representations denoted RN-Codings were introduced, allowing an unbiased rounding-to-nearest to take place by a simple truncation, with the property that problems with double-roundings are avoided. In this paper, we first investigate a particular encoding of the binary representation. This encoding is generalized to any radix and digit set; however, radix complement representations for even values of the radix turn out to be particularly feasible. The encoding is essentially an ordinary radix complement representation with an appended round-bit, but still allowing rounding-to-nearest by truncation, and thus avoiding problems with double-roundings. Conversions from radix complement to these round-to-nearest representations can be performed in constant time, whereas conversion the other way, in general, takes at least logarithmic time. Not only is rounding-to-nearest a constant time operation, but so is also sign inversion, both of which are at best log-time operations on ordinary two's complement representations. Addition and multiplication on such fixed-point representations are first analyzed and defined in such a way that rounding information can be carried along in a meaningful way, at minimal cost. The analysis is carried through for a compact (canonical) encoding using two's complement representation, supplied with a round-bit. Based on the fixed-point encoding, it is shown possible to define floating-point representations, and a sketch of the implementation of an FPU is presented.

entry:
@Article{Kornerup:2011:PAO,
  author =       "Peter Kornerup and Jean-Michel Muller and Adrien
                 Panhaleux",
  title =        "Performing Arithmetic Operations on Round-to-Nearest
                 Representations",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "60",
  number =       "2",
  pages =        "282--291",
  month =        feb,
  year =         "2011",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2010.134",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sun Feb 20 19:15:33 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  abstract =     "During any composite computation, there is a constant
                 need for rounding intermediate results before they can
                 participate in further processing. Recently, a class of
                 number representations denoted RN-Codings were
                 introduced, allowing an unbiased rounding-to-nearest to
                 take place by a simple truncation, with the property
                 that problems with double-roundings are avoided. In
                 this paper, we first investigate a particular encoding
                 of the binary representation. This encoding is
                 generalized to any radix and digit set; however, radix
                 complement representations for even values of the radix
                 turn out to be particularly feasible. The encoding is
                 essentially an ordinary radix complement representation
                 with an appended round-bit, but still allowing
                 rounding-to-nearest by truncation, and thus avoiding
                 problems with double-roundings. Conversions from radix
                 complement to these round-to-nearest representations
                 can be performed in constant time, whereas conversion
                 the other way, in general, takes at least logarithmic
                 time. Not only is rounding-to-nearest a constant time
                 operation, but so is also sign inversion, both of which
                 are at best log-time operations on ordinary two's
                 complement representations. Addition and multiplication
                 on such fixed-point representations are first analyzed
                 and defined in such a way that rounding information can
                 be carried along in a meaningful way, at minimal cost.
                 The analysis is carried through for a compact
                 (canonical) encoding using two's complement
                 representation, supplied with a round-bit. Based on the
                 fixed-point encoding, it is shown possible to define
                 floating-point representations, and a sketch of the
                 implementation of an FPU is presented.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Kulisch:2011:EDP
author: Ulrich Kulisch and Van Snyder
title: The exact dot product as basic tool for long interval arithmetic
journal: j-COMPUTING
volume: 91
number: 3
pages: 307--313
month: mar
monthnumber: 3
year: 2011
CODEN: CMPTA2
DOI: https://doi.org/10.1007/s00607-010-0127-7
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
bibdate: Tue Sep 6 19:14:24 MDT 2011
bibtimestamp: 2011.09.06 19:14:24 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=91&issue=3&spage=307
fjournal: Computing
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/607
rawauthor: Ulrich Kulisch and Van Snyder
rawtitle: The exact dot product as basic tool for long interval arithmetic
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=91&issue=3; https://www.math.utah.edu/pub/tex/bib/computing.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
Computing with guarantees is based on two arithmetical features. One is fixed (double) precision interval arithmetic. The other one is dynamic precision interval arithmetic, here also called long interval arithmetic. The basic tool to achieve high speed dynamic precision arithmetic for real and interval data is an exact multiply and accumulate operation and with it an exact dot product. Pipelining allows to compute it at the same high speed as vector operations on conventional vector processors. Long interval arithmetic fully benefits from such high speed. Exactitude brings very high accuracy, and thereby stability into computation. This document, which has been incorporated into the draft standard for interval arithmetic being developed by IEEE P1788, specifies the implementation of an exact multiply and accumulate operation.

keywords:
arithmetic standard; computer arithmetic; exact dot product; floating-point arithmetic; scientific computing

remark:
This document is an identical copy of a motion accepted by the international standards committee IEEE P1788 on interval arithmetic. Its contents will be published in a few years when the development of the standard is completed. The new floating-point arithmetic standard IEEE 754 (available since 2008) provides a function for accumulation of the dot product of two vectors with no accuracy requirement. Manufacturers who support the dot product by hardware should be aware that IEEE P1788 requires the exact result. Once a weak solution has been put into hardware it may be difficult to change it later. It is therefore important to bring this decision to public attention as soon as possible. Actually the simplest and fastest way for computing a dot product is to compute it exactly [4].

rawabstract:
Computing with guarantees is based on two arithmetical features. One is fixed (double) precision interval arithmetic. The other one is dynamic precision interval arithmetic, here also called long interval arithmetic. The basic tool to achieve high speed dynamic precision arithmetic for real and interval data is an exact multiply and accumulate operation and with it an exact dot product. Pipelining allows to compute it at the same high speed as vector operations on conventional vector processors. Long interval arithmetic fully benefits from such high speed. Exactitude brings very high accuracy, and thereby stability into computation. This document, which has been incorporated into the draft standard for interval arithmetic being developed by IEEE P1788, specifies the implementation of an exact multiply and accumulate operation.

entry:
@Article{Kulisch:2011:EDP,
  author =       "Ulrich Kulisch and Van Snyder",
  title =        "The exact dot product as basic tool for long interval
                 arithmetic",
  journal =      j-COMPUTING,
  volume =       "91",
  number =       "3",
  pages =        "307--313",
  month =        mar,
  year =         "2011",
  CODEN =        "CMPTA2",
  DOI =          "https://doi.org/10.1007/s00607-010-0127-7",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  bibdate =      "Tue Sep 6 19:14:24 MDT 2011",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=91&issue=3;
                 https://www.math.utah.edu/pub/tex/bib/computing.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=91&issue=3&spage=307",
  abstract =     "Computing with guarantees is based on two arithmetical
                 features. One is fixed (double) precision interval
                 arithmetic. The other one is dynamic precision interval
                 arithmetic, here also called long interval arithmetic.
                 The basic tool to achieve high speed dynamic precision
                 arithmetic for real and interval data is an exact
                 multiply and accumulate operation and with it an exact
                 dot product. Pipelining allows to compute it at the
                 same high speed as vector operations on conventional
                 vector processors. Long interval arithmetic fully
                 benefits from such high speed. Exactitude brings very
                 high accuracy, and thereby stability into computation.
                 This document, which has been incorporated into the
                 draft standard for interval arithmetic being developed
                 by IEEE P1788, specifies the implementation of an exact
                 multiply and accumulate operation.",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing",
  journal-URL =  "http://link.springer.com/journal/607",
  keywords =     "arithmetic standard; computer arithmetic; exact dot
                 product; floating-point arithmetic; scientific
                 computing",
  remark =       "This document is an identical copy of a motion
                 accepted by the international standards committee IEEE
                 P1788 on interval arithmetic. Its contents will be
                 published in a few years when the development of the
                 standard is completed. The new floating-point
                 arithmetic standard IEEE 754 (available since 2008)
                 provides a function for accumulation of the dot product
                 of two vectors with no accuracy requirement.
                 Manufacturers who support the dot product by hardware
                 should be aware that IEEE P1788 requires the exact
                 result. Once a weak solution has been put into hardware
                 it may be difficult to change it later. It is therefore
                 important to bring this decision to public attention as
                 soon as possible. Actually the simplest and fastest way
                 for computing a dot product is to compute it exactly
                 [4].",
}


bibtype: article
filename: fparith.bib
label: Kulisch:2011:VFE
author: Ulrich Kulisch
title: Very fast and exact accumulation of products
journal: j-COMPUTING
volume: 91
number: 4
pages: 397--405
month: apr
monthnumber: 4
year: 2011
CODEN: CMPTA2
DOI: https://doi.org/10.1007/s00607-010-0131-y
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
bibdate: Tue Sep 6 19:14:31 MDT 2011
bibtimestamp: 2011.09.06 19:14:31 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=91&issue=4&spage=397
fjournal: Computing: Archiv fur informatik und numerik
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/607
rawauthor: Ulrich Kulisch
rawtitle: Very fast and exact accumulation of products
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=91&issue=4; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
The IFIP Working Group on Numerical Software and other scientists repeatedly requested that a future arithmetic standard should consider and specify an exact dot product (EDP) [The IFIP WG IEEE 754R letter, dated September 4 (2007), The IFIP WG IEEE P1788 letter, dated September 9 (2009)]. On 18 November 2009 the IEEE standards committee P1788 on interval arithmetic accepted a motion [Kulisch and Snyder (The exact dot product as basic tool for long interval arithmetic, passed on Nov 18, 2009 as official IEEE P1788 document)] for including the EDP into a future interval arithmetic standard. Actually the simplest and fastest way for computing a dot product is to compute it exactly. By pipelining, it can be computed in the time the processor needs to read the data, i.e., it comes with utmost speed. A hardware implementation of the EDP exceeds any approximate computation of the dot product in software by several orders of magnitude. By a sample illustration the paper informally specifies the implementation of the EDP on computers. While [Kulisch and Snyder (The exact dot product as basic tool for long interval arithmetic, passed on Nov 18, 2009 as official IEEE P1788 document)] defines what has to be provided, how to embed the EDP into the new standard IEEE 754, [IEEE Floating-Point Arithmetic Standard 754 (2008)] and how exceptions like NaN are to be dealt with, this article illustrates how the EDP can be implemented on computers. There is indeed no simpler way of accumulating a dot product. Any method that just computes an approximation also has to consider the relative values of the summands. This results in a more complicated method. The hardware needed for the EDP is comparable to that for a fast multiplier by an adder tree, accepted years ago and now standard technology in every modern processor. The EDP brings the same speedup for accumulations at comparable costs. In Numerical Analysis the dot product is ubiquitous. It is not merely a fundamental operation in all vector and matrix spaces. It is the EDP which makes residual correction effective. This has a direct and positive influence on all iterative solvers of systems of equations. The EDP is essential for fast long real and long interval arithmetic, as well as for assessing and managing uncertainty in computing. By operator overloading variable precision interval arithmetic is very easy to use. With it the result of every arithmetic expression can be guaranteed to a number of correct digits.

keywords:
arithmetic standards; computer arithmetic; exact dot product; floating-point arithmetic; scientific computing

rawabstract:
The IFIP Working Group on Numerical Software and other scientists repeatedly requested that a future arithmetic standard should consider and specify an exact dot product (EDP) [The IFIP WG IEEE 754R letter, dated September 4 (2007), The IFIP WG IEEE P1788 letter, dated September 9 (2009)]. On 18 November 2009 the IEEE standards committee P1788 on interval arithmetic accepted a motion [Kulisch and Snyder (The exact dot product as basic tool for long interval arithmetic, passed on Nov 18, 2009 as official IEEE P1788 document)] for including the EDP into a future interval arithmetic standard. Actually the simplest and fastest way for computing a dot product is to compute it exactly. By pipelining, it can be computed in the time the processor needs to read the data, i.e., it comes with utmost speed. A hardware implementation of the EDP exceeds any approximate computation of the dot product in software by several orders of magnitude. By a sample illustration the paper informally specifies the implementation of the EDP on computers. While [Kulisch and Snyder (The exact dot product as basic tool for long interval arithmetic, passed on Nov 18, 2009 as official IEEE P1788 document)] defines what has to be provided, how to embed the EDP into the new standard IEEE 754, [IEEE Floating-Point Arithmetic Standard 754 (2008)] and how exceptions like NaN are to be dealt with, this article illustrates how the EDP can be implemented on computers. There is indeed no simpler way of accumulating a dot product. Any method that just computes an approximation also has to consider the relative values of the summands. This results in a more complicated method. The hardware needed for the EDP is comparable to that for a fast multiplier by an adder tree, accepted years ago and now standard technology in every modern processor. The EDP brings the same speedup for accumulations at comparable costs. In Numerical Analysis the dot product is ubiquitous. It is not merely a fundamental operation in all vector and matrix spaces. It is the EDP which makes residual correction effective. This has a direct and positive influence on all iterative solvers of systems of equations. The EDP is essential for fast long real and long interval arithmetic, as well as for assessing and managing uncertainty in computing. By operator overloading variable precision interval arithmetic is very easy to use. With it the result of every arithmetic expression can be guaranteed to a number of correct digits.

entry:
@Article{Kulisch:2011:VFE,
  author =       "Ulrich Kulisch",
  title =        "Very fast and exact accumulation of products",
  journal =      j-COMPUTING,
  volume =       "91",
  number =       "4",
  pages =        "397--405",
  month =        apr,
  year =         "2011",
  CODEN =        "CMPTA2",
  DOI =          "https://doi.org/10.1007/s00607-010-0131-y",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  bibdate =      "Tue Sep 6 19:14:31 MDT 2011",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=91&issue=4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=91&issue=4&spage=397",
  abstract =     "The IFIP Working Group on Numerical Software and other
                 scientists repeatedly requested that a future
                 arithmetic standard should consider and specify an
                 exact dot product (EDP) [The IFIP WG IEEE 754R letter,
                 dated September 4 (2007), The IFIP WG IEEE P1788
                 letter, dated September 9 (2009)]. On 18 November 2009
                 the IEEE standards committee P1788 on interval
                 arithmetic accepted a motion [Kulisch and Snyder (The
                 exact dot product as basic tool for long interval
                 arithmetic, passed on Nov 18, 2009 as official IEEE
                 P1788 document)] for including the EDP into a future
                 interval arithmetic standard. Actually the simplest and
                 fastest way for computing a dot product is to compute
                 it exactly. By pipelining, it can be computed in the
                 time the processor needs to read the data, i.e., it
                 comes with utmost speed. A hardware implementation of
                 the EDP exceeds any approximate computation of the dot
                 product in software by several orders of magnitude. By
                 a sample illustration the paper informally specifies
                 the implementation of the EDP on computers. While
                 [Kulisch and Snyder (The exact dot product as basic
                 tool for long interval arithmetic, passed on Nov 18,
                 2009 as official IEEE P1788 document)] defines what has
                 to be provided, how to embed the EDP into the new
                 standard IEEE 754, [IEEE Floating-Point Arithmetic
                 Standard 754 (2008)] and how exceptions like NaN are to
                 be dealt with, this article illustrates how the EDP can
                 be implemented on computers. There is indeed no simpler
                 way of accumulating a dot product. Any method that just
                 computes an approximation also has to consider the
                 relative values of the summands. This results in a more
                 complicated method. The hardware needed for the EDP is
                 comparable to that for a fast multiplier by an adder
                 tree, accepted years ago and now standard technology in
                 every modern processor. The EDP brings the same speedup
                 for accumulations at comparable costs. In Numerical
                 Analysis the dot product is ubiquitous. It is not
                 merely a fundamental operation in all vector and matrix
                 spaces. It is the EDP which makes residual correction
                 effective. This has a direct and positive influence on
                 all iterative solvers of systems of equations. The EDP
                 is essential for fast long real and long interval
                 arithmetic, as well as for assessing and managing
                 uncertainty in computing. By operator overloading
                 variable precision interval arithmetic is very easy to
                 use. With it the result of every arithmetic expression
                 can be guaranteed to a number of correct digits.",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing: Archiv f{\"u}r informatik und numerik",
  journal-URL =  "http://link.springer.com/journal/607",
  keywords =     "arithmetic standards; computer arithmetic; exact dot
                 product; floating-point arithmetic; scientific
                 computing",
}


bibtype: article
filename: fparith.bib
label: Lamberti:2011:RCT
author: Fabrizio Lamberti and Nikos Andrikos and Elisardo Antelo and Paolo Montuschi
title: Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 60
number: 2
pages: 148--156
month: feb
monthnumber: 2
year: 2011
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2010.156
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sun Feb 20 19:15:33 2011
bibtimestamp: 2011.02.20 19:15:33 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Fabrizio Lamberti and Nikos Andrikos and Elisardo Antelo and Paolo Montuschi
rawtitle: Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers
entry:
@Article{Lamberti:2011:RCT,
  author =       "Fabrizio Lamberti and Nikos Andrikos and Elisardo
                 Antelo and Paolo Montuschi",
  title =        "Reducing the Computation Time in (Short Bit-Width)
                 Two's Complement Multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "60",
  number =       "2",
  pages =        "148--156",
  month =        feb,
  year =         "2011",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2010.156",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sun Feb 20 19:15:33 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Langhammer:2011:TFD
author: Martin Langhammer
title: Teraflop FPGA Design
crossref: Schwarz:2011:PIS
pages: 187--188
year: 2011
DOI: https://doi.org/10.1109/ARITH.2011.32
bibdate: Sat Aug 20 09:00:00 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.08.20 09:00:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992124
keywords: ARITH-20
acknowledgement: ack-nhfb
rawauthor: Martin Langhammer
rawtitle: Teraflop {FPGA} Design
entry:
@InProceedings{Langhammer:2011:TFD,
  author =       "Martin Langhammer",
  title =        "Teraflop {FPGA} Design",
  crossref =     "Schwarz:2011:PIS",
  pages =        "187--188",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ARITH.2011.32",
  bibdate =      "Sat Aug 20 09:00:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992124",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-20",
}


bibtype: techreport
filename: fparith.bib
label: Lefevre:2011:SSI
author: Vincent Lefevre
title: SIPE: Small Integer Plus Exponent
institution: INRIA
address: Lyon, France
pages: 25
year: 2011
bibdate: Tue Dec 26 14:57:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.26 14:57:40 ???
URL: http://hal.inria.fr/hal-00650659
acknowledgement: ack-nhfb
rawauthor: Vincent Lef{\`e}vre
rawtitle: {SIPE}: Small Integer Plus Exponent
entry:
@TechReport{Lefevre:2011:SSI,
  author =       "Vincent Lef{\`e}vre",
  title =        "{SIPE}: Small Integer Plus Exponent",
  institution =  "INRIA",
  address =      "Lyon, France",
  pages =        "25",
  year =         "2011",
  bibdate =      "Tue Dec 26 14:57:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://hal.inria.fr/hal-00650659",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lipetz:2011:SCC
author: Daniel Lipetz and Eric Schwarz
title: Self Checking in Current Floating-Point Units
crossref: Schwarz:2011:PIS
pages: 73--76
year: 2011
DOI: https://doi.org/10.1109/ARITH.2011.18
bibdate: Sat Aug 20 09:00:00 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.08.20 09:00:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992110
keywords: ARITH-20
acknowledgement: ack-nhfb
rawauthor: Daniel Lipetz and Eric Schwarz
rawtitle: Self Checking in Current Floating-Point Units
entry:
@InProceedings{Lipetz:2011:SCC,
  author =       "Daniel Lipetz and Eric Schwarz",
  title =        "Self Checking in Current Floating-Point Units",
  crossref =     "Schwarz:2011:PIS",
  pages =        "73--76",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ARITH.2011.18",
  bibdate =      "Sat Aug 20 09:00:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992110",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-20",
}


bibtype: article
filename: fparith.bib
label: Liu:2011:FAH
author: Feng Liu and Xiaoyu Song and Qingping Tan and Gang Chen
title: Formal Analysis of Hybrid Prefix / Carry-Select Arithmetic Systems
journal: j-COMP-J
volume: 54
number: 6
pages: 894--904
month: jun
monthnumber: 6
year: 2011
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/bxq048
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Wed Jun 1 18:54:12 MDT 2011
bibsource: content/54/6.toc; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.06.01 18:54:12 MDT
URL: http://comjnl.oxfordjournals.org/content/54/6/894.full.pdf+html
fjournal: The Computer Journal
keywords: carry-select adders; computer arithmetic; formal methods; parallel prefix adders
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
onlinedate: May 25, 2010
rawauthor: Feng Liu and Xiaoyu Song and Qingping Tan and Gang Chen
rawtitle: Formal Analysis of Hybrid Prefix\slash Carry-Select Arithmetic Systems
abstract:
Arithmetic circuits play an important role in high-performance digital systems. The paper considers a generic architecture of hybrid prefix / carry-select arithmetic systems. A novel proof methodology is proposed to model and verify hybrid addition systems. Algebraic structures and first-order recursive equations are harnessed in proof derivations. Case studies on several typical classes of hybrid prefix / carry-select adders and special cases with pseudo-carries such as Ling's carry demonstrate the effectiveness of the proposed approach.

rawabstract:
Arithmetic circuits play an important role in high-performance digital systems. The paper considers a generic architecture of hybrid prefix\slash carry-select arithmetic systems. A novel proof methodology is proposed to model and verify hybrid addition systems. Algebraic structures and first-order recursive equations are harnessed in proof derivations. Case studies on several typical classes of hybrid prefix\slash carry-select adders and special cases with pseudo-carries such as Ling's carry demonstrate the effectiveness of the proposed approach.

entry:
@Article{Liu:2011:FAH,
  author =       "Feng Liu and Xiaoyu Song and Qingping Tan and Gang
                 Chen",
  title =        "Formal Analysis of Hybrid Prefix\slash Carry-Select
                 Arithmetic Systems",
  journal =      j-COMP-J,
  volume =       "54",
  number =       "6",
  pages =        "894--904",
  month =        jun,
  year =         "2011",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/bxq048",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Wed Jun 1 18:54:12 MDT 2011",
  bibsource =    "content/54/6.toc;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://comjnl.oxfordjournals.org/content/54/6/894.full.pdf+html",
  abstract =     "Arithmetic circuits play an important role in
                 high-performance digital systems. The paper considers a
                 generic architecture of hybrid prefix\slash
                 carry-select arithmetic systems. A novel proof
                 methodology is proposed to model and verify hybrid
                 addition systems. Algebraic structures and first-order
                 recursive equations are harnessed in proof derivations.
                 Case studies on several typical classes of hybrid
                 prefix\slash carry-select adders and special cases with
                 pseudo-carries such as Ling's carry demonstrate the
                 effectiveness of the proposed approach.",
  acknowledgement = ack-nhfb,
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "carry-select adders; computer arithmetic; formal
                 methods; parallel prefix adders",
  onlinedate =   "May 25, 2010",
}


bibtype: inproceedings
filename: fparith.bib
label: Liu:2011:ILC
author: Yuanlong Liu and Bateer and Wen Zhong
booktitle: 2011 International Conference on Computer Science and Service System (CSSS)
title: Implementation of a low complexity divider for ILUT-based FPGAs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 464--466
year: 2011
DOI: https://doi.org/10.1109/CSSS.2011.5974453
bibdate: Tue Sep 27 08:11:09 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:09 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5974453
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5959270
rawauthor: Yuanlong Liu and Bateer and Wen Zhong
rawbooktitle: {2011 International Conference on Computer Science and Service System (CSSS)}
rawtitle: Implementation of a low complexity divider for {ILUT}-based {FPGAs}
entry:
@InProceedings{Liu:2011:ILC,
  author =       "Yuanlong Liu and Bateer and Wen Zhong",
  booktitle =    "{2011 International Conference on Computer Science and
                 Service System (CSSS)}",
  title =        "Implementation of a low complexity divider for
                 {ILUT}-based {FPGAs}",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "464--466",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/CSSS.2011.5974453",
  bibdate =      "Tue Sep 27 08:11:09 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5974453",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5959270",
}


bibtype: inproceedings
filename: fparith.bib
label: Lutz:2011:FMA
author: David R. Lutz
crossref: Schwarz:2011:PIS
pages: 123--128
year: 2011
DOI: https://doi.org/10.1109/ARITH.2011.25
bibdate: Sat Aug 20 09:00:00 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.08.20 09:00:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992117
keywords: ARITH-20
acknowledgement: ack-nhfb
rawauthor: David R. Lutz
title:
Fused Multiply-Add Microarchitecture Comprising Separate Early-Normalizing Multiply and Add Pipelines

rawtitle:
Fused Multiply-Add Microarchitecture Comprising Separate Early-Normalizing Multiply and Add Pipelines

entry:
@InProceedings{Lutz:2011:FMA,
  author =       "David R. Lutz",
  title =        "Fused Multiply-Add Microarchitecture Comprising
                 Separate Early-Normalizing Multiply and Add Pipelines",
  crossref =     "Schwarz:2011:PIS",
  pages =        "123--128",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ARITH.2011.25",
  bibdate =      "Sat Aug 20 09:00:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992117",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-20",
}


bibtype: inproceedings
filename: fparith.bib
label: Malone:2011:FBI
author: A. N. Malone and G. R. Morris and K. H. Abed
booktitle: Southeastcon, 2011 Proceedings of IEEE
title: FPGA-based implementation of Horner's rule on a high performance heterogeneous computer
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 277--282
year: 2011
DOI: https://doi.org/10.1109/SECON.2011.5752949
bibdate: Tue Sep 27 08:11:09 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:09 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5752949
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5746658
rawauthor: A. N. Malone and G. R. Morris and K. H. Abed
rawbooktitle: {Southeastcon, 2011 Proceedings of IEEE}
rawtitle: {FPGA}-based implementation of {Horner}'s rule on a high performance heterogeneous computer
entry:
@InProceedings{Malone:2011:FBI,
  author =       "A. N. Malone and G. R. Morris and K. H. Abed",
  booktitle =    "{Southeastcon, 2011 Proceedings of IEEE}",
  title =        "{FPGA}-based implementation of {Horner}'s rule on a
                 high performance heterogeneous computer",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "277--282",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/SECON.2011.5752949",
  bibdate =      "Tue Sep 27 08:11:09 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5752949",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5746658",
}


bibtype: article
filename: fparith.bib
label: Masakova:2011:ANS
author: Z. Masakova and E. Pelantova and T. Vavra
title: Arithmetics in number systems with a negative base
journal: j-THEOR-COMP-SCI
volume: 412
number: 8--10
pages: 835--845
day: 4
month: mar
monthnumber: 3
year: 2011
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Wed Aug 31 10:15:30 MDT 2011
bibtimestamp: 2011.08.31 10:15:30 MDT
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: Z. Mas{\'a}kov{\'a} and E. Pelantov{\'a} and T. V{\'a}vra
rawtitle: Arithmetics in number systems with a negative base
entry:
@Article{Masakova:2011:ANS,
  author =       "Z. Mas{\'a}kov{\'a} and E. Pelantov{\'a} and T.
                 V{\'a}vra",
  title =        "Arithmetics in number systems with a negative base",
  journal =      j-THEOR-COMP-SCI,
  volume =       "412",
  number =       "8--10",
  pages =        "835--845",
  day =          "4",
  month =        mar,
  year =         "2011",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Wed Aug 31 10:15:30 MDT 2011",
  bibsource =    "http://www.sciencedirect.com/science/journal/03043975;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
}


bibtype: inproceedings
filename: fparith.bib
label: Matula:2011:PLP
author: David W. Matula and Mihai T. Panu
crossref: Schwarz:2011:PIS
pages: 177--183
year: 2011
DOI: https://doi.org/10.1109/ARITH.2011.31
bibdate: Sat Aug 20 09:00:00 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.08.20 09:00:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992123
keywords: ARITH-20
acknowledgement: ack-nhfb
rawauthor: David W. Matula and Mihai T. Panu
title:
A Prescale-Lookup-Postscale Additive Procedure for Obtaining a Single Precision Ulp Accurate Reciprocal

rawtitle:
A Prescale-Lookup-Postscale Additive Procedure for Obtaining a Single Precision Ulp Accurate Reciprocal

entry:
@InProceedings{Matula:2011:PLP,
  author =       "David W. Matula and Mihai T. Panu",
  title =        "A Prescale-Lookup-Postscale Additive Procedure for
                 Obtaining a Single Precision Ulp Accurate Reciprocal",
  crossref =     "Schwarz:2011:PIS",
  pages =        "177--183",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ARITH.2011.31",
  bibdate =      "Sat Aug 20 09:00:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992123",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-20",
}


bibtype: inproceedings
filename: fparith.bib
label: Mauer:2011:FPS
author: V. Mauer and M. Parker
booktitle: Radar Conference (RADAR), 2011 IEEE
title: Floating point STAP implementation on FPGAs
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 901--904
year: 2011
DOI: https://doi.org/10.1109/RADAR.2011.5960667
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5960667
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5941184
rawauthor: V. Mauer and M. Parker
rawbooktitle: {Radar Conference (RADAR), 2011 IEEE}
rawtitle: Floating point {STAP} implementation on {FPGAs}
entry:
@InProceedings{Mauer:2011:FPS,
  author =       "V. Mauer and M. Parker",
  booktitle =    "{Radar Conference (RADAR), 2011 IEEE}",
  title =        "Floating point {STAP} implementation on {FPGAs}",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "901--904",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/RADAR.2011.5960667",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5960667",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5941184",
}


bibtype: inproceedings
filename: fparith.bib
label: Minchola:2011:FID
author: C. Minchola and M. Vazquez and G. Sutter
booktitle: 2011 VII Southern Conference on Programmable Logic (SPL)
title: A FPGA IEEE-754-2008 decimal64 floating-point adder / subtractor
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 251--256
year: 2011
DOI: https://doi.org/10.1109/SPL.2011.5782657
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5782657
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5771182
rawauthor: C. Minchola and M. Vazquez and G. Sutter
rawbooktitle: {2011 VII Southern Conference on Programmable Logic (SPL)}
rawtitle: A {FPGA} {IEEE-754-2008} decimal64 floating-point adder\slash subtractor
entry:
@InProceedings{Minchola:2011:FID,
  author =       "C. Minchola and M. Vazquez and G. Sutter",
  booktitle =    "{2011 VII Southern Conference on Programmable Logic
                 (SPL)}",
  title =        "A {FPGA} {IEEE-754-2008} decimal64 floating-point
                 adder\slash subtractor",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "251--256",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/SPL.2011.5782657",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5782657",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5771182",
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Moller:2011:IDI
author: Niels Moller and Torbjorn Granlund
title: Improved Division by Invariant Integers
journal: j-IEEE-TRANS-COMPUT
volume: 60
number: 2
pages: 165--175
month: feb
monthnumber: 2
year: 2011
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2010.143
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sun Feb 20 19:15:33 2011
bibtimestamp: 2011.02.20 19:15:33 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Niels M{\"o}ller and Torbj{\"o}rn Granlund
rawtitle: Improved Division by Invariant Integers
abstract:
This paper considers the problem of dividing a two-word integer by a single-word integer, together with a few extensions and applications. Due to lack of efficient division instructions in current processors, the division is performed as a multiplication using a precomputed single-word approximation of the reciprocal of the divisor, followed by a couple of adjustment steps. There are three common types of unsigned multiplication instructions: we define full word multiplication (umul), which produces the two-word product of two single-word integers; low multiplication (umullo), which produces only the least significant word of the product; and high multiplication (umulhi), which produces only the most significant word. We describe an algorithm that produces a quotient and remainder using one umul and one umullo. This is an improvement over earlier methods, since the new method uses cheaper multiplication operations. It turns out that we also get some additional savings from simpler adjustment conditions. The algorithm has been implemented in version 4.3 of the gmp library. When applied to the problem of dividing a large integer by a single word, the new algorithm gives a speedup of roughly 30 percent, benchmarked on AMD and Intel processors in the x86_64 family.

rawabstract:
This paper considers the problem of dividing a two-word integer by a single-word integer, together with a few extensions and applications. Due to lack of efficient division instructions in current processors, the division is performed as a multiplication using a precomputed single-word approximation of the reciprocal of the divisor, followed by a couple of adjustment steps. There are three common types of unsigned multiplication instructions: we define full word multiplication (umul), which produces the two-word product of two single-word integers; low multiplication (umullo), which produces only the least significant word of the product; and high multiplication (umulhi), which produces only the most significant word. We describe an algorithm that produces a quotient and remainder using one umul and one umullo. This is an improvement over earlier methods, since the new method uses cheaper multiplication operations. It turns out that we also get some additional savings from simpler adjustment conditions. The algorithm has been implemented in version 4.3 of the gmp library. When applied to the problem of dividing a large integer by a single word, the new algorithm gives a speedup of roughly 30 percent, benchmarked on AMD and Intel processors in the x86\_64 family.

entry:
@Article{Moller:2011:IDI,
  author =       "Niels M{\"o}ller and Torbj{\"o}rn Granlund",
  title =        "Improved Division by Invariant Integers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "60",
  number =       "2",
  pages =        "165--175",
  month =        feb,
  year =         "2011",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2010.143",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sun Feb 20 19:15:33 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  abstract =     "This paper considers the problem of dividing a
                 two-word integer by a single-word integer, together
                 with a few extensions and applications. Due to lack of
                 efficient division instructions in current processors,
                 the division is performed as a multiplication using a
                 precomputed single-word approximation of the reciprocal
                 of the divisor, followed by a couple of adjustment
                 steps. There are three common types of unsigned
                 multiplication instructions: we define full word
                 multiplication (umul), which produces the two-word
                 product of two single-word integers; low multiplication
                 (umullo), which produces only the least significant
                 word of the product; and high multiplication (umulhi),
                 which produces only the most significant word. We
                 describe an algorithm that produces a quotient and
                 remainder using one umul and one umullo. This is an
                 improvement over earlier methods, since the new method
                 uses cheaper multiplication operations. It turns out
                 that we also get some additional savings from simpler
                 adjustment conditions. The algorithm has been
                 implemented in version 4.3 of the gmp library. When
                 applied to the problem of dividing a large integer by a
                 single word, the new algorithm gives a speedup of
                 roughly 30 percent, benchmarked on AMD and Intel
                 processors in the x86\_64 family.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Mouilleron:2011:AGF
author: Christophe Mouilleron and Guillaume Revy
title: Automatic Generation of Fast and Certified Code for Polynomial Evaluation
crossref: Schwarz:2011:PIS
pages: 233--242
year: 2011
DOI: https://doi.org/10.1109/ARITH.2011.39
bibdate: Sat Aug 20 09:00:00 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.08.20 09:00:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992131
keywords: ARITH-20
acknowledgement: ack-nhfb
rawauthor: Christophe Mouilleron and Guillaume Revy
rawtitle: Automatic Generation of Fast and Certified Code for Polynomial Evaluation
entry:
@InProceedings{Mouilleron:2011:AGF,
  author =       "Christophe Mouilleron and Guillaume Revy",
  title =        "Automatic Generation of Fast and Certified Code for
                 Polynomial Evaluation",
  crossref =     "Schwarz:2011:PIS",
  pages =        "233--242",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ARITH.2011.39",
  bibdate =      "Sat Aug 20 09:00:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992131",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-20",
}


bibtype: inproceedings
filename: fparith.bib
label: Nannarelli:2011:RCD
author: Alberto Nannarelli
title: Radix-16 Combined Division and Square Root Unit
crossref: Schwarz:2011:PIS
pages: 169--176
year: 2011
DOI: https://doi.org/10.1109/ARITH.2011.30
bibdate: Sat Aug 20 09:00:00 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.08.20 09:00:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992122
keywords: ARITH-20; sqrt(x); square root
acknowledgement: ack-nhfb
rawauthor: Alberto Nannarelli
rawtitle: Radix-16 Combined Division and Square Root Unit
entry:
@InProceedings{Nannarelli:2011:RCD,
  author =       "Alberto Nannarelli",
  title =        "Radix-16 Combined Division and Square Root Unit",
  crossref =     "Schwarz:2011:PIS",
  pages =        "169--176",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ARITH.2011.30",
  bibdate =      "Sat Aug 20 09:00:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992122",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-20; sqrt(x); square root",
}


bibtype: incollection
filename: fparith.bib
label: Nguyen:2011:FSA
author: Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preuss er
editor: Peter Athanas and Dionisios Pnevmatikatos and Nicolas Sklavos
title: FPGA-specific arithmetic optimizations of short-latency adders
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 232--237
year: 2011
DOI: https://doi.org/10.1109/FPL.2011.49
ISBN: 0-7695-4529-7 OR 0769545297
ISBN13: 978-0-7695-4529-5 OR 9780769545295
LCCN: TK7895.G36
bibdate: Sat Feb 08 09:55:40 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 09:55:40 ???
URL: https://ieeexplore.ieee.org/document/6044770
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/servlet/opac?punumber=6044763
bookpages: xxviii + 560
rawauthor: Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preu{\ss}er
raweditor: Peter Athanas and Dionisios Pnevmatikatos and Nicolas Sklavos
rawtitle: {FPGA}-specific arithmetic optimizations of short-latency adders
booktitle:
21st International Conference on Field Programmable Logic and Applications: FPL 2011: proceedings: 5--7 September 2011, Chania, Greece

rawbooktitle:
{21st International Conference on Field Programmable Logic and Applications: FPL 2011: proceedings: 5--7 September 2011, Chania, Greece}

entry:
@InCollection{Nguyen:2011:FSA,
  author =       "Hong Diep Nguyen and Bogdan Pasca and Thomas B.
                 Preu{\ss}er",
  editor =       "Peter Athanas and Dionisios Pnevmatikatos and Nicolas
                 Sklavos",
  booktitle =    "{21st International Conference on Field Programmable
                 Logic and Applications: FPL 2011: proceedings: 5--7
                 September 2011, Chania, Greece}",
  title =        "{FPGA}-specific arithmetic optimizations of
                 short-latency adders",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  bookpages =    "xxviii + 560",
  pages =        "232--237",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/FPL.2011.49",
  ISBN =         "0-7695-4529-7",
  ISBN-13 =      "978-0-7695-4529-5",
  LCCN =         "TK7895.G36",
  bibdate =      "Sat Feb 08 09:55:40 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/document/6044770",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/servlet/opac?punumber=6044763",
}


bibtype: article
filename: fparith.bib
label: Ozaki:2011:TEE
author: Katsuhisa Ozaki and Takeshi Ogita and Shin'ichi Oishi
title: Tight and efficient enclosure of matrix multiplication by using optimized BLAS
journal: j-NUM-LIN-ALG-APPL
volume: 18
number: 2
pages: 237--248
month: mar
monthnumber: 3
year: 2011
CODEN: NLAAEM
DOI: https://doi.org/10.1002/nla.724
ISSN: 1070-5325 (print), 1099-1506 (electronic) OR 10705325 (print), 10991506 (electronic)
ISSNL: 1070-5325 OR 10705325
bibdate: Wed Mar 16 10:14:59 MDT 2011
bibtimestamp: 2011.03.16 10:14:59 MDT
fjournal: Numerical linear algebra with applications
keywords: interval arithmetic; matrix multiplication; verified numerical computation
acknowledgement: ack-nhfb
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1099-1506
onlinedate: 19 May 2010
rawauthor: Katsuhisa Ozaki and Takeshi Ogita and Shin'ichi Oishi
rawtitle: Tight and efficient enclosure of matrix multiplication by using optimized {BLAS}
bibsource:
http://www.interscience.wiley.com/jpages/1070-5325; http://www3.interscience.wiley.com/journalfinder.html; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
This paper is concerned with the tight enclosure of matrix multiplication $ A B $ for two floating-point matrices $A$ and $B$. The aim of this paper is to compute component-wise upper and lower bounds of the exact result $C$ of the matrix multiplication $ A B $ by floating-point arithmetic. Namely, an interval matrix enclosing $C$ is obtained. In this paper, new algorithms for enclosing $C$ are proposed. The proposed algorithms are designed to mainly exploit the level 3 operations in BLAS. Although the proposed algorithms take around twice as much costs as a standard algorithm promoted by Oishi and Rump, the accuracy of the result by the proposed algorithms is better than that of the standard algorithm. At the end of this paper, we present numerical examples showing the efficiency of the proposed algorithms

rawabstract:
This paper is concerned with the tight enclosure of matrix multiplication $ A B $ for two floating-point matrices $A$ and $B$. The aim of this paper is to compute component-wise upper and lower bounds of the exact result $C$ of the matrix multiplication $ A B $ by floating-point arithmetic. Namely, an interval matrix enclosing $C$ is obtained. In this paper, new algorithms for enclosing $C$ are proposed. The proposed algorithms are designed to mainly exploit the level 3 operations in BLAS. Although the proposed algorithms take around twice as much costs as a standard algorithm promoted by Oishi and Rump, the accuracy of the result by the proposed algorithms is better than that of the standard algorithm. At the end of this paper, we present numerical examples showing the efficiency of the proposed algorithms

entry:
@Article{Ozaki:2011:TEE,
  author =       "Katsuhisa Ozaki and Takeshi Ogita and Shin'ichi
                 Oishi",
  title =        "Tight and efficient enclosure of matrix multiplication
                 by using optimized {BLAS}",
  journal =      j-NUM-LIN-ALG-APPL,
  volume =       "18",
  number =       "2",
  pages =        "237--248",
  month =        mar,
  year =         "2011",
  CODEN =        "NLAAEM",
  DOI =          "https://doi.org/10.1002/nla.724",
  ISSN =         "1070-5325 (print), 1099-1506 (electronic)",
  ISSN-L =       "1070-5325",
  bibdate =      "Wed Mar 16 10:14:59 MDT 2011",
  bibsource =    "http://www.interscience.wiley.com/jpages/1070-5325;
                 http://www3.interscience.wiley.com/journalfinder.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper is concerned with the tight enclosure of
                 matrix multiplication $ A B $ for two floating-point
                 matrices $A$ and $B$. The aim of this paper is to
                 compute component-wise upper and lower bounds of the
                 exact result $C$ of the matrix multiplication $ A B $
                 by floating-point arithmetic. Namely, an interval
                 matrix enclosing $C$ is obtained. In this paper, new
                 algorithms for enclosing $C$ are proposed. The proposed
                 algorithms are designed to mainly exploit the level 3
                 operations in BLAS. Although the proposed algorithms
                 take around twice as much costs as a standard algorithm
                 promoted by Oishi and Rump, the accuracy of the result
                 by the proposed algorithms is better than that of the
                 standard algorithm. At the end of this paper, we
                 present numerical examples showing the efficiency of
                 the proposed algorithms",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerical linear algebra with applications",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1099-1506",
  keywords =     "interval arithmetic; matrix multiplication; verified
                 numerical computation",
  onlinedate =   "19 May 2010",
}


bibtype: inproceedings
filename: fparith.bib
label: Park:2011:LPS
author: Daejin Park and Tag Gon Kim and Changmin Kim and Sungho Kwak
crossref: IEEE:2011:ICC
pages: 1--3
year: 2011
CODEN: IRELAO
DOI: https://doi.org/10.1109/COOLCHIPS.2011.5890924
ISSN: 0367-9950 OR 03679950
bibdate: Wed Dec 21 14:34:51 MST 2011
bibtimestamp: 2011.12.21 14:34:51 MST
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5890924
acknowledgement: ack-nhfb
rawauthor: Daejin Park and Tag Gon Kim and Changmin Kim and Sungho Kwak
title:
A low-power sync processor with a floating-point timer and universal edge tracer for 3DTV active shutter glasses

bibsource:
https://www.math.utah.edu/pub/tex/bib/cool-chips.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
A low-power sync processor with a floating-point timer and universal edge tracer for {3DTV} active shutter glasses

entry:
@InProceedings{Park:2011:LPS,
  author =       "Daejin Park and Tag Gon Kim and Changmin Kim and
                 Sungho Kwak",
  title =        "A low-power sync processor with a floating-point timer
                 and universal edge tracer for {3DTV} active shutter
                 glasses",
  crossref =     "IEEE:2011:ICC",
  pages =        "1--3",
  year =         "2011",
  CODEN =        "IRELAO",
  DOI =          "https://doi.org/10.1109/COOLCHIPS.2011.5890924",
  ISSN =         "0367-9950",
  bibdate =      "Wed Dec 21 14:34:51 MST 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cool-chips.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5890924",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Peay:2011:IQW
author: N. S. Peay and G. R. Morris and K. H. Abed
booktitle: 2011 Proceedings of IEEE Southeastcon
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 413--417
year: 2011
DOI: https://doi.org/10.1109/SECON.2011.5752977
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5752977
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5746658
rawauthor: N. S. Peay and G. R. Morris and K. H. Abed
rawbooktitle: {2011 Proceedings of IEEE Southeastcon}
title:
Integrating Quartus Wizard-based VHDL floating-point components into a high performance heterogeneous computing environment

rawtitle:
Integrating {Quartus Wizard}-based {VHDL} floating-point components into a high performance heterogeneous computing environment

entry:
@InProceedings{Peay:2011:IQW,
  author =       "N. S. Peay and G. R. Morris and K. H. Abed",
  booktitle =    "{2011 Proceedings of IEEE Southeastcon}",
  title =        "Integrating {Quartus Wizard}-based {VHDL}
                 floating-point components into a high performance
                 heterogeneous computing environment",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "413--417",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/SECON.2011.5752977",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5752977",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5746658",
}


bibtype: article
filename: fparith.bib
label: Piso:2011:VLG
author: Daniel Piso and Javier D. Bruguera
title: Variable Latency Goldschmidt Algorithm Based on a New Rounding Method and a Remainder Estimate
journal: j-IEEE-TRANS-COMPUT
volume: 60
number: 11
pages: 1535--1546
month: nov
monthnumber: 11
year: 2011
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2010.269
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Sep 27 07:57:50 MDT 2011
bibtimestamp: 2011.09.27 07:57:50 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5669291
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Daniel Piso and Javier D. Bruguera
rawtitle: Variable Latency {Goldschmidt} Algorithm Based on a New Rounding Method and a Remainder Estimate
abstract:
A new variable latency Goldschmidt algorithm is presented. The algorithm is based on a new rounding method for division, square root, and their reciprocals that avoids the conventional remainder calculation in most of cases and improves previous proposals. The rounding decision is taken by checking the least significant bits of the output of the last Goldschmidt iteration without any other transformation. This helps to reduce the number of cases which need the calculation of the remainder. Additionally, we avoid the calculation of the remainder for most of those cases by using a remainder estimate that can be easily obtained from the Goldschmidt iteration. The calculation of the estimate is much simpler and less time consuming than the calculation of the remainder and this contributes to reducing the number of cases which need a large latency. The combination of both techniques allows us to define a variable latency algorithm which needs to compute the remainder in just nine percent of the total number of cases for reciprocal and division and in 12 percent for square root and square root reciprocal.

keywords:
accuracy; approximation algorithms; approximation methods; computers; division; equations; Goldschmidt algorithm; hardware; mathematical model; reciprocal; rounding; square root; square root reciprocal; variable latency.

rawabstract:
A new variable latency Goldschmidt algorithm is presented. The algorithm is based on a new rounding method for division, square root, and their reciprocals that avoids the conventional remainder calculation in most of cases and improves previous proposals. The rounding decision is taken by checking the least significant bits of the output of the last Goldschmidt iteration without any other transformation. This helps to reduce the number of cases which need the calculation of the remainder. Additionally, we avoid the calculation of the remainder for most of those cases by using a remainder estimate that can be easily obtained from the Goldschmidt iteration. The calculation of the estimate is much simpler and less time consuming than the calculation of the remainder and this contributes to reducing the number of cases which need a large latency. The combination of both techniques allows us to define a variable latency algorithm which needs to compute the remainder in just nine percent of the total number of cases for reciprocal and division and in 12 percent for square root and square root reciprocal.

entry:
@Article{Piso:2011:VLG,
  author =       "Daniel Piso and Javier D. Bruguera",
  title =        "Variable Latency {Goldschmidt} Algorithm Based on a
                 New Rounding Method and a Remainder Estimate",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "60",
  number =       "11",
  pages =        "1535--1546",
  month =        nov,
  year =         "2011",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2010.269",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Sep 27 07:57:50 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5669291",
  abstract =     "A new variable latency Goldschmidt algorithm is
                 presented. The algorithm is based on a new rounding
                 method for division, square root, and their reciprocals
                 that avoids the conventional remainder calculation in
                 most of cases and improves previous proposals. The
                 rounding decision is taken by checking the least
                 significant bits of the output of the last Goldschmidt
                 iteration without any other transformation. This helps
                 to reduce the number of cases which need the
                 calculation of the remainder. Additionally, we avoid
                 the calculation of the remainder for most of those
                 cases by using a remainder estimate that can be easily
                 obtained from the Goldschmidt iteration. The
                 calculation of the estimate is much simpler and less
                 time consuming than the calculation of the remainder
                 and this contributes to reducing the number of cases
                 which need a large latency. The combination of both
                 techniques allows us to define a variable latency
                 algorithm which needs to compute the remainder in just
                 nine percent of the total number of cases for
                 reciprocal and division and in 12 percent for square
                 root and square root reciprocal.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "accuracy; approximation algorithms; approximation
                 methods; computers; division; equations; Goldschmidt
                 algorithm; hardware; mathematical model; reciprocal;
                 rounding; square root; square root reciprocal; variable
                 latency.",
}


bibtype: inproceedings
filename: fparith.bib
label: Preusser:2011:ACF
author: Thomas B. Preuss er and Martin Zabel and Rainer G. Spallek
title: Accelerating Computations on FPGA Carry Chains by Operand Compaction
crossref: Schwarz:2011:PIS
pages: 95--102
year: 2011
DOI: https://doi.org/10.1109/ARITH.2011.22
bibdate: Sat Aug 20 09:00:00 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.08.20 09:00:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992114
keywords: ARITH-20
acknowledgement: ack-nhfb
rawauthor: Thomas B. Preu{\ss}er and Martin Zabel and Rainer G. Spallek
rawtitle: Accelerating Computations on {FPGA} Carry Chains by Operand Compaction
entry:
@InProceedings{Preusser:2011:ACF,
  author =       "Thomas B. Preu{\ss}er and Martin Zabel and Rainer G.
                 Spallek",
  title =        "Accelerating Computations on {FPGA} Carry Chains by
                 Operand Compaction",
  crossref =     "Schwarz:2011:PIS",
  pages =        "95--102",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ARITH.2011.22",
  bibdate =      "Sat Aug 20 09:00:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992114",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-20",
}


bibtype: inproceedings
filename: fparith.bib
label: Ramakrishnan:2011:AFP
author: A. Ramakrishnan and J. M. Conrad
booktitle: 2011 Proceedings of IEEE Southeastcon
title: Analysis of floating point operations in microcontrollers
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 97--100
year: 2011
DOI: https://doi.org/10.1109/SECON.2011.5752913
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5752913
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5746658
rawauthor: A. Ramakrishnan and J. M. Conrad
rawbooktitle: {2011 Proceedings of IEEE Southeastcon}
rawtitle: Analysis of floating point operations in microcontrollers
entry:
@InProceedings{Ramakrishnan:2011:AFP,
  author =       "A. Ramakrishnan and J. M. Conrad",
  booktitle =    "{2011 Proceedings of IEEE Southeastcon}",
  title =        "Analysis of floating point operations in
                 microcontrollers",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "97--100",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/SECON.2011.5752913",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5752913",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5746658",
}


bibtype: article
filename: fparith.bib
label: Romano:2011:NLR
author: Paul K. Romano and Harry McLaughlin
title: On Non-Linear Recursive Sequences and Benford's Law
journal: j-FIB-QUART
volume: 49
number: 2
pages: 134--138
month: may
monthnumber: 5
year: 2011
CODEN: FIBQAU
ISSN: 0015-0517 OR 00150517
ISSNL: 0015-0517 OR 00150517
bibdate: Thu Oct 20 18:04:45 MDT 2011
bibtimestamp: 2011.10.20 18:04:45 MDT
URL: http://www.fq.math.ca/Abstracts/49-2/romano.pdf
fjournal: The Fibonacci Quarterly
acknowledgement: ack-nhfb
ajournal: Fib. Quart
journalURL: http://www.fq.math.ca/
rawauthor: Paul K. Romano and Harry McLaughlin
rawtitle: On Non-Linear Recursive Sequences and {Benford's Law}
bibsource:
http://www.fq.math.ca/49-2.html; https://www.math.utah.edu/pub/tex/bib/fibquart.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Romano:2011:NLR,
  author =       "Paul K. Romano and Harry McLaughlin",
  title =        "On Non-Linear Recursive Sequences and {Benford's
                 Law}",
  journal =      j-FIB-QUART,
  volume =       "49",
  number =       "2",
  pages =        "134--138",
  month =        may,
  year =         "2011",
  CODEN =        "FIBQAU",
  ISSN =         "0015-0517",
  ISSN-L =       "0015-0517",
  bibdate =      "Thu Oct 20 18:04:45 MDT 2011",
  bibsource =    "http://www.fq.math.ca/49-2.html;
                 https://www.math.utah.edu/pub/tex/bib/fibquart.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.fq.math.ca/Abstracts/49-2/romano.pdf",
  acknowledgement = ack-nhfb,
  ajournal =     "Fib. Quart",
  fjournal =     "The Fibonacci Quarterly",
  journal-URL =  "http://www.fq.math.ca/",
}


bibtype: article
filename: fparith.bib
label: Romanovski:2011:ASS
author: Valery G. Romanovski and Mateja Presern
title: An approach to solving systems of polynomials via modular arithmetics with applications
journal: j-J-COMPUT-APPL-MATH
volume: 236
number: 2
pages: 196--208
day: 15
month: aug
monthnumber: 8
year: 2011
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:24:37 MST 2017
bibtimestamp: 2017.02.25 13:24:37 MST
URL: http://www.sciencedirect.com/science/article/pii/S0377042711003542
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Valery G. Romanovski and Mateja Presern
rawtitle: An approach to solving systems of polynomials via modular arithmetics with applications
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2010.bib

entry:
@Article{Romanovski:2011:ASS,
  author =       "Valery G. Romanovski and Mateja Presern",
  title =        "An approach to solving systems of polynomials via
                 modular arithmetics with applications",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "236",
  number =       "2",
  pages =        "196--208",
  day =          "15",
  month =        aug,
  year =         "2011",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:24:37 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2010.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042711003542",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: inproceedings
filename: fparith.bib
label: Rupp:2011:SBF
author: Benjamin Rupp and Howard Lovatt and Andrea Vezzini
booktitle: Proceedings of the 2011 14th European Conference on Power Electronics and Applications (EPE 2011)
title: Simulink-based floating-point DSP Control Platform
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--7
year: 2011
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6020132
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6014782
rawauthor: Benjamin Rupp and Howard Lovatt and Andrea Vezzini
rawbooktitle: {Proceedings of the 2011 14th European Conference on Power Electronics and Applications (EPE 2011)}
rawtitle: Simulink-based floating-point {DSP} Control Platform
entry:
@InProceedings{Rupp:2011:SBF,
  author =       "Benjamin Rupp and Howard Lovatt and Andrea Vezzini",
  booktitle =    "{Proceedings of the 2011 14th European Conference on
                 Power Electronics and Applications (EPE 2011)}",
  title =        "Simulink-based floating-point {DSP} Control Platform",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "1--7",
  year =         "2011",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6020132",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6014782",
}


bibtype: inproceedings
filename: fparith.bib
label: Samman:2011:RSP
author: F. A. Samman and P. Surapong and M. Glesner
booktitle: 2011 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2011
DOI: https://doi.org/10.1109/ReCoSoC.2011.5981539
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5981539
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5967008
rawauthor: F. A. Samman and P. Surapong and M. Glesner
rawbooktitle: {2011 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}
title:
Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems

rawtitle:
Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems

entry:
@InProceedings{Samman:2011:RSP,
  author =       "F. A. Samman and P. Surapong and M. Glesner",
  booktitle =    "{2011 6th International Workshop on Reconfigurable
                 Communication-centric Systems-on-Chip (ReCoSoC)}",
  title =        "Reconfigurable streaming processor core with
                 interconnected floating-point arithmetic units for
                 multicore adaptive signal processing systems",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "1--6",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ReCoSoC.2011.5981539",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5981539",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5967008",
}


bibtype: inproceedings
filename: fparith.bib
label: Sarbishei:2011:FPA
author: Omid Sarbishei and Katarzyna Radecka
title: On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC Multipliers
crossref: Schwarz:2011:PIS
pages: 62--69
year: 2011
DOI: https://doi.org/10.1109/ARITH.2011.17
bibdate: Sat Aug 20 09:00:00 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.08.20 09:00:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992109
keywords: ARITH-20
acknowledgement: ack-nhfb
rawauthor: Omid Sarbishei and Katarzyna Radecka
rawtitle: On the Fixed-Point Accuracy Analysis and Optimization of {FFT} Units with {CORDIC} Multipliers
entry:
@InProceedings{Sarbishei:2011:FPA,
  author =       "Omid Sarbishei and Katarzyna Radecka",
  title =        "On the Fixed-Point Accuracy Analysis and Optimization
                 of {FFT} Units with {CORDIC} Multipliers",
  crossref =     "Schwarz:2011:PIS",
  pages =        "62--69",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ARITH.2011.17",
  bibdate =      "Sat Aug 20 09:00:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992109",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-20",
}


bibtype: article
filename: fparith.bib
label: Seidel:2011:FVI
author: Peter-Michael Seidel
title: Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback
journal: arXiv.org
pages: ??--??
day: 21
month: oct
monthnumber: 10
year: 2011
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
note: Published in EPTCS 70, 2011, pp. 70--83.
URL: http://arxiv.org/abs/1110.4675
subject: Logic in Computer Science (cs.LO); Hardware Architecture (cs.AR); Mathematical Software (cs.MS)
acknowledgement: ack-nhfb
rawauthor: Peter-Michael Seidel
rawnote: Published in EPTCS 70, 2011, pp. 70--83.
rawtitle: Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback
abstract:
We present the formal verification of a low-power x86 floating-point multiplier. The multiplier operates iteratively and feeds back intermediate results in redundant representation. It supports x87 and SSE instructions in various precisions and can block the issuing of new instructions. The design has been optimized for low-power operation and has not been constrained by the formal verification effort. Additional improvements for the implementation were identified through formal verification. The formal verification of the design also incorporates the implementation of clock-gating and control logic. The core of the verification effort was based on ACL2 theorem proving. Additionally, model checking has been used to verify some properties of the floating-point scheduler that are relevant for the correct operation of the unit.

rawabstract:
We present the formal verification of a low-power x86 floating-point multiplier. The multiplier operates iteratively and feeds back intermediate results in redundant representation. It supports x87 and SSE instructions in various precisions and can block the issuing of new instructions. The design has been optimized for low-power operation and has not been constrained by the formal verification effort. Additional improvements for the implementation were identified through formal verification. The formal verification of the design also incorporates the implementation of clock-gating and control logic. The core of the verification effort was based on ACL2 theorem proving. Additionally, model checking has been used to verify some properties of the floating-point scheduler that are relevant for the correct operation of the unit.

entry:
@Article{Seidel:2011:FVI,
  author =       "Peter-Michael Seidel",
  title =        "Formal Verification of an Iterative Low-Power x86
                 Floating-Point Multiplier with Redundant Feedback",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "21",
  month =        oct,
  year =         "2011",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Published in EPTCS 70, 2011, pp. 70--83.",
  URL =          "http://arxiv.org/abs/1110.4675",
  abstract =     "We present the formal verification of a low-power x86
                 floating-point multiplier. The multiplier operates
                 iteratively and feeds back intermediate results in
                 redundant representation. It supports x87 and SSE
                 instructions in various precisions and can block the
                 issuing of new instructions. The design has been
                 optimized for low-power operation and has not been
                 constrained by the formal verification effort.
                 Additional improvements for the implementation were
                 identified through formal verification. The formal
                 verification of the design also incorporates the
                 implementation of clock-gating and control logic. The
                 core of the verification effort was based on ACL2
                 theorem proving. Additionally, model checking has been
                 used to verify some properties of the floating-point
                 scheduler that are relevant for the correct operation
                 of the unit.",
  acknowledgement = ack-nhfb,
  subject =      "Logic in Computer Science (cs.LO); Hardware
                 Architecture (cs.AR); Mathematical Software (cs.MS)",
}


bibtype: article
filename: fparith.bib
label: Seo:2011:GDP
author: Young-Hun Seo and Seon-Kyoo Lee and Jae-Yoon Sim
title: A 1-GHz Digital PLL with a 3-ps resolution floating-point-number TDC in a 0.18-CMOS
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 58
number: 2
pages: 70--74
year: 2011
DOI: https://doi.org/10.1109/TCSII.2011.2106315
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5713246
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8920
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Young-Hun Seo and Seon-Kyoo Lee and Jae-Yoon Sim
rawtitle: A {1-GHz} Digital {PLL} with a 3-ps resolution floating-point-number {TDC} in a 0.18-{CMOS}
entry:
@Article{Seo:2011:GDP,
  author =       "Young-Hun Seo and Seon-Kyoo Lee and Jae-Yoon Sim",
  title =        "A {1-GHz} Digital {PLL} with a 3-ps resolution
                 floating-point-number {TDC} in a 0.18-{CMOS}",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "58",
  number =       "2",
  pages =        "70--74",
  month =        "????",
  year =         "2011",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/TCSII.2011.2106315",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5713246",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8920",
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
}


bibtype: article
filename: fparith.bib
label: Siegel:2011:LAL
author: Stefan Siegel and Jurgen Wolff von Gudenberg
title: A long accumulator like a carry-save adder
journal: j-COMPUTING
volume: 93
pages: ??--??
year: 2011
CODEN: CMPTA2
DOI: https://doi.org/10.1007/s00607-011-0164-x
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
bibdate: Fri Nov 18 15:08:38 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.11.18 15:08:38 ???
fjournal: Computing: Archiv fur informatik und numerik
keywords: accurate floating-point summation
remark: Online on 12 November 2011, but not yet assigned to a journal issue.
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/607
rawauthor: Stefan Siegel and J{\"u}rgen Wolff von Gudenberg
rawtitle: A long accumulator like a carry-save adder
entry:
@Article{Siegel:2011:LAL,
  author =       "Stefan Siegel and J{\"u}rgen Wolff von Gudenberg",
  title =        "A long accumulator like a carry-save adder",
  journal =      j-COMPUTING,
  volume =       "93",
  number =       "??",
  pages =        "??--??",
  month =        "????",
  year =         "2011",
  CODEN =        "CMPTA2",
  DOI =          "https://doi.org/10.1007/s00607-011-0164-x",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  bibdate =      "Fri Nov 18 15:08:38 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing: Archiv f{\"u}r informatik und numerik",
  journal-URL =  "http://link.springer.com/journal/607",
  keywords =     "accurate floating-point summation",
  pagecount =    "11",
  remark =       "Online on 12 November 2011, but not yet assigned to a
                 journal issue.",
}


bibtype: inproceedings
filename: fparith.bib
label: Singh:2011:VEF
author: R. R. Singh and A. Tiwari and V. K. Singh and G. S. Tomar
booktitle: 2011 International Conference on Communication Systems and Network Technologies (CSNT)
title: VHDL Environment for Floating Point Arithmetic Logic Unit-ALU Design and Simulation
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 469--472
year: 2011
DOI: https://doi.org/10.1109/CSNT.2011.167
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5966491
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5963767
rawauthor: R. R. Singh and A. Tiwari and V. K. Singh and G. S. Tomar
rawbooktitle: {2011 International Conference on Communication Systems and Network Technologies (CSNT)}
rawtitle: {VHDL} Environment for Floating Point Arithmetic Logic Unit-{ALU} Design and Simulation
entry:
@InProceedings{Singh:2011:VEF,
  author =       "R. R. Singh and A. Tiwari and V. K. Singh and G. S.
                 Tomar",
  booktitle =    "{2011 International Conference on Communication
                 Systems and Network Technologies (CSNT)}",
  title =        "{VHDL} Environment for Floating Point Arithmetic Logic
                 Unit-{ALU} Design and Simulation",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "469--472",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/CSNT.2011.167",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5966491",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5963767",
}


bibtype: article
filename: fparith.bib
label: Singha:2011:NAF
author: Satrughna Singha and Aniruddha Ghosh and Amitabha Sinha
journal: j-COMP-ARCH-NEWS
volume: 39
number: 5
pages: 12--18
month: dec
monthnumber: 12
year: 2011
CODEN: CANED2
DOI: https://doi.org/10.1145/2093339.2093343
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Thu Mar 15 14:07:10 MDT 2012
bibtimestamp: 2012.03.15 14:07:10 MDT
fjournal: ACM SIGARCH Computer Architecture News
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J89
rawauthor: Satrughna Singha and Aniruddha Ghosh and Amitabha Sinha
title:
A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique

bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigarch.bib

abstract:
Non-binary number systems are increasingly gaining popularity in signal processing applications for their capabilities of handling arithmetic operations efficiently. One such number system, ``Double Base Number System (DBNS)'' has gained attention to many researchers for it's capability of performing multiplication operation efficiently. Recently, ``Triple Base Number System (TBNS)'' has been introduced which shows better performance over DBNS for higher bit operations in terms of speed, hardware complexity and power dissipation. However, the advantages of TBNS systems cannot be exploited due to substantial overhead of conversion from binary to TBNS. Keeping this issue in view, in this paper, a novel architecture has been proposed for high performance binary to TBNS conversion. Efficiency of this conversion scheme has been dealt with in details and experimental results and analysis clearly indicate the novelty of the architecture.

rawabstract:
Non-binary number systems are increasingly gaining popularity in signal processing applications for their capabilities of handling arithmetic operations efficiently. One such number system, ``Double Base Number System (DBNS)'' has gained attention to many researchers for it's capability of performing multiplication operation efficiently. Recently, ``Triple Base Number System (TBNS)'' has been introduced which shows better performance over DBNS for higher bit operations in terms of speed, hardware complexity and power dissipation. However, the advantages of TBNS systems cannot be exploited due to substantial overhead of conversion from binary to TBNS. Keeping this issue in view, in this paper, a novel architecture has been proposed for high performance binary to TBNS conversion. Efficiency of this conversion scheme has been dealt with in details and experimental results and analysis clearly indicate the novelty of the architecture.

rawtitle:
A new architecture for {FPGA} based implementation of conversion of binary to double base number system ({DBNS}) using parallel search technique

entry:
@Article{Singha:2011:NAF,
  author =       "Satrughna Singha and Aniruddha Ghosh and Amitabha
                 Sinha",
  title =        "A new architecture for {FPGA} based implementation of
                 conversion of binary to double base number system
                 ({DBNS}) using parallel search technique",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "39",
  number =       "5",
  pages =        "12--18",
  month =        dec,
  year =         "2011",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/2093339.2093343",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Thu Mar 15 14:07:10 MDT 2012",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Non-binary number systems are increasingly gaining
                 popularity in signal processing applications for their
                 capabilities of handling arithmetic operations
                 efficiently. One such number system, ``Double Base
                 Number System (DBNS)'' has gained attention to many
                 researchers for it's capability of performing
                 multiplication operation efficiently. Recently,
                 ``Triple Base Number System (TBNS)'' has been
                 introduced which shows better performance over DBNS for
                 higher bit operations in terms of speed, hardware
                 complexity and power dissipation. However, the
                 advantages of TBNS systems cannot be exploited due to
                 substantial overhead of conversion from binary to TBNS.
                 Keeping this issue in view, in this paper, a novel
                 architecture has been proposed for high performance
                 binary to TBNS conversion. Efficiency of this
                 conversion scheme has been dealt with in details and
                 experimental results and analysis clearly indicate the
                 novelty of the architecture.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
}


bibtype: inproceedings
filename: fparith.bib
label: Tang:2011:TCT
author: Ping Tak Peter Tang and J. Adam Butts and Ron O. Dror and David E. Shaw
crossref: Schwarz:2011:PIS
pages: 159--168
year: 2011
DOI: https://doi.org/10.1109/ARITH.2011.29
bibdate: Sat Aug 20 09:00:00 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.08.20 09:00:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992121
keywords: ARITH-20; reciprocal square root; rsqrt(x)
acknowledgement: ack-nhfb
rawauthor: Ping Tak Peter Tang and J. Adam Butts and Ron O. Dror and David E. Shaw
title:
Tight Certification Techniques for Digit-by-Rounding Algorithms with Application to a New $ 1 / sqrt x $ Design

rawtitle:
Tight Certification Techniques for Digit-by-Rounding Algorithms with Application to a New $ 1 / \sqrt {x} $ Design

entry:
@InProceedings{Tang:2011:TCT,
  author =       "Ping Tak Peter Tang and J. Adam Butts and Ron O. Dror
                 and David E. Shaw",
  title =        "Tight Certification Techniques for Digit-by-Rounding
                 Algorithms with Application to a New $ 1 / \sqrt {x} $
                 Design",
  crossref =     "Schwarz:2011:PIS",
  pages =        "159--168",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ARITH.2011.29",
  bibdate =      "Sat Aug 20 09:00:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992121",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-20; reciprocal square root; rsqrt(x)",
}


bibtype: article
filename: fparith.bib
label: Tsen:2011:HDB
author: Charles Tsen and Sonia Gonzalez-Navarro and Michael J. Schulte and Katherine Compton
title: Hardware Designs for Binary Integer Decimal-Based Rounding
journal: j-IEEE-TRANS-COMPUT
volume: 60
number: 5
pages: 614--627
month: may
monthnumber: 5
year: 2011
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2010.268
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jun 29 10:26:18 2011
bibtimestamp: 2011.06.29 10:26:18 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Charles Tsen and Sonia Gonzalez-Navarro and Michael J. Schulte and Katherine Compton
rawtitle: Hardware Designs for Binary Integer Decimal-Based Rounding
abstract:
Decimal floating-point (DFP) arithmetic is becoming increasingly important, and specifications for it are included in the revised IEEE 754 Standard for Floating-Point Arithmetic (IEEE 754-2008). The binary encoding of DFP numbers specified in IEEE 754-2008 is commonly referred to as Binary-Integer Decimal (BID). BID uses a binary integer to encode the significand, which allows it to leverage existing high-speed binary circuits. However, performing decimal rounding on these binary significands is challenging. In this paper, we propose and evaluate several approaches to perform decimal rounding in hardware for DFP numbers that use the BID encoding. We summarize several rounding techniques, present the theory and design of each proposed rounding unit, and use synthesis results to evaluate the critical path delay, latency, and area of rounding units for 64-bit BID numbers. Our results indicate that the bulk of each rounder design is occupied by a binary fixed-point multiplier that can be shared with other integer and floating-point operations. This is the first paper to present and compare a variety of techniques for BID-based rounding hardware. These techniques are valuable to designers of BID-based DFP solutions.

keywords:
Arithmetic algorithms; BID rounding; binary integer decimal; computer arithmetic; decimal floating-point; hardware designs; IEEE 754-2008; rounding

rawabstract:
Decimal floating-point (DFP) arithmetic is becoming increasingly important, and specifications for it are included in the revised IEEE 754 Standard for Floating-Point Arithmetic (IEEE 754-2008). The binary encoding of DFP numbers specified in IEEE 754-2008 is commonly referred to as Binary-Integer Decimal (BID). BID uses a binary integer to encode the significand, which allows it to leverage existing high-speed binary circuits. However, performing decimal rounding on these binary significands is challenging. In this paper, we propose and evaluate several approaches to perform decimal rounding in hardware for DFP numbers that use the BID encoding. We summarize several rounding techniques, present the theory and design of each proposed rounding unit, and use synthesis results to evaluate the critical path delay, latency, and area of rounding units for 64-bit BID numbers. Our results indicate that the bulk of each rounder design is occupied by a binary fixed-point multiplier that can be shared with other integer and floating-point operations. This is the first paper to present and compare a variety of techniques for BID-based rounding hardware. These techniques are valuable to designers of BID-based DFP solutions.

entry:
@Article{Tsen:2011:HDB,
  author =       "Charles Tsen and Sonia Gonzalez-Navarro and Michael J.
                 Schulte and Katherine Compton",
  title =        "Hardware Designs for Binary Integer Decimal-Based
                 Rounding",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "60",
  number =       "5",
  pages =        "614--627",
  month =        may,
  year =         "2011",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2010.268",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jun 29 10:26:18 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  abstract =     "Decimal floating-point (DFP) arithmetic is becoming
                 increasingly important, and specifications for it are
                 included in the revised IEEE 754 Standard for
                 Floating-Point Arithmetic (IEEE 754-2008). The binary
                 encoding of DFP numbers specified in IEEE 754-2008 is
                 commonly referred to as Binary-Integer Decimal (BID).
                 BID uses a binary integer to encode the significand,
                 which allows it to leverage existing high-speed binary
                 circuits. However, performing decimal rounding on these
                 binary significands is challenging. In this paper, we
                 propose and evaluate several approaches to perform
                 decimal rounding in hardware for DFP numbers that use
                 the BID encoding. We summarize several rounding
                 techniques, present the theory and design of each
                 proposed rounding unit, and use synthesis results to
                 evaluate the critical path delay, latency, and area of
                 rounding units for 64-bit BID numbers. Our results
                 indicate that the bulk of each rounder design is
                 occupied by a binary fixed-point multiplier that can be
                 shared with other integer and floating-point
                 operations. This is the first paper to present and
                 compare a variety of techniques for BID-based rounding
                 hardware. These techniques are valuable to designers of
                 BID-based DFP solutions.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Arithmetic algorithms; BID rounding; binary integer
                 decimal; computer arithmetic; decimal floating-point;
                 hardware designs; IEEE 754-2008; rounding",
}


bibtype: inproceedings
filename: fparith.bib
label: Vazquez:2011:CIA
author: Alvaro Vazquez and Javier D. Bruguera
title: Composite Iterative Algorithm and Architecture for $q$-th Root Calculation
crossref: Schwarz:2011:PIS
pages: 52--61
year: 2011
DOI: https://doi.org/10.1109/ARITH.2011.16
bibdate: Sat Aug 20 09:00:00 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.08.20 09:00:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992108
keywords: ARITH-20
acknowledgement: ack-nhfb
rawauthor: {\'A}lvaro V{\'a}zquez and Javier D. Bruguera
rawtitle: Composite Iterative Algorithm and Architecture for $q$-th Root Calculation
entry:
@InProceedings{Vazquez:2011:CIA,
  author =       "{\'A}lvaro V{\'a}zquez and Javier D. Bruguera",
  title =        "Composite Iterative Algorithm and Architecture for
                 $q$-th Root Calculation",
  crossref =     "Schwarz:2011:PIS",
  pages =        "52--61",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ARITH.2011.16",
  bibdate =      "Sat Aug 20 09:00:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5992108",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-20",
}


bibtype: inproceedings
filename: fparith.bib
label: Vestias:2011:IDM
author: M. P. Vestias and H. C. Neto
booktitle: 2011 VII Southern Conference on Programmable Logic (SPL)
title: Iterative decimal multiplication using binary arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 257--262
year: 2011
DOI: https://doi.org/10.1109/SPL.2011.5782658
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5782658
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5771182
rawauthor: M. P. Vestias and H. C. Neto
rawbooktitle: {2011 VII Southern Conference on Programmable Logic (SPL)}
rawtitle: Iterative decimal multiplication using binary arithmetic
entry:
@InProceedings{Vestias:2011:IDM,
  author =       "M. P. Vestias and H. C. Neto",
  booktitle =    "{2011 VII Southern Conference on Programmable Logic
                 (SPL)}",
  title =        "Iterative decimal multiplication using binary
                 arithmetic",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "257--262",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/SPL.2011.5782658",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5782658",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5771182",
  keywords =     "decimal floating-point arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Vigliar:2011:MFB
author: Mario Vigliar and Giancarlo Raiconi and Amedeo D'Auria and Giuseppe Del Mastro
booktitle: 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)
title: Modelling a fast BLAS level-1 inspired vectorized FPU for ARM devices
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--4
year: 2011
DOI: https://doi.org/10.1109/MWSCAS.2011.6026644
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6026644
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6019810
rawauthor: Mario Vigliar and Giancarlo Raiconi and Amedeo D'Auria and Giuseppe Del Mastro
rawbooktitle: {2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)}
rawtitle: Modelling a fast {BLAS} level-1 inspired vectorized {FPU} for {ARM} devices
entry:
@InProceedings{Vigliar:2011:MFB,
  author =       "Mario Vigliar and Giancarlo Raiconi and Amedeo D'Auria
                 and Giuseppe Del Mastro",
  booktitle =    "{2011 IEEE 54th International Midwest Symposium on
                 Circuits and Systems (MWSCAS)}",
  title =        "Modelling a fast {BLAS} level-1 inspired vectorized
                 {FPU} for {ARM} devices",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "1--4",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/MWSCAS.2011.6026644",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6026644",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6019810",
}


bibtype: inproceedings
filename: fparith.bib
label: Wang:2011:DFB
author: Mulan Wang and Xinghua Zhu and Baosheng Wang and Xiaoxia Li
booktitle: 2011 International Conference on Mechatronic Science, Electric Engineering and Computer (MEC)
title: Development of FPGA-based arithmetic module in CNC system
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 494--497
year: 2011
DOI: https://doi.org/10.1109/MEC.2011.6025510
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6025510
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6020827
rawauthor: Mulan Wang and Xinghua Zhu and Baosheng Wang and Xiaoxia Li
rawbooktitle: {2011 International Conference on Mechatronic Science, Electric Engineering and Computer (MEC)}
rawtitle: Development of {FPGA}-based arithmetic module in {CNC} system
entry:
@InProceedings{Wang:2011:DFB,
  author =       "Mulan Wang and Xinghua Zhu and Baosheng Wang and
                 Xiaoxia Li",
  booktitle =    "{2011 International Conference on Mechatronic Science,
                 Electric Engineering and Computer (MEC)}",
  title =        "Development of {FPGA}-based arithmetic module in {CNC}
                 system",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "494--497",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/MEC.2011.6025510",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6025510",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6020827",
}


bibtype: article
filename: fparith.bib
label: Wang:2011:RCM
author: Xiaofang Wang and Pallav Gupta
title: Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs
journal: j-TODAES
volume: 16
number: 4
pages: 41:1--41:??
month: oct
monthnumber: 10
year: 2011
CODEN: ATASFO
DOI: https://doi.org/10.1145/2003695.2003701
ISSN: 1084-4309 (print), 1557-7309 (electronic) OR 10844309 (print), 15577309 (electronic)
ISSNL: 1084-4309 OR 10844309
bibdate: Sat Oct 22 09:25:48 MDT 2011
bibtimestamp: 2011.10.22 09:25:48 MDT
fjournal: ACM Transactions on Design Automation of Electronic Systems
acknowledgement: ack-nhfb
articleno: 41
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J776
rawauthor: Xiaofang Wang and Pallav Gupta
rawtitle: Resource-constrained multiprocessor synthesis for floating-point applications on {FPGAs}
bibsource:
http://www.acm.org/pubs/contents/journals/todaes/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/todaes.bib

entry:
@Article{Wang:2011:RCM,
  author =       "Xiaofang Wang and Pallav Gupta",
  title =        "Resource-constrained multiprocessor synthesis for
                 floating-point applications on {FPGAs}",
  journal =      j-TODAES,
  volume =       "16",
  number =       "4",
  pages =        "41:1--41:??",
  month =        oct,
  year =         "2011",
  CODEN =        "ATASFO",
  DOI =          "https://doi.org/10.1145/2003695.2003701",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Sat Oct 22 09:25:48 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/todaes/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/todaes.bib",
  acknowledgement = ack-nhfb,
  articleno =    "41",
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J776",
}


bibtype: techreport
filename: fparith.bib
label: Whitehead:2011:PPF
author: Nathan Whitehead and Alex Fit-Florea
title: Precision & Performance: Floating Point and IEEE 754 Compliance for NVIDIA GPUs
type: Report
institution: nVidia Corporation
address: Santa Clara, CA, USA
pages: 7
day: 21
month: jun
monthnumber: 6
year: 2011
bibdate: Tue Sep 04 09:13:29 2012
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2012.09.04 09:13:29 ???
URL: http://developer.download.nvidia.com/assets/cuda/files/NVIDIA-CUDA-Floating-Point.pdf
acknowledgement: ack-nhfb
rawauthor: Nathan Whitehead and Alex Fit-Florea
rawtitle: Precision \& Performance: Floating Point and {IEEE 754} Compliance for {NVIDIA GPUs}
entry:
@TechReport{Whitehead:2011:PPF,
  author =       "Nathan Whitehead and Alex Fit-Florea",
  title =        "Precision \& Performance: Floating Point and {IEEE
                 754} Compliance for {NVIDIA GPUs}",
  type =         "Report",
  institution =  "nVidia Corporation",
  address =      "Santa Clara, CA, USA",
  pages =        "7",
  day =          "21",
  month =        jun,
  year =         "2011",
  bibdate =      "Tue Sep 04 09:13:29 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://developer.download.nvidia.com/assets/cuda/files/NVIDIA-CUDA-Floating-Point.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Xu:2011:DLF
author: Jun Xu and Hong Wang
booktitle: 2011 IEEE International Symposium on Circuits and Systems (ISCAS)
title: Desynchronize a legacy floating-point adder with operand-dependant delay elements
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1427--1430
year: 2011
DOI: https://doi.org/10.1109/ISCAS.2011.5937841
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5937841
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5910713
rawauthor: Jun Xu and Hong Wang
rawbooktitle: {2011 IEEE International Symposium on Circuits and Systems (ISCAS)}
rawtitle: Desynchronize a legacy floating-point adder with operand-dependant delay elements
entry:
@InProceedings{Xu:2011:DLF,
  author =       "Jun Xu and Hong Wang",
  booktitle =    "{2011 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Desynchronize a legacy floating-point adder with
                 operand-dependant delay elements",
  publisher =    "pub-IEEE",
  address =      "pub-IEEE:adr",
  pages =        "1427--1430",
  year =         "2011",
  DOI =          "https://doi.org/10.1109/ISCAS.2011.5937841",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5937841",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5910713",
}


bibtype: inproceedings
filename: fparith.bib
label: Yeung:2011:MCF
author: Jackson H. C. Yeung and Evangeline F. Y. Young and Philip H. W. Leong
title: A Monte-Carlo floating-point unit for self-validating arithmetic
publisher: pub-ACM
address: pub-ACM:adr
pages: 199--208
year: 2011
DOI: https://doi.org/10.1145/1950413.1950453
ISBN: 1-4503-0554-7 OR 1450305547
ISBN13: 978-1-4503-0554-9 OR 9781450305549
bibdate: Tue Sep 27 08:57:51 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:57:51 ???
keywords: floating-point; FPGA; FPU; Monte Carlo arithmetic
acknowledgement: ack-nhfb
rawauthor: Jackson H. C. Yeung and Evangeline F. Y. Young and Philip H. W. Leong
rawtitle: A {Monte-Carlo} floating-point unit for self-validating arithmetic
booktitle:
FPGA '11: Proceedings of the 19th ACM / SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, USA, February 27--March 01, 2011

abstract:
Monte-Carlo arithmetic is a form of self-validating arithmetic that accounts for the effect of rounding errors. We have implemented a floating point unit that can perform either IEEE 754 or Monte-Carlo floating point computation, allowing hardware accelerated validation of results during execution. Experiments show that our approach has a modest hardware overhead and allows the propagation of rounding error to be accurately estimated.

rawabstract:
Monte-Carlo arithmetic is a form of self-validating arithmetic that accounts for the effect of rounding errors. We have implemented a floating point unit that can perform either IEEE 754 or Monte-Carlo floating point computation, allowing hardware accelerated validation of results during execution. Experiments show that our approach has a modest hardware overhead and allows the propagation of rounding error to be accurately estimated.

rawbooktitle:
{FPGA '11: Proceedings of the 19th ACM\slash SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, USA, February 27--March 01, 2011}

entry:
@InProceedings{Yeung:2011:MCF,
  author =       "Jackson H. C. Yeung and Evangeline F. Y. Young and
                 Philip H. W. Leong",
  booktitle =    "{FPGA '11: Proceedings of the 19th ACM\slash SIGDA
                 International Symposium on Field Programmable Gate
                 Arrays, Monterey, CA, USA, February 27--March 01,
                 2011}",
  title =        "A {Monte-Carlo} floating-point unit for
                 self-validating arithmetic",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "199--208",
  year =         "2011",
  DOI =          "https://doi.org/10.1145/1950413.1950453",
  ISBN =         "1-4503-0554-7",
  ISBN-13 =      "978-1-4503-0554-9",
  bibdate =      "Tue Sep 27 08:57:51 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Monte-Carlo arithmetic is a form of self-validating
                 arithmetic that accounts for the effect of rounding
                 errors. We have implemented a floating point unit that
                 can perform either IEEE 754 or Monte-Carlo floating
                 point computation, allowing hardware accelerated
                 validation of results during execution. Experiments
                 show that our approach has a modest hardware overhead
                 and allows the propagation of rounding error to be
                 accurately estimated.",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point; FPGA; FPU; Monte Carlo arithmetic",
  numpages =     "10",
}


bibtype: article
filename: fparith.bib
label: Yu:2011:OFP
author: C. Yu and A. M. Smith and W. Luk and P. H. W. Leong and S. J. E. Wilton
title: Optimizing Floating Point Units in Hybrid FPGAs
journal: j-IEEE-TRANS-VLSI-SYST
volume: PP
number: 99
pages: 1--10
year: 2011
CODEN: IEVSE9
DOI: https://doi.org/10.1109/TVLSI.2011.2153883
ISSN: 1063-8210 (print), 1557-9999 (electronic) OR 10638210 (print), 15579999 (electronic)
ISSNL: 1063-8210 OR 10638210
bibdate: Tue Sep 27 08:11:02 MDT 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.09.27 08:11:02 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5893965
fjournal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
acknowledgement: ack-nhfb
bookURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=92
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=92
rawauthor: C. Yu and A. M. Smith and W. Luk and P. H. W. Leong and S. J. E. Wilton
rawtitle: Optimizing Floating Point Units in Hybrid {FPGAs}
entry:
@Article{Yu:2011:OFP,
  author =       "C. Yu and A. M. Smith and W. Luk and P. H. W. Leong
                 and S. J. E. Wilton",
  title =        "Optimizing Floating Point Units in Hybrid {FPGAs}",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "PP",
  number =       "99",
  pages =        "1--10",
  month =        "????",
  year =         "2011",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2011.2153883",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Tue Sep 27 08:11:02 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5893965",
  acknowledgement = ack-nhfb,
  book-URL =     "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=92",
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}


bibtype: article
filename: fparith.bib
label: Zalaket:2011:PFU
author: Joseph Zalaket and Joseph Hajj-Boutros
title: Prime factorization using square root approximation
journal: j-COMPUT-MATH-APPL
volume: 61
number: 9
pages: 2463--2467
month: may
monthnumber: 5
year: 2011
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 21:50:54 MST 2017
bibtimestamp: 2017.03.01 21:50:54 MST
URL: http://www.sciencedirect.com/science/article/pii/S0898122111001131
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: Joseph Zalaket and Joseph Hajj-Boutros
rawtitle: Prime factorization using square root approximation
bibsource:
https://www.math.utah.edu/pub/tex/bib/computmathappl2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Zalaket:2011:PFU,
  author =       "Joseph Zalaket and Joseph Hajj-Boutros",
  title =        "Prime factorization using square root approximation",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "61",
  number =       "9",
  pages =        "2463--2467",
  month =        may,
  year =         "2011",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 21:50:54 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0898122111001131",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: article
filename: fparith.bib
label: Abbott:2012:TFA
author: John Abbott
title: Twin-float arithmetic
journal: j-J-SYMBOLIC-COMP
volume: 47
number: 5
pages: 536--551
month: may
monthnumber: 5
year: 2012
CODEN: JSYCEH
DOI: https://doi.org/10.1016/j.jsc.2011.12.005
ISSN: 0747-7171 (print), 1095-855X (electronic) OR 07477171 (print), 1095855X (electronic)
ISSNL: 0747-7171 OR 07477171
bibdate: Sat Feb 25 10:12:47 MST 2012
bibtimestamp: 2012.02.25 10:12:47 MST
URL: http://www.sciencedirect.com/science/article/pii/S0747717111001970
fjournal: Journal of Symbolic Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/07477171
rawauthor: John Abbott
rawtitle: Twin-float arithmetic
bibsource:
http://www.sciencedirect.com/science/journal/07477171; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jsymcomp.bib

abstract:
We present a heuristically certified form of floating-point arithmetic and its implementation in CoCoALib. This arithmetic is intended to act as a fast alternative to exact rational arithmetic, and is developed from the idea of paired floats expounded by Traverso and Zanoni (2002). As prerequisites we need a source of (pseudo-)random numbers, and an underlying floating-point arithmetic system where the user can set the precision. Twin-float arithmetic can be used only where the input data are exact, or can be obtained at high enough precision. Our arithmetic includes a total cancellation heuristic for sums and differences, and so can be used in classical algebraic algorithms such as Buchberger's algorithm. We also present a (new) algorithm for recovering an exact rational value from a twin-float, so in some cases an exact answer can be obtained from an approximate computation.par The ideas presented here are implemented as a ring in CoCoALib, called RingTwinFloat, allowing them to be used easily in a wide variety of algebraic computations (including Grobner bases).

rawabstract:
We present a heuristically certified form of floating-point arithmetic and its implementation in CoCoALib. This arithmetic is intended to act as a fast alternative to exact rational arithmetic, and is developed from the idea of paired floats expounded by Traverso and Zanoni (2002). As prerequisites we need a source of (pseudo-)random numbers, and an underlying floating-point arithmetic system where the user can set the precision. Twin-float arithmetic can be used only where the input data are exact, or can be obtained at high enough precision. Our arithmetic includes a total cancellation heuristic for sums and differences, and so can be used in classical algebraic algorithms such as Buchberger's algorithm. We also present a (new) algorithm for recovering an exact rational value from a twin-float, so in some cases an exact answer can be obtained from an approximate computation.\par The ideas presented here are implemented as a ring in CoCoALib, called RingTwinFloat, allowing them to be used easily in a wide variety of algebraic computations (including Gr{\"o}bner bases).

entry:
@Article{Abbott:2012:TFA,
  author =       "John Abbott",
  title =        "Twin-float arithmetic",
  journal =      j-J-SYMBOLIC-COMP,
  volume =       "47",
  number =       "5",
  pages =        "536--551",
  month =        may,
  year =         "2012",
  CODEN =        "JSYCEH",
  DOI =          "https://doi.org/10.1016/j.jsc.2011.12.005",
  ISSN =         "0747-7171 (print), 1095-855X (electronic)",
  ISSN-L =       "0747-7171",
  bibdate =      "Sat Feb 25 10:12:47 MST 2012",
  bibsource =    "http://www.sciencedirect.com/science/journal/07477171;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsymcomp.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0747717111001970",
  abstract =     "We present a heuristically certified form of
                 floating-point arithmetic and its implementation in
                 CoCoALib. This arithmetic is intended to act as a fast
                 alternative to exact rational arithmetic, and is
                 developed from the idea of paired floats expounded by
                 Traverso and Zanoni (2002). As prerequisites we need a
                 source of (pseudo-)random numbers, and an underlying
                 floating-point arithmetic system where the user can set
                 the precision. Twin-float arithmetic can be used only
                 where the input data are exact, or can be obtained at
                 high enough precision. Our arithmetic includes a total
                 cancellation heuristic for sums and differences, and so
                 can be used in classical algebraic algorithms such as
                 Buchberger's algorithm. We also present a (new)
                 algorithm for recovering an exact rational value from a
                 twin-float, so in some cases an exact answer can be
                 obtained from an approximate computation.\par

                 The ideas presented here are implemented as a ring in
                 CoCoALib, called RingTwinFloat, allowing them to be
                 used easily in a wide variety of algebraic computations
                 (including Gr{\"o}bner bases).",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Symbolic Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/07477171",
}


bibtype: article
filename: fparith.bib
label: Adam:2012:FPD
author: Sanda Adam and Gheorghe Adam
title: Floating Point Degree of Precision in Numerical Quadrature
journal: j-LECT-NOTES-COMP-SCI
volume: 7125
pages: 189--194
year: 2012
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-28212-6_19
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Wed Dec 19 15:24:39 MST 2012
bibtimestamp: 2012.12.19 15:24:39 MST
URL: http://link.springer.com/chapter/10.1007/978-3-642-28212-6_19/
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-642-28212-6
bookURL: http://www.springerlink.com/content/978-3-642-28212-6
journalURL: http://link.springer.com/bookseries/558
rawauthor: Sanda Adam and Gheorghe Adam
rawtitle: Floating Point Degree of Precision in Numerical Quadrature
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs2012b.bib

entry:
@Article{Adam:2012:FPD,
  author =       "Sanda Adam and Gheorghe Adam",
  title =        "Floating Point Degree of Precision in Numerical
                 Quadrature",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "7125",
  pages =        "189--194",
  year =         "2012",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-28212-6_19",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Wed Dec 19 15:24:39 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs2012b.bib",
  URL =          "http://link.springer.com/chapter/10.1007/978-3-642-28212-6_19/",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-642-28212-6",
  book-URL =     "http://www.springerlink.com/content/978-3-642-28212-6",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Aharony:2012:IFP
author: Merav Aharony and Emanuel Gofman and Elena Guralnik and Anatoly Koyfman
title: Injecting Floating-Point Testing Knowledge into Test Generators
journal: j-LECT-NOTES-COMP-SCI
volume: 7261
pages: 234--241
year: 2012
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-34188-5_20
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Wed Dec 19 15:18:42 MST 2012
bibtimestamp: 2012.12.19 15:18:42 MST
URL: http://link.springer.com/chapter/10.1007/978-3-642-34188-5_20/
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-642-34188-5
bookURL: http://www.springerlink.com/content/978-3-642-34188-5
journalURL: http://link.springer.com/bookseries/558
rawauthor: Merav Aharony and Emanuel Gofman and Elena Guralnik and Anatoly Koyfman
rawtitle: Injecting Floating-Point Testing Knowledge into Test Generators
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs2012d.bib

entry:
@Article{Aharony:2012:IFP,
  author =       "Merav Aharony and Emanuel Gofman and Elena Guralnik
                 and Anatoly Koyfman",
  title =        "Injecting Floating-Point Testing Knowledge into Test
                 Generators",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "7261",
  pages =        "234--241",
  year =         "2012",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-34188-5_20",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Wed Dec 19 15:18:42 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs2012d.bib",
  URL =          "http://link.springer.com/chapter/10.1007/978-3-642-34188-5_20/",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-642-34188-5",
  book-URL =     "http://www.springerlink.com/content/978-3-642-34188-5",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Akleylek:2012:MRR
author: Sedat Akleylek and Ferruh Ozbudak
title: Modified Redundant Representation for Designing Arithmetic Circuits with Small Complexity
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 3
pages: 427--432
month: mar
monthnumber: 3
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2011.29
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Feb 3 07:35:03 2012
bibtimestamp: 2012.02.03 07:35:03 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Sedat Akleylek and Ferruh Ozbudak
rawtitle: Modified Redundant Representation for Designing Arithmetic Circuits with Small Complexity
entry:
@Article{Akleylek:2012:MRR,
  author =       "Sedat Akleylek and Ferruh Ozbudak",
  title =        "Modified Redundant Representation for Designing
                 Arithmetic Circuits with Small Complexity",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "3",
  pages =        "427--432",
  month =        mar,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2011.29",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Feb 3 07:35:03 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Al-Mohy:2012:MAB
author: Awad H. Al-Mohy
title: A more accurate Briggs method for the logarithm
journal: j-NUMER-ALGORITHMS
volume: 59
pages: ??--??
year: 2012
CODEN: NUALEG
DOI: https://doi.org/10.1007/s11075-011-9496-z
ISSN: 1017-1398 (print), 1572-9265 (electronic) OR 10171398 (print), 15729265 (electronic)
ISSNL: 1017-1398 OR 10171398
bibdate: Wed Nov 30 06:36:53 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.11.30 06:36:53 ???
URL: http://www.springerlink.com/content/4110609h521kg66m/
fjournal: Numerical Algorithms
keywords: Briggs' method; Briggs' tables; Inverse scaling and squaring method; Logarithm function
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11075
rawauthor: Awad H. Al-Mohy
rawtitle: A more accurate {Briggs} method for the logarithm
abstract:
A new approach for computing an expression of the form $ a^1 / 2^k - 1 $ is presented that avoids the danger of subtractive cancellation in floating point arithmetic, where $a$ is a complex number not belonging to the closed negative real axis and $k$ is a nonnegative integer. We also derive a condition number for the problem. The algorithm therefore allows highly accurate numerical calculation of $ log (a) $ using Briggs' method.

rawabstract:
A new approach for computing an expression of the form $ a^{1 / 2^k} - 1 $ is presented that avoids the danger of subtractive cancellation in floating point arithmetic, where $a$ is a complex number not belonging to the closed negative real axis and $k$ is a nonnegative integer. We also derive a condition number for the problem. The algorithm therefore allows highly accurate numerical calculation of $ \log (a) $ using Briggs' method.

entry:
@Article{Al-Mohy:2012:MAB,
  author =       "Awad H. Al-Mohy",
  title =        "A more accurate {Briggs} method for the logarithm",
  journal =      j-NUMER-ALGORITHMS,
  volume =       "59",
  number =       "??",
  pages =        "??--??",
  month =        "????",
  year =         "2012",
  CODEN =        "NUALEG",
  DOI =          "https://doi.org/10.1007/s11075-011-9496-z",
  ISSN =         "1017-1398 (print), 1572-9265 (electronic)",
  ISSN-L =       "1017-1398",
  bibdate =      "Wed Nov 30 06:36:53 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/content/4110609h521kg66m/",
  abstract =     "A new approach for computing an expression of the form
                 $ a^{1 / 2^k} - 1 $ is presented that avoids the danger
                 of subtractive cancellation in floating point
                 arithmetic, where $a$ is a complex number not belonging
                 to the closed negative real axis and $k$ is a
                 nonnegative integer. We also derive a condition number
                 for the problem. The algorithm therefore allows highly
                 accurate numerical calculation of $ \log (a) $ using
                 Briggs' method.",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerical Algorithms",
  journal-URL =  "http://link.springer.com/journal/11075",
  keywords =     "Briggs' method; Briggs' tables; Inverse scaling and
                 squaring method; Logarithm function",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2012:FIS
author: Anonymous
title: Fast inverse square root
pages: ??--??
day: 20
month: mar
monthnumber: 3
year: 2012
bibdate: Mon Apr 02 17:03:18 2012
bibtimestamp: 2012.04.02 17:03:18 ???
URL: http://en.wikipedia.org/wiki/Fast_inverse_square_root
acknowledgement: ack-nhfb
howpublished: Wikipedia article.
rawauthor: Anonymous
rawtitle: Fast inverse square root
note:
This article describes an algorithm for the inverse square root. The only novel feature is use of two IEEE-754 specific magic constants for 32-bit and 64-bit binary arithmetic that allow obtaining fast starting estimates for Newton--Raphson iterations by manipulating the floating-point representations as integers. The code fails to handle signed zero, Infinity, and NaN arguments, uses too few iterations, and does not adjust for rounding errors to obtain correctly-rounded results. See cite Blinn:1997:JBC.

rawnote:
This article describes an algorithm for the inverse square root. The only novel feature is use of two IEEE-754 specific magic constants for 32-bit and 64-bit binary arithmetic that allow obtaining fast starting estimates for Newton--Raphson iterations by manipulating the floating-point representations as integers. The code fails to handle signed zero, Infinity, and NaN arguments, uses too few iterations, and does not adjust for rounding errors to obtain correctly-rounded results. See \cite{Blinn:1997:JBC}.

entry:
@Misc{Anonymous:2012:FIS,
  author =       "Anonymous",
  title =        "Fast inverse square root",
  howpublished = "Wikipedia article.",
  day =          "20",
  month =        mar,
  year =         "2012",
  bibdate =      "Mon Apr 02 17:03:18 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "This article describes an algorithm for the inverse
                 square root. The only novel feature is use of two
                 IEEE-754 specific magic constants for 32-bit and 64-bit
                 binary arithmetic that allow obtaining fast starting
                 estimates for Newton--Raphson iterations by
                 manipulating the floating-point representations as
                 integers. The code fails to handle signed zero,
                 Infinity, and NaN arguments, uses too few iterations,
                 and does not adjust for rounding errors to obtain
                 correctly-rounded results. See \cite{Blinn:1997:JBC}.",
  URL =          "http://en.wikipedia.org/wiki/Fast_inverse_square_root",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Antao:2012:RBE
author: Samuel Antao and Jean-Claude Bajard and Leonel Sousa
title: RNS-Based Elliptic Curve Point Multiplication for Massive Parallel Architectures
journal: j-COMP-J
volume: 55
number: 5
pages: 629--647
month: may
monthnumber: 5
year: 2012
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/bxr119
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Wed May 2 11:34:42 MDT 2012
bibtimestamp: 2012.05.02 11:34:42 MDT
URL: http://comjnl.oxfordjournals.org/content/55/5/629.full.pdf+html
fjournal: Computer Journal
keywords: Residue Number System (RNS)
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
onlinedate: November 30, 2011
rawauthor: Samuel Ant{\~a}o and Jean-Claude Bajard and Leonel Sousa
rawtitle: {RNS}-Based Elliptic Curve Point Multiplication for Massive Parallel Architectures
bibsource:
http://comjnl.oxfordjournals.org/content/55/5.toc; https://www.math.utah.edu/pub/tex/bib/compj2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Antao:2012:RBE,
  author =       "Samuel Ant{\~a}o and Jean-Claude Bajard and Leonel
                 Sousa",
  title =        "{RNS}-Based Elliptic Curve Point Multiplication for
                 Massive Parallel Architectures",
  journal =      j-COMP-J,
  volume =       "55",
  number =       "5",
  pages =        "629--647",
  month =        may,
  year =         "2012",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/bxr119",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Wed May 2 11:34:42 MDT 2012",
  bibsource =    "http://comjnl.oxfordjournals.org/content/55/5.toc;
                 https://www.math.utah.edu/pub/tex/bib/compj2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://comjnl.oxfordjournals.org/content/55/5/629.full.pdf+html",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "Residue Number System (RNS)",
  onlinedate =   "November 30, 2011",
}


bibtype: article
filename: fparith.bib
label: Antelo:2012:GEI
author: Elisardo Antelo and David Hough and Paolo Ienne
title: Guest Editors' Introduction: Special Section on Computer Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 8
pages: 1057--1058
month: aug
monthnumber: 8
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2012.153
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 27 08:30:49 2012
bibtimestamp: 2012.07.27 08:30:49 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Elisardo Antelo and David Hough and Paolo Ienne
rawtitle: {Guest Editors}' Introduction: Special Section on Computer Arithmetic
entry:
@Article{Antelo:2012:GEI,
  author =       "Elisardo Antelo and David Hough and Paolo Ienne",
  title =        "{Guest Editors}' Introduction: Special Section on
                 Computer Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "8",
  pages =        "1057--1058",
  month =        aug,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2012.153",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 27 08:30:49 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: book
filename: fparith.bib
label: Antelo:2012:IIFa
author: Elisardo Antelo
title: Industrial Implementations of Floating-Point Units: Vol. 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 103 (est.)
year: 2012
bibdate: Thu Dec 06 11:34:04 2012
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2012.12.06 11:34:04 ???
note: Product ID ES0000033.
acknowledgement: ack-nhfb
rawauthor: Elisardo Antelo
rawnote: Product ID ES0000033.
rawtitle: Industrial Implementations of Floating-Point Units: Vol. 1
TOC:
Editor's Introduction Related Videos P6 Binary Floating-Point Unit / Son Dao Trong, Martin Schmookler, Eric M. Schwarz, and Michael Kroener FPU Implementations with Denormalized Numbers / Eric M. Schwarz, Martin Schmookler, and Son Dao Trong 1-GHz HAL SPARC64TM Dual Floating Point Unit with RAS Features / Ajay Naini, Atul Dhablania, Warren James, and Debjit Das Sarma Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support / Dimitri Tan, Carl E. Lemonds, and Michael J. Schulte The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor / Silvia M. Mueller, Christian Jacobi, Hwa-Joon Oh, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, and Sang H. Dhong A High-Performance SIMD Floating Point Unit for BlueGene/L: Architecture, Compilation, and Algorithm Design / Leonardo Bachega, Siddhartha Chatterjee, Kenneth A. Dockser, John A. Gunnels, Manish Gupta, Fred G. Gustavson, Christopher A. Lapkowski, Gary K. Liu, Mark P. Mendell, Charles D. Wait, and T.J. Chris Ward Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell / Neil Burgess and Chris N. Hinds Correctness Proofs Outline for Newton--Raphson Based Floating-Point Divide and Square Root Algorithms / Marius A. Cornea-Hasegan, Roger A. Golliver, and Peter Markstein Recommended Resources About the Editor

rawTOC:
Editor's Introduction \\ Related Videos \\ P6 Binary Floating-Point Unit / Son Dao Trong, Martin Schmookler, Eric M. Schwarz, and Michael Kroener \\ FPU Implementations with Denormalized Numbers / Eric M. Schwarz, Martin Schmookler, and Son Dao Trong \\ 1-GHz HAL SPARC64{\TM} Dual Floating Point Unit with RAS Features / Ajay Naini, Atul Dhablania, Warren James, and Debjit Das Sarma \\ Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support / Dimitri Tan, Carl E. Lemonds, and Michael J. Schulte \\ The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor / Silvia M. Mueller, Christian Jacobi, Hwa-Joon Oh, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, and Sang H. Dhong \\ A High-Performance SIMD Floating Point Unit for BlueGene/L: Architecture, Compilation, and Algorithm Design / Leonardo Bachega, Siddhartha Chatterjee, Kenneth A. Dockser, John A. Gunnels, Manish Gupta, Fred G. Gustavson, Christopher A. Lapkowski, Gary K. Liu, Mark P. Mendell, Charles D. Wait, and T.J. Chris Ward \\ Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell / Neil Burgess and Chris N. Hinds \\ Correctness Proofs Outline for Newton--Raphson Based Floating-Point Divide and Square Root Algorithms / Marius A. Cornea-Hasegan, Roger A. Golliver, and Peter Markstein \\ Recommended Resources \\ About the Editor

entry:
@Book{Antelo:2012:IIFa,
  author =       "Elisardo Antelo",
  title =        "Industrial Implementations of Floating-Point Units:
                 Vol. 1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "103 (est.)",
  year =         "2012",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Thu Dec 06 11:34:04 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Product ID ES0000033.",
  acknowledgement = ack-nhfb,
  tableofcontents = "Editor's Introduction \\
                 Related Videos \\
                 P6 Binary Floating-Point Unit / Son Dao Trong, Martin
                 Schmookler, Eric M. Schwarz, and Michael Kroener \\
                 FPU Implementations with Denormalized Numbers / Eric M.
                 Schwarz, Martin Schmookler, and Son Dao Trong \\
                 1-GHz HAL SPARC64{\TM} Dual Floating Point Unit with
                 RAS Features / Ajay Naini, Atul Dhablania, Warren
                 James, and Debjit Das Sarma \\
                 Low-Power Multiple-Precision Iterative Floating-Point
                 Multiplier with SIMD Support / Dimitri Tan, Carl E.
                 Lemonds, and Michael J. Schulte \\
                 The Vector Floating-Point Unit in a Synergistic
                 Processor Element of a CELL Processor / Silvia M.
                 Mueller, Christian Jacobi, Hwa-Joon Oh, Kevin D. Tran,
                 Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa,
                 Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi
                 Machida, and Sang H. Dhong \\
                 A High-Performance SIMD Floating Point Unit for
                 BlueGene/L: Architecture, Compilation, and Algorithm
                 Design / Leonardo Bachega, Siddhartha Chatterjee,
                 Kenneth A. Dockser, John A. Gunnels, Manish Gupta, Fred
                 G. Gustavson, Christopher A. Lapkowski, Gary K. Liu,
                 Mark P. Mendell, Charles D. Wait, and T.J. Chris Ward
                 \\
                 Design of the ARM VFP11 Divide and Square Root
                 Synthesisable Macrocell / Neil Burgess and Chris N.
                 Hinds \\
                 Correctness Proofs Outline for Newton--Raphson Based
                 Floating-Point Divide and Square Root Algorithms /
                 Marius A. Cornea-Hasegan, Roger A. Golliver, and Peter
                 Markstein \\
                 Recommended Resources \\
                 About the Editor",
}


bibtype: book
filename: fparith.bib
label: Antelo:2012:IIFb
author: Elisardo Antelo
title: Industrial Implementations of Floating-Point Units: Vol. 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 79 (est.)
year: 2012
bibdate: Thu Dec 06 11:34:04 2012
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2012.12.06 11:34:04 ???
note: Product ID ES0000034.
acknowledgement: ack-nhfb
rawauthor: Elisardo Antelo
rawnote: Product ID ES0000034.
rawtitle: Industrial Implementations of Floating-Point Units: Vol. 2
TOC:
Table of Contents Editor Bio Editor's Introduction Related Videos A High-Performance Area-Efficient Multifunction Interpolator / Stuart F. Oberman and Michael Y. Siu New Algorithms for Improved Transcendental Functions on IA-64 / Shane Story and Ping Tak Peter Tang Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders / Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Dao, Sanu Mathew, and Ram Krishnamurthy Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units / Jochen Preiss, Maarten Boersma, and Silvia Melitta Mueller Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power / Zichu Qi, Qi Guo, Ge Zhang, Xiangku Li, and Weiwu Hu Decimal Floating-Point: Algorism for Computers / Michael F. Cowlishaw A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format / Marius Cornea, John Harrison, Cristina Anderson, Ping Tak Peter Tang, Eric Schneider, and Evgeny Gvozdev Recommended Resources About the Editor

rawTOC:
Table of Contents \\ Editor Bio \\ Editor's Introduction \\ Related Videos \\ A High-Performance Area-Efficient Multifunction Interpolator / Stuart F. Oberman and Michael Y. Siu \\ New Algorithms for Improved Transcendental Functions on IA-64 / Shane Story and Ping Tak Peter Tang \\ Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders / Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Dao, Sanu Mathew, and Ram Krishnamurthy \\ Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units / Jochen Preiss, Maarten Boersma, and Silvia Melitta Mueller \\ Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power / Zichu Qi, Qi Guo, Ge Zhang, Xiangku Li, and Weiwu Hu \\ Decimal Floating-Point: Algorism for Computers / Michael F. Cowlishaw \\ A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format / Marius Cornea, John Harrison, Cristina Anderson, Ping Tak Peter Tang, Eric Schneider, and Evgeny Gvozdev \\ Recommended Resources \\ About the Editor

entry:
@Book{Antelo:2012:IIFb,
  author =       "Elisardo Antelo",
  title =        "Industrial Implementations of Floating-Point Units:
                 Vol. 2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "79 (est.)",
  year =         "2012",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Thu Dec 06 11:34:04 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Product ID ES0000034.",
  acknowledgement = ack-nhfb,
  tableofcontents = "Table of Contents \\
                 Editor Bio \\
                 Editor's Introduction \\
                 Related Videos \\
                 A High-Performance Area-Efficient Multifunction
                 Interpolator / Stuart F. Oberman and Michael Y. Siu \\
                 New Algorithms for Improved Transcendental Functions on
                 IA-64 / Shane Story and Ping Tak Peter Tang \\
                 Energy-Delay Estimation Technique for High-Performance
                 Microprocessor VLSI Adders / Vojin G. Oklobdzija, Bart
                 R. Zeydel, Hoang Dao, Sanu Mathew, and Ram
                 Krishnamurthy \\
                 Advanced Clockgating Schemes for
                 Fused-Multiply-Add-Type Floating-Point Units / Jochen
                 Preiss, Maarten Boersma, and Silvia Melitta Mueller \\
                 Design of Low-Cost High-Performance Floating-Point
                 Fused Multiply-Add with Reduced Power / Zichu Qi, Qi
                 Guo, Ge Zhang, Xiangku Li, and Weiwu Hu \\
                 Decimal Floating-Point: Algorism for Computers /
                 Michael F. Cowlishaw \\
                 A Software Implementation of the IEEE 754R Decimal
                 Floating-Point Arithmetic Using the Binary Encoding
                 Format / Marius Cornea, John Harrison, Cristina
                 Anderson, Ping Tak Peter Tang, Eric Schneider, and
                 Evgeny Gvozdev \\
                 Recommended Resources \\
                 About the Editor",
}


bibtype: article
filename: fparith.bib
label: Aswal:2012:BFD
author: Abhilasha Aswal and M. Ganesh Perumal and G. N. Srinivasa Prasanna
title: On Basic Financial Decimal Operations on Binary Machines
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 8
pages: 1084--1096
month: aug
monthnumber: 8
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2012.89
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 27 08:30:49 2012
bibtimestamp: 2012.07.27 08:30:49 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Abhilasha Aswal and M. Ganesh Perumal and G. N. Srinivasa Prasanna
rawtitle: On Basic Financial Decimal Operations on Binary Machines
entry:
@Article{Aswal:2012:BFD,
  author =       "Abhilasha Aswal and M. Ganesh Perumal and G. N.
                 Srinivasa Prasanna",
  title =        "On Basic Financial Decimal Operations on Binary
                 Machines",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "8",
  pages =        "1084--1096",
  month =        aug,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2012.89",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 27 08:30:49 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Bailey:2012:AIS
author: David H. Bailey and Jonathan M. Borwein
title: Ancient Indian Square Roots: An Exercise in Forensic Paleo-Mathematics
journal: j-AMER-MATH-MONTHLY
volume: 119
number: 8
pages: 646--657
month: oct
monthnumber: 10
year: 2012
CODEN: AMMYAE
DOI: https://doi.org/10.4169/amer.math.monthly.119.08.646
ISSN: 0002-9890 (print), 1930-0972 (electronic) OR 00029890 (print), 19300972 (electronic)
ISSNL: 0002-9890 OR 00029890
bibdate: Thu Nov 8 07:34:21 MST 2012
bibtimestamp: 2012.11.08 07:34:21 MST
URL: http://www.jstor.org/stable/pdfplus/10.4169/amer.math.monthly.119.08.646.pdf
fjournal: American Mathematical Monthly
acknowledgement: ack-nhfb
journalURL: https://www.jstor.org/journals/00029890.htm
rawauthor: David H. Bailey and Jonathan M. Borwein
rawtitle: Ancient {Indian} Square Roots: An Exercise in Forensic Paleo-Mathematics
bibsource:
http://www.jstor.org/journals/00029890.html; http://www.jstor.org/stable/10.4169/amermathmont.119.issue-8; https://www.math.utah.edu/pub/tex/bib/amermathmonthly2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Bailey:2012:AIS,
  author =       "David H. Bailey and Jonathan M. Borwein",
  title =        "Ancient {Indian} Square Roots: An Exercise in Forensic
                 Paleo-Mathematics",
  journal =      j-AMER-MATH-MONTHLY,
  volume =       "119",
  number =       "8",
  pages =        "646--657",
  month =        oct,
  year =         "2012",
  CODEN =        "AMMYAE",
  DOI =          "https://doi.org/10.4169/amer.math.monthly.119.08.646",
  ISSN =         "0002-9890 (print), 1930-0972 (electronic)",
  ISSN-L =       "0002-9890",
  bibdate =      "Thu Nov 8 07:34:21 MST 2012",
  bibsource =    "http://www.jstor.org/journals/00029890.html;
                 http://www.jstor.org/stable/10.4169/amermathmont.119.issue-8;
                 https://www.math.utah.edu/pub/tex/bib/amermathmonthly2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.jstor.org/stable/pdfplus/10.4169/amer.math.monthly.119.08.646.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "American Mathematical Monthly",
  journal-URL =  "https://www.jstor.org/journals/00029890.htm",
}


bibtype: article
filename: fparith.bib
label: Bailey:2012:HPC
author: David H. Bailey and Roberto Barrio and Jonathan M. Borwein
title: High-precision computation: Mathematical physics and dynamics
journal: j-APPL-MATH-COMP
volume: 218
number: 20
pages: 10106--10121
day: 15
month: jun
monthnumber: 6
year: 2012
CODEN: AMHCBQ
DOI: https://doi.org/10.1016/j.amc.2012.03.087
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
MRclass: 65Y04 (68M07)
MRnumber: 2921767
bibdate: Thu Aug 11 10:27:38 2016
bibtimestamp: 2016.08.11 10:27:38 ???
fjournal: Applied Mathematics and Computation
keywords: Dynamical systems; Experimental mathematics; High-precision computation; Mathematical physics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003/
rawauthor: David H. Bailey and Roberto Barrio and Jonathan M. Borwein
rawtitle: High-precision computation: Mathematical physics and dynamics
ORCID: Borwein, Jonathan/0000-0002-1263-0646
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/b/borwein-jonathan-m.bib; https://www.math.utah.edu/pub/tex/bib/applmathcomput2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://docserver.carma.newcastle.edu.au/775/; http://www.sciencedirect.com/science/article/pii/S0096300312003505

abstract:
At the present time, IEEE 64-bit floating-point arithmetic is sufficiently accurate for most scientific applications. However, for a rapidly growing body of important scientific computing applications, a higher level of numeric precision is required. Such calculations are facilitated by high-precision software packages that include high-level language translation modules to minimize the conversion effort. This paper presents an overview of recent applications of these techniques and provides some analysis of their numerical requirements. We conclude that high-precision arithmetic facilities are now an indispensable component of a modern large-scale scientific computing environment.

rawabstract:
At the present time, IEEE 64-bit floating-point arithmetic is sufficiently accurate for most scientific applications. However, for a rapidly growing body of important scientific computing applications, a higher level of numeric precision is required. Such calculations are facilitated by high-precision software packages that include high-level language translation modules to minimize the conversion effort. This paper presents an overview of recent applications of these techniques and provides some analysis of their numerical requirements. We conclude that high-precision arithmetic facilities are now an indispensable component of a modern large-scale scientific computing environment.

entry:
@Article{Bailey:2012:HPC,
  author =       "David H. Bailey and Roberto Barrio and Jonathan M.
                 Borwein",
  title =        "High-precision computation: Mathematical physics and
                 dynamics",
  journal =      j-APPL-MATH-COMP,
  volume =       "218",
  number =       "20",
  pages =        "10106--10121",
  day =          "15",
  month =        jun,
  year =         "2012",
  CODEN =        "AMHCBQ",
  DOI =          "https://doi.org/10.1016/j.amc.2012.03.087",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  MRclass =      "65Y04 (68M07)",
  MRnumber =     "2921767",
  bibdate =      "Thu Aug 11 10:27:38 2016",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/b/borwein-jonathan-m.bib;
                 https://www.math.utah.edu/pub/tex/bib/applmathcomput2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://docserver.carma.newcastle.edu.au/775/;
                 http://www.sciencedirect.com/science/article/pii/S0096300312003505",
  abstract =     "At the present time, IEEE 64-bit floating-point
                 arithmetic is sufficiently accurate for most scientific
                 applications. However, for a rapidly growing body of
                 important scientific computing applications, a higher
                 level of numeric precision is required. Such
                 calculations are facilitated by high-precision software
                 packages that include high-level language translation
                 modules to minimize the conversion effort. This paper
                 presents an overview of recent applications of these
                 techniques and provides some analysis of their
                 numerical requirements. We conclude that high-precision
                 arithmetic facilities are now an indispensable
                 component of a modern large-scale scientific computing
                 environment.",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003/",
  keywords =     "Dynamical systems; Experimental mathematics;
                 High-precision computation; Mathematical physics",
  ORCID-numbers = "Borwein, Jonathan/0000-0002-1263-0646",
  researcherid-numbers = "Barrio, Roberto/L-4983-2014",
}


bibtype: article
filename: fparith.bib
label: Baudin:2012:RCD
author: Michael Baudin and Robert L. Smith
title: A Robust Complex Division in Scilab
journal: CoRR
volume: abs/1210.4539
pages: 10106--10121
year: 2012
bibdate: Tue Apr 16 08:18:25 2013
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcw.bib
bibtimestamp: 2013.04.16 08:18:25 ???
URL: http://arxiv.org/abs/1210.4539
acknowledgement: ack-nhfb
rawauthor: Michael Baudin and Robert L. Smith
rawtitle: A Robust Complex Division in {Scilab}
abstract:
The most widely used algorithm for floating point complex division, known as Smith's method, may fail more often than expected. This document presents two improved complex division algorithms. We present a proof of the robustness of the first improved algorithm. Numerical simulations show that this algorithm performs well in practice and is significantly more robust than other known implementations. By combining additional scaling methods with this first algorithm, we were able to create a second algorithm, which rarely fails.

rawabstract:
The most widely used algorithm for floating point complex division, known as Smith's method, may fail more often than expected. This document presents two improved complex division algorithms. We present a proof of the robustness of the first improved algorithm. Numerical simulations show that this algorithm performs well in practice and is significantly more robust than other known implementations. By combining additional scaling methods with this first algorithm, we were able to create a second algorithm, which rarely fails.

entry:
@Article{Baudin:2012:RCD,
  author =       "Michael Baudin and Robert L. Smith",
  title =        "A Robust Complex Division in {Scilab}",
  journal =      "CoRR",
  volume =       "abs/1210.4539",
  year =         "2012",
  bibdate =      "Tue Apr 16 08:18:25 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcw.bib",
  URL =          "http://arxiv.org/abs/1210.4539",
  abstract =     "The most widely used algorithm for floating point
                 complex division, known as Smith's method, may fail
                 more often than expected. This document presents two
                 improved complex division algorithms. We present a
                 proof of the robustness of the first improved
                 algorithm. Numerical simulations show that this
                 algorithm performs well in practice and is
                 significantly more robust than other known
                 implementations. By combining additional scaling
                 methods with this first algorithm, we were able to
                 create a second algorithm, which rarely fails.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Benz:2012:DPA
author: Florian Benz and Andreas Hildebrandt and Sebastian Hack
title: A dynamic program analysis to find floating-point accuracy problems
journal: j-SIGPLAN
volume: 47
number: 6
pages: 453--462
month: jun
monthnumber: 6
year: 2012
CODEN: SINODQ
DOI: https://doi.org/10.1145/2345156.2254118
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Mon Aug 6 16:31:49 MDT 2012
bibtimestamp: 2012.08.06 16:31:49 MDT
note: PLDI '12 proceedings.
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Florian Benz and Andreas Hildebrandt and Sebastian Hack
rawnote: PLDI '12 proceedings.
rawtitle: A dynamic program analysis to find floating-point accuracy problems
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib

abstract:
Programs using floating-point arithmetic are prone to accuracy problems caused by rounding and catastrophic cancellation. These phenomena provoke bugs that are notoriously hard to track down: the program does not necessarily crash and the results are not necessarily obviously wrong, but often subtly inaccurate. Further use of these values can lead to catastrophic errors. In this paper, we present a dynamic program analysis that supports the programmer in finding accuracy problems. Our analysis uses binary translation to perform every floating-point computation side by side in higher precision. Furthermore, we use a lightweight slicing approach to track the evolution of errors. We evaluate our analysis by demonstrating that it catches well-known floating-point accuracy problems and by analyzing the Spec CFP2006 floating-point benchmark. In the latter, we show how our tool tracks down a catastrophic cancellation that causes a complete loss of accuracy leading to a meaningless program result. Finally, we apply our program to a complex, real-world bioinformatics application in which our program detected a serious cancellation. Correcting the instability led not only to improved quality of the result, but also to an improvement of the program's run time.In this paper, we present a dynamic program analysis that supports the programmer in finding accuracy problems. Our analysis uses binary translation to perform every floating-point computation side by side in higher precision. Furthermore, we use a lightweight slicing approach to track the evolution of errors. We evaluate our analysis by demonstrating that it catches well-known floating-point accuracy problems and by analyzing the SpecfiCFP2006 floating-point benchmark. In the latter, we show how our tool tracks down a catastrophic cancellation that causes a complete loss of accuracy leading to a meaningless program result. Finally, we apply our program to a complex, real-world bioinformatics application in which our program detected a serious cancellation. Correcting the instability led not only to improved quality of the result, but also to an improvement of the program's run time.

rawabstract:
Programs using floating-point arithmetic are prone to accuracy problems caused by rounding and catastrophic cancellation. These phenomena provoke bugs that are notoriously hard to track down: the program does not necessarily crash and the results are not necessarily obviously wrong, but often subtly inaccurate. Further use of these values can lead to catastrophic errors. In this paper, we present a dynamic program analysis that supports the programmer in finding accuracy problems. Our analysis uses binary translation to perform every floating-point computation side by side in higher precision. Furthermore, we use a lightweight slicing approach to track the evolution of errors. We evaluate our analysis by demonstrating that it catches well-known floating-point accuracy problems and by analyzing the Spec CFP2006 floating-point benchmark. In the latter, we show how our tool tracks down a catastrophic cancellation that causes a complete loss of accuracy leading to a meaningless program result. Finally, we apply our program to a complex, real-world bioinformatics application in which our program detected a serious cancellation. Correcting the instability led not only to improved quality of the result, but also to an improvement of the program's run time.In this paper, we present a dynamic program analysis that supports the programmer in finding accuracy problems. Our analysis uses binary translation to perform every floating-point computation side by side in higher precision. Furthermore, we use a lightweight slicing approach to track the evolution of errors. We evaluate our analysis by demonstrating that it catches well-known floating-point accuracy problems and by analyzing the SpecfiCFP2006 floating-point benchmark. In the latter, we show how our tool tracks down a catastrophic cancellation that causes a complete loss of accuracy leading to a meaningless program result. Finally, we apply our program to a complex, real-world bioinformatics application in which our program detected a serious cancellation. Correcting the instability led not only to improved quality of the result, but also to an improvement of the program's run time.

entry:
@Article{Benz:2012:DPA,
  author =       "Florian Benz and Andreas Hildebrandt and Sebastian
                 Hack",
  title =        "A dynamic program analysis to find floating-point
                 accuracy problems",
  journal =      j-SIGPLAN,
  volume =       "47",
  number =       "6",
  pages =        "453--462",
  month =        jun,
  year =         "2012",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/2345156.2254118",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Mon Aug 6 16:31:49 MDT 2012",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  note =         "PLDI '12 proceedings.",
  abstract =     "Programs using floating-point arithmetic are prone to
                 accuracy problems caused by rounding and catastrophic
                 cancellation. These phenomena provoke bugs that are
                 notoriously hard to track down: the program does not
                 necessarily crash and the results are not necessarily
                 obviously wrong, but often subtly inaccurate. Further
                 use of these values can lead to catastrophic errors. In
                 this paper, we present a dynamic program analysis that
                 supports the programmer in finding accuracy problems.
                 Our analysis uses binary translation to perform every
                 floating-point computation side by side in higher
                 precision. Furthermore, we use a lightweight slicing
                 approach to track the evolution of errors. We evaluate
                 our analysis by demonstrating that it catches
                 well-known floating-point accuracy problems and by
                 analyzing the Spec CFP2006 floating-point benchmark. In
                 the latter, we show how our tool tracks down a
                 catastrophic cancellation that causes a complete loss
                 of accuracy leading to a meaningless program result.
                 Finally, we apply our program to a complex, real-world
                 bioinformatics application in which our program
                 detected a serious cancellation. Correcting the
                 instability led not only to improved quality of the
                 result, but also to an improvement of the program's run
                 time.In this paper, we present a dynamic program
                 analysis that supports the programmer in finding
                 accuracy problems. Our analysis uses binary translation
                 to perform every floating-point computation side by
                 side in higher precision. Furthermore, we use a
                 lightweight slicing approach to track the evolution of
                 errors. We evaluate our analysis by demonstrating that
                 it catches well-known floating-point accuracy problems
                 and by analyzing the SpecfiCFP2006 floating-point
                 benchmark. In the latter, we show how our tool tracks
                 down a catastrophic cancellation that causes a complete
                 loss of accuracy leading to a meaningless program
                 result. Finally, we apply our program to a complex,
                 real-world bioinformatics application in which our
                 program detected a serious cancellation. Correcting the
                 instability led not only to improved quality of the
                 result, but also to an improvement of the program's run
                 time.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
}


bibtype: inproceedings
filename: fparith.bib
label: Bohlender:2012:CFE
author: G. Bohlender and U. Kulisch
title: Comments on fast and exact accumulation of products
crossref: Jonasson:2012:APSb
pages: 148--156
year: 2012
DOI: https://doi.org/10.1007/978-3-642-28145-7_15
bibdate: Sat Oct 31 07:09:45 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.10.31 07:09:45 ???
acknowledgement: ack-nhfb
rawauthor: G. Bohlender and U. Kulisch
rawtitle: Comments on fast and exact accumulation of products
entry:
@InProceedings{Bohlender:2012:CFE,
  author =       "G. Bohlender and U. Kulisch",
  title =        "Comments on fast and exact accumulation of products",
  crossref =     "Jonasson:2012:APSb",
  pages =        "148--156",
  year =         "2012",
  DOI =          "https://doi.org/10.1007/978-3-642-28145-7_15",
  bibdate =      "Sat Oct 31 07:09:45 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Boldo:2012:AOP
author: Sylvie Boldo and Guillaume Melquiond
title: Arithmetique des ordinateurs et preuves formelles. (French) [Computer arithmetic and formal proofs]
institution: Ecole des Jeunes Chercheurs en Informatique Mathematique
pages: 31
day: 22
month: mar
monthnumber: 3
year: 2012
bibdate: Fri Sep 22 17:09:39 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 17:09:39 ???
URL: https://inria.hal.science/hal-00755333/file/main.pdf
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo and Guillaume Melquiond
rawtitle:
Arithm{\'e}tique des ordinateurs et preuves formelles. ({French}) [{Computer} arithmetic and formal proofs]

entry:
@TechReport{Boldo:2012:AOP,
  author =       "Sylvie Boldo and Guillaume Melquiond",
  title =        "Arithm{\'e}tique des ordinateurs et preuves formelles.
                 ({French}) [{Computer} arithmetic and formal proofs]",
  institution =  "{\'E}cole des Jeunes Chercheurs en Informatique
                 Math{\'e}matique",
  address =      "????",
  pages =        "31",
  day =          "22",
  month =        mar,
  year =         "2012",
  bibdate =      "Fri Sep 22 17:09:39 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://inria.hal.science/hal-00755333/file/main.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Brisebarre:2012:MPK
author: Nicolas Brisebarre and Milo D. Ercegovac and Jean-Michel Muller
editor: IEEE
title: $ (M, p, k) $-Friendly Points: a Table-Based Method for Trigonometric Function Evaluation
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 46--52
year: 2012
DOI: https://doi.org/10.1109/ASAP.2012.17
ISBN: 0-7695-4768-0 OR 0769547680
ISBN13: 978-0-7695-4768-8 OR 9780769547688
ISSN: 1063-6862 OR 10636862
ISSNL: 1063-6862 OR 10636862
bibdate: Fri Sep 29 10:49:22 2023
bibtimestamp: 2023.09.29 10:49:22 ???
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Milo D. Ercegovac and Jean-Michel Muller
raweditor: {IEEE}
rawtitle: {$ (M, p, k) $}-Friendly Points: a Table-Based Method for Trigonometric Function Evaluation
booktitle:
2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, 9--11 July 2012. Delft, The Netherlands

rawbooktitle:
{2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, 9--11 July 2012. Delft, The Netherlands}

entry:
@InProceedings{Brisebarre:2012:MPK,
  author =       "Nicolas Brisebarre and Milo D. Ercegovac and
                 Jean-Michel Muller",
  editor =       "{IEEE}",
  booktitle =    "{2012 IEEE 23rd International Conference on
                 Application-Specific Systems, Architectures and
                 Processors, 9--11 July 2012. Delft, The Netherlands}",
  title =        "{$ (M, p, k) $}-Friendly Points: a Table-Based Method
                 for Trigonometric Function Evaluation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "46--52",
  year =         "2012",
  DOI =          "https://doi.org/10.1109/ASAP.2012.17",
  ISBN =         "0-7695-4768-0",
  ISBN-13 =      "978-0-7695-4768-8",
  ISSN =         "1063-6862",
  ISSN-L =       "1063-6862",
  bibdate =      "Fri Sep 29 10:49:22 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Bruintjes:2012:SLA
title: Sabrewing: a lightweight architecture for combined floating-point and integer arithmetic
journal: j-TACO
volume: 8
number: 4
pages: 41:1--41:??
month: jan
monthnumber: 1
year: 2012
DOI: https://doi.org/10.1145/2086696.2086720
ISSN: 1544-3566 (print), 1544-3973 (electronic) OR 15443566 (print), 15443973 (electronic)
ISSNL: 1544-3566 OR 15443566
bibdate: Sat Jan 21 07:49:49 MST 2012
bibtimestamp: 2012.01.21 07:49:49 MST
fjournal: ACM Transactions on Architecture and Code Optimization (TACO)
acknowledgement: ack-nhfb
articleno: 41
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J924
rawtitle: {Sabrewing}: a lightweight architecture for combined floating-point and integer arithmetic
author:
Tom M. Bruintjes and Karel H. G. Walters and Sabih H. Gerez and Bert Molenkamp and Gerard J. M. Smit

bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/taco.bib

abstract:
In spite of the fact that floating-point arithmetic is costly in terms of silicon area, the joint design of hardware for floating-point and integer arithmetic is seldom considered. While components like multipliers and adders can potentially be shared, floating-point and integer units in contemporary processors are practically disjoint. This work presents a new architecture which tightly integrates floating-point and integer arithmetic in a single datapath. It is mainly intended for use in low-power embedded digital signal processors and therefore the following design constraints were important: limited use of pipelining for the convenience of the compiler; maintaining compatibility with existing technology; minimal area and power consumption for applicability in embedded systems.

rawabstract:
In spite of the fact that floating-point arithmetic is costly in terms of silicon area, the joint design of hardware for floating-point and integer arithmetic is seldom considered. While components like multipliers and adders can potentially be shared, floating-point and integer units in contemporary processors are practically disjoint. This work presents a new architecture which tightly integrates floating-point and integer arithmetic in a single datapath. It is mainly intended for use in low-power embedded digital signal processors and therefore the following design constraints were important: limited use of pipelining for the convenience of the compiler; maintaining compatibility with existing technology; minimal area and power consumption for applicability in embedded systems.

rawauthor:
Tom M. Bruintjes and Karel H. G. Walters and Sabih H. Gerez and Bert Molenkamp and Gerard J. M. Smit

entry:
@Article{Bruintjes:2012:SLA,
  author =       "Tom M. Bruintjes and Karel H. G. Walters and Sabih H.
                 Gerez and Bert Molenkamp and Gerard J. M. Smit",
  title =        "{Sabrewing}: a lightweight architecture for combined
                 floating-point and integer arithmetic",
  journal =      j-TACO,
  volume =       "8",
  number =       "4",
  pages =        "41:1--41:??",
  month =        jan,
  year =         "2012",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/2086696.2086720",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Sat Jan 21 07:49:49 MST 2012",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  abstract =     "In spite of the fact that floating-point arithmetic is
                 costly in terms of silicon area, the joint design of
                 hardware for floating-point and integer arithmetic is
                 seldom considered. While components like multipliers
                 and adders can potentially be shared, floating-point
                 and integer units in contemporary processors are
                 practically disjoint. This work presents a new
                 architecture which tightly integrates floating-point
                 and integer arithmetic in a single datapath. It is
                 mainly intended for use in low-power embedded digital
                 signal processors and therefore the following design
                 constraints were important: limited use of pipelining
                 for the convenience of the compiler; maintaining
                 compatibility with existing technology; minimal area
                 and power consumption for applicability in embedded
                 systems.",
  acknowledgement = ack-nhfb,
  articleno =    "41",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J924",
}


bibtype: article
filename: fparith.bib
label: Chen:2012:IDF
author: Dongdong Chen and Liu Han and Younhee Choi and Seok-Bum Ko
title: Improved Decimal Floating-Point Logarithmic Converter Based on Selection by Rounding
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 5
pages: 607--621
month: may
monthnumber: 5
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2011.43
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Apr 6 18:50:40 2012
bibtimestamp: 2012.04.06 18:50:40 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Dongdong Chen and Liu Han and Younhee Choi and Seok-Bum Ko
rawtitle: Improved Decimal Floating-Point Logarithmic Converter Based on Selection by Rounding
abstract:
This paper presents the algorithm and architecture of the decimal floating-point (DFP) logarithmic converter, based on the digit-recurrence algorithm with selection by rounding. The proposed approach can compute faithful DFP logarithm results for any one of the three DFP formats specified in the IEEE 754-2008 standard. In order to optimize the latency for the proposed design, we mainly integrate the following novel features: (1) using the redundant carry-save representation of the data-path; (2) reducing the number of iterations by determining the number of initial iteration; and (3) retiming and balancing the delay of the proposed architecture. The proposed architecture is synthesized with STM 90-nm standard cell library and the results show that the critical path delay and the number of clock cycles of the proposed Decimal64 logarithmic converter are 1.55 ns (34.4 FO4) and 19 respectively, and the total hardware complexity is 43572 NAND2 gates. The delay estimation results of the proposed architecture show that its latency is close to that of the binary radix-16 logarithmic converter, and that it has a significant decrease on latency compared with a recently published high performance CORDIC implementation.

rawabstract:
This paper presents the algorithm and architecture of the decimal floating-point (DFP) logarithmic converter, based on the digit-recurrence algorithm with selection by rounding. The proposed approach can compute faithful DFP logarithm results for any one of the three DFP formats specified in the IEEE 754-2008 standard. In order to optimize the latency for the proposed design, we mainly integrate the following novel features: (1) using the redundant carry-save representation of the data-path; (2) reducing the number of iterations by determining the number of initial iteration; and (3) retiming and balancing the delay of the proposed architecture. The proposed architecture is synthesized with STM 90-nm standard cell library and the results show that the critical path delay and the number of clock cycles of the proposed Decimal64 logarithmic converter are 1.55 ns (34.4 FO4) and 19 respectively, and the total hardware complexity is 43572 NAND2 gates. The delay estimation results of the proposed architecture show that its latency is close to that of the binary radix-16 logarithmic converter, and that it has a significant decrease on latency compared with a recently published high performance CORDIC implementation.

entry:
@Article{Chen:2012:IDF,
  author =       "Dongdong Chen and Liu Han and Younhee Choi and
                 Seok-Bum Ko",
  title =        "Improved Decimal Floating-Point Logarithmic Converter
                 Based on Selection by Rounding",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "5",
  pages =        "607--621",
  month =        may,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2011.43",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Apr 6 18:50:40 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  abstract =     "This paper presents the algorithm and architecture of
                 the decimal floating-point (DFP) logarithmic converter,
                 based on the digit-recurrence algorithm with selection
                 by rounding. The proposed approach can compute faithful
                 DFP logarithm results for any one of the three DFP
                 formats specified in the IEEE 754-2008 standard. In
                 order to optimize the latency for the proposed design,
                 we mainly integrate the following novel features: (1)
                 using the redundant carry-save representation of the
                 data-path; (2) reducing the number of iterations by
                 determining the number of initial iteration; and (3)
                 retiming and balancing the delay of the proposed
                 architecture. The proposed architecture is synthesized
                 with STM 90-nm standard cell library and the results
                 show that the critical path delay and the number of
                 clock cycles of the proposed Decimal64 logarithmic
                 converter are 1.55 ns (34.4 FO4) and 19 respectively,
                 and the total hardware complexity is 43572 NAND2 gates.
                 The delay estimation results of the proposed
                 architecture show that its latency is close to that of
                 the binary radix-16 logarithmic converter, and that it
                 has a significant decrease on latency compared with a
                 recently published high performance CORDIC
                 implementation.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Das:2012:AAT
author: Subrata Das and Partha Sarathi Dasgupta and Samar Sensarma
title: Arithmetic Algorithms for Ternary Number System
journal: j-LECT-NOTES-COMP-SCI
volume: 7373
pages: 111--120
year: 2012
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-31494-0_13
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Wed Dec 19 15:21:09 MST 2012
bibtimestamp: 2012.12.19 15:21:09 MST
URL: http://link.springer.com/chapter/10.1007/978-3-642-31494-0_13/
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-642-31494-0
bookURL: http://www.springerlink.com/content/978-3-642-31494-0
journalURL: http://link.springer.com/bookseries/558
rawauthor: Subrata Das and Partha Sarathi Dasgupta and Samar Sensarma
rawtitle: Arithmetic Algorithms for Ternary Number System
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs2012f.bib

entry:
@Article{Das:2012:AAT,
  author =       "Subrata Das and Partha Sarathi Dasgupta and Samar
                 Sensarma",
  title =        "Arithmetic Algorithms for Ternary Number System",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "7373",
  pages =        "111--120",
  year =         "2012",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-31494-0_13",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Wed Dec 19 15:21:09 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs2012f.bib",
  URL =          "http://link.springer.com/chapter/10.1007/978-3-642-31494-0_13/",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-642-31494-0",
  book-URL =     "http://www.springerlink.com/content/978-3-642-31494-0",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: deDinechin:2012:MRC
author: Florent de Dinechin
title: Multiplication by rational constants
journal: j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS
volume: 52
number: 2
pages: 98--102
month: feb
monthnumber: 2
year: 2012
DOI: https://doi.org/10.1109/TCSII.2011.2177706
ISSN: 1549-7747 (print), 1558-3791 (electronic) OR 15497747 (print), 15583791 (electronic)
ISSNL: 1549-7747 OR 15497747
bibdate: Sat Feb 08 09:46:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 09:46:07 ???
URL: https://ieeexplore.ieee.org/document/6126071
fjournal: IEEE Transactions on Circuits and Systems II: Express Briefs
acknowledgement: ack-nhfb
ajournal: IEEE trans. circuits syst., II Express briefs
journalURL: https://ieeexplore.ieee.org/xpl/issues?punumber=8920
rawauthor: Florent de Dinechin
rawtitle: Multiplication by rational constants
entry:
@Article{deDinechin:2012:MRC,
  author =       "Florent de Dinechin",
  title =        "Multiplication by rational constants",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "52",
  number =       "2",
  pages =        "98--102",
  month =        feb,
  year =         "2012",
  DOI =          "https://doi.org/10.1109/TCSII.2011.2177706",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Sat Feb 08 09:46:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/document/6126071",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE trans. circuits syst., II Express briefs",
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
}


bibtype: article
filename: fparith.bib
label: deDinechin:2012:TBD
author: Florent de Dinechin and Laurent-Stephane Didier
title: Table-Based Division by Small Integer Constants
journal: j-LECT-NOTES-COMP-SCI
volume: 7199
pages: 53--63
year: 2012
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-28365-9_5
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Wed Dec 19 15:26:07 MST 2012
bibtimestamp: 2012.12.19 15:26:07 MST
URL: http://link.springer.com/chapter/10.1007/978-3-642-28365-9_5/
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-642-28365-9
bookURL: http://www.springerlink.com/content/978-3-642-28365-9
journalURL: http://link.springer.com/bookseries/558
rawauthor: Florent de Dinechin and Laurent-St{\'e}phane Didier
rawtitle: Table-Based Division by Small Integer Constants
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs2012b.bib

entry:
@Article{deDinechin:2012:TBD,
  author =       "Florent de Dinechin and Laurent-St{\'e}phane Didier",
  title =        "Table-Based Division by Small Integer Constants",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "7199",
  pages =        "53--63",
  year =         "2012",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-28365-9_5",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Wed Dec 19 15:26:07 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs2012b.bib",
  URL =          "http://link.springer.com/chapter/10.1007/978-3-642-28365-9_5/",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-642-28365-9",
  book-URL =     "http://www.springerlink.com/content/978-3-642-28365-9",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: book
filename: fparith.bib
label: Deschamps:2012:GFI
author: Jean-Pierre Deschamps and Gustavo D. Sutter and Enrique Canto
title: Guide to FPGA implementation of arithmetic functions
volume: 95
publisher: pub-SV
address: pub-SV:adr
pages: xv + 469
year: 2012
DOI: https://doi.org/10.1007/978-94-007-2987-2
ISBN: 94-007-2986-3 (hardcover), 94-007-2987-1 (e-book) OR 9400729863 (hardcover), 9400729871 (ebook)
LCCN: TK7895.G36
bibdate: Wed Oct 1 10:19:58 MDT 2014
bibtimestamp: 2014.10.01 10:19:58 MDT
series: Lecture notes in electrical engineering
subject: Field programmable gate arrays; Programming; Arithmetic functions
acknowledgement: ack-nhfb
authordates: 1945--
rawauthor: Jean-Pierre Deschamps and Gustavo D. Sutter and Enrique Cant{\'o}
rawtitle: Guide to {FPGA} implementation of arithmetic functions
ISBN13:
978-94-007-2986-5 (hardcover), 978-94-007-2987-2 (e-book) OR 9789400729865 (hardcover), 9789400729872 (ebook)

bibsource:
fsz3950.oclc.org:210/WorldCat; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcw.bib

abstract:
This book is designed both for FPGA users interested in developing new, specific components --- generally for reducing execution times and IP core designers interested in extending their catalog of specific components. The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption. This is not a book on algorithms. It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others. Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download.

TOC:
Basic Building Blocks Architecture of Digital Circuits Special Topics of Data Path Synthesis Control Unit Synthesis Electronic Aspects of Digital Design EDA Tools Adders Multipliers Dividers Other Operations Decimal Operations Floating Point Arithmetic Finite-Field Arithmetic Systems on Chip Embedded Systems Development: Case Studies Partial Reconfiguration on Xilinx FPGAs

rawabstract:
This book is designed both for FPGA users interested in developing new, specific components --- generally for reducing execution times and IP core designers interested in extending their catalog of specific components. The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption. This is not a book on algorithms. It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others. Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download.

rawTOC:
Basic Building Blocks \\ Architecture of Digital Circuits \\ Special Topics of Data Path Synthesis \\ Control Unit Synthesis \\ Electronic Aspects of Digital Design \\ EDA Tools \\ Adders \\ Multipliers \\ Dividers \\ Other Operations \\ Decimal Operations \\ Floating Point Arithmetic \\ Finite-Field Arithmetic \\ Systems on Chip \\ Embedded Systems Development: Case Studies \\ Partial Reconfiguration on Xilinx FPGAs

entry:
@Book{Deschamps:2012:GFI,
  author =       "Jean-Pierre Deschamps and Gustavo D. Sutter and
                 Enrique Cant{\'o}",
  title =        "Guide to {FPGA} implementation of arithmetic
                 functions",
  volume =       "95",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "xv + 469",
  year =         "2012",
  DOI =          "https://doi.org/10.1007/978-94-007-2987-2",
  ISBN =         "94-007-2986-3 (hardcover), 94-007-2987-1 (e-book)",
  ISBN-13 =      "978-94-007-2986-5 (hardcover), 978-94-007-2987-2
                 (e-book)",
  LCCN =         "TK7895.G36",
  bibdate =      "Wed Oct 1 10:19:58 MDT 2014",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcw.bib",
  series =       "Lecture notes in electrical engineering",
  abstract =     "This book is designed both for FPGA users interested
                 in developing new, specific components --- generally
                 for reducing execution times and IP core designers
                 interested in extending their catalog of specific
                 components. The main focus is circuit synthesis and the
                 discussion shows, for example, how a given algorithm
                 executing some complex function can be translated to a
                 synthesizable circuit description, as well as which are
                 the best choices the designer can make to reduce the
                 circuit cost, latency, or power consumption. This is
                 not a book on algorithms. It is a book that shows how
                 to translate efficiently an algorithm to a circuit,
                 using techniques such as parallelism, pipeline, loop
                 unrolling, and others. Numerous examples of FPGA
                 implementation are described throughout this book and
                 the circuits are modeled in VHDL. Complete and
                 synthesizable source files are available for
                 download.",
  acknowledgement = ack-nhfb,
  author-dates = "1945--",
  subject =      "Field programmable gate arrays; Programming;
                 Arithmetic functions",
  tableofcontents = "Basic Building Blocks \\
                 Architecture of Digital Circuits \\
                 Special Topics of Data Path Synthesis \\
                 Control Unit Synthesis \\
                 Electronic Aspects of Digital Design \\
                 EDA Tools \\
                 Adders \\
                 Multipliers \\
                 Dividers \\
                 Other Operations \\
                 Decimal Operations \\
                 Floating Point Arithmetic \\
                 Finite-Field Arithmetic \\
                 Systems on Chip \\
                 Embedded Systems Development: Case Studies \\
                 Partial Reconfiguration on Xilinx FPGAs",
}


bibtype: article
filename: fparith.bib
label: Diethelm:2012:LRN
author: Kai Diethelm
title: The Limits of Reproducibility in Numerical Simulation
journal: j-COMPUT-SCI-ENG
volume: 14
number: 1
pages: 64--72
month: jan
monthnumber: 1
year: 2012
CODEN: CSENFA
DOI: https://doi.org/10.1109/MCSE.2011.21
ISSN: 1521-9615 (print), 1558-366X (electronic) OR 15219615 (print), 1558366X (electronic)
ISSNL: 1521-9615 OR 15219615
bibdate: Tue Jan 31 12:29:01 2012
bibtimestamp: 2012.01.31 12:29:01 ???
fjournal: Computing in Science and Engineering
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5992
rawauthor: Kai Diethelm
rawtitle: The Limits of Reproducibility in Numerical Simulation
bibsource:
https://www.math.utah.edu/pub/tex/bib/computscieng.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

remark:
This paper discusses the problem of reproducible, and accurate, computation of long floating-point dot products in parallel computing environments, and how nonreproducibility leads to user confusion.

entry:
@Article{Diethelm:2012:LRN,
  author =       "Kai Diethelm",
  title =        "The Limits of Reproducibility in Numerical
                 Simulation",
  journal =      j-COMPUT-SCI-ENG,
  volume =       "14",
  number =       "1",
  pages =        "64--72",
  month =        jan # "\slash " # feb,
  year =         "2012",
  CODEN =        "CSENFA",
  DOI =          "https://doi.org/10.1109/MCSE.2011.21",
  ISSN =         "1521-9615 (print), 1558-366X (electronic)",
  ISSN-L =       "1521-9615",
  bibdate =      "Tue Jan 31 12:29:01 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computscieng.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing in Science and Engineering",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5992",
  remark =       "This paper discusses the problem of reproducible, and
                 accurate, computation of long floating-point dot
                 products in parallel computing environments, and how
                 nonreproducibility leads to user confusion.",
}


bibtype: article
filename: fparith.bib
label: Fan:2012:EHI
author: Junfeng Fan and Frederik Vercauteren and Ingrid Verbauwhede
title: Efficient Hardware Implementation of FP-Arithmetic for Pairing-Friendly Curves
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 5
pages: 676--685
month: may
monthnumber: 5
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2011.78
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Apr 6 18:50:40 2012
bibtimestamp: 2012.04.06 18:50:40 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Junfeng Fan and Frederik Vercauteren and Ingrid Verbauwhede
rawtitle: Efficient Hardware Implementation of {FP}-Arithmetic for Pairing-Friendly Curves
entry:
@Article{Fan:2012:EHI,
  author =       "Junfeng Fan and Frederik Vercauteren and Ingrid
                 Verbauwhede",
  title =        "Efficient Hardware Implementation of {FP}-Arithmetic
                 for Pairing-Friendly Curves",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "5",
  pages =        "676--685",
  month =        may,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2011.78",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Apr 6 18:50:40 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Fout:2012:APB
author: Nathaniel Fout and Kwan-Liu Ma
title: An Adaptive Prediction-Based Approach to Lossless Compression of Floating-Point Volume Data
journal: j-IEEE-TRANS-VIS-COMPUT-GRAPH
volume: 18
number: 12
pages: 2295--2304
month: dec
monthnumber: 12
year: 2012
CODEN: ITVGEA
DOI: https://doi.org/10.1109/TVCG.2012.194
ISSNL: 1077-2626 OR 10772626
bibdate: Mon Oct 22 07:55:05 2012
bibtimestamp: 2012.10.22 07:55:05 ???
fjournal: IEEE Transactions on Visualization and Computer Graphics
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2945
rawauthor: Nathaniel Fout and Kwan-Liu Ma
rawtitle: An Adaptive Prediction-Based Approach to Lossless Compression of Floating-Point Volume Data
ISSN:
1077-2626 (print), 1941-0506 (electronic), 2160-9306 OR 10772626 (print), 19410506 (electronic), 21609306

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetransviscomputgraph.bib

entry:
@Article{Fout:2012:APB,
  author =       "Nathaniel Fout and Kwan-Liu Ma",
  title =        "An Adaptive Prediction-Based Approach to Lossless
                 Compression of Floating-Point Volume Data",
  journal =      j-IEEE-TRANS-VIS-COMPUT-GRAPH,
  volume =       "18",
  number =       "12",
  pages =        "2295--2304",
  month =        dec,
  year =         "2012",
  CODEN =        "ITVGEA",
  DOI =          "https://doi.org/10.1109/TVCG.2012.194",
  ISSN =         "1077-2626 (print), 1941-0506 (electronic), 2160-9306",
  ISSN-L =       "1077-2626",
  bibdate =      "Mon Oct 22 07:55:05 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransviscomputgraph.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Visualization and Computer
                 Graphics",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2945",
}


bibtype: article
filename: fparith.bib
label: Gandino:2012:AAS
title: An Algorithmic and Architectural Study on Montgomery Exponentiation in RNS
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 8
pages: 1071--1083
month: aug
monthnumber: 8
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2012.84
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 27 08:30:49 2012
bibtimestamp: 2012.07.27 08:30:49 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawtitle: An Algorithmic and Architectural Study on {Montgomery} Exponentiation in {RNS}
author:
Filippo Gandino and Fabrizio Lamberti and Gianluca Paravati and Jean-Claude Bajard and Paolo Montuschi

rawauthor:
Filippo Gandino and Fabrizio Lamberti and Gianluca Paravati and Jean-Claude Bajard and Paolo Montuschi

entry:
@Article{Gandino:2012:AAS,
  author =       "Filippo Gandino and Fabrizio Lamberti and Gianluca
                 Paravati and Jean-Claude Bajard and Paolo Montuschi",
  title =        "An Algorithmic and Architectural Study on {Montgomery}
                 Exponentiation in {RNS}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "8",
  pages =        "1071--1083",
  month =        aug,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2012.84",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 27 08:30:49 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Gazeau:2012:NLM
author: Ivan Gazeau and Dale Miller and Catuscia Palamidessi
title: A non-local method for robustness analysis of floating point programs
journal: arXiv.org
pages: ??--??
day: 3
month: feb
monthnumber: 2
year: 2012
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1202.0693
subject: Programming Languages (cs.PL)
acknowledgement: ack-nhfb
rawauthor: Ivan Gazeau and Dale Miller and Catuscia Palamidessi
rawtitle: A non-local method for robustness analysis of floating point programs
abstract:
Robustness is a standard correctness property which intuitively means that if the input to the program changes less than a fixed small amount then the output changes only slightly. This notion is useful in the analysis of rounding error for floating point programs because it helps to establish bounds on output errors introduced by both measurement errors and by floating point computation. Compositional methods often do not work since key constructs---like the conditional and the while-loop---are not robust. We propose a method for proving the robustness of a while-loop. This method is non-local in the sense that instead of breaking the analysis down to single lines of code, it checks certain global properties of its structure. We show the applicability of our method on two standard algorithms: the CORDIC computation of the cosine and Dijkstra's shortest path algorithm.

rawabstract:
Robustness is a standard correctness property which intuitively means that if the input to the program changes less than a fixed small amount then the output changes only slightly. This notion is useful in the analysis of rounding error for floating point programs because it helps to establish bounds on output errors introduced by both measurement errors and by floating point computation. Compositional methods often do not work since key constructs---like the conditional and the while-loop---are not robust. We propose a method for proving the robustness of a while-loop. This method is non-local in the sense that instead of breaking the analysis down to single lines of code, it checks certain global properties of its structure. We show the applicability of our method on two standard algorithms: the CORDIC computation of the cosine and Dijkstra's shortest path algorithm.

entry:
@Article{Gazeau:2012:NLM,
  author =       "Ivan Gazeau and Dale Miller and Catuscia Palamidessi",
  title =        "A non-local method for robustness analysis of floating
                 point programs",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "3",
  month =        feb,
  year =         "2012",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1202.0693",
  abstract =     "Robustness is a standard correctness property which
                 intuitively means that if the input to the program
                 changes less than a fixed small amount then the output
                 changes only slightly. This notion is useful in the
                 analysis of rounding error for floating point programs
                 because it helps to establish bounds on output errors
                 introduced by both measurement errors and by floating
                 point computation. Compositional methods often do not
                 work since key constructs---like the conditional and
                 the while-loop---are not robust. We propose a method
                 for proving the robustness of a while-loop. This method
                 is non-local in the sense that instead of breaking the
                 analysis down to single lines of code, it checks
                 certain global properties of its structure. We show the
                 applicability of our method on two standard algorithms:
                 the CORDIC computation of the cosine and Dijkstra's
                 shortest path algorithm.",
  acknowledgement = ack-nhfb,
  subject =      "Programming Languages (cs.PL)",
}


bibtype: article
filename: fparith.bib
label: Ghosh:2012:FPR
author: Aniruddha Ghosh and Satrughna Singha and Amitabha Sinha
title: ``Floating point RNS'': a new concept for designing the MAC unit of digital signal processor
journal: j-COMP-ARCH-NEWS
volume: 40
number: 2
pages: 39--43
month: may
monthnumber: 5
year: 2012
CODEN: CANED2
DOI: https://doi.org/10.1145/2234336.2234343
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Fri Jun 1 17:06:51 MDT 2012
bibtimestamp: 2012.06.01 17:06:51 MDT
fjournal: ACM SIGARCH Computer Architecture News
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J89
rawauthor: Aniruddha Ghosh and Satrughna Singha and Amitabha Sinha
rawtitle: {``Floating point RNS''}: a new concept for designing the {MAC} unit of digital signal processor
abstract:
Execution of arithmetic operations at a very high speed in real time is the major concern in compute intensive digital signal processing (DSP) algorithms Residue Number Systems are being considered as alternative to binary number system because of their capabilities of performing ``carry free'' arithmetic operations. However, RNS systems have so far been used to handle integer numbers only. Floating Point RNS arithmetic units have obvious advantages over fixed point multiply & accumulate (MAC) units which are the key units in Digital Signal Processors. Keeping this in view, in this paper, the architecture of a floating point MAC unit is presented.

rawabstract:
Execution of arithmetic operations at a very high speed in real time is the major concern in compute intensive digital signal processing (DSP) algorithms Residue Number Systems are being considered as alternative to binary number system because of their capabilities of performing ``carry free'' arithmetic operations. However, RNS systems have so far been used to handle integer numbers only. Floating Point RNS arithmetic units have obvious advantages over fixed point multiply {\&} accumulate (MAC) units which are the key units in Digital Signal Processors. Keeping this in view, in this paper, the architecture of a floating point MAC unit is presented.

entry:
@Article{Ghosh:2012:FPR,
  author =       "Aniruddha Ghosh and Satrughna Singha and Amitabha
                 Sinha",
  title =        "{``Floating point RNS''}: a new concept for designing
                 the {MAC} unit of digital signal processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "40",
  number =       "2",
  pages =        "39--43",
  month =        may,
  year =         "2012",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/2234336.2234343",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 1 17:06:51 MDT 2012",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Execution of arithmetic operations at a very high
                 speed in real time is the major concern in compute
                 intensive digital signal processing (DSP) algorithms
                 Residue Number Systems are being considered as
                 alternative to binary number system because of their
                 capabilities of performing ``carry free'' arithmetic
                 operations. However, RNS systems have so far been used
                 to handle integer numbers only. Floating Point RNS
                 arithmetic units have obvious advantages over fixed
                 point multiply {\&} accumulate (MAC) units which are
                 the key units in Digital Signal Processors. Keeping
                 this in view, in this paper, the architecture of a
                 floating point MAC unit is presented.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
}


bibtype: article
filename: fparith.bib
label: Giessing:2012:FRB
author: Sarah Giessing
title: Flexible Rounding Based on Consistent Post-tabular Stochastic Noise
journal: j-LECT-NOTES-COMP-SCI
volume: 7556
pages: 22--34
year: 2012
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-33627-0_3
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Wed Dec 19 15:24:52 MST 2012
bibtimestamp: 2012.12.19 15:24:52 MST
URL: http://link.springer.com/chapter/10.1007/978-3-642-33627-0_3/
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-642-33627-0
bookURL: http://www.springerlink.com/content/978-3-642-33627-0
journalURL: http://link.springer.com/bookseries/558
rawauthor: Sarah Giessing
rawtitle: Flexible Rounding Based on Consistent Post-tabular Stochastic Noise
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs2012j.bib

entry:
@Article{Giessing:2012:FRB,
  author =       "Sarah Giessing",
  title =        "Flexible Rounding Based on Consistent Post-tabular
                 Stochastic Noise",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "7556",
  pages =        "22--34",
  year =         "2012",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-33627-0_3",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Wed Dec 19 15:24:52 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs2012j.bib",
  URL =          "http://link.springer.com/chapter/10.1007/978-3-642-33627-0_3/",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-642-33627-0",
  book-URL =     "http://www.springerlink.com/content/978-3-642-33627-0",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: incollection
filename: fparith.bib
label: Goldberg:2012:CA
author: David Goldberg
title: Computer Arithmetic
crossref: Hennessy:2012:CAQ
chapter: J
pages: J-1--J-74
year: 2012
bibdate: Mon Nov 11 05:34:58 2019
bibsource: http://www.mkp.com/CA3; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.11.11 05:34:58 ???
note: The complete Appendix J is not in the printed book; it is available only at the book's Web site.
URL: http://booksite.mkp.com/9780123838728/references/appendix_j.pdf
acknowledgement: ack-nhfb
rawauthor: David Goldberg
rawnote: The complete Appendix J is not in the printed book; it is available only at the book's Web site.
rawtitle: Computer Arithmetic
entry:
@InCollection{Goldberg:2012:CA,
  author =       "David Goldberg",
  title =        "Computer Arithmetic",
  crossref =     "Hennessy:2012:CAQ",
  chapter =      "J",
  pages =        "J-1--J-74",
  year =         "2012",
  bibdate =      "Mon Nov 11 05:34:58 2019",
  bibsource =    "http://www.mkp.com/CA3;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "The complete Appendix J is not in the printed book; it
                 is available only at the book's Web site.",
  URL =          "http://booksite.mkp.com/9780123838728/references/appendix_j.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Goossens:2012:CTS
author: Bernard Goossens and Philippe [Gregoire] Langlois and David Parello and Kathy Porada
booktitle: Numerical Sofware: Design, Analysis and Verification, Santander, Spain, 4--6 July 2012
title: Computing time for summation algorithm: Less hazard and more scientific research
pages: i + 34
year: 2012
bibdate: Sat Apr 01 08:09:42 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.04.01 08:09:42 ???
URL: http://hal-lirmm.ccsd.cnrs.fr/lirmm-00835508
remark: Lecture slides
acknowledgement: ack-nhfb
rawauthor: Bernard Goossens and Philippe [Gr{\'e}goire] Langlois and David Parello and Kathy Porada
rawbooktitle: Numerical Sofware: Design, Analysis and Verification, Santander, Spain, 4--6 July 2012
rawtitle: Computing time for summation algorithm: Less hazard and more scientific research
abstract:
Several accurate algorithms to sum IEEE-754 floating point numbers have been recently published. The contributions by Rump, Ogita and Oishi [3, 4, 2] and the newest ones proposed by Zhu and Hayes [5, 6] are examples of accurate summation algorithms. Some of these actually compute the correct rounding of the exact sum, i.e., the most accurate value with respect to the finite precision of the floating point arithmetic. This computed sum does not suffer anymore from the condition number of the summation. In such cases, the run-time performances and the memory print become the discriminant properties to decide which algorithm to choose. In this talk we focus the problem of presenting reliable measures of the run-time performances of such core algorithms. As Rump writes in [2], Measuring the computing time of summation algorithms in a high-level language on today's architectures is more of a hazard than scientific research. We introduced PerPI, a software tool that automatizes an almost machine independent analysis based on the instruction-level parallelism of the algorithm [1]. We analyze the previously mentioned accurate summation algorithms. We discuss whether PerPI provides a more reliable performance analysis and how to improve the confidence level of future contributions in this area.

keywords:
correct rounding; faithful summation; floating-point arithmetic, accurate summation; instruction level parallelism; performance evaluation; PerPI; reproducibility

rawabstract:
Several accurate algorithms to sum IEEE-754 floating point numbers have been recently published. The contributions by Rump, Ogita and Oishi [3, 4, 2] and the newest ones proposed by Zhu and Hayes [5, 6] are examples of accurate summation algorithms. Some of these actually compute the correct rounding of the exact sum, i.e., the most accurate value with respect to the finite precision of the floating point arithmetic. This computed sum does not suffer anymore from the condition number of the summation. In such cases, the run-time performances and the memory print become the discriminant properties to decide which algorithm to choose. In this talk we focus the problem of presenting reliable measures of the run-time performances of such core algorithms. As Rump writes in [2], Measuring the computing time of summation algorithms in a high-level language on today's architectures is more of a hazard than scientific research. We introduced PerPI, a software tool that automatizes an almost machine independent analysis based on the instruction-level parallelism of the algorithm [1]. We analyze the previously mentioned accurate summation algorithms. We discuss whether PerPI provides a more reliable performance analysis and how to improve the confidence level of future contributions in this area.

entry:
@InProceedings{Goossens:2012:CTS,
  author =       "Bernard Goossens and Philippe [Gr{\'e}goire] Langlois
                 and David Parello and Kathy Porada",
  booktitle =    "Numerical Sofware: Design, Analysis and Verification,
                 Santander, Spain, 4--6 July 2012",
  title =        "Computing time for summation algorithm: Less hazard
                 and more scientific research",
  publisher =    "????",
  address =      "????",
  pages =        "i + 34",
  year =         "2012",
  bibdate =      "Sat Apr 01 08:09:42 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://hal-lirmm.ccsd.cnrs.fr/lirmm-00835508",
  abstract =     "Several accurate algorithms to sum IEEE-754 floating
                 point numbers have been recently published. The
                 contributions by Rump, Ogita and Oishi [3, 4, 2] and
                 the newest ones proposed by Zhu and Hayes [5, 6] are
                 examples of accurate summation algorithms. Some of
                 these actually compute the correct rounding of the
                 exact sum, i.e., the most accurate value with respect
                 to the finite precision of the floating point
                 arithmetic. This computed sum does not suffer anymore
                 from the condition number of the summation. In such
                 cases, the run-time performances and the memory print
                 become the discriminant properties to decide which
                 algorithm to choose. In this talk we focus the problem
                 of presenting reliable measures of the run-time
                 performances of such core algorithms. As Rump writes in
                 [2], Measuring the computing time of summation
                 algorithms in a high-level language on today's
                 architectures is more of a hazard than scientific
                 research. We introduced PerPI, a software tool that
                 automatizes an almost machine independent analysis
                 based on the instruction-level parallelism of the
                 algorithm [1]. We analyze the previously mentioned
                 accurate summation algorithms. We discuss whether PerPI
                 provides a more reliable performance analysis and how
                 to improve the confidence level of future contributions
                 in this area.",
  acknowledgement = ack-nhfb,
  keywords =     "correct rounding; faithful summation; floating-point
                 arithmetic, accurate summation; instruction level
                 parallelism; performance evaluation; PerPI;
                 reproducibility",
  remark =       "Lecture slides",
}


bibtype: article
filename: fparith.bib
label: Grcar:2012:JNA
author: Joseph F. Grcar
title: John von Neumann's Analysis of Gaussian Elimination and the Origins of Modern Numerical Analysis
journal: j-SIAM-REVIEW
volume: 53
number: 4
pages: 607--682
year: 2012
CODEN: SIREAD
DOI: https://doi.org/10.1137/080734716
ISSN: 0036-1445 (print), 1095-7200 (electronic) OR 00361445 (print), 10957200 (electronic)
ISSNL: 0036-1445 OR 00361445
MRclass: 01-08, 65-03, 65F05, 65F35, 65G50, 65M12, 68-03
bibdate: Thu Jan 12 12:42:30 MST 2012
bibtimestamp: 2012.01.12 12:42:30 MST
URL: http://epubs.siam.org/sirev/resource/1/siread/v53/i4/p607_s1
fjournal: SIAM Review
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sirev
onlinedate: November 07, 2011
rawauthor: Joseph F. Grcar
bibsource:
http://epubs.siam.org/sam-bin/dbq/toc/SIREV/53/4; https://www.math.utah.edu/pub/bibnet/authors/v/von-neumann-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamreview.bib

abstract:
Just when modern computers (digital, electronic, and programmable) were being invented, John von Neumann and Herman Goldstine wrote a paper to illustrate the mathematical analyses that they believed would be needed to use the new machines effectively and to guide the development of still faster computers. Their foresight and the congruence of historical events made their work the first modern paper in numerical analysis. Von Neumann once remarked that to found a mathematical theory one had to prove the first theorem, which he and Goldstine did for the accuracy of mechanized Gaussian elimination --- but their paper was about more than that. Von Neumann and Goldstine described what they surmised would be the significant questions once computers became available for computational science, and they suggested enduring ways to answer them.

keywords:
backward error, CFL condition, computer architecture, computer arithmetic, computer programming, condition number, decomposition paradigm, Gaussian elimination, history, matrix norms, numerical analysis, rounding error analysis, stability, stochastic linear algebra, von Neumann

rawabstract:
Just when modern computers (digital, electronic, and programmable) were being invented, John von Neumann and Herman Goldstine wrote a paper to illustrate the mathematical analyses that they believed would be needed to use the new machines effectively and to guide the development of still faster computers. Their foresight and the congruence of historical events made their work the first modern paper in numerical analysis. Von Neumann once remarked that to found a mathematical theory one had to prove the first theorem, which he and Goldstine did for the accuracy of mechanized Gaussian elimination --- but their paper was about more than that. Von Neumann and Goldstine described what they surmised would be the significant questions once computers became available for computational science, and they suggested enduring ways to answer them.

rawtitle:
{John von Neumann}'s Analysis of {Gaussian} Elimination and the Origins of Modern Numerical Analysis

entry:
@Article{Grcar:2012:JNA,
  author =       "Joseph F. Grcar",
  title =        "{John von Neumann}'s Analysis of {Gaussian}
                 Elimination and the Origins of Modern Numerical
                 Analysis",
  journal =      j-SIAM-REVIEW,
  volume =       "53",
  number =       "4",
  pages =        "607--682",
  month =        "????",
  year =         "2012",
  CODEN =        "SIREAD",
  DOI =          "https://doi.org/10.1137/080734716",
  ISSN =         "0036-1445 (print), 1095-7200 (electronic)",
  ISSN-L =       "0036-1445",
  MRclass =      "01-08, 65-03, 65F05, 65F35, 65G50, 65M12, 68-03",
  bibdate =      "Thu Jan 12 12:42:30 MST 2012",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SIREV/53/4;
                 https://www.math.utah.edu/pub/bibnet/authors/v/von-neumann-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamreview.bib",
  URL =          "http://epubs.siam.org/sirev/resource/1/siread/v53/i4/p607_s1",
  abstract =     "Just when modern computers (digital, electronic, and
                 programmable) were being invented, John von Neumann and
                 Herman Goldstine wrote a paper to illustrate the
                 mathematical analyses that they believed would be
                 needed to use the new machines effectively and to guide
                 the development of still faster computers. Their
                 foresight and the congruence of historical events made
                 their work the first modern paper in numerical
                 analysis. Von Neumann once remarked that to found a
                 mathematical theory one had to prove the first theorem,
                 which he and Goldstine did for the accuracy of
                 mechanized Gaussian elimination --- but their paper was
                 about more than that. Von Neumann and Goldstine
                 described what they surmised would be the significant
                 questions once computers became available for
                 computational science, and they suggested enduring ways
                 to answer them.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Review",
  journal-URL =  "http://epubs.siam.org/sirev",
  keywords =     "backward error, CFL condition, computer architecture,
                 computer arithmetic, computer programming, condition
                 number, decomposition paradigm, Gaussian elimination,
                 history, matrix norms, numerical analysis, rounding
                 error analysis, stability, stochastic linear algebra,
                 von Neumann",
  onlinedate =   "November 07, 2011",
}


bibtype: inproceedings
filename: fparith.bib
label: Haller:2012:DFP
author: L. Haller and A. Griggio and M. Brain and D. Kroening
booktitle: Formal Methods in Computer-Aided Design (FMCAD), 2012
title: Deciding floating-point logic with systematic abstraction
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 131--140
month: oct
monthnumber: 10
year: 2012
ISBN: 1-4673-4832-5 OR 1467348325
ISBN13: 978-1-4673-4832-4 OR 9781467348324
bibdate: Sat Jun 4 18:09:21 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.06.04 18:09:21 ???
acknowledgement: ack-nhfb
rawauthor: L. Haller and A. Griggio and M. Brain and D. Kroening
rawbooktitle: {Formal Methods in Computer-Aided Design (FMCAD), 2012}
rawtitle: Deciding floating-point logic with systematic abstraction
keywords:
abstract interpretation; Abstracts; Algorithm design and analysis; Analytical models; binary floating-point arithmetic; bit-precise decision procedure; bit-vector encoding; computability; conflict analysis algorithm; conflict driven clause learning algorithm; decision procedures; Design automation; encoding; Encoding; floating point; floating point arithmetic; floating-point interval abstraction; floating-point logic; floating-point satisfiability checking; lattice-based abstraction; Lattices; MATHSAT5; natural-domain SMT approach; propositional solver; SAT solver; Standards; systematic abstraction

entry:
@InProceedings{Haller:2012:DFP,
  author =       "L. Haller and A. Griggio and M. Brain and D.
                 Kroening",
  booktitle =    "{Formal Methods in Computer-Aided Design (FMCAD),
                 2012}",
  title =        "Deciding floating-point logic with systematic
                 abstraction",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "131--140",
  month =        oct,
  year =         "2012",
  ISBN =         "1-4673-4832-5",
  ISBN-13 =      "978-1-4673-4832-4",
  bibdate =      "Sat Jun 4 18:09:21 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "abstract interpretation; Abstracts; Algorithm design
                 and analysis; Analytical models; binary floating-point
                 arithmetic; bit-precise decision procedure; bit-vector
                 encoding; computability; conflict analysis algorithm;
                 conflict driven clause learning algorithm; decision
                 procedures; Design automation; encoding; Encoding;
                 floating point; floating point arithmetic;
                 floating-point interval abstraction; floating-point
                 logic; floating-point satisfiability checking;
                 lattice-based abstraction; Lattices; MATHSAT5;
                 natural-domain SMT approach; propositional solver; SAT
                 solver; Standards; systematic abstraction",
}


bibtype: article
filename: fparith.bib
label: Huang:2012:LCB
author: Libo Huang and Sheng Ma and Li Shen and Zhiying Wang and Nong Xiao
title: Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 5
pages: 745--751
month: may
monthnumber: 5
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2011.77
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Apr 6 18:50:40 2012
bibtimestamp: 2012.04.06 18:50:40 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Libo Huang and Sheng Ma and Li Shen and Zhiying Wang and Nong Xiao
rawtitle: Low-Cost {Binary128} Floating-Point {FMA} Unit Design with {SIMD} Support
entry:
@Article{Huang:2012:LCB,
  author =       "Libo Huang and Sheng Ma and Li Shen and Zhiying Wang
                 and Nong Xiao",
  title =        "Low-Cost {Binary128} Floating-Point {FMA} Unit Design
                 with {SIMD} Support",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "5",
  pages =        "745--751",
  month =        may,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2011.77",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Apr 6 18:50:40 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Hyman:2012:LF
author: Paul Hyman
title: Lost and found
journal: j-CACM
volume: 55
number: 7
pages: 21--21
month: jul
monthnumber: 7
year: 2012
CODEN: CACMA2
DOI: https://doi.org/10.1145/2209249.2209258
ISSN: 0001-0782 (print), 1557-7317 (electronic) OR 00010782 (print), 15577317 (electronic)
ISSNL: 0001-0782 OR 00010782
bibdate: Tue Jul 3 13:54:33 MDT 2012
bibtimestamp: 2012.07.03 13:54:33 MDT
fjournal: Communications of the ACM
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/cacm
rawauthor: Paul Hyman
rawtitle: Lost and found
bibsource:
http://www.acm.org/pubs/contents/journals/cacm/; https://www.math.utah.edu/pub/tex/bib/cacm2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
Researchers discover computer pioneer Konrad Zuse's long-forgotten Z9, the world's first program-controlled binary relay calculator using floating-point arithmetic.

rawabstract:
Researchers discover computer pioneer Konrad Zuse's long-forgotten Z9, the world's first program-controlled binary relay calculator using floating-point arithmetic.

entry:
@Article{Hyman:2012:LF,
  author =       "Paul Hyman",
  title =        "Lost and found",
  journal =      j-CACM,
  volume =       "55",
  number =       "7",
  pages =        "21--21",
  month =        jul,
  year =         "2012",
  CODEN =        "CACMA2",
  DOI =          "https://doi.org/10.1145/2209249.2209258",
  ISSN =         "0001-0782 (print), 1557-7317 (electronic)",
  ISSN-L =       "0001-0782",
  bibdate =      "Tue Jul 3 13:54:33 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/cacm/;
                 https://www.math.utah.edu/pub/tex/bib/cacm2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Researchers discover computer pioneer Konrad Zuse's
                 long-forgotten Z9, the world's first program-controlled
                 binary relay calculator using floating-point
                 arithmetic.",
  acknowledgement = ack-nhfb,
  fjournal =     "Communications of the ACM",
  journal-URL =  "https://dl.acm.org/loi/cacm",
}


bibtype: techreport
filename: fparith.bib
label: Katranov:2012:DRN
author: A. Katranov
title: Deterministic Reduction: a new Community Preview Feature in Intel Threading Building Blocks
type: Report
institution: pub-INTEL
address: pub-INTEL:adr
year: 2012
bibdate: Sat Oct 31 06:58:31 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.10.31 06:58:31 ???
acknowledgement: ack-nhfb
rawauthor: A. Katranov
rawtitle: Deterministic Reduction: a new Community Preview Feature in {Intel Threading Building Blocks}
entry:
@TechReport{Katranov:2012:DRN,
  author =       "A. Katranov",
  title =        "Deterministic Reduction: a new Community Preview
                 Feature in {Intel Threading Building Blocks}",
  type =         "Report",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "????",
  year =         "2012",
  bibdate =      "Sat Oct 31 06:58:31 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Koiran:2012:ACC
author: Pascal Koiran
title: Arithmetic circuits: the chasm at depth four gets wider
journal: j-THEOR-COMP-SCI
volume: 448
number: 1
pages: 56--65
day: 24
month: aug
monthnumber: 8
year: 2012
CODEN: TCSCDI
DOI: https://doi.org/10.1016/j.tcs.2012.03.041
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Sat Jun 30 13:07:21 MDT 2012
bibtimestamp: 2012.06.30 13:07:21 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0304397512003131
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975/
rawauthor: Pascal Koiran
rawtitle: Arithmetic circuits: the chasm at depth four gets wider
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tcs2010.bib

entry:
@Article{Koiran:2012:ACC,
  author =       "Pascal Koiran",
  title =        "Arithmetic circuits: the chasm at depth four gets
                 wider",
  journal =      j-THEOR-COMP-SCI,
  volume =       "448",
  number =       "1",
  pages =        "56--65",
  day =          "24",
  month =        aug,
  year =         "2012",
  CODEN =        "TCSCDI",
  DOI =          "https://doi.org/10.1016/j.tcs.2012.03.041",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Sat Jun 30 13:07:21 MDT 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tcs2010.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0304397512003131",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975/",
}


bibtype: article
filename: fparith.bib
label: Kornerup:2012:CCR
author: Peter Kornerup and Vincent Lefevre and Nicolas Louvet and Jean-Michel Muller
title: On the Computation of Correctly Rounded Sums
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 3
pages: 289--298
month: mar
monthnumber: 3
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2011.27
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Feb 3 07:35:03 2012
bibtimestamp: 2012.02.03 07:35:03 ???
fjournal: IEEE Transactions on Computers
keywords: accurate floating-point summation; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Peter Kornerup and Vincent Lef{\`e}vre and Nicolas Louvet and Jean-Michel Muller
rawtitle: On the Computation of Correctly Rounded Sums
abstract:
This paper presents a study of some basic blocks needed in the design of floating-point summation algorithms. In particular, in radix-2 floating-point arithmetic, we show that among the set of the algorithms with no comparisons performing only floating-point additions/subtractions, the 2Sum algorithm introduced by Knuth is minimal, both in terms of number of operations and depth of the dependency graph. We investigate the possible use of another algorithm, Dekker's Fast2Sum algorithm, in radix-10 arithmetic. We give methods for computing, in radix 10, the floating-point number nearest the average value of two floating-point numbers. We also prove that under reasonable conditions, an algorithm performing only round-to-nearest additions/subtractions cannot compute the round-to-nearest sum of at least three floating-point numbers. Starting from an algorithm due to Boldo and Melquiond, we also present new results about the computation of the correctly-rounded sum of three floating-point numbers. For a few of our algorithms, we assume new operations defined by the recent IEEE 754-2008 Standard are available.

rawabstract:
This paper presents a study of some basic blocks needed in the design of floating-point summation algorithms. In particular, in radix-2 floating-point arithmetic, we show that among the set of the algorithms with no comparisons performing only floating-point additions/subtractions, the 2Sum algorithm introduced by Knuth is minimal, both in terms of number of operations and depth of the dependency graph. We investigate the possible use of another algorithm, Dekker's Fast2Sum algorithm, in radix-10 arithmetic. We give methods for computing, in radix 10, the floating-point number nearest the average value of two floating-point numbers. We also prove that under reasonable conditions, an algorithm performing only round-to-nearest additions/subtractions cannot compute the round-to-nearest sum of at least three floating-point numbers. Starting from an algorithm due to Boldo and Melquiond, we also present new results about the computation of the correctly-rounded sum of three floating-point numbers. For a few of our algorithms, we assume new operations defined by the recent IEEE 754-2008 Standard are available.

entry:
@Article{Kornerup:2012:CCR,
  author =       "Peter Kornerup and Vincent Lef{\`e}vre and Nicolas
                 Louvet and Jean-Michel Muller",
  title =        "On the Computation of Correctly Rounded Sums",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "3",
  pages =        "289--298",
  month =        mar,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2011.27",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Feb 3 07:35:03 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  abstract =     "This paper presents a study of some basic blocks
                 needed in the design of floating-point summation
                 algorithms. In particular, in radix-2 floating-point
                 arithmetic, we show that among the set of the
                 algorithms with no comparisons performing only
                 floating-point additions/subtractions, the 2Sum
                 algorithm introduced by Knuth is minimal, both in terms
                 of number of operations and depth of the dependency
                 graph. We investigate the possible use of another
                 algorithm, Dekker's Fast2Sum algorithm, in radix-10
                 arithmetic. We give methods for computing, in radix 10,
                 the floating-point number nearest the average value of
                 two floating-point numbers. We also prove that under
                 reasonable conditions, an algorithm performing only
                 round-to-nearest additions/subtractions cannot compute
                 the round-to-nearest sum of at least three
                 floating-point numbers. Starting from an algorithm due
                 to Boldo and Melquiond, we also present new results
                 about the computation of the correctly-rounded sum of
                 three floating-point numbers. For a few of our
                 algorithms, we assume new operations defined by the
                 recent IEEE 754-2008 Standard are available.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "accurate floating-point summation; correct rounding;
                 floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Kornerup:2012:FPA
author: Peter Kornerup and Jean-Michel Muller and Adrien Panhaleux
title: Floating-Point Arithmetic on Round-to-Nearest Representations
journal: arXiv.org
pages: ??--??
day: 18
month: jan
monthnumber: 1
year: 2012
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1201.3914
subject: Numerical Analysis (cs.NA)
acknowledgement: ack-nhfb
rawauthor: Peter Kornerup and Jean-Michel Muller and Adrien Panhaleux
rawtitle: Floating-Point Arithmetic on Round-to-Nearest Representations
abstract:
Recently we introduced a class of number representations denoted RN-representations, allowing an un-biased rounding-to-nearest to take place by a simple truncation. In this paper we briefly review the binary fixed-point representation in an encoding which is essentially an ordinary 2's complement representation with an appended round-bit. Not only is this rounding a constant time operation, so is also sign inversion, both of which are at best log-time operations on ordinary 2's complement representations. Addition, multiplication and division is defined in such a way that rounding information can be carried along in a meaningful way, at minimal cost. Based on the fixed-point encoding we here define a floating point representation, and describe to some detail a possible implementation of a floating point arithmetic unit employing this representation, including also the directed roundings.

rawabstract:
Recently we introduced a class of number representations denoted RN-representations, allowing an un-biased rounding-to-nearest to take place by a simple truncation. In this paper we briefly review the binary fixed-point representation in an encoding which is essentially an ordinary 2's complement representation with an appended round-bit. Not only is this rounding a constant time operation, so is also sign inversion, both of which are at best log-time operations on ordinary 2's complement representations. Addition, multiplication and division is defined in such a way that rounding information can be carried along in a meaningful way, at minimal cost. Based on the fixed-point encoding we here define a floating point representation, and describe to some detail a possible implementation of a floating point arithmetic unit employing this representation, including also the directed roundings.

entry:
@Article{Kornerup:2012:FPA,
  author =       "Peter Kornerup and Jean-Michel Muller and Adrien
                 Panhaleux",
  title =        "Floating-Point Arithmetic on Round-to-Nearest
                 Representations",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "18",
  month =        jan,
  year =         "2012",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1201.3914",
  abstract =     "Recently we introduced a class of number
                 representations denoted RN-representations, allowing an
                 un-biased rounding-to-nearest to take place by a simple
                 truncation. In this paper we briefly review the binary
                 fixed-point representation in an encoding which is
                 essentially an ordinary 2's complement representation
                 with an appended round-bit. Not only is this rounding a
                 constant time operation, so is also sign inversion,
                 both of which are at best log-time operations on
                 ordinary 2's complement representations. Addition,
                 multiplication and division is defined in such a way
                 that rounding information can be carried along in a
                 meaningful way, at minimal cost. Based on the
                 fixed-point encoding we here define a floating point
                 representation, and describe to some detail a possible
                 implementation of a floating point arithmetic unit
                 employing this representation, including also the
                 directed roundings.",
  acknowledgement = ack-nhfb,
  subject =      "Numerical Analysis (cs.NA)",
}


bibtype: article
filename: fparith.bib
label: Kramer:2012:MAP
author: Walter Kramer
title: Multiple / arbitrary precision interval computations in C-XSC
journal: j-COMPUTING
volume: 94
number: 2--4
pages: 229--241
month: mar
monthnumber: 3
year: 2012
CODEN: CMPTA2
DOI: https://doi.org/10.1007/s00607-011-0174-8
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
bibdate: Mon Apr 9 16:41:18 MDT 2012
bibtimestamp: 2012.04.09 16:41:18 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=94&issue=2&spage=229
fjournal: Computing
acknowledgement: ack-nhfb
authordates: 1952--2014
journalURL: http://link.springer.com/journal/607
rawauthor: Walter Kr{\"a}mer
rawtitle: Multiple\slash arbitrary precision interval computations in {C-XSC}
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=94&issue=2; https://www.math.utah.edu/pub/tex/bib/computing.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

remark:
Special Issue on GAMM--IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN2010).

entry:
@Article{Kramer:2012:MAP,
  author =       "Walter Kr{\"a}mer",
  title =        "Multiple\slash arbitrary precision interval
                 computations in {C-XSC}",
  journal =      j-COMPUTING,
  volume =       "94",
  number =       "2--4",
  pages =        "229--241",
  month =        mar,
  year =         "2012",
  CODEN =        "CMPTA2",
  DOI =          "https://doi.org/10.1007/s00607-011-0174-8",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  bibdate =      "Mon Apr 9 16:41:18 MDT 2012",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=94&issue=2;
                 https://www.math.utah.edu/pub/tex/bib/computing.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=94&issue=2&spage=229",
  acknowledgement = ack-nhfb,
  author-dates = "1952--2014",
  fjournal =     "Computing",
  journal-URL =  "http://link.springer.com/journal/607",
  remark =       "Special Issue on GAMM--IMACS International Symposium
                 on Scientific Computing, Computer Arithmetic and
                 Validated Numerics (SCAN2010).",
}


bibtype: inproceedings
filename: fparith.bib
label: Kumm:2012:RCS
author: Martin Kumm and Katharina Liebisch and Peter Zipf
booktitle: IEEE 22nd International Conference on Field Programmable Logic and Application (FPL), 2012
title: Reduced Complexity Single and Multiple Constant Multiplication in Floating Point Precision
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 255--261
year: 2012
DOI: https://doi.org/10.1109/FPL.2012.6339190
bibdate: Sat Feb 08 09:39:36 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 09:39:36 ???
URL: https://ieeexplore.ieee.org/document/6339190/
acknowledgement: ack-nhfb
rawauthor: Martin Kumm and Katharina Liebisch and Peter Zipf
rawbooktitle: {IEEE 22nd International Conference on Field Programmable Logic and Application (FPL), 2012}
rawtitle: Reduced Complexity Single and Multiple Constant Multiplication in Floating Point Precision
entry:
@InProceedings{Kumm:2012:RCS,
  author =       "Martin Kumm and Katharina Liebisch and Peter Zipf",
  editor =       "????",
  booktitle =    "{IEEE 22nd International Conference on Field
                 Programmable Logic and Application (FPL), 2012}",
  title =        "Reduced Complexity Single and Multiple Constant
                 Multiplication in Floating Point Precision",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "255--261",
  year =         "2012",
  DOI =          "https://doi.org/10.1109/FPL.2012.6339190",
  bibdate =      "Sat Feb 08 09:39:36 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/document/6339190/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kurka:2012:FAA
author: Petr Kurka
title: Fast Arithmetical Algorithms in Mobius Number Systems
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 8
pages: 1097--1109
month: aug
monthnumber: 8
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2012.87
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 27 08:30:49 2012
bibtimestamp: 2012.07.27 08:30:49 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Petr K{\r{u}}rka
rawtitle: Fast Arithmetical Algorithms in {M{\"o}bius} Number Systems
entry:
@Article{Kurka:2012:FAA,
  author =       "Petr K{\r{u}}rka",
  title =        "Fast Arithmetical Algorithms in {M{\"o}bius} Number
                 Systems",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "8",
  pages =        "1097--1109",
  month =        aug,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2012.87",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 27 08:30:49 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Langlois:2012:ACT
author: Philippe Langlois and Matthieu Martel and Laurent Thevenoux
title: Automatic code transformation to optimize accuracy and speed in floating-point arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: ??--??
year: 2012
bibdate: Sat Apr 01 07:42:30 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.04.01 07:42:30 ???
URL: https://hal.archives-ouvertes.fr/hal-00821667
acknowledgement: ack-nhfb
rawauthor: Philippe Langlois and Matthieu Martel and Laurent Th{\'e}venoux
rawtitle: Automatic code transformation to optimize accuracy and speed in floating-point arithmetic
booktitle:
Proceedings of the 15th GAMM--IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics, Novosibirsk, Russia

abstract:
We want to allow the standard software developer to automatically transform his/her code in order to increase the accuracy of floating-point computations. This transformation is actually an optimization since we aim to take into account two opposite criteria: accuracy and execution time. A first step towards this automatic optimization is presented in this work. We propose to automatically introduce at the compile-time compensation steps in (parts of) the floating-point computations. We present a tool to parse C codes and to insert compensated floating-point operations. This provides a compensated computation that improves the accuracy of specific computing patterns.

rawabstract:
We want to allow the standard software developer to automatically transform his/her code in order to increase the accuracy of floating-point computations. This transformation is actually an optimization since we aim to take into account two opposite criteria: accuracy and execution time. A first step towards this automatic optimization is presented in this work. We propose to automatically introduce at the compile-time compensation steps in (parts of) the floating-point computations. We present a tool to parse C codes and to insert compensated floating-point operations. This provides a compensated computation that improves the accuracy of specific computing patterns.

rawbooktitle:
{Proceedings of the 15th GAMM--IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics, Novosibirsk, Russia}

entry:
@InProceedings{Langlois:2012:ACT,
  author =       "Philippe Langlois and Matthieu Martel and Laurent
                 Th{\'e}venoux",
  editor =       "????",
  booktitle =    "{Proceedings of the 15th GAMM--IMACS International
                 Symposium on Scientific Computing, Computer Arithmetic
                 and Validated Numerics, Novosibirsk, Russia}",
  title =        "Automatic code transformation to optimize accuracy and
                 speed in floating-point arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "??--??",
  year =         "2012",
  bibdate =      "Sat Apr 01 07:42:30 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.archives-ouvertes.fr/hal-00821667",
  abstract =     "We want to allow the standard software developer to
                 automatically transform his/her code in order to
                 increase the accuracy of floating-point computations.
                 This transformation is actually an optimization since
                 we aim to take into account two opposite criteria:
                 accuracy and execution time. A first step towards this
                 automatic optimization is presented in this work. We
                 propose to automatically introduce at the compile-time
                 compensation steps in (parts of) the floating-point
                 computations. We present a tool to parse C codes and to
                 insert compensated floating-point operations. This
                 provides a compensated computation that improves the
                 accuracy of specific computing patterns.",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Langlois:2012:CTS
author: Philippe Langlois and David Parello and Bernard Goossens and Kathy Porada
title: Computing time for summation algorithm: Less hazard and more scientific research
type: Research Report
number: RR-12021
institution: LIRMM, Universite Montpellier 2
address: CNRS UMR 5506, France
pages: i + 34
year: 2012
bibdate: Sat Apr 01 08:09:42 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.04.01 08:09:42 ???
acknowledgement: ack-nhfb
rawauthor: Philippe Langlois and David Parello and Bernard Goossens and Kathy Porada
rawtitle: Computing time for summation algorithm: Less hazard and more scientific research
URL:
http://personales.unican.es/segurajj/numsoft12/; https://hal-lirmm.ccsd.cnrs.fr/lirmm-00737617; https://hal-lirmm.ccsd.cnrs.fr/lirmm-00737617/document

abstract:
Several accurate algorithms to sum IEEE-754 floating-point numbers have been recently published. The recent contributions by Rump, Ogita and Oishi and the newest ones proposed by Zhu and Hayes are examples of accurate summation algorithms. Some of these even compute the faithful or the correct rounding of the exact sum, i.e. the most accurate value with respect to the finite precision of the floating-point arithmetic. This computed sum does not suffer anymore from the condition number of the summation. In such cases, the run-time performances and the memory prints become the discriminant properties to decide which algorithm is best.par In this paper we focus on the reliability of the run-time performance measure of such core algorithms. We explain how right Rump when he writes ``Measuring the computing time of summation algorithms in a high-level language on today's architectures is more of a hazard than scientific research.'' Neither the classical flop count nor hardware counter based measures are satisfactory here. We propose to analyze the instruction level parallelism of these algorithms to reliably evaluate their performance potential. We use PerPI, a software tool that automatizes an almost machine independent instruction-level parallelism analysis. We study recent accurate summation algorithms with a detailed focus on the two newest faithful ones. We illustrate and discuss why PerPI provides a more reliable performance analysis, the remaining weakness and how to improve confidence for future contributions in this area.

keywords:
correct rounding; faithful summation; floating-point arithmetic, accurate summation; instruction level parallelism; performance evaluation; PerPI; reproducibility

rawabstract:
Several accurate algorithms to sum IEEE-754 floating-point numbers have been recently published. The recent contributions by Rump, Ogita and Oishi and the newest ones proposed by Zhu and Hayes are examples of accurate summation algorithms. Some of these even compute the faithful or the correct rounding of the exact sum, i.e. the most accurate value with respect to the finite precision of the floating-point arithmetic. This computed sum does not suffer anymore from the condition number of the summation. In such cases, the run-time performances and the memory prints become the discriminant properties to decide which algorithm is best.\par In this paper we focus on the reliability of the run-time performance measure of such core algorithms. We explain how right Rump when he writes ``Measuring the computing time of summation algorithms in a high-level language on today's architectures is more of a hazard than scientific research.'' Neither the classical flop count nor hardware counter based measures are satisfactory here. We propose to analyze the instruction level parallelism of these algorithms to reliably evaluate their performance potential. We use PerPI, a software tool that automatizes an almost machine independent instruction-level parallelism analysis. We study recent accurate summation algorithms with a detailed focus on the two newest faithful ones. We illustrate and discuss why PerPI provides a more reliable performance analysis, the remaining weakness and how to improve confidence for future contributions in this area.

entry:
@TechReport{Langlois:2012:CTS,
  author =       "Philippe Langlois and David Parello and Bernard
                 Goossens and Kathy Porada",
  title =        "Computing time for summation algorithm: Less hazard
                 and more scientific research",
  type =         "Research Report",
  number =       "RR-12021",
  institution =  "LIRMM, Universit{\'e} Montpellier 2",
  address =      "CNRS UMR 5506, France",
  pages =        "i + 34",
  year =         "2012",
  bibdate =      "Sat Apr 01 08:09:42 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://personales.unican.es/segurajj/numsoft12/;
                 https://hal-lirmm.ccsd.cnrs.fr/lirmm-00737617;
                 https://hal-lirmm.ccsd.cnrs.fr/lirmm-00737617/document",
  abstract =     "Several accurate algorithms to sum IEEE-754
                 floating-point numbers have been recently published.
                 The recent contributions by Rump, Ogita and Oishi and
                 the newest ones proposed by Zhu and Hayes are examples
                 of accurate summation algorithms. Some of these even
                 compute the faithful or the correct rounding of the
                 exact sum, i.e. the most accurate value with respect to
                 the finite precision of the floating-point arithmetic.
                 This computed sum does not suffer anymore from the
                 condition number of the summation. In such cases, the
                 run-time performances and the memory prints become the
                 discriminant properties to decide which algorithm is
                 best.\par

                 In this paper we focus on the reliability of the
                 run-time performance measure of such core algorithms.
                 We explain how right Rump when he writes ``Measuring
                 the computing time of summation algorithms in a
                 high-level language on today's architectures is more of
                 a hazard than scientific research.'' Neither the
                 classical flop count nor hardware counter based
                 measures are satisfactory here. We propose to analyze
                 the instruction level parallelism of these algorithms
                 to reliably evaluate their performance potential. We
                 use PerPI, a software tool that automatizes an almost
                 machine independent instruction-level parallelism
                 analysis. We study recent accurate summation algorithms
                 with a detailed focus on the two newest faithful ones.
                 We illustrate and discuss why PerPI provides a more
                 reliable performance analysis, the remaining weakness
                 and how to improve confidence for future contributions
                 in this area.",
  acknowledgement = ack-nhfb,
  keywords =     "correct rounding; faithful summation; floating-point
                 arithmetic, accurate summation; instruction level
                 parallelism; performance evaluation; PerPI;
                 reproducibility",
}


bibtype: article
filename: fparith.bib
label: Lee:2012:CPS
author: Mun-Kyu Lee
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 4
pages: 591--592
month: apr
monthnumber: 4
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2011.109
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Sat Mar 10 16:19:08 2012
bibtimestamp: 2012.03.10 16:19:08 ???
note: See cite Dimitrov:2008:PSP.
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Mun-Kyu Lee
rawnote: See \cite{Dimitrov:2008:PSP}.
title:
Comments on ``Provably Sublinear Point Multiplication on Koblitz Curves and Its Hardware Implementation''

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib

rawtitle:
Comments on {``Provably Sublinear Point Multiplication on Koblitz Curves and Its Hardware Implementation''}

entry:
@Article{Lee:2012:CPS,
  author =       "Mun-Kyu Lee",
  title =        "Comments on {``Provably Sublinear Point Multiplication
                 on Koblitz Curves and Its Hardware Implementation''}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "4",
  pages =        "591--592",
  month =        apr,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2011.109",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Mar 10 16:19:08 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  note =         "See \cite{Dimitrov:2008:PSP}.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Lee:2012:DHP
author: Yong-Hwan Lee and Young-Sung Cho and Sangook Moon
title: Design of a high precision logarithmic converter in a binary floating point divider
journal: j-CCPE
volume: 24
number: 4
pages: 342--353
year: 2012
CODEN: CCPEBO
DOI: https://doi.org/10.1002/cpe.1569
ISSN: 1532-0626 (print), 1532-0634 (electronic) OR 15320626 (print), 15320634 (electronic)
ISSNL: 1532-0626 OR 15320626
bibdate: Wed Apr 4 09:18:01 MDT 2012
bibtimestamp: 2012.04.04 09:18:01 MDT
fjournal: Concurrency and Computation: Practice and Experience
acknowledgement: ack-nhfb
journalURL: http://www.interscience.wiley.com/jpages/1532-0626
onlinedate: 1 Apr 2010
rawauthor: Yong-Hwan Lee and Young-Sung Cho and Sangook Moon
rawtitle: Design of a high precision logarithmic converter in a binary floating point divider
bibsource:
http://www.interscience.wiley.com/jpages/1532-0626; https://www.math.utah.edu/pub/tex/bib/ccpe.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Lee:2012:DHP,
  author =       "Yong-Hwan Lee and Young-Sung Cho and Sangook Moon",
  title =        "Design of a high precision logarithmic converter in a
                 binary floating point divider",
  journal =      j-CCPE,
  volume =       "24",
  number =       "4",
  pages =        "342--353",
  month =        "????",
  year =         "2012",
  CODEN =        "CCPEBO",
  DOI =          "https://doi.org/10.1002/cpe.1569",
  ISSN =         "1532-0626 (print), 1532-0634 (electronic)",
  ISSN-L =       "1532-0626",
  bibdate =      "Wed Apr 4 09:18:01 MDT 2012",
  bibsource =    "http://www.interscience.wiley.com/jpages/1532-0626;
                 https://www.math.utah.edu/pub/tex/bib/ccpe.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Concurrency and Computation: Prac\-tice and
                 Experience",
  journal-URL =  "http://www.interscience.wiley.com/jpages/1532-0626",
  onlinedate =   "1 Apr 2010",
}


bibtype: article
filename: fparith.bib
label: Li:2012:ENE
author: Wenbin Li and Sven Simon and Steffen Kiess
journal: j-APPL-NUM-MATH
volume: 62
number: 5
pages: 536--555
month: may
monthnumber: 5
year: 2012
CODEN: ANMAEL
DOI: https://doi.org/10.1016/j.apnum.2012.01.001
ISSN: 0168-9274 (print), 1873-5460 (electronic) OR 01689274 (print), 18735460 (electronic)
ISSNL: 0168-9274 OR 01689274
bibdate: Thu Mar 8 07:24:49 MST 2012
bibtimestamp: 2012.03.08 07:24:49 MST
URL: http://www.sciencedirect.com/science/article/pii/S0168927412000086
fjournal: Applied Numerical Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/01689274/
rawauthor: Wenbin Li and Sven Simon and Steffen Kie{\ss}
title:
On the estimation of numerical error bounds in linear algebra based on discrete stochastic arithmetic

bibsource:
https://www.math.utah.edu/pub/tex/bib/applnummath.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
On the estimation of numerical error bounds in linear algebra based on discrete stochastic arithmetic

entry:
@Article{Li:2012:ENE,
  author =       "Wenbin Li and Sven Simon and Steffen Kie{\ss}",
  title =        "On the estimation of numerical error bounds in linear
                 algebra based on discrete stochastic arithmetic",
  journal =      j-APPL-NUM-MATH,
  volume =       "62",
  number =       "5",
  pages =        "536--555",
  month =        may,
  year =         "2012",
  CODEN =        "ANMAEL",
  DOI =          "https://doi.org/10.1016/j.apnum.2012.01.001",
  ISSN =         "0168-9274 (print), 1873-5460 (electronic)",
  ISSN-L =       "0168-9274",
  bibdate =      "Thu Mar 8 07:24:49 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/applnummath.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0168927412000086",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Numerical Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01689274/",
}


bibtype: article
filename: fparith.bib
label: Liedel:2012:SDC
author: Manuel Liedel
title: Secure Distributed Computation of the Square Root and Applications
journal: j-LECT-NOTES-COMP-SCI
volume: 7232
pages: 277--288
year: 2012
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-29101-2_19
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Mon Dec 24 07:23:24 MST 2012
bibtimestamp: 2012.12.24 07:23:24 MST
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-642-29101-2
bookURL: http://www.springerlink.com/content/978-3-642-29101-2
journalURL: http://link.springer.com/bookseries/558
rawauthor: Manuel Liedel
rawtitle: Secure Distributed Computation of the Square Root and Applications
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs2012c.bib

URL:
http://link.springer.com/chapter/10.1007/978-3-642-29101-2_19/; http://link.springer.com/content/pdf/10.1007/978-3-642-29101-2_19

entry:
@Article{Liedel:2012:SDC,
  author =       "Manuel Liedel",
  title =        "Secure Distributed Computation of the Square Root and
                 Applications",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "7232",
  pages =        "277--288",
  year =         "2012",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-29101-2_19",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Mon Dec 24 07:23:24 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs2012c.bib",
  URL =          "http://link.springer.com/chapter/10.1007/978-3-642-29101-2_19/;
                 http://link.springer.com/content/pdf/10.1007/978-3-642-29101-2_19",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-642-29101-2",
  book-URL =     "http://www.springerlink.com/content/978-3-642-29101-2",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Liu:2012:PED
author: Wei Liu and Alberto Nannarelli
title: Power Efficient Division and Square Root Unit
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 8
pages: 1059--1070
month: aug
monthnumber: 8
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2012.82
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jul 27 08:30:49 2012
bibtimestamp: 2012.07.27 08:30:49 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Wei Liu and Alberto Nannarelli
rawtitle: Power Efficient Division and Square Root Unit
entry:
@Article{Liu:2012:PED,
  author =       "Wei Liu and Alberto Nannarelli",
  title =        "Power Efficient Division and Square Root Unit",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "8",
  pages =        "1059--1070",
  month =        aug,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2012.82",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jul 27 08:30:49 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Maitra:2012:NAC
author: Subhashis Maitra and Amitabha Sinha
title: A new algorithm for computing triple-base number system
journal: j-COMP-ARCH-NEWS
volume: 40
number: 4
pages: 3--9
month: sep
monthnumber: 9
year: 2012
CODEN: CANED2
DOI: https://doi.org/10.1145/2411116.2411119
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Tue Dec 11 08:06:57 MST 2012
bibtimestamp: 2012.12.11 08:06:57 MST
fjournal: ACM SIGARCH Computer Architecture News
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J89
rawauthor: Subhashis Maitra and Amitabha Sinha
rawtitle: A new algorithm for computing triple-base number system
abstract:
We introduce here a generalized method a new Algorithm to find Triple-Base number system and Triple-Base chain and hence in turn Single Digit Triple-Base number system(SDTBNS). The proposed method is not only simpler and faster than the Algorithms to find Double-Base number system or Double-Base chain, experimentally it also returns a shorter length of Triple-Base chain which in turn reduces the size of the look-up-table to find out SDTBNS. The complexity analysis and experimental results shows the novelty of the proposed Algorithm. Moreover when the proposed method is applied to find scalar multiplication in case of Elliptic Curve Cryptography and coefficient multiplication in case of designing digital filter, its efficiency also proves its novelty. Here we have used third base as $5$ because when it is multiplied by $2$ gives $ 10 $ which can be efficiently used for decimal shifting, i.e. if an integer '$n$' can be represented in SDTBNS form, then $ n / 10_x $ or $ n times 10_x $ can also represented in SDTBNS only by diving or multiplying '$n$' by $ 10 $.

rawabstract:
We introduce here a generalized method a new Algorithm to find Triple-Base number system and Triple-Base chain and hence in turn Single Digit Triple-Base number system(SDTBNS). The proposed method is not only simpler and faster than the Algorithms to find Double-Base number system or Double-Base chain, experimentally it also returns a shorter length of Triple-Base chain which in turn reduces the size of the look-up-table to find out SDTBNS. The complexity analysis and experimental results shows the novelty of the proposed Algorithm. Moreover when the proposed method is applied to find scalar multiplication in case of Elliptic Curve Cryptography and coefficient multiplication in case of designing digital filter, its efficiency also proves its novelty. Here we have used third base as $5$ because when it is multiplied by $2$ gives $ 10 $ which can be efficiently used for decimal shifting, i.e. if an integer '$n$' can be represented in SDTBNS form, then $ n / 10_x $ or $ n \times 10_x $ can also represented in SDTBNS only by diving or multiplying '$n$' by $ 10 $.

entry:
@Article{Maitra:2012:NAC,
  author =       "Subhashis Maitra and Amitabha Sinha",
  title =        "A new algorithm for computing triple-base number
                 system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "40",
  number =       "4",
  pages =        "3--9",
  month =        sep,
  year =         "2012",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/2411116.2411119",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Dec 11 08:06:57 MST 2012",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "We introduce here a generalized method a new Algorithm
                 to find Triple-Base number system and Triple-Base chain
                 and hence in turn Single Digit Triple-Base number
                 system(SDTBNS). The proposed method is not only simpler
                 and faster than the Algorithms to find Double-Base
                 number system or Double-Base chain, experimentally it
                 also returns a shorter length of Triple-Base chain
                 which in turn reduces the size of the look-up-table to
                 find out SDTBNS. The complexity analysis and
                 experimental results shows the novelty of the proposed
                 Algorithm. Moreover when the proposed method is applied
                 to find scalar multiplication in case of Elliptic Curve
                 Cryptography and coefficient multiplication in case of
                 designing digital filter, its efficiency also proves
                 its novelty. Here we have used third base as $5$
                 because when it is multiplied by $2$ gives $ 10 $ which
                 can be efficiently used for decimal shifting, i.e. if
                 an integer '$n$' can be represented in SDTBNS form,
                 then $ n / 10_x $ or $ n \times 10_x $ can also
                 represented in SDTBNS only by diving or multiplying
                 '$n$' by $ 10 $.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
}


bibtype: article
filename: fparith.bib
label: Masotti:2012:FPN
author: Glauco Masotti
title: Floating-Point Numbers with Error Estimates (revised)
journal: arXiv.org
pages: 1--45
day: 28
month: jan
monthnumber: 1
year: 2012
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1201.5975
subject: Numerical Analysis (cs.NA)
acknowledgement: ack-nhfb
rawauthor: Glauco Masotti
rawtitle: Floating-Point Numbers with Error Estimates (revised)
abstract:
The study addresses the problem of precision in floating-point (FP) computations. A method for estimating the errors which affect intermediate and final results is proposed and a summary of many software simulations is discussed. The basic idea consists of representing FP numbers by means of a data structure collecting value and estimated error information. Under certain constraints, the estimate of the absolute error is accurate and has a compact statistical distribution. By monitoring the estimated relative error during a computation (an ad-hoc definition of relative error has been used), the validity of results can be ensured. The error estimate enables the implementation of robust algorithms, and the detection of ill-conditioned problems. A dynamic extension of number precision, under the control of error estimates, is advocated, in order to compute results within given error bounds. A reduced time penalty could be achieved by a specialized FP processor. The realization of a hardwired processor incorporating the method, with current technology, should not be anymore a problem and would make the practical adoption of the method feasible for most applications.

rawabstract:
The study addresses the problem of precision in floating-point (FP) computations. A method for estimating the errors which affect intermediate and final results is proposed and a summary of many software simulations is discussed. The basic idea consists of representing FP numbers by means of a data structure collecting value and estimated error information. Under certain constraints, the estimate of the absolute error is accurate and has a compact statistical distribution. By monitoring the estimated relative error during a computation (an ad-hoc definition of relative error has been used), the validity of results can be ensured. The error estimate enables the implementation of robust algorithms, and the detection of ill-conditioned problems. A dynamic extension of number precision, under the control of error estimates, is advocated, in order to compute results within given error bounds. A reduced time penalty could be achieved by a specialized FP processor. The realization of a hardwired processor incorporating the method, with current technology, should not be anymore a problem and would make the practical adoption of the method feasible for most applications.

entry:
@Article{Masotti:2012:FPN,
  author =       "Glauco Masotti",
  title =        "Floating-Point Numbers with Error Estimates
                 (revised)",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--45",
  day =          "28",
  month =        jan,
  year =         "2012",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1201.5975",
  abstract =     "The study addresses the problem of precision in
                 floating-point (FP) computations. A method for
                 estimating the errors which affect intermediate and
                 final results is proposed and a summary of many
                 software simulations is discussed. The basic idea
                 consists of representing FP numbers by means of a data
                 structure collecting value and estimated error
                 information. Under certain constraints, the estimate of
                 the absolute error is accurate and has a compact
                 statistical distribution. By monitoring the estimated
                 relative error during a computation (an ad-hoc
                 definition of relative error has been used), the
                 validity of results can be ensured. The error estimate
                 enables the implementation of robust algorithms, and
                 the detection of ill-conditioned problems. A dynamic
                 extension of number precision, under the control of
                 error estimates, is advocated, in order to compute
                 results within given error bounds. A reduced time
                 penalty could be achieved by a specialized FP
                 processor. The realization of a hardwired processor
                 incorporating the method, with current technology,
                 should not be anymore a problem and would make the
                 practical adoption of the method feasible for most
                 applications.",
  acknowledgement = ack-nhfb,
  subject =      "Numerical Analysis (cs.NA)",
}


bibtype: misc
filename: fparith.bib
label: McCalpin:2012:OSH
author: J. D. McCalpin
title: Is ``ordered summation'' a hard problem to speed up?
pages: 1--45
day: 28
month: may
monthnumber: 5
year: 2012
bibdate: Sat Oct 31 07:16:11 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.10.31 07:16:11 ???
URL: http://blogs.utexas.edu/jdm4372/2012/02/15/is-ordered-summation-a-hard-problem-to-speed-up/
acknowledgement: ack-nhfb
howpublished: Web document
rawauthor: J. D. McCalpin
rawtitle: Is ``ordered summation'' a hard problem to speed up?
entry:
@Misc{McCalpin:2012:OSH,
  author =       "J. D. McCalpin",
  title =        "Is ``ordered summation'' a hard problem to speed up?",
  howpublished = "Web document",
  day =          "28",
  month =        may,
  year =         "2012",
  bibdate =      "Sat Oct 31 07:16:11 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://blogs.utexas.edu/jdm4372/2012/02/15/is-ordered-summation-a-hard-problem-to-speed-up/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Milicevic:2012:PAO
author: Aleksandar Milicevic and Daniel Jackson
title: Preventing Arithmetic Overflows in Alloy
journal: j-LECT-NOTES-COMP-SCI
volume: 7316
pages: 108--121
year: 2012
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-30885-7_8
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Mon Dec 24 07:32:30 MST 2012
bibtimestamp: 2012.12.24 07:32:30 MST
URL: http://link.springer.com/content/pdf/10.1007/978-3-642-30885-7_8
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-642-30885-7
bookURL: http://www.springerlink.com/content/978-3-642-30885-7
journalURL: http://link.springer.com/bookseries/558
rawauthor: Aleksandar Milicevic and Daniel Jackson
rawtitle: Preventing Arithmetic Overflows in {Alloy}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs2012e.bib

entry:
@Article{Milicevic:2012:PAO,
  author =       "Aleksandar Milicevic and Daniel Jackson",
  title =        "Preventing Arithmetic Overflows in {Alloy}",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "7316",
  pages =        "108--121",
  year =         "2012",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-30885-7_8",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Mon Dec 24 07:32:30 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs2012e.bib",
  URL =          "http://link.springer.com/content/pdf/10.1007/978-3-642-30885-7_8",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-642-30885-7",
  book-URL =     "http://www.springerlink.com/content/978-3-642-30885-7",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: inproceedings
filename: fparith.bib
label: Mine:2012:ADB
author: Antoine Mine
editor: Gudmund Grov
title: Abstract domains for bit-level machine integer and floating-point operations
publisher: pub-ELSEVIER
address: pub-ELSEVIER:adr
pages: 16
year: 2012
bibdate: Sat Jun 4 17:14:37 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.06.04 17:14:37 ???
acknowledgement: ack-nhfb
rawauthor: Antoine Min{\'e}
raweditor: Gudmund Grov
rawtitle: Abstract domains for bit-level machine integer and floating-point operations
booktitle:
WING'12 --- 4th International Workshop on Invariant Generation, held on June 30, 2012 in Manchester, UK

rawbooktitle:
{WING'12 --- 4th International Workshop on Invariant Generation, held on June 30, 2012 in Manchester, UK}

entry:
@InProceedings{Mine:2012:ADB,
  author =       "Antoine Min{\'e}",
  editor =       "Gudmund Grov",
  booktitle =    "{WING'12 --- 4th International Workshop on Invariant
                 Generation, held on June 30, 2012 in Manchester, UK}",
  title =        "Abstract domains for bit-level machine integer and
                 floating-point operations",
  publisher =    pub-ELSEVIER,
  address =      pub-ELSEVIER:adr,
  pages =        "16",
  year =         "2012",
  bibdate =      "Sat Jun 4 17:14:37 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Mukunoki:2012:PCD
author: Daichi Mukunoki and Daisuke Takahashi
publisher: pub-ACM
address: pub-ACM:adr
pages: 788--790
year: 2012
ISBN: 1-4503-1644-1 OR 1450316441
ISBN13: 978-1-4503-1644-6 OR 9781450316446
bibdate: Wed Nov 14 11:07:15 2012
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2012.11.14 11:07:15 ???
keywords: doubled double precision; quad-double precision; triple precision
acknowledgement: ack-nhfb
rawauthor: Daichi Mukunoki and Daisuke Takahashi
booktitle:
ATIP '12: Proceedings of the ATIP / A*CRC Workshop on Accelerator Technologies for High-Performance Computing: Does Asia Lead the Way?

title:
Performance Comparison of Double, Triple and Quadruple Precision Real and Complex BLAS Subroutines on GPUs (extended abstract)

remark:
From page 788: ``ldots the computation cost of the quadruple precision BLAS subroutines is approximately 20 times more than the double precision subroutines.''

rawbooktitle:
{ATIP '12: Proceedings of the ATIP\slash A*CRC Workshop on Accelerator Technologies for High-Performance Computing: Does Asia Lead the Way?}

rawtitle:
Performance Comparison of Double, Triple and Quadruple Precision Real and Complex {BLAS} Subroutines on {GPUs} (extended abstract)

entry:
@InProceedings{Mukunoki:2012:PCD,
  author =       "Daichi Mukunoki and Daisuke Takahashi",
  editor =       "????",
  booktitle =    "{ATIP '12: Proceedings of the ATIP\slash A*CRC
                 Workshop on Accelerator Technologies for
                 High-Performance Computing: Does Asia Lead the Way?}",
  title =        "Performance Comparison of Double, Triple and Quadruple
                 Precision Real and Complex {BLAS} Subroutines on {GPUs}
                 (extended abstract)",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "788--790",
  year =         "2012",
  ISBN =         "1-4503-1644-1",
  ISBN-13 =      "978-1-4503-1644-6",
  LCCN =         "????",
  bibdate =      "Wed Nov 14 11:07:15 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "doubled double precision; quad-double precision;
                 triple precision",
  remark =       "From page 788: ``\ldots{} the computation cost of the
                 quadruple precision BLAS subroutines is approximately
                 20 times more than the double precision
                 subroutines.''",
}


bibtype: article
filename: fparith.bib
label: Muller:2012:SSV
author: Norbert Th. Muller and Christian Uhrhan
title: Some Steps into Verification of Exact Real Arithmetic
journal: j-LECT-NOTES-COMP-SCI
volume: 7226
pages: 168--173
year: 2012
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-28891-3_17
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Wed Dec 19 15:18:01 MST 2012
bibtimestamp: 2012.12.19 15:18:01 MST
URL: http://link.springer.com/chapter/10.1007/978-3-642-28891-3_17/
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-642-28891-3
bookURL: http://www.springerlink.com/content/978-3-642-28891-3
journalURL: http://link.springer.com/bookseries/558
rawauthor: Norbert Th. M{\"u}ller and Christian Uhrhan
rawtitle: Some Steps into Verification of Exact Real Arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs2012c.bib

entry:
@Article{Muller:2012:SSV,
  author =       "Norbert Th. M{\"u}ller and Christian Uhrhan",
  title =        "Some Steps into Verification of Exact Real
                 Arithmetic",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "7226",
  pages =        "168--173",
  year =         "2012",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-28891-3_17",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Wed Dec 19 15:18:01 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs2012c.bib",
  URL =          "http://link.springer.com/chapter/10.1007/978-3-642-28891-3_17/",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-642-28891-3",
  book-URL =     "http://www.springerlink.com/content/978-3-642-28891-3",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Nehmeier:2012:SHI
author: M. Nehmeier and S. Siegel and J. Wolff von Gudenberg
title: Specification of hardware for interval arithmetic
journal: j-COMPUTING
volume: 94
number: 2--4
pages: 243--255
month: mar
monthnumber: 3
year: 2012
CODEN: CMPTA2
DOI: https://doi.org/10.1007/s00607-012-0185-0
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
bibdate: Mon Apr 9 16:41:18 MDT 2012
bibtimestamp: 2012.04.09 16:41:18 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=94&issue=2&spage=243
fjournal: Computing
keywords: Hardware design; Interval arithmetic; Interval standardization
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/607
rawauthor: M. Nehmeier and S. Siegel and J. Wolff von Gudenberg
rawtitle: Specification of hardware for interval arithmetic
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=94&issue=2; https://www.math.utah.edu/pub/tex/bib/computing.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

remark:
Special Issue on GAMM--IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN2010).

entry:
@Article{Nehmeier:2012:SHI,
  author =       "M. Nehmeier and S. Siegel and J. Wolff von Gudenberg",
  title =        "Specification of hardware for interval arithmetic",
  journal =      j-COMPUTING,
  volume =       "94",
  number =       "2--4",
  pages =        "243--255",
  month =        mar,
  year =         "2012",
  CODEN =        "CMPTA2",
  DOI =          "https://doi.org/10.1007/s00607-012-0185-0",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  bibdate =      "Mon Apr 9 16:41:18 MDT 2012",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=94&issue=2;
                 https://www.math.utah.edu/pub/tex/bib/computing.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=94&issue=2&spage=243",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing",
  journal-URL =  "http://link.springer.com/journal/607",
  keywords =     "Hardware design; Interval arithmetic; Interval
                 standardization",
  remark =       "Special Issue on GAMM--IMACS International Symposium
                 on Scientific Computing, Computer Arithmetic and
                 Validated Numerics (SCAN2010).",
}


bibtype: article
filename: fparith.bib
label: Neron:2012:FPS
author: Pierre Neron
title: A Formal Proof of Square Root and Division Elimination in Embedded Programs
journal: j-LECT-NOTES-COMP-SCI
volume: 7679
pages: 256--272
year: 2012
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-35308-6_20
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Sun Dec 16 12:08:25 MST 2012
bibtimestamp: 2012.12.16 12:08:25 MST
URL: http://www.springerlink.com//chapter/10.1007/978-3-642-35308-6_20/
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-642-35308-6Certified Programs and Proofs
bookURL: http://www.springerlink.com/content/978-3-642-35308-6
journalURL: http://link.springer.com/bookseries/558
rawauthor: Pierre Neron
rawtitle: A Formal Proof of Square Root and Division Elimination in Embedded Programs
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs2012l.bib

entry:
@Article{Neron:2012:FPS,
  author =       "Pierre Neron",
  title =        "A Formal Proof of Square Root and Division Elimination
                 in Embedded Programs",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "7679",
  pages =        "256--272",
  year =         "2012",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-35308-6_20",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Sun Dec 16 12:08:25 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs2012l.bib",
  URL =          "http://www.springerlink.com//chapter/10.1007/978-3-642-35308-6_20/",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-642-35308-6Certified
                 Programs and Proofs",
  book-URL =     "http://www.springerlink.com/content/978-3-642-35308-6",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Oudjida:2012:NHR
author: A. K. Oudjida and N. Chaillet and M. L. Berrandjia and A. Liacha
journal: j-COMP-ARCH-NEWS
volume: 40
number: 4
pages: 32--43
month: sep
monthnumber: 9
year: 2012
CODEN: CANED2
DOI: https://doi.org/10.1145/2411116.2411122
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Tue Dec 11 08:06:57 MST 2012
bibtimestamp: 2012.12.11 08:06:57 MST
fjournal: ACM SIGARCH Computer Architecture News
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J89
rawauthor: A. K. Oudjida and N. Chaillet and M. L. Berrandjia and A. Liacha
title:
A new high radix-2 $r$ ($ r geq 8 $) multibit recoding algorithm for large operand size ($ N geq 32 $) multipliers

abstract:
This paper addresses the problem of multiplication with large operand sizes ($ N geq 32 $). We propose a new recursive recoding algorithm that shortens the critical path of the multiplier and reduces the hardware complexity of partial-product-generators as well. The new recoding algorithm provides an optimal space/time partitioning of the multiplier architecture for any size $N$ of the operands. As a result, the critical path is drastically reduced to $ 3^3 sqrt N / 2 - 3 $ with no area overhead in comparison to modified Booth algorithm that shows a critical path of $ N / 2 $ in adder stages. For instance, only $7$ adder stages are needed for a 64-bit two's complement multiplier. Confronted to reference algorithms for $ N = 64 $, important gain ratios of $ 1.62 $, $ 1.71 $, $ 2.64 $ are obtained in terms of multiply-time, energy consumption per multiply operation, and total gate count, respectively.

rawabstract:
This paper addresses the problem of multiplication with large operand sizes ($ N \geq 32 $). We propose a new recursive recoding algorithm that shortens the critical path of the multiplier and reduces the hardware complexity of partial-product-generators as well. The new recoding algorithm provides an optimal space/time partitioning of the multiplier architecture for any size $N$ of the operands. As a result, the critical path is drastically reduced to $ 3^3 \sqrt N / 2 - 3 $ with no area overhead in comparison to modified Booth algorithm that shows a critical path of $ N / 2 $ in adder stages. For instance, only $7$ adder stages are needed for a 64-bit two's complement multiplier. Confronted to reference algorithms for $ N = 64 $, important gain ratios of $ 1.62 $, $ 1.71 $, $ 2.64 $ are obtained in terms of multiply-time, energy consumption per multiply operation, and total gate count, respectively.

rawtitle:
A new high radix-2 $r$ ($ r \geq 8 $) multibit recoding algorithm for large operand size ({$ N \geq 32 $}) multipliers

entry:
@Article{Oudjida:2012:NHR,
  author =       "A. K. Oudjida and N. Chaillet and M. L. Berrandjia and
                 A. Liacha",
  title =        "A new high radix-2 $r$ ($ r \geq 8 $) multibit
                 recoding algorithm for large operand size ({$ N \geq 32
                 $}) multipliers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "40",
  number =       "4",
  pages =        "32--43",
  month =        sep,
  year =         "2012",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/2411116.2411122",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Dec 11 08:06:57 MST 2012",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This paper addresses the problem of multiplication
                 with large operand sizes ($ N \geq 32 $). We propose a
                 new recursive recoding algorithm that shortens the
                 critical path of the multiplier and reduces the
                 hardware complexity of partial-product-generators as
                 well. The new recoding algorithm provides an optimal
                 space/time partitioning of the multiplier architecture
                 for any size $N$ of the operands. As a result, the
                 critical path is drastically reduced to $ 3^3 \sqrt N /
                 2 - 3 $ with no area overhead in comparison to modified
                 Booth algorithm that shows a critical path of $ N / 2 $
                 in adder stages. For instance, only $7$ adder stages
                 are needed for a 64-bit two's complement multiplier.
                 Confronted to reference algorithms for $ N = 64 $,
                 important gain ratios of $ 1.62 $, $ 1.71 $, $ 2.64 $
                 are obtained in terms of multiply-time, energy
                 consumption per multiply operation, and total gate
                 count, respectively.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
}


bibtype: article
filename: fparith.bib
label: Ozaki:2012:FAF
author: Katsuhisa Ozaki and Takeshi Ogita and Siegfried M. Rump and Shin'ichi Oishi
title: Fast algorithms for floating-point interval matrix multiplication
journal: j-J-COMPUT-APPL-MATH
volume: 236
number: 7
pages: 1795--1814
month: jan
monthnumber: 1
year: 2012
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:24:38 MST 2017
bibtimestamp: 2017.02.25 13:24:38 MST
URL: http://www.sciencedirect.com/science/article/pii/S0377042711005449
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Katsuhisa Ozaki and Takeshi Ogita and Siegfried M. Rump and Shin'ichi Oishi
rawtitle: Fast algorithms for floating-point interval matrix multiplication
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2010.bib

entry:
@Article{Ozaki:2012:FAF,
  author =       "Katsuhisa Ozaki and Takeshi Ogita and Siegfried M.
                 Rump and Shin'ichi Oishi",
  title =        "Fast algorithms for floating-point interval matrix
                 multiplication",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "236",
  number =       "7",
  pages =        "1795--1814",
  month =        jan,
  year =         "2012",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:24:38 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2010.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042711005449",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: phdthesis
filename: fparith.bib
label: Panhaleux:2012:CFP
author: A. Panhaleux
title: Contributions to floating-point arithmetic: Coding and correct rounding of algebraic functions
type: Ph.D. dissertation
school: Ecole Normale Superieure de Lyon
address: Lyon, France
pages: 1795--1814
year: 2012
bibdate: Sun Jun 19 15:08:09 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.06.19 15:08:09 ???
URL: https://theses.hal.science/tel-00744373v1
acknowledgement: ack-nhfb
rawauthor: A. Panhaleux
rawtitle: Contributions to floating-point arithmetic: Coding and correct rounding of algebraic functions
abstract:
Efficient and reliable computer arithmetic is a key requirement to perform fast and reliable numerical computations. The choice of the number system and the choice of the arithmetic algorithms are important. We present a new representation of numbers, the ``RN-codings'', such that truncating a RN-coded number to some position is equivalent to rounding it to the nearest. We give some arithmetic algorithms for manipulating RN-codings and introduce the concept of ``floating-point RN-codings''. When implementing a function f in floating-point arithmetic, if we wish to always return the floating-point number nearest $ f(x) $, one must be able to determine if $ f(x) $ is above or below the closest ``midpoint'', where a midpoint is the middle of two consecutive floating-point numbers. This determination is first done with some given precision, and if it does not suffice, we start again with higher precision, and so on. This process may not terminate if $ f(x) $ can be a midpoint. Given an algebraic function $f$, we try either to show that there are no floating-point numbers $x$ such that $ f(x)$ is a midpoint, or we try to enumerate or characterize them. Since the IBM PowerPC, binary division has frequently been implemented using variants of the Newton-Raphson iteration due to Peter Markstein. This iteration is very fast, but much care is needed if we aim at always returning the floating-point number nearest the exact quotient. We investigate a way of efficiently merging Markstein iterations with faster yet less accurate iterations called Goldschmidt iterations. We also investigate whether those iterations can be used for decimal floating-point arithmetic. We provide sure and tight error bounds for these algorithms.

rawabstract:
Efficient and reliable computer arithmetic is a key requirement to perform fast and reliable numerical computations. The choice of the number system and the choice of the arithmetic algorithms are important. We present a new representation of numbers, the ``RN-codings'', such that truncating a RN-coded number to some position is equivalent to rounding it to the nearest. We give some arithmetic algorithms for manipulating RN-codings and introduce the concept of ``floating-point RN-codings''. When implementing a function f in floating-point arithmetic, if we wish to always return the floating-point number nearest $ f(x) $, one must be able to determine if $ f(x) $ is above or below the closest ``midpoint'', where a midpoint is the middle of two consecutive floating-point numbers. This determination is first done with some given precision, and if it does not suffice, we start again with higher precision, and so on. This process may not terminate if $ f(x) $ can be a midpoint. Given an algebraic function $f$, we try either to show that there are no floating-point numbers $x$ such that $ f(x)$ is a midpoint, or we try to enumerate or characterize them. Since the IBM PowerPC, binary division has frequently been implemented using variants of the Newton-Raphson iteration due to Peter Markstein. This iteration is very fast, but much care is needed if we aim at always returning the floating-point number nearest the exact quotient. We investigate a way of efficiently merging Markstein iterations with faster yet less accurate iterations called Goldschmidt iterations. We also investigate whether those iterations can be used for decimal floating-point arithmetic. We provide sure and tight error bounds for these algorithms.

entry:
@PhdThesis{Panhaleux:2012:CFP,
  author =       "A. Panhaleux",
  title =        "Contributions to floating-point arithmetic: Coding and
                 correct rounding of algebraic functions",
  type =         "{Ph.D.} dissertation",
  school =       "{\'E}cole Normale Sup{\'e}rieure de Lyon",
  address =      "Lyon, France",
  year =         "2012",
  bibdate =      "Sun Jun 19 15:08:09 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://theses.hal.science/tel-00744373v1",
  abstract =     "Efficient and reliable computer arithmetic is a key
                 requirement to perform fast and reliable numerical
                 computations. The choice of the number system and the
                 choice of the arithmetic algorithms are important. We
                 present a new representation of numbers, the
                 ``RN-codings'', such that truncating a RN-coded number
                 to some position is equivalent to rounding it to the
                 nearest. We give some arithmetic algorithms for
                 manipulating RN-codings and introduce the concept of
                 ``floating-point RN-codings''. When implementing a
                 function f in floating-point arithmetic, if we wish to
                 always return the floating-point number nearest $ f(x)
                 $, one must be able to determine if $ f(x) $ is above
                 or below the closest ``midpoint'', where a midpoint is
                 the middle of two consecutive floating-point numbers.
                 This determination is first done with some given
                 precision, and if it does not suffice, we start again
                 with higher precision, and so on. This process may not
                 terminate if $ f(x) $ can be a midpoint. Given an
                 algebraic function $f$, we try either to show that
                 there are no floating-point numbers $x$ such that $
                 f(x)$ is a midpoint, or we try to enumerate or
                 characterize them. Since the IBM PowerPC, binary
                 division has frequently been implemented using variants
                 of the Newton-Raphson iteration due to Peter Markstein.
                 This iteration is very fast, but much care is needed if
                 we aim at always returning the floating-point number
                 nearest the exact quotient. We investigate a way of
                 efficiently merging Markstein iterations with faster
                 yet less accurate iterations called Goldschmidt
                 iterations. We also investigate whether those
                 iterations can be used for decimal floating-point
                 arithmetic. We provide sure and tight error bounds for
                 these algorithms.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Rodriguez:2012:RRE
author: Marcos Rodriguez and Roberto Barrio
title: Reducing rounding errors and achieving Brouwer's law with Taylor Series Method
journal: j-APPL-NUM-MATH
volume: 62
number: 8
pages: 1014--1024
month: aug
monthnumber: 8
year: 2012
CODEN: ANMAEL
DOI: https://doi.org/10.1016/j.apnum.2012.03.008
ISSN: 0168-9274 (print), 1873-5460 (electronic) OR 01689274 (print), 18735460 (electronic)
ISSNL: 0168-9274 OR 01689274
bibdate: Sat Apr 28 09:37:06 MDT 2012
bibtimestamp: 2012.04.28 09:37:06 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0168927412000645
fjournal: Applied Numerical Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/01689274/
rawauthor: Marcos Rodr{\'\i}guez and Roberto Barrio
rawtitle: Reducing rounding errors and achieving {Brouwer}'s law with {Taylor Series Method}
bibsource:
https://www.math.utah.edu/pub/tex/bib/applnummath.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Rodriguez:2012:RRE,
  author =       "Marcos Rodr{\'\i}guez and Roberto Barrio",
  title =        "Reducing rounding errors and achieving {Brouwer}'s law
                 with {Taylor Series Method}",
  journal =      j-APPL-NUM-MATH,
  volume =       "62",
  number =       "8",
  pages =        "1014--1024",
  month =        aug,
  year =         "2012",
  CODEN =        "ANMAEL",
  DOI =          "https://doi.org/10.1016/j.apnum.2012.03.008",
  ISSN =         "0168-9274 (print), 1873-5460 (electronic)",
  ISSN-L =       "0168-9274",
  bibdate =      "Sat Apr 28 09:37:06 MDT 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/applnummath.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0168927412000645",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Numerical Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01689274/",
}


bibtype: article
filename: fparith.bib
label: Rump:2012:EEF
author: Siegfried M. Rump
title: Error estimation of floating-point summation and dot product
journal: j-BIT-NUM-MATH
volume: 52
number: 1
pages: 201--220
month: mar
monthnumber: 3
year: 2012
CODEN: BITTEL, NBITAB
DOI: https://doi.org/10.1007/s10543-011-0342-4
ISSN: 0006-3835 (print), 1572-9125 (electronic) OR 00063835 (print), 15729125 (electronic)
ISSNL: 0006-3835 OR 00063835
bibdate: Mon Apr 9 17:00:06 MDT 2012
bibtimestamp: 2012.04.09 17:00:06 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0006-3835&volume=52&issue=1&spage=201
fjournal: BIT Numerical Mathematics
keywords: accurate floating-point dot product; accurate floating-point summation
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10543
rawauthor: Siegfried M. Rump
rawtitle: Error estimation of floating-point summation and dot product
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0006-3835&volume=52&issue=1; https://www.math.utah.edu/pub/tex/bib/bit.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
We improve the well-known Wilkinson-type estimates for the error of standard floating-point recursive summation and dot product by up to a factor 2. The bounds are valid when computed in rounding to nearest, no higher order terms are necessary, and they are best possible. For summation there is no restriction on the number of summands. The proofs are short by using a new tool for the estimation of errors in floating-point computations which cures drawbacks of the ``unit in the last place (ulp)''. The presented estimates are nice and simple, and closer to what one may expect.

rawabstract:
We improve the well-known Wilkinson-type estimates for the error of standard floating-point recursive summation and dot product by up to a factor 2. The bounds are valid when computed in rounding to nearest, no higher order terms are necessary, and they are best possible. For summation there is no restriction on the number of summands. The proofs are short by using a new tool for the estimation of errors in floating-point computations which cures drawbacks of the ``unit in the last place (ulp)''. The presented estimates are nice and simple, and closer to what one may expect.

entry:
@Article{Rump:2012:EEF,
  author =       "Siegfried M. Rump",
  title =        "Error estimation of floating-point summation and dot
                 product",
  journal =      j-BIT-NUM-MATH,
  volume =       "52",
  number =       "1",
  pages =        "201--220",
  month =        mar,
  year =         "2012",
  CODEN =        "BITTEL, NBITAB",
  DOI =          "https://doi.org/10.1007/s10543-011-0342-4",
  ISSN =         "0006-3835 (print), 1572-9125 (electronic)",
  ISSN-L =       "0006-3835",
  bibdate =      "Mon Apr 9 17:00:06 MDT 2012",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0006-3835&volume=52&issue=1;
                 https://www.math.utah.edu/pub/tex/bib/bit.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0006-3835&volume=52&issue=1&spage=201",
  abstract =     "We improve the well-known Wilkinson-type estimates for
                 the error of standard floating-point recursive
                 summation and dot product by up to a factor 2. The
                 bounds are valid when computed in rounding to nearest,
                 no higher order terms are necessary, and they are best
                 possible. For summation there is no restriction on the
                 number of summands. The proofs are short by using a new
                 tool for the estimation of errors in floating-point
                 computations which cures drawbacks of the ``unit in the
                 last place (ulp)''. The presented estimates are nice
                 and simple, and closer to what one may expect.",
  acknowledgement = ack-nhfb,
  fjournal =     "BIT Numerical Mathematics",
  journal-URL =  "http://link.springer.com/journal/10543",
  keywords =     "accurate floating-point dot product; accurate
                 floating-point summation",
}


bibtype: article
filename: fparith.bib
label: Rump:2012:FIM
author: Siegfried M. Rump
title: Fast interval matrix multiplication
journal: j-NUMER-ALGORITHMS
volume: 61
number: 1
pages: 1--34
month: sep
monthnumber: 9
year: 2012
CODEN: NUALEG
ISSN: 1017-1398 (print), 1572-9265 (electronic) OR 10171398 (print), 15729265 (electronic)
ISSNL: 1017-1398 OR 10171398
bibdate: Wed Mar 6 09:10:18 MST 2013
bibtimestamp: 2013.03.06 09:10:18 MST
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=1017-1398&volume=61&issue=1&spage=1
fjournal: Numerical Algorithms
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11075
rawauthor: Siegfried M. Rump
rawtitle: Fast interval matrix multiplication
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=1017-1398&volume=61&issue=1; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/numeralgorithms.bib

entry:
@Article{Rump:2012:FIM,
  author =       "Siegfried M. Rump",
  title =        "Fast interval matrix multiplication",
  journal =      j-NUMER-ALGORITHMS,
  volume =       "61",
  number =       "1",
  pages =        "1--34",
  month =        sep,
  year =         "2012",
  CODEN =        "NUALEG",
  ISSN =         "1017-1398 (print), 1572-9265 (electronic)",
  ISSN-L =       "1017-1398",
  bibdate =      "Wed Mar 6 09:10:18 MST 2013",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=1017-1398&volume=61&issue=1;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/numeralgorithms.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=1017-1398&volume=61&issue=1&spage=1",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerical Algorithms",
  journal-URL =  "http://link.springer.com/journal/11075",
}


bibtype: article
filename: fparith.bib
label: Saha:2012:DHS
author: Prabir Saha and Arindam Banerjee and Anup Dandapat and Partha Bhattacharyya
title: Design of High Speed Vedic Multiplier for Decimal Number System
journal: j-LECT-NOTES-COMP-SCI
volume: 7373
pages: 79--88
year: 2012
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-31494-0_10
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Wed Dec 19 15:21:09 MST 2012
bibtimestamp: 2012.12.19 15:21:09 MST
URL: http://link.springer.com/chapter/10.1007/978-3-642-31494-0_10/
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-642-31494-0
bookURL: http://www.springerlink.com/content/978-3-642-31494-0
journalURL: http://link.springer.com/bookseries/558
rawauthor: Prabir Saha and Arindam Banerjee and Anup Dandapat and Partha Bhattacharyya
rawtitle: Design of High Speed {Vedic} Multiplier for Decimal Number System
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs2012f.bib

entry:
@Article{Saha:2012:DHS,
  author =       "Prabir Saha and Arindam Banerjee and Anup Dandapat and
                 Partha Bhattacharyya",
  title =        "Design of High Speed {Vedic} Multiplier for Decimal
                 Number System",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "7373",
  pages =        "79--88",
  year =         "2012",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-31494-0_10",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Wed Dec 19 15:21:09 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs2012f.bib",
  URL =          "http://link.springer.com/chapter/10.1007/978-3-642-31494-0_10/",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-642-31494-0",
  book-URL =     "http://www.springerlink.com/content/978-3-642-31494-0",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Saito:2012:AGM
author: Tsubasa Saito and Emiko Ishiwata and Hidehiko Hasegawa
title: Analysis of the GCR method with mixed precision arithmetic using QuPAT
journal: j-J-COMPUT-SCI
volume: 3
number: 3
pages: 87--91
month: may
monthnumber: 5
year: 2012
DOI: https://doi.org/10.1016/j.jocs.2011.05.001
ISSN: 1877-7503 (print), 1877-7511 (electronic) OR 18777503 (print), 18777511 (electronic)
ISSNL: 1877-7503 OR 18777503
bibdate: Tue Sep 19 13:53:15 MDT 2023
bibtimestamp: 2023.09.19 13:53:15 MDT
URL: https://www.sciencedirect.com/science/article/pii/S1877750311000329
fjournal: Journal of Computational Science
acknowledgement: ack-nhfb
ajournal: J. Comput. Sci.
journalURL: https://www.sciencedirect.com/journal/journal-of-computational-science
rawauthor: Tsubasa Saito and Emiko Ishiwata and Hidehiko Hasegawa
rawtitle: Analysis of the {GCR} method with mixed precision arithmetic using {QuPAT}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputsci.bib

entry:
@Article{Saito:2012:AGM,
  author =       "Tsubasa Saito and Emiko Ishiwata and Hidehiko
                 Hasegawa",
  title =        "Analysis of the {GCR} method with mixed precision
                 arithmetic using {QuPAT}",
  journal =      j-J-COMPUT-SCI,
  volume =       "3",
  number =       "3",
  pages =        "87--91",
  month =        may,
  year =         "2012",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1016/j.jocs.2011.05.001",
  ISSN =         "1877-7503 (print), 1877-7511 (electronic)",
  ISSN-L =       "1877-7503",
  bibdate =      "Tue Sep 19 13:53:15 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputsci.bib",
  URL =          "https://www.sciencedirect.com/science/article/pii/S1877750311000329",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Comput. Sci.",
  fjournal =     "Journal of Computational Science",
  journal-URL =  "https://www.sciencedirect.com/journal/journal-of-computational-science",
}


bibtype: article
filename: fparith.bib
label: Seo:2012:MPM
author: Hwajeong Seo and Howon Kim
title: Multi-precision Multiplication for Public-Key Cryptography on Embedded Microprocessors
journal: j-LECT-NOTES-COMP-SCI
volume: 7690
pages: 55--67
year: 2012
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-35416-8_5
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Wed Dec 19 15:18:58 MST 2012
bibtimestamp: 2012.12.19 15:18:58 MST
URL: http://link.springer.com/chapter/10.1007/978-3-642-35416-8_5/
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-642-35416-8
bookURL: http://www.springerlink.com/content/978-3-642-35416-8
journalURL: http://link.springer.com/bookseries/558
rawauthor: Hwajeong Seo and Howon Kim
rawtitle: Multi-precision Multiplication for Public-Key Cryptography on Embedded Microprocessors
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs2012l.bib

entry:
@Article{Seo:2012:MPM,
  author =       "Hwajeong Seo and Howon Kim",
  title =        "Multi-precision Multiplication for Public-Key
                 Cryptography on Embedded Microprocessors",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "7690",
  pages =        "55--67",
  year =         "2012",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-35416-8_5",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Wed Dec 19 15:18:58 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs2012l.bib",
  URL =          "http://link.springer.com/chapter/10.1007/978-3-642-35416-8_5/",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-642-35416-8",
  book-URL =     "http://www.springerlink.com/content/978-3-642-35416-8",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: inproceedings
filename: fparith.bib
label: Sheikh:2012:AFP
author: Basit Riaz Sheikh and Rajit Manohar
editor: IEEE
title: An Asynchronous Floating-Point Multiplier
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 89--96
year: 2012
DOI: https://doi.org/10.1109/ASYNC.2012.19
ISBN: 1-4673-1360-2, 0-7695-4688-9 OR 1467313602, 0769546889
ISBN13: 978-1-4673-1360-5, 978-0-7695-4688-9 OR 9781467313605, 9780769546889
ISSN: 1522-8681 OR 15228681
ISSNL: 1522-8681 OR 15228681
LCCN: TK7868.A79
bibdate: Sat Apr 02 16:30:48 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.04.02 16:30:48 ???
URL: http://ieeexplore.ieee.org/servlet/opac?punumber=6242773
acknowledgement: ack-nhfb
rawauthor: Basit Riaz Sheikh and Rajit Manohar
raweditor: {IEEE}
rawtitle: An Asynchronous Floating-Point Multiplier
booktitle:
2012 IEEE International Symposium on Asynchronous Circuits and Systems: proceedings, ASYNC 2012: 7--9 May 2012, Copenhagen, Denmark

rawbooktitle:
{2012 IEEE International Symposium on Asynchronous Circuits and Systems: proceedings, ASYNC 2012: 7--9 May 2012, Copenhagen, Denmark}

entry:
@InProceedings{Sheikh:2012:AFP,
  author =       "Basit Riaz Sheikh and Rajit Manohar",
  editor =       "{IEEE}",
  booktitle =    "{2012 IEEE International Symposium on Asynchronous
                 Circuits and Systems: proceedings, ASYNC 2012: 7--9 May
                 2012, Copenhagen, Denmark}",
  title =        "An Asynchronous Floating-Point Multiplier",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "89--96",
  year =         "2012",
  DOI =          "https://doi.org/10.1109/ASYNC.2012.19",
  ISBN =         "1-4673-1360-2, 0-7695-4688-9",
  ISBN-13 =      "978-1-4673-1360-5, 978-0-7695-4688-9",
  ISSN =         "1522-8681",
  ISSN-L =       "1522-8681",
  LCCN =         "TK7868.A79",
  bibdate =      "Sat Apr 02 16:30:48 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/servlet/opac?punumber=6242773",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Siegel:2012:LAL
author: Stefan Siegel and Jurgen Wolff von Gudenberg
title: A long accumulator like a carry-save adder
journal: j-COMPUTING
volume: 94
number: 2--4
pages: 203--213
month: mar
monthnumber: 3
year: 2012
CODEN: CMPTA2
DOI: https://doi.org/10.1007/s00607-011-0164-x
ISSN: 0010-485X (print), 1436-5057 (electronic) OR 0010485X (print), 14365057 (electronic)
ISSNL: 0010-485X OR 0010485X
bibdate: Mon Apr 9 16:41:18 MDT 2012
bibtimestamp: 2012.04.09 16:41:18 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=94&issue=2&spage=203
fjournal: Computing
keywords: accurate floating-point dot product; accurate floating-point summation
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/607
rawauthor: Stefan Siegel and J{\"u}rgen Wolff von Gudenberg
rawtitle: A long accumulator like a carry-save adder
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=94&issue=2; https://www.math.utah.edu/pub/tex/bib/computing.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

remark:
Special Issue on GAMM--IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN2010).

entry:
@Article{Siegel:2012:LAL,
  author =       "Stefan Siegel and J{\"u}rgen Wolff von Gudenberg",
  title =        "A long accumulator like a carry-save adder",
  journal =      j-COMPUTING,
  volume =       "94",
  number =       "2--4",
  pages =        "203--213",
  month =        mar,
  year =         "2012",
  CODEN =        "CMPTA2",
  DOI =          "https://doi.org/10.1007/s00607-011-0164-x",
  ISSN =         "0010-485X (print), 1436-5057 (electronic)",
  ISSN-L =       "0010-485X",
  bibdate =      "Mon Apr 9 16:41:18 MDT 2012",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0010-485X&volume=94&issue=2;
                 https://www.math.utah.edu/pub/tex/bib/computing.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=0010-485X&volume=94&issue=2&spage=203",
  acknowledgement = ack-nhfb,
  fjournal =     "Computing",
  journal-URL =  "http://link.springer.com/journal/607",
  keywords =     "accurate floating-point dot product; accurate
                 floating-point summation",
  remark =       "Special Issue on GAMM--IMACS International Symposium
                 on Scientific Computing, Computer Arithmetic and
                 Validated Numerics (SCAN2010).",
}


bibtype: article
filename: fparith.bib
label: Su:2012:IIN
author: Chen Su and Haining Fan
title: Impact of Intel's new instruction sets on software implementation of $ rm GF(2)[x] $ multiplication
journal: j-INFO-PROC-LETT
volume: 112
number: 12
pages: 497--502
day: 30
month: jun
monthnumber: 6
year: 2012
CODEN: IFPLAT
DOI: https://doi.org/10.1016/j.ipl.2012.03.012
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Mon May 21 07:13:00 MDT 2012
bibtimestamp: 2012.05.21 07:13:00 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0020019012000804
fjournal: Information Processing Letters
keywords: AVX; Cryptography; GF(2)[x] multiplication; Karatsuba algorithm; PCLMULQDQ; SSE
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: Chen Su and Haining Fan
bibsource:
http://www.sciencedirect.com/science/journal/00200190; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/infoproc2010.bib

rawtitle:
Impact of {Intel}'s new instruction sets on software implementation of {$ {\rm GF}(2)[x] $} multiplication

entry:
@Article{Su:2012:IIN,
  author =       "Chen Su and Haining Fan",
  title =        "Impact of {Intel}'s new instruction sets on software
                 implementation of {$ {\rm GF}(2)[x] $} multiplication",
  journal =      j-INFO-PROC-LETT,
  volume =       "112",
  number =       "12",
  pages =        "497--502",
  day =          "30",
  month =        jun,
  year =         "2012",
  CODEN =        "IFPLAT",
  DOI =          "https://doi.org/10.1016/j.ipl.2012.03.012",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Mon May 21 07:13:00 MDT 2012",
  bibsource =    "http://www.sciencedirect.com/science/journal/00200190;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/infoproc2010.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0020019012000804",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
  keywords =     "AVX; Cryptography; GF(2)[x] multiplication; Karatsuba
                 algorithm; PCLMULQDQ; SSE",
}


bibtype: article
filename: fparith.bib
label: Swartzlander:2012:FIF
author: Earl E. Swartzlander and Hani H. M. Saleh
title: FFT Implementation with Fused Floating-Point Operations
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 2
pages: 284--288
month: feb
monthnumber: 2
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2010.271
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Jan 13 17:55:10 2012
bibtimestamp: 2012.01.13 17:55:10 ???
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5669293
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
bookURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Earl E. Swartzlander and Hani H. M. Saleh
rawtitle: {FFT} Implementation with Fused Floating-Point Operations
abstract:
This paper applies two fused floating-point operations to the implementation of fast Fourier transform butterfly units. The operations are a fused two-term dot product and a fused add-subtract unit. The FFT `butterfly' operations consist of complex multiplications, additions and subtractions. Both radix-2 and radix-4 butterflies are implemented efficiently with the two fused floating-point operations. When placed and routed using a high performance standard cell technology, the fused FFT butterflies are about 15% faster and 30% smaller than a conventional implementation. Also the numerical results of the fused implementations are slightly more accurate since they use fewer rounding operations.

rawabstract:
This paper applies two fused floating-point operations to the implementation of fast Fourier transform butterfly units. The operations are a fused two-term dot product and a fused add-subtract unit. The FFT `butterfly' operations consist of complex multiplications, additions and subtractions. Both radix-2 and radix-4 butterflies are implemented efficiently with the two fused floating-point operations. When placed and routed using a high performance standard cell technology, the fused FFT butterflies are about 15\% faster and 30\% smaller than a conventional implementation. Also the numerical results of the fused implementations are slightly more accurate since they use fewer rounding operations.

entry:
@Article{Swartzlander:2012:FIF,
  author =       "Earl E. Swartzlander and Hani H. M. Saleh",
  title =        "{FFT} Implementation with Fused Floating-Point
                 Operations",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "2",
  pages =        "284--288",
  month =        feb,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2010.271",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Jan 13 17:55:10 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5669293",
  abstract =     "This paper applies two fused floating-point operations
                 to the implementation of fast Fourier transform
                 butterfly units. The operations are a fused two-term
                 dot product and a fused add-subtract unit. The FFT
                 `butterfly' operations consist of complex
                 multiplications, additions and subtractions. Both
                 radix-2 and radix-4 butterflies are implemented
                 efficiently with the two fused floating-point
                 operations. When placed and routed using a high
                 performance standard cell technology, the fused FFT
                 butterflies are about 15\% faster and 30\% smaller than
                 a conventional implementation. Also the numerical
                 results of the fused implementations are slightly more
                 accurate since they use fewer rounding operations.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  book-URL =     "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Thome:2012:SRA
author: Emmanuel Thome
title: Square Root Algorithms for the Number Field Sieve
journal: j-LECT-NOTES-COMP-SCI
volume: 7369
pages: 208--224
year: 2012
CODEN: LNCSD9
DOI: https://doi.org/10.1007/978-3-642-31662-3_15
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Mon Dec 24 07:44:06 MST 2012
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncs.bib
bibtimestamp: 2012.12.24 07:44:06 MST
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-642-31662-3
bookURL: http://www.springerlink.com/content/978-3-642-31662-3
journalURL: http://link.springer.com/bookseries/558
rawauthor: Emmanuel Thom{\'e}
rawtitle: Square Root Algorithms for the Number Field Sieve
URL:
http://link.springer.com/chapter/10.1007/978-3-642-31662-3_15/; http://link.springer.com/content/pdf/10.1007/978-3-642-31662-3_15

entry:
@Article{Thome:2012:SRA,
  author =       "Emmanuel Thom{\'e}",
  title =        "Square Root Algorithms for the Number Field Sieve",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "7369",
  pages =        "208--224",
  year =         "2012",
  CODEN =        "LNCSD9",
  DOI =          "https://doi.org/10.1007/978-3-642-31662-3_15",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Mon Dec 24 07:44:06 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncs.bib",
  URL =          "http://link.springer.com/chapter/10.1007/978-3-642-31662-3_15/;
                 http://link.springer.com/content/pdf/10.1007/978-3-642-31662-3_15",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-642-31662-3",
  book-URL =     "http://www.springerlink.com/content/978-3-642-31662-3",
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Vazquez:2012:RFP
author: Alvaro Vazquez and Julio Villalba-Moreno and Elisardo Antelo and Emilio L. Zapata
title: Redundant Floating-Point Decimal CORDIC Algorithm
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 11
pages: 1551--1562
month: nov
monthnumber: 11
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2011.217
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Oct 22 08:22:47 2012
bibtimestamp: 2012.10.22 08:22:47 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Alvaro Vazquez and Julio Villalba-Moreno and Elisardo Antelo and Emilio L. Zapata
rawtitle: Redundant Floating-Point Decimal {CORDIC} Algorithm
entry:
@Article{Vazquez:2012:RFP,
  author =       "Alvaro Vazquez and Julio Villalba-Moreno and Elisardo
                 Antelo and Emilio L. Zapata",
  title =        "Redundant Floating-Point Decimal {CORDIC} Algorithm",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "11",
  pages =        "1551--1562",
  month =        nov,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2011.217",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Oct 22 08:22:47 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Wang:2012:EMB
author: Zhen Wang and Shuqin Fan
title: Efficient Montgomery-Based Semi-Systolic Multiplier for Even-Type GNB of $ rm GF(2^m) $
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 3
pages: 415--419
month: mar
monthnumber: 3
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2010.272
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Feb 3 07:35:03 2012
bibtimestamp: 2012.02.03 07:35:03 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Zhen Wang and Shuqin Fan
rawtitle: Efficient {Montgomery}-Based Semi-Systolic Multiplier for Even-Type {GNB} of {$ {\rm GF}(2^m) $}
entry:
@Article{Wang:2012:EMB,
  author =       "Zhen Wang and Shuqin Fan",
  title =        "Efficient {Montgomery}-Based Semi-Systolic Multiplier
                 for Even-Type {GNB} of {$ {\rm GF}(2^m) $}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "3",
  pages =        "415--419",
  month =        mar,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2010.272",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Feb 3 07:35:03 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Wang:2012:RCC
author: Dong Wang and Milos D. Ercegovac
title: A Radix-16 Combined Complex Division / Square Root Unit with Operand Prescaling
journal: j-IEEE-TRANS-COMPUT
volume: 61
number: 9
pages: 1243--1255
month: sep
monthnumber: 9
year: 2012
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2011.143
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Aug 29 17:48:10 2012
bibtimestamp: 2012.08.29 17:48:10 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Dong Wang and Milo{\v{s}} D. Ercegovac
rawtitle: A Radix-16 Combined Complex Division\slash Square Root Unit with Operand Prescaling
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib; https://www.math.utah.edu/pub/tex/bib/mathcw.bib

entry:
@Article{Wang:2012:RCC,
  author =       "Dong Wang and Milo{\v{s}} D. Ercegovac",
  title =        "A Radix-16 Combined Complex Division\slash Square Root
                 Unit with Operand Prescaling",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "61",
  number =       "9",
  pages =        "1243--1255",
  month =        sep,
  year =         "2012",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2011.143",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Aug 29 17:48:10 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcw.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Wang:2012:UBW
editor: ACM
title: Undefined Behavior: What Happened to My Code?
publisher: pub-ACM
address: pub-ACM:adr
pages: 101
year: 2012
DOI: https://doi.org/10.1145/2349896.2349905
ISBN: 1-4503-1669-7 OR 1450316697
ISBN13: 978-1-4503-1669-9 OR 9781450316699
LCCN: QA75.5
bibdate: Thu Feb 18 06:30:11 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/unix.bib
bibtimestamp: 2016.02.18 06:30:11 ???
URL: http://dl.acm.org/citation.cfm?id=2349896
acknowledgement: ack-nhfb
raweditor: {ACM}
rawtitle: Undefined Behavior: What Happened to My Code?
author:
Xi Wang and Haogang Chen and Alvin Cheung and Zhihao Jia and Nickolai Zeldovich and M. Frans Kaashoek

booktitle:
Proceedings of the Asia--Pacific Workshop on Systems: APSys '12, July 23--24, 2012, Seoul, South Korea

abstract:
System programming languages such as C grant compiler writers freedom to generate efficient code for a specific instruction set by defining certain language constructs as undefined behavior. Unfortunately, the rules for what is undefined behavior are subtle and programmers make mistakes that sometimes lead to security vulnerabilities. This position paper argues that the research community should help address the problems that arise from undefined behavior, and not dismiss them as esoteric C implementation issues. We show that these errors do happen in real-world systems, that the issues are tricky, and that current practices to address the issues are insufficient.

remark:
This article exhibits several small code snippets where, because of C's rules of undefined behavior, compilers are free to change, order, or even eliminate, code in unexpected ways. Several of the examples are protective code intended to detect errors, such as division by zero and pointer dereferencing.

rawabstract:
System programming languages such as C grant compiler writers freedom to generate efficient code for a specific instruction set by defining certain language constructs as undefined behavior. Unfortunately, the rules for what is undefined behavior are subtle and programmers make mistakes that sometimes lead to security vulnerabilities. This position paper argues that the research community should help address the problems that arise from undefined behavior, and not dismiss them as esoteric C implementation issues. We show that these errors do happen in real-world systems, that the issues are tricky, and that current practices to address the issues are insufficient.

rawauthor:
Xi Wang and Haogang Chen and Alvin Cheung and Zhihao Jia and Nickolai Zeldovich and M. Frans Kaashoek

rawbooktitle:
Proceedings of the {Asia--Pacific Workshop on Systems: APSys '12, July 23--24, 2012, Seoul, South Korea}

entry:
@InProceedings{Wang:2012:UBW,
  author =       "Xi Wang and Haogang Chen and Alvin Cheung and Zhihao
                 Jia and Nickolai Zeldovich and M. Frans Kaashoek",
  editor =       "{ACM}",
  booktitle =    "Proceedings of the {Asia--Pacific Workshop on Systems:
                 APSys '12, July 23--24, 2012, Seoul, South Korea}",
  title =        "Undefined Behavior: What Happened to My Code?",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "101",
  year =         "2012",
  DOI =          "https://doi.org/10.1145/2349896.2349905",
  ISBN =         "1-4503-1669-7",
  ISBN-13 =      "978-1-4503-1669-9",
  LCCN =         "QA75.5",
  bibdate =      "Thu Feb 18 06:30:11 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/unix.bib",
  URL =          "http://dl.acm.org/citation.cfm?id=2349896",
  abstract =     "System programming languages such as C grant compiler
                 writers freedom to generate efficient code for a
                 specific instruction set by defining certain language
                 constructs as undefined behavior. Unfortunately, the
                 rules for what is undefined behavior are subtle and
                 programmers make mistakes that sometimes lead to
                 security vulnerabilities. This position paper argues
                 that the research community should help address the
                 problems that arise from undefined behavior, and not
                 dismiss them as esoteric C implementation issues. We
                 show that these errors do happen in real-world systems,
                 that the issues are tricky, and that current practices
                 to address the issues are insufficient.",
  acknowledgement = ack-nhfb,
  remark =       "This article exhibits several small code snippets
                 where, because of C's rules of undefined behavior,
                 compilers are free to change, order, or even eliminate,
                 code in unexpected ways. Several of the examples are
                 protective code intended to detect errors, such as
                 division by zero and pointer dereferencing.",
}


