# bibtab

bibtype: article
filename: fparith.bib
label: Hitchcock:2002:NEC
author: Yvonne Hitchcock and Paul Montague
title: A New Elliptic Curve Scalar Multiplication Algorithm to Resist Simple Power Analysis
journal: j-LECT-NOTES-COMP-SCI
volume: 2384
pages: 214--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:10:02 MDT 2002
bibtimestamp: 2002.09.10 19:10:02 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Yvonne Hitchcock and Paul Montague
rawtitle: A New Elliptic Curve Scalar Multiplication Algorithm to Resist Simple Power Analysis
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2384.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2384/23840214.htm; http://link.springer-ny.com/link/service/series/0558/papers/2384/23840214.pdf

entry:
@Article{Hitchcock:2002:NEC,
  author =       "Yvonne Hitchcock and Paul Montague",
  title =        "A New Elliptic Curve Scalar Multiplication Algorithm
                 to Resist Simple Power Analysis",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2384",
  pages =        "214--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:10:02 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2384.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2384/23840214.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2384/23840214.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Hoenninger:2002:FPD
author: J. C. Hoenninger III and L. E. Crooks and M. Arakawa
title: A floating-point digital receiver for MRI
journal: j-IEEE-TRANS-BIOMED-ENG
volume: 49
number: 7
pages: 689--693
month: jul
monthnumber: 7
year: 2002
CODEN: IEBEAX
ISSN: 0018-9294 (print), 1558-2531 (electronic) OR 00189294 (print), 15582531 (electronic)
ISSNL: 0018-9294 OR 00189294
bibdate: Sat Jul 16 08:40:52 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 08:40:52 MDT
fjournal: IEEE Transactions on Biomedical Engineering
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10
rawauthor: J. C. {Hoenninger III} and L. E. Crooks and M. Arakawa
rawtitle: A floating-point digital receiver for {MRI}
entry:
@Article{Hoenninger:2002:FPD,
  author =       "J. C. {Hoenninger III} and L. E. Crooks and M.
                 Arakawa",
  title =        "A floating-point digital receiver for {MRI}",
  journal =      j-IEEE-TRANS-BIOMED-ENG,
  volume =       "49",
  number =       "7",
  pages =        "689--693",
  month =        jul,
  year =         "2002",
  CODEN =        "IEBEAX",
  ISSN =         "0018-9294 (print), 1558-2531 (electronic)",
  ISSN-L =       "0018-9294",
  bibdate =      "Sat Jul 16 08:40:52 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Biomedical Engineering",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10",
  summary =      "A magnetic resonance imaging (MRI) system requires the
                 highest possible signal fidelity and stability for
                 clinical applications. Quadrature analog receivers have
                 problems with channel matching, dc offset and
                 analog-to-digital linearity. Fixed-point \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Honda:2002:DFT
author: M. Honda and H. Harada and M. Fujise
booktitle: VTC Spring 2002, IEEE 55th Vehicular Technology Conference, 6--9 May 2002
volume: 1
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 280--284
year: 2002
DOI: https://doi.org/10.1109/VTC.2002.1002710
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. Honda and H. Harada and M. Fujise
rawbooktitle: {VTC} Spring 2002, {IEEE 55th} Vehicular Technology Conference, 6--9 May 2002
title:
Design of fault-tolerant digital filters based on redundant residue number arithmetic for over-the-air reconfiguration in software radio communication systems

rawtitle:
Design of fault-tolerant digital filters based on redundant residue number arithmetic for over-the-air reconfiguration in software radio communication systems

entry:
@InProceedings{Honda:2002:DFT,
  author =       "M. Honda and H. Harada and M. Fujise",
  booktitle =    "{VTC} Spring 2002, {IEEE 55th} Vehicular Technology
                 Conference, 6--9 May 2002",
  title =        "Design of fault-tolerant digital filters based on
                 redundant residue number arithmetic for over-the-air
                 reconfiguration in software radio communication
                 systems",
  volume =       "1",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "280--284",
  year =         "2002",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/VTC.2002.1002710",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Over-the-air reconfiguration is a key characteristic
                 of software defined radio communication systems. It
                 offers great advantages in terms of cost-effective
                 software deployment to a large number of user
                 terminals. It also enables manufacturers and \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Hug:2002:DBP
author: Hubert Hug and Rainer Schuler
title: DNA-based Parallel Computation of Simple Arithmetic
journal: j-LECT-NOTES-COMP-SCI
volume: 2340
pages: 321--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:09:41 MDT 2002
bibtimestamp: 2002.09.10 19:09:41 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Hubert Hug and Rainer Schuler
rawtitle: {DNA}-based Parallel Computation of Simple Arithmetic
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2340.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2340/23400321.htm; http://link.springer-ny.com/link/service/series/0558/papers/2340/23400321.pdf

entry:
@Article{Hug:2002:DBP,
  author =       "Hubert Hug and Rainer Schuler",
  title =        "{DNA}-based Parallel Computation of Simple
                 Arithmetic",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2340",
  pages =        "321--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:09:41 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2340.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2340/23400321.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2340/23400321.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: misc
filename: fparith.bib
label: Ide:2002:GTE
author: Nobuhiro Ide and Atsushi Kunimatsu and Maki Ueno
pages: 321--??
day: 14
month: may
monthnumber: 5
year: 2002
bibdate: Thu Oct 17 11:19:42 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 11:19:42 ???
URL: https://patents.google.com/patent/US6388672B1
acknowledgement: ack-nhfb
howpublished: US Patent 6,388,672
rawauthor: Nobuhiro Ide and Atsushi Kunimatsu and Maki Ueno
title:
Graphic translate engine, floating point arithmetic unit and floating point multiply-add calculation unit

abstract:
An internal memory section is divided into plural memory blocks. During a period of time, a relevant memory block of the internal memory section is connected to an external memory unit, while another memory block thereof is connected to a data holding section. During a succeeding period of time, the relevant memory block is connected to the data holding section, while the other memory block is connected to the external memory unit. Data exchange between the data holding section and the external memory unit via the internal memory section is performed while the alternative connection is repeated.

remark:
Patent filed 31 January 1997, granted to Toshiba Corporation on 14 May 2002, possibly expired on 31 January 2019.

rawabstract:
An internal memory section is divided into plural memory blocks. During a period of time, a relevant memory block of the internal memory section is connected to an external memory unit, while another memory block thereof is connected to a data holding section. During a succeeding period of time, the relevant memory block is connected to the data holding section, while the other memory block is connected to the external memory unit. Data exchange between the data holding section and the external memory unit via the internal memory section is performed while the alternative connection is repeated.

rawtitle:
Graphic translate engine, floating point arithmetic unit and floating point multiply-add calculation unit

entry:
@Misc{Ide:2002:GTE,
  author =       "Nobuhiro Ide and Atsushi Kunimatsu and Maki Ueno",
  title =        "Graphic translate engine, floating point arithmetic
                 unit and floating point multiply-add calculation unit",
  howpublished = "US Patent 6,388,672",
  day =          "14",
  month =        may,
  year =         "2002",
  bibdate =      "Thu Oct 17 11:19:42 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://patents.google.com/patent/US6388672B1",
  abstract =     "An internal memory section is divided into plural
                 memory blocks. During a period of time, a relevant
                 memory block of the internal memory section is
                 connected to an external memory unit, while another
                 memory block thereof is connected to a data holding
                 section. During a succeeding period of time, the
                 relevant memory block is connected to the data holding
                 section, while the other memory block is connected to
                 the external memory unit. Data exchange between the
                 data holding section and the external memory unit via
                 the internal memory section is performed while the
                 alternative connection is repeated.",
  acknowledgement = ack-nhfb,
  remark =       "Patent filed 31 January 1997, granted to Toshiba
                 Corporation on 14 May 2002, possibly expired on 31
                 January 2019.",
}


bibtype: inproceedings
filename: fparith.bib
label: Iso:2002:NCI
author: Yuusuke Iso and Hiroshi Fujiwara
title: Numerical Computations for Ill-conditioned Problems by Multiple-Precision Systems
crossref: Babuska:2002:MMN
volume: 19
pages: 185--194
year: 2002
DOI: https://doi.org/10.1007/978-3-642-56288-4_13
bibdate: Sat Dec 22 08:36:17 MST 2012
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/lncse.bib
bibtimestamp: 2012.12.22 08:36:17 MST
URL: http://link.springer.com/content/pdf/10.1007/978-3-642-56288-4_13
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1007/978-3-642-56288-4
bookURL: http://www.springerlink.com/content/978-3-642-56288-4
rawauthor: Yuusuke Iso and Hiroshi Fujiwara
rawtitle: Numerical Computations for Ill-conditioned Problems by Multiple-Precision Systems
entry:
@InProceedings{Iso:2002:NCI,
  author =       "Yuusuke Iso and Hiroshi Fujiwara",
  title =        "Numerical Computations for Ill-conditioned Problems by
                 Multiple-Precision Systems",
  crossref =     "Babuska:2002:MMN",
  volume =       "19",
  pages =        "185--194",
  year =         "2002",
  DOI =          "https://doi.org/10.1007/978-3-642-56288-4_13",
  bibdate =      "Sat Dec 22 08:36:17 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/lncse.bib",
  URL =          "http://link.springer.com/content/pdf/10.1007/978-3-642-56288-4_13",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1007/978-3-642-56288-4",
  book-URL =     "http://www.springerlink.com/content/978-3-642-56288-4",
}


bibtype: phdthesis
filename: fparith.bib
label: Jacobi:2002:FVF
author: Christian Jacobi
title: Formal verification of a fully IEEE compliant floating point unit
type: Ph.D. thesis
address: Saarbrucken, Germany
pages: 185--194
year: 2002
bibdate: Tue May 07 16:38:40 2024
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2024.05.07 16:38:40 ???
acknowledgement: ack-nhfb
rawauthor: Christian Jacobi
rawtitle: Formal verification of a fully {IEEE} compliant floating point unit
school:
Universitat Saarbrucken Fakultat 6 --- Naturwissenschaftlich-Technische Fakultat I. Fachrichtung 6.2 --- Informatik

abstract:
In this thesis we describe the formal verification of a fully IEEE compliant floating point unit (FPU). The hardware is verified on the gate-level against a formalization of the IEEE standard. The verification is performed using the theorem proving system PVS. The FPU supports both single and double precision floating point numbers, normal and denormal numbers, all four IEEE rounding modes, and exceptions as required by the standard. Beside the verification of the combinatorial correctness of the FPUs we pipeline the FPUs to allow the integration into an out-of-order processor. We formally define the correctness criterion the pipelines must obey in order to work properly within the processor. We then describe a new methodology based on combining model checking and theorem proving for the verification of the pipelines

rawabstract:
In this thesis we describe the formal verification of a fully IEEE compliant floating point unit (FPU). The hardware is verified on the gate-level against a formalization of the IEEE standard. The verification is performed using the theorem proving system PVS. The FPU supports both single and double precision floating point numbers, normal and denormal numbers, all four IEEE rounding modes, and exceptions as required by the standard. Beside the verification of the combinatorial correctness of the FPUs we pipeline the FPUs to allow the integration into an out-of-order processor. We formally define the correctness criterion the pipelines must obey in order to work properly within the processor. We then describe a new methodology based on combining model checking and theorem proving for the verification of the pipelines

entry:
@PhdThesis{Jacobi:2002:FVF,
  author =       "Christian Jacobi",
  title =        "Formal verification of a fully {IEEE} compliant
                 floating point unit",
  type =         "{Ph.D.} thesis",
  school =       "Universit{\"a}t Saarbr{\"u}cken Fakult{\"a}t 6 ---
                 Naturwissenschaftlich-Technische Fakult{\"a}t I.
                 Fachrichtung 6.2 --- Informatik",
  address =      "Saarbr{\"u}cken, Germany",
  year =         "2002",
  bibdate =      "Tue May 07 16:38:40 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this thesis we describe the formal verification of
                 a fully IEEE compliant floating point unit (FPU). The
                 hardware is verified on the gate-level against a
                 formalization of the IEEE standard. The verification is
                 performed using the theorem proving system PVS. The FPU
                 supports both single and double precision floating
                 point numbers, normal and denormal numbers, all four
                 IEEE rounding modes, and exceptions as required by the
                 standard. Beside the verification of the combinatorial
                 correctness of the FPUs we pipeline the FPUs to allow
                 the integration into an out-of-order processor. We
                 formally define the correctness criterion the pipelines
                 must obey in order to work properly within the
                 processor. We then describe a new methodology based on
                 combining model checking and theorem proving for the
                 verification of the pipelines",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Kahan:2002:FPC
author: W. Kahan
title: Fclass: a Proposed Classification of Standard Floating-Point Operands
pages: 6
day: 23
month: mar
monthnumber: 3
year: 2002
bibdate: Mon Apr 25 17:53:00 2005
bibtimestamp: 2005.04.25 17:53:00 ???
URL: http://www.cs.berkeley.edu/~wkahan/ieee754status/Fclass.pdf
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: W. Kahan
rawtitle: {Fclass}: a Proposed Classification of Standard Floating-Point Operands
entry:
@Misc{Kahan:2002:FPC,
  author =       "W. Kahan",
  title =        "{Fclass}: a Proposed Classification of Standard
                 Floating-Point Operands",
  howpublished = "World-Wide Web document",
  pages =        "6",
  day =          "23",
  month =        mar,
  year =         "2002",
  bibdate =      "Mon Apr 25 17:53:00 2005",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.cs.berkeley.edu/~wkahan/ieee754status/Fclass.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kim:2002:BSA
author: Hyun-Sung Kim and Kee-Young Yoo
title: Bit-Serial AOP Arithmetic Architectures over GF$ (2^m) $
journal: j-LECT-NOTES-COMP-SCI
volume: 2437
pages: 303--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Sat Nov 30 20:57:24 MST 2002
bibtimestamp: 2002.11.30 20:57:24 MST
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Hyun-Sung Kim and Kee-Young Yoo
rawtitle: Bit-Serial {AOP} Arithmetic Architectures over {GF$ (2^m) $}
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2437.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer.de/link/service/series/0558/bibs/2437/24370303.htm; http://link.springer.de/link/service/series/0558/papers/2437/24370303.pdf

entry:
@Article{Kim:2002:BSA,
  author =       "Hyun-Sung Kim and Kee-Young Yoo",
  title =        "Bit-Serial {AOP} Arithmetic Architectures over {GF$
                 (2^m) $}",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2437",
  pages =        "303--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Sat Nov 30 20:57:24 MST 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2437.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer.de/link/service/series/0558/bibs/2437/24370303.htm;
                 http://link.springer.de/link/service/series/0558/papers/2437/24370303.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Kim:2002:IDS
author: Nam-Yeun Kim and Dae-Ghon Kho and Kee-Young Yoo
title: Inversion / Division Systolic Architecture for Public-Key Cryptosystems in GF($ 2^m $)
journal: j-LECT-NOTES-COMP-SCI
volume: 2433
pages: 289--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Thu Sep 12 08:41:42 2002
bibtimestamp: 2002.09.12 08:41:42 ???
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Nam-Yeun Kim and Dae-Ghon Kho and Kee-Young Yoo
rawtitle: Inversion\slash Division Systolic Architecture for Public-Key Cryptosystems in {GF($ 2^m $) }
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2433.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2433/24330289.htm; http://link.springer-ny.com/link/service/series/0558/papers/2433/24330289.pdf

entry:
@Article{Kim:2002:IDS,
  author =       "Nam-Yeun Kim and Dae-Ghon Kho and Kee-Young Yoo",
  title =        "Inversion\slash Division Systolic Architecture for
                 Public-Key Cryptosystems in {GF($ 2^m $) }",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2433",
  pages =        "289--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Thu Sep 12 08:41:42 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2433.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2433/24330289.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2433/24330289.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: book
filename: fparith.bib
label: Koren:2002:CAA
author: Israel Koren
title: Computer Arithmetic Algorithms
publisher: pub-A-K-PETERS
address: pub-A-K-PETERS:adr
edition: Second
pages: xv + 281
year: 2002
ISBN: 1-56881-160-8 (hardcover), 1-4398-6371-7 (e-book) OR 1568811608 (hardcover), 1439863717 (ebook)
LCCN: QA76.9.C62 K67
bibdate: Sat May 04 10:29:22 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/master.bib
bibtimestamp: 2002.05.04 10:29:22 ???
acknowledgement: ack-nhfb
rawauthor: Israel Koren
rawtitle: Computer Arithmetic Algorithms
ISBN13:
978-1-56881-160-4 (hardcover), 978-1-4398-6371-8 (e-book) OR 9781568811604 (hardcover), 9781439863718 (ebook)

abstract:
Concentrating on the underlying principles, this book explains the algorithms used in arithmetic operations on digital computers. It identifies the similarities between the different algorithms and provides guidance for selecting the appropriate algorithms for a given technology. Chapters cover conventional number systems, unconventional fixed-radix number systems, sequential algorithms for multiplication and division, binary floating-point numbers, fast addition, high-speed multiplication, fast division, division through multiplication, the evaluations of elementary functions, logarithmic number systems, and the residue number system.

TOC:
1: Conventional Number Systems 2: Unconventional Fixed-Radix Number Systems 3: Sequential Algorithms for Multiplication and Division 4: Binary Floating-Point Numbers 5: Fast Addition 6: High-Speed Multiplication 7: Fast Division 8: Division Through Multiplication 9: Evaluation of Elementary Functions 10: Logarithmic Number Systems 11: The Residue Number System

rawabstract:
Concentrating on the underlying principles, this book explains the algorithms used in arithmetic operations on digital computers. It identifies the similarities between the different algorithms and provides guidance for selecting the appropriate algorithms for a given technology. Chapters cover conventional number systems, unconventional fixed-radix number systems, sequential algorithms for multiplication and division, binary floating-point numbers, fast addition, high-speed multiplication, fast division, division through multiplication, the evaluations of elementary functions, logarithmic number systems, and the residue number system.

rawTOC:
1: Conventional Number Systems \\ 2: Unconventional Fixed-Radix Number Systems \\ 3: Sequential Algorithms for Multiplication and Division \\ 4: Binary Floating-Point Numbers \\ 5: Fast Addition \\ 6: High-Speed Multiplication \\ 7: Fast Division \\ 8: Division Through Multiplication \\ 9: Evaluation of Elementary Functions \\ 10: Logarithmic Number Systems \\ 11: The Residue Number System

entry:
@Book{Koren:2002:CAA,
  author =       "Israel Koren",
  title =        "Computer Arithmetic Algorithms",
  publisher =    pub-A-K-PETERS,
  address =      pub-A-K-PETERS:adr,
  edition =      "Second",
  pages =        "xv + 281",
  year =         "2002",
  ISBN =         "1-56881-160-8 (hardcover), 1-4398-6371-7 (e-book)",
  ISBN-13 =      "978-1-56881-160-4 (hardcover), 978-1-4398-6371-8
                 (e-book)",
  LCCN =         "QA76.9.C62 K67",
  bibdate =      "Sat May 04 10:29:22 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib",
  abstract =     "Concentrating on the underlying principles, this book
                 explains the algorithms used in arithmetic operations
                 on digital computers. It identifies the similarities
                 between the different algorithms and provides guidance
                 for selecting the appropriate algorithms for a given
                 technology. Chapters cover conventional number systems,
                 unconventional fixed-radix number systems, sequential
                 algorithms for multiplication and division, binary
                 floating-point numbers, fast addition, high-speed
                 multiplication, fast division, division through
                 multiplication, the evaluations of elementary
                 functions, logarithmic number systems, and the residue
                 number system.",
  acknowledgement = ack-nhfb,
  tableofcontents = "1: Conventional Number Systems \\
                 2: Unconventional Fixed-Radix Number Systems \\
                 3: Sequential Algorithms for Multiplication and
                 Division \\
                 4: Binary Floating-Point Numbers \\
                 5: Fast Addition \\
                 6: High-Speed Multiplication \\
                 7: Fast Division \\
                 8: Division Through Multiplication \\
                 9: Evaluation of Elementary Functions \\
                 10: Logarithmic Number Systems \\
                 11: The Residue Number System",
}


bibtype: article
filename: fparith.bib
label: Kornerup:2002:PRN
author: Peter Kornerup and Jean-Claude Bajard and Christiane Frougny and Jean-Michel Muller
title: Preface: Real Numbers and Computers
journal: j-THEOR-COMP-SCI
volume: 291
number: 2
pages: 133--134
month: nov
monthnumber: 11
year: 2002
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Wed Nov 20 18:15:29 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.20 18:15:29 MST
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: Peter Kornerup and Jean-Claude Bajard and Christiane Frougny and Jean-Michel Muller
rawtitle: Preface: Real Numbers and Computers
entry:
@Article{Kornerup:2002:PRN,
  author =       "Peter Kornerup and Jean-Claude Bajard and Christiane
                 Frougny and Jean-Michel Muller",
  title =        "Preface: Real Numbers and Computers",
  journal =      j-THEOR-COMP-SCI,
  volume =       "291",
  number =       "2",
  pages =        "133--134",
  month =        nov,
  year =         "2002",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Wed Nov 20 18:15:29 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
}


bibtype: article
filename: fparith.bib
label: Koutroumpezis:2002:ADR
author: G. Koutroumpezis and K. Tatas and D. Soudris and S. Blionas and K. Masselos and A. Thanailakis
title: Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations
journal: j-LECT-NOTES-COMP-SCI
volume: 2438
pages: 1027--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:10:28 MDT 2002
bibtimestamp: 2002.09.10 19:10:28 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: G. Koutroumpezis and K. Tatas and D. Soudris and S. Blionas and K. Masselos and A. Thanailakis
rawtitle: Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations
URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2438/24381027.htm; http://link.springer-ny.com/link/service/series/0558/papers/2438/24381027.pdf

entry:
@Article{Koutroumpezis:2002:ADR,
  author =       "G. Koutroumpezis and K. Tatas and D. Soudris and S.
                 Blionas and K. Masselos and A. Thanailakis",
  title =        "Architecture Design of a Reconfigurable Multiplier for
                 Flexible Coarse-Grain Implementations",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2438",
  pages =        "1027--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:10:28 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2438.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2438/24381027.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2438/24381027.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: misc
filename: fparith.bib
label: Krygowski:2002:FPM
author: C. A. Krygowski and E. M. Schwarz
title: Floating-point multiplier for de-normalized inputs
pages: 1027--??
day: 5
month: sep
monthnumber: 9
year: 2002
bibdate: Fri Nov 28 15:26:12 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 15:26:12 ???
note: U.S. Patent Application No. 2002/0124037 A1.
acknowledgement: ack-nhfb
rawauthor: C. A. Krygowski and E. M. Schwarz
rawnote: U.S. Patent Application No. 2002/0124037 A1.
rawtitle: Floating-point multiplier for de-normalized inputs
entry:
@Misc{Krygowski:2002:FPM,
  author =       "C. A. Krygowski and E. M. Schwarz",
  title =        "Floating-point multiplier for de-normalized inputs",
  day =          "5",
  month =        sep,
  year =         "2002",
  bibdate =      "Fri Nov 28 15:26:12 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "U.S. Patent Application No. 2002/0124037 A1.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Ku:2002:NPA
author: Kyo-Min Ku and Kyeoung-Ju Ha and Hyun-Sung Kim and Kee-Young Yoo
title: New Parallel Architecture for Modular Multiplication and Squaring Based on Cellular Automata
journal: j-LECT-NOTES-COMP-SCI
volume: 2367
pages: 359--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:09:54 MDT 2002
bibtimestamp: 2002.09.10 19:09:54 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Kyo-Min Ku and Kyeoung-Ju Ha and Hyun-Sung Kim and Kee-Young Yoo
rawtitle: New Parallel Architecture for Modular Multiplication and Squaring Based on Cellular Automata
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2367.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2367/23670359.htm; http://link.springer-ny.com/link/service/series/0558/papers/2367/23670359.pdf

entry:
@Article{Ku:2002:NPA,
  author =       "Kyo-Min Ku and Kyeoung-Ju Ha and Hyun-Sung Kim and
                 Kee-Young Yoo",
  title =        "New Parallel Architecture for Modular Multiplication
                 and Squaring Based on Cellular Automata",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2367",
  pages =        "359--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:09:54 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2367.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2367/23670359.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2367/23670359.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: book
filename: fparith.bib
label: Kulisch:2002:AAD
author: U. Kulisch
title: Advanced Arithmetic for the Digital Computer: Design of Arithmetic Units
publisher: pub-SPRINGER-WIEN
address: pub-SPRINGER-WIEN:adr
pages: xii + 141
year: 2002
ISBN: 3-211-83870-8 OR 3211838708
ISBN13: 978-3-211-83870-9 OR 9783211838709
LCCN: QA76.9.C62 K85 2002
bibdate: Mon Feb 03 07:48:36 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.02.03 07:48:36 ???
URL: http://www.springer.at/main/book.jsp?bookID=3-211-83870-8&categoryID=10
acknowledgement: ack-nhfb
rawauthor: U. Kulisch
rawtitle: Advanced Arithmetic for the Digital Computer: Design of Arithmetic Units
keywords:
accuracy; computer algebra; floating-point arithmetic; interval arithmetic; scalar product; speed of computation; vector operations

entry:
@Book{Kulisch:2002:AAD,
  author =       "U. Kulisch",
  title =        "Advanced Arithmetic for the Digital Computer: Design
                 of Arithmetic Units",
  publisher =    pub-SPRINGER-WIEN,
  address =      pub-SPRINGER-WIEN:adr,
  pages =        "xii + 141",
  year =         "2002",
  ISBN =         "3-211-83870-8",
  ISBN-13 =      "978-3-211-83870-9",
  LCCN =         "QA76.9.C62 K85 2002",
  bibdate =      "Mon Feb 03 07:48:36 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  price =        "EUR 25.00",
  URL =          "http://www.springer.at/main/book.jsp?bookID=3-211-83870-8&categoryID=10",
  acknowledgement = ack-nhfb,
  keywords =     "accuracy; computer algebra; floating-point arithmetic;
                 interval arithmetic; scalar product; speed of
                 computation; vector operations",
}


bibtype: inproceedings
filename: fparith.bib
label: Kulisch:2002:RNZ
author: Ulrich Kulisch
editor: Peter Kornerup and Jean-Claude Bajard and Christiane Frougny and Jean-Michel Muller
booktitle: 4th Real Numbers and Computers Conference, Dagstuhl, Germany, 2000
title: Rounding near zero
volume: 291(2)
publisher: pub-ELSEVIER
address: pub-ELSEVIER:adr
pages: 23--29
day: 5
month: jan
monthnumber: 1
year: 2002
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Wed Nov 24 09:14:41 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.24 09:14:41 ???
series: j-THEOR-COMP-SCI
acknowledgement: ack-nhfb
rawauthor: Ulrich Kulisch
rawbooktitle: 4th Real Numbers and Computers Conference, Dagstuhl, Germany, 2000
raweditor: Peter Kornerup and Jean-Claude Bajard and Christiane Frougny and Jean-Michel Muller
rawtitle: Rounding near zero
remark:
This reference is incorrect: there is no paper by Kulisch in this journal issue. Where was it published??

entry:
@InProceedings{Kulisch:2002:RNZ,
  author =       "Ulrich Kulisch",
  editor =       "Peter Kornerup and Jean-Claude Bajard and Christiane
                 Frougny and Jean-Michel Muller",
  booktitle =    "4th Real Numbers and Computers Conference, Dagstuhl,
                 Germany, 2000",
  title =        "Rounding near zero",
  volume =       "291(2)",
  publisher =    pub-ELSEVIER,
  address =      pub-ELSEVIER:adr,
  pages =        "23--29",
  day =          "5",
  month =        jan,
  year =         "2002",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Wed Nov 24 09:14:41 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       j-THEOR-COMP-SCI,
  acknowledgement = ack-nhfb,
  remark =       "This reference is incorrect: there is no paper by
                 Kulisch in this journal issue. Where was it
                 published??",
}


bibtype: article
filename: fparith.bib
label: Kwon:2002:EBS
author: Soonhak Kwon and Heuisu Ryu
title: Efficient Bit Serial Multiplication Using Optimal Normal Bases of Type II in em GF$ (2^m) $
journal: j-LECT-NOTES-COMP-SCI
volume: 2433
pages: 300--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Thu Sep 12 08:47:11 2002
bibtimestamp: 2002.09.12 08:47:11 ???
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Soonhak Kwon and Heuisu Ryu
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2433.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2433/24330300.htm; http://link.springer-ny.com/link/service/series/0558/papers/2433/24330300.pdf

rawtitle:
Efficient Bit Serial Multiplication Using Optimal Normal Bases of Type {II} in {{\em GF\/}}$ (2^m) $

entry:
@Article{Kwon:2002:EBS,
  author =       "Soonhak Kwon and Heuisu Ryu",
  title =        "Efficient Bit Serial Multiplication Using Optimal
                 Normal Bases of Type {II} in {{\em GF\/}}$ (2^m) $",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2433",
  pages =        "300--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Thu Sep 12 08:47:11 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2433.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2433/24330300.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2433/24330300.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: inproceedings
filename: fparith.bib
label: Lang:2002:FPF
author: T. Lang and J. Bruguera
title: Floating-point fused multiply-add with reduced latency
crossref: IEEE:2002:IIC
pages: 145--150
year: 2002
DOI: https://doi.org/10.1109/ICCD.2002.1106762
bibdate: Fri Jun 24 14:33:25 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 14:33:25 ???
URL: http://csdl.computer.org/dl/proceedings/iccd/2002/1700/00/17000145.pdf
acknowledgement: ack-nhfb
rawauthor: T. Lang and J. Bruguera
rawtitle: Floating-point fused multiply-add with reduced latency
abstract:
We propose an architecture for the computation of the floating-point multiply-add-fused (MAF) operation $ A + (B times C) $. This architecture is based on the combined addition and rounding (using a dual adder) and on the anticipation of the normalization step before the addition. Because the normalization is performed before the addition, it is not possible to overlap the leading-zero-anticipator with the adder. Consequently, to avoid the increase in delay we modify the design of the LZA so that the leading bits of its output are produced first and can be used to begin the normalization. Moreover, parts of the addition are also anticipated. We have estimated the delay of the resulting architecture for double-precision format, considering the load introduced by long connections, and estimate a reduction of about 15% to 20% with respect to traditional implementations of the floating-point MAF unit.

rawabstract:
We propose an architecture for the computation of the floating-point multiply-add-fused (MAF) operation $ A + (B \times C) $. This architecture is based on the combined addition and rounding (using a dual adder) and on the anticipation of the normalization step before the addition. Because the normalization is performed before the addition, it is not possible to overlap the leading-zero-anticipator with the adder. Consequently, to avoid the increase in delay we modify the design of the LZA so that the leading bits of its output are produced first and can be used to begin the normalization. Moreover, parts of the addition are also anticipated. We have estimated the delay of the resulting architecture for double-precision format, considering the load introduced by long connections, and estimate a reduction of about 15\% to 20\% with respect to traditional implementations of the floating-point MAF unit.

entry:
@InProceedings{Lang:2002:FPF,
  author =       "T. Lang and J. Bruguera",
  title =        "Floating-point fused multiply-add with reduced
                 latency",
  crossref =     "IEEE:2002:IIC",
  pages =        "145--150",
  year =         "2002",
  DOI =          "https://doi.org/10.1109/ICCD.2002.1106762",
  bibdate =      "Fri Jun 24 14:33:25 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/dl/proceedings/iccd/2002/1700/00/17000145.pdf",
  abstract =     "We propose an architecture for the computation of the
                 floating-point multiply-add-fused (MAF) operation $ A +
                 (B \times C) $. This architecture is based on the
                 combined addition and rounding (using a dual adder) and
                 on the anticipation of the normalization step before
                 the addition. Because the normalization is performed
                 before the addition, it is not possible to overlap the
                 leading-zero-anticipator with the adder. Consequently,
                 to avoid the increase in delay we modify the design of
                 the LZA so that the leading bits of its output are
                 produced first and can be used to begin the
                 normalization. Moreover, parts of the addition are also
                 anticipated. We have estimated the delay of the
                 resulting architecture for double-precision format,
                 considering the load introduced by long connections,
                 and estimate a reduction of about 15\% to 20\% with
                 respect to traditional implementations of the
                 floating-point MAF unit.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Lee:2002:DSS
author: Keon-Jik Lee and Kee-Won Kim and Kee-Young Yoo
title: Digit-serial-in-serial-out systolic multiplier for Montgomery algorithm
journal: j-INFO-PROC-LETT
volume: 82
number: 2
pages: 65--71
day: 30
month: apr
monthnumber: 4
year: 2002
CODEN: IFPLAT
ISSN: 0020-0190 (print), 1872-6119 (electronic) OR 00200190 (print), 18726119 (electronic)
ISSNL: 0020-0190 OR 00200190
bibdate: Mon Jan 26 06:35:43 MST 2004
bibtimestamp: 2004.01.26 06:35:43 MST
URL: http://www.elsevier.com/gej-ng/10/23/20/86/33/27/abstract.html
fjournal: Information Processing Letters
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00200190
rawauthor: Keon-Jik Lee and Kee-Won Kim and Kee-Young Yoo
rawtitle: Digit-serial-in-serial-out systolic multiplier for {Montgomery} algorithm
bibsource:
http://www.sciencedirect.com/science/journal/00200190; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Lee:2002:DSS,
  author =       "Keon-Jik Lee and Kee-Won Kim and Kee-Young Yoo",
  title =        "Digit-serial-in-serial-out systolic multiplier for
                 {Montgomery} algorithm",
  journal =      j-INFO-PROC-LETT,
  volume =       "82",
  number =       "2",
  pages =        "65--71",
  day =          "30",
  month =        apr,
  year =         "2002",
  CODEN =        "IFPLAT",
  ISSN =         "0020-0190 (print), 1872-6119 (electronic)",
  ISSN-L =       "0020-0190",
  bibdate =      "Mon Jan 26 06:35:43 MST 2004",
  bibsource =    "http://www.sciencedirect.com/science/journal/00200190;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.elsevier.com/gej-ng/10/23/20/86/33/27/abstract.html",
  acknowledgement = ack-nhfb,
  fjournal =     "Information Processing Letters",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00200190",
}


bibtype: inproceedings
filename: fparith.bib
label: Lee:2002:PFP
author: B. Lee and N. Burgess
title: Parameterisable floating-point operations on FPGA
crossref: Matthews:2002:PTS
volume: 2
pages: 1064--1068
year: 2002
DOI: https://doi.org/10.1109/ACSSC.2002.1196947
bibdate: Sat Oct 9 12:47:53 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 12:47:53 ???
acknowledgement: ack-nhfb
rawauthor: B. Lee and N. Burgess
rawtitle: Parameterisable floating-point operations on {FPGA}
abstract:
The paper presents a group of IEEE 754-style floating-point units targeted at Xilinx VirtexII FPGA. Special features of the technology are taken advantage of to produce optimised components. Pipelined designs are given that show the latency of 100 MHz single-precision components. Non-pipelined reference designs are included for future comparison purposes.

rawabstract:
The paper presents a group of IEEE 754-style floating-point units targeted at Xilinx VirtexII FPGA. Special features of the technology are taken advantage of to produce optimised components. Pipelined designs are given that show the latency of 100 MHz single-precision components. Non-pipelined reference designs are included for future comparison purposes.

entry:
@InProceedings{Lee:2002:PFP,
  author =       "B. Lee and N. Burgess",
  title =        "Parameterisable floating-point operations on {FPGA}",
  crossref =     "Matthews:2002:PTS",
  volume =       "2",
  pages =        "1064--1068",
  year =         "2002",
  DOI =          "https://doi.org/10.1109/ACSSC.2002.1196947",
  bibdate =      "Sat Oct 9 12:47:53 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The paper presents a group of IEEE 754-style
                 floating-point units targeted at Xilinx VirtexII FPGA.
                 Special features of the technology are taken advantage
                 of to produce optimised components. Pipelined designs
                 are given that show the latency of 100 MHz
                 single-precision components. Non-pipelined reference
                 designs are included for future comparison purposes.",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Leeser:2002:LPH
author: Miriam Leeser
title: A Library of Parameterized Hardware Modules for Floating Point Arithmetic and Its Use
type: Technical report
institution: Department of Electrical and Computer Engineering, Northeastern University
address: Boston, MA, USA
pages: 28
year: 2002
bibdate: Mon May 22 11:20:03 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.05.22 11:20:03 ???
acknowledgement: ack-nhfb
rawauthor: Miriam Leeser
rawtitle: A Library of Parameterized Hardware Modules for Floating Point Arithmetic and Its Use
note:
Presented at High Performance Embedded Computing (HPEC) Workshop (6th) held in Lexington, MA on 24--26 September 2002.

rawnote:
Presented at High Performance Embedded Computing (HPEC) Workshop (6th) held in Lexington, MA on 24--26 September 2002.

entry:
@TechReport{Leeser:2002:LPH,
  author =       "Miriam Leeser",
  title =        "A Library of Parameterized Hardware Modules for
                 Floating Point Arithmetic and Its Use",
  type =         "Technical report",
  institution =  "Department of Electrical and Computer Engineering,
                 Northeastern University",
  address =      "Boston, MA, USA",
  pages =        "28",
  year =         "2002",
  bibdate =      "Mon May 22 11:20:03 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Presented at High Performance Embedded Computing
                 (HPEC) Workshop (6th) held in Lexington, MA on 24--26
                 September 2002.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Leong:2002:IMM
author: P. C. Leong and E. C. Tan and P. C. Tan
title: An iterative modular multiplication algorithm
journal: j-COMPUT-MATH-APPL
volume: 44
number: 1--2
pages: 175--180
month: jul
monthnumber: 7
year: 2002
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 21:49:23 MST 2017
bibtimestamp: 2017.03.01 21:49:23 MST
URL: http://www.sciencedirect.com/science/article/pii/S0898122102001384
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: P. C. Leong and E. C. Tan and P. C. Tan
rawtitle: An iterative modular multiplication algorithm
entry:
@Article{Leong:2002:IMM,
  author =       "P. C. Leong and E. C. Tan and P. C. Tan",
  title =        "An iterative modular multiplication algorithm",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "44",
  number =       "1--2",
  pages =        "175--180",
  month =        jul,
  year =         "2002",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 21:49:23 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0898122102001384",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: article
filename: fparith.bib
label: Lester:2002:CAF
author: David Lester and Scott Chambers and Heoi Lee Lu
journal: j-THEOR-COMP-SCI
volume: 279
number: 1-2
pages: 51--64
month: may
monthnumber: 5
year: 2002
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Wed Nov 20 18:08:56 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.20 18:08:56 MST
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: David Lester and Scott Chambers and Heoi Lee Lu
title:
A constructive algorithm for finding the exact roots of polynomials with computable real coefficients

rawtitle:
A constructive algorithm for finding the exact roots of polynomials with computable real coefficients

entry:
@Article{Lester:2002:CAF,
  author =       "David Lester and Scott Chambers and Heoi Lee Lu",
  title =        "A constructive algorithm for finding the exact roots
                 of polynomials with computable real coefficients",
  journal =      j-THEOR-COMP-SCI,
  volume =       "279",
  number =       "1-2",
  pages =        "51--64",
  month =        may,
  year =         "2002",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Wed Nov 20 18:08:56 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
}


bibtype: article
filename: fparith.bib
label: Lester:2002:UPV
author: David Lester and Paul Gowland
title: Using PVS to validate the algorithms of an exact arithmetic
journal: j-THEOR-COMP-SCI
volume: 291
number: 2
pages: 203--218
month: nov
monthnumber: 11
year: 2002
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Wed Nov 20 18:15:29 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.20 18:15:29 MST
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: David Lester and Paul Gowland
rawtitle: Using {PVS} to validate the algorithms of an exact arithmetic
entry:
@Article{Lester:2002:UPV,
  author =       "David Lester and Paul Gowland",
  title =        "Using {PVS} to validate the algorithms of an exact
                 arithmetic",
  journal =      j-THEOR-COMP-SCI,
  volume =       "291",
  number =       "2",
  pages =        "203--218",
  month =        nov,
  year =         "2002",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Wed Nov 20 18:15:29 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
}


bibtype: article
filename: fparith.bib
label: Li:2002:DIT
title: Design, implementation and testing of extended and mixed precision BLAS
journal: j-TOMS
volume: 28
number: 2
pages: 152--205
month: jun
monthnumber: 6
year: 2002
CODEN: ACMSCU
DOI: https://doi.org/10.1145/567806.567808
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Sat Nov 9 11:16:50 MST 2002
bibsource: http://www.acm.org/pubs/contents/journals/toms/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.09 11:16:50 MST
URL: http://crd.lbl.gov/~xiaoye/XBLAS/
fjournal: ACM Transactions on Mathematical Software (TOMS)
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
journalURL: https://dl.acm.org/loi/toms
rawtitle: Design, implementation and testing of extended and mixed precision {BLAS}
author:
Xiaoye S. Li and James W. Demmel and David H. Bailey and Greg Henry and Yozo Hida and Jimmy Iskandar and William Kahan and Suh Y. Kang and Anil Kapur and Michael C. Martin and Brandon J. Thompson and Teresa Tung and Daniel J. Yoo

abstract:
This paper describes the design rationale, a C implementation, and conformance testing of a subset of the new Standard for the BLAS (Basic Linear Algebra Subroutines): Extended and Mixed Precision BLAS. Permitting higher internal precision and mixed input / output types and precisions allows us to implement some algorithms that are simpler, more accurate, and sometimes faster than possible without these features. The new BLAS are challenging to implement and test because there are many more subroutines than in the existing Standard, and because we must be able to assess whether a higher precision is used for internal computations than is used for either input or output variables. We have therefore developed an automated process of generating and systematically testing these routines. Our methodology is applicable to languages besides C. In particular, our algorithms used in the testing code will be valuable to all other BLAS implementors. Our extra precision routines achieve excellent performance---close to half of the machine peak Megaflop rate even for the Level 2 BLAS, when the data access is stride one.

rawabstract:
This paper describes the design rationale, a C implementation, and conformance testing of a subset of the new Standard for the BLAS (Basic Linear Algebra Subroutines): Extended and Mixed Precision BLAS. Permitting higher internal precision and mixed input\slash output types and precisions allows us to implement some algorithms that are simpler, more accurate, and sometimes faster than possible without these features. The new BLAS are challenging to implement and test because there are many more subroutines than in the existing Standard, and because we must be able to assess whether a higher precision is used for internal computations than is used for either input or output variables. We have therefore developed an automated process of generating and systematically testing these routines. Our methodology is applicable to languages besides C. In particular, our algorithms used in the testing code will be valuable to all other BLAS implementors. Our extra precision routines achieve excellent performance---close to half of the machine peak Megaflop rate even for the Level 2 BLAS, when the data access is stride one.

rawauthor:
Xiaoye S. Li and James W. Demmel and David H. Bailey and Greg Henry and Yozo Hida and Jimmy Iskandar and William Kahan and Suh Y. Kang and Anil Kapur and Michael C. Martin and Brandon J. Thompson and Teresa Tung and Daniel J. Yoo

entry:
@Article{Li:2002:DIT,
  author =       "Xiaoye S. Li and James W. Demmel and David H. Bailey
                 and Greg Henry and Yozo Hida and Jimmy Iskandar and
                 William Kahan and Suh Y. Kang and Anil Kapur and
                 Michael C. Martin and Brandon J. Thompson and Teresa
                 Tung and Daniel J. Yoo",
  title =        "Design, implementation and testing of extended and
                 mixed precision {BLAS}",
  journal =      j-TOMS,
  volume =       "28",
  number =       "2",
  pages =        "152--205",
  month =        jun,
  year =         "2002",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/567806.567808",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Sat Nov 9 11:16:50 MST 2002",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toms/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://crd.lbl.gov/~xiaoye/XBLAS/",
  abstract =     "This paper describes the design rationale, a C
                 implementation, and conformance testing of a subset of
                 the new Standard for the BLAS (Basic Linear Algebra
                 Subroutines): Extended and Mixed Precision BLAS.
                 Permitting higher internal precision and mixed
                 input\slash output types and precisions allows us to
                 implement some algorithms that are simpler, more
                 accurate, and sometimes faster than possible without
                 these features. The new BLAS are challenging to
                 implement and test because there are many more
                 subroutines than in the existing Standard, and because
                 we must be able to assess whether a higher precision is
                 used for internal computations than is used for either
                 input or output variables. We have therefore developed
                 an automated process of generating and systematically
                 testing these routines. Our methodology is applicable
                 to languages besides C. In particular, our algorithms
                 used in the testing code will be valuable to all other
                 BLAS implementors. Our extra precision routines achieve
                 excellent performance---close to half of the machine
                 peak Megaflop rate even for the Level 2 BLAS, when the
                 data access is stride one.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
  keywords =     "accurate floating-point summation",
}


bibtype: techreport
filename: fparith.bib
label: Li:2002:LLF
author: Ren-Cang Li and Peter Markstein and Jon P. Okada and James W. Thomas
title: The tt libm library and floating-point arithmetic for HP-UX on Itanium-2
type: Technical report
institution: inst-HP
address: inst-HP:adr
year: 2002
bibdate: Tue Nov 18 15:06:56 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.11.18 15:06:56 ???
acknowledgement: ack-nhfb
rawauthor: Ren-Cang Li and Peter Markstein and Jon P. Okada and James W. Thomas
rawtitle: The {\tt libm} library and floating-point arithmetic for {HP-UX} on {Itanium-2}
entry:
@TechReport{Li:2002:LLF,
  author =       "Ren-Cang Li and Peter Markstein and Jon P. Okada and
                 James W. Thomas",
  title =        "The {\tt libm} library and floating-point arithmetic
                 for {HP-UX} on {Itanium-2}",
  type =         "Technical report",
  institution =  inst-HP,
  address =      inst-HP:adr,
  pages =        "??",
  year =         "2002",
  bibdate =      "Tue Nov 18 15:06:56 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "????",
  acknowledgement = ack-nhfb,
}


bibtype: phdthesis
filename: fparith.bib
label: Liddicoat:2002:HPA
author: Albert Austin Liddicoat
title: High-performance arithmetic for division and the elementary functions
type: Ph.D. Thesis
school: Stanford University
address: Stanford, CA, USA
pages: 141
year: 2002
ISBN: 0-493-53347-8 OR 0493533478
ISBN13: 978-0-493-53347-6 OR 9780493533476
bibdate: Fri Oct 25 17:06:55 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.10.25 17:06:55 ???
acknowledgement: ack-nhfb
rawauthor: Albert Austin Liddicoat
rawtitle: High-performance arithmetic for division and the elementary functions
URL:
http://wwwlib.umi.com/dissertations/fullcit/3040035; http://wwwlib.umi.com/dissertations/preview/3040035

entry:
@PhdThesis{Liddicoat:2002:HPA,
  author =       "Albert Austin Liddicoat",
  title =        "High-performance arithmetic for division and the
                 elementary functions",
  type =         "{Ph.D.} Thesis",
  school =       "Stanford University",
  address =      "Stanford, CA, USA",
  pages =        "141",
  year =         "2002",
  ISBN =         "0-493-53347-8",
  ISBN-13 =      "978-0-493-53347-6",
  bibdate =      "Fri Oct 25 17:06:55 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://wwwlib.umi.com/dissertations/fullcit/3040035;
                 http://wwwlib.umi.com/dissertations/preview/3040035",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lienhart:2002:UFP
author: G. Lienhart and A. Kugel and R. Manner
title: Using floating-point arithmetic on FPGAs to accelerate scientific $N$-body simulations
crossref: Pocek:2002:FAI
pages: 182--191
year: 2002
DOI: https://doi.org/10.1109/FPGA.2002.1106673
bibdate: Sat Oct 9 12:49:37 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 12:49:37 ???
acknowledgement: ack-nhfb
rawauthor: G. Lienhart and A. Kugel and R. Manner
rawtitle: Using floating-point arithmetic on {FPGAs} to accelerate scientific {$N$}-body simulations
abstract:
This paper investigates the usage of floating-point arithmetic on FPGAs for N-Body simulation in natural science. The common aspect of these applications is the simple computing structure where forces between a particle and its surrounding particles are summed up. The role of reduced precision arithmetic is discussed, and our implementation of a floating-point arithmetic library with parameterized operators is presented. On the base of this library, implementation strategies of complex arithmetic units are discussed. Finally the realization of a fully pipelined pressure force calculation unit consisting of 60 floating-point operators with a resulting performance of 3.9 Gflops on an off the shelf FPGA is presented.

rawabstract:
This paper investigates the usage of floating-point arithmetic on FPGAs for N-Body simulation in natural science. The common aspect of these applications is the simple computing structure where forces between a particle and its surrounding particles are summed up. The role of reduced precision arithmetic is discussed, and our implementation of a floating-point arithmetic library with parameterized operators is presented. On the base of this library, implementation strategies of complex arithmetic units are discussed. Finally the realization of a fully pipelined pressure force calculation unit consisting of 60 floating-point operators with a resulting performance of 3.9 Gflops on an off the shelf FPGA is presented.

entry:
@InProceedings{Lienhart:2002:UFP,
  author =       "G. Lienhart and A. Kugel and R. Manner",
  title =        "Using floating-point arithmetic on {FPGAs} to
                 accelerate scientific {$N$}-body simulations",
  crossref =     "Pocek:2002:FAI",
  pages =        "182--191",
  year =         "2002",
  DOI =          "https://doi.org/10.1109/FPGA.2002.1106673",
  bibdate =      "Sat Oct 9 12:49:37 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper investigates the usage of floating-point
                 arithmetic on FPGAs for N-Body simulation in natural
                 science. The common aspect of these applications is the
                 simple computing structure where forces between a
                 particle and its surrounding particles are summed up.
                 The role of reduced precision arithmetic is discussed,
                 and our implementation of a floating-point arithmetic
                 library with parameterized operators is presented. On
                 the base of this library, implementation strategies of
                 complex arithmetic units are discussed. Finally the
                 realization of a fully pipelined pressure force
                 calculation unit consisting of 60 floating-point
                 operators with a resulting performance of 3.9 Gflops on
                 an off the shelf FPGA is presented.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Loh:2002:RER
author: Eugene Loh and G. William Walster
title: Rump's Example Revisited
journal: j-RELIABLE-COMPUTING
volume: 8
number: 3
pages: 245--248
month: jun
monthnumber: 6
year: 2002
CODEN: RCOMF8
DOI: https://doi.org/10.1023/A:1015569431383
ISSN: 1385-3139 (print), 1573-1340 (electronic) OR 13853139 (print), 15731340 (electronic)
ISSNL: 1385-3139 OR 13853139
bibdate: Sat Jan 5 10:21:56 2013
bibtimestamp: 2013.01.05 10:21:56 ???
fjournal: Reliable Computing = Nadezhnye vychisleniia
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11155
rawauthor: Eugene Loh and G. William Walster
rawtitle: {Rump}'s Example Revisited
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=1385-3139&volume=8&issue=3; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/reliablecomputing.bib

URL:
http://link.springer.com/article/10.1023/A%3A1015569431383/; http://www.springerlink.com/openurl.asp?genre=article&issn=1385-3139&volume=8&issue=3&spage=245; http://www.springerlink.com/openurl.asp?genre=article&issn=1385-3139&volume=8&issue=3&spage=245-248

entry:
@Article{Loh:2002:RER,
  author =       "Eugene Loh and G. William Walster",
  title =        "{Rump}'s Example Revisited",
  journal =      j-RELIABLE-COMPUTING,
  volume =       "8",
  number =       "3",
  pages =        "245--248",
  month =        jun,
  year =         "2002",
  CODEN =        "RCOMF8",
  DOI =          "https://doi.org/10.1023/A:1015569431383",
  ISSN =         "1385-3139 (print), 1573-1340 (electronic)",
  ISSN-L =       "1385-3139",
  bibdate =      "Sat Jan 5 10:21:56 2013",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=1385-3139&volume=8&issue=3;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/reliablecomputing.bib",
  URL =          "http://link.springer.com/article/10.1023/A%3A1015569431383/;
                 http://www.springerlink.com/openurl.asp?genre=article&issn=1385-3139&volume=8&issue=3&spage=245;
                 http://www.springerlink.com/openurl.asp?genre=article&issn=1385-3139&volume=8&issue=3&spage=245-248",
  acknowledgement = ack-nhfb # "\slash " # ack-rbk # "\slash " # ack-vk,
  fjournal =     "Reliable Computing = Nadezhnye vychisleniia",
  journal-URL =  "http://link.springer.com/journal/11155",
}


bibtype: article
filename: fparith.bib
label: Lutz:2002:BGB
author: Michael J. Lutz
journal: j-COMPUTER
volume: 35
number: 12
pages: 117--117
month: dec
monthnumber: 12
year: 2002
CODEN: CPTRB4
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Fri Dec 12 19:53:37 MST 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.12 19:53:37 MST
fjournal: Computer
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
rawauthor: Michael J. Lutz
title:
Bookshelf: Getting the Bugs Out [Debugging: The 9 Indispensable Rules for Finding Even the Most Elusive Software and Hardware Problems]; Saving Time With Arithmetic and Logic [Hacker's Delight]; Probability and Computing [Probability and Statistics with Reliability, Queuing and Computer Science Applications, 2nd edition]; Graphics Toolbox [Guide to Graphics Software Tools]

URL:
http://csdl.computer.org/dl/mags/co/2002/12/rz117.htm; http://csdl.computer.org/dl/mags/co/2002/12/rz117.pdf

rawtitle:
Bookshelf: Getting the Bugs Out [{Debugging: The 9 Indispensable Rules for Finding Even the Most Elusive Software and Hardware Problems}]; Saving Time With Arithmetic and Logic [{Hacker's Delight}]; Probability and Computing [{Probability and Statistics with Reliability, Queuing and Computer Science Applications, 2nd edition}]; Graphics Toolbox [{Guide to Graphics Software Tools}]

entry:
@Article{Lutz:2002:BGB,
  author =       "Michael J. Lutz",
  title =        "Bookshelf: Getting the Bugs Out [{Debugging: The 9
                 Indispensable Rules for Finding Even the Most Elusive
                 Software and Hardware Problems}]; Saving Time With
                 Arithmetic and Logic [{Hacker's Delight}]; Probability
                 and Computing [{Probability and Statistics with
                 Reliability, Queuing and Computer Science Applications,
                 2nd edition}]; Graphics Toolbox [{Guide to Graphics
                 Software Tools}]",
  journal =      j-COMPUTER,
  volume =       "35",
  number =       "12",
  pages =        "117--117",
  month =        dec,
  year =         "2002",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Fri Dec 12 19:53:37 MST 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/dl/mags/co/2002/12/rz117.htm;
                 http://csdl.computer.org/dl/mags/co/2002/12/rz117.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
}


bibtype: article
filename: fparith.bib
label: Madhukumar:2002:RNS
author: A. S. Madhukumar and F. Chin
title: Residue number system-based multicarrier CDMA system for high-speed broadband wireless access
journal: j-IEEE-TRANS-BROADCAST
volume: 48
number: 1
pages: 46--52
month: mar
monthnumber: 3
year: 2002
CODEN: IETBAC
DOI: https://doi.org/10.1109/11.992855
ISSNL: 0018-9316 OR 00189316
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=21407
fjournal: IEEE Transactions on Broadcasting
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: A. S. Madhukumar and F. Chin
rawtitle: Residue number system-based multicarrier {CDMA} system for high-speed broadband wireless access
entry:
@Article{Madhukumar:2002:RNS,
  author =       "A. S. Madhukumar and F. Chin",
  title =        "Residue number system-based multicarrier {CDMA} system
                 for high-speed broadband wireless access",
  journal =      j-IEEE-TRANS-BROADCAST,
  volume =       "48",
  number =       "1",
  pages =        "46--52",
  month =        mar,
  year =         "2002",
  CODEN =        "IETBAC",
  DOI =          "https://doi.org/10.1109/11.992855",
  ISSN =         "????",
  ISSN-L =       "0018-9316",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=21407",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Broadcasting",
  keywords =     "residue arithmetic; residue number system",
  summary =      "This correspondence is concerned with a new method to
                 enhance the bandwidth efficiency of a multicarrier CDMA
                 system by using a residue number based representation
                 for information symbols. The residues are mapped into a
                 set of orthogonal sequences \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Matousek:2002:LNS
author: Rudolf Matousek and Milan Tichy and Zdenek Pohl and Jiri Kadlec and Chris Softley and Nick Coleman
title: Logarithmic Number System and Floating-Point Arithmetics on FPGA
journal: j-LECT-NOTES-COMP-SCI
volume: 2438
pages: 175--188
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:10:28 MDT 2002
bibtimestamp: 2002.09.10 19:10:28 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawtitle: Logarithmic Number System and Floating-Point Arithmetics on {FPGA}
URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2438/24380627.htm; http://link.springer-ny.com/link/service/series/0558/papers/2438/24380627.pdf

rawauthor:
Rudolf Matousek and Milan Tich{\'y} and Zdenek Pohl and Jir{\'\i} Kadlec and Chris Softley and Nick Coleman

entry:
@Article{Matousek:2002:LNS,
  author =       "Rudolf Matousek and Milan Tich{\'y} and Zdenek Pohl
                 and Jir{\'\i} Kadlec and Chris Softley and Nick
                 Coleman",
  title =        "Logarithmic Number System and Floating-Point
                 Arithmetics on {FPGA}",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2438",
  pages =        "175--188",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:10:28 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2438.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2438/24380627.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2438/24380627.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  xxpages =      "627--??",
}


bibtype: article
filename: fparith.bib
label: Matula:2002:PTP
author: David W. Matula and Lee D. McFearin
title: A $ p times p $ bit fraction model of binary floating point division and extremal rounding cases
journal: j-THEOR-COMP-SCI
volume: 291
number: 2
pages: 159--182
month: nov
monthnumber: 11
year: 2002
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Wed Nov 20 18:15:29 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.20 18:15:29 MST
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: David W. Matula and Lee D. McFearin
rawtitle: A $ p \times p $ bit fraction model of binary floating point division and extremal rounding cases
entry:
@Article{Matula:2002:PTP,
  author =       "David W. Matula and Lee D. McFearin",
  title =        "A $ p \times p $ bit fraction model of binary floating
                 point division and extremal rounding cases",
  journal =      j-THEOR-COMP-SCI,
  volume =       "291",
  number =       "2",
  pages =        "159--182",
  month =        nov,
  year =         "2002",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Wed Nov 20 18:15:29 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
}


bibtype: article
filename: fparith.bib
label: McCluskey:2002:MLF
author: Glen McCluskey
title: Math library functions in C9X
journal: j-LOGIN
volume: 27
number: 2
pages: 9--13
month: apr
monthnumber: 4
year: 2002
CODEN: LOGNEM
ISSN: 1044-6397 (print), 2169-9364 (electronic) OR 10446397 (print), 21699364 (electronic)
bibdate: Sat May 04 10:26:38 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.05.04 10:26:38 ???
fjournal: ;login: the USENIX Association newsletter
acknowledgement: ack-nhfb
rawauthor: Glen McCluskey
rawtitle: Math library functions in {C9X}
entry:
@Article{McCluskey:2002:MLF,
  author =       "Glen McCluskey",
  title =        "Math library functions in {C9X}",
  journal =      j-LOGIN,
  volume =       "27",
  number =       "2",
  pages =        "9--13",
  month =        apr,
  year =         "2002",
  CODEN =        "LOGNEM",
  ISSN =         "1044-6397 (print), 2169-9364 (electronic)",
  bibdate =      "Sat May 04 10:26:38 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     ";login: the USENIX Association newsletter",
}


bibtype: phdthesis
filename: fparith.bib
label: McIlhenny:2002:CNL
author: Robert Dean McIlhenny
type: Ph.D. dissertation
school: Computer Science Department, University of California, Los Angeles
address: Los Angeles, CA, USA
pages: xiv + 182
year: 2002
ISBN: 0-493-82665-3 OR 0493826653
ISBN13: 978-0-493-82665-3 OR 9780493826653
bibdate: Sat Dec 04 09:27:33 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.12.04 09:27:33 ???
acknowledgement: ack-nhfb
advisor: Milos Ercegovac
rawauthor: Robert Dean McIlhenny
title:
Complex Number On-line Arithmetic for Reconfigurable Hardware: Algorithms, Implementations, and Application

abstract:
Complex number arithmetic plays an important role in various signal processing tasks, such as correlations, convolutions, and digital filtering. There is a need in such applications to exploit parallelism in implementing sequences of arithmetic expressions, as well as to reduce the bandwidth of the data path. Reconfigurable architectures are emerging as a viable technology for mapping numeric-intensive computations onto hardware. In order to provide efficient implementations that can accommodate changes with a minimal amount of redesign, the methodology for deriving algorithms and corresponding implementations must be flexible toward change.par In this dissertation, we present an efficient representation which treats the real and imaginary components as a unified number. We propose algorithms for various complex number on-line floating-point arithmetic operations. The algorithms are translated into actual implementations mapped onto reconfigurable hardware. The implementations are applied toward computing the complex singular value decomposition of a matrix, with a significant reduction in cost compared to networks of real number on-line and parallel arithmetic approaches.

rawabstract:
Complex number arithmetic plays an important role in various signal processing tasks, such as correlations, convolutions, and digital filtering. There is a need in such applications to exploit parallelism in implementing sequences of arithmetic expressions, as well as to reduce the bandwidth of the data path. Reconfigurable architectures are emerging as a viable technology for mapping numeric-intensive computations onto hardware. In order to provide efficient implementations that can accommodate changes with a minimal amount of redesign, the methodology for deriving algorithms and corresponding implementations must be flexible toward change.\par In this dissertation, we present an efficient representation which treats the real and imaginary components as a unified number. We propose algorithms for various complex number on-line floating-point arithmetic operations. The algorithms are translated into actual implementations mapped onto reconfigurable hardware. The implementations are applied toward computing the complex singular value decomposition of a matrix, with a significant reduction in cost compared to networks of real number on-line and parallel arithmetic approaches.

rawtitle:
Complex Number On-line Arithmetic for Reconfigurable Hardware: Algorithms, Implementations, and Application

entry:
@PhdThesis{McIlhenny:2002:CNL,
  author =       "Robert Dean McIlhenny",
  title =        "Complex Number On-line Arithmetic for Reconfigurable
                 Hardware: Algorithms, Implementations, and
                 Application",
  type =         "{Ph.D.} dissertation",
  school =       "Computer Science Department, University of California,
                 Los Angeles",
  address =      "Los Angeles, CA, USA",
  pages =        "xiv + 182",
  year =         "2002",
  ISBN =         "0-493-82665-3",
  ISBN-13 =      "978-0-493-82665-3",
  bibdate =      "Sat Dec 04 09:27:33 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Complex number arithmetic plays an important role in
                 various signal processing tasks, such as correlations,
                 convolutions, and digital filtering. There is a need in
                 such applications to exploit parallelism in
                 implementing sequences of arithmetic expressions, as
                 well as to reduce the bandwidth of the data path.
                 Reconfigurable architectures are emerging as a viable
                 technology for mapping numeric-intensive computations
                 onto hardware. In order to provide efficient
                 implementations that can accommodate changes with a
                 minimal amount of redesign, the methodology for
                 deriving algorithms and corresponding implementations
                 must be flexible toward change.\par

                 In this dissertation, we present an efficient
                 representation which treats the real and imaginary
                 components as a unified number. We propose algorithms
                 for various complex number on-line floating-point
                 arithmetic operations. The algorithms are translated
                 into actual implementations mapped onto reconfigurable
                 hardware. The implementations are applied toward
                 computing the complex singular value decomposition of a
                 matrix, with a significant reduction in cost compared
                 to networks of real number on-line and parallel
                 arithmetic approaches.",
  acknowledgement = ack-nhfb,
  advisor =      "Milo{\v{s}} Ercegovac",
}


bibtype: article
filename: fparith.bib
label: Messine:2002:EAA
author: F. Messine
title: Extentions [sic] of Affine Arithmetic: Application to Unconstrained Global Optimization
journal: j-J-UCS
volume: 8
number: 11
pages: 992--??
day: 28
month: nov
monthnumber: 11
year: 2002
ISSN: 0948-6968 OR 09486968
ISSNL: 0948-6968 OR 09486968
bibdate: Tue Dec 16 10:06:03 MST 2003
bibsource: http://www.jucs.org/jucs; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.16 10:06:03 MST
URL: http://www.jucs.org/jucs_8_11/extentions_of_affine_arithmetic
fjournal: J.UCS: Journal of Universal Computer Science
keywords: interval arithmetic
acknowledgement: ack-nhfb
journalURL: http://www.jucs.org/jucs
rawauthor: F. Messine
rawtitle: Extentions [sic] of Affine Arithmetic: Application to Unconstrained Global Optimization
entry:
@Article{Messine:2002:EAA,
  author =       "F. Messine",
  title =        "Extentions [sic] of Affine Arithmetic: Application to
                 Unconstrained Global Optimization",
  journal =      j-J-UCS,
  volume =       "8",
  number =       "11",
  pages =        "992--??",
  day =          "28",
  month =        nov,
  year =         "2002",
  CODEN =        "????",
  ISSN =         "0948-6968",
  ISSN-L =       "0948-6968",
  bibdate =      "Tue Dec 16 10:06:03 MST 2003",
  bibsource =    "http://www.jucs.org/jucs;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.jucs.org/jucs_8_11/extentions_of_affine_arithmetic",
  acknowledgement = ack-nhfb,
  fjournal =     "J.UCS: Journal of Universal Computer Science",
  journal-URL =  "http://www.jucs.org/jucs",
  keywords =     "interval arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Molina:2002:BLA
author: M. C. Molina and J. M. Mendias and R. Hermida
booktitle: Proceedings of the Euromicro Symposium on Digital System Design
title: Bit-level allocation of multiple-precision specifications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 385--392
year: 2002
bibdate: Sat Jul 16 16:53:44 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 16:53:44 MDT
acknowledgement: ack-nhfb
rawauthor: M. C. Molina and J. M. Mendias and R. Hermida
rawbooktitle: Proceedings of the Euromicro Symposium on Digital System Design
rawtitle: Bit-level allocation of multiple-precision specifications
entry:
@InProceedings{Molina:2002:BLA,
  author =       "M. C. Molina and J. M. Mendias and R. Hermida",
  booktitle =    "Proceedings of the Euromicro Symposium on Digital
                 System Design",
  title =        "Bit-level allocation of multiple-precision
                 specifications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "385--392",
  year =         "2002",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 16:53:44 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "This paper proposes an allocation algorithm able to
                 perform the combined resource selection and operation
                 binding of multiple-precision specifications that
                 maximizes the bit-level reuse of hardware resources.
                 Additionally, it presents an analytic \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Molina:2002:HLS
author: M. C. Molina and J. M. Mendias and R. Hermida
booktitle: Proceedings of the 39th Design Automation Conference, 10--14 June 2002
title: High-level synthesis of multiple-precision circuits independent of data-objects length
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 612--615
year: 2002
bibdate: Sat Jul 16 16:53:44 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 16:53:44 MDT
acknowledgement: ack-nhfb
rawauthor: M. C. Molina and J. M. Mendias and R. Hermida
rawbooktitle: Proceedings of the 39th Design Automation Conference, 10--14 June 2002
rawtitle: High-level synthesis of multiple-precision circuits independent of data-objects length
entry:
@InProceedings{Molina:2002:HLS,
  author =       "M. C. Molina and J. M. Mendias and R. Hermida",
  booktitle =    "Proceedings of the 39th Design Automation Conference,
                 10--14 June 2002",
  title =        "High-level synthesis of multiple-precision circuits
                 independent of data-objects length",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "612--615",
  year =         "2002",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 16:53:44 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "This paper presents an heuristic method to perform the
                 high-level synthesis of multiple-precision
                 specifications. The scheduling is based on the balance
                 of the number of bits calculated per cycle, and the
                 allocation on the bit-level reuse of the \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Molina:2002:MPC
author: M. C. Molina and J. M. Mendias and R. Hermida
booktitle: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 4--8 March 2002
title: Multiple-precision circuits allocation independent of data-objects length
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 909--913
year: 2002
bibdate: Sat Jul 16 16:53:44 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 16:53:44 MDT
acknowledgement: ack-nhfb
rawauthor: M. C. Molina and J. M. Mendias and R. Hermida
rawbooktitle: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 4--8 March 2002
rawtitle: Multiple-precision circuits allocation independent of data-objects length
entry:
@InProceedings{Molina:2002:MPC,
  author =       "M. C. Molina and J. M. Mendias and R. Hermida",
  booktitle =    "Proceedings of the Design, Automation and Test in
                 Europe Conference and Exhibition, 4--8 March 2002",
  title =        "Multiple-precision circuits allocation independent of
                 data-objects length",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "909--913",
  year =         "2002",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 16:53:44 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "This paper presents an heuristic method to solve the
                 combined resource selection and binding problems for
                 the high-level synthesis of multiple-precision
                 specifications. Traditionally, the number of functional
                 (and storage) units in a datapath is \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Moller:2002:PEC
author: Bodo Moller
journal: j-LECT-NOTES-COMP-SCI
volume: 2433
pages: 402--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:10:26 MDT 2002
bibtimestamp: 2002.09.10 19:10:26 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Bodo M{\"o}ller
title:
Parallelizable Elliptic Curve Point Multiplication Method with Resistance against Side-Channel Attacks

bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2433.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2433/24330402.htm; http://link.springer-ny.com/link/service/series/0558/papers/2433/24330402.pdf

rawtitle:
Parallelizable Elliptic Curve Point Multiplication Method with Resistance against Side-Channel Attacks

entry:
@Article{Moller:2002:PEC,
  author =       "Bodo M{\"o}ller",
  title =        "Parallelizable Elliptic Curve Point Multiplication
                 Method with Resistance against Side-Channel Attacks",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2433",
  pages =        "402--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:10:26 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2433.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2433/24330402.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2433/24330402.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Motegi:2002:EGG
author: Makoto Motegi and Naofumi Homma and Takafumi Aoki and Tatsuo Higuchi
title: Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis
journal: j-LECT-NOTES-COMP-SCI
volume: 2439
pages: 831--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Sat Nov 30 20:57:24 MST 2002
bibtimestamp: 2002.11.30 20:57:24 MST
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Makoto Motegi and Naofumi Homma and Takafumi Aoki and Tatsuo Higuchi
rawtitle: Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2439.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer.de/link/service/series/0558/bibs/2439/24390831.htm; http://link.springer.de/link/service/series/0558/papers/2439/24390831.pdf

entry:
@Article{Motegi:2002:EGG,
  author =       "Makoto Motegi and Naofumi Homma and Takafumi Aoki and
                 Tatsuo Higuchi",
  title =        "Evolutionary Graph Generation System and Its
                 Application to Bit-Serial Arithmetic Circuit
                 Synthesis",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2439",
  pages =        "831--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Sat Nov 30 20:57:24 MST 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2439.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer.de/link/service/series/0558/bibs/2439/24390831.htm;
                 http://link.springer.de/link/service/series/0558/papers/2439/24390831.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Okeya:2002:FSM
author: Katsuyuki Okeya and Kunihiko Miyazaki and Kouichi Sakurai
journal: j-LECT-NOTES-COMP-SCI
volume: 2288
pages: 428--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:09:14 MDT 2002
bibtimestamp: 2002.09.10 19:09:14 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Katsuyuki Okeya and Kunihiko Miyazaki and Kouichi Sakurai
title:
A Fast Scalar Multiplication Method with Randomized Projective Coordinates on a Montgomery-Form Elliptic Curve Secure against Side Channel Attacks

bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2288.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2288/22880428.htm; http://link.springer-ny.com/link/service/series/0558/papers/2288/22880428.pdf

rawtitle:
A Fast Scalar Multiplication Method with Randomized Projective Coordinates on a {Montgomery}-Form Elliptic Curve Secure against Side Channel Attacks

entry:
@Article{Okeya:2002:FSM,
  author =       "Katsuyuki Okeya and Kunihiko Miyazaki and Kouichi
                 Sakurai",
  title =        "A Fast Scalar Multiplication Method with Randomized
                 Projective Coordinates on a {Montgomery}-Form Elliptic
                 Curve Secure against Side Channel Attacks",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2288",
  pages =        "428--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:09:14 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2288.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2288/22880428.htm;
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  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: book
filename: fparith.bib
label: Overton:2002:CNC
author: Michael L. Overton
title: Computo numerico con aritmetica de punto flotante IEEE
volume: 19
publisher: Sociedad Matematica Mexicana
address: Mexico
pages: xii + 123
year: 2002
ISBN: 970-32-0086-9 OR 9703200869
ISBN13: 978-970-32-0086-3 OR 9789703200863
MRclass: 65-02 (65Bxx 65G30)
MRnumber: MR1925397 (2003g:65003)
bibdate: Thu Nov 8 19:16:14 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 19:16:14 ???
series: Aportaciones Matematicas: Textos [Mathematical Contributions: Texts]
acknowledgement: ack-nhfb
rawauthor: Michael L. Overton
rawtitle: {C}{\'o}mputo num{\'e}rico con aritm{\'e}tica de punto flotante {IEEE}
note:
Con un teorema, una regla empirica y ciento un ejercicios. [Including one theorem, one rule of thumb and one hundred and one exercises], Translated from the 2001 English original by Alejandro Casares Maldonado

rawnote:
Con un teorema, una regla emp{\'\i}rica y ciento un ejercicios. [Including one theorem, one rule of thumb and one hundred and one exercises], Translated from the 2001 English original by Alejandro Casares Maldonado

entry:
@Book{Overton:2002:CNC,
  author =       "Michael L. Overton",
  title =        "{C}{\'o}mputo num{\'e}rico con aritm{\'e}tica de punto
                 flotante {IEEE}",
  volume =       "19",
  publisher =    "Sociedad Matem{\'a}tica Mexicana",
  address =      "M{\'e}xico",
  pages =        "xii + 123",
  year =         "2002",
  ISBN =         "970-32-0086-9",
  ISBN-13 =      "978-970-32-0086-3",
  MRclass =      "65-02 (65Bxx 65G30)",
  MRnumber =     "MR1925397 (2003g:65003)",
  bibdate =      "Thu Nov 8 19:16:14 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Con un teorema, una regla emp{\'\i}rica y ciento un
                 ejercicios. [Including one theorem, one rule of thumb
                 and one hundred and one exercises], Translated from the
                 2001 English original by Alejandro Casares Maldonado",
  series =       "Aportaciones Matem\'aticas: Textos [Mathematical
                 Contributions: Texts]",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Paliouras:2002:LPC
author: V. Paliouras and A. Skavantzos and T. Stouraitis
booktitle: ISCAS 2002, IEEE International Symposium on Circuits and Systems, 26--29 May 2002
title: Low power convolvers using the Polynomial Residue Number System
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: II-748--II-751
year: 2002
DOI: https://doi.org/10.1109/ISCAS.2002.1011461
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: V. Paliouras and A. Skavantzos and T. Stouraitis
rawbooktitle: {ISCAS 2002}, {IEEE} International Symposium on Circuits and Systems, 26--29 May 2002
rawtitle: Low power convolvers using the {Polynomial Residue Number System}
entry:
@InProceedings{Paliouras:2002:LPC,
  author =       "V. Paliouras and A. Skavantzos and T. Stouraitis",
  booktitle =    "{ISCAS 2002}, {IEEE} International Symposium on
                 Circuits and Systems, 26--29 May 2002",
  title =        "Low power convolvers using the {Polynomial Residue
                 Number System}",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "II-748--II-751",
  year =         "2002",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.2002.1011461",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A novel approach for the reduction of the power
                 dissipated in a signal processing application is
                 introduced in this paper. By exploiting the properties
                 of the Polynomial Residue Number System (PRNS) and of
                 the arithmetic modulo (2/sup n/+1), the \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Paliouras:2002:OLO
author: V. Paliouras
booktitle: IEEE International Symposium on Circuits and Systems: ISCAS 2002, 26--29 May 2002
title: Optimization of LNS operations for embedded signal processing applications
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: II-744--II-747
year: 2002
bibdate: Sat Jul 16 16:14:38 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 16:14:38 MDT
acknowledgement: ack-nhfb
rawauthor: V. Paliouras
rawbooktitle: {IEEE} International Symposium on Circuits and Systems: {ISCAS 2002}, 26--29 May 2002
rawtitle: Optimization of {LNS} operations for embedded signal processing applications
entry:
@InProceedings{Paliouras:2002:OLO,
  author =       "V. Paliouras",
  booktitle =    "{IEEE} International Symposium on Circuits and
                 Systems: {ISCAS 2002}, 26--29 May 2002",
  title =        "Optimization of {LNS} operations for embedded signal
                 processing applications",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "II-744--II-747",
  year =         "2002",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 16:14:38 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "This paper introduces an optimization technique for
                 the design of logarithmic arithmetic-based embedded
                 signal processors. The fundamental concept of the
                 proposed technique is the determination of the optimal
                 values of the logarithmic base b, which \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Park:2002:SPM
author: Young-Ho Park and Sangtae Jeong and Jongin Lim
title: Speeding Up Point Multiplication on Hyperelliptic Curves with Efficiently-Computable Endomorphisms
journal: j-LECT-NOTES-COMP-SCI
volume: 2332
pages: 197--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:09:37 MDT 2002
bibtimestamp: 2002.09.10 19:09:37 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Young-Ho Park and Sangtae Jeong and Jongin Lim
rawtitle: Speeding Up Point Multiplication on Hyperelliptic Curves with Efficiently-Computable Endomorphisms
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2332.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2332/23320197.htm; http://link.springer-ny.com/link/service/series/0558/papers/2332/23320197.pdf

entry:
@Article{Park:2002:SPM,
  author =       "Young-Ho Park and Sangtae Jeong and Jongin Lim",
  title =        "Speeding Up Point Multiplication on Hyperelliptic
                 Curves with Efficiently-Computable Endomorphisms",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2332",
  pages =        "197--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:09:37 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2332.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2332/23320197.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2332/23320197.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Paul:2002:BB
author: Wolfgang J. Paul and Peter-Michael Seidel
title: To Booth or not to Booth?
journal: j-INTEGRATION-VLSI-J
volume: 32
number: 1--3
pages: 5--40
month: nov
monthnumber: 11
year: 2002
CODEN: IVJODL
ISSN: 0167-9260 (print), 1872-7522 (electronic) OR 01679260 (print), 18727522 (electronic)
ISSNL: 0167-9260 OR 01679260
bibdate: Mon Dec 24 10:05:36 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.12.24 10:05:36 ???
fjournal: Integration, the VLSI journal
acknowledgement: ack-nhfb
rawauthor: Wolfgang J. Paul and Peter-Michael Seidel
rawtitle: To {Booth} or not to {Booth}?
abstract:
Booth Recoding is a commonly used technique to recode one of the operands in binary multiplication. In this way the implementation of a multipliers' adder tree can be improved in both cost and delay. The improvement due to Booth Recoding is said to be due to improvements in the layout of the adder tree especially regarding the lengths of wire connections and thus cannot be analyzed with a simple gate model. Although conventional VLSI models consider wires in layouts, they usually neglect wires when modeling the delay. To make the layout improvements due to Booth recoding tractable in a technology-independent way, we introduce a VLSI model that also considers wire delays and constant factors. Based on this model we consider the layouts of binary multipliers in a parametric analysis providing answers to the question whether to use Booth Recoding or not. We formalize and prove the folklore theorems that Booth recoding improves the cost and cycle time of standard' multipliers by certain constant factors. We also analyze the number of full adders in certain 4/2 trees.

rawabstract:
Booth Recoding is a commonly used technique to recode one of the operands in binary multiplication. In this way the implementation of a multipliers' adder tree can be improved in both cost and delay. The improvement due to Booth Recoding is said to be due to improvements in the layout of the adder tree especially regarding the lengths of wire connections and thus cannot be analyzed with a simple gate model. Although conventional VLSI models consider wires in layouts, they usually neglect wires when modeling the delay. To make the layout improvements due to Booth recoding tractable in a technology-independent way, we introduce a VLSI model that also considers wire delays and constant factors. Based on this model we consider the layouts of binary multipliers in a parametric analysis providing answers to the question whether to use Booth Recoding or not. We formalize and prove the folklore theorems that Booth recoding improves the cost and cycle time of standard' multipliers by certain constant factors. We also analyze the number of full adders in certain 4/2 trees.

entry:
@Article{Paul:2002:BB,
  author =       "Wolfgang J. Paul and Peter-Michael Seidel",
  title =        "To {Booth} or not to {Booth}?",
  journal =      j-INTEGRATION-VLSI-J,
  volume =       "32",
  number =       "1--3",
  pages =        "5--40",
  month =        nov,
  year =         "2002",
  CODEN =        "IVJODL",
  ISSN =         "0167-9260 (print), 1872-7522 (electronic)",
  ISSN-L =       "0167-9260",
  bibdate =      "Mon Dec 24 10:05:36 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Booth Recoding is a commonly used technique to recode
                 one of the operands in binary multiplication. In this
                 way the implementation of a multipliers' adder tree can
                 be improved in both cost and delay. The improvement due
                 to Booth Recoding is said to be due to improvements in
                 the layout of the adder tree especially regarding the
                 lengths of wire connections and thus cannot be analyzed
                 with a simple gate model. Although conventional VLSI
                 models consider wires in layouts, they usually neglect
                 wires when modeling the delay. To make the layout
                 improvements due to Booth recoding tractable in a
                 technology-independent way, we introduce a VLSI model
                 that also considers wire delays and constant factors.
                 Based on this model we consider the layouts of binary
                 multipliers in a parametric analysis providing answers
                 to the question whether to use Booth Recoding or not.
                 We formalize and prove the folklore theorems that Booth
                 recoding improves the cost and cycle time of standard'
                 multipliers by certain constant factors. We also
                 analyze the number of full adders in certain 4/2
                 trees.",
  acknowledgement = ack-nhfb,
  fjournal =     "Integration, the VLSI journal",
}


bibtype: inproceedings
filename: fparith.bib
label: Pillmeier:2002:DAB
author: M. R. Pillmeier and M. J. Schulte
title: Design Alternatives for Barrel Shifters and Rotators
crossref: Luk:2002:PSA
pages: 436--447
year: 2002
bibdate: Sun Mar 04 17:45:23 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 17:45:23 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2002-02.pdf
acknowledgement: ack-nhfb
rawauthor: M. R. Pillmeier and M. J. Schulte
rawtitle: Design Alternatives for Barrel Shifters and Rotators
entry:
@InProceedings{Pillmeier:2002:DAB,
  author =       "M. R. Pillmeier and M. J. Schulte",
  title =        "Design Alternatives for Barrel Shifters and Rotators",
  crossref =     "Luk:2002:PSA",
  pages =        "436--447",
  year =         "2002",
  bibdate =      "Sun Mar 04 17:45:23 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2002-02.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Pineiro:2002:HRL
author: J.-A. Pineiro and M. D. Ercegovac and J. D. Bruguera
title: High-radix logarithm with selection by rounding
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 101--110
year: 2002
bibdate: Sat Jul 16 11:25:05 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:05 MDT
acknowledgement: ack-nhfb
rawauthor: J.-A. Pineiro and M. D. Ercegovac and J. D. Bruguera
rawtitle: High-radix logarithm with selection by rounding
booktitle:
Application-Specific Systems, Architectures and Processors, 2002. Proceedings. The IEEE International Conference on. 17--19 July 2002

rawbooktitle:
Application-Specific Systems, Architectures and Processors, 2002. Proceedings. The {IEEE} International Conference on. 17--19 July 2002

entry:
@InProceedings{Pineiro:2002:HRL,
  author =       "J.-A. Pineiro and M. D. Ercegovac and J. D. Bruguera",
  booktitle =    "Application-Specific Systems, Architectures and
                 Processors, 2002. Proceedings. The {IEEE} International
                 Conference on. 17--19 July 2002",
  title =        "High-radix logarithm with selection by rounding",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "101--110",
  year =         "2002",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 11:25:05 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "A high-radix digit-recurrence algorithm or the
                 computation of the logarithm is presented in this
                 paper. Selection by rounding is used in iterations
                 j/spl ges/2, and selection by table in the first
                 iteration is combined with a restricted digit-set
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Pineiro:2002:HSD
author: J. A. Pineiro and J. D. Bruguera
journal: j-IEEE-TRANS-COMPUT
volume: 51
number: 12
pages: 1377--1388
month: dec
monthnumber: 12
year: 2002
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2002.1146704
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 09:42:01 MDT 2011
bibtimestamp: 2011.07.05 09:42:01 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1146704
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. A. Pi{\~n}eiro and J. D. Bruguera
title:
High-Speed Double Precision Computation of Reciprocal, Division, Square Root, and Inverse Square Root

rawtitle:
High-Speed Double Precision Computation of Reciprocal, Division, Square Root, and Inverse Square Root

entry:
@Article{Pineiro:2002:HSD,
  author =       "J. A. Pi{\~n}eiro and J. D. Bruguera",
  title =        "High-Speed Double Precision Computation of Reciprocal,
                 Division, Square Root, and Inverse Square Root",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "51",
  number =       "12",
  pages =        "1377--1388",
  month =        dec,
  year =         "2002",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2002.1146704",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 09:42:01 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1146704",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  summary =      "A new method for the high-speed computation of
                 double-precision floating-point reciprocal, division,
                 square root, and inverse square root operations is
                 presented in this paper. This method employs a
                 second-degree minimax polynomial approximation to
                 \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Puchta:2002:RNN
author: Jan-Christoph Puchta
title: Representation of Numbers with Negative Digits and Multiplication of Small Integers
journal: j-FIB-QUART
volume: 40
number: 1
pages: 66--67
month: feb
monthnumber: 2
year: 2002
CODEN: FIBQAU
ISSN: 0015-0517 OR 00150517
ISSNL: 0015-0517 OR 00150517
bibdate: Thu Oct 20 18:03:31 MDT 2011
bibtimestamp: 2011.10.20 18:03:31 MDT
URL: http://www.fq.math.ca/Scanned/40-1/puchta1.pdf
fjournal: The Fibonacci Quarterly. Official Organ of the Fibonacci Association
acknowledgement: ack-nhfb
ajournal: Fib. Quart
journalURL: http://www.fq.math.ca/
rawauthor: Jan-Christoph Puchta
rawtitle: Representation of Numbers with Negative Digits and Multiplication of Small Integers
bibsource:
http://www.fq.math.ca/40-1.html; https://www.math.utah.edu/pub/tex/bib/fibquart.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Puchta:2002:RNN,
  author =       "Jan-Christoph Puchta",
  title =        "Representation of Numbers with Negative Digits and
                 Multiplication of Small Integers",
  journal =      j-FIB-QUART,
  volume =       "40",
  number =       "1",
  pages =        "66--67",
  month =        feb,
  year =         "2002",
  CODEN =        "FIBQAU",
  ISSN =         "0015-0517",
  ISSN-L =       "0015-0517",
  bibdate =      "Thu Oct 20 18:03:31 MDT 2011",
  bibsource =    "http://www.fq.math.ca/40-1.html;
                 https://www.math.utah.edu/pub/tex/bib/fibquart.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.fq.math.ca/Scanned/40-1/puchta1.pdf",
  acknowledgement = ack-nhfb,
  ajournal =     "Fib. Quart",
  fjournal =     "The Fibonacci Quarterly. Official Organ of the
                 Fibonacci Association",
  journal-URL =  "http://www.fq.math.ca/",
}


bibtype: article
filename: fparith.bib
label: Ramasubramanian:2002:ACL
author: Narasimhan Ramasubramanian and Ram Subramanian and Santosh Pande
journal: j-IEEE-TRANS-PAR-DIST-SYS
volume: 13
number: 1
pages: 45--66
month: jan
monthnumber: 1
year: 2002
CODEN: ITDSEO
ISSN: 1045-9219 (print), 1558-2183 (electronic) OR 10459219 (print), 15582183 (electronic)
ISSNL: 1045-9219 OR 10459219
bibdate: Sat Feb 23 09:26:04 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.02.23 09:26:04 MST
fjournal: IEEE Transactions on Parallel and Distributed Systems
acknowledgement: ack-nhfb
journalURL: http://www.computer.org/tpds/archives.htm
rawauthor: Narasimhan Ramasubramanian and Ram Subramanian and Santosh Pande
title:
Automatic Compilation of Loops to Exploit Operator Parallelism on Configurable Arithmetic Logic Units

URL:
http://dlib.computer.org/td/books/td2002/pdf/l0045.pdf; http://www.computer.org/tpds/td2001/l0045abs.htm

rawtitle:
Automatic Compilation of Loops to Exploit Operator Parallelism on Configurable Arithmetic Logic Units

entry:
@Article{Ramasubramanian:2002:ACL,
  author =       "Narasimhan Ramasubramanian and Ram Subramanian and
                 Santosh Pande",
  title =        "Automatic Compilation of Loops to Exploit Operator
                 Parallelism on Configurable Arithmetic Logic Units",
  journal =      j-IEEE-TRANS-PAR-DIST-SYS,
  volume =       "13",
  number =       "1",
  pages =        "45--66",
  month =        jan,
  year =         "2002",
  CODEN =        "ITDSEO",
  ISSN =         "1045-9219 (print), 1558-2183 (electronic)",
  ISSN-L =       "1045-9219",
  bibdate =      "Sat Feb 23 09:26:04 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://dlib.computer.org/td/books/td2002/pdf/l0045.pdf;
                 http://www.computer.org/tpds/td2001/l0045abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Parallel and Distributed
                 Systems",
  journal-URL =  "http://www.computer.org/tpds/archives.htm",
}


bibtype: article
filename: fparith.bib
label: Ramirez:2002:FRF
author: J. Ramirez and A. Garcia and U. Meyer-Baese and A. Lloris
title: Fast RNS FPL-based Communications Receiver Design and Implementation
journal: j-LECT-NOTES-COMP-SCI
volume: 2438
pages: 472--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:10:28 MDT 2002
bibtimestamp: 2002.09.10 19:10:28 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: J. Ram{\'\i}rez and A. Garc{\'\i}a and U. Meyer-Baese and A. Lloris
rawtitle: Fast {RNS} {FPL}-based Communications Receiver Design and Implementation
URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2438/24380472.htm; http://link.springer-ny.com/link/service/series/0558/papers/2438/24380472.pdf

entry:
@Article{Ramirez:2002:FRF,
  author =       "J. Ram{\'\i}rez and A. Garc{\'\i}a and U. Meyer-Baese
                 and A. Lloris",
  title =        "Fast {RNS} {FPL}-based Communications Receiver Design
                 and Implementation",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2438",
  pages =        "472--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:10:28 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2438.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2438/24380472.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2438/24380472.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Reid-Green:2002:TEA
author: Keith S. Reid-Green
journal: j-IEEE-ANN-HIST-COMPUT
volume: 24
number: 4
pages: 10--13
month: oct
monthnumber: 10
year: 2002
CODEN: IAHCEX
DOI: https://doi.org/10.1109/MAHC.2002.1114866
ISSN: 1058-6180 (print), 1934-1547 (electronic) OR 10586180 (print), 19341547 (electronic)
ISSNL: 1058-6180 OR 10586180
bibdate: Sat Nov 29 16:19:45 MST 2003
bibtimestamp: 2003.11.29 16:19:45 MST
fjournal: IEEE Annals of the History of Computing
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=85
rawauthor: Keith S. Reid-Green
title:
Three early algorithms: [Bresenham's line-drawing algorithm; a square-root algorithm; Machin's algorithm: computation of $ pi $ ]

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeeannhistcomput.bib; https://www.math.utah.edu/pub/tex/bib/pi.bib

URL:
http://csdl.computer.org/dl/mags/an/2002/04/a4010.htm; http://csdl.computer.org/dl/mags/an/2002/04/a4010.pdf; http://csdl.computer.org/dl/mags/an/2002/04/a4010abs.htm

rawtitle:
Three early algorithms: [{Bresenham}'s line-drawing algorithm; a square-root algorithm; {Machin}'s algorithm: computation of $ \pi $ ]

entry:
@Article{Reid-Green:2002:TEA,
  author =       "Keith S. Reid-Green",
  title =        "Three early algorithms: [{Bresenham}'s line-drawing
                 algorithm; a square-root algorithm; {Machin}'s
                 algorithm: computation of $ \pi $ ]",
  journal =      j-IEEE-ANN-HIST-COMPUT,
  volume =       "24",
  number =       "4",
  pages =        "10--13",
  month =        oct,
  year =         "2002",
  CODEN =        "IAHCEX",
  DOI =          "https://doi.org/10.1109/MAHC.2002.1114866",
  ISSN =         "1058-6180 (print), 1934-1547 (electronic)",
  ISSN-L =       "1058-6180",
  bibdate =      "Sat Nov 29 16:19:45 MST 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeeannhistcomput.bib;
                 https://www.math.utah.edu/pub/tex/bib/pi.bib",
  URL =          "http://csdl.computer.org/dl/mags/an/2002/04/a4010.htm;
                 http://csdl.computer.org/dl/mags/an/2002/04/a4010.pdf;
                 http://csdl.computer.org/dl/mags/an/2002/04/a4010abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Annals of the History of Computing",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=85",
}


bibtype: techreport
filename: fparith.bib
label: Revol:2002:MAPa
author: N. Revol and F. Rouillier
title: Motivations for an Arbitrary Precision Interval Arithmetic and the MPFI Library
type: Report
pages: 6
day: 17
month: apr
monthnumber: 4
year: 2002
bibdate: Fri Mar 10 16:23:31 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.03.10 16:23:31 ???
URL: http://pauillac.inria.fr/cdrom/www/mpfi/ValidC02.pdf
keywords: interval arithmetic; multiple precision
acknowledgement: ack-nhfb
rawauthor: N. Revol and F. Rouillier
rawtitle: Motivations for an Arbitrary Precision Interval Arithmetic and the {MPFI Library}
institution:
Laboratoire ANO, University of Lille and CNRS/ENSL/INRIA Project Arenaire LIP, Ecole Normale Superieure de Lyon, France, Project Spaces, LORIA/INRIA/LIP 6, France

entry:
@TechReport{Revol:2002:MAPa,
  author =       "N. Revol and F. Rouillier",
  title =        "Motivations for an Arbitrary Precision Interval
                 Arithmetic and the {MPFI Library}",
  type =         "Report",
  institution =  "Laboratoire ANO, University of Lille and
                 CNRS/ENSL/INRIA Project Arenaire LIP, {\'E}cole Normale
                 Sup{\'e}rieure de Lyon, France, Project Spaces,
                 LORIA/INRIA/LIP 6, France",
  pages =        "6",
  day =          "17",
  month =        apr,
  year =         "2002",
  bibdate =      "Fri Mar 10 16:23:31 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://pauillac.inria.fr/cdrom/www/mpfi/ValidC02.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "interval arithmetic; multiple precision",
}


bibtype: inproceedings
filename: fparith.bib
label: Revol:2002:MAPb
author: Nathalie Revol and Fabrice Rouillier
editor: R. Baker Kearfott
booktitle: SIAM Workshop on Validated Computing 2002, Toronto, Canada, May 23--25, 2002: extended abstracts
title: Motivations for an Arbitrary Precision Interval Arithmetic and the MPFI Library
publisher: pub-SIAM
address: pub-SIAM:adr
pages: ??--??
year: 2002
LCCN: QA76.76.R44 W67 2002
bibdate: Fri Jan 28 15:34:54 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.01.28 15:34:54 ???
acknowledgement: ack-nhfb
bookpages: 187
rawauthor: Nathalie Revol and Fabrice Rouillier
rawbooktitle: {SIAM} Workshop on Validated Computing 2002, Toronto, Canada, May 23--25, 2002: extended abstracts
raweditor: R. Baker Kearfott
rawtitle: Motivations for an Arbitrary Precision Interval Arithmetic and the {MPFI Library}
abstract:
MPFI is a library implementing interval arithmetic with arbitrary accuracy. It can be freely downloaded (including source code and documentation). It is written in C and is based on the MPFR library for arbitrary precision floating-point arithmetic, which is in turn built upon the GMP library. MPFR has been chosen because it provides outward rounding, even for the elementary functions, which is mandatory to implement interval arithmetic. An important issue in interval computation is ``computing in the large'', i.e., getting tight enclosures for the range of a function over a large interval. However, this issue has no well established answer, and one common way to circumvent the problem consists in bisecting the input interval again and again, until the evaluation of the function upon each sub-part is tight enough. For some problems, such as roots approximations or optimization of a ``very flat'' function, splitting beyond the limits of usual (single or double) floating-point capacities reveals necessary in order to reach the required accuracy on the function evaluation.

rawabstract:
MPFI is a library implementing interval arithmetic with arbitrary accuracy. It can be freely downloaded (including source code and documentation). It is written in C and is based on the MPFR library for arbitrary precision floating-point arithmetic, which is in turn built upon the GMP library. MPFR has been chosen because it provides outward rounding, even for the elementary functions, which is mandatory to implement interval arithmetic. An important issue in interval computation is ``computing in the large'', i.e., getting tight enclosures for the range of a function over a large interval. However, this issue has no well established answer, and one common way to circumvent the problem consists in bisecting the input interval again and again, until the evaluation of the function upon each sub-part is tight enough. For some problems, such as roots approximations or optimization of a ``very flat'' function, splitting beyond the limits of usual (single or double) floating-point capacities reveals necessary in order to reach the required accuracy on the function evaluation.

entry:
@InProceedings{Revol:2002:MAPb,
  author =       "Nathalie Revol and Fabrice Rouillier",
  editor =       "R. Baker Kearfott",
  booktitle =    "{SIAM} Workshop on Validated Computing 2002, Toronto,
                 Canada, May 23--25, 2002: extended abstracts",
  title =        "Motivations for an Arbitrary Precision Interval
                 Arithmetic and the {MPFI Library}",
  publisher =    pub-SIAM,
  address =      pub-SIAM:adr,
  bookpages =    "187",
  pages =        "??--??",
  year =         "2002",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "QA76.76.R44 W67 2002",
  bibdate =      "Fri Jan 28 15:34:54 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "MPFI is a library implementing interval arithmetic
                 with arbitrary accuracy. It can be freely downloaded
                 (including source code and documentation). It is
                 written in C and is based on the MPFR library for
                 arbitrary precision floating-point arithmetic, which is
                 in turn built upon the GMP library. MPFR has been
                 chosen because it provides outward rounding, even for
                 the elementary functions, which is mandatory to
                 implement interval arithmetic. An important issue in
                 interval computation is ``computing in the large'',
                 i.e., getting tight enclosures for the range of a
                 function over a large interval. However, this issue has
                 no well established answer, and one common way to
                 circumvent the problem consists in bisecting the input
                 interval again and again, until the evaluation of the
                 function upon each sub-part is tight enough. For some
                 problems, such as roots approximations or optimization
                 of a ``very flat'' function, splitting beyond the
                 limits of usual (single or double) floating-point
                 capacities reveals necessary in order to reach the
                 required accuracy on the function evaluation.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Reyhani-Masoleh:2002:NCM
author: A. Reyhani-Masoleh and M. A. Hasan
title: A new construction of Massey--Omura parallel multiplier over $ mathrm GF(2^m) $
journal: j-IEEE-TRANS-COMPUT
volume: 51
number: 5
pages: 511--520
month: may
monthnumber: 5
year: 2002
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2002.1004590
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 09:41:51 MDT 2011
bibtimestamp: 2011.07.05 09:41:51 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1004590
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Reyhani-Masoleh and M. A. Hasan
rawtitle: A new construction of {Massey--Omura} parallel multiplier over {$ \mathrm {GF}(2^m) $}
entry:
@Article{Reyhani-Masoleh:2002:NCM,
  author =       "A. Reyhani-Masoleh and M. A. Hasan",
  title =        "A new construction of {Massey--Omura} parallel
                 multiplier over {$ \mathrm {GF}(2^m) $}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "51",
  number =       "5",
  pages =        "511--520",
  month =        may,
  year =         "2002",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2002.1004590",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 09:41:51 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1004590",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Roesler:2002:NOH
author: Eric Roesler and Brent Nelson
title: Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture
journal: j-LECT-NOTES-COMP-SCI
volume: 2438
pages: 637--646
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:10:28 MDT 2002
bibtimestamp: 2002.09.10 19:10:28 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Eric Roesler and Brent Nelson
rawtitle: Novel Optimizations for Hardware Floating-Point Units in a Modern {FPGA} Architecture
URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2438/24380637.htm; http://link.springer-ny.com/link/service/series/0558/papers/2438/24380637.pdf

entry:
@Article{Roesler:2002:NOH,
  author =       "Eric Roesler and Brent Nelson",
  title =        "Novel Optimizations for Hardware Floating-Point Units
                 in a Modern {FPGA} Architecture",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2438",
  pages =        "637--646",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:10:28 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2438.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2438/24380637.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2438/24380637.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Saed:2002:NSC
author: A. Saed and M. Ahmadi and G. A. Jullien
title: A number system with continuous valued digits and modulo arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 51
number: 11
pages: 1294--1305
month: nov
monthnumber: 11
year: 2002
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2002.1047754
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 09:42:00 MDT 2011
bibtimestamp: 2011.07.05 09:42:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1047754
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Saed and M. Ahmadi and G. A. Jullien
rawtitle: A number system with continuous valued digits and modulo arithmetic
entry:
@Article{Saed:2002:NSC,
  author =       "A. Saed and M. Ahmadi and G. A. Jullien",
  title =        "A number system with continuous valued digits and
                 modulo arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "51",
  number =       "11",
  pages =        "1294--1305",
  month =        nov,
  year =         "2002",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2002.1047754",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 09:42:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1047754",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Sahin:2002:FFP
author: Ibrahim Sahin and Clay S. Gloster and Christopher Doss
title: Feasibility of floating-point arithmetic in reconfigurable computing systems
crossref: Vladimirova:2002:TMA
pages: ??--??
year: 2002
bibdate: Sat Oct 9 12:59:55 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 12:59:55 ???
URL: http://klabs.org/richcontent/MAPLDCon00/Abstracts/sahin_a.txt
acknowledgement: ack-nhfb
rawauthor: Ibrahim Sahin and Clay S. Gloster and Christopher Doss
rawtitle: Feasibility of floating-point arithmetic in reconfigurable computing systems
abstract:
Reconfigurable Computing (RC) has emerged as a viable computing solution for computationally intensive applications. Applications mapped to RC systems include image processing algorithms, pattern recognition in high energy physics and genetic optimization algorithms. Due to the hardware complexity of the floating point modules and limited resources available in prior RC systems, applications that required floating point operations were either, not mapped to RC systems, or converted to fixed point before developing the RC implementation. Recent advances in Field Programmable Gate Array (FPGA) technology offer the user more hardware resources on a single FPGA device and thus the greater potential to develop complex RC systems. In this paper, the feasibility of mapping applications containing floating point operations to RC systems is presented. Three floating point modules: vector addition, subtraction, and multiplication were modeled using VHDL and mapped to a Xilinx XC4044XL FPGA device. These modules are highly pipelined and optimized for both speed and area. Our results verify that floating point applications are feasible and that significant speedup can be obtained when mapping these applications to RC systems.

rawabstract:
Reconfigurable Computing (RC) has emerged as a viable computing solution for computationally intensive applications. Applications mapped to RC systems include image processing algorithms, pattern recognition in high energy physics and genetic optimization algorithms. Due to the hardware complexity of the floating point modules and limited resources available in prior RC systems, applications that required floating point operations were either, not mapped to RC systems, or converted to fixed point before developing the RC implementation. Recent advances in Field Programmable Gate Array (FPGA) technology offer the user more hardware resources on a single FPGA device and thus the greater potential to develop complex RC systems. In this paper, the feasibility of mapping applications containing floating point operations to RC systems is presented. Three floating point modules: vector addition, subtraction, and multiplication were modeled using VHDL and mapped to a Xilinx XC4044XL FPGA device. These modules are highly pipelined and optimized for both speed and area. Our results verify that floating point applications are feasible and that significant speedup can be obtained when mapping these applications to RC systems.

entry:
@InProceedings{Sahin:2002:FFP,
  author =       "Ibrahim Sahin and Clay S. Gloster and Christopher
                 Doss",
  title =        "Feasibility of floating-point arithmetic in
                 reconfigurable computing systems",
  crossref =     "Vladimirova:2002:TMA",
  pages =        "??--??",
  year =         "2002",
  bibdate =      "Sat Oct 9 12:59:55 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://klabs.org/richcontent/MAPLDCon00/Abstracts/sahin_a.txt",
  abstract =     "Reconfigurable Computing (RC) has emerged as a viable
                 computing solution for computationally intensive
                 applications. Applications mapped to RC systems include
                 image processing algorithms, pattern recognition in
                 high energy physics and genetic optimization
                 algorithms. Due to the hardware complexity of the
                 floating point modules and limited resources available
                 in prior RC systems, applications that required
                 floating point operations were either, not mapped to RC
                 systems, or converted to fixed point before developing
                 the RC implementation. Recent advances in Field
                 Programmable Gate Array (FPGA) technology offer the
                 user more hardware resources on a single FPGA device
                 and thus the greater potential to develop complex RC
                 systems. In this paper, the feasibility of mapping
                 applications containing floating point operations to RC
                 systems is presented. Three floating point modules:
                 vector addition, subtraction, and multiplication were
                 modeled using VHDL and mapped to a Xilinx XC4044XL FPGA
                 device. These modules are highly pipelined and
                 optimized for both speed and area. Our results verify
                 that floating point applications are feasible and that
                 significant speedup can be obtained when mapping these
                 applications to RC systems.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Sakai:2002:AES
author: Yasuyuki Sakai and Kouichi Sakurai
journal: j-LECT-NOTES-COMP-SCI
volume: 2433
pages: 484--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:10:26 MDT 2002
bibtimestamp: 2002.09.10 19:10:26 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Yasuyuki Sakai and Kouichi Sakurai
title:
Algorithms for Efficient Simultaneous Elliptic Scalar Multiplication with Reduced Joint Hamming Weight Representation of Scalars

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2433/24330484.htm; http://link.springer-ny.com/link/service/series/0558/papers/2433/24330484.pdf

rawtitle:
Algorithms for Efficient Simultaneous Elliptic Scalar Multiplication with Reduced Joint {Hamming} Weight Representation of Scalars

entry:
@Article{Sakai:2002:AES,
  author =       "Yasuyuki Sakai and Kouichi Sakurai",
  title =        "Algorithms for Efficient Simultaneous Elliptic Scalar
                 Multiplication with Reduced Joint {Hamming} Weight
                 Representation of Scalars",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2433",
  pages =        "484--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:10:26 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2433.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2433/24330484.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2433/24330484.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: inproceedings
filename: fparith.bib
label: Sawada:2002:FVD
author: J. Sawada
title: Formal verification of divide and square root algorithms using series calculation
crossref: Borrione:2002:TIW
pages: 31--49
year: 2002
bibdate: Fri Jun 24 15:14:00 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 15:14:00 ???
acknowledgement: ack-nhfb
rawauthor: J. Sawada
rawtitle: Formal verification of divide and square root algorithms using series calculation
entry:
@InProceedings{Sawada:2002:FVD,
  author =       "J. Sawada",
  title =        "Formal verification of divide and square root
                 algorithms using series calculation",
  crossref =     "Borrione:2002:TIW",
  pages =        "31--49",
  year =         "2002",
  bibdate =      "Fri Jun 24 15:14:00 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Sawada:2002:MVS
author: Jun Sawada and Ruben Gamboa
title: Mechanical Verification of a Square Root Algorithm Using Taylor's Theorem
journal: j-LECT-NOTES-COMP-SCI
volume: 2517
pages: 274--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Sat Nov 30 20:58:00 MST 2002
bibtimestamp: 2002.11.30 20:58:00 MST
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Jun Sawada and Ruben Gamboa
rawtitle: Mechanical Verification of a Square Root Algorithm Using {Taylor}'s Theorem
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2517.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer.de/link/service/series/0558/bibs/2517/25170274.htm; http://link.springer.de/link/service/series/0558/papers/2517/25170274.pdf

entry:
@Article{Sawada:2002:MVS,
  author =       "Jun Sawada and Ruben Gamboa",
  title =        "Mechanical Verification of a Square Root Algorithm
                 Using {Taylor}'s Theorem",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2517",
  pages =        "274--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Sat Nov 30 20:58:00 MST 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2517.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer.de/link/service/series/0558/bibs/2517/25170274.htm;
                 http://link.springer.de/link/service/series/0558/papers/2517/25170274.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Schwarz:2002:MIE
title: The microarchitecture of the IBM eServer z900 processor
journal: j-IBM-JRD
volume: 46
number: 4/5
pages: 381--395
year: 2002
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Fri Nov 22 17:58:43 MST 2002
bibsource: http://www.research.ibm.com/journal/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.22 17:58:43 MST
fjournal: IBM Journal of Research and Development
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawtitle: The microarchitecture of the {IBM eServer z900} processor
author:
E. M. Schwarz and M. A. Check and C.-L. K. Shum and T. Koehler and S. B. Swaney and J. D. MacDougall and C. A. Krygowski

URL:
http://www.research.ibm.com/journal/rd/464/schwarz.html; http://www.research.ibm.com/journal/rd/464/schwarz.pdf

abstract:
The recent IBM ESA/390 CMOS line of processors, from 1997 to 1999, consisted of the G4, G5, and G6 processors. The architecture they implemented lacked 64-bit addressability and had only a limited set of 64-bit arithmetic instructions. The processors also lacked data and instruction bandwidth, since they utilized a unified cache. The branch performance was good, but there were delays due to conflicts in searching and writing the branch target buffer. Also, the hardware data compression and decimal arithmetic performance, though good, was in demand by database and COBOL programmers. Most of the performance concerns regarding prior processors were due to area constraints. Recent technology advances have increased the circuit density by 50 percent over that of the G6 processor. This has allowed the design of several performance-critical areas to be revisited. The end result of these efforts is the IBM eServer z900 processor, which is the first high-end processor based on the new 64-bit z/ArchitectureTM .

rawabstract:
The recent IBM ESA/390 CMOS line of processors, from 1997 to 1999, consisted of the G4, G5, and G6 processors. The architecture they implemented lacked 64-bit addressability and had only a limited set of 64-bit arithmetic instructions. The processors also lacked data and instruction bandwidth, since they utilized a unified cache. The branch performance was good, but there were delays due to conflicts in searching and writing the branch target buffer. Also, the hardware data compression and decimal arithmetic performance, though good, was in demand by database and COBOL programmers. Most of the performance concerns regarding prior processors were due to area constraints. Recent technology advances have increased the circuit density by 50 percent over that of the G6 processor. This has allowed the design of several performance-critical areas to be revisited. The end result of these efforts is the IBM eServer z900 processor, which is the first high-end processor based on the new 64-bit z/Architecture{\TM}.

rawauthor:
E. M. Schwarz and M. A. Check and C.-L. K. Shum and T. Koehler and S. B. Swaney and J. D. MacDougall and C. A. Krygowski

entry:
@Article{Schwarz:2002:MIE,
  author =       "E. M. Schwarz and M. A. Check and C.-L. K. Shum and T.
                 Koehler and S. B. Swaney and J. D. MacDougall and C. A.
                 Krygowski",
  title =        "The microarchitecture of the {IBM eServer z900}
                 processor",
  journal =      j-IBM-JRD,
  volume =       "46",
  number =       "4/5",
  pages =        "381--395",
  month =        "????",
  year =         "2002",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Fri Nov 22 17:58:43 MST 2002",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.research.ibm.com/journal/rd/464/schwarz.html;
                 http://www.research.ibm.com/journal/rd/464/schwarz.pdf",
  abstract =     "The recent IBM ESA/390 CMOS line of processors, from
                 1997 to 1999, consisted of the G4, G5, and G6
                 processors. The architecture they implemented lacked
                 64-bit addressability and had only a limited set of
                 64-bit arithmetic instructions. The processors also
                 lacked data and instruction bandwidth, since they
                 utilized a unified cache. The branch performance was
                 good, but there were delays due to conflicts in
                 searching and writing the branch target buffer. Also,
                 the hardware data compression and decimal arithmetic
                 performance, though good, was in demand by database and
                 COBOL programmers. Most of the performance concerns
                 regarding prior processors were due to area
                 constraints. Recent technology advances have increased
                 the circuit density by 50 percent over that of the G6
                 processor. This has allowed the design of several
                 performance-critical areas to be revisited. The end
                 result of these efforts is the IBM eServer z900
                 processor, which is the first high-end processor based
                 on the new 64-bit z/Architecture{\TM}.",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "decimal floating-point arithmetic",
  ordernumber =  "G322-0232",
}


bibtype: article
filename: fparith.bib
label: Serebrenik:2002:TLP
author: Alexander Serebrenik and Danny De Schreye
title: On Termination of Logic Programs with Floating Point Computations
journal: j-LECT-NOTES-COMP-SCI
volume: 2477
pages: 151--164
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
MRnumber: MR2049473
bibdate: Tue Sep 10 19:11:24 MDT 2002
bibtimestamp: 2002.09.10 19:11:24 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Alexander Serebrenik and Danny De Schreye
rawtitle: On Termination of Logic Programs with Floating Point Computations
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2477.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2477/24770151.htm; http://link.springer-ny.com/link/service/series/0558/papers/2477/24770151.pdf

entry:
@Article{Serebrenik:2002:TLP,
  author =       "Alexander Serebrenik and Danny De Schreye",
  title =        "On Termination of Logic Programs with Floating Point
                 Computations",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2477",
  pages =        "151--164",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  MRnumber =     "MR2049473",
  bibdate =      "Tue Sep 10 19:11:24 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2477.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2477/24770151.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2477/24770151.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: mastersthesis
filename: fparith.bib
label: Shi:2002:SMF
author: Changchun Shi
title: Statistical method for floating-point to fixed-point conversion
type: Master of Science, Plan II
school: Department of Electrical Engineering and Computer Sciences, University of California, Berkeley
address: Berkeley, CA, USA
pages: x + 131
year: 2002
LCCN: T7.49.2002 S55
bibdate: Thu Oct 24 14:20:51 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.10.24 14:20:51 ???
acknowledgement: ack-nhfb
rawauthor: Changchun Shi
rawtitle: Statistical method for floating-point to fixed-point conversion
entry:
@MastersThesis{Shi:2002:SMF,
  author =       "Changchun Shi",
  title =        "Statistical method for floating-point to fixed-point
                 conversion",
  type =         "{Master of Science, Plan II}",
  school =       "Department of Electrical Engineering and Computer
                 Sciences, University of California, Berkeley",
  address =      "Berkeley, CA, USA",
  pages =        "x + 131",
  year =         "2002",
  LCCN =         "T7.49.2002 S55",
  bibdate =      "Thu Oct 24 14:20:51 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Soudris:2002:FAB
author: D. Soudris and M. Dasygenis and K. Mitroglou and K. Tatas and A. Thanailakis
booktitle: 9th International Conference on Electronics, Circuits and Systems, 2002
title: A full adder based methodology for scaling operation in residue number system
volume: 3
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 891--894
year: 2002
DOI: https://doi.org/10.1109/ICECS.2002.1046391
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: D. Soudris and M. Dasygenis and K. Mitroglou and K. Tatas and A. Thanailakis
rawbooktitle: 9th International Conference on Electronics, Circuits and Systems, 2002
rawtitle: A full adder based methodology for scaling operation in residue number system
entry:
@InProceedings{Soudris:2002:FAB,
  author =       "D. Soudris and M. Dasygenis and K. Mitroglou and K.
                 Tatas and A. Thanailakis",
  booktitle =    "9th International Conference on Electronics, Circuits
                 and Systems, 2002",
  title =        "A full adder based methodology for scaling operation
                 in residue number system",
  volume =       "3",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "891--894",
  year =         "2002",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICECS.2002.1046391",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "A systematic methodology for designing
                 full-adder-based architectures in residue number system
                 for scaling operation and its software tool
                 development, are introduced. Starting from the
                 mathematical description of scaling operation in RNS,
                 we end up \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Spiteri:2002:PPA
author: Pierre Spiteri and Jean-Claude Miellou and Didier El Baz
title: Perturbation of parallel asynchronous linear iterations by floating point errors
journal: j-ELECTRON-TRANS-NUMER-ANAL
volume: 13
pages: 38--55
year: 2002
ISSN: 1068-9613 (print), 1097-4067 (electronic) OR 10689613 (print), 10974067 (electronic)
ISSNL: 1068-9613 OR 10689613
MRclass: 65F10 (65G50 65Y05)
MRnumber: MR1924261 (2003h:65042)
bibdate: Thu Nov 8 19:16:14 2007
bibsource: http://etna.mcs.kent.edu/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 19:16:14 ???
URL: http://etna.mcs.kent.edu/vol.13.2002/pp38-55.dir/pp38-55.pdf
fjournal: Electronic Transactions on Numerical Analysis
acknowledgement: ack-nhfb
journalURL: http://etna.mcs.kent.edu/
rawauthor: Pierre Spiteri and Jean-Claude Miellou and Didier El Baz
rawtitle: Perturbation of parallel asynchronous linear iterations by floating point errors
entry:
@Article{Spiteri:2002:PPA,
  author =       "Pierre Spiteri and Jean-Claude Miellou and Didier El
                 Baz",
  title =        "Perturbation of parallel asynchronous linear
                 iterations by floating point errors",
  journal =      j-ELECTRON-TRANS-NUMER-ANAL,
  volume =       "13",
  pages =        "38--55",
  year =         "2002",
  CODEN =        "????",
  ISSN =         "1068-9613 (print), 1097-4067 (electronic)",
  ISSN-L =       "1068-9613",
  MRclass =      "65F10 (65G50 65Y05)",
  MRnumber =     "MR1924261 (2003h:65042)",
  bibdate =      "Thu Nov 8 19:16:14 2007",
  bibsource =    "http://etna.mcs.kent.edu/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://etna.mcs.kent.edu/vol.13.2002/pp38-55.dir/pp38-55.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronic Transactions on Numerical Analysis",
  journal-URL =  "http://etna.mcs.kent.edu/",
}


bibtype: article
filename: fparith.bib
label: Stakhov:2002:BTP
author: Alexey Stakhov
title: Brousentsov's Ternary Principle, Bergman's Number System and Ternary Mirror-symmetrical Arithmetic
journal: j-COMP-J
volume: 45
number: 2
pages: 221--236
year: 2002
CODEN: CMPJA6
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Thu Apr 4 07:33:05 MST 2002
bibtimestamp: 2002.04.04 07:33:05 MST
fjournal: The Computer Journal
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
rawauthor: Alexey Stakhov
bibsource:
http://www3.oup.co.uk/computer_journal/hdb/Volume_45/Issue_02/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://www3.oup.co.uk/computer_journal/hdb/Volume_45/Issue_02/450221.sgm.abs.html; http://www3.oup.co.uk/computer_journal/hdb/Volume_45/Issue_02/pdf/450221.pdf

rawtitle:
{Brousentsov}'s Ternary Principle, {Bergman}'s Number System and Ternary Mirror-symmetrical Arithmetic

entry:
@Article{Stakhov:2002:BTP,
  author =       "Alexey Stakhov",
  title =        "{Brousentsov}'s Ternary Principle, {Bergman}'s Number
                 System and Ternary Mirror-symmetrical Arithmetic",
  journal =      j-COMP-J,
  volume =       "45",
  number =       "2",
  pages =        "221--236",
  month =        "????",
  year =         "2002",
  CODEN =        "CMPJA6",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Thu Apr 4 07:33:05 MST 2002",
  bibsource =    "http://www3.oup.co.uk/computer_journal/hdb/Volume_45/Issue_02/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www3.oup.co.uk/computer_journal/hdb/Volume_45/Issue_02/450221.sgm.abs.html;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_45/Issue_02/pdf/450221.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
}


bibtype: misc
filename: fparith.bib
label: Steele:2002:SMF
author: Guy L. Steele Jr.
title: System and method for floating-point computation
pages: 221--236
day: 12
month: mar
monthnumber: 3
year: 2002
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/6356927/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 6356927
rawauthor: Guy L. {Steele Jr.}
rawtitle: System and method for floating-point computation
abstract:
A system is disclosed for performing floating point computation in connection with numbers in a base floating point representation (such as the representation defined in IEEE Std. 754) that defines a plurality of formats, including a normalized format and a de-normalized format, using a common floating point representation that defines a unitary normalized format. The system includes a base to common representation converter, a processor and a common to base representation converter. The base to common representation converter converts numbers from the base floating point representation to the common floating point representation, so that all numbers involved in a computation will be expressed in the unitary normalized format. The processor is configured to perform a mathematical operation of at least one predetermined type in connection with the converted numbers generated by the base to common representation converter to generate a floating point result in the common representation. The common to base representation converter converts numbers from the common floating point representation selectively to either the normalized or de-normalized format of the base representation.

entry:
@Misc{Steele:2002:SMF,
  author =       "Guy L. {Steele Jr.}",
  title =        "System and method for floating-point computation",
  howpublished = "US Patent 6356927",
  day =          "12",
  month =        mar,
  year =         "2002",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/6356927/fulltext.html",
  abstract =     "A system is disclosed for performing floating point
                 computation in connection with numbers in a base
                 floating point representation (such as the
                 representation defined in IEEE Std. 754) that defines a
                 plurality of formats, including a normalized format and
                 a de-normalized format, using a common floating point
                 representation that defines a unitary normalized
                 format. The system includes a base to common
                 representation converter, a processor and a common to
                 base representation converter. The base to common
                 representation converter converts numbers from the base
                 floating point representation to the common floating
                 point representation, so that all numbers involved in a
                 computation will be expressed in the unitary normalized
                 format. The processor is configured to perform a
                 mathematical operation of at least one predetermined
                 type in connection with the converted numbers generated
                 by the base to common representation converter to
                 generate a floating point result in the common
                 representation. The common to base representation
                 converter converts numbers from the common floating
                 point representation selectively to either the
                 normalized or de-normalized format of the base
                 representation.",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Stehle:2002:WCL
author: Damien Stehle and Vincent Lefevre and Paul Zimmermann
title: Worst Cases and Lattice Reduction
type: Research Report
institution: inst-LORIA-INRIA-LORRAINE
address: inst-LORIA-INRIA-LORRAINE:adr
pages: 10
day: 15
month: oct
monthnumber: 10
year: 2002
bibdate: Sun Sep 10 08:24:59 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.09.10 08:24:59 ???
URL: http://www.loria.fr/~zimmerma/papers/wclr.ps.gz
acknowledgement: ack-nhfb
rawauthor: Damien Stehl{\'e} and Vincent Lef{\`e}vre and Paul Zimmermann
rawtitle: Worst Cases and Lattice Reduction
abstract:
We propose a new algorithm to find worst cases for correct rounding of an analytic function. We first reduce this problem to the em real small value problem --- i.e., for polynomials with real coefficients. Then we show that this second problem can be solved efficiently, by extending Coppersmith's work on the em integer small value problem --- for polynomials with integer coefficients --- using lattice reduction [4, 5, 6].par For floating-point numbers with a mantissa less than $N$, and a polynomial approximation of degree $d$, our algorithm finds all worst cases at distance $ < N^-d^2 / (2d + 1) $ from a machine number in time $ O(N^(d + 1) / (2d + 1) + epsilon ) $. For $ d = 2 $, this improves on the $ O(N^2 / 3 + epsilon ) $ complexity from Lefevre's algorithm [12, 13] to $ O(N^3 / 5 + epsilon ) $. We exhibit some new worst cases found using our algorithm, for double-extended and quadruple precision. For larger $d$, our algorithm can be used to check that there exist no worst cases at distance $ < N^-k $ in time $ O(N^1 / 2 + O(1 / k)) $.

keywords:
Coppersmith's theorem; correct rounding; Exact rounding; floating-point arithmetic; IEEE-754; lattice reduction; table maker's dilemma; worst case

rawabstract:
We propose a new algorithm to find worst cases for correct rounding of an analytic function. We first reduce this problem to the {\em real small value problem} --- i.e., for polynomials with real coefficients. Then we show that this second problem can be solved efficiently, by extending Coppersmith's work on the {\em integer small value problem} --- for polynomials with integer coefficients --- using lattice reduction [4, 5, 6].\par For floating-point numbers with a mantissa less than $N$, and a polynomial approximation of degree $d$, our algorithm finds all worst cases at distance $ < N^{-d^2 / (2d + 1)} $ from a machine number in time $ O(N^{(d + 1) / (2d + 1) + \epsilon }) $. For $ d = 2 $, this improves on the $ O(N^{2 / 3 + \epsilon }) $ complexity from Lef{\`e}vre's algorithm [12, 13] to $ O(N^{3 / 5 + \epsilon }) $. We exhibit some new worst cases found using our algorithm, for double-extended and quadruple precision. For larger $d$, our algorithm can be used to check that there exist no worst cases at distance $ < N^{-k} $ in time $ O(N^{1 / 2 + O(1 / k)}) $.

entry:
@TechReport{Stehle:2002:WCL,
  author =       "Damien Stehl{\'e} and Vincent Lef{\`e}vre and Paul
                 Zimmermann",
  title =        "Worst Cases and Lattice Reduction",
  type =         "Research Report",
  institution =  inst-LORIA-INRIA-LORRAINE,
  address =      inst-LORIA-INRIA-LORRAINE:adr,
  pages =        "10",
  day =          "15",
  month =        oct,
  year =         "2002",
  bibdate =      "Sun Sep 10 08:24:59 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.loria.fr/~zimmerma/papers/wclr.ps.gz",
  abstract =     "We propose a new algorithm to find worst cases for
                 correct rounding of an analytic function. We first
                 reduce this problem to the {\em real small value
                 problem} --- i.e., for polynomials with real
                 coefficients. Then we show that this second problem can
                 be solved efficiently, by extending Coppersmith's work
                 on the {\em integer small value problem} --- for
                 polynomials with integer coefficients --- using lattice
                 reduction [4, 5, 6].\par

                 For floating-point numbers with a mantissa less than
                 $N$, and a polynomial approximation of degree $d$, our
                 algorithm finds all worst cases at distance $ < N^{-d^2
                 / (2d + 1)} $ from a machine number in time $ O(N^{(d +
                 1) / (2d + 1) + \epsilon }) $. For $ d = 2 $, this
                 improves on the $ O(N^{2 / 3 + \epsilon }) $ complexity
                 from Lef{\`e}vre's algorithm [12, 13] to $ O(N^{3 / 5 +
                 \epsilon }) $. We exhibit some new worst cases found
                 using our algorithm, for double-extended and quadruple
                 precision. For larger $d$, our algorithm can be used to
                 check that there exist no worst cases at distance $ <
                 N^{-k} $ in time $ O(N^{1 / 2 + O(1 / k)}) $.",
  acknowledgement = ack-nhfb,
  keywords =     "Coppersmith's theorem; correct rounding; Exact
                 rounding; floating-point arithmetic; IEEE-754; lattice
                 reduction; table maker's dilemma; worst case",
}


bibtype: article
filename: fparith.bib
label: Stoianov:2002:AAB
author: Ivilin Stoianov and Marco Zorzi and Suzanna Becker and Carlo Umilta
title: Associative Arithmetic with Boltzmann Machines: The Role of Number Representations
journal: j-LECT-NOTES-COMP-SCI
volume: 2415
pages: 277--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:10:20 MDT 2002
bibtimestamp: 2002.09.10 19:10:20 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Ivilin Stoianov and Marco Zorzi and Suzanna Becker and Carlo Umilta
rawtitle: Associative Arithmetic with {Boltzmann} Machines: The Role of Number Representations
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2415.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2415/24150277.htm; http://link.springer-ny.com/link/service/series/0558/papers/2415/24150277.pdf

entry:
@Article{Stoianov:2002:AAB,
  author =       "Ivilin Stoianov and Marco Zorzi and Suzanna Becker and
                 Carlo Umilta",
  title =        "Associative Arithmetic with {Boltzmann} Machines: The
                 Role of Number Representations",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2415",
  pages =        "277--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:10:20 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2415.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2415/24150277.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2415/24150277.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: manual
filename: fparith.bib
label: Sun:2002:BJP
author: Sun Microsystems
title: BigDecimal (Java 2 Platform SE v1.4.0)
organization: Sun Microsystems
address: Mountain View, CA, USA
pages: 17
year: 2002
bibdate: Fri Nov 28 11:16:16 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 11:16:16 ???
URL: http://java.sun/com/products
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: {Sun Microsystems}
rawtitle: {BigDecimal (Java 2 Platform SE v1.4.0)}
abstract:
Immutable, arbitrary-precision signed decimal numbers. A BigDecimal consists of an arbitrary precision integer unscaled value and a non-negative 32-bit integer scale, which represents the number of digits to the right of the decimal point. The number represented by the BigDecimal is $ (mbox unscaledValue / 10^mbox scale) $. BigDecimal provides operations for basic arithmetic, scale manipulation, comparison, hashing, and format conversion.

rawabstract:
Immutable, arbitrary-precision signed decimal numbers. A BigDecimal consists of an arbitrary precision integer unscaled value and a non-negative 32-bit integer scale, which represents the number of digits to the right of the decimal point. The number represented by the BigDecimal is $ (\mbox {unscaledValue} / 10^{\mbox {scale}}) $. BigDecimal provides operations for basic arithmetic, scale manipulation, comparison, hashing, and format conversion.

entry:
@Manual{Sun:2002:BJP,
  author =       "{Sun Microsystems}",
  title =        "{BigDecimal (Java 2 Platform SE v1.4.0)}",
  organization = "Sun Microsystems",
  address =      "Mountain View, CA, USA",
  pages =        "17",
  year =         "2002",
  bibdate =      "Fri Nov 28 11:16:16 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://java.sun/com/products",
  abstract =     "Immutable, arbitrary-precision signed decimal numbers.
                 A BigDecimal consists of an arbitrary precision integer
                 unscaled value and a non-negative 32-bit integer scale,
                 which represents the number of digits to the right of
                 the decimal point. The number represented by the
                 BigDecimal is $ (\mbox {unscaledValue} / 10^{\mbox
                 {scale}}) $. BigDecimal provides operations for basic
                 arithmetic, scale manipulation, comparison, hashing,
                 and format conversion.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: manual
filename: fparith.bib
label: TI:2002:TFL
title: TMS320C67x FastRTS Library Programmer's Reference (SPRU100A)
organization: Texas Instruments
address: Dallas, TX, USA
pages: 17
month: oct
monthnumber: 10
year: 2002
bibdate: Sat Jan 15 06:11:57 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.01.15 06:11:57 ???
URL: http://focus.ti.com/lit/ug/spru100a/spru100a.pdf
acknowledgement: ack-nhfb
rawtitle: {TMS320C67x FastRTS} Library Programmer's Reference ({SPRU100A})
note:
The FastRTS library is a collection of 26 optimized floating-point math functions for the TMS320C67x device. This source code library includes C-callable (ANSI-C-language compatible) optimized versions of the floating-point math functions included in previous run-time-support libraries.

rawnote:
The FastRTS library is a collection of 26 optimized floating-point math functions for the TMS320C67x device. This source code library includes C-callable (ANSI-C-language compatible) optimized versions of the floating-point math functions included in previous run-time-support libraries.

entry:
@Manual{TI:2002:TFL,
  title =        "{TMS320C67x FastRTS} Library Programmer's Reference
                 ({SPRU100A})",
  organization = "Texas Instruments",
  address =      "Dallas, TX, USA",
  month =        oct,
  year =         "2002",
  bibdate =      "Sat Jan 15 06:11:57 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "The FastRTS library is a collection of 26 optimized
                 floating-point math functions for the TMS320C67x
                 device. This source code library includes C-callable
                 (ANSI-C-language compatible) optimized versions of the
                 floating-point math functions included in previous
                 run-time-support libraries.",
  URL =          "http://focus.ti.com/lit/ug/spru100a/spru100a.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Tornaria:2002:SRM
author: Gonzalo Tornaria
title: Square Roots Modulo $p$
journal: j-LECT-NOTES-COMP-SCI
volume: 2286
pages: 430--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:09:12 MDT 2002
bibtimestamp: 2002.09.10 19:09:12 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Gonzalo Tornar{\'\i}a
rawtitle: Square Roots Modulo $p$
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2286.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2286/22860430.htm; http://link.springer-ny.com/link/service/series/0558/papers/2286/22860430.pdf

entry:
@Article{Tornaria:2002:SRM,
  author =       "Gonzalo Tornar{\'\i}a",
  title =        "Square Roots Modulo $p$",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2286",
  pages =        "430--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:09:12 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2286.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2286/22860430.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2286/22860430.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Turner:2002:RPS
author: Peter R. Turner
title: Residue polynomial systems
journal: j-THEOR-COMP-SCI
volume: 279
number: 1-2
pages: 29--49
month: may
monthnumber: 5
year: 2002
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Wed Nov 20 18:08:56 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.20 18:08:56 MST
fjournal: Theoretical Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: Peter R. Turner
rawtitle: Residue polynomial systems
entry:
@Article{Turner:2002:RPS,
  author =       "Peter R. Turner",
  title =        "Residue polynomial systems",
  journal =      j-THEOR-COMP-SCI,
  volume =       "279",
  number =       "1-2",
  pages =        "29--49",
  month =        may,
  year =         "2002",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Wed Nov 20 18:08:56 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
}


bibtype: article
filename: fparith.bib
label: vanEmden:2002:NDI
author: M. H. van Emden
title: New Developments in Interval Arithmetic and Their Implications for Floating-Point Standardization
journal: arXiv.org
pages: 1--12
day: 16
month: oct
monthnumber: 10
year: 2002
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/cs/0210015
subject: Numerical Analysis (cs.NA)
acknowledgement: ack-nhfb
rawauthor: M. H. van Emden
rawtitle: New Developments in Interval Arithmetic and Their Implications for Floating-Point Standardization
abstract:
We consider the prospect of a processor that can perform interval arithmetic at the same speed as conventional floating-point arithmetic. This makes it possible for all arithmetic to be performed with the superior security of interval methods without any penalty in speed. In such a situation the IEEE floating-point standard needs to be compared with a version of floating-point arithmetic that is ideal for the purpose of interval arithmetic. Such a comparison requires a succinct and complete exposition of interval arithmetic according to its recent developments. We present such an exposition in this paper. We conclude that the directed roundings toward the infinities and the definition of division by the signed zeros are valuable features of the standard. Because the operations of interval arithmetic are always defined, exceptions do not arise. As a result neither Nans nor exceptions are needed. Of the status flags, only the inexact flag may be useful. Denormalized numbers seem to have no use for interval arithmetic; in the use of interval constraints, they are a handicap.

rawabstract:
We consider the prospect of a processor that can perform interval arithmetic at the same speed as conventional floating-point arithmetic. This makes it possible for all arithmetic to be performed with the superior security of interval methods without any penalty in speed. In such a situation the IEEE floating-point standard needs to be compared with a version of floating-point arithmetic that is ideal for the purpose of interval arithmetic. Such a comparison requires a succinct and complete exposition of interval arithmetic according to its recent developments. We present such an exposition in this paper. We conclude that the directed roundings toward the infinities and the definition of division by the signed zeros are valuable features of the standard. Because the operations of interval arithmetic are always defined, exceptions do not arise. As a result neither Nans nor exceptions are needed. Of the status flags, only the inexact flag may be useful. Denormalized numbers seem to have no use for interval arithmetic; in the use of interval constraints, they are a handicap.

entry:
@Article{vanEmden:2002:NDI,
  author =       "M. H. van Emden",
  title =        "New Developments in Interval Arithmetic and Their
                 Implications for Floating-Point Standardization",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--12",
  day =          "16",
  month =        oct,
  year =         "2002",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/cs/0210015",
  abstract =     "We consider the prospect of a processor that can
                 perform interval arithmetic at the same speed as
                 conventional floating-point arithmetic. This makes it
                 possible for all arithmetic to be performed with the
                 superior security of interval methods without any
                 penalty in speed. In such a situation the IEEE
                 floating-point standard needs to be compared with a
                 version of floating-point arithmetic that is ideal for
                 the purpose of interval arithmetic. Such a comparison
                 requires a succinct and complete exposition of interval
                 arithmetic according to its recent developments. We
                 present such an exposition in this paper. We conclude
                 that the directed roundings toward the infinities and
                 the definition of division by the signed zeros are
                 valuable features of the standard. Because the
                 operations of interval arithmetic are always defined,
                 exceptions do not arise. As a result neither Nans nor
                 exceptions are needed. Of the status flags, only the
                 inexact flag may be useful. Denormalized numbers seem
                 to have no use for interval arithmetic; in the use of
                 interval constraints, they are a handicap.",
  acknowledgement = ack-nhfb,
  subject =      "Numerical Analysis (cs.NA)",
}


bibtype: inproceedings
filename: fparith.bib
label: Walters:2002:DTU
author: E. G. Walters and M. J. Schulte
title: Design Tradeoffs Using Truncated Multipliers in FIR Filter Implementations
crossref: Luk:2002:PSA
pages: 357--368
year: 2002
bibdate: Sun Mar 04 17:47:29 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.03.04 17:47:29 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2002-03.pdf
acknowledgement: ack-nhfb
rawauthor: E. G. Walters and M. J. Schulte
rawtitle: Design Tradeoffs Using Truncated Multipliers in {FIR} Filter Implementations
entry:
@InProceedings{Walters:2002:DTU,
  author =       "E. G. Walters and M. J. Schulte",
  title =        "Design Tradeoffs Using Truncated Multipliers in {FIR}
                 Filter Implementations",
  crossref =     "Luk:2002:PSA",
  pages =        "357--368",
  year =         "2002",
  bibdate =      "Sun Mar 04 17:47:29 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2002-03.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Winkler:2002:SVU
author: Jurgen F. H. Winkler
title: A safe variant of the unsafe integer arithmetic of Java$^TM$
journal: j-SPE
volume: 32
number: 7
pages: 669--701
month: jun
monthnumber: 6
year: 2002
CODEN: SPEXBL
DOI: https://doi.org/10.1002/spe.454
ISSN: 0038-0644 (print), 1097-024X (electronic) OR 00380644 (print), 1097024X (electronic)
ISSNL: 0038-0644 OR 00380644
bibdate: Wed Oct 16 18:25:58 MDT 2002
bibtimestamp: 2002.10.16 18:25:58 MDT
fjournal: Software---Practice and Experience
acknowledgement: ack-nhfb
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X
rawauthor: J{\"u}rgen F. H. Winkler
rawtitle: A safe variant of the unsafe integer arithmetic of {Java$^{TM}$}
bibsource:
http://www.interscience.wiley.com/jpages/0038-0644; http://www3.interscience.wiley.com/journalfinder.html; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://www3.interscience.wiley.com/cgi-bin/abstract/94515736/START; http://www3.interscience.wiley.com/cgi-bin/fulltext?ID=94515736&PLACEBO=IE.pdf

keywords:
arithmetics in programming languages; divide-by-zero; floating-point arithmetic; IEEE 754; Java; overflow; program structure; range limitation; rounding; safe arithmetic operations; underflow; zero-divide

entry:
@Article{Winkler:2002:SVU,
  author =       "J{\"u}rgen F. H. Winkler",
  title =        "A safe variant of the unsafe integer arithmetic of
                 {Java$^{TM}$}",
  journal =      j-SPE,
  volume =       "32",
  number =       "7",
  pages =        "669--701",
  month =        jun,
  year =         "2002",
  CODEN =        "SPEXBL",
  DOI =          "https://doi.org/10.1002/spe.454",
  ISSN =         "0038-0644 (print), 1097-024X (electronic)",
  ISSN-L =       "0038-0644",
  bibdate =      "Wed Oct 16 18:25:58 MDT 2002",
  bibsource =    "http://www.interscience.wiley.com/jpages/0038-0644;
                 http://www3.interscience.wiley.com/journalfinder.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www3.interscience.wiley.com/cgi-bin/abstract/94515736/START;
                 http://www3.interscience.wiley.com/cgi-bin/fulltext?ID=94515736&PLACEBO=IE.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Software---Practice and Experience",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X",
  keywords =     "arithmetics in programming languages; divide-by-zero;
                 floating-point arithmetic; IEEE 754; Java; overflow;
                 program structure; range limitation; rounding; safe
                 arithmetic operations; underflow; zero-divide",
}


bibtype: article
filename: fparith.bib
label: Wu:2002:BPF
author: Huapeng Wu
title: Bit-parallel finite field multiplier and squarer using polynomial basis
journal: j-IEEE-TRANS-COMPUT
volume: 51
number: 7
pages: 750--758
month: jul
monthnumber: 7
year: 2002
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2002.1017695
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 09:41:54 MDT 2011
bibtimestamp: 2011.07.05 09:41:54 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1017695
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Huapeng Wu
rawtitle: Bit-parallel finite field multiplier and squarer using polynomial basis
entry:
@Article{Wu:2002:BPF,
  author =       "Huapeng Wu",
  title =        "Bit-parallel finite field multiplier and squarer using
                 polynomial basis",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "51",
  number =       "7",
  pages =        "750--758",
  month =        jul,
  year =         "2002",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2002.1017695",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 09:41:54 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1017695",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Wu:2002:FFM
author: Huapeng Wu and M. A. Hasan and I. F. Blake and Shuhong Gao
title: Finite field multiplier using redundant representation
journal: j-IEEE-TRANS-COMPUT
volume: 51
number: 11
pages: 1306--1316
month: nov
monthnumber: 11
year: 2002
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2002.1047755
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 09:42:00 MDT 2011
bibtimestamp: 2011.07.05 09:42:00 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1047755
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Huapeng Wu and M. A. Hasan and I. F. Blake and Shuhong Gao
rawtitle: Finite field multiplier using redundant representation
entry:
@Article{Wu:2002:FFM,
  author =       "Huapeng Wu and M. A. Hasan and I. F. Blake and Shuhong
                 Gao",
  title =        "Finite field multiplier using redundant
                 representation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "51",
  number =       "11",
  pages =        "1306--1316",
  month =        nov,
  year =         "2002",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2002.1047755",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 09:42:00 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1047755",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Wu:2002:MMS
author: Huapeng Wu
title: Montgomery multiplier and squarer for a class of finite fields
journal: j-IEEE-TRANS-COMPUT
volume: 51
number: 5
pages: 521--529
month: may
monthnumber: 5
year: 2002
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2002.1004591
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 09:41:51 MDT 2011
bibtimestamp: 2011.07.05 09:41:51 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1004591
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Huapeng Wu
rawtitle: {Montgomery} multiplier and squarer for a class of finite fields
entry:
@Article{Wu:2002:MMS,
  author =       "Huapeng Wu",
  title =        "{Montgomery} multiplier and squarer for a class of
                 finite fields",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "51",
  number =       "5",
  pages =        "521--529",
  month =        may,
  year =         "2002",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2002.1004591",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 09:41:51 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1004591",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Yang:2002:RNSa
author: Lie-Liang Yang and L. Hanzo
journal: j-IEEE-TRANS-VEH-TECHNOL
volume: 51
number: 6
pages: 1547--1559
month: nov
monthnumber: 11
year: 2002
CODEN: ITUTAB
DOI: https://doi.org/10.1109/TVT.2002.804849
ISSN: 0018-9545 (print), 1939-9359 (electronic) OR 00189545 (print), 19399359 (electronic)
ISSNL: 0018-9545 OR 00189545
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=26382
fjournal: IEEE Transactions on Vehicular Technology
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=25
rawauthor: Lie-Liang Yang and L. Hanzo
title:
A residue number system based parallel communication scheme using orthogonal signaling. II. Multipath fading channels

rawtitle:
A residue number system based parallel communication scheme using orthogonal signaling. {II}. {Multipath} fading channels

entry:
@Article{Yang:2002:RNSa,
  author =       "Lie-Liang Yang and L. Hanzo",
  title =        "A residue number system based parallel communication
                 scheme using orthogonal signaling. {II}. {Multipath}
                 fading channels",
  journal =      j-IEEE-TRANS-VEH-TECHNOL,
  volume =       "51",
  number =       "6",
  pages =        "1547--1559",
  month =        nov,
  year =         "2002",
  CODEN =        "ITUTAB",
  DOI =          "https://doi.org/10.1109/TVT.2002.804849",
  ISSN =         "0018-9545 (print), 1939-9359 (electronic)",
  ISSN-L =       "0018-9545",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=26382",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Vehicular Technology",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=25",
  keywords =     "residue arithmetic; residue number system",
  summary =      "For pt.I see ibid., vol.51, no.6, p.1534-46 (2002). A
                 novel signaling scheme is presented, where a set of
                 orthogonal signals is transmitted in parallel. The
                 signals are selected according to the so-called residue
                 number system (RNS). Hence the \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Yang:2002:RNSb
author: Lie-Liang Yang and L. Hanzo
journal: j-IEEE-TRANS-VEH-TECHNOL
volume: 51
number: 6
pages: 1534--1546
month: nov
monthnumber: 11
year: 2002
CODEN: ITUTAB
DOI: https://doi.org/10.1109/TVT.2002.804850
ISSN: 0018-9545 (print), 1939-9359 (electronic) OR 00189545 (print), 19399359 (electronic)
ISSNL: 0018-9545 OR 00189545
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=26382
fjournal: IEEE Transactions on Vehicular Technology
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=25
rawauthor: Lie-Liang Yang and L. Hanzo
title:
A residue number system based parallel communication scheme using orthogonal signaling. I. System outline

rawtitle:
A residue number system based parallel communication scheme using orthogonal signaling. {I}. {System} outline

entry:
@Article{Yang:2002:RNSb,
  author =       "Lie-Liang Yang and L. Hanzo",
  title =        "A residue number system based parallel communication
                 scheme using orthogonal signaling. {I}. {System}
                 outline",
  journal =      j-IEEE-TRANS-VEH-TECHNOL,
  volume =       "51",
  number =       "6",
  pages =        "1534--1546",
  month =        nov,
  year =         "2002",
  CODEN =        "ITUTAB",
  DOI =          "https://doi.org/10.1109/TVT.2002.804850",
  ISSN =         "0018-9545 (print), 1939-9359 (electronic)",
  ISSN-L =       "0018-9545",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=26382",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Vehicular Technology",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=25",
  keywords =     "residue arithmetic; residue number system",
  summary =      "A novel signaling scheme is presented, where a set of
                 orthogonal signals is transmitted in parallel. The
                 signals are selected according to the so-called residue
                 number system (RNS). Hence the system is essentially a
                 multiple code parallel \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Yang:2002:RNSc
author: Lie-Liang Yang and L. Hanzo
journal: j-IEEE-J-SEL-AREAS-COMMUN
volume: 20
number: 9
pages: 1652--1663
month: dec
monthnumber: 12
year: 2002
CODEN: ISACEM
DOI: https://doi.org/10.1109/JSAC.2002.805059
ISSN: 0733-8716 (print), 1558-0008 (electronic) OR 07338716 (print), 15580008 (electronic)
ISSNL: 0733-8716 OR 07338716
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=24076
fjournal: IEEE Journal on Selected Areas in Communications
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: Lie-Liang Yang and L. Hanzo
title:
Residue number system assisted fast frequency-hopped synchronous ultra-wideband spread-spectrum multiple-access: a design alternative to impulse radio

rawtitle:
Residue number system assisted fast frequency-hopped synchronous ultra-wideband spread-spectrum multiple-access: a design alternative to impulse radio

entry:
@Article{Yang:2002:RNSc,
  author =       "Lie-Liang Yang and L. Hanzo",
  title =        "Residue number system assisted fast frequency-hopped
                 synchronous ultra-wideband spread-spectrum
                 multiple-access: a design alternative to impulse
                 radio",
  journal =      j-IEEE-J-SEL-AREAS-COMMUN,
  volume =       "20",
  number =       "9",
  pages =        "1652--1663",
  month =        dec,
  year =         "2002",
  CODEN =        "ISACEM",
  DOI =          "https://doi.org/10.1109/JSAC.2002.805059",
  ISSN =         "0733-8716 (print), 1558-0008 (electronic)",
  ISSN-L =       "0733-8716",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=24076",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal on Selected Areas in Communications",
  keywords =     "residue arithmetic; residue number system",
  summary =      "Ultra-wideband (UWB) systems having a bandwidth on the
                 order of gigahertz have received wide attention both in
                 the US and in Europe. The family of UWB systems may
                 communicate either, by generating ultra-wideband
                 signals or with the aid of \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Yen:2002:RSR
author: Sung-Ming Yen and Seungjoo Kim and Seongan Lim and Sangjae Moon
title: RSA Speedup with Residue Number System Immune against Hardware Fault Cryptanalysis
journal: j-LECT-NOTES-COMP-SCI
volume: 2288
pages: 397--??
year: 2002
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Sep 10 19:09:14 MDT 2002
bibtimestamp: 2002.09.10 19:09:14 MDT
fjournal: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Sung-Ming Yen and Seungjoo Kim and Seongan Lim and Sangjae Moon
rawtitle: {RSA} Speedup with Residue Number System Immune against Hardware Fault Cryptanalysis
bibsource:
http://link.springer-ny.com/link/service/series/0558/tocs/t2288.htm; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://link.springer-ny.com/link/service/series/0558/bibs/2288/22880397.htm; http://link.springer-ny.com/link/service/series/0558/papers/2288/22880397.pdf

entry:
@Article{Yen:2002:RSR,
  author =       "Sung-Ming Yen and Seungjoo Kim and Seongan Lim and
                 Sangjae Moon",
  title =        "{RSA} Speedup with Residue Number System Immune
                 against Hardware Fault Cryptanalysis",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2288",
  pages =        "397--??",
  year =         "2002",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Sep 10 19:09:14 MDT 2002",
  bibsource =    "http://link.springer-ny.com/link/service/series/0558/tocs/t2288.htm;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer-ny.com/link/service/series/0558/bibs/2288/22880397.htm;
                 http://link.springer-ny.com/link/service/series/0558/papers/2288/22880397.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
}


bibtype: article
filename: fparith.bib
label: Ziv:2002:SGM
author: Abraham Ziv and Laurent Fournier
title: Solving the generalized mask constraint for test generation of binary floating point add operation
journal: j-THEOR-COMP-SCI
volume: 291
number: 2
pages: 183--201
month: nov
monthnumber: 11
year: 2002
CODEN: TCSCDI
ISSN: 0304-3975 (print), 1879-2294 (electronic) OR 03043975 (print), 18792294 (electronic)
ISSNL: 0304-3975 OR 03043975
bibdate: Wed Nov 20 18:15:29 MST 2002
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2002.11.20 18:15:29 MST
fjournal: Theoretical Computer Science
keywords: floating-point testing
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03043975
rawauthor: Abraham Ziv and Laurent Fournier
rawtitle: Solving the generalized mask constraint for test generation of binary floating point add operation
entry:
@Article{Ziv:2002:SGM,
  author =       "Abraham Ziv and Laurent Fournier",
  title =        "Solving the generalized mask constraint for test
                 generation of binary floating point add operation",
  journal =      j-THEOR-COMP-SCI,
  volume =       "291",
  number =       "2",
  pages =        "183--201",
  month =        nov,
  year =         "2002",
  CODEN =        "TCSCDI",
  ISSN =         "0304-3975 (print), 1879-2294 (electronic)",
  ISSN-L =       "0304-3975",
  bibdate =      "Wed Nov 20 18:15:29 MST 2002",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Computer Science",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03043975",
  keywords =     "floating-point testing",
}


bibtype: article
filename: fparith.bib
label: Abed:2003:VIL
author: K. H. Abed and R. E. Siferd
title: VLSI implementation of a low-power antilogarithmic converter
journal: j-IEEE-TRANS-COMPUT
volume: 52
number: 9
pages: 1221--1228
month: sep
monthnumber: 9
year: 2003
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2003.1228517
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 08:52:55 MDT 2011
bibtimestamp: 2011.07.05 08:52:55 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1228517
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: K. H. Abed and R. E. Siferd
rawtitle: {VLSI} implementation of a low-power antilogarithmic converter
entry:
@Article{Abed:2003:VIL,
  author =       "K. H. Abed and R. E. Siferd",
  title =        "{VLSI} implementation of a low-power antilogarithmic
                 converter",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "52",
  number =       "9",
  pages =        "1221--1228",
  month =        sep,
  year =         "2003",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2003.1228517",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 08:52:55 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1228517",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Agou:2003:SPR
author: Simon Joseph Agou and Marc Deleglise and Jean-Louis Nicolas
title: Short Polynomial Representations for Square Roots Modulo $p$
journal: j-DESIGNS-CODES-CRYPTOGR
volume: 28
number: 1
pages: 33--44
month: jan
monthnumber: 1
year: 2003
CODEN: DCCREC
ISSN: 0925-1022 (print), 1573-7586 (electronic) OR 09251022 (print), 15737586 (electronic)
ISSNL: 0925-1022 OR 09251022
bibdate: Thu Dec 11 06:27:20 MST 2003
bibsource: http://www.wkap.nl/jrnltoc.htm/0925-1022; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.11 06:27:20 MST
fjournal: Designs, codes, and cryptography
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10623
rawauthor: Simon Joseph Agou and Marc Del{\'e}glise and Jean-Louis Nicolas
rawtitle: Short Polynomial Representations for Square Roots Modulo $p$
URL:
http://ipsapp007.kluweronline.com/content/getfile/4630/45/2/abstract.htm; http://ipsapp007.kluweronline.com/content/getfile/4630/45/2/fulltext.pdf

entry:
@Article{Agou:2003:SPR,
  author =       "Simon Joseph Agou and Marc Del{\'e}glise and
                 Jean-Louis Nicolas",
  title =        "Short Polynomial Representations for Square Roots
                 Modulo $p$",
  journal =      j-DESIGNS-CODES-CRYPTOGR,
  volume =       "28",
  number =       "1",
  pages =        "33--44",
  month =        jan,
  year =         "2003",
  CODEN =        "DCCREC",
  ISSN =         "0925-1022 (print), 1573-7586 (electronic)",
  ISSN-L =       "0925-1022",
  bibdate =      "Thu Dec 11 06:27:20 MST 2003",
  bibsource =    "http://www.wkap.nl/jrnltoc.htm/0925-1022;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ipsapp007.kluweronline.com/content/getfile/4630/45/2/abstract.htm;
                 http://ipsapp007.kluweronline.com/content/getfile/4630/45/2/fulltext.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Designs, codes, and cryptography",
  journal-URL =  "http://link.springer.com/journal/10623",
}


bibtype: inproceedings
filename: fparith.bib
label: Aharoni:2003:FTG
author: Merav Aharoni and Sigal Asaf and Laurent Fournier and Anatoly Koifman and Raviv Nagel
title: FPgen --- a Test Generation Framework for Datapath Floating-Point Verification
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 17--22
month: nov
monthnumber: 11
year: 2003
DOI: https://doi.org/10.1109/HLDVT.2003.1252469
ISBN: 0-7803-8236-6 OR 0780382366
ISBN13: 978-0-7803-8236-7 OR 9780780382367
LCCN: QA76.76.V47 I35 2003; TK7895.M5 I34 2003
bibdate: Tue Jun 22 06:49:59 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.06.22 06:49:59 ???
keywords: floating-point testing
acknowledgement: ack-nhfb
bookpages: viii + 178
rawauthor: Merav Aharoni and Sigal Asaf and Laurent Fournier and Anatoly Koifman and Raviv Nagel
rawtitle: {FPgen} --- a Test Generation Framework for Datapath Floating-Point Verification
booktitle:
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop, 12--14 November, 2003 (HLDVT03)

URL:
http://ieeexplore.ieee.org/servlet/opac?punumber=8873; http://www.haifa.ibm.com/projects/verification/fpgen; https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1252469; https://www.research.ibm.com/haifa/projects/verification/fpgen/ieeets.html

abstract:
FPgen is a new test generation framework targeted toward the verification of the floating point (FP) datapath, through the generation of test cases. This framework provides the capacity to define virtually any architectural FP coverage model, consisting of verification tasks. The tool supplies strong constraint solving capabilities, allowing the generation of random tests that target these tasks. We present an overview of FPgen's functionality, describe the results of its use for the verification of several FP units, and compare its efficiency with existing test generators.

rawabstract:
FPgen is a new test generation framework targeted toward the verification of the floating point (FP) datapath, through the generation of test cases. This framework provides the capacity to define virtually any architectural FP coverage model, consisting of verification tasks. The tool supplies strong constraint solving capabilities, allowing the generation of random tests that target these tasks. We present an overview of FPgen's functionality, describe the results of its use for the verification of several FP units, and compare its efficiency with existing test generators.

rawbooktitle:
{Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop, 12--14 November, 2003 (HLDVT03)}

entry:
@InProceedings{Aharoni:2003:FTG,
  author =       "Merav Aharoni and Sigal Asaf and Laurent Fournier and
                 Anatoly Koifman and Raviv Nagel",
  booktitle =    "{Proceedings of the Eighth IEEE International
                 High-Level Design Validation and Test Workshop, 12--14
                 November, 2003 (HLDVT03)}",
  title =        "{FPgen} --- a Test Generation Framework for Datapath
                 Floating-Point Verification",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  bookpages =    "viii + 178",
  pages =        "17--22",
  month =        nov,
  year =         "2003",
  DOI =          "https://doi.org/10.1109/HLDVT.2003.1252469",
  ISBN =         "0-7803-8236-6",
  ISBN-13 =      "978-0-7803-8236-7",
  LCCN =         "QA76.76.V47 I35 2003; TK7895.M5 I34 2003",
  bibdate =      "Tue Jun 22 06:49:59 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/servlet/opac?punumber=8873;
                 http://www.haifa.ibm.com/projects/verification/fpgen;
                 https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1252469;
                 https://www.research.ibm.com/haifa/projects/verification/fpgen/ieeets.html",
  abstract =     "FPgen is a new test generation framework targeted
                 toward the verification of the floating point (FP)
                 datapath, through the generation of test cases. This
                 framework provides the capacity to define virtually any
                 architectural FP coverage model, consisting of
                 verification tasks. The tool supplies strong constraint
                 solving capabilities, allowing the generation of random
                 tests that target these tasks. We present an overview
                 of FPgen's functionality, describe the results of its
                 use for the verification of several FP units, and
                 compare its efficiency with existing test generators.",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point testing",
}


bibtype: inproceedings
filename: fparith.bib
label: Akkas:2003:QPD
author: A. Akkas and M. J. Schulte
title: A Quadruple Precision and Dual Double Precision Floating-Point Multiplier
pages: 76--81
year: 2003
bibdate: Fri Jun 11 05:37:57 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.06.11 05:37:57 ???
acknowledgement: ack-nhfb
rawauthor: A. Akkas and M. J. Schulte
rawtitle: A Quadruple Precision and Dual Double Precision Floating-Point Multiplier
booktitle:
Proceedings of the 2003 Euromicro Symposium on Digital System Design, Antalya, Turkey, September 2003

URL:
http://home.ku.edu.tr/~ahakkas/publications/quadruple_multiplier.pdf; http://mesa.ece.wisc.edu/publications/cp_2003-07.pdf

rawbooktitle:
Proceedings of the 2003 Euromicro Symposium on Digital System Design, Antalya, Turkey, September 2003

entry:
@InProceedings{Akkas:2003:QPD,
  author =       "A. Akkas and M. J. Schulte",
  booktitle =    "Proceedings of the 2003 Euromicro Symposium on Digital
                 System Design, Antalya, Turkey, September 2003",
  title =        "A Quadruple Precision and Dual Double Precision
                 Floating-Point Multiplier",
  publisher =    "????",
  address =      "????",
  pages =        "76--81",
  year =         "2003",
  bibdate =      "Fri Jun 11 05:37:57 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://home.ku.edu.tr/~ahakkas/publications/quadruple_multiplier.pdf;
                 http://mesa.ece.wisc.edu/publications/cp_2003-07.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Al-Radadi:2003:RSD
author: E. Al-Radadi and P. Siy
title: RNS: sign detector based on Chinese Remainder Theorem II (CRT II)
journal: j-COMPUT-MATH-APPL
volume: 46
number: 10--11
pages: 1559--1570
month: nov
monthnumber: 11
year: 2003
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 21:49:30 MST 2017
bibtimestamp: 2017.03.01 21:49:30 MST
URL: http://www.sciencedirect.com/science/article/pii/S089812210390191X
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: E. Al-Radadi and P. Siy
rawtitle: {RNS}: sign detector based on {Chinese Remainder Theorem II} {(CRT II)}
entry:
@Article{Al-Radadi:2003:RSD,
  author =       "E. Al-Radadi and P. Siy",
  title =        "{RNS}: sign detector based on {Chinese Remainder
                 Theorem II} {(CRT II)}",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "46",
  number =       "10--11",
  pages =        "1559--1570",
  month =        nov # "\slash " # dec,
  year =         "2003",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 21:49:30 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S089812210390191X",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: article
filename: fparith.bib
label: Altman:2003:RAN
author: Micah Altman and Michael P. McDonald
title: Replication with Attention to Numerical Accuracy
journal: j-POLIT-ANAL
volume: 11
number: 3
pages: 302--307
month: Summer
year: 2003
DOI: https://doi.org/10.1093/pan/mpg016
ISSN: 1047-1987 (print), 1476-4989 (electronic) OR 10471987 (print), 14764989 (electronic)
ISSNL: 1047-1987 OR 10471987
bibdate: Sat Feb 8 10:28:55 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 10:28:55 ???
fjournal: Political Analysis
acknowledgement: ack-nhfb
journalURL: https://www.cambridge.org/core/journals/political-analysis/all-issues
rawauthor: Micah Altman and Michael P. McDonald
rawtitle: Replication with Attention to Numerical Accuracy
remark:
The authors attempt to replicate numerically two papers in the booktitle American Journal of Political Science, and find that the results in those papers are dependent on the statistical package used. Their abstract concludes: ``In the course of our replications, we uncover other pitfalls that may prevent accurate replication, and make recommendations to ensure the ability for future researchers to replicate results.''

entry:
@Article{Altman:2003:RAN,
  author =       "Micah Altman and Michael P. McDonald",
  title =        "Replication with Attention to Numerical Accuracy",
  journal =      j-POLIT-ANAL,
  volume =       "11",
  number =       "3",
  pages =        "302--307",
  month =        "Summer",
  year =         "2003",
  DOI =          "https://doi.org/10.1093/pan/mpg016",
  ISSN =         "1047-1987 (print), 1476-4989 (electronic)",
  ISSN-L =       "1047-1987",
  bibdate =      "Sat Feb 8 10:28:55 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Political Analysis",
  journal-URL =  "https://www.cambridge.org/core/journals/political-analysis/all-issues",
  remark =       "The authors attempt to replicate numerically two
                 papers in the \booktitle{American Journal of Political
                 Science}, and find that the results in those papers are
                 dependent on the statistical package used. Their
                 abstract concludes: ``In the course of our
                 replications, we uncover other pitfalls that may
                 prevent accurate replication, and make recommendations
                 to ensure the ability for future researchers to
                 replicate results.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Ammar:2003:NDH
author: A. Ammar and A. S. S. El-Kabbany and M. I. Youssef and A. Emam
booktitle: NRSC 2003, Proceedings of the Twentieth National Radio Science Conference, 18--20 March 2003
title: A novel data hiding technique using residue number system
publisher: pub-IEEE
address: pub-IEEE:adr
pages: C15--1--12
year: 2003
DOI: https://doi.org/10.1109/NRSC.2003.1217348
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: A. Ammar and A. S. S. El-Kabbany and M. I. Youssef and A. Emam
rawbooktitle: {NRSC 2003}, Proceedings of the Twentieth National Radio Science Conference, 18--20 March 2003
rawtitle: A novel data hiding technique using residue number system
entry:
@InProceedings{Ammar:2003:NDH,
  author =       "A. Ammar and A. S. S. El-Kabbany and M. I. Youssef and
                 A. Emam",
  booktitle =    "{NRSC 2003}, Proceedings of the Twentieth National
                 Radio Science Conference, 18--20 March 2003",
  title =        "A novel data hiding technique using residue number
                 system",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "C15--1--12",
  year =         "2003",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/NRSC.2003.1217348",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "Data hiding technique is a very attractive field. The
                 field of data hiding in imagery is relatively very
                 young and is growing at an exponential rate. This field
                 is highly multidisciplinary field that combines image
                 and signal processing with \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2003:AI
author: Anonymous
title: Author index
crossref: Bajard:2003:ISC
pages: 281--281
year: 2003
bibdate: Fri Nov 28 11:06:15 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 11:06:15 ???
keywords: ARITH-16
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: Author index
entry:
@InProceedings{Anonymous:2003:AI,
  author =       "Anonymous",
  title =        "Author index",
  crossref =     "Bajard:2003:ISC",
  pages =        "281--281",
  year =         "2003",
  bibdate =      "Fri Nov 28 11:06:15 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-16",
}


bibtype: techreport
filename: fparith.bib
label: Anonymous:2003:FFP
author: Anonymous
title: Fast Floating-Point Arithmetic Emulation on the Blackfin Processor Platform
type: Engineer To Engineer Note
number: EE-185
institution: Analog Devices
pages: 281--281
day: 26
month: may
monthnumber: 5
year: 2003
bibdate: Fri May 20 12:26:05 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.05.20 12:26:05 ???
URL: http://www.analog.com/UploadedFiles/Application_Notes/47485184002118EE185.pdf
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: Fast Floating-Point Arithmetic Emulation on the {Blackfin} Processor Platform
remark:
Describes a software implementation of IEEE 754 32-bit and 64-bit arithmetic for the Blackfin fixed-point embedded processor.

entry:
@TechReport{Anonymous:2003:FFP,
  author =       "Anonymous",
  title =        "Fast Floating-Point Arithmetic Emulation on the
                 {Blackfin} Processor Platform",
  type =         "Engineer To Engineer Note",
  number =       "EE-185",
  institution =  "Analog Devices",
  address =      "????",
  day =          "26",
  month =        may,
  year =         "2003",
  bibdate =      "Fri May 20 12:26:05 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.analog.com/UploadedFiles/Application_Notes/47485184002118EE185.pdf",
  acknowledgement = ack-nhfb,
  remark =       "Describes a software implementation of IEEE 754 32-bit
                 and 64-bit arithmetic for the Blackfin fixed-point
                 embedded processor.",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2003:RHP
author: Anonymous
title: Recently heard Pentium jokes
pages: 281--281
day: 20
month: oct
monthnumber: 10
year: 2003
bibdate: Fri Jul 29 16:01:53 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.29 16:01:53 ???
keywords: Intel Pentium divide flaw; Thomas R. Nicely
acknowledgement: ack-nhfb
howpublished: World Wide Web document
rawauthor: Anonymous
rawtitle: Recently heard {Pentium} jokes
URL:
http://web.archive.org/web/20031020012234/http://www-pcd.stanford.edu/cousins/pentium.html; http://www-pcd.stanford.edu/cousins/pentium.html

entry:
@Misc{Anonymous:2003:RHP,
  author =       "Anonymous",
  title =        "Recently heard {Pentium} jokes",
  howpublished = "World Wide Web document",
  day =          "20",
  month =        oct,
  year =         "2003",
  bibdate =      "Fri Jul 29 16:01:53 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://web.archive.org/web/20031020012234/http://www-pcd.stanford.edu/cousins/pentium.html;
                 http://www-pcd.stanford.edu/cousins/pentium.html",
  acknowledgement = ack-nhfb,
  keywords =     "Intel Pentium divide flaw; Thomas R. Nicely",
}


bibtype: article
filename: fparith.bib
label: Arnold:2003:FFT
author: M. Arnold and T. Bailey and J. Cowles and C. Walter
title: Fast Fourier Transforms Using the Complex Logarithmic Number System
journal: j-J-VLSI-SIGNAL-PROC
volume: 33
number: 3
pages: 325--335
month: mar
monthnumber: 3
year: 2003
CODEN: JVSPED
DOI: https://doi.org/10.1023/A:1022236132192
ISSN: 0922-5773 (print), 1573-109x (electronic) OR 09225773 (print), 1573109x (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Sat Aug 22 09:28:10 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.08.22 09:28:10 ???
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
rawauthor: M. Arnold and T. Bailey and J. Cowles and C. Walter
rawtitle: {Fast Fourier Transforms} Using the Complex Logarithmic Number System
abstract:
The complex-logarithmic number system (CLNS), which represents each complex point in log/polar coordinates, may be practical to implement the Fast Fourier Transform (FFT). The roots of unity needed by the FFT have exact representations in CLNS and do not require a ROM.par We present an error analysis and simulation results for a radix-two FFT that compares a rectangular fixed-point representation of complex numbers to CLNS. We observe that CLNS saves 9--12 bits in word-size for 256--1024 point FFTs compared to the fixed-point number system while producing comparable accuracy.par The consequence of the word-size advantage is that the number of full adders required for CLNS is significantly smaller than for an equivalent fixed-point implementation. The major cost of CLNS is the memory, which unlike conventional LNS, is addressed by both real and imaginary parts. Table-reduction techniques can mitigate this. The simplicity of the CLNS approach requires significantly fewer full adders, which pays for some or all of the extra memory. In applications needing the magnitude of the complex parts, such as a power spectrum, the CLNS approach can actually require less memory than the conventional approach.

rawabstract:
The complex-logarithmic number system (CLNS), which represents each complex point in log/polar coordinates, may be practical to implement the Fast Fourier Transform (FFT). The roots of unity needed by the FFT have exact representations in CLNS and do not require a ROM.\par We present an error analysis and simulation results for a radix-two FFT that compares a rectangular fixed-point representation of complex numbers to CLNS. We observe that CLNS saves 9--12 bits in word-size for 256--1024 point FFTs compared to the fixed-point number system while producing comparable accuracy.\par The consequence of the word-size advantage is that the number of full adders required for CLNS is significantly smaller than for an equivalent fixed-point implementation. The major cost of CLNS is the memory, which unlike conventional LNS, is addressed by both real and imaginary parts. Table-reduction techniques can mitigate this. The simplicity of the CLNS approach requires significantly fewer full adders, which pays for some or all of the extra memory. In applications needing the magnitude of the complex parts, such as a power spectrum, the CLNS approach can actually require less memory than the conventional approach.

entry:
@Article{Arnold:2003:FFT,
  author =       "M. Arnold and T. Bailey and J. Cowles and C. Walter",
  title =        "{Fast Fourier Transforms} Using the Complex
                 Logarithmic Number System",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "33",
  number =       "3",
  pages =        "325--335",
  month =        mar,
  year =         "2003",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1023/A:1022236132192",
  ISSN =         "0922-5773 (print), 1573-109x (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Sat Aug 22 09:28:10 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The complex-logarithmic number system (CLNS), which
                 represents each complex point in log/polar coordinates,
                 may be practical to implement the Fast Fourier
                 Transform (FFT). The roots of unity needed by the FFT
                 have exact representations in CLNS and do not require a
                 ROM.\par

                 We present an error analysis and simulation results for
                 a radix-two FFT that compares a rectangular fixed-point
                 representation of complex numbers to CLNS. We observe
                 that CLNS saves 9--12 bits in word-size for 256--1024
                 point FFTs compared to the fixed-point number system
                 while producing comparable accuracy.\par

                 The consequence of the word-size advantage is that the
                 number of full adders required for CLNS is
                 significantly smaller than for an equivalent
                 fixed-point implementation. The major cost of CLNS is
                 the memory, which unlike conventional LNS, is addressed
                 by both real and imaginary parts. Table-reduction
                 techniques can mitigate this. The simplicity of the
                 CLNS approach requires significantly fewer full adders,
                 which pays for some or all of the extra memory. In
                 applications needing the magnitude of the complex
                 parts, such as a power spectrum, the CLNS approach can
                 actually require less memory than the conventional
                 approach.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of VLSI Signal Processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Arnold:2003:ILN
author: Mark G. Arnold and Jesus Garcia and Michael J. Schulte
title: The interval logarithmic number system
crossref: Bajard:2003:ISC
pages: 253--261
year: 2003
bibdate: Wed Nov 26 12:04:40 MST 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.26 12:04:40 MST
keywords: ARITH-16
acknowledgement: ack-nhfb
rawauthor: Mark G. Arnold and Jesus Garcia and Michael J. Schulte
rawtitle: The interval logarithmic number system
URL:
http://mesa.ece.wisc.edu/publications/cp_2003-01.pdf; http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Arnold.pdf

abstract:
This paper introduces the Interval Logarithmic Number System (ILNS), in which the Logarithmic Number System (LNS) is used as the underlying number system for interval arithmetic. The basic operations in ILNS are introduced and an efficient method for performing ILNS addition and subtraction is presented. The paper compares ILNS to Interval Floating Point (IFP) for a few sample applications. For applications like the N-body problem, which have a large percentage of multiplies, divides and square roots, ILNS provides much narrower intervals than IFP. In other applications, like the Fast Fourier Transform, where addition and subtraction dominate, ILNS and IFP produce intervals having similar widths. Based on our analysis, ILNS is an attractive alternative to IFP for application that can tolerate low to moderate precisions.

rawabstract:
This paper introduces the Interval Logarithmic Number System (ILNS), in which the Logarithmic Number System (LNS) is used as the underlying number system for interval arithmetic. The basic operations in ILNS are introduced and an efficient method for performing ILNS addition and subtraction is presented. The paper compares ILNS to Interval Floating Point (IFP) for a few sample applications. For applications like the N-body problem, which have a large percentage of multiplies, divides and square roots, ILNS provides much narrower intervals than IFP. In other applications, like the Fast Fourier Transform, where addition and subtraction dominate, ILNS and IFP produce intervals having similar widths. Based on our analysis, ILNS is an attractive alternative to IFP for application that can tolerate low to moderate precisions.

entry:
@InProceedings{Arnold:2003:ILN,
  author =       "Mark G. Arnold and Jesus Garcia and Michael J.
                 Schulte",
  title =        "The interval logarithmic number system",
  crossref =     "Bajard:2003:ISC",
  pages =        "253--261",
  year =         "2003",
  bibdate =      "Wed Nov 26 12:04:40 MST 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2003-01.pdf;
                 http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Arnold.pdf",
  abstract =     "This paper introduces the Interval Logarithmic Number
                 System (ILNS), in which the Logarithmic Number System
                 (LNS) is used as the underlying number system for
                 interval arithmetic. The basic operations in ILNS are
                 introduced and an efficient method for performing ILNS
                 addition and subtraction is presented. The paper
                 compares ILNS to Interval Floating Point (IFP) for a
                 few sample applications. For applications like the
                 N-body problem, which have a large percentage of
                 multiplies, divides and square roots, ILNS provides
                 much narrower intervals than IFP. In other
                 applications, like the Fast Fourier Transform, where
                 addition and subtraction dominate, ILNS and IFP produce
                 intervals having similar widths. Based on our analysis,
                 ILNS is an attractive alternative to IFP for
                 application that can tolerate low to moderate
                 precisions.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-16",
}


bibtype: inproceedings
filename: fparith.bib
label: Bajard:2003:EMG
author: J.-C. Bajard and L. Imbert and C. Negre and T. Plantard
title: Efficient multiplication in $ mathrm GF(p_k) $ for Elliptic Curve Cryptography
crossref: Bajard:2003:ISC
pages: 181--187
year: 2003
bibdate: Wed Nov 26 12:04:35 MST 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.26 12:04:35 MST
URL: http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Bajard.pdf
keywords: ARITH-16
acknowledgement: ack-nhfb
rawauthor: J.-C. Bajard and L. Imbert and C. N{\`e}gre and T. Plantard
rawtitle: Efficient multiplication in {$ \mathrm {GF}(p_k) $} for Elliptic Curve Cryptography
abstract:
We present a new multiplication algorithm for the implementation of elliptic curve cryptography (ECC) over the finite extension fields $ mathrm GF(p_k) $ where $p$ is a prime number greater than $ 2 k $. In the context of ECC we can assume that $p$ is a 7-to-10 bit number, and easily find values for $k$ which satisfy: $ p > 2 k $, and for security reasons $ l o g_2 (p) times k approx 160 $. All the computations are performed within an alternate polynomial representation of the field elements which is directly obtained from the inputs. No conversion step is needed. We describe our algorithm in terms of matrix operations and point out some properties of the matrices that can be used to improve the design. The proposed algorithm is highly parallelizable and seems well adapted to hardware implementation of elliptic curve cryptosystems.

rawabstract:
We present a new multiplication algorithm for the implementation of elliptic curve cryptography (ECC) over the finite extension fields $ \mathrm {GF}(p_k) $ where $p$ is a prime number greater than $ 2 k $. In the context of ECC we can assume that $p$ is a 7-to-10 bit number, and easily find values for $k$ which satisfy: $ p > 2 k $, and for security reasons $ l o g_2 (p) \times k \approx 160 $. All the computations are performed within an alternate polynomial representation of the field elements which is directly obtained from the inputs. No conversion step is needed. We describe our algorithm in terms of matrix operations and point out some properties of the matrices that can be used to improve the design. The proposed algorithm is highly parallelizable and seems well adapted to hardware implementation of elliptic curve cryptosystems.

entry:
@InProceedings{Bajard:2003:EMG,
  author =       "J.-C. Bajard and L. Imbert and C. N{\`e}gre and T.
                 Plantard",
  title =        "Efficient multiplication in {$ \mathrm {GF}(p_k) $}
                 for Elliptic Curve Cryptography",
  crossref =     "Bajard:2003:ISC",
  pages =        "181--187",
  year =         "2003",
  bibdate =      "Wed Nov 26 12:04:35 MST 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Bajard.pdf",
  abstract =     "We present a new multiplication algorithm for the
                 implementation of elliptic curve cryptography (ECC)
                 over the finite extension fields $ \mathrm {GF}(p_k) $
                 where $p$ is a prime number greater than $ 2 k $. In
                 the context of ECC we can assume that $p$ is a 7-to-10
                 bit number, and easily find values for $k$ which
                 satisfy: $ p > 2 k $, and for security reasons $ l o
                 g_2 (p) \times k \approx 160 $. All the computations
                 are performed within an alternate polynomial
                 representation of the field elements which is directly
                 obtained from the inputs. No conversion step is needed.
                 We describe our algorithm in terms of matrix operations
                 and point out some properties of the matrices that can
                 be used to improve the design. The proposed algorithm
                 is highly parallelizable and seems well adapted to
                 hardware implementation of elliptic curve
                 cryptosystems.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-16",
}


bibtype: inproceedings
filename: fparith.bib
label: Bajard:2003:FII
author: Jean-Claude Bajard and Michael Schulte
title: Foreword: 16th IEEE International Symposium on Computer Arithmetic
crossref: Bajard:2003:ISC
pages: viii--viii
year: 2003
bibdate: Sat Nov 17 21:53:37 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.17 21:53:37 ???
keywords: ARITH-16
acknowledgement: ack-nhfb
rawauthor: Jean-Claude Bajard and Michael Schulte
rawtitle: Foreword: {16th IEEE International Symposium on Computer Arithmetic}
URL:
http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_contents.pdf; http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_foreword.pdf; http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_preface.pdf

entry:
@InProceedings{Bajard:2003:FII,
  author =       "Jean-Claude Bajard and Michael Schulte",
  title =        "Foreword: {16th IEEE International Symposium on
                 Computer Arithmetic}",
  crossref =     "Bajard:2003:ISC",
  pages =        "viii--viii",
  year =         "2003",
  bibdate =      "Sat Nov 17 21:53:37 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_contents.pdf;
                 http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_foreword.pdf;
                 http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_preface.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-16",
}


bibtype: article
filename: fparith.bib
label: Barrio:2003:NEL
author: Roberto Barrio and B. Melendo and S. Serrano
title: On the numerical evaluation of linear recurrences
journal: j-J-COMPUT-APPL-MATH
volume: 150
number: 1
pages: 71--86
day: 1
month: jan
monthnumber: 1
year: 2003
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 12:52:32 MST 2017
bibtimestamp: 2017.02.25 12:52:32 MST
URL: http://www.sciencedirect.com/science/article/pii/S0377042702005654
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Roberto Barrio and B. Melendo and S. Serrano
rawtitle: On the numerical evaluation of linear recurrences
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2000.bib

entry:
@Article{Barrio:2003:NEL,
  author =       "Roberto Barrio and B. Melendo and S. Serrano",
  title =        "On the numerical evaluation of linear recurrences",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "150",
  number =       "1",
  pages =        "71--86",
  day =          "1",
  month =        jan,
  year =         "2003",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 12:52:32 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2000.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042702005654",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: article
filename: fparith.bib
label: Barrio:2003:URE
author: Roberto Barrio
title: A unified rounding error bound for polynomial evaluation
journal: j-ADV-COMPUT-MATH
volume: 19
number: 4
pages: 385--399
month: nov
monthnumber: 11
year: 2003
CODEN: ACMHEX
DOI: https://doi.org/10.1023/A:1024203520270
ISSN: 1019-7168 (print), 1572-9044 (electronic) OR 10197168 (print), 15729044 (electronic)
ISSNL: 1019-7168 OR 10197168
MRclass: 65G50
MRnumber: 1989623
bibdate: Sat Feb 3 18:22:17 MST 2018
bibtimestamp: 2018.02.03 18:22:17 MST
URL: http://link.springer.com/article/10.1023/A:1024203520270
fjournal: Advances in Computational Mathematics
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10444
rawauthor: Roberto Barrio
rawtitle: A unified rounding error bound for polynomial evaluation
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/f/forsythe-george-elmer.bib; https://www.math.utah.edu/pub/bibnet/authors/w/wilkinson-james-hardy.bib; https://www.math.utah.edu/pub/tex/bib/advcomputmath.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
Bernstein polynomial; Clenshaw--Forsythe algorithm; de-Casteljau algorithm; Horner's algorithm; polynomial evaluation; recurrence relations; rounding errors; Szego polynomial

entry:
@Article{Barrio:2003:URE,
  author =       "Roberto Barrio",
  title =        "A unified rounding error bound for polynomial
                 evaluation",
  journal =      j-ADV-COMPUT-MATH,
  volume =       "19",
  number =       "4",
  pages =        "385--399",
  month =        nov,
  year =         "2003",
  CODEN =        "ACMHEX",
  DOI =          "https://doi.org/10.1023/A:1024203520270",
  ISSN =         "1019-7168 (print), 1572-9044 (electronic)",
  ISSN-L =       "1019-7168",
  MRclass =      "65G50",
  MRnumber =     "1989623",
  bibdate =      "Sat Feb 3 18:22:17 MST 2018",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/f/forsythe-george-elmer.bib;
                 https://www.math.utah.edu/pub/bibnet/authors/w/wilkinson-james-hardy.bib;
                 https://www.math.utah.edu/pub/tex/bib/advcomputmath.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer.com/article/10.1023/A:1024203520270",
  acknowledgement = ack-nhfb,
  fjournal =     "Advances in Computational Mathematics",
  journal-URL =  "http://link.springer.com/journal/10444",
  keywords =     "Bernstein polynomial; Clenshaw--Forsythe algorithm;
                 de-Casteljau algorithm; Horner's algorithm; polynomial
                 evaluation; recurrence relations; rounding errors;
                 Szeg{\H{o}} polynomial",
}


bibtype: article
filename: fparith.bib
label: Bertoni:2003:EAA
title: Efficient $ GF(p^m) $ Arithmetic Architectures for Cryptographic Applications
journal: j-LECT-NOTES-COMP-SCI
volume: 2612
pages: 158--175
year: 2003
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Apr 4 18:46:22 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.04.04 18:46:22 ???
fjournal: Lecture Notes in Computer Science
keywords: cryptology; Topics in Cryptology CT-RSA 2003
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawtitle: Efficient $ {GF}(p^m) $ Arithmetic Architectures for Cryptographic Applications
author:
Guido Bertoni and Jorge Guajardo and Sandeep Kumar and Gerardo Orlando and Christof Paar and Thomas Wollinger

rawauthor:
Guido Bertoni and Jorge Guajardo and Sandeep Kumar and Gerardo Orlando and Christof Paar and Thomas Wollinger

entry:
@Article{Bertoni:2003:EAA,
  author =       "Guido Bertoni and Jorge Guajardo and Sandeep Kumar and
                 Gerardo Orlando and Christof Paar and Thomas
                 Wollinger",
  title =        "Efficient $ {GF}(p^m) $ Arithmetic Architectures for
                 Cryptographic Applications",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2612",
  pages =        "158--175",
  year =         "2003",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Apr 4 18:46:22 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  keywords =     "cryptology; Topics in Cryptology CT-RSA 2003",
}


bibtype: inproceedings
filename: fparith.bib
label: Boldo:2003:FPC
author: Sylvie Boldo and Marc Daumas and Laurent Thery
editor: Therese Hardin and Renaud Rioboo
title: Formal proofs and computations in finite precision arithmetic
pages: 101--111
year: 2003
bibdate: Tue Nov 23 10:09:27 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.23 10:09:27 ???
URL: http://ftp.lip6.fr/lip6/reports/2003/lip6.2003.010.pdf
acknowledgement: ack-nhfb
bookpages: vii + 141
rawauthor: Sylvie Boldo and Marc Daumas and Laurent Th{\'e}ry
raweditor: Th{\'e}r{\`e}se Hardin and Renaud Rioboo
rawtitle: Formal proofs and computations in finite precision arithmetic
booktitle:
CALCULEMUS-2003: 11th Symposium on the Integration of Symbolic Computation and Mechanized Reasoning: September 10--12, 2003, Roma, Italy

rawbooktitle:
{CALCULEMUS-2003: 11th} Symposium on the Integration of Symbolic Computation and Mechanized Reasoning: September 10--12, 2003, Roma, Italy

entry:
@InProceedings{Boldo:2003:FPC,
  author =       "Sylvie Boldo and Marc Daumas and Laurent Th{\'e}ry",
  editor =       "Th{\'e}r{\`e}se Hardin and Renaud Rioboo",
  booktitle =    "{CALCULEMUS-2003: 11th} Symposium on the Integration
                 of Symbolic Computation and Mechanized Reasoning:
                 September 10--12, 2003, Roma, Italy",
  title =        "Formal proofs and computations in finite precision
                 arithmetic",
  publisher =    "????",
  address =      "????",
  bookpages =    "vii + 141",
  pages =        "101--111",
  year =         "2003",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Tue Nov 23 10:09:27 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ftp.lip6.fr/lip6/reports/2003/lip6.2003.010.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Boldo:2003:RCT
author: Sylvie Boldo and Marc Daumas
title: Representable correcting terms for possibly underflowing floating point operations
crossref: Bajard:2003:ISC
pages: 79--86
year: 2003
bibdate: Wed Nov 26 11:59:51 MST 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.26 11:59:51 MST
keywords: accurate floating-point summation; ARITH-16
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo and Marc Daumas
rawtitle: Representable correcting terms for possibly underflowing floating point operations
URL:
http://csdl.computer.org/comp/proceedings/arith/2003/1894/00/1894toc.htm; http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Boldo.pdf; http://www.dec.usc.es/arith16/papers/paper-156.pdf

abstract:
Studying floating point arithmetic, authors have shown that the implemented operations (addition, subtraction, multiplication, division and square root) can compute a result and an exact correcting term using the same format as the inputs. Following a path initiated in 1965, many authors supposed that neither underflow nor overflow occurred in the process. Overflow is not critical as this kind of exception creates persisting nonnumeric quantities. Underflow may be fatal to the process as it returns wrong numeric values with little warning. Our new conditions guarantee that the correcting term is exact when the result is a number. We have validated our proofs against Coq automatic proof checker. Our development has raised many questions, some of them were expected while other ones were surprising.

rawabstract:
Studying floating point arithmetic, authors have shown that the implemented operations (addition, subtraction, multiplication, division and square root) can compute a result and an exact correcting term using the same format as the inputs. Following a path initiated in 1965, many authors supposed that neither underflow nor overflow occurred in the process. Overflow is not critical as this kind of exception creates persisting nonnumeric quantities. Underflow may be fatal to the process as it returns wrong numeric values with little warning. Our new conditions guarantee that the correcting term is exact when the result is a number. We have validated our proofs against Coq automatic proof checker. Our development has raised many questions, some of them were expected while other ones were surprising.

entry:
@InProceedings{Boldo:2003:RCT,
  author =       "Sylvie Boldo and Marc Daumas",
  title =        "Representable correcting terms for possibly
                 underflowing floating point operations",
  crossref =     "Bajard:2003:ISC",
  pages =        "79--86",
  year =         "2003",
  bibdate =      "Wed Nov 26 11:59:51 MST 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://csdl.computer.org/comp/proceedings/arith/2003/1894/00/1894toc.htm;
                 http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Boldo.pdf;
                 http://www.dec.usc.es/arith16/papers/paper-156.pdf",
  abstract =     "Studying floating point arithmetic, authors have shown
                 that the implemented operations (addition, subtraction,
                 multiplication, division and square root) can compute a
                 result and an exact correcting term using the same
                 format as the inputs. Following a path initiated in
                 1965, many authors supposed that neither underflow nor
                 overflow occurred in the process. Overflow is not
                 critical as this kind of exception creates persisting
                 nonnumeric quantities. Underflow may be fatal to the
                 process as it returns wrong numeric values with little
                 warning. Our new conditions guarantee that the
                 correcting term is exact when the result is a number.
                 We have validated our proofs against Coq automatic
                 proof checker. Our development has raised many
                 questions, some of them were expected while other ones
                 were surprising.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation; ARITH-16",
}


bibtype: techreport
filename: fparith.bib
label: Boldo:2003:STQ
author: Sylvie Boldo and Marc Daumas
title: A simple test qualifying the accuracy of Horner's rule for polynomials
type: Research Report
number: 2003-01
institution: Ecole Normale Superieure de Lyon
address: 69364 Lyon Cedex 07, France
pages: 41
month: jan
monthnumber: 1
year: 2003
bibdate: Tue Nov 23 10:54:34 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.11.23 10:54:34 ???
keywords: floating-point testing
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo and Marc Daumas
rawtitle: A simple test qualifying the accuracy of {Horner}'s rule for polynomials
URL:
ftp://ftp.ens-lyon.fr/pub/LIP/Rapports/RR/RR2003/RR2003-01.ps.gz; ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-4707.pdf

entry:
@TechReport{Boldo:2003:STQ,
  author =       "Sylvie Boldo and Marc Daumas",
  title =        "A simple test qualifying the accuracy of {Horner}'s
                 rule for polynomials",
  type =         "Research Report",
  number =       "2003-01",
  institution =  "{\'E}cole Normale Sup{\'e}rieure de Lyon",
  address =      "69364 Lyon Cedex 07, France",
  pages =        "41",
  month =        jan,
  year =         "2003",
  bibdate =      "Tue Nov 23 10:54:34 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://ftp.ens-lyon.fr/pub/LIP/Rapports/RR/RR2003/RR2003-01.ps.gz;
                 ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-4707.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point testing",
}


bibtype: inproceedings
filename: fparith.bib
label: Boullis:2003:SOH
author: Nicolas Boullis and Arnaud Tisserand
title: Some optimizations of hardware multiplication by constant matrices
crossref: Bajard:2003:ISC
pages: 20--27
year: 2003
bibdate: Wed Nov 26 11:59:51 MST 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.26 11:59:51 MST
URL: http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Boullis.pdf
keywords: ARITH-16
acknowledgement: ack-nhfb
rawauthor: Nicolas Boullis and Arnaud Tisserand
rawtitle: Some optimizations of hardware multiplication by constant matrices
abstract:
This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication (CMM), i.e. multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common sub-expression factorization algorithms was implemented in a VHDL generator. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40% area and speed savings are achieved.

rawabstract:
This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication (CMM), i.e. multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common sub-expression factorization algorithms was implemented in a VHDL generator. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40\% area and speed savings are achieved.

entry:
@InProceedings{Boullis:2003:SOH,
  author =       "Nicolas Boullis and Arnaud Tisserand",
  title =        "Some optimizations of hardware multiplication by
                 constant matrices",
  crossref =     "Bajard:2003:ISC",
  pages =        "20--27",
  year =         "2003",
  bibdate =      "Wed Nov 26 11:59:51 MST 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Boullis.pdf",
  abstract =     "This paper presents some improvements on the
                 optimization of hardware multiplication by constant
                 matrices. We focus on the automatic generation of
                 circuits that involve constant matrix multiplication
                 (CMM), i.e. multiplication of a vector by a constant
                 matrix. The proposed method, based on number recoding
                 and dedicated common sub-expression factorization
                 algorithms was implemented in a VHDL generator. The
                 obtained results on several applications have been
                 implemented on FPGAs and compared to previous
                 solutions. Up to 40\% area and speed savings are
                 achieved.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-16",
}


bibtype: techreport
filename: fparith.bib
label: Brisebarre:2003:FTP
author: Nicolas Brisebarre and Jean-Michel Muller
title: Finding the ``truncated'' polynomial that is closest to a function
type: Research Report
number: 4787
institution: INRIA Rhone-Alpes
address: ZIRST, 655 Avenue de l'Europe, Montbonnot, 38334 Saint Ismier cedex, France
pages: 20--27
year: 2003
bibdate: Fri Jun 24 14:41:03 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 14:41:03 ???
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Jean-Michel Muller
rawtitle: Finding the ``truncated'' polynomial that is closest to a function
URL:
ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-4787.pdf; ftp://ftp.inria.fr/INRIA/publication/publi-ps-gz/RR/RR-4787.ps.gz; http://arxiv.org/pdf/cs.MS/0307009; http://www.inria.fr/rrrt/rr-4787.html

abstract:
When implementing regular enough functions (e.g., elementary or special functions) on a computing system, we frequently use polynomial approximations. In most cases, the polynomial that best approximates (for a given distance and in a given interval) a function has coefficients that are not exactly representable with a finite number of bits. And yet, the polynomial approximations that are actually implemented do have coefficients that are represented with a finite - and sometimes small - number of bits: this is due to the finiteness of the floating-point representations (for software implementations), and to the need to have small, hence fast and/or inexpensive, multipliers (for hardware implementations). We then have to consider polynomial approximations for which the degree-$i$ coefficient has at most $ m_i $ fractional bits (in other words, it is a rational number with denominator $ 2^m_i $). We provide a general method for finding the best polynomial approximation under this constraint. Then, we suggest refinements than can be used to accelerate our method.

rawabstract:
When implementing regular enough functions (e.g., elementary or special functions) on a computing system, we frequently use polynomial approximations. In most cases, the polynomial that best approximates (for a given distance and in a given interval) a function has coefficients that are not exactly representable with a finite number of bits. And yet, the polynomial approximations that are actually implemented do have coefficients that are represented with a finite - and sometimes small - number of bits: this is due to the finiteness of the floating-point representations (for software implementations), and to the need to have small, hence fast and/or inexpensive, multipliers (for hardware implementations). We then have to consider polynomial approximations for which the degree-$i$ coefficient has at most $ m_i $ fractional bits (in other words, it is a rational number with denominator $ 2^{m_i} $). We provide a general method for finding the best polynomial approximation under this constraint. Then, we suggest refinements than can be used to accelerate our method.

entry:
@TechReport{Brisebarre:2003:FTP,
  author =       "Nicolas Brisebarre and Jean-Michel Muller",
  title =        "Finding the ``truncated'' polynomial that is closest
                 to a function",
  type =         "Research Report",
  number =       "4787",
  institution =  "INRIA Rhone-Alpes",
  address =      "ZIRST, 655 Avenue de l'Europe, Montbonnot, 38334 Saint
                 Ismier cedex, France",
  year =         "2003",
  bibdate =      "Fri Jun 24 14:41:03 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-4787.pdf;
                 ftp://ftp.inria.fr/INRIA/publication/publi-ps-gz/RR/RR-4787.ps.gz;
                 http://arxiv.org/pdf/cs.MS/0307009;
                 http://www.inria.fr/rrrt/rr-4787.html",
  abstract =     "When implementing regular enough functions (e.g.,
                 elementary or special functions) on a computing system,
                 we frequently use polynomial approximations. In most
                 cases, the polynomial that best approximates (for a
                 given distance and in a given interval) a function has
                 coefficients that are not exactly representable with a
                 finite number of bits. And yet, the polynomial
                 approximations that are actually implemented do have
                 coefficients that are represented with a finite - and
                 sometimes small - number of bits: this is due to the
                 finiteness of the floating-point representations (for
                 software implementations), and to the need to have
                 small, hence fast and/or inexpensive, multipliers (for
                 hardware implementations). We then have to consider
                 polynomial approximations for which the degree-$i$
                 coefficient has at most $ m_i $ fractional bits (in
                 other words, it is a rational number with denominator $
                 2^{m_i} $). We provide a general method for finding the
                 best polynomial approximation under this constraint.
                 Then, we suggest refinements than can be used to
                 accelerate our method.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Brown:2003:DPA
author: Walter E. Brown
title: A [DRAFT] Proposal to Add Mathematical Special Functions to the C++ Standard Library
pages: 20--27
day: 3
month: jan
monthnumber: 1
year: 2003
bibdate: Wed Jan 29 17:15:07 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.01.29 17:15:07 ???
URL: http://home.fnal.gov/~wb/N0000.html
acknowledgement: ack-nhfb
howpublished: World-Wide Web document
rawauthor: Walter E. Brown
rawtitle: A [{DRAFT}] Proposal to Add Mathematical Special Functions to the {C++ Standard Library}
entry:
@Misc{Brown:2003:DPA,
  author =       "Walter E. Brown",
  title =        "A [{DRAFT}] Proposal to Add Mathematical Special
                 Functions to the {C++ Standard Library}",
  howpublished = "World-Wide Web document",
  day =          "3",
  month =        jan,
  year =         "2003",
  bibdate =      "Wed Jan 29 17:15:07 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://home.fnal.gov/~wb/N0000.html",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Burgess:2003:SRN
author: Neil Burgess
title: Scaling an RNS number using the core function
crossref: Bajard:2003:ISC
pages: 262--269
year: 2003
bibdate: Wed Nov 26 12:04:40 MST 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.26 12:04:40 MST
URL: http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Burgess.pdf
keywords: ARITH-16
acknowledgement: ack-nhfb
rawauthor: Neil Burgess
rawtitle: Scaling an {RNS} number using the core function
abstract:
This paper introduces a method for extracting the core of a Residue Number System (RNS) number within the RNS, this affording a new method for scaling RNS numbers. Suppose an RNS comprises a set of co-prime moduli, $ m_i $, with $ prod m_i = M $. This paper describes a method for approximately scaling such an RNS number by a subset of the moduli, $ prod m_j = M_J = sqrt M $, with the characteristic that all computations are performed using the original moduli and one other non-maintained short wordlength modulus.

rawabstract:
This paper introduces a method for extracting the core of a Residue Number System (RNS) number within the RNS, this affording a new method for scaling RNS numbers. Suppose an RNS comprises a set of co-prime moduli, $ m_i $, with $ \prod m_i = M $. This paper describes a method for approximately scaling such an RNS number by a subset of the moduli, $ \prod m_j = M_J = \sqrt {M} $, with the characteristic that all computations are performed using the original moduli and one other non-maintained short wordlength modulus.

entry:
@InProceedings{Burgess:2003:SRN,
  author =       "Neil Burgess",
  title =        "Scaling an {RNS} number using the core function",
  crossref =     "Bajard:2003:ISC",
  pages =        "262--269",
  year =         "2003",
  bibdate =      "Wed Nov 26 12:04:40 MST 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Burgess.pdf",
  abstract =     "This paper introduces a method for extracting the core
                 of a Residue Number System (RNS) number within the RNS,
                 this affording a new method for scaling RNS numbers.
                 Suppose an RNS comprises a set of co-prime moduli, $
                 m_i $, with $ \prod m_i = M $. This paper describes a
                 method for approximately scaling such an RNS number by
                 a subset of the moduli, $ \prod m_j = M_J = \sqrt {M}
                 $, with the characteristic that all computations are
                 performed using the original moduli and one other
                 non-maintained short wordlength modulus.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-16",
}


bibtype: inproceedings
filename: fparith.bib
label: Cao:2003:DHS
author: Bin Cao and T. Srikanthan and Chip-Hong Chang
booktitle: ISCAS '03, Proceedings of the 2003 International Symposium on Circuits and Systems, 25--28 May 2003
title: Design of a high speed reverse converter for a new $4$-moduli set residue number system
volume: 4
publisher: pub-IEEE
address: pub-IEEE:adr
pages: IV-520--IV-523
year: 2003
DOI: https://doi.org/10.1109/ISCAS.2003.1205951
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: Bin Cao and T. Srikanthan and Chip-Hong Chang
rawtitle: Design of a high speed reverse converter for a new $4$-moduli set residue number system
rawbooktitle:
{ISCAS '03}, Proceedings of the 2003 International Symposium on Circuits and Systems, 25--28 May 2003

entry:
@InProceedings{Cao:2003:DHS,
  author =       "Bin Cao and T. Srikanthan and Chip-Hong Chang",
  booktitle =    "{ISCAS '03}, Proceedings of the 2003 International
                 Symposium on Circuits and Systems, 25--28 May 2003",
  title =        "Design of a high speed reverse converter for a new
                 $4$-moduli set residue number system",
  volume =       "4",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "IV-520--IV-523",
  year =         "2003",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ISCAS.2003.1205951",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "This paper presents an elegant residue-to-binary
                 algorithm for a new 4-moduli set (2/sup n/ - 1, 2/sup
                 n/, 2/sup n/ + 1, 2/sup 2n/ + 1) Residue Number System.
                 Our reverse conversion algorithm takes advantage of the
                 special number properties of the \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Chaudhuri:2003:DAO
author: Ranjan Chaudhuri
title: Do the arithmetic operations really execute in constant time?
journal: j-SIGCSE
volume: 35
number: 2
pages: 43--44
month: jun
monthnumber: 6
year: 2003
CODEN: SIGSD3
DOI: https://doi.org/10.1145/782941.782977
ISSN: 0097-8418 (print), 2331-3927 (electronic) OR 00978418 (print), 23313927 (electronic)
ISSNL: 0097-8418 OR 00978418
bibdate: Sat Nov 17 16:57:02 MST 2012
bibtimestamp: 2012.11.17 16:57:02 MST
URL: ftp://ftp.math.utah.edu/pub/mirrors/ftp.ira.uka.de/bibliography/Misc/DBLP/2003.bib
fjournal: SIGCSE Bulletin (ACM Special Interest Group on Computer Science Education)
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J688
rawauthor: Ranjan Chaudhuri
rawtitle: Do the arithmetic operations really execute in constant time?
bibsource:
DBLP; http://dblp.uni-trier.de/db/journals/sigcse/sigcse35.html#Chaudhuri03; http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigcse2000.bib

abstract:
The paper emphasizes the need for exposing the undergraduate computer science students to the bit-level analysis of the run-times of certain computer algorithms. These are algorithms where the input(s) consist of one or more integers and only a bit-level analysis yields a more realistic estimate of the run-time behaviors of such algorithms.

rawabstract:
The paper emphasizes the need for exposing the undergraduate computer science students to the bit-level analysis of the run-times of certain computer algorithms. These are algorithms where the input(s) consist of one or more integers and only a bit-level analysis yields a more realistic estimate of the run-time behaviors of such algorithms.

entry:
@Article{Chaudhuri:2003:DAO,
  author =       "Ranjan Chaudhuri",
  title =        "Do the arithmetic operations really execute in
                 constant time?",
  journal =      j-SIGCSE,
  volume =       "35",
  number =       "2",
  pages =        "43--44",
  month =        jun,
  year =         "2003",
  CODEN =        "SIGSD3",
  DOI =          "https://doi.org/10.1145/782941.782977",
  ISSN =         "0097-8418 (print), 2331-3927 (electronic)",
  ISSN-L =       "0097-8418",
  bibdate =      "Sat Nov 17 16:57:02 MST 2012",
  bibsource =    "DBLP;
                 http://dblp.uni-trier.de/db/journals/sigcse/sigcse35.html#Chaudhuri03;
                 http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigcse2000.bib",
  URL =          "ftp://ftp.math.utah.edu/pub/mirrors/ftp.ira.uka.de/bibliography/Misc/DBLP/2003.bib",
  abstract =     "The paper emphasizes the need for exposing the
                 undergraduate computer science students to the
                 bit-level analysis of the run-times of certain computer
                 algorithms. These are algorithms where the input(s)
                 consist of one or more integers and only a bit-level
                 analysis yields a more realistic estimate of the
                 run-time behaviors of such algorithms.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIGCSE Bulletin (ACM Special Interest Group on
                 Computer Science Education)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J688",
}


bibtype: inproceedings
filename: fparith.bib
label: Chaves:2003:RRD
author: R. Chaves and L. Sousa
booktitle: Proceedings. Euromicro Symposium on Digital System Design, 2003
title: RDSP: a RISC DSP based on residue number system
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 128--135
year: 2003
DOI: https://doi.org/10.1109/DSD.2003.1231911
ISBN: 0-7695-2003-0 OR 0769520030
ISBN13: 978-0-7695-2003-2 OR 9780769520032
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: R. Chaves and L. Sousa
rawbooktitle: Proceedings. Euromicro Symposium on Digital System Design, 2003
rawtitle: {RDSP}: a {RISC} {DSP} based on residue number system
entry:
@InProceedings{Chaves:2003:RRD,
  author =       "R. Chaves and L. Sousa",
  booktitle =    "Proceedings. Euromicro Symposium on Digital System
                 Design, 2003",
  title =        "{RDSP}: a {RISC} {DSP} based on residue number
                 system",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "128--135",
  year =         "2003",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/DSD.2003.1231911",
  ISBN =         "0-7695-2003-0",
  ISBN-13 =      "978-0-7695-2003-2",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "This paper is focused on low power programmable fast
                 digital signal processors (DSP) design based on a
                 configurable 5-stage RISC core architecture and on
                 residue number systems (RNS). Several innovative
                 aspects are introduced at the control and \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Chen:2003:PIC
author: Chichyang Chen and Rui-Lin Chen
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 337--347
year: 2003
bibdate: Sat Jul 16 16:14:38 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 16:14:38 MDT
acknowledgement: ack-nhfb
rawauthor: Chichyang Chen and Rui-Lin Chen
booktitle:
Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, 24--26 June 2003

title:
Performance-improved computation of very large word-length LNS addition / subtraction using signed-digit arithmetic

rawbooktitle:
Proceedings of the {IEEE} International Conference on Application-Specific Systems, Architectures, and Processors, 24--26 June 2003

rawtitle:
Performance-improved computation of very large word-length {LNS} addition\slash subtraction using signed-digit arithmetic

entry:
@InProceedings{Chen:2003:PIC,
  author =       "Chichyang Chen and Rui-Lin Chen",
  booktitle =    "Proceedings of the {IEEE} International Conference on
                 Application-Specific Systems, Architectures, and
                 Processors, 24--26 June 2003",
  title =        "Performance-improved computation of very large
                 word-length {LNS} addition\slash subtraction using
                 signed-digit arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "337--347",
  year =         "2003",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 16:14:38 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "Pipelined computation of very large word-length LNS
                 addition/subtraction requires a significant amount of
                 hardware and long pipeline latency. We propose a base-e
                 exponential algorithm to simplify the exponential
                 computation and to replace half of \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Chevallier-Mames:2003:FDS
author: Benoit Chevallier-Mames and Marc Joye and Pascal Paillierinst
title: Faster Double-Size Modular Multiplication from Euclidean Multipliers
journal: j-LECT-NOTES-COMP-SCI
volume: 2779
pages: 214--227
year: 2003
CODEN: LNCSD9
ISSN: 0302-9743 (print), 1611-3349 (electronic) OR 03029743 (print), 16113349 (electronic)
ISSNL: 0302-9743 OR 03029743
bibdate: Tue Apr 4 18:12:50 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.04.04 18:12:50 ???
fjournal: Lecture Notes in Computer Science
keywords: CHES 2003; cryptography
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/bookseries/558
rawauthor: Beno{\^\i}t Chevallier-Mames and Marc Joye and Pascal Paillierinst
rawtitle: Faster Double-Size Modular Multiplication from {Euclidean} Multipliers
entry:
@Article{Chevallier-Mames:2003:FDS,
  author =       "Beno{\^\i}t Chevallier-Mames and Marc Joye and Pascal
                 Paillierinst",
  title =        "Faster Double-Size Modular Multiplication from
                 {Euclidean} Multipliers",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "2779",
  pages =        "214--227",
  year =         "2003",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Tue Apr 4 18:12:50 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
  journal-URL =  "http://link.springer.com/bookseries/558",
  keywords =     "CHES 2003; cryptography",
}


bibtype: inproceedings
filename: fparith.bib
label: Ciet:2003:PFI
author: M. Ciet and M. Neve and E. Peeters and J.-J. Quisquater
booktitle: MWSCAS '03. Proceedings of the 46th IEEE International Midwest Symposium on Circuits and Systems
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 806--810
year: 2003
DOI: https://doi.org/10.1109/MWSCAS.2003.1562409
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. Ciet and M. Neve and E. Peeters and J.-J. Quisquater
title:
Parallel FPGA implementation of RSA with residue number systems --- can side-channel threats be avoided?

rawbooktitle:
{MWSCAS '03}. Proceedings of the 46th {IEEE} International Midwest Symposium on Circuits and Systems

rawtitle:
Parallel {FPGA} implementation of {RSA} with residue number systems --- can side-channel threats be avoided?

entry:
@InProceedings{Ciet:2003:PFI,
  author =       "M. Ciet and M. Neve and E. Peeters and J.-J.
                 Quisquater",
  booktitle =    "{MWSCAS '03}. Proceedings of the 46th {IEEE}
                 International Midwest Symposium on Circuits and
                 Systems",
  title =        "Parallel {FPGA} implementation of {RSA} with residue
                 number systems --- can side-channel threats be
                 avoided?",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "806--810",
  year =         "2003",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/MWSCAS.2003.1562409",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "In this paper, the authors presented a new parallel
                 architecture to avoid side-channel analysis such as:
                 timing attack, simple/differential power analysis,
                 fault induction attack and simple/differential
                 electromagnetic analysis. Montgomery \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Constantinides:2003:BRB
author: George A. Constantinides
title: Book Review: booktitle Computer Arithmetic Algorithms, by Israel Koren. A.K. Peters
journal: j-SIGACT
volume: 34
number: 3
pages: 13--15
month: sep
monthnumber: 9
year: 2003
CODEN: SIGNDM
DOI: https://doi.org/10.1145/945526.945532
ISSN: 0163-5700 (print), 1943-5827 (electronic) OR 01635700 (print), 19435827 (electronic)
ISSNL: 0163-5700 OR 01635700
bibdate: Wed Mar 21 18:30:26 MDT 2012
bibtimestamp: 2012.03.21 18:30:26 MDT
note: See cite Koren:1993:CAA,Koren:2002:CAA.
fjournal: ACM SIGACT News
acknowledgement: ack-nhfb
journalURL: http://dl.acm.org/citation.cfm?id=J697
rawauthor: George A. Constantinides
rawnote: See \cite{Koren:1993:CAA,Koren:2002:CAA}.
rawtitle: Book Review: {{\booktitle{Computer Arithmetic Algorithms}}, by Israel Koren. A.K. Peters}
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigact.bib

entry:
@Article{Constantinides:2003:BRB,
  author =       "George A. Constantinides",
  title =        "Book Review: {{\booktitle{Computer Arithmetic
                 Algorithms}}, by Israel Koren. A.K. Peters}",
  journal =      j-SIGACT,
  volume =       "34",
  number =       "3",
  pages =        "13--15",
  month =        sep,
  year =         "2003",
  CODEN =        "SIGNDM",
  DOI =          "https://doi.org/10.1145/945526.945532",
  ISSN =         "0163-5700 (print), 1943-5827 (electronic)",
  ISSN-L =       "0163-5700",
  bibdate =      "Wed Mar 21 18:30:26 MDT 2012",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigact.bib",
  note =         "See \cite{Koren:1993:CAA,Koren:2002:CAA}.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGACT News",
  journal-URL =  "http://dl.acm.org/citation.cfm?id=J697",
}


bibtype: article
filename: fparith.bib
label: Constantinides:2003:SSA
author: G. A. Constantinides and P. Y. K. Cheung and W. Luk
title: Synthesis of saturation arithmetic architectures
journal: j-TODAES
volume: 8
number: 3
pages: 334--354
month: jul
monthnumber: 7
year: 2003
CODEN: ATASFO
ISSN: 1084-4309 (print), 1557-7309 (electronic) OR 10844309 (print), 15577309 (electronic)
ISSNL: 1084-4309 OR 10844309
bibdate: Thu Aug 7 11:12:06 MDT 2003
bibtimestamp: 2003.08.07 11:12:06 MDT
fjournal: ACM Transactions on Design Automation of Electronic Systems (TODAES)
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J776
rawauthor: G. A. Constantinides and P. Y. K. Cheung and W. Luk
rawtitle: Synthesis of saturation arithmetic architectures
bibsource:
http://www.acm.org/pubs/contents/journals/todaes/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Constantinides:2003:SSA,
  author =       "G. A. Constantinides and P. Y. K. Cheung and W. Luk",
  title =        "Synthesis of saturation arithmetic architectures",
  journal =      j-TODAES,
  volume =       "8",
  number =       "3",
  pages =        "334--354",
  month =        jul,
  year =         "2003",
  CODEN =        "ATASFO",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Thu Aug 7 11:12:06 MDT 2003",
  bibsource =    "http://www.acm.org/pubs/contents/journals/todaes/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems (TODAES)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J776",
}


bibtype: article
filename: fparith.bib
label: Conway:2003:NCB
author: R. Conway and J. Nelson
title: New CRT-based RNS converter using restricted moduli set
journal: j-IEEE-TRANS-COMPUT
volume: 52
number: 5
pages: 572--578
month: may
monthnumber: 5
year: 2003
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2003.1197124
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 08:52:48 MDT 2011
bibtimestamp: 2011.07.05 08:52:48 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1197124
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: R. Conway and J. Nelson
rawtitle: New {CRT}-based {RNS} converter using restricted moduli set
entry:
@Article{Conway:2003:NCB,
  author =       "R. Conway and J. Nelson",
  title =        "New {CRT}-based {RNS} converter using restricted
                 moduli set",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "52",
  number =       "5",
  pages =        "572--578",
  month =        may,
  year =         "2003",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2003.1197124",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 08:52:48 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1197124",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: techreport
filename: fparith.bib
label: Cornea:2003:DSR
author: M. Cornea and J. Harrison and C. Iordache and B. Norin and S. Story
title: Division, Square Root and Remainder Algorithms for the Intel Itanium Architecture
type: Report
institution: pub-INTEL
address: pub-INTEL:adr
pages: 572--578
month: nov
monthnumber: 11
year: 2003
bibdate: Fri Jun 24 12:05:58 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 12:05:58 ???
acknowledgement: ack-nhfb
rawauthor: M. Cornea and J. Harrison and C. Iordache and B. Norin and S. Story
rawtitle: Division, Square Root and Remainder Algorithms for the {Intel Itanium} Architecture
entry:
@TechReport{Cornea:2003:DSR,
  author =       "M. Cornea and J. Harrison and C. Iordache and B. Norin
                 and S. Story",
  title =        "Division, Square Root and Remainder Algorithms for the
                 {Intel Itanium} Architecture",
  type =         "Report",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  month =        nov,
  year =         "2003",
  bibdate =      "Fri Jun 24 12:05:58 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Cotofana:2003:CAR
author: Sorin Cotofana and Casper Lageweg and Stamatis Vassiliadis
title: On computing addition related arithmetic operations via controlled transport of charge
crossref: Bajard:2003:ISC
pages: 245--252
year: 2003
bibdate: Wed Nov 26 12:04:40 MST 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.26 12:04:40 MST
URL: http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Cotofana.pdf
keywords: ARITH-16
acknowledgement: ack-nhfb
rawauthor: Sorin Cotofana and Casper Lageweg and Stamatis Vassiliadis
rawtitle: On computing addition related arithmetic operations via controlled transport of charge
abstract:
In this paper we investigate the implementation of basic arithmetic functions, such as addition and multiplication, in Single Electron Tunneling (SET) technology. First, we describe the SET equivalents of Boolean CMOS gates and Threshold logic gates. Second, we propose a set of building blocks, which can be utilized for a novel design style, namely arithmetic operations performed by direct manipulation of the location of individual electrons within the system. Using this new set of building blocks, we propose several novel approaches for computing addition related arithmetic operations via the controlled transport of charge (individual electrons). In particular, we prove the following: $n$-bit addition can be implemented with a depth-$2$ network built with $ O(n) $ circuit elements; $n$-input parity can be computed with a depth-$2$ network constructed with $ O(n) $ circuit elements and the same applies for $ n | log n $ counters; multiple operand addition of $ m | n $-bit operands can be implemented with a depth-$2$ network using $ O(m n) $ circuit elements; and finally $n$-bit multiplication can be implemented with a depth-$3$ network built with $ O(n) $ circuit elements.

rawabstract:
In this paper we investigate the implementation of basic arithmetic functions, such as addition and multiplication, in Single Electron Tunneling (SET) technology. First, we describe the SET equivalents of Boolean CMOS gates and Threshold logic gates. Second, we propose a set of building blocks, which can be utilized for a novel design style, namely arithmetic operations performed by direct manipulation of the location of individual electrons within the system. Using this new set of building blocks, we propose several novel approaches for computing addition related arithmetic operations via the controlled transport of charge (individual electrons). In particular, we prove the following: $n$-bit addition can be implemented with a depth-$2$ network built with $ O(n) $ circuit elements; $n$-input parity can be computed with a depth-$2$ network constructed with $ O(n) $ circuit elements and the same applies for $ n | \log n $ counters; multiple operand addition of $ m | n $-bit operands can be implemented with a depth-$2$ network using $ O(m n) $ circuit elements; and finally $n$-bit multiplication can be implemented with a depth-$3$ network built with $ O(n) $ circuit elements.

entry:
@InProceedings{Cotofana:2003:CAR,
  author =       "Sorin Cotofana and Casper Lageweg and Stamatis
                 Vassiliadis",
  title =        "On computing addition related arithmetic operations
                 via controlled transport of charge",
  crossref =     "Bajard:2003:ISC",
  pages =        "245--252",
  year =         "2003",
  bibdate =      "Wed Nov 26 12:04:40 MST 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Cotofana.pdf",
  abstract =     "In this paper we investigate the implementation of
                 basic arithmetic functions, such as addition and
                 multiplication, in Single Electron Tunneling (SET)
                 technology. First, we describe the SET equivalents of
                 Boolean CMOS gates and Threshold logic gates. Second,
                 we propose a set of building blocks, which can be
                 utilized for a novel design style, namely arithmetic
                 operations performed by direct manipulation of the
                 location of individual electrons within the system.
                 Using this new set of building blocks, we propose
                 several novel approaches for computing addition related
                 arithmetic operations via the controlled transport of
                 charge (individual electrons). In particular, we prove
                 the following: $n$-bit addition can be implemented with
                 a depth-$2$ network built with $ O(n) $ circuit
                 elements; $n$-input parity can be computed with a
                 depth-$2$ network constructed with $ O(n) $ circuit
                 elements and the same applies for $ n | \log n $
                 counters; multiple operand addition of $ m | n $-bit
                 operands can be implemented with a depth-$2$ network
                 using $ O(m n) $ circuit elements; and finally $n$-bit
                 multiplication can be implemented with a depth-$3$
                 network built with $ O(n) $ circuit elements.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-16",
}


bibtype: techreport
filename: fparith.bib
label: Cowlishaw:2003:DAE
author: Mike Cowlishaw
title: Decimal Arithmetic Encoding Strawman 4d
type: Report
number: Version 0.96
institution: IBM UK Laboratories
address: Hursley, UK
pages: 245--252
day: 21
month: feb
monthnumber: 2
year: 2003
bibdate: Fri Mar 03 07:15:51 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.03.03 07:15:51 ???
URL: http://www2.hursley.ibm.com/decimal/decbits.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Mike Cowlishaw
rawtitle: Decimal Arithmetic Encoding Strawman 4d
abstract:
This document describes proposed encodings suitable for supporting the general purpose floating-point decimal arithmetic defined in the Decimal Arithmetic Specification, which allows fixed-point and integer decimal arithmetic as subsets. Three formats of decimal numbers are described: (1) a decimal32 number, which is encoded in four consecutive bytes (32 bits); (2) a decimal64 number, which is encoded in eight consecutive bytes (64 bits); (3) a decimal128 number, which is encoded in 16 consecutive bytes (128 bits). The encodings provide ranges of positive normal numbers of approximately $ [1.0 e - 95, 1.0 e + 97) $, $ [1.0 e - 383, 1.0 e + 385) $, and $ [1.0 e - 6143, 1.0 e6145) $, with precisions of 7, 16, and 34 decimal digits respectively. Subnormals extended the range down to 1.0e-390, 1.0e-398, and 1.0e-6176, respectively.

rawabstract:
This document describes proposed encodings suitable for supporting the general purpose floating-point decimal arithmetic defined in the Decimal Arithmetic Specification, which allows fixed-point and integer decimal arithmetic as subsets. Three formats of decimal numbers are described: (1) a decimal32 number, which is encoded in four consecutive bytes (32 bits); (2) a decimal64 number, which is encoded in eight consecutive bytes (64 bits); (3) a decimal128 number, which is encoded in 16 consecutive bytes (128 bits). The encodings provide ranges of positive normal numbers of approximately $ [1.0 e - 95, 1.0 e + 97) $, $ [1.0 e - 383, 1.0 e + 385) $, and $ [1.0 e - 6143, 1.0 e6145) $, with precisions of 7, 16, and 34 decimal digits respectively. Subnormals extended the range down to 1.0e-390, 1.0e-398, and 1.0e-6176, respectively.

entry:
@TechReport{Cowlishaw:2003:DAE,
  author =       "Mike Cowlishaw",
  title =        "Decimal Arithmetic Encoding Strawman 4d",
  type =         "Report",
  number =       "Version 0.96",
  institution =  "IBM UK Laboratories",
  address =      "Hursley, UK",
  day =          "21",
  month =        feb,
  year =         "2003",
  bibdate =      "Fri Mar 03 07:15:51 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www2.hursley.ibm.com/decimal/decbits.pdf",
  abstract =     "This document describes proposed encodings suitable
                 for supporting the general purpose floating-point
                 decimal arithmetic defined in the Decimal Arithmetic
                 Specification, which allows fixed-point and integer
                 decimal arithmetic as subsets.

                 Three formats of decimal numbers are described: (1) a
                 decimal32 number, which is encoded in four consecutive
                 bytes (32 bits); (2) a decimal64 number, which is
                 encoded in eight consecutive bytes (64 bits); (3) a
                 decimal128 number, which is encoded in 16 consecutive
                 bytes (128 bits). The encodings provide ranges of
                 positive normal numbers of approximately $ [1.0 e - 95,
                 1.0 e + 97) $, $ [1.0 e - 383, 1.0 e + 385) $, and $
                 [1.0 e - 6143, 1.0 e6145) $, with precisions of 7, 16,
                 and 34 decimal digits respectively. Subnormals extended
                 the range down to 1.0e-390, 1.0e-398, and 1.0e-6176,
                 respectively.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Cowlishaw:2003:DFP
author: Michael F. Cowlishaw
title: Decimal floating-point: algorism for computers
crossref: Bajard:2003:ISC
pages: 104--111
year: 2003
DOI: https://doi.org/10.1109/ARITH.2003.1207666
bibdate: Fri Nov 28 11:02:29 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 11:02:29 ???
keywords: algorism (the decimal system of numeration); ARITH-16; decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Michael F. Cowlishaw
rawtitle: Decimal floating-point: algorism for computers
URL:
http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Cowlishaw.pdf; http://www.dec.usc.es/arith16/papers/paper-107.pdf; http://www2.hursley.ibm.com/decimal/IEEE-cowlishaw-arith16.pdf

abstract:
Decimal arithmetic is the norm in human calculations, and human-centric applications must use a decimal floating-point arithmetic to achieve the same results.par Initial benchmarks indicate that some applications spend 50% to 90% of their time in decimal processing, because software decimal arithmetic suffers a $ 100 times $ to $ 1000 times $ performance penalty over hardware. The need for decimal floating-point in hardware is urgent.par Existing designs, however, either fail to conform to modern standards or are incompatible with the established rules of decimal arithmetic. This paper introduces a new approach to decimal floating-point which not only provides the strict results which are necessary for commercial applications but also meets the constraints and requirements of the IEEE 854 standard.par A hardware implementation of this arithmetic is in development, and it is expected that this will significantly accelerate a wide variety of applications.

rawabstract:
Decimal arithmetic is the norm in human calculations, and human-centric applications must use a decimal floating-point arithmetic to achieve the same results.\par Initial benchmarks indicate that some applications spend 50\% to 90\% of their time in decimal processing, because software decimal arithmetic suffers a $ 100 \times $ to $ 1000 \times $ performance penalty over hardware. The need for decimal floating-point in hardware is urgent.\par Existing designs, however, either fail to conform to modern standards or are incompatible with the established rules of decimal arithmetic. This paper introduces a new approach to decimal floating-point which not only provides the strict results which are necessary for commercial applications but also meets the constraints and requirements of the IEEE 854 standard.\par A hardware implementation of this arithmetic is in development, and it is expected that this will significantly accelerate a wide variety of applications.

entry:
@InProceedings{Cowlishaw:2003:DFP,
  author =       "Michael F. Cowlishaw",
  title =        "Decimal floating-point: algorism for computers",
  crossref =     "Bajard:2003:ISC",
  pages =        "104--111",
  year =         "2003",
  DOI =          "https://doi.org/10.1109/ARITH.2003.1207666",
  bibdate =      "Fri Nov 28 11:02:29 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Cowlishaw.pdf;
                 http://www.dec.usc.es/arith16/papers/paper-107.pdf;
                 http://www2.hursley.ibm.com/decimal/IEEE-cowlishaw-arith16.pdf",
  abstract =     "Decimal arithmetic is the norm in human calculations,
                 and human-centric applications must use a decimal
                 floating-point arithmetic to achieve the same
                 results.\par

                 Initial benchmarks indicate that some applications
                 spend 50\% to 90\% of their time in decimal processing,
                 because software decimal arithmetic suffers a $ 100
                 \times $ to $ 1000 \times $ performance penalty over
                 hardware. The need for decimal floating-point in
                 hardware is urgent.\par

                 Existing designs, however, either fail to conform to
                 modern standards or are incompatible with the
                 established rules of decimal arithmetic. This paper
                 introduces a new approach to decimal floating-point
                 which not only provides the strict results which are
                 necessary for commercial applications but also meets
                 the constraints and requirements of the IEEE 854
                 standard.\par

                 A hardware implementation of this arithmetic is in
                 development, and it is expected that this will
                 significantly accelerate a wide variety of
                 applications.",
  acknowledgement = ack-nhfb,
  keywords =     "algorism (the decimal system of numeration); ARITH-16;
                 decimal floating-point arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Daneshbeh:2003:UBS
author: Amir.K. Daneshbeh and M. A. Hasan
title: A unidirectional bit serial systolic architecture for double-basis division over $ mathrm GF(2^m) $
crossref: Bajard:2003:ISC
pages: 174--180
year: 2003
bibdate: Wed Nov 26 12:04:35 MST 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.26 12:04:35 MST
URL: http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Daneshbeh.pdf
keywords: ARITH-16
acknowledgement: ack-nhfb
rawauthor: Amir.K. Daneshbeh and M. A. Hasan
abstract:
A unidirectional bit serial systolic architecture for division over Galois field $ mathrm GF(2^m) $ is presented which uses both triangular and polynomial basis representations. It is suitable for hardware implementations where the dimension of the field is large and may vary. This is the typical case for cryptographic applications. This architecture is simulated in Verilog-HDL and synthesized for a clock period of $ 1.4 $ ns using Synopsys. The time and area complexities are truly linear, since no carry propagation structures are present, and the complexity measures are equivalent or excel the best designs proposed so far.

rawabstract:
A unidirectional bit serial systolic architecture for division over Galois field $ \mathrm {GF}(2^m) $ is presented which uses both triangular and polynomial basis representations. It is suitable for hardware implementations where the dimension of the field is large and may vary. This is the typical case for cryptographic applications. This architecture is simulated in Verilog-HDL and synthesized for a clock period of $ 1.4 $ ns using Synopsys. The time and area complexities are truly linear, since no carry propagation structures are present, and the complexity measures are equivalent or excel the best designs proposed so far.

rawtitle:
A unidirectional bit serial systolic architecture for double-basis division over {$ \mathrm {GF}(2^m) $}

entry:
@InProceedings{Daneshbeh:2003:UBS,
  author =       "Amir.K. Daneshbeh and M. A. Hasan",
  title =        "A unidirectional bit serial systolic architecture for
                 double-basis division over {$ \mathrm {GF}(2^m) $}",
  crossref =     "Bajard:2003:ISC",
  pages =        "174--180",
  year =         "2003",
  bibdate =      "Wed Nov 26 12:04:35 MST 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Daneshbeh.pdf",
  abstract =     "A unidirectional bit serial systolic architecture for
                 division over Galois field $ \mathrm {GF}(2^m) $ is
                 presented which uses both triangular and polynomial
                 basis representations. It is suitable for hardware
                 implementations where the dimension of the field is
                 large and may vary. This is the typical case for
                 cryptographic applications. This architecture is
                 simulated in Verilog-HDL and synthesized for a clock
                 period of $ 1.4 $ ns using Synopsys. The time and area
                 complexities are truly linear, since no carry
                 propagation structures are present, and the complexity
                 measures are equivalent or excel the best designs
                 proposed so far.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-16",
}


bibtype: article
filename: fparith.bib
label: Daumas:2003:FRR
author: Marc Daumas and David W. Matula
title: Further Reducing the Redundancy of a Notation Over a Minimally Redundant Digit Set
journal: j-J-VLSI-SIGNAL-PROC
volume: 33
number: 1--2
pages: 7--18
month: jan
monthnumber: 1
year: 2003
CODEN: JVSPED
DOI: https://doi.org/10.1023/A:1021133616373
ISSN: 0922-5773 (print), 1573-109x (electronic) OR 09225773 (print), 1573109x (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Tue Nov 27 14:14:52 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.27 14:14:52 ???
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
rawauthor: Marc Daumas and David W. Matula
rawtitle: Further Reducing the Redundancy of a Notation Over a Minimally Redundant Digit Set
abstract:
Redundant notations are used implicitly or explicitly in many digital designs. They have been studied in details and a general framework is known to reduce the redundancy of a notation down to the minimally redundant digit set. We present here an operator to further reduce the redundancy of such a representation. It does not reduce the number of allowed digits since removing one digit to a minimally redundant digit set is a conversion to a non redundant digit set and this is an expensive operation. Our operator introduces some correlation between the digits to reduce the number of possible redundant notations for any represented number. This reduction is visible in small useful operators like the elimination of leading zeros. We also present a key application with a CMOS Booth recoded multiplier. Our multiplier is able to accept both a redundant or a non redundant input with very little modifications and almost no penalty in time or space compared to state-of-the-art non redundant multipliers.

rawabstract:
Redundant notations are used implicitly or explicitly in many digital designs. They have been studied in details and a general framework is known to reduce the redundancy of a notation down to the minimally redundant digit set. We present here an operator to further reduce the redundancy of such a representation. It does not reduce the number of allowed digits since removing one digit to a minimally redundant digit set is a conversion to a non redundant digit set and this is an expensive operation. Our operator introduces some correlation between the digits to reduce the number of possible redundant notations for any represented number. This reduction is visible in small useful operators like the elimination of leading zeros. We also present a key application with a CMOS Booth recoded multiplier. Our multiplier is able to accept both a redundant or a non redundant input with very little modifications and almost no penalty in time or space compared to state-of-the-art non redundant multipliers.

entry:
@Article{Daumas:2003:FRR,
  author =       "Marc Daumas and David W. Matula",
  title =        "Further Reducing the Redundancy of a Notation Over a
                 Minimally Redundant Digit Set",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "33",
  number =       "1--2",
  pages =        "7--18",
  month =        jan,
  year =         "2003",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1023/A:1021133616373",
  ISSN =         "0922-5773 (print), 1573-109x (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Tue Nov 27 14:14:52 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Redundant notations are used implicitly or explicitly
                 in many digital designs. They have been studied in
                 details and a general framework is known to reduce the
                 redundancy of a notation down to the minimally
                 redundant digit set. We present here an operator to
                 further reduce the redundancy of such a representation.
                 It does not reduce the number of allowed digits since
                 removing one digit to a minimally redundant digit set
                 is a conversion to a non redundant digit set and this
                 is an expensive operation. Our operator introduces some
                 correlation between the digits to reduce the number of
                 possible redundant notations for any represented
                 number. This reduction is visible in small useful
                 operators like the elimination of leading zeros. We
                 also present a key application with a CMOS Booth
                 recoded multiplier. Our multiplier is able to accept
                 both a redundant or a non redundant input with very
                 little modifications and almost no penalty in time or
                 space compared to state-of-the-art non redundant
                 multipliers.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of VLSI Signal Processing",
}


bibtype: phdthesis
filename: fparith.bib
label: Defour:2003:FEA
author: David Defour
school: L'Ecole Normale Superieure de Lyon
address: Lyon, France
pages: viii + 133
day: 9
month: sep
monthnumber: 9
year: 2003
bibdate: Tue Dec 02 11:25:16 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.02 11:25:16 ???
keywords: correct rounding; floating-point arithmetic
language: French
acknowledgement: ack-nhfb
rawauthor: David Defour
title:
Fonctions Elementaires: Algorithmes et Implementations Efficaces pour l'Arrondi Correct en Double Precision. (French) [Elementary Functions: Efficient Algorithms and Implementations for Correct Rounding in Double Precision]

URL:
http://gala.univ-perp.fr/ddefour/research/thesis_dd.pdf; http://www.ens-lyon.fr/LIP/Pub/Rapports/PhD/PhD2003/PhD2003-01.ps.gz; https://theses.hal.science/tel-00006022v1

abstract:
The representation formats and behaviors of floating point arithmetics available in computers are defined by the IEEE-754 standard. This standard imposes the system to return as a result of one of the four basic operations (+, *, /, sqrt), the rounding of the exact result. This property is called <>,this warranties the quality of the result. It enables construction of proof that this particular algorithms can be manipulated independently of the machine. However, due to the <>, elementary functions (sine, cosine, exponential...) are absent in the IEEE-754 standard. Contrary to basic operations, it is difficult to discover the necessary accuracy required to guarantee correct rounding for elementary functions. However if the representation format is set, it is possible that an exhaustive search will help determine this bound: it was Lefevre's work for the double precision.par The objectives of this thesis is to exploit these bounds for each functions and rounding modes, to certify correct rounding in double precision. Thanks to this bound we have defined an evaluation within 2 steps: a quick phase which is based on the property of the IEEE standard that often proves satisfactory and an accurate step based on multiprecision operations which is precise all the time. For the second step we have designed a multiprecision library which was optimized in order to acquire precision corresponding to the bound, and the characteristics of processors in 2003.

rawabstract:
The representation formats and behaviors of floating point arithmetics available in computers are defined by the IEEE-754 standard. This standard imposes the system to return as a result of one of the four basic operations (+, *, /, sqrt), the rounding of the exact result. This property is called <>,this warranties the quality of the result. It enables construction of proof that this particular algorithms can be manipulated independently of the machine. However, due to the <>, elementary functions (sine, cosine, exponential...) are absent in the IEEE-754 standard. Contrary to basic operations, it is difficult to discover the necessary accuracy required to guarantee correct rounding for elementary functions. However if the representation format is set, it is possible that an exhaustive search will help determine this bound: it was Lef{\`e}vre's work for the double precision.\par The objectives of this thesis is to exploit these bounds for each functions and rounding modes, to certify correct rounding in double precision. Thanks to this bound we have defined an evaluation within 2 steps: a quick phase which is based on the property of the IEEE standard that often proves satisfactory and an accurate step based on multiprecision operations which is precise all the time. For the second step we have designed a multiprecision library which was optimized in order to acquire precision corresponding to the bound, and the characteristics of processors in 2003.

rawtitle:
Fonctions {{\'E}}l{\'e}mentaires: Algorithmes et Impl{\'e}mentations Efficaces pour {l'Arrondi} Correct en Double Pr{\'e}cision. ({French}) [{Elementary} Functions: Efficient Algorithms and Implementations for Correct Rounding in Double Precision]

entry:
@PhdThesis{Defour:2003:FEA,
  author =       "David Defour",
  title =        "Fonctions {{\'E}}l{\'e}mentaires: Algorithmes et
                 Impl{\'e}mentations Efficaces pour {l'Arrondi} Correct
                 en Double Pr{\'e}cision. ({French}) [{Elementary}
                 Functions: Efficient Algorithms and Implementations for
                 Correct Rounding in Double Precision]",
  school =       "L'{\'E}cole Normale Sup{\'e}rieure de Lyon",
  address =      "Lyon, France",
  pages =        "viii + 133",
  day =          "9",
  month =        sep,
  year =         "2003",
  bibdate =      "Tue Dec 02 11:25:16 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://gala.univ-perp.fr/ddefour/research/thesis_dd.pdf;
                 http://www.ens-lyon.fr/LIP/Pub/Rapports/PhD/PhD2003/PhD2003-01.ps.gz;
                 https://theses.hal.science/tel-00006022v1",
  abstract =     "The representation formats and behaviors of floating
                 point arithmetics available in computers are defined by
                 the IEEE-754 standard. This standard imposes the system
                 to return as a result of one of the four basic
                 operations (+, *, /, sqrt), the rounding of the exact
                 result. This property is called <>,this warranties the
                 quality of the result. It enables construction of proof
                 that this particular algorithms can be manipulated
                 independently of the machine. However, due to the <>,
                 elementary functions (sine, cosine, exponential...) are
                 absent in the IEEE-754 standard. Contrary to basic
                 operations, it is difficult to discover the necessary
                 accuracy required to guarantee correct rounding for
                 elementary functions. However if the representation
                 format is set, it is possible that an exhaustive search
                 will help determine this bound: it was Lef{\`e}vre's
                 work for the double precision.\par

                 The objectives of this thesis is to exploit these
                 bounds for each functions and rounding modes, to
                 certify correct rounding in double precision. Thanks to
                 this bound we have defined an evaluation within 2
                 steps: a quick phase which is based on the property of
                 the IEEE standard that often proves satisfactory and an
                 accurate step based on multiprecision operations which
                 is precise all the time. For the second step we have
                 designed a multiprecision library which was optimized
                 in order to acquire precision corresponding to the
                 bound, and the characteristics of processors in 2003.",
  acknowledgement = ack-nhfb,
  keywords =     "correct rounding; floating-point arithmetic",
  language =     "French",
}


bibtype: article
filename: fparith.bib
label: Demmel:2003:AEF
author: James Demmel and Yozo Hida
title: Accurate and Efficient Floating Point Summation
journal: j-SIAM-J-SCI-COMP
volume: 25
number: 4
pages: 1214--1248
day: 5
month: dec
monthnumber: 12
year: 2003
CODEN: SJOCE3
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
MRclass: 65G50 (65B10)
MRnumber: MR2045054 (2005b:65055)
bibdate: Mon Jan 12 19:00:46 MST 2004
bibsource: http://epubs.siam.org/sam-bin/dbq/toc/SISC/25/4; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.01.12 19:00:46 MST
URL: http://epubs.siam.org/sam-bin/dbq/article/40762
fjournal: SIAM Journal on Scientific Computing
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
rawauthor: James Demmel and Yozo Hida
rawtitle: Accurate and Efficient Floating Point Summation
abstract:
We present and analyze several simple algorithms for accurately computing the sum of $n$ floating point numbers using a wider accumulator. Let $f$ and $F$ be the number of significant bits in the summands and the accumulator, respectively. Then assuming gradual underflow, no overflow, and round-to-nearest arithmetic, up to approximately $ 2^F - f $ numbers can be added accurately by simply summing the terms in decreasing order of exponents, yielding a sum correct to within about $ 1.5 $ units in the last place (ulps). We apply this result to the floating point formats in the IEEE floating point standard. For example, a dot product of single precision vectors of length at most 33 computed using double precision and sorting is guaranteed correct to nearly 1.5 ulps. If double-extended precision is used, the vector length can be as large as 65,537. We also investigate how the cost of sorting can be reduced or eliminated while retaining accuracy.

rawabstract:
We present and analyze several simple algorithms for accurately computing the sum of $n$ floating point numbers using a wider accumulator. Let $f$ and $F$ be the number of significant bits in the summands and the accumulator, respectively. Then assuming gradual underflow, no overflow, and round-to-nearest arithmetic, up to approximately $ 2^{F - f} $ numbers can be added accurately by simply summing the terms in decreasing order of exponents, yielding a sum correct to within about $ 1.5 $ units in the last place (ulps). We apply this result to the floating point formats in the IEEE floating point standard. For example, a dot product of single precision vectors of length at most 33 computed using double precision and sorting is guaranteed correct to nearly 1.5 ulps. If double-extended precision is used, the vector length can be as large as 65,537. We also investigate how the cost of sorting can be reduced or eliminated while retaining accuracy.

entry:
@Article{Demmel:2003:AEF,
  author =       "James Demmel and Yozo Hida",
  title =        "Accurate and Efficient Floating Point Summation",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "25",
  number =       "4",
  pages =        "1214--1248",
  day =          "5",
  month =        dec,
  year =         "2003",
  CODEN =        "SJOCE3",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  MRclass =      "65G50 (65B10)",
  MRnumber =     "MR2045054 (2005b:65055)",
  bibdate =      "Mon Jan 12 19:00:46 MST 2004",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SISC/25/4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://epubs.siam.org/sam-bin/dbq/article/40762",
  abstract =     "We present and analyze several simple algorithms for
                 accurately computing the sum of $n$ floating point
                 numbers using a wider accumulator. Let $f$ and $F$ be
                 the number of significant bits in the summands and the
                 accumulator, respectively. Then assuming gradual
                 underflow, no overflow, and round-to-nearest
                 arithmetic, up to approximately $ 2^{F - f} $ numbers
                 can be added accurately by simply summing the terms in
                 decreasing order of exponents, yielding a sum correct
                 to within about $ 1.5 $ units in the last place (ulps).
                 We apply this result to the floating point formats in
                 the IEEE floating point standard. For example, a dot
                 product of single precision vectors of length at most
                 33 computed using double precision and sorting is
                 guaranteed correct to nearly 1.5 ulps. If
                 double-extended precision is used, the vector length
                 can be as large as 65,537. We also investigate how the
                 cost of sorting can be reduced or eliminated while
                 retaining accuracy.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "accurate floating-point summation",
}


bibtype: article
filename: fparith.bib
label: Demmel:2003:CAF
author: James Demmel
title: The complexity of accurate floating point computation
journal: arXiv.org
pages: ??--??
day: 1
month: may
monthnumber: 5
year: 2003
MRclass: 65F, 65G50, 65Y20, 68Q25
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
note: Published in Proceedings of the ICM, Beijing 2002, vol. 3, 697--706.
URL: http://arxiv.org/abs/math/0305004
subject: Numerical Analysis (math.NA)
acknowledgement: ack-nhfb
rawauthor: James Demmel
rawnote: Published in Proceedings of the ICM, Beijing 2002, vol. 3, 697--706.
rawtitle: The complexity of accurate floating point computation
abstract:
Our goal is to find accurate and efficient algorithms, when they exist, for evaluating rational expressions containing floating point numbers, and for computing matrix factorizations (like LU and the SVD) of matrices with rational expressions as entries. More precisely, em accuracy means the relative error in the output must be less than one (no matter how tiny the output is), and em efficiency means that the algorithm runs in polynomial time. Our goal is challenging because our accuracy demand is much stricter than usual.

rawabstract:
Our goal is to find accurate and efficient algorithms, when they exist, for evaluating rational expressions containing floating point numbers, and for computing matrix factorizations (like LU and the SVD) of matrices with rational expressions as entries. More precisely, {\em accuracy} means the relative error in the output must be less than one (no matter how tiny the output is), and {\em efficiency} means that the algorithm runs in polynomial time. Our goal is challenging because our accuracy demand is much stricter than usual.

entry:
@Article{Demmel:2003:CAF,
  author =       "James Demmel",
  title =        "The complexity of accurate floating point
                 computation",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "1",
  month =        may,
  year =         "2003",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  MRclass =      "65F, 65G50, 65Y20, 68Q25",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Published in Proceedings of the ICM, Beijing 2002,
                 vol. 3, 697--706.",
  URL =          "http://arxiv.org/abs/math/0305004",
  abstract =     "Our goal is to find accurate and efficient algorithms,
                 when they exist, for evaluating rational expressions
                 containing floating point numbers, and for computing
                 matrix factorizations (like LU and the SVD) of matrices
                 with rational expressions as entries. More precisely,
                 {\em accuracy} means the relative error in the output
                 must be less than one (no matter how tiny the output
                 is), and {\em efficiency} means that the algorithm runs
                 in polynomial time. Our goal is challenging because our
                 accuracy demand is much stricter than usual.",
  acknowledgement = ack-nhfb,
  subject =      "Numerical Analysis (math.NA)",
}


bibtype: techreport
filename: fparith.bib
label: Deshmukh:2003:HPS
author: R. G. Deshmukh and Hatim Ghazi Zaini
title: High performance signal processing through computational enhancement and hardware integration
institution: Florida Institute of Technology
address: Melbourne, FL, USA
pages: 320
year: 2003
bibdate: Thu Aug 07 18:49:39 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 18:49:39 ???
note: Order Number AAI3099386.
keywords: decimal arithmetic
acknowledgement: ack-nhfb
rawauthor: R. G. Deshmukh and Hatim Ghazi Zaini
rawnote: Order Number AAI3099386.
rawtitle: High performance signal processing through computational enhancement and hardware integration
abstract:
Mathematical operations on complex numbers are commonly required in numerous computer applications. The use of complex number computations in the design algorithms for various digital signal processing (DSP) has received considerable attention in recent years. Algorithms in complex orthogonal transformations, correlations, and filtrations are a part of arithmetic computations such as geometric analysis in graphics or signal processing. The digital signal processing algorithms and modern digital communication systems such as equalization, modulation and demodulation are all deal with data streams represented by complex numbers. These applications require efficient representation and manipulation, in addition to treatment of complex numbers. These algorithms usually include arithmetic operations. The digital signal processing demands always increase and higher performance in the implementation of algorithms are investigated. Therefore, the implementations of the arithmetic operations of the complex numbers for high-performance especially for complex number multiplier are of significant interest.par A novel method for complex numbers representation and the arithmetic operations on them was introduced for computer vision which is a relatively new area. The proposed Redundant Complex Binary Number System (RCBNS) was developed by combining a Redundant Binary Number and a complex number in the base $ ( - 1 + j) $.par A Redundant Complex Binary Number System consists of both the real and the imaginary parts presented by a radix number system that forms a single redundant integer digit set. This system is formed by using complex radix of $ ( - 1 + j) $ and a digit set of $ alpha = 3 $, where $ alpha $ assumes a value of $ - 3, - 2, - 1, 0, 1, 2, 3 $. The arithmetic operations on these complex numbers treat the real and the imaginary parts as one unit. Carry-free addition is the advantage in the arithmetic operations that uses operands in the Redundant Complex Binary Number System.par Conversion of decimal complex numbers in the standard binary form to the RCBNS form is accomplished by converting the decimal complex number to the complex binary form and then the real part and the imaginary part to be treated in one unit. Two methods for the conversion to the RCBNS form are presented. These complex numbers in the RCBNS form are used to perform arithmetic operations, addition, subtraction, multiplication and division. The results of arithmetic operations on complex number are available in the RCBNS form. These results in the RCBNS form should be converted back to the Standard Binary Number form. Two methods are presented for the reconversion. Both methods are based on separating the real part and the imaginary part of each row of four digit positions of the RCBNS number and forward them to two dedicated registers. The comparisons of the proposed multiplier with other existing multipliers were done. Finally, methodology and processes of the proposed work were modeled (functional and behavioral) using a hardware description language, VHDL. In this research, the RCBNS form for complex number reduces the number of steps required to perform complex number arithmetic operations, thus enhancing the speed.

rawabstract:
Mathematical operations on complex numbers are commonly required in numerous computer applications. The use of complex number computations in the design algorithms for various digital signal processing (DSP) has received considerable attention in recent years. Algorithms in complex orthogonal transformations, correlations, and filtrations are a part of arithmetic computations such as geometric analysis in graphics or signal processing. The digital signal processing algorithms and modern digital communication systems such as equalization, modulation and demodulation are all deal with data streams represented by complex numbers. These applications require efficient representation and manipulation, in addition to treatment of complex numbers. These algorithms usually include arithmetic operations. The digital signal processing demands always increase and higher performance in the implementation of algorithms are investigated. Therefore, the implementations of the arithmetic operations of the complex numbers for high-performance especially for complex number multiplier are of significant interest.\par A novel method for complex numbers representation and the arithmetic operations on them was introduced for computer vision which is a relatively new area. The proposed Redundant Complex Binary Number System (RCBNS) was developed by combining a Redundant Binary Number and a complex number in the base $ ( - 1 + j) $.\par A Redundant Complex Binary Number System consists of both the real and the imaginary parts presented by a radix number system that forms a single redundant integer digit set. This system is formed by using complex radix of $ ( - 1 + j) $ and a digit set of $ \alpha = 3 $, where $ \alpha $ assumes a value of $ - 3, - 2, - 1, 0, 1, 2, 3 $. The arithmetic operations on these complex numbers treat the real and the imaginary parts as one unit. Carry-free addition is the advantage in the arithmetic operations that uses operands in the Redundant Complex Binary Number System.\par Conversion of decimal complex numbers in the standard binary form to the RCBNS form is accomplished by converting the decimal complex number to the complex binary form and then the real part and the imaginary part to be treated in one unit. Two methods for the conversion to the RCBNS form are presented. These complex numbers in the RCBNS form are used to perform arithmetic operations, addition, subtraction, multiplication and division. The results of arithmetic operations on complex number are available in the RCBNS form. These results in the RCBNS form should be converted back to the Standard Binary Number form. Two methods are presented for the reconversion. Both methods are based on separating the real part and the imaginary part of each row of four digit positions of the RCBNS number and forward them to two dedicated registers. The comparisons of the proposed multiplier with other existing multipliers were done. Finally, methodology and processes of the proposed work were modeled (functional and behavioral) using a hardware description language, VHDL. In this research, the RCBNS form for complex number reduces the number of steps required to perform complex number arithmetic operations, thus enhancing the speed.

entry:
@TechReport{Deshmukh:2003:HPS,
  author =       "R. G. Deshmukh and Hatim Ghazi Zaini",
  title =        "High performance signal processing through
                 computational enhancement and hardware integration",
  institution =  "Florida Institute of Technology",
  address =      "Melbourne, FL, USA",
  pages =        "320",
  year =         "2003",
  bibdate =      "Thu Aug 07 18:49:39 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Order Number AAI3099386.",
  abstract =     "Mathematical operations on complex numbers are
                 commonly required in numerous computer applications.
                 The use of complex number computations in the design
                 algorithms for various digital signal processing (DSP)
                 has received considerable attention in recent years.
                 Algorithms in complex orthogonal transformations,
                 correlations, and filtrations are a part of arithmetic
                 computations such as geometric analysis in graphics or
                 signal processing. The digital signal processing
                 algorithms and modern digital communication systems
                 such as equalization, modulation and demodulation are
                 all deal with data streams represented by complex
                 numbers. These applications require efficient
                 representation and manipulation, in addition to
                 treatment of complex numbers. These algorithms usually
                 include arithmetic operations. The digital signal
                 processing demands always increase and higher
                 performance in the implementation of algorithms are
                 investigated. Therefore, the implementations of the
                 arithmetic operations of the complex numbers for
                 high-performance especially for complex number
                 multiplier are of significant interest.\par

                 A novel method for complex numbers representation and
                 the arithmetic operations on them was introduced for
                 computer vision which is a relatively new area. The
                 proposed Redundant Complex Binary Number System (RCBNS)
                 was developed by combining a Redundant Binary Number
                 and a complex number in the base $ ( - 1 + j) $.\par

                 A Redundant Complex Binary Number System consists of
                 both the real and the imaginary parts presented by a
                 radix number system that forms a single redundant
                 integer digit set. This system is formed by using
                 complex radix of $ ( - 1 + j) $ and a digit set of $
                 \alpha = 3 $, where $ \alpha $ assumes a value of $ -
                 3, - 2, - 1, 0, 1, 2, 3 $. The arithmetic operations on
                 these complex numbers treat the real and the imaginary
                 parts as one unit. Carry-free addition is the advantage
                 in the arithmetic operations that uses operands in the
                 Redundant Complex Binary Number System.\par

                 Conversion of decimal complex numbers in the standard
                 binary form to the RCBNS form is accomplished by
                 converting the decimal complex number to the complex
                 binary form and then the real part and the imaginary
                 part to be treated in one unit. Two methods for the
                 conversion to the RCBNS form are presented. These
                 complex numbers in the RCBNS form are used to perform
                 arithmetic operations, addition, subtraction,
                 multiplication and division. The results of arithmetic
                 operations on complex number are available in the RCBNS
                 form. These results in the RCBNS form should be
                 converted back to the Standard Binary Number form. Two
                 methods are presented for the reconversion. Both
                 methods are based on separating the real part and the
                 imaginary part of each row of four digit positions of
                 the RCBNS number and forward them to two dedicated
                 registers. The comparisons of the proposed multiplier
                 with other existing multipliers were done. Finally,
                 methodology and processes of the proposed work were
                 modeled (functional and behavioral) using a hardware
                 description language, VHDL. In this research, the RCBNS
                 form for complex number reduces the number of steps
                 required to perform complex number arithmetic
                 operations, thus enhancing the speed.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Detrey:2003:VLL
author: Jeremie Detrey and Florent de Dinechim
title: A VHDL Library of LNS Operators
crossref: Matthews:2003:PTS
pages: 2227--2231
year: 2003
bibdate: Sat Jul 16 16:14:38 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 16:14:38 MDT
keywords: logarithmic number system (LNS)
acknowledgement: ack-nhfb
rawauthor: J{\'e}r{\'e}mie Detrey and Florent de Dinechim
rawtitle: A {VHDL} Library of {LNS} Operators
URL:
http://perso.ens-lyon.fr/jeremie.detrey/FPLibrary/; http://perso.ens-lyon.fr/jeremie.detrey/publications/DetDin2003:asilomar.pdf

entry:
@InProceedings{Detrey:2003:VLL,
  author =       "J{\'e}r{\'e}mie Detrey and Florent de Dinechim",
  title =        "A {VHDL} Library of {LNS} Operators",
  crossref =     "Matthews:2003:PTS",
  pages =        "2227--2231",
  year =         "2003",
  bibdate =      "Sat Jul 16 16:14:38 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://perso.ens-lyon.fr/jeremie.detrey/FPLibrary/;
                 http://perso.ens-lyon.fr/jeremie.detrey/publications/DetDin2003:asilomar.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "logarithmic number system (LNS)",
  summary =      "Not \ldots{}",
}


bibtype: misc
filename: fparith.bib
label: DiBrino:2003:FPP
author: M. DiBrino and F. Karim
title: Floating-point pipeline with leading zeros anticipator circuit
pages: 2227--2231
month: apr
monthnumber: 4
year: 2003
bibdate: Fri Jun 24 10:46:57 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.24 10:46:57 ???
acknowledgement: ack-nhfb
howpublished: US Patent 6542915
rawauthor: M. DiBrino and F. Karim
rawtitle: Floating-point pipeline with leading zeros anticipator circuit
entry:
@Misc{DiBrino:2003:FPP,
  author =       "M. DiBrino and F. Karim",
  title =        "Floating-point pipeline with leading zeros anticipator
                 circuit",
  howpublished = "US Patent 6542915",
  month =        apr,
  year =         "2003",
  bibdate =      "Fri Jun 24 10:46:57 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Ercegovac:2003:CDP
author: Milos Ercegovac and Jean-Michel Muller
title: Complex Division with Prescaling of Operands
crossref: Deprettere:2003:IIC
pages: 304--314
year: 2003
DOI: https://doi.org/10.1109/ASAP.2003.1212854
bibdate: Sat Dec 04 09:09:15 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.12.04 09:09:15 ???
acknowledgement: ack-nhfb
rawauthor: Milo{\v{s}} Ercegovac and Jean-Michel Muller
rawtitle: Complex Division with Prescaling of Operands
abstract:
We adapt the radix-r digit-recurrence division algorithm to complex division. By prescaling the operands, we make the selection of quotient digits simple. This leads to a simple hardware implementation, and allows correct rounding of complex quotient. To reduce large prescaling tables required for radices greater than 4, we adapt the bipartite-table method to multiple-operand functions.

keywords:
bipartite-table method; complex division; correct rounding; digital arithmetic; floating-point arithmetic; multiple-operand function; number theory; prescaling table; quotient digit selection; radix-r digit-recurrence division algorithm; table lookup

rawabstract:
We adapt the radix-r digit-recurrence division algorithm to complex division. By prescaling the operands, we make the selection of quotient digits simple. This leads to a simple hardware implementation, and allows correct rounding of complex quotient. To reduce large prescaling tables required for radices greater than 4, we adapt the bipartite-table method to multiple-operand functions.

entry:
@InProceedings{Ercegovac:2003:CDP,
  author =       "Milo{\v{s}} Ercegovac and Jean-Michel Muller",
  title =        "Complex Division with Prescaling of Operands",
  crossref =     "Deprettere:2003:IIC",
  pages =        "304--314",
  year =         "2003",
  DOI =          "https://doi.org/10.1109/ASAP.2003.1212854",
  bibdate =      "Sat Dec 04 09:09:15 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We adapt the radix-r digit-recurrence division
                 algorithm to complex division. By prescaling the
                 operands, we make the selection of quotient digits
                 simple. This leads to a simple hardware implementation,
                 and allows correct rounding of complex quotient. To
                 reduce large prescaling tables required for radices
                 greater than 4, we adapt the bipartite-table method to
                 multiple-operand functions.",
  acknowledgement = ack-nhfb,
  keywords =     "bipartite-table method; complex division; correct
                 rounding; digital arithmetic; floating-point
                 arithmetic; multiple-operand function; number theory;
                 prescaling table; quotient digit selection; radix-r
                 digit-recurrence division algorithm; table lookup",
}


bibtype: inproceedings
filename: fparith.bib
label: Ercegovac:2003:DRA
author: M. D. Ercegovac and Jean-Michel Muller
booktitle: Conference Record of the Thirty-Seventh Asilomar Conference on Signals, Systems and Computers, 2003
title: Digit-recurrence algorithms for division and square root with limited precision primitives
volume: 2
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1440--1444
year: 2003
bibdate: Sat Jul 16 15:28:13 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 15:28:13 MDT
acknowledgement: ack-nhfb
rawauthor: M. D. Ercegovac and Jean-Michel Muller
rawbooktitle: Conference Record of the Thirty-Seventh Asilomar Conference on Signals, Systems and Computers, 2003
rawtitle: Digit-recurrence algorithms for division and square root with limited precision primitives
entry:
@InProceedings{Ercegovac:2003:DRA,
  author =       "M. D. Ercegovac and Jean-Michel Muller",
  booktitle =    "Conference Record of the Thirty-Seventh Asilomar
                 Conference on Signals, Systems and Computers, 2003",
  title =        "Digit-recurrence algorithms for division and square
                 root with limited precision primitives",
  volume =       "2",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1440--1444",
  year =         "2003",
  CODEN =        "????",
  ISSN =         "????",
  bibdate =      "Sat Jul 16 15:28:13 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "We propose a digit-recurrence algorithm for square
                 root using limited-precision multipliers, adders, and
                 table-lookups. The algorithm, except in the
                 initialization, uses the digit-recurrence algorithm for
                 division with limited-precision primitives \ldots{}",
}


bibtype: inproceedings
filename: fparith.bib
label: Erdem:2003:LRV
author: Serdar S. Erdem and Cetin K. Koc
crossref: Bajard:2003:ISC
pages: 28--35
year: 2003
bibdate: Wed Nov 26 11:59:51 MST 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.26 11:59:51 MST
URL: http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Erdem.pdf
keywords: ARITH-16
acknowledgement: ack-nhfb
rawauthor: Serdar S. Erdem and {\c{C}}etin K. Ko{\c{c}}
title:
A less recursive variant of Karatsuba--Ofman algorithm for multiplying operands of size a power of two

abstract:
We propose a new algorithm for fast multiplication of large integers having a precision of $ 2^k $ computer words, where $k$ is an integer. The algorithm is derived from the Karatsuba--Ofman Algorithm and has the same asymptotic complexity. However, the running time of the new algorithm is slightly better, and it makes one third as many recursive calls.

rawabstract:
We propose a new algorithm for fast multiplication of large integers having a precision of $ 2^k $ computer words, where $k$ is an integer. The algorithm is derived from the Karatsuba--Ofman Algorithm and has the same asymptotic complexity. However, the running time of the new algorithm is slightly better, and it makes one third as many recursive calls.

rawtitle:
A less recursive variant of {Karatsuba--Ofman} algorithm for multiplying operands of size a power of two

entry:
@InProceedings{Erdem:2003:LRV,
  author =       "Serdar S. Erdem and {\c{C}}etin K. Ko{\c{c}}",
  title =        "A less recursive variant of {Karatsuba--Ofman}
                 algorithm for multiplying operands of size a power of
                 two",
  crossref =     "Bajard:2003:ISC",
  pages =        "28--35",
  year =         "2003",
  bibdate =      "Wed Nov 26 11:59:51 MST 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Erdem.pdf",
  abstract =     "We propose a new algorithm for fast multiplication of
                 large integers having a precision of $ 2^k $ computer
                 words, where $k$ is an integer. The algorithm is
                 derived from the Karatsuba--Ofman Algorithm and has the
                 same asymptotic complexity. However, the running time
                 of the new algorithm is slightly better, and it makes
                 one third as many recursive calls.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-16",
}


bibtype: inproceedings
filename: fparith.bib
label: Erle:2003:DMC
author: M. A. Erle and M. J. Schulte
title: Decimal multiplication via carry-save addition
crossref: Deprettere:2003:IIC
pages: 348--358
year: 2003
bibdate: Fri Mar 25 05:52:41 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.03.25 05:52:41 ???
URL: http://mesa.ece.wisc.edu/publications/cp_2003-03.pdf
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: M. A. Erle and M. J. Schulte
rawtitle: Decimal multiplication via carry-save addition
abstract:
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents two novel designs for fixed-point decimal multiplication that utilize decimal carry-save addition to reduce the critical path delay. First, a multiplier that stores a reduced number of multiplicand multiples and uses decimal carry-save addition in the iterative portion of the design is presented. Then, a second multiplier design is proposed with several notable improvements including fast generation of multiplicand multiples that do not need to be stored, the use of decimal (4:2) compressors, and a simplified decimal carry-propagate addition to produce the final product. When multiplying two $n$-digit operands to produce a $ 2 n $-digit product, the improved multiplier design has a worst-case latency of $ n + 4 $ cycles and an initiation interval of $ n + 1 $ cycles. Three data-dependent optimizations, which help reduce the multipliers' average latency, are also described. The multipliers presented can be extended to support decimal floating-point multiplication.

rawabstract:
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents two novel designs for fixed-point decimal multiplication that utilize decimal carry-save addition to reduce the critical path delay. First, a multiplier that stores a reduced number of multiplicand multiples and uses decimal carry-save addition in the iterative portion of the design is presented. Then, a second multiplier design is proposed with several notable improvements including fast generation of multiplicand multiples that do not need to be stored, the use of decimal (4:2) compressors, and a simplified decimal carry-propagate addition to produce the final product. When multiplying two $n$-digit operands to produce a $ 2 n $-digit product, the improved multiplier design has a worst-case latency of $ n + 4 $ cycles and an initiation interval of $ n + 1 $ cycles. Three data-dependent optimizations, which help reduce the multipliers' average latency, are also described. The multipliers presented can be extended to support decimal floating-point multiplication.

entry:
@InProceedings{Erle:2003:DMC,
  author =       "M. A. Erle and M. J. Schulte",
  title =        "Decimal multiplication via carry-save addition",
  crossref =     "Deprettere:2003:IIC",
  pages =        "348--358",
  year =         "2003",
  bibdate =      "Fri Mar 25 05:52:41 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://mesa.ece.wisc.edu/publications/cp_2003-03.pdf",
  abstract =     "Decimal multiplication is important in many commercial
                 applications including financial analysis, banking, tax
                 calculation, currency conversion, insurance, and
                 accounting. This paper presents two novel designs for
                 fixed-point decimal multiplication that utilize decimal
                 carry-save addition to reduce the critical path delay.
                 First, a multiplier that stores a reduced number of
                 multiplicand multiples and uses decimal carry-save
                 addition in the iterative portion of the design is
                 presented. Then, a second multiplier design is proposed
                 with several notable improvements including fast
                 generation of multiplicand multiples that do not need
                 to be stored, the use of decimal (4:2) compressors, and
                 a simplified decimal carry-propagate addition to
                 produce the final product. When multiplying two
                 $n$-digit operands to produce a $ 2 n $-digit product,
                 the improved multiplier design has a worst-case latency
                 of $ n + 4 $ cycles and an initiation interval of $ n +
                 1 $ cycles. Three data-dependent optimizations, which
                 help reduce the multipliers' average latency, are also
                 described. The multipliers presented can be extended to
                 support decimal floating-point multiplication.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Even:2003:PEA
author: Guy Even and Peter-Michael Seidel and Warren E. Ferguson
title: A parametric error analysis of Goldschmidt's division algorithm
crossref: Bajard:2003:ISC
pages: 165--171
year: 2003
bibdate: Wed Nov 26 12:04:35 MST 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.26 12:04:35 MST
URL: http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Even.pdf
keywords: ARITH-16; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Guy Even and Peter-Michael Seidel and Warren E. Ferguson
rawtitle: A parametric error analysis of {Goldschmidt}'s division algorithm
abstract:
Back in the 60's Goldschmidt presented a variation of Newton--Raphson iterations for division that is well suited for pipelining. The problem in using Goldschmidt's division algorithm is to present an error analysis that enables one to save hardware by using just the right amount of precision for intermediate calculations while still providing correct rounding. Previous implementations relied on combining formal proof methods (that span thousands of lines) with millions of test vectors. These techniques yield correct designs but the analysis is hard to follow and is not quite tight.par We present a simple parametric error analysis of Goldschmidt's division algorithm. This analysis sheds more light on the effect of the different parameters on the error. In addition, we derive closed error formulae that allow to determine optimal parameter choices in four practical settings.par We apply our analysis to show that a few bits of precision can be saved in the floating-point division (FP-DIV) microarchitecture of the AMD-K7TM microprocessor. These reductions in precision apply to the initial approximation and to the lengths of the multiplicands in the multiplier. When translated to cost, the reductions reflect a savings of $ 10.6 % $ in the overall cost of the FP-DIV micro-architecture.

rawabstract:
Back in the 60's Goldschmidt presented a variation of Newton--Raphson iterations for division that is well suited for pipelining. The problem in using Goldschmidt's division algorithm is to present an error analysis that enables one to save hardware by using just the right amount of precision for intermediate calculations while still providing correct rounding. Previous implementations relied on combining formal proof methods (that span thousands of lines) with millions of test vectors. These techniques yield correct designs but the analysis is hard to follow and is not quite tight.\par We present a simple parametric error analysis of Goldschmidt's division algorithm. This analysis sheds more light on the effect of the different parameters on the error. In addition, we derive closed error formulae that allow to determine optimal parameter choices in four practical settings.\par We apply our analysis to show that a few bits of precision can be saved in the floating-point division (FP-DIV) microarchitecture of the AMD-K7TM microprocessor. These reductions in precision apply to the initial approximation and to the lengths of the multiplicands in the multiplier. When translated to cost, the reductions reflect a savings of $ 10.6 \% $ in the overall cost of the FP-DIV micro-architecture.

entry:
@InProceedings{Even:2003:PEA,
  author =       "Guy Even and Peter-Michael Seidel and Warren E.
                 Ferguson",
  title =        "A parametric error analysis of {Goldschmidt}'s
                 division algorithm",
  crossref =     "Bajard:2003:ISC",
  pages =        "165--171",
  year =         "2003",
  bibdate =      "Wed Nov 26 12:04:35 MST 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Even.pdf",
  abstract =     "Back in the 60's Goldschmidt presented a variation of
                 Newton--Raphson iterations for division that is well
                 suited for pipelining. The problem in using
                 Goldschmidt's division algorithm is to present an error
                 analysis that enables one to save hardware by using
                 just the right amount of precision for intermediate
                 calculations while still providing correct rounding.
                 Previous implementations relied on combining formal
                 proof methods (that span thousands of lines) with
                 millions of test vectors. These techniques yield
                 correct designs but the analysis is hard to follow and
                 is not quite tight.\par

                 We present a simple parametric error analysis of
                 Goldschmidt's division algorithm. This analysis sheds
                 more light on the effect of the different parameters on
                 the error. In addition, we derive closed error formulae
                 that allow to determine optimal parameter choices in
                 four practical settings.\par

                 We apply our analysis to show that a few bits of
                 precision can be saved in the floating-point division
                 (FP-DIV) microarchitecture of the AMD-K7TM
                 microprocessor. These reductions in precision apply to
                 the initial approximation and to the lengths of the
                 multiplicands in the multiplier. When translated to
                 cost, the reductions reflect a savings of $ 10.6 \% $
                 in the overall cost of the FP-DIV micro-architecture.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-16; correct rounding; floating-point
                 arithmetic",
}


bibtype: inproceedings
filename: fparith.bib
label: Even:2003:PMD
author: G. Even and P.-M. Seidel
booktitle: Proceedings of the 21st International Conference on Computer Design
title: Pipelined multiplicative division with IEEE rounding
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 240--245
year: 2003
DOI: https://doi.org/10.1109/ICCD.2003.1240901
ISBN: 0-7695-2025-1 OR 0769520251
ISBN13: 978-0-7695-2025-4 OR 9780769520254
ISSN: 1063-6404 OR 10636404
ISSNL: 1063-6404 OR 10636404
bibdate: Sat Jul 16 11:25:05 MDT 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.07.16 11:25:05 MDT
acknowledgement: ack-nhfb
rawauthor: G. Even and P.-M. Seidel
rawbooktitle: Proceedings of the 21st International Conference on Computer Design
rawtitle: Pipelined multiplicative division with {IEEE} rounding
entry:
@InProceedings{Even:2003:PMD,
  author =       "G. Even and P.-M. Seidel",
  booktitle =    "Proceedings of the 21st International Conference on
                 Computer Design",
  title =        "Pipelined multiplicative division with {IEEE}
                 rounding",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "240--245",
  year =         "2003",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICCD.2003.1240901",
  ISBN =         "0-7695-2025-1",
  ISBN-13 =      "978-0-7695-2025-4",
  ISSN =         "1063-6404",
  ISSN-L =       "1063-6404",
  bibdate =      "Sat Jul 16 11:25:05 MDT 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  summary =      "We propose optimized pipelined implementations for
                 Goldschmidt's division algorithm with IEEE rounding
                 based on Booth radix-8 multiplication. Compared to
                 other FP-division algorithms, our implementations
                 require fewer clock cycles and admit shorter periods.
                 The considered optimizations for the quotient
                 approximation are based on a careful general analysis
                 of tight error bounds for the implementation and are
                 accompanied by the utilization of redundant
                 representations, partial compressions, injection-based
                 rounding, and rectangular multipliers for the internal
                 computations. To efficiently achieve IEEE compliant
                 rounding, we introduce the concept of dew-point
                 rounding that allows efficient implementation and
                 reduced requirements for the quotient approximation. On
                 this basis, we propose the implementation of different
                 versions of Goldschmidt's division algorithm with
                 different pipeline depths. None of these
                 implementations requires a full-sized multiplier at any
                 stage of the computations. In this way we reduce
                 latency, cost, and enable increased throughput at a
                 reasonable cost. We suggest a full range of pipelining
                 depths: On one extreme is a 3-stage pipeline with a
                 restart time that simply equals the latency minus the
                 number of pipeline stages. On the other extreme is a
                 fully pipelined design.",
}


bibtype: inproceedings
filename: fparith.bib
label: Fahmy:2003:CRF
author: Hossam A. H. Fahmy and Michael J. Flynn
title: The case for a redundant format in floating point arithmetic
crossref: Bajard:2003:ISC
pages: 95--102
year: 2003
bibdate: Wed Nov 26 11:59:51 MST 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.26 11:59:51 MST
URL: http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Fahmy.pdf
keywords: ARITH-16
acknowledgement: ack-nhfb
rawauthor: Hossam A. H. Fahmy and Michael J. Flynn
rawtitle: The case for a redundant format in floating point arithmetic
abstract:
This work uses a partially redundant number system as an internal format for floating point arithmetic operations. The redundant number system enables carry free arithmetic operations to improve performance. Conversion from the proposed internal format back to the standard IEEE format is done only when an operand is written to memory. A detailed discussion of an adder using the proposed format is presented and the specific challenges of the design are explained. A brief description of a multiplier and divider using the proposed format is also presented. The proposed internal format and arithmetic units comply with all the rounding modes of the IEEE 754 floating point standard. Transistor simulation of the adder and multiplier confirm the performance advantage predicted by the analytical model.

rawabstract:
This work uses a partially redundant number system as an internal format for floating point arithmetic operations. The redundant number system enables carry free arithmetic operations to improve performance. Conversion from the proposed internal format back to the standard IEEE format is done only when an operand is written to memory. A detailed discussion of an adder using the proposed format is presented and the specific challenges of the design are explained. A brief description of a multiplier and divider using the proposed format is also presented. The proposed internal format and arithmetic units comply with all the rounding modes of the IEEE 754 floating point standard. Transistor simulation of the adder and multiplier confirm the performance advantage predicted by the analytical model.

entry:
@InProceedings{Fahmy:2003:CRF,
  author =       "Hossam A. H. Fahmy and Michael J. Flynn",
  title =        "The case for a redundant format in floating point
                 arithmetic",
  crossref =     "Bajard:2003:ISC",
  pages =        "95--102",
  year =         "2003",
  bibdate =      "Wed Nov 26 11:59:51 MST 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Fahmy.pdf",
  abstract =     "This work uses a partially redundant number system as
                 an internal format for floating point arithmetic
                 operations. The redundant number system enables carry
                 free arithmetic operations to improve performance.
                 Conversion from the proposed internal format back to
                 the standard IEEE format is done only when an operand
                 is written to memory. A detailed discussion of an adder
                 using the proposed format is presented and the specific
                 challenges of the design are explained. A brief
                 description of a multiplier and divider using the
                 proposed format is also presented. The proposed
                 internal format and arithmetic units comply with all
                 the rounding modes of the IEEE 754 floating point
                 standard. Transistor simulation of the adder and
                 multiplier confirm the performance advantage predicted
                 by the analytical model.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-16",
}


bibtype: phdthesis
filename: fparith.bib
label: Fahmy:2003:RDF
author: Hossam A. H. Fahmy
title: A redundant digit floating point system
type: Ph.D. dissertation
school: Department of Computer Science, Stanford University
address: Stanford, CA, USA
pages: 146
month: nov
monthnumber: 11
year: 2003
bibdate: Wed Nov 15 07:59:18 2006
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2006.11.15 07:59:18 ???
URL: http://wwwlib.umi.com/dissertations/fullcit/3090583
acknowledgement: ack-nhfb
rawauthor: Hossam A. H. Fahmy
rawtitle: A redundant digit floating point system
abstract:
Arithmetic operations are among the most basic instructions in microprocessors, digital signal processors and graphics accelerators. Addition is the most frequent arithmetic operation in numerically intensive applications. Multiplication follows closely and then division and other elementary functions. The speed of those arithmetic operations is also often directly linked to the overall performance of the computers. The work presented in this thesis proposes several techniques to improve the effectiveness of floating point arithmetic units. A partially redundant number system is used as an internal format for floating point arithmetic operations. The redundant number system is based on signed digits and enables carry free arithmetic operations to improve the performance. Conversion from the proposed internal format back to the standard IEEE format is done only when an operand is written to memory. A detailed discussion of an adder and a multiplier using the proposed format is presented and the specific challenges of the designs are explained. Beside the redundancy, the proposed units include further enhancements that increase the floating point performance such as a hexadecimal based number format and a postponed rounding technique. A time delay model is developed and applied to analytically predict the performance of the floating point units. The predicted delays are then compared to state-of-the-art designs. The comparison is done over a range of operand widths, fan-in and radices to show the merits of each implementation. The proposed system achieves better performance for double precision and larger operand width. Transistor simulation of the complete adder and multiplier confirm the performance advantage predicted by the analytical model. A brief description of a divider using; the proposed format is also presented. The proposed internal format and arithmetic units comply with all the rounding modes of the IEEE 754 floating point standard.

rawabstract:
Arithmetic operations are among the most basic instructions in microprocessors, digital signal processors and graphics accelerators. Addition is the most frequent arithmetic operation in numerically intensive applications. Multiplication follows closely and then division and other elementary functions. The speed of those arithmetic operations is also often directly linked to the overall performance of the computers. The work presented in this thesis proposes several techniques to improve the effectiveness of floating point arithmetic units. A partially redundant number system is used as an internal format for floating point arithmetic operations. The redundant number system is based on signed digits and enables carry free arithmetic operations to improve the performance. Conversion from the proposed internal format back to the standard IEEE format is done only when an operand is written to memory. A detailed discussion of an adder and a multiplier using the proposed format is presented and the specific challenges of the designs are explained. Beside the redundancy, the proposed units include further enhancements that increase the floating point performance such as a hexadecimal based number format and a postponed rounding technique. A time delay model is developed and applied to analytically predict the performance of the floating point units. The predicted delays are then compared to state-of-the-art designs. The comparison is done over a range of operand widths, fan-in and radices to show the merits of each implementation. The proposed system achieves better performance for double precision and larger operand width. Transistor simulation of the complete adder and multiplier confirm the performance advantage predicted by the analytical model. A brief description of a divider using; the proposed format is also presented. The proposed internal format and arithmetic units comply with all the rounding modes of the IEEE 754 floating point standard.

entry:
@PhdThesis{Fahmy:2003:RDF,
  author =       "Hossam A. H. Fahmy",
  title =        "A redundant digit floating point system",
  type =         "{Ph.D.} dissertation",
  school =       "Department of Computer Science, Stanford University",
  address =      "Stanford, CA, USA",
  pages =        "146",
  month =        nov,
  year =         "2003",
  bibdate =      "Wed Nov 15 07:59:18 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://wwwlib.umi.com/dissertations/fullcit/3090583",
  abstract =     "Arithmetic operations are among the most basic
                 instructions in microprocessors, digital signal
                 processors and graphics accelerators. Addition is the
                 most frequent arithmetic operation in numerically
                 intensive applications. Multiplication follows closely
                 and then division and other elementary functions. The
                 speed of those arithmetic operations is also often
                 directly linked to the overall performance of the
                 computers. The work presented in this thesis proposes
                 several techniques to improve the effectiveness of
                 floating point arithmetic units. A partially redundant
                 number system is used as an internal format for
                 floating point arithmetic operations. The redundant
                 number system is based on signed digits and enables
                 carry free arithmetic operations to improve the
                 performance. Conversion from the proposed internal
                 format back to the standard IEEE format is done only
                 when an operand is written to memory. A detailed
                 discussion of an adder and a multiplier using the
                 proposed format is presented and the specific
                 challenges of the designs are explained. Beside the
                 redundancy, the proposed units include further
                 enhancements that increase the floating point
                 performance such as a hexadecimal based number format
                 and a postponed rounding technique. A time delay model
                 is developed and applied to analytically predict the
                 performance of the floating point units. The predicted
                 delays are then compared to state-of-the-art designs.
                 The comparison is done over a range of operand widths,
                 fan-in and radices to show the merits of each
                 implementation. The proposed system achieves better
                 performance for double precision and larger operand
                 width. Transistor simulation of the complete adder and
                 multiplier confirm the performance advantage predicted
                 by the analytical model. A brief description of a
                 divider using; the proposed format is also presented.
                 The proposed internal format and arithmetic units
                 comply with all the rounding modes of the IEEE 754
                 floating point standard.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Fang:2003:FPE
author: Claire Fang Fang and Tsuhan Chen and Rob A. Rutenbar
title: Floating-point error analysis based on affine arithmetic
crossref: IEEE:2003:IICa
pages: 561--564
year: 2003
DOI: https://doi.org/10.1109/ICASSP.2003.1202428
bibdate: Thu Mar 24 20:40:52 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.03.24 20:40:52 ???
URL: http://amp.ece.cmu.edu/Publication/Fang/icassp2003_fang.pdf
acknowledgement: ack-nhfb
rawauthor: Claire Fang Fang and Tsuhan Chen and Rob A. Rutenbar
rawtitle: Floating-point error analysis based on affine arithmetic
entry:
@InProceedings{Fang:2003:FPE,
  author =       "Claire Fang Fang and Tsuhan Chen and Rob A. Rutenbar",
  title =        "Floating-point error analysis based on affine
                 arithmetic",
  crossref =     "IEEE:2003:IICa",
  pages =        "561--564",
  year =         "2003",
  DOI =          "https://doi.org/10.1109/ICASSP.2003.1202428",
  bibdate =      "Thu Mar 24 20:40:52 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://amp.ece.cmu.edu/Publication/Fang/icassp2003_fang.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Fernandez:2003:FPA
author: Jose-Jesus Fernandez and Inmaculada Garcia and Ester M. Garzon
title: Floating point arithmetic teaching for computational science
journal: j-FUT-GEN-COMP-SYS
volume: 19
number: 8
pages: 1321--1334
month: nov
monthnumber: 11
year: 2003
CODEN: FGSEVI
ISSN: 0167-739X (print), 1872-7115 (electronic) OR 0167739X (print), 18727115 (electronic)
ISSNL: 0167-739X OR 0167739X
bibdate: Sat Jan 10 10:03:38 MST 2004
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2004.01.10 10:03:38 MST
fjournal: Future Generation Computer Systems
keywords: Computational science education; Computer arithmetic; Floating point computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/0167739X
rawauthor: Jos{\'e}-Jes{\'u}s Fern{\'a}ndez and Inmaculada Garc{\'\i}a and Ester M. Garz{\'o}n
rawtitle: Floating point arithmetic teaching for computational science
abstract:
Computational science is based upon numerical computing and, consequently, requires excellent knowledge of floating point computer arithmetic. In general, the average computational science student has a relatively limited understanding of the implications of floating point computation. This paper presents an initiative to teach floating point number representation and arithmetic in undergraduate courses in computational science. The approach is based on carefully designed practical exercises which highlight the main properties and computational issues of finite length number representation and arithmetic. In conjunction to the exercises, an auxiliary educational tool constitutes a valuable support for students to learn and understand the concepts involved. Simpler formats are used as an introduction to the IEEE 754 standard, with the aim of presenting the fundamentals of the floating point computation and emphasizing its limitations. This approach could be included in courses related to computer organization, programming, discrete mathematics, numerical methods or scientific computing in computational science curricula.

remark:
Selected papers from the Workshop on Education in Computational Sciences held at the International Conference on Computational Science.

rawabstract:
Computational science is based upon numerical computing and, consequently, requires excellent knowledge of floating point computer arithmetic. In general, the average computational science student has a relatively limited understanding of the implications of floating point computation. This paper presents an initiative to teach floating point number representation and arithmetic in undergraduate courses in computational science. The approach is based on carefully designed practical exercises which highlight the main properties and computational issues of finite length number representation and arithmetic. In conjunction to the exercises, an auxiliary educational tool constitutes a valuable support for students to learn and understand the concepts involved. Simpler formats are used as an introduction to the IEEE 754 standard, with the aim of presenting the fundamentals of the floating point computation and emphasizing its limitations. This approach could be included in courses related to computer organization, programming, discrete mathematics, numerical methods or scientific computing in computational science curricula.

entry:
@Article{Fernandez:2003:FPA,
  author =       "Jos{\'e}-Jes{\'u}s Fern{\'a}ndez and Inmaculada
                 Garc{\'\i}a and Ester M. Garz{\'o}n",
  title =        "Floating point arithmetic teaching for computational
                 science",
  journal =      j-FUT-GEN-COMP-SYS,
  volume =       "19",
  number =       "8",
  pages =        "1321--1334",
  month =        nov,
  year =         "2003",
  CODEN =        "FGSEVI",
  ISSN =         "0167-739X (print), 1872-7115 (electronic)",
  ISSN-L =       "0167-739X",
  bibdate =      "Sat Jan 10 10:03:38 MST 2004",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Computational science is based upon numerical
                 computing and, consequently, requires excellent
                 knowledge of floating point computer arithmetic. In
                 general, the average computational science student has
                 a relatively limited understanding of the implications
                 of floating point computation. This paper presents an
                 initiative to teach floating point number
                 representation and arithmetic in undergraduate courses
                 in computational science. The approach is based on
                 carefully designed practical exercises which highlight
                 the main properties and computational issues of finite
                 length number representation and arithmetic. In
                 conjunction to the exercises, an auxiliary educational
                 tool constitutes a valuable support for students to
                 learn and understand the concepts involved. Simpler
                 formats are used as an introduction to the IEEE 754
                 standard, with the aim of presenting the fundamentals
                 of the floating point computation and emphasizing its
                 limitations. This approach could be included in courses
                 related to computer organization, programming, discrete
                 mathematics, numerical methods or scientific computing
                 in computational science curricula.",
  acknowledgement = ack-nhfb,
  fjournal =     "Future Generation Computer Systems",
  journal-URL =  "http://www.sciencedirect.com/science/journal/0167739X",
  keywords =     "Computational science education; Computer arithmetic;
                 Floating point computation",
  remark =       "Selected papers from the Workshop on Education in
                 Computational Sciences held at the International
                 Conference on Computational Science.",
}


bibtype: inproceedings
filename: fparith.bib
label: Fousse:2003:AST
author: L. Fousse and P. Zimmermann
title: Accurate Summation: Towards a Simpler and Formal Proof
crossref: Anonymous:2003:CRN
pages: 97--108
year: 2003
bibdate: Sat Jun 25 14:56:11 2005
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2005.06.25 14:56:11 ???
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
rawauthor: L. Fousse and P. Zimmermann
rawtitle: Accurate Summation: Towards a Simpler and Formal Proof
entry:
@InProceedings{Fousse:2003:AST,
  author =       "L. Fousse and P. Zimmermann",
  title =        "Accurate Summation: Towards a Simpler and Formal
                 Proof",
  crossref =     "Anonymous:2003:CRN",
  pages =        "97--108",
  year =         "2003",
  bibdate =      "Sat Jun 25 14:56:11 2005",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation",
}


bibtype: inproceedings
filename: fparith.bib
label: Frougny:2003:LMR
author: Christiane Frougny and Athasit Surarerks
title: On-line multiplication in real and complex base
crossref: Bajard:2003:ISC
pages: 212--219
year: 2003
bibdate: Fri Nov 28 11:03:48 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.28 11:03:48 ???
URL: http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Frougny.pdf
keywords: ARITH-16
acknowledgement: ack-nhfb
rawauthor: Christiane Frougny and Athasit Surarerks
rawtitle: On-line multiplication in real and complex base
abstract:
Multiplication of two numbers represented in base $ beta $ is shown to be computable by an on-line algorithm when $ beta $ is a negative integer, a positive non-integer real number, or a complex number of the form $ i sqrt r $, where $r$ is a positive integer.

rawabstract:
Multiplication of two numbers represented in base $ \beta $ is shown to be computable by an on-line algorithm when $ \beta $ is a negative integer, a positive non-integer real number, or a complex number of the form $ i \sqrt {r} $, where $r$ is a positive integer.

entry:
@InProceedings{Frougny:2003:LMR,
  author =       "Christiane Frougny and Athasit Surarerks",
  title =        "On-line multiplication in real and complex base",
  crossref =     "Bajard:2003:ISC",
  pages =        "212--219",
  year =         "2003",
  bibdate =      "Fri Nov 28 11:03:48 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Frougny.pdf",
  abstract =     "Multiplication of two numbers represented in base $
                 \beta $ is shown to be computable by an on-line
                 algorithm when $ \beta $ is a negative integer, a
                 positive non-integer real number, or a complex number
                 of the form $ i \sqrt {r} $, where $r$ is a positive
                 integer.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-16",
}


bibtype: book
filename: fparith.bib
label: Gansner:2003:SMB
author: Emden R. Gansner and John H. Reppy
title: The Standard ML Basis Manual
publisher: pub-CAMBRIDGE
address: pub-CAMBRIDGE:adr
year: 2003
bibdate: Wed Jan 29 16:31:52 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.01.29 16:31:52 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Emden R. Gansner and John H. Reppy
rawtitle: The {Standard ML} Basis Manual
remark:
From cite Steele:2004:RHP: ``toDecimal should produce only as many digits as are necessary for fromDecimal to convert back to the same number, i.e., for any Normal or SubNormal real value r, we have: fromDecimal (toDecimal r) = r ldots Algorithms for accurately and efficiently converting between binary and decimal real representations are readily available, e.g., see the technical report cite Gay:1990:CRB.''

entry:
@Book{Gansner:2003:SMB,
  author =       "Emden R. Gansner and John H. Reppy",
  title =        "The {Standard ML} Basis Manual",
  publisher =    pub-CAMBRIDGE,
  address =      pub-CAMBRIDGE:adr,
  pages =        "????",
  year =         "2003",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Wed Jan 29 16:31:52 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
  remark =       "From \cite{Steele:2004:RHP}: ``toDecimal should
                 produce only as many digits as are necessary for
                 fromDecimal to convert back to the same number, i.e.,
                 for any Normal or SubNormal real value r, we have:
                 fromDecimal (toDecimal r) = r \ldots{} Algorithms for
                 accurately and efficiently converting between binary
                 and decimal real representations are readily available,
                 e.g., see the technical report \cite{Gay:1990:CRB}.''",
}


bibtype: incollection
filename: fparith.bib
label: Gavrilova:2003:ESC
author: M. L. Gavrilova
booktitle: Computational science and its applications---ICCSA 2003. Part III
volume: 2669
publisher: pub-SV
address: pub-SV:adr
pages: 827--835
year: 2003
MRclass: 68U05 (52B55)
MRnumber: MR2118360
bibdate: Thu Nov 8 19:16:14 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 19:16:14 ???
series: Lecture Notes in Computer Science
acknowledgement: ack-nhfb
rawauthor: M. L. Gavrilova
rawbooktitle: Computational science and its {applications---ICCSA 2003}. Part {III}
title:
An explicit solution for computing the Euclidean $d$-dimensional Voronoi diagram of spheres in a floating-point arithmetic

rawtitle:
An explicit solution for computing the {Euclidean} {$d$}-dimensional {Voronoi} diagram of spheres in a floating-point arithmetic

entry:
@InCollection{Gavrilova:2003:ESC,
  author =       "M. L. Gavrilova",
  booktitle =    "Computational science and its {applications---ICCSA
                 2003}. Part {III}",
  title =        "An explicit solution for computing the {Euclidean}
                 {$d$}-dimensional {Voronoi} diagram of spheres in a
                 floating-point arithmetic",
  volume =       "2669",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "827--835",
  year =         "2003",
  MRclass =      "68U05 (52B55)",
  MRnumber =     "MR2118360",
  bibdate =      "Thu Nov 8 19:16:14 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       "Lecture Notes in Computer Science",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Geddes:2003:EFH
author: Keith O. Geddes and Wei Wei Zheng
title: Exploiting fast hardware floating point in high precision computation
crossref: Senda:2003:IPI
pages: 111--118
year: 2003
DOI: https://doi.org/10.1145/860854.860886
MRclass: 65G99
MRnumber: MR2035201 (2005d:65074)
bibdate: Sat Dec 13 18:17:28 MST 2003
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.12.13 18:17:28 MST
acknowledgement: ack-nhfb
rawauthor: Keith O. Geddes and Wei Wei Zheng
rawtitle: Exploiting fast hardware floating point in high precision computation
abstract:
We apply an iterative refinement method based on a linear Newton iteration to solve a particular group of high precision computation problems. The method generates an initial solution at hardware floating point precision using a traditional method and then repeatedly refines this solution to higher precision, exploiting hardware floating point computation in each iteration. This is in contrast to direct solution of the high precision problem completely in software floating point. Theoretical cost analysis, as well as experimental evidence, shows a significant reduction in computational cost is achieved by the iterative refinement method on this group of problems.

rawabstract:
We apply an iterative refinement method based on a linear Newton iteration to solve a particular group of high precision computation problems. The method generates an initial solution at hardware floating point precision using a traditional method and then repeatedly refines this solution to higher precision, exploiting hardware floating point computation in each iteration. This is in contrast to direct solution of the high precision problem completely in software floating point. Theoretical cost analysis, as well as experimental evidence, shows a significant reduction in computational cost is achieved by the iterative refinement method on this group of problems.

entry:
@InProceedings{Geddes:2003:EFH,
  author =       "Keith O. Geddes and Wei Wei Zheng",
  title =        "Exploiting fast hardware floating point in high
                 precision computation",
  crossref =     "Senda:2003:IPI",
  pages =        "111--118",
  year =         "2003",
  DOI =          "https://doi.org/10.1145/860854.860886",
  MRclass =      "65G99",
  MRnumber =     "MR2035201 (2005d:65074)",
  bibdate =      "Sat Dec 13 18:17:28 MST 2003",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We apply an iterative refinement method based on a
                 linear Newton iteration to solve a particular group of
                 high precision computation problems. The method
                 generates an initial solution at hardware floating
                 point precision using a traditional method and then
                 repeatedly refines this solution to higher precision,
                 exploiting hardware floating point computation in each
                 iteration. This is in contrast to direct solution of
                 the high precision problem completely in software
                 floating point. Theoretical cost analysis, as well as
                 experimental evidence, shows a significant reduction in
                 computational cost is achieved by the iterative
                 refinement method on this group of problems.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Geiselmann:2003:RRD
author: W. Geiselmann and R. Steinwandt
title: A redundant representation of $ mathrm GF(q^n) $ for designing arithmetic circuits
journal: j-IEEE-TRANS-COMPUT
volume: 52
number: 7
pages: 848--853
month: jul
monthnumber: 7
year: 2003
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2003.1214334
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Jul 5 08:52:51 MDT 2011
bibtimestamp: 2011.07.05 08:52:51 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1214334
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: W. Geiselmann and R. Steinwandt
rawtitle: A redundant representation of {$ \mathrm {GF}(q^n) $} for designing arithmetic circuits
entry:
@Article{Geiselmann:2003:RRD,
  author =       "W. Geiselmann and R. Steinwandt",
  title =        "A redundant representation of {$ \mathrm {GF}(q^n) $}
                 for designing arithmetic circuits",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "52",
  number =       "7",
  pages =        "848--853",
  month =        jul,
  year =         "2003",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2003.1214334",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Jul 5 08:52:51 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1214334",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Gerwig:2003:HPF
author: Guenter Gerwig and Holger Wetter and Eric M. Schwarz and Juergen Haess
title: High performance floating-point unit with 116 bit wide divider
crossref: Bajard:2003:ISC
pages: 87--94
year: 2003
bibdate: Wed Nov 26 11:59:51 MST 2003
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2003.11.26 11:59:51 MST
URL: http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Gerwig.pdf
keywords: ARITH-16
acknowledgement: ack-nhfb
rawauthor: Guenter Gerwig and Holger Wetter and Eric M. Schwarz and Juergen Haess
rawtitle: High performance floating-point unit with 116 bit wide divider
abstract:
The next generation zSeries floating-point unit is unveiled which is the first IBM mainframe with a fused multiply-add dataflow. It supports both S/390 hexadecimal floating-point architecture and the IEEE 754 binary floating-point architecture which was first implemented in S/390 on the 1998 S/390 G5 floating-point unit. The new floating-point unit supports a total of 6 formats including single, double, and quadword formats implemented in hardware. The floating-point pipeline is 5 cycles with a throughput of 1 multiply-add per cycle. Both hexadecimal and binary floating-point instructions are capable of this performance due to a novel way of handling both formats. Other key developments include new methods for handling denormalized numbers and quad precision divide engine dataflow. This divider uses a radix-4 SRT algorithm and is able to handle quad precision divides in multiple floating-point and fixed-point formats. The number of iterations for fixed-point divisions depend on the effective number of quotient bits. It uses a reduced carry-save form for the partial remainder, with only 1 carry bit for every 4 sum bits, to save area and power.

rawabstract:
The next generation zSeries floating-point unit is unveiled which is the first IBM mainframe with a fused multiply-add dataflow. It supports both S/390 hexadecimal floating-point architecture and the IEEE 754 binary floating-point architecture which was first implemented in S/390 on the 1998 S/390 G5 floating-point unit. The new floating-point unit supports a total of 6 formats including single, double, and quadword formats implemented in hardware. The floating-point pipeline is 5 cycles with a throughput of 1 multiply-add per cycle. Both hexadecimal and binary floating-point instructions are capable of this performance due to a novel way of handling both formats. Other key developments include new methods for handling denormalized numbers and quad precision divide engine dataflow. This divider uses a radix-4 SRT algorithm and is able to handle quad precision divides in multiple floating-point and fixed-point formats. The number of iterations for fixed-point divisions depend on the effective number of quotient bits. It uses a reduced carry-save form for the partial remainder, with only 1 carry bit for every 4 sum bits, to save area and power.

entry:
@InProceedings{Gerwig:2003:HPF,
  author =       "Guenter Gerwig and Holger Wetter and Eric M. Schwarz
                 and Juergen Haess",
  title =        "High performance floating-point unit with 116 bit wide
                 divider",
  crossref =     "Bajard:2003:ISC",
  pages =        "87--94",
  year =         "2003",
  bibdate =      "Wed Nov 26 11:59:51 MST 2003",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.acsel-lab.com/arithmetic/arith16/papers/ARITH16_Gerwig.pdf",
  abstract =     "The next generation zSeries floating-point unit is
                 unveiled which is the first IBM mainframe with a fused
                 multiply-add dataflow. It supports both S/390
                 hexadecimal floating-point architecture and the IEEE
                 754 binary floating-point architecture which was first
                 implemented in S/390 on the 1998 S/390 G5
                 floating-point unit. The new floating-point unit
                 supports a total of 6 formats including single, double,
                 and quadword formats implemented in hardware. The
                 floating-point pipeline is 5 cycles with a throughput
                 of 1 multiply-add per cycle. Both hexadecimal and
                 binary floating-point instructions are capable of this
                 performance due to a novel way of handling both
                 formats. Other key developments include new methods for
                 handling denormalized numbers and quad precision divide
                 engine dataflow. This divider uses a radix-4 SRT
                 algorithm and is able to handle quad precision divides
                 in multiple floating-point and fixed-point formats. The
                 number of iterations for fixed-point divisions depend
                 on the effective number of quotient bits. It uses a
                 reduced carry-save form for the partial remainder, with
                 only 1 carry bit for every 4 sum bits, to save area and
                 power.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-16",
}


