# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Bocco:2019:BAF
booktitle: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
title: Byte-Aware Floating-point Operations through a UNUM Computing Unit
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 323--328
year: 2019
DOI: https://doi.org/10.1109/VLSI-SoC.2019.8920387
bibdate: Fri Dec 15 07:38:18 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 07:38:18 ???
acknowledgement: ack-nhfb
rawbooktitle: {2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)}
rawtitle: Byte-Aware Floating-point Operations through a {UNUM} Computing Unit
author:
Andrea Bocco and Tiago T. Jost and Albert Cohen and Florent de Dinechin and Yves Durand and Christian Fabre

rawauthor:
Andrea Bocco and Tiago T. Jost and Albert Cohen and Florent de Dinechin and Yves Durand and Christian Fabre

entry:
@InProceedings{Bocco:2019:BAF,
  author =       "Andrea Bocco and Tiago T. Jost and Albert Cohen and
                 Florent de Dinechin and Yves Durand and Christian
                 Fabre",
  booktitle =    "{2019 IFIP/IEEE 27th International Conference on Very
                 Large Scale Integration (VLSI-SoC)}",
  title =        "Byte-Aware Floating-point Operations through a {UNUM}
                 Computing Unit",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "323--328",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/VLSI-SoC.2019.8920387",
  bibdate =      "Fri Dec 15 07:38:18 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Bocco:2019:DPN
author: Andrea Bocco and Yves Durand and Florent de Dinechin
title: Dynamic Precision Numerics Using a Variable-Precision UNUM Type I HW Coprocessor
crossref: Takagi:2019:ISC
pages: 104--107
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00028
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Andrea Bocco and Yves Durand and Florent de Dinechin
rawtitle: Dynamic Precision Numerics Using a Variable-Precision {UNUM Type I HW} Coprocessor
abstract:
A very large internal accumulation register has been proposed to increase the accuracy of scientific code. However, there is a general class of iterative kernels where a vector of high-precision data must be saved from one iteration to the next. Saving the large internal accumulator to memory is impractical in such cases. This work proposes a Variable Precision (VP) Floating Point (FP) arithmetic co-processor architecture based on RISC-V, which 1/ supports legacy IEEE formats for input and output variables, 2/ uses variable length internal registers (up to 512 bits of mantissa) for inner loop multiply-add and 3/ supports loads and stores of intermediate results to cache memory with a dynamically adjustable precision (up to 256 bits of mantissa). It exploits the UNUM type I floating point format, proposing solutions to address some of its pitfalls such as the variable latency of the internal operation, and the variable memory footprint of the intermediate variables. This work is integrated on FPGA and demonstrated on a representative example.

keywords:
ARITH-26; Arrays; cache storage; Computational modeling; coprocessors; Coprocessors; dynamic Precision numerics; field programmable gate arrays; floating point arithmetic; floating point arithmetic co-processor architecture; FPGA; internal accumulation register; iterative kernels; iterative methods; Kernel; Programming; reduced instruction set computing; Registers; RISC-V; Variable Precision; Variable precision, Floating-point, UNUM, Scientific computing, Instruction set design, Hardware architecture, RISC-V, Coprocessor, Multiple precision, FPGA, ASIC; variable-precision UNUM Type I HW coprocessor

rawabstract:
A very large internal accumulation register has been proposed to increase the accuracy of scientific code. However, there is a general class of iterative kernels where a vector of high-precision data must be saved from one iteration to the next. Saving the large internal accumulator to memory is impractical in such cases. This work proposes a Variable Precision (VP) Floating Point (FP) arithmetic co-processor architecture based on RISC-V, which 1/ supports legacy IEEE formats for input and output variables, 2/ uses variable length internal registers (up to 512 bits of mantissa) for inner loop multiply-add and 3/ supports loads and stores of intermediate results to cache memory with a dynamically adjustable precision (up to 256 bits of mantissa). It exploits the UNUM type I floating point format, proposing solutions to address some of its pitfalls such as the variable latency of the internal operation, and the variable memory footprint of the intermediate variables. This work is integrated on FPGA and demonstrated on a representative example.

entry:
@InProceedings{Bocco:2019:DPN,
  author =       "Andrea Bocco and Yves Durand and Florent de Dinechin",
  title =        "Dynamic Precision Numerics Using a Variable-Precision
                 {UNUM Type I HW} Coprocessor",
  crossref =     "Takagi:2019:ISC",
  pages =        "104--107",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00028",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A very large internal accumulation register has been
                 proposed to increase the accuracy of scientific code.
                 However, there is a general class of iterative kernels
                 where a vector of high-precision data must be saved
                 from one iteration to the next. Saving the large
                 internal accumulator to memory is impractical in such
                 cases. This work proposes a Variable Precision (VP)
                 Floating Point (FP) arithmetic co-processor
                 architecture based on RISC-V, which 1/ supports legacy
                 IEEE formats for input and output variables, 2/ uses
                 variable length internal registers (up to 512 bits of
                 mantissa) for inner loop multiply-add and 3/ supports
                 loads and stores of intermediate results to cache
                 memory with a dynamically adjustable precision (up to
                 256 bits of mantissa). It exploits the UNUM type I
                 floating point format, proposing solutions to address
                 some of its pitfalls such as the variable latency of
                 the internal operation, and the variable memory
                 footprint of the intermediate variables. This work is
                 integrated on FPGA and demonstrated on a representative
                 example.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Arrays; cache storage; Computational
                 modeling; coprocessors; Coprocessors; dynamic Precision
                 numerics; field programmable gate arrays; floating
                 point arithmetic; floating point arithmetic
                 co-processor architecture; FPGA; internal accumulation
                 register; iterative kernels; iterative methods; Kernel;
                 Programming; reduced instruction set computing;
                 Registers; RISC-V; Variable Precision; Variable
                 precision, Floating-point, UNUM, Scientific computing,
                 Instruction set design, Hardware architecture, RISC-V,
                 Coprocessor, Multiple precision, FPGA, ASIC;
                 variable-precision UNUM Type I HW coprocessor",
}


bibtype: inproceedings
filename: fparith.bib
label: Bocco:2019:SSM
author: Andrea Bocco and Yves Durand and Florent de Dinechin
title: SMURF: Scalar Multiple-precision Unum RISC-V Floating-point Accelerator for Scientific Computing
crossref: Gustafson:2019:CPC
pages: 1:1--1:8
year: 2019
DOI: https://doi.org/10.1145/3316279.3316280
bibdate: Mon Feb 10 09:31:49 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2020.02.10 09:31:49 ???
URL: https://hal.inria.fr/hal-02087098
acknowledgement: ack-nhfb
articleno: 1
rawauthor: Andrea Bocco and Yves Durand and Florent de Dinechin
abstract:
This paper proposes an innovative Floating Point (FP) architecture for Variable Precision (VP) computation suitable for high precision FP computing, based on a refined version of the UNUM type I format. This architecture supports VP FP intervals where each interval endpoint can have up to 512 bits of mantissa. The proposed hardware architecture is pipelined and has an internal word-size of 64 bits. Computations on longer mantissas are performed iteratively on the existing hardware. The prototype is integrated in a RISC-V environment, it is exposed to the user through an instruction set extension. The paper we provide an example of software usage. The system has been prototyped on a FPGA (Field-Programmable Gate Array) platform and also synthesized for a 28nm FDSOI process technology. The respective working frequency of FPGA and ASIC implementations are 50MHz and 600MHz. The estimated chip area is 1.5mm 2 and the estimated power consumption is 95mW. The flops performance of this architecture remains within the range of a regular fixed-precision IEEE FPU while enabling arbitrary precision computation at reasonable cost.

keywords:
ASIC, UNUM, Floating-point, RISC-V, Coprocessor, Instruction set design, Variable precision, Scientific computing, Hardware architecture, Multiple precision, FPGA

rawabstract:
This paper proposes an innovative Floating Point (FP) architecture for Variable Precision (VP) computation suitable for high precision FP computing, based on a refined version of the UNUM type I format. This architecture supports VP FP intervals where each interval endpoint can have up to 512 bits of mantissa. The proposed hardware architecture is pipelined and has an internal word-size of 64 bits. Computations on longer mantissas are performed iteratively on the existing hardware. The prototype is integrated in a RISC-V environment, it is exposed to the user through an instruction set extension. The paper we provide an example of software usage. The system has been prototyped on a FPGA (Field-Programmable Gate Array) platform and also synthesized for a 28nm FDSOI process technology. The respective working frequency of FPGA and ASIC implementations are 50MHz and 600MHz. The estimated chip area is 1.5mm 2 and the estimated power consumption is 95mW. The flops performance of this architecture remains within the range of a regular fixed-precision IEEE FPU while enabling arbitrary precision computation at reasonable cost.

rawtitle:
{SMURF}: {Scalar Multiple-precision Unum RISC-V Floating-point} Accelerator for Scientific Computing

entry:
@InProceedings{Bocco:2019:SSM,
  author =       "Andrea Bocco and Yves Durand and Florent de Dinechin",
  title =        "{SMURF}: {Scalar Multiple-precision Unum RISC-V
                 Floating-point} Accelerator for Scientific Computing",
  crossref =     "Gustafson:2019:CPC",
  pages =        "1:1--1:8",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316280",
  bibdate =      "Mon Feb 10 09:31:49 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://hal.inria.fr/hal-02087098",
  abstract =     "This paper proposes an innovative Floating Point (FP)
                 architecture for Variable Precision (VP) computation
                 suitable for high precision FP computing, based on a
                 refined version of the UNUM type I format. This
                 architecture supports VP FP intervals where each
                 interval endpoint can have up to 512 bits of mantissa.
                 The proposed hardware architecture is pipelined and has
                 an internal word-size of 64 bits. Computations on
                 longer mantissas are performed iteratively on the
                 existing hardware. The prototype is integrated in a
                 RISC-V environment, it is exposed to the user through
                 an instruction set extension. The paper we provide an
                 example of software usage. The system has been
                 prototyped on a FPGA (Field-Programmable Gate Array)
                 platform and also synthesized for a 28nm FDSOI process
                 technology. The respective working frequency of FPGA
                 and ASIC implementations are 50MHz and 600MHz. The
                 estimated chip area is 1.5mm 2 and the estimated power
                 consumption is 95mW. The flops performance of this
                 architecture remains within the range of a regular
                 fixed-precision IEEE FPU while enabling arbitrary
                 precision computation at reasonable cost.",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  keywords =     "ASIC, UNUM, Floating-point, RISC-V, Coprocessor,
                 Instruction set design, Variable precision, Scientific
                 computing, Hardware architecture, Multiple precision,
                 FPGA",
}


bibtype: article
filename: fparith.bib
label: Boghosian:2019:NPS
author: Bruce M. Boghosian and Peter V. Coveney and Hongyan Wang
title: A New Pathology in the Simulation of Chaotic Dynamical Systems on Digital Computers
journal: j-ADV-THEORY-SIMUL
pages: 1900125
month: sep
monthnumber: 9
year: 2019
CODEN: ATSDCW
DOI: https://doi.org/10.1002/adts.201900125
ISSN: 2513-0390 OR 25130390
bibdate: Tue Sep 24 05:31:42 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.24 05:31:42 ???
URL: https://onlinelibrary.wiley.com/journal/25130390
fjournal: Advanced Theory and Simulations
acknowledgement: ack-nhfb
ajournal: Adv. Theory Simul.
journalURL: https://onlinelibrary.wiley.com/journal/25130390
rawauthor: Bruce M. Boghosian and Peter V. Coveney and Hongyan Wang
rawtitle: A New Pathology in the Simulation of Chaotic Dynamical Systems on Digital Computers
note:
See also news releases cite Caygill:2019:NLH,Caygill:2019:DCF,Silver:2019:CCN,Anonymous:2019:CPC,Dockrill:2019:CMH,Grossman:2019:CSC.

abstract:
Systematic distortions are uncovered in the statistical properties of chaotic dynamical systems when represented and simulated on digital computers using standard IEEE floating-point numbers. This is done by studying a model chaotic dynamical system with a single free parameter $ beta $, known as the generalized Bernoulli map, many of whose exact properties are known. Much of the structure of the dynamical system is lost in the floating-point representation. For even integer values of the parameter, the long time behaviour is completely wrong, subsuming the known anomalous behaviour for $ beta = 2 $. For non-integer $ beta $, relative errors in observables can reach 14%. For odd integer values of $ beta $, floating-point results are more accurate, but still produce relative errors two orders of magnitude larger than those attributable to roundoff. The analysis indicates that the pathology described, which cannot be mitigated by increasing the precision of the floating point numbers, is a representative example of a deeper problem in the computation of expectation values for chaotic systems. The findings sound a warning about the uncritical application of numerical methods in studies of the statistical properties of chaotic dynamical systems, such as are routinely performed throughout computational science, including turbulence and molecular dynamics.

remark:
This study demonstrates the perils of computing with too few significant digits in the floating-point representation. However, the authors report: ``Though the root of this problem resides in the use of finite-precision floating-point arithmetic, it cannot be mitigated by increasing the precision of the floating-point representation. Our analysis strongly suggests that the pathology we describe will exhibit for mantissa and exponent fields of any finite length whatsoever, and for floating-point numbers encoded in any radix whatsoever. Indeed, there is every reason to anticipate that this anomalous behaviour is generic in dissipative chaotic systems of the kind encountered in turbulence and molecular dynamics, and that it is entirely possible that many published results of numerical simulation are substantially inaccurate for this reason.''

rawabstract:
Systematic distortions are uncovered in the statistical properties of chaotic dynamical systems when represented and simulated on digital computers using standard IEEE floating-point numbers. This is done by studying a model chaotic dynamical system with a single free parameter $ \beta $, known as the generalized Bernoulli map, many of whose exact properties are known. Much of the structure of the dynamical system is lost in the floating-point representation. For even integer values of the parameter, the long time behaviour is completely wrong, subsuming the known anomalous behaviour for $ \beta = 2 $. For non-integer $ \beta $, relative errors in observables can reach 14\%. For odd integer values of $ \beta $, floating-point results are more accurate, but still produce relative errors two orders of magnitude larger than those attributable to roundoff. The analysis indicates that the pathology described, which cannot be mitigated by increasing the precision of the floating point numbers, is a representative example of a deeper problem in the computation of expectation values for chaotic systems. The findings sound a warning about the uncritical application of numerical methods in studies of the statistical properties of chaotic dynamical systems, such as are routinely performed throughout computational science, including turbulence and molecular dynamics.

rawnote:
See also news releases \cite{Caygill:2019:NLH,Caygill:2019:DCF,Silver:2019:CCN,Anonymous:2019:CPC,Dockrill:2019:CMH,Grossman:2019:CSC}.

entry:
@Article{Boghosian:2019:NPS,
  author =       "Bruce M. Boghosian and Peter V. Coveney and Hongyan
                 Wang",
  title =        "A New Pathology in the Simulation of Chaotic Dynamical
                 Systems on Digital Computers",
  journal =      j-ADV-THEORY-SIMUL,
  pages =        "1900125",
  month =        sep,
  year =         "2019",
  CODEN =        "ATSDCW",
  DOI =          "https://doi.org/10.1002/adts.201900125",
  ISSN =         "2513-0390",
  bibdate =      "Tue Sep 24 05:31:42 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See also news releases
                 \cite{Caygill:2019:NLH,Caygill:2019:DCF,Silver:2019:CCN,Anonymous:2019:CPC,Dockrill:2019:CMH,Grossman:2019:CSC}.",
  URL =          "https://onlinelibrary.wiley.com/journal/25130390",
  abstract =     "Systematic distortions are uncovered in the
                 statistical properties of chaotic dynamical systems
                 when represented and simulated on digital computers
                 using standard IEEE floating-point numbers. This is
                 done by studying a model chaotic dynamical system with
                 a single free parameter $ \beta $, known as the
                 generalized Bernoulli map, many of whose exact
                 properties are known. Much of the structure of the
                 dynamical system is lost in the floating-point
                 representation. For even integer values of the
                 parameter, the long time behaviour is completely wrong,
                 subsuming the known anomalous behaviour for $ \beta = 2
                 $. For non-integer $ \beta $, relative errors in
                 observables can reach 14\%. For odd integer values of $
                 \beta $, floating-point results are more accurate, but
                 still produce relative errors two orders of magnitude
                 larger than those attributable to roundoff. The
                 analysis indicates that the pathology described, which
                 cannot be mitigated by increasing the precision of the
                 floating point numbers, is a representative example of
                 a deeper problem in the computation of expectation
                 values for chaotic systems. The findings sound a
                 warning about the uncritical application of numerical
                 methods in studies of the statistical properties of
                 chaotic dynamical systems, such as are routinely
                 performed throughout computational science, including
                 turbulence and molecular dynamics.",
  acknowledgement = ack-nhfb,
  ajournal =     "Adv. Theory Simul.",
  fjournal =     "Advanced Theory and Simulations",
  journal-URL =  "https://onlinelibrary.wiley.com/journal/25130390",
  remark =       "This study demonstrates the perils of computing with
                 too few significant digits in the floating-point
                 representation. However, the authors report: ``Though
                 the root of this problem resides in the use of
                 finite-precision floating-point arithmetic, it cannot
                 be mitigated by increasing the precision of the
                 floating-point representation. Our analysis strongly
                 suggests that the pathology we describe will exhibit
                 for mantissa and exponent fields of any finite length
                 whatsoever, and for floating-point numbers encoded in
                 any radix whatsoever. Indeed, there is every reason to
                 anticipate that this anomalous behaviour is generic in
                 dissipative chaotic systems of the kind encountered in
                 turbulence and molecular dynamics, and that it is
                 entirely possible that many published results of
                 numerical simulation are substantially inaccurate for
                 this reason.''",
}


bibtype: article
filename: fparith.bib
label: Borges:2019:IAH
author: Carlos F. Borges
title: An Improved Algorithm for tt hypot(a,b)
journal: arXiv.org
pages: 1--15
day: 14
month: jun
monthnumber: 6
year: 2019
bibdate: Fri Apr 19 05:40:55 2024
bibtimestamp: 2024.04.19 05:40:55 ???
URL: https://arxiv.org/abs/1904.09481
acknowledgement: ack-nhfb
rawauthor: Carlos F. Borges
rawtitle: An Improved Algorithm for {\tt hypot(a,b)}
abstract:
We develop a fast and accurate algorithm for evaluating $ sqrt x^2 + y^2 $ for two floating point numbers $a$ and $b$. Library functions that perform this computation are generally named tt hypot(a,b). We will compare four approaches that we will develop in this paper to the current resident library function that is delivered with Julia 1.1 and to the code that has been distributed with the C math library for decades. We will demonstrate the performance of our algorithms by simulation.

rawabstract:
We develop a fast and accurate algorithm for evaluating $ \sqrt {x^2 + y^2} $ for two floating point numbers $a$ and $b$. Library functions that perform this computation are generally named {\tt hypot(a,b)}. We will compare four approaches that we will develop in this paper to the current resident library function that is delivered with Julia 1.1 and to the code that has been distributed with the C math library for decades. We will demonstrate the performance of our algorithms by simulation.

entry:
@Article{Borges:2019:IAH,
  author =       "Carlos F. Borges",
  title =        "An Improved Algorithm for {\tt hypot(a,b)}",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--15",
  day =          "14",
  month =        jun,
  year =         "2019",
  bibdate =      "Fri Apr 19 05:40:55 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1904.09481",
  abstract =     "We develop a fast and accurate algorithm for
                 evaluating $ \sqrt {x^2 + y^2} $ for two floating point
                 numbers $a$ and $b$. Library functions that perform
                 this computation are generally named {\tt hypot(a,b)}.
                 We will compare four approaches that we will develop in
                 this paper to the current resident library function
                 that is delivered with Julia 1.1 and to the code that
                 has been distributed with the C math library for
                 decades. We will demonstrate the performance of our
                 algorithms by simulation.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Bos:2019:ACI
author: J. W. Bos and S. J. Friedberger
title: Arithmetic Considerations for Isogeny-Based Cryptography
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 7
pages: 979--990
month: jul
monthnumber: 7
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2851238
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. W. Bos and S. J. Friedberger
rawtitle: Arithmetic Considerations for Isogeny-Based Cryptography
bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib

keywords:
arithmetic; arithmetic considerations; arithmetic techniques; Computer architecture; cryptographic protocols; curve models; digital arithmetic; efficient addition-subtraction chains; efficient arithmetic modulo; efficient chains; elliptic curve scalar multiplication; Elliptic curves; isogeny-based cryptography; Montgomery curves; Montgomery reduction; NIST; Optimization; post-quantum public-key arena; Protocols; Public key cryptography; quadratic extension field; scalar multiplication arithmetic; SIDH setting; special shape; supersingular isogeny Diffie-Hellman key-exchange protocol; systematic overview; twisted Edwards curves

entry:
@Article{Bos:2019:ACI,
  author =       "J. W. Bos and S. J. Friedberger",
  title =        "Arithmetic Considerations for Isogeny-Based
                 Cryptography",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "7",
  pages =        "979--990",
  month =        jul,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2851238",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "arithmetic; arithmetic considerations; arithmetic
                 techniques; Computer architecture; cryptographic
                 protocols; curve models; digital arithmetic; efficient
                 addition-subtraction chains; efficient arithmetic
                 modulo; efficient chains; elliptic curve scalar
                 multiplication; Elliptic curves; isogeny-based
                 cryptography; Montgomery curves; Montgomery reduction;
                 NIST; Optimization; post-quantum public-key arena;
                 Protocols; Public key cryptography; quadratic extension
                 field; scalar multiplication arithmetic; SIDH setting;
                 special shape; supersingular isogeny Diffie-Hellman
                 key-exchange protocol; systematic overview; twisted
                 Edwards curves",
}


bibtype: misc
filename: fparith.bib
label: Bright:2019:CEN
author: Peter Bright
pages: 979--990
day: 7
month: mar
monthnumber: 3
year: 2019
bibdate: Fri Mar 08 07:46:06 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.03.08 07:46:06 ???
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Peter Bright
title:
tt calc.exe is now open source; there's surprising depth in its ancient code. The actual calculation engine is more than 20 years old

URL:
https://arstechnica.com/gadgets/2019/03/calc-exe-is-now-open-source-theres-surprising-depth-in-its-ancient-code/; https://github.com/Microsoft/calculator

abstract:
Microsoft's embrace and adoption of open source software has continued with the surprising decision to publish the code for Windows Calculator and release it on GitHub under the permissive MIT license.

rawabstract:
Microsoft's embrace and adoption of open source software has continued with the surprising decision to publish the code for Windows Calculator and release it on GitHub under the permissive MIT license.

rawtitle:
{\tt calc.exe} is now open source; there's surprising depth in its ancient code. {The} actual calculation engine is more than 20 years old

entry:
@Misc{Bright:2019:CEN,
  author =       "Peter Bright",
  title =        "{\tt calc.exe} is now open source; there's surprising
                 depth in its ancient code. {The} actual calculation
                 engine is more than 20 years old",
  howpublished = "Web site",
  day =          "7",
  month =        mar,
  year =         "2019",
  bibdate =      "Fri Mar 08 07:46:06 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arstechnica.com/gadgets/2019/03/calc-exe-is-now-open-source-theres-surprising-depth-in-its-ancient-code/;
                 https://github.com/Microsoft/calculator",
  abstract =     "Microsoft's embrace and adoption of open source
                 software has continued with the surprising decision to
                 publish the code for Windows Calculator and release it
                 on GitHub under the permissive MIT license.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Brown:2019:RCF
author: Erin Clare Brown
title: Rust and C++ on Floating-point Intensive Code
pages: 979--990
day: 19
month: oct
monthnumber: 10
year: 2019
bibdate: Fri Oct 25 06:25:15 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.25 06:25:15 ???
URL: https://upshed.com/2019/10/24/rust-and-c-on-floating-point-intensive-code/
acknowledgement: ack-nhfb
howpublished: Web site.
rawauthor: Erin Clare Brown
rawtitle: {Rust} and {C++} on Floating-point Intensive Code
entry:
@Misc{Brown:2019:RCF,
  author =       "Erin Clare Brown",
  title =        "{Rust} and {C++} on Floating-point Intensive Code",
  howpublished = "Web site.",
  day =          "19",
  month =        oct,
  year =         "2019",
  bibdate =      "Fri Oct 25 06:25:15 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://upshed.com/2019/10/24/rust-and-c-on-floating-point-intensive-code/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Bruguera:2019:GEI
author: J. D. Bruguera and F. de Dinechin
title: Guest Editors Introduction: Special Section on Computer Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 7
pages: 951--952
month: jul
monthnumber: 7
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2918447
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
keywords: Cryptography; Digital arithmetic; Mathematics; Software algorithms; Special issues and sections
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. D. Bruguera and F. de Dinechin
rawtitle: {Guest Editors} Introduction: Special Section on Computer Arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib

entry:
@Article{Bruguera:2019:GEI,
  author =       "J. D. Bruguera and F. de Dinechin",
  title =        "{Guest Editors} Introduction: Special Section on
                 Computer Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "7",
  pages =        "951--952",
  month =        jul,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2918447",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Cryptography; Digital arithmetic; Mathematics;
                 Software algorithms; Special issues and sections",
}


bibtype: inproceedings
filename: fparith.bib
label: Burgess:2019:BPN
title: Bfloat16 Processing for Neural Networks
crossref: Takagi:2019:ISC
pages: 88--91
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00022
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawtitle: {Bfloat16} Processing for Neural Networks
author:
Neil Burgess and Jelena Milanovic and Nigel Stephens and Konstantinos Monachopoulos and David Mansell

abstract:
Bfloat16 (``BF16'') is a new floating-point format tailored specifically for high-performance processing of Neural Networks and will be supported by major CPU and GPU architectures as well as Neural Network accelerators. This paper proposes a possible implementation of a BF16 multiply-accumulation operation that relaxes several IEEE Floating-Point Standard features to afford low-cost hardware implementations. Specifically, subnorms are flushed to zero; only one non-standard rounding mode (Round-Odd) is supported; NaNs are not propagated; and IEEE exception flags are not provided. The paper shows that this approach achieves the same network-level accuracy as using IEEE single-precision arithmetic (``FP32'') for less than half the datapath area cost and with greater throughput.

keywords:
ARITH-26; Artificial neural networks; BF16 multiply-accumulation operation; bfloat16 processing; Computer architecture; CPU architectures; Digital arithmetic; Error analysis; floating point arithmetic; floating-point, rounding mode, neural networks; FP32; GPU architectures; high-performance processing; IEEE exception flags; IEEE floating-point standard features; IEEE single-precision arithmetic; low-cost hardware implementations; network-level accuracy; neural nets; Neural Network accelerators; neural networks; nonstandard rounding mode; Standards; Training

rawabstract:
Bfloat16 (``BF16'') is a new floating-point format tailored specifically for high-performance processing of Neural Networks and will be supported by major CPU and GPU architectures as well as Neural Network accelerators. This paper proposes a possible implementation of a BF16 multiply-accumulation operation that relaxes several IEEE Floating-Point Standard features to afford low-cost hardware implementations. Specifically, subnorms are flushed to zero; only one non-standard rounding mode (Round-Odd) is supported; NaNs are not propagated; and IEEE exception flags are not provided. The paper shows that this approach achieves the same network-level accuracy as using IEEE single-precision arithmetic (``FP32'') for less than half the datapath area cost and with greater throughput.

rawauthor:
Neil Burgess and Jelena Milanovic and Nigel Stephens and Konstantinos Monachopoulos and David Mansell

entry:
@InProceedings{Burgess:2019:BPN,
  author =       "Neil Burgess and Jelena Milanovic and Nigel Stephens
                 and Konstantinos Monachopoulos and David Mansell",
  title =        "{Bfloat16} Processing for Neural Networks",
  crossref =     "Takagi:2019:ISC",
  pages =        "88--91",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00022",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Bfloat16 (``BF16'') is a new floating-point format
                 tailored specifically for high-performance processing
                 of Neural Networks and will be supported by major CPU
                 and GPU architectures as well as Neural Network
                 accelerators. This paper proposes a possible
                 implementation of a BF16 multiply-accumulation
                 operation that relaxes several IEEE Floating-Point
                 Standard features to afford low-cost hardware
                 implementations. Specifically, subnorms are flushed to
                 zero; only one non-standard rounding mode (Round-Odd)
                 is supported; NaNs are not propagated; and IEEE
                 exception flags are not provided. The paper shows that
                 this approach achieves the same network-level accuracy
                 as using IEEE single-precision arithmetic (``FP32'')
                 for less than half the datapath area cost and with
                 greater throughput.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Artificial neural networks; BF16
                 multiply-accumulation operation; bfloat16 processing;
                 Computer architecture; CPU architectures; Digital
                 arithmetic; Error analysis; floating point arithmetic;
                 floating-point, rounding mode, neural networks; FP32;
                 GPU architectures; high-performance processing; IEEE
                 exception flags; IEEE floating-point standard features;
                 IEEE single-precision arithmetic; low-cost hardware
                 implementations; network-level accuracy; neural nets;
                 Neural Network accelerators; neural networks;
                 nonstandard rounding mode; Standards; Training",
}


bibtype: article
filename: fparith.bib
label: Burgess:2019:HPA
author: N. Burgess and C. Goodyer and C. N. Hinds and D. R. Lutz
title: High-Precision Anchored Accumulators for Reproducible Floating-Point Summation
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 7
pages: 967--978
month: jul
monthnumber: 7
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2855729
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: N. Burgess and C. Goodyer and C. N. Hinds and D. R. Lutz
rawtitle: High-Precision Anchored Accumulators for Reproducible Floating-Point Summation
keywords:
2-lane HPA accumulation; 3-lane reproducible FP summation; accurate floating-point summation; computational properties; Computer architecture; datatype; double double accumulation; Electronic mail; Encoding; existing FP formats; floating point arithmetic; Floating-point addition; floating-point numbers; floating-point summation; FP arithmetic; FP16 summations; FP32 summations; FP64 accumulations; FP64 operands; Hardware; high-precision anchored accumulators; high-precision anchored number; high-precision computing; HPA processing; Instruction sets; modest ranges; programmer-selectable range; Proposals; Registers; reproducibility; reproducible accumulation; reproducible floating-point summation; scalable vector extension; SVE; vector architecture; vector processing

entry:
@Article{Burgess:2019:HPA,
  author =       "N. Burgess and C. Goodyer and C. N. Hinds and D. R.
                 Lutz",
  title =        "High-Precision Anchored Accumulators for Reproducible
                 Floating-Point Summation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "7",
  pages =        "967--978",
  month =        jul,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2855729",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "2-lane HPA accumulation; 3-lane reproducible FP
                 summation; accurate floating-point summation;
                 computational properties; Computer architecture;
                 datatype; double double accumulation; Electronic mail;
                 Encoding; existing FP formats; floating point
                 arithmetic; Floating-point addition; floating-point
                 numbers; floating-point summation; FP arithmetic; FP16
                 summations; FP32 summations; FP64 accumulations; FP64
                 operands; Hardware; high-precision anchored
                 accumulators; high-precision anchored number;
                 high-precision computing; HPA processing; Instruction
                 sets; modest ranges; programmer-selectable range;
                 Proposals; Registers; reproducibility; reproducible
                 accumulation; reproducible floating-point summation;
                 scalable vector extension; SVE; vector architecture;
                 vector processing",
}


bibtype: article
filename: fparith.bib
label: Cappello:2019:UCL
title: Use cases of lossy compression for floating-point data in scientific data sets
journal: j-IJHPCA
volume: 33
number: 6
pages: 1201--1220
day: 1
month: nov
monthnumber: 11
year: 2019
CODEN: IHPCFL
DOI: https://doi.org/10.1177/1094342019853336
ISSN: 1094-3420 (print), 1741-2846 (electronic) OR 10943420 (print), 17412846 (electronic)
ISSNL: 1094-3420 OR 10943420
bibdate: Wed Oct 9 14:35:54 MDT 2019
bibtimestamp: 2019.10.09 14:35:54 MDT
URL: https://journals.sagepub.com/doi/full/10.1177/1094342019853336
fjournal: International Journal of High Performance Computing Applications
acknowledgement: ack-nhfb
journalURL: https://journals.sagepub.com/home/hpc
rawtitle: Use cases of lossy compression for floating-point data in scientific data sets
author:
Franck Cappello and Sheng Di and Sihuan Li and Xin Liang and Ali Murat Gok and Dingwen Tao and Chun Hong Yoon and Xin-Chuan Wu and Yuri Alexeev and Frederic T. Chong

bibsource:
http://hpc.sagepub.com/; https://www.math.utah.edu/pub/tex/bib/datacompression.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ijsa.bib

rawauthor:
Franck Cappello and Sheng Di and Sihuan Li and Xin Liang and Ali Murat Gok and Dingwen Tao and Chun Hong Yoon and Xin-Chuan Wu and Yuri Alexeev and Frederic T. Chong

entry:
@Article{Cappello:2019:UCL,
  author =       "Franck Cappello and Sheng Di and Sihuan Li and Xin
                 Liang and Ali Murat Gok and Dingwen Tao and Chun Hong
                 Yoon and Xin-Chuan Wu and Yuri Alexeev and Frederic T.
                 Chong",
  title =        "Use cases of lossy compression for floating-point data
                 in scientific data sets",
  journal =      j-IJHPCA,
  volume =       "33",
  number =       "6",
  pages =        "1201--1220",
  day =          "1",
  month =        nov,
  year =         "2019",
  CODEN =        "IHPCFL",
  DOI =          "https://doi.org/10.1177/1094342019853336",
  ISSN =         "1094-3420 (print), 1741-2846 (electronic)",
  ISSN-L =       "1094-3420",
  bibdate =      "Wed Oct 9 14:35:54 MDT 2019",
  bibsource =    "http://hpc.sagepub.com/;
                 https://www.math.utah.edu/pub/tex/bib/datacompression.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ijsa.bib",
  URL =          "https://journals.sagepub.com/doi/full/10.1177/1094342019853336",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of High Performance Computing
                 Applications",
  journal-URL =  "https://journals.sagepub.com/home/hpc",
}


bibtype: misc
filename: fparith.bib
label: Carlough:2019:DBF
title: Decimal and binary floating point arithmetic calculations
pages: 1201--1220
day: 17
month: sep
monthnumber: 9
year: 2019
bibdate: Thu Oct 17 11:29:24 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 11:29:24 ???
URL: https://patents.google.com/patent/US10416962B2
acknowledgement: ack-nhfb
howpublished: US Patent 10,416,962
rawtitle: Decimal and binary floating point arithmetic calculations
author:
Steven R. Carlough and Juergen Haess and Michael Klein and Klaus M. Kroener and Petra Leber and Silvia M. Mueller and Kerstin Schelm

abstract:
Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract.

remark:
Patent filed 2 October 2015 based on British patent GB1417582.2 of 6 October 2014, granted 17 September 2019 to IBM, expected expiration 11 January 2036 (in 17th year after grant).

rawabstract:
Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract.

rawauthor:
Steven R. Carlough and Juergen Haess and Michael Klein and Klaus M. Kroener and Petra Leber and Silvia M. Mueller and Kerstin Schelm

entry:
@Misc{Carlough:2019:DBF,
  author =       "Steven R. Carlough and Juergen Haess and Michael Klein
                 and Klaus M. Kroener and Petra Leber and Silvia M.
                 Mueller and Kerstin Schelm",
  title =        "Decimal and binary floating point arithmetic
                 calculations",
  howpublished = "US Patent 10,416,962",
  day =          "17",
  month =        sep,
  year =         "2019",
  bibdate =      "Thu Oct 17 11:29:24 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://patents.google.com/patent/US10416962B2",
  abstract =     "Logic is provided for performing decimal and binary
                 floating point arithmetic calculations on first and
                 second operands. The method includes: receiving the
                 first and second operands in packed format; unpacking
                 the first and second operands; swapping the first
                 operand to a fourth operand and the second operand to a
                 third operand, if an exponent of the first operand is
                 less than an exponent of the second operand, otherwise
                 storing the first operand to the third operand and the
                 second operand to the fourth operand; aligning the
                 third operand and the fourth operands based on the
                 exponent difference of the third and fourth operand and
                 a number of leading zeroes of the third operand;
                 performing an add/subtract operation on the aligned
                 third and fourth operands with normalizing and rounding
                 between the operands; and packing the result obtained
                 from the add/subtract.",
  acknowledgement = ack-nhfb,
  remark =       "Patent filed 2 October 2015 based on British patent
                 GB1417582.2 of 6 October 2014, granted 17 September
                 2019 to IBM, expected expiration 11 January 2036 (in
                 17th year after grant).",
}


bibtype: inproceedings
filename: fparith.bib
label: Carmichael:2019:DPD
editor: IEEE
booktitle: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
title: Deep Positron: a Deep Neural Network Using the Posit Number System
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1421--1426
year: 2019
DOI: https://doi.org/10.23919/DATE.2019.8715262
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawbooktitle: {2019 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}
raweditor: {IEEE}
rawtitle: {Deep Positron}: a Deep Neural Network Using the Posit Number System
author:
Zachariah Carmichael and Hamed F. Langroudi and Char Khazanov and Jeffrey Lillie and John L. Gustafson and Dhireesha Kudithipudi

rawauthor:
Zachariah Carmichael and Hamed F. Langroudi and Char Khazanov and Jeffrey Lillie and John L. Gustafson and Dhireesha Kudithipudi

entry:
@InProceedings{Carmichael:2019:DPD,
  author =       "Zachariah Carmichael and Hamed F. Langroudi and Char
                 Khazanov and Jeffrey Lillie and John L. Gustafson and
                 Dhireesha Kudithipudi",
  editor =       "{IEEE}",
  booktitle =    "{2019 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "{Deep Positron}: a Deep Neural Network Using the Posit
                 Number System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1421--1426",
  year =         "2019",
  DOI =          "https://doi.org/10.23919/DATE.2019.8715262",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Carmichael:2019:PET
title: Performance-Efficiency Trade-off of Low-Precision Numerical Formats in Deep Neural Networks
crossref: Gustafson:2019:CPC
pages: 3:1--3:9
year: 2019
DOI: https://doi.org/10.1145/3316279.3316282
bibdate: Mon Feb 10 12:11:16 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 12:11:16 ???
acknowledgement: ack-nhfb
articleno: 3
rawtitle: Performance-Efficiency Trade-off of Low-Precision Numerical Formats in Deep Neural Networks
author:
Zachariah Carmichael and Hamed F. Langroudi and Char Khazanov and Jeffrey Lillie and John L. Gustafson and Dhireesha Kudithipudi

keywords:
machine learning, deep neural networks, floating point, posit numerical format, DNN accelerators, tapered precision, low-precision

entry:
@InProceedings{Carmichael:2019:PET,
  author =       "Zachariah Carmichael and Hamed F. Langroudi and Char
                 Khazanov and Jeffrey Lillie and John L. Gustafson and
                 Dhireesha Kudithipudi",
  title =        "Performance-Efficiency Trade-off of Low-Precision
                 Numerical Formats in Deep Neural Networks",
  crossref =     "Gustafson:2019:CPC",
  pages =        "3:1--3:9",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316282",
  bibdate =      "Mon Feb 10 12:11:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  keywords =     "machine learning, deep neural networks, floating
                 point, posit numerical format, DNN accelerators,
                 tapered precision, low-precision",
  location =     "Singapore, Singapore",
  numpages =     "9",
}


bibtype: misc
filename: fparith.bib
label: Caygill:2019:DCF
author: Rebecca Caygill
title: Digital Computers Fail to Accurately Model Chaos Because of Fundamental Numbers Limit
pages: 3:1--3:9
day: 23
month: sep
monthnumber: 9
year: 2019
bibdate: Tue Sep 24 05:29:26 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.24 05:29:26 ???
note: See cite Boghosian:2019:NPS.
acknowledgement: ack-nhfb
howpublished: University College London news release.
rawauthor: Rebecca Caygill
rawnote: See \cite{Boghosian:2019:NPS}.
rawtitle: Digital Computers Fail to Accurately Model Chaos Because of Fundamental Numbers Limit
URL:
https://scitechdaily.com/digital-computers-fail-to-accurately-model-chaos-because-of-fundamental-numbers-limit/

entry:
@Misc{Caygill:2019:DCF,
  author =       "Rebecca Caygill",
  title =        "Digital Computers Fail to Accurately Model Chaos
                 Because of Fundamental Numbers Limit",
  howpublished = "University College London news release.",
  day =          "23",
  month =        sep,
  year =         "2019",
  bibdate =      "Tue Sep 24 05:29:26 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Boghosian:2019:NPS}.",
  URL =          "https://scitechdaily.com/digital-computers-fail-to-accurately-model-chaos-because-of-fundamental-numbers-limit/",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Caygill:2019:NLH
author: Rebecca Caygill
title: Numbers limit how accurately digital computers model chaos
pages: 3:1--3:9
day: 23
month: sep
monthnumber: 9
year: 2019
bibdate: Tue Sep 24 05:29:26 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.24 05:29:26 ???
note: See cite Boghosian:2019:NPS.
URL: https://www.eurekalert.org/pub_releases/2019-09/ucl-nlh092019.php
acknowledgement: ack-nhfb
howpublished: University College London news release.
rawauthor: Rebecca Caygill
rawnote: See \cite{Boghosian:2019:NPS}.
rawtitle: Numbers limit how accurately digital computers model chaos
entry:
@Misc{Caygill:2019:NLH,
  author =       "Rebecca Caygill",
  title =        "Numbers limit how accurately digital computers model
                 chaos",
  howpublished = "University College London news release.",
  day =          "23",
  month =        sep,
  year =         "2019",
  bibdate =      "Tue Sep 24 05:29:26 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Boghosian:2019:NPS}.",
  URL =          "https://www.eurekalert.org/pub_releases/2019-09/ucl-nlh092019.php",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Chen:2019:EIR
author: K. Chen and L. Chen and P. Reviriego and F. Lombardi
title: Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC)
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 5
pages: 784--790
month: may
monthnumber: 5
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2885044
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: K. Chen and L. Chen and P. Reviriego and F. Lombardi
rawtitle: Efficient Implementations of Reduced Precision Redundancy ({RPR}) Multiply and Accumulate ({MAC})
keywords:
Adders; arithmetic circuits; circuit overhead; computational environments; critical systems; deep machine learning; digital arithmetic; Discrete cosine transforms; error correction; error correction capabilities; error correction codes; implementation overhead; learning (artificial intelligence); MAC implementations; MAC operation; Machine learning; matrix multiplication; Mean Square Error; mean square error methods; modern computing systems; multiply and accumulate; neural networks; Neural networks; object recognition; precision copies; reduced precision redundancy; redundancy; Redundancy; RPR implementations; signed integer multiplication; soft error; Soft errors; Tunneling magnetoresistance

entry:
@Article{Chen:2019:EIR,
  author =       "K. Chen and L. Chen and P. Reviriego and F. Lombardi",
  title =        "Efficient Implementations of Reduced Precision
                 Redundancy ({RPR}) Multiply and Accumulate ({MAC})",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "5",
  pages =        "784--790",
  month =        may,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2885044",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adders; arithmetic circuits; circuit overhead;
                 computational environments; critical systems; deep
                 machine learning; digital arithmetic; Discrete cosine
                 transforms; error correction; error correction
                 capabilities; error correction codes; implementation
                 overhead; learning (artificial intelligence); MAC
                 implementations; MAC operation; Machine learning;
                 matrix multiplication; Mean Square Error; mean square
                 error methods; modern computing systems; multiply and
                 accumulate; neural networks; Neural networks; object
                 recognition; precision copies; reduced precision
                 redundancy; redundancy; Redundancy; RPR
                 implementations; signed integer multiplication; soft
                 error; Soft errors; Tunneling magnetoresistance",
}


bibtype: article
filename: fparith.bib
label: Cheng:2019:TCI
author: Xi Cheng and Min Zhou and Xiaoyu Song and Ming Gu and Jiaguang Sun
title: Tolerating C Integer Error via Precision Elevation
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 2
pages: 270--286
month: feb
monthnumber: 2
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2866388
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Feb 4 19:28:55 MST 2019
bibtimestamp: 2019.02.04 19:28:55 MST
URL: https://ieeexplore.ieee.org/document/8443077/
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Xi Cheng and Min Zhou and Xiaoyu Song and Ming Gu and Jiaguang Sun
rawtitle: Tolerating {C} Integer Error via Precision Elevation
entry:
@Article{Cheng:2019:TCI,
  author =       "Xi Cheng and Min Zhou and Xiaoyu Song and Ming Gu and
                 Jiaguang Sun",
  title =        "Tolerating {C} Integer Error via Precision Elevation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "2",
  pages =        "270--286",
  month =        feb,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2866388",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Feb 4 19:28:55 MST 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "https://ieeexplore.ieee.org/document/8443077/",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Cornea:2019:NTI
author: Marius Cornea
title: New Technologies for Improved Computing
crossref: Takagi:2019:ISC
pages: 96--96
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00024
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Marius Cornea
rawtitle: New Technologies for Improved Computing
abstract:
In recent years, we learned to live with a slow-down in the growth rates predicted so far with remarkable accuracy by Moore's law. However, this does not necessarily mean that advancements in performance and reduced power consumption are not possible anymore. There will be more innovations and improvements in processor and system architecture and microarchitecture than before, which will enable continued growth - at Intel, and in the industry. Intel has identified several areas which deserve focused efforts and investment, with the promise of providing in return growth and results we came to expect. Manufacturing processes constitute the first such area. Besides using more advanced technologies to achieve smaller features on our ICs, Intel is also introducing advanced packaging solutions, which will enable exponential scaling in computing density by extending transistor placement in a third dimension. The second area is that of processor and system architecture. Computing architectures from Intel span most of the existing compute spectrum, with scalar, vector, matrix, and spatial architectures. These map roughly to our CPUs, GPUs, accelerators, and FPGAs. Memory is at the center of the third focus area. The memory hierarchy is optimized by capacity, latency, bandwidth, cost, and other features. Persistent memory and high-bandwidth memory have been introduced relatively recently in Intel systems, and will continue to influence the way the memory system is structured. The interconnect is the next important component, in a vastly heterogeneous computing environment for almost all compute devices. Communication has to keep up with computation capacity, a true challenge when trillions of operations per second are possible in many commonly used systems. Security is the fifth focus area, where Intel has the components to improve safety in computation and data preservation in a world where threats increase in number and sophistication, as seen too often recently. Last but not least, software has a significant potential in increasing computing capabilities. Intel is aiming to offer a common set of tools that can address the needs of developers for all the devices we offer, from CPUs and GPUs, to accelerators and FPGAs. Computer arithmetic is central to several of the areas highlighted above. Advancements in this field will play an important role in present as well as future processor architectures and implementations. In conclusion, we will also look at developments in this area for future Intel processors.

keywords:
accelerator; ARITH-26; Computer architecture; computer arithmetic; computing architectures; Cornea; CPU; data preservation; data security; Digital arithmetic; digital arithmetic; Field programmable gate arrays; field programmable gate arrays; FPGA; GPU; hardware accelerators; heterogeneous computing environment; improved computing; industrial economics; integrated circuit manufacture; integrated circuit packaging; manufacturing processes; memory hierarchy; microprocessor chips; packaging solutions; Power demand; security of data; semiconductor storage; semiconductor technology; Systems architecture; Technological innovation; three-dimensional integrated circuits; transistor placement

rawabstract:
In recent years, we learned to live with a slow-down in the growth rates predicted so far with remarkable accuracy by Moore's law. However, this does not necessarily mean that advancements in performance and reduced power consumption are not possible anymore. There will be more innovations and improvements in processor and system architecture and microarchitecture than before, which will enable continued growth - at Intel, and in the industry. Intel has identified several areas which deserve focused efforts and investment, with the promise of providing in return growth and results we came to expect. Manufacturing processes constitute the first such area. Besides using more advanced technologies to achieve smaller features on our ICs, Intel is also introducing advanced packaging solutions, which will enable exponential scaling in computing density by extending transistor placement in a third dimension. The second area is that of processor and system architecture. Computing architectures from Intel span most of the existing compute spectrum, with scalar, vector, matrix, and spatial architectures. These map roughly to our CPUs, GPUs, accelerators, and FPGAs. Memory is at the center of the third focus area. The memory hierarchy is optimized by capacity, latency, bandwidth, cost, and other features. Persistent memory and high-bandwidth memory have been introduced relatively recently in Intel systems, and will continue to influence the way the memory system is structured. The interconnect is the next important component, in a vastly heterogeneous computing environment for almost all compute devices. Communication has to keep up with computation capacity, a true challenge when trillions of operations per second are possible in many commonly used systems. Security is the fifth focus area, where Intel has the components to improve safety in computation and data preservation in a world where threats increase in number and sophistication, as seen too often recently. Last but not least, software has a significant potential in increasing computing capabilities. Intel is aiming to offer a common set of tools that can address the needs of developers for all the devices we offer, from CPUs and GPUs, to accelerators and FPGAs. Computer arithmetic is central to several of the areas highlighted above. Advancements in this field will play an important role in present as well as future processor architectures and implementations. In conclusion, we will also look at developments in this area for future Intel processors.

entry:
@InProceedings{Cornea:2019:NTI,
  author =       "Marius Cornea",
  title =        "New Technologies for Improved Computing",
  crossref =     "Takagi:2019:ISC",
  pages =        "96--96",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00024",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In recent years, we learned to live with a slow-down
                 in the growth rates predicted so far with remarkable
                 accuracy by Moore's law. However, this does not
                 necessarily mean that advancements in performance and
                 reduced power consumption are not possible anymore.
                 There will be more innovations and improvements in
                 processor and system architecture and microarchitecture
                 than before, which will enable continued growth - at
                 Intel, and in the industry. Intel has identified
                 several areas which deserve focused efforts and
                 investment, with the promise of providing in return
                 growth and results we came to expect. Manufacturing
                 processes constitute the first such area. Besides using
                 more advanced technologies to achieve smaller features
                 on our ICs, Intel is also introducing advanced
                 packaging solutions, which will enable exponential
                 scaling in computing density by extending transistor
                 placement in a third dimension. The second area is that
                 of processor and system architecture. Computing
                 architectures from Intel span most of the existing
                 compute spectrum, with scalar, vector, matrix, and
                 spatial architectures. These map roughly to our CPUs,
                 GPUs, accelerators, and FPGAs. Memory is at the center
                 of the third focus area. The memory hierarchy is
                 optimized by capacity, latency, bandwidth, cost, and
                 other features. Persistent memory and high-bandwidth
                 memory have been introduced relatively recently in
                 Intel systems, and will continue to influence the way
                 the memory system is structured. The interconnect is
                 the next important component, in a vastly heterogeneous
                 computing environment for almost all compute devices.
                 Communication has to keep up with computation capacity,
                 a true challenge when trillions of operations per
                 second are possible in many commonly used systems.
                 Security is the fifth focus area, where Intel has the
                 components to improve safety in computation and data
                 preservation in a world where threats increase in
                 number and sophistication, as seen too often recently.
                 Last but not least, software has a significant
                 potential in increasing computing capabilities. Intel
                 is aiming to offer a common set of tools that can
                 address the needs of developers for all the devices we
                 offer, from CPUs and GPUs, to accelerators and FPGAs.
                 Computer arithmetic is central to several of the areas
                 highlighted above. Advancements in this field will play
                 an important role in present as well as future
                 processor architectures and implementations. In
                 conclusion, we will also look at developments in this
                 area for future Intel processors.",
  acknowledgement = ack-nhfb,
  keywords =     "accelerator; ARITH-26; Computer architecture; computer
                 arithmetic; computing architectures; Cornea; CPU; data
                 preservation; data security; Digital arithmetic;
                 digital arithmetic; Field programmable gate arrays;
                 field programmable gate arrays; FPGA; GPU; hardware
                 accelerators; heterogeneous computing environment;
                 improved computing; industrial economics; integrated
                 circuit manufacture; integrated circuit packaging;
                 manufacturing processes; memory hierarchy;
                 microprocessor chips; packaging solutions; Power
                 demand; security of data; semiconductor storage;
                 semiconductor technology; Systems architecture;
                 Technological innovation; three-dimensional integrated
                 circuits; transistor placement",
}


bibtype: article
filename: fparith.bib
label: Courtois:2019:RRR
author: J. Courtois and L. Abbas-Turki and J. Bajard
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 12
pages: 1720--1730
month: dec
monthnumber: 12
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2924630
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Nov 7 11:20:24 2019
bibtimestamp: 2019.11.07 11:20:24 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. Courtois and L. Abbas-Turki and J. Bajard
title:
Resilience of Randomized RNS Arithmetic with Respect to Side-Channel Leaks of Cryptographic Computation

bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib

keywords:
CPA; DPA; ECC; Elliptic curve cryptography; Elliptic curves; Hamming distance; Hamming weight; information leakage; Maximum likelihood estimation; maximum likelihood estimator; moduli randomization; Monte Carlo; Multiprotocol label switching; Resilience; RNS; side channel

rawtitle:
Resilience of Randomized {RNS} Arithmetic with Respect to Side-Channel Leaks of Cryptographic Computation

entry:
@Article{Courtois:2019:RRR,
  author =       "J. Courtois and L. Abbas-Turki and J. Bajard",
  title =        "Resilience of Randomized {RNS} Arithmetic with Respect
                 to Side-Channel Leaks of Cryptographic Computation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "12",
  pages =        "1720--1730",
  month =        dec,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2924630",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Nov 7 11:20:24 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "CPA; DPA; ECC; Elliptic curve cryptography; Elliptic
                 curves; Hamming distance; Hamming weight; information
                 leakage; Maximum likelihood estimation; maximum
                 likelihood estimator; moduli randomization; Monte
                 Carlo; Multiprotocol label switching; Resilience; RNS;
                 side channel",
}


bibtype: article
filename: fparith.bib
label: Covanov:2019:FIM
author: Svyatoslav Covanov and Emmanuel Thome
title: Fast integer multiplication using generalized Fermat primes
journal: j-MATH-COMPUT
volume: 88
number: 317
pages: 1449--1477
month: jan
monthnumber: 1
year: 2019
CODEN: MCMPAF
DOI: https://doi.org/10.1090/mcom/3367
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Tue Jul 14 06:45:38 MDT 2020
bibtimestamp: 2020.07.14 06:45:38 MDT
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Svyatoslav Covanov and Emmanuel Thom{\'e}
rawtitle: Fast integer multiplication using generalized {Fermat} primes
bibsource:
http://www.ams.org/mcom/2019-88-317; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib

URL:
https://www.ams.org/journals/mcom/2019-88-317/S0025-5718-2018-03367-1; https://www.ams.org/journals/mcom/2019-88-317/S0025-5718-2018-03367-1/S0025-5718-2018-03367-1.pdf; https://www.ams.org/mathscinet/search/authors.html?authorName=Thome%2C%20Emmanuel; https://www.ams.org/mathscinet/search/authors.html?mrauthid=1105937

entry:
@Article{Covanov:2019:FIM,
  author =       "Svyatoslav Covanov and Emmanuel Thom{\'e}",
  title =        "Fast integer multiplication using generalized {Fermat}
                 primes",
  journal =      j-MATH-COMPUT,
  volume =       "88",
  number =       "317",
  pages =        "1449--1477",
  month =        jan,
  year =         "2019",
  CODEN =        "MCMPAF",
  DOI =          "https://doi.org/10.1090/mcom/3367",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Tue Jul 14 06:45:38 MDT 2020",
  bibsource =    "http://www.ams.org/mcom/2019-88-317;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib",
  URL =          "https://www.ams.org/journals/mcom/2019-88-317/S0025-5718-2018-03367-1;
                 https://www.ams.org/journals/mcom/2019-88-317/S0025-5718-2018-03367-1/S0025-5718-2018-03367-1.pdf;
                 https://www.ams.org/mathscinet/search/authors.html?authorName=Thome%2C%20Emmanuel;
                 https://www.ams.org/mathscinet/search/authors.html?mrauthid=1105937",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
}


bibtype: misc
filename: fparith.bib
label: Cowlishaw:2019:AIS
author: Mike Cowlishaw and David Hough
title: ANSI/IEEE Std 754-2019
pages: 1449--1477
day: 13
month: jun
monthnumber: 6
year: 2019
bibdate: Fri Aug 30 07:30:45 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.08.30 07:30:45 ???
URL: http://754r.ucbtest.org/remote/background/
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Mike Cowlishaw and David Hough
rawtitle: {ANSI/IEEE Std 754-2019}
abstract:
The IEEE 754-2008 standard expired in 2019, so a minor revision was undertaken, to determine a set of relatively non-controversial upward-compatible editorial corrections and clarifications and minor enhancements to the 2008 standard. 754-2019 was approved by IEEE Standards Board on 13 June 2019 and published in July 2019. David Hough was chair, Mike Cowlishaw was editor. The base document was the technical content of ANSI/IEEE Std 754-2008. Some new operations have been recommended in 2019. In particular, new min/max operations better match application requirements, augmented addition, subtraction, and multiplication operations support building higher precision in software and support reproducible reductions on arrays, and new operations get and set NaN payloads. These recommended operations might be required in a future edition of this standard.

rawabstract:
The IEEE 754-2008 standard expired in 2019, so a minor revision was undertaken, to determine a set of relatively non-controversial upward-compatible editorial corrections and clarifications and minor enhancements to the 2008 standard. 754-2019 was approved by IEEE Standards Board on 13 June 2019 and published in July 2019. David Hough was chair, Mike Cowlishaw was editor. The base document was the technical content of ANSI/IEEE Std 754-2008. Some new operations have been recommended in 2019. In particular, new min/max operations better match application requirements, augmented addition, subtraction, and multiplication operations support building higher precision in software and support reproducible reductions on arrays, and new operations get and set NaN payloads. These recommended operations might be required in a future edition of this standard.

entry:
@Misc{Cowlishaw:2019:AIS,
  author =       "Mike Cowlishaw and David Hough",
  title =        "{ANSI/IEEE Std 754-2019}",
  howpublished = "Web site",
  day =          "13",
  month =        jun,
  year =         "2019",
  bibdate =      "Fri Aug 30 07:30:45 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://754r.ucbtest.org/remote/background/",
  abstract =     "The IEEE 754-2008 standard expired in 2019, so a minor
                 revision was undertaken, to determine a set of
                 relatively non-controversial upward-compatible
                 editorial corrections and clarifications and minor
                 enhancements to the 2008 standard. 754-2019 was
                 approved by IEEE Standards Board on 13 June 2019 and
                 published in July 2019. David Hough was chair, Mike
                 Cowlishaw was editor. The base document was the
                 technical content of ANSI/IEEE Std 754-2008.

                 Some new operations have been recommended in 2019. In
                 particular, new min/max operations better match
                 application requirements, augmented addition,
                 subtraction, and multiplication operations support
                 building higher precision in software and support
                 reproducible reductions on arrays, and new operations
                 get and set NaN payloads. These recommended operations
                 might be required in a future edition of this
                 standard.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: deDinechin:2019:PGB
author: Florent de Dinechin and Luc Forget and Jean-Michel Muller and Yohann Uguen
title: Posits: The Good, the Bad and the Ugly
crossref: Gustafson:2019:CPC
pages: 6:1--6:10
year: 2019
DOI: https://doi.org/10.1145/3316279.3316285
bibdate: Mon Feb 10 12:11:16 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 12:11:16 ???
keywords: numerical analysis, Posits, floating-point
acknowledgement: ack-nhfb
articleno: 6
rawauthor: Florent de Dinechin and Luc Forget and Jean-Michel Muller and Yohann Uguen
rawtitle: Posits: The Good, the Bad and the Ugly
entry:
@InProceedings{deDinechin:2019:PGB,
  author =       "Florent de Dinechin and Luc Forget and Jean-Michel
                 Muller and Yohann Uguen",
  title =        "Posits: The Good, the Bad and the Ugly",
  crossref =     "Gustafson:2019:CPC",
  pages =        "6:1--6:10",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316285",
  bibdate =      "Mon Feb 10 12:11:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "6",
  keywords =     "numerical analysis, Posits, floating-point",
  location =     "Singapore, Singapore",
  numpages =     "10",
}


bibtype: inproceedings
filename: fparith.bib
label: deDinechin:2019:RYF
author: Florent de Dinechin
title: Reflections on 10 Years of FloPoCo
crossref: Takagi:2019:ISC
pages: 187--189
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00042
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Florent de Dinechin
rawtitle: Reflections on 10 Years of {FloPoCo}
abstract:
The FloPoCo open-source arithmetic core generator project started modestly in 2008 with a few parametric floating point cores. It has since then evolved to become a framework for research on hardware arithmetic cores at large. This article reviews some of the choices made in this past decade, and some of the challenges ahead for the next.

keywords:
ARITH-26; arithmetic core generation; Computer architecture; Digital arithmetic; Field programmable gate arrays; floating point arithmetic; flopoco; FloPoCo open-source arithmetic core generator project; Generators; Hardware; hardware arithmetic cores; parametric floating point cores; Tools; VHDL

rawabstract:
The FloPoCo open-source arithmetic core generator project started modestly in 2008 with a few parametric floating point cores. It has since then evolved to become a framework for research on hardware arithmetic cores at large. This article reviews some of the choices made in this past decade, and some of the challenges ahead for the next.

entry:
@InProceedings{deDinechin:2019:RYF,
  author =       "Florent de Dinechin",
  title =        "Reflections on 10 Years of {FloPoCo}",
  crossref =     "Takagi:2019:ISC",
  pages =        "187--189",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00042",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The FloPoCo open-source arithmetic core generator
                 project started modestly in 2008 with a few parametric
                 floating point cores. It has since then evolved to
                 become a framework for research on hardware arithmetic
                 cores at large. This article reviews some of the
                 choices made in this past decade, and some of the
                 challenges ahead for the next.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; arithmetic core generation; Computer
                 architecture; Digital arithmetic; Field programmable
                 gate arrays; floating point arithmetic; flopoco;
                 FloPoCo open-source arithmetic core generator project;
                 Generators; Hardware; hardware arithmetic cores;
                 parametric floating point cores; Tools; VHDL",
}


bibtype: inproceedings
filename: fparith.bib
label: deDinechin:2019:TBV
author: Florent de Dinechin and Silviu-Ioan Filip and Martin Kumm and Luc Forget
title: Table-Based versus Shift-And-Add Constant Multipliers for FPGAs
crossref: Takagi:2019:ISC
pages: 151--158
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00037
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Florent de Dinechin and Silviu-Ioan Filip and Martin Kumm and Luc Forget
rawtitle: Table-Based versus Shift-And-Add Constant Multipliers for {FPGAs}
abstract:
The multiplication by a constant is a frequently used operation. To implement it on Field Programmable Gate Arrays (FPGAs), the state of the art offers two completely different methods: one relying on bit shifts and additions/subtractions, and another one using look-up tables and additions. So far, it was unclear which method performs best for a given constant and input/output data types. The main contribution of this work is a thorough comparison of both methods in the main application contexts of constant multiplication: filters, signal-processing transforms, and elementary functions. Most of the previous state of the art addresses multiplication by an integer constant. This work shows that, in most of these application contexts, a formulation of the problem as the multiplication by a real constant allows for more efficient architectures. Another contribution is a novel extension of the shift-and-add method to real constants. For that, an integer linear programming (ILP) formulation is proposed, which truncates each component in the shift-and-add network to a minimum necessary word size that is aligned with the approximation error of the coefficient. All methods are implemented within the open-source FloPoCo framework.

keywords:
Adders; approximation theory; ARITH-26; Complexity theory; constant multiplier, FPGA, optimization, ILP; Field programmable gate arrays; Field Programmable Gate Arrays; field programmable gate arrays; FPGAs; Hardware; integer linear programming; integer programming; linear programming; look-up tables; multiplying circuits; shift-and-add network; signal-processing transforms; Table lookup; table lookup; table-based versus shift-and-add constant multipliers; Throughput

rawabstract:
The multiplication by a constant is a frequently used operation. To implement it on Field Programmable Gate Arrays (FPGAs), the state of the art offers two completely different methods: one relying on bit shifts and additions/subtractions, and another one using look-up tables and additions. So far, it was unclear which method performs best for a given constant and input/output data types. The main contribution of this work is a thorough comparison of both methods in the main application contexts of constant multiplication: filters, signal-processing transforms, and elementary functions. Most of the previous state of the art addresses multiplication by an integer constant. This work shows that, in most of these application contexts, a formulation of the problem as the multiplication by a real constant allows for more efficient architectures. Another contribution is a novel extension of the shift-and-add method to real constants. For that, an integer linear programming (ILP) formulation is proposed, which truncates each component in the shift-and-add network to a minimum necessary word size that is aligned with the approximation error of the coefficient. All methods are implemented within the open-source FloPoCo framework.

entry:
@InProceedings{deDinechin:2019:TBV,
  author =       "Florent de Dinechin and Silviu-Ioan Filip and Martin
                 Kumm and Luc Forget",
  title =        "Table-Based versus Shift-And-Add Constant Multipliers
                 for {FPGAs}",
  crossref =     "Takagi:2019:ISC",
  pages =        "151--158",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00037",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The multiplication by a constant is a frequently used
                 operation. To implement it on Field Programmable Gate
                 Arrays (FPGAs), the state of the art offers two
                 completely different methods: one relying on bit shifts
                 and additions/subtractions, and another one using
                 look-up tables and additions. So far, it was unclear
                 which method performs best for a given constant and
                 input/output data types. The main contribution of this
                 work is a thorough comparison of both methods in the
                 main application contexts of constant multiplication:
                 filters, signal-processing transforms, and elementary
                 functions. Most of the previous state of the art
                 addresses multiplication by an integer constant. This
                 work shows that, in most of these application contexts,
                 a formulation of the problem as the multiplication by a
                 real constant allows for more efficient architectures.
                 Another contribution is a novel extension of the
                 shift-and-add method to real constants. For that, an
                 integer linear programming (ILP) formulation is
                 proposed, which truncates each component in the
                 shift-and-add network to a minimum necessary word size
                 that is aligned with the approximation error of the
                 coefficient. All methods are implemented within the
                 open-source FloPoCo framework.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; approximation theory; ARITH-26; Complexity
                 theory; constant multiplier, FPGA, optimization, ILP;
                 Field programmable gate arrays; Field Programmable Gate
                 Arrays; field programmable gate arrays; FPGAs;
                 Hardware; integer linear programming; integer
                 programming; linear programming; look-up tables;
                 multiplying circuits; shift-and-add network;
                 signal-processing transforms; Table lookup; table
                 lookup; table-based versus shift-and-add constant
                 multipliers; Throughput",
}


bibtype: inproceedings
filename: fparith.bib
label: Didier:2019:RAP
title: Randomization of Arithmetic Over Polynomial Modular Number System
crossref: Takagi:2019:ISC
pages: 199--206
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00048
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawtitle: Randomization of Arithmetic Over Polynomial Modular Number System
author:
Laurent-Stephane Didier and Fangan-Yssouf Dosso and Nadia El Mrabet and Jeremy Marrez and Pascal Veron

abstract:
The Polynomial Modular Number System (PMNS) is an integer number system designed to speed up arithmetic operations modulo a prime p. Such a system is defined by a tuple B = (p, n, , , E) where E Z[X] and E() = 0 mod p. In a PMNS, an element a of Z/pZ is represented by a polynomial A such that: A() = a mod p, deg A <; n ||A|| <; p. In [6], the authors mentioned that PMNS can be highly redundant but they didn't really take advantage of this possibility. In this paper we use, for the first time, the redundancy of PMNS to protect algorithms against Side Channel Attacks (SCA). More precisely, we focus on elliptic curve cryptography. We show how to randomize the modular multiplication in order to be safe against existing SCA and we demonstrate the resistance of our construction. We describe the generation of a PMNS while guaranteeing, for all elements of Z/pZ, the minimum number of distinct representations we want. We also show how to reach all these representations.

keywords:
ARITH-26; arithmetic operations; digital arithmetic; elliptic curve cryptography; Elliptic curve cryptography; Elliptic curves; integer number system; Lattices; Manganese; modular multiplication; PMNS; polynomial modular number system; Polynomial Modular Number System, Side Channel Countermeasure, Modular Arithmetic; polynomials; Protocols; public key cryptography; Resistance; side channel attacks; Side-channel attacks

rawabstract:
The Polynomial Modular Number System (PMNS) is an integer number system designed to speed up arithmetic operations modulo a prime p. Such a system is defined by a tuple B = (p, n, , , E) where E Z[X] and E() = 0 mod p. In a PMNS, an element a of Z/pZ is represented by a polynomial A such that: A() = a mod p, deg A <; n ||A|| <; p. In [6], the authors mentioned that PMNS can be highly redundant but they didn't really take advantage of this possibility. In this paper we use, for the first time, the redundancy of PMNS to protect algorithms against Side Channel Attacks (SCA). More precisely, we focus on elliptic curve cryptography. We show how to randomize the modular multiplication in order to be safe against existing SCA and we demonstrate the resistance of our construction. We describe the generation of a PMNS while guaranteeing, for all elements of Z/pZ, the minimum number of distinct representations we want. We also show how to reach all these representations.

rawauthor:
Laurent-Stephane Didier and Fangan-Yssouf Dosso and Nadia {El Mrabet} and Jeremy Marrez and Pascal V{\'e}ron

entry:
@InProceedings{Didier:2019:RAP,
  author =       "Laurent-Stephane Didier and Fangan-Yssouf Dosso and
                 Nadia {El Mrabet} and Jeremy Marrez and Pascal
                 V{\'e}ron",
  title =        "Randomization of Arithmetic Over Polynomial Modular
                 Number System",
  crossref =     "Takagi:2019:ISC",
  pages =        "199--206",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00048",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Polynomial Modular Number System (PMNS) is an
                 integer number system designed to speed up arithmetic
                 operations modulo a prime p. Such a system is defined
                 by a tuple B = (p, n, , , E) where E Z[X] and E() = 0
                 mod p. In a PMNS, an element a of Z/pZ is represented
                 by a polynomial A such that: A() = a mod p, deg A <; n
                 ||A|| <; p. In [6], the authors mentioned that PMNS can
                 be highly redundant but they didn't really take
                 advantage of this possibility. In this paper we use,
                 for the first time, the redundancy of PMNS to protect
                 algorithms against Side Channel Attacks (SCA). More
                 precisely, we focus on elliptic curve cryptography. We
                 show how to randomize the modular multiplication in
                 order to be safe against existing SCA and we
                 demonstrate the resistance of our construction. We
                 describe the generation of a PMNS while guaranteeing,
                 for all elements of Z/pZ, the minimum number of
                 distinct representations we want. We also show how to
                 reach all these representations.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; arithmetic operations; digital arithmetic;
                 elliptic curve cryptography; Elliptic curve
                 cryptography; Elliptic curves; integer number system;
                 Lattices; Manganese; modular multiplication; PMNS;
                 polynomial modular number system; Polynomial Modular
                 Number System, Side Channel Countermeasure, Modular
                 Arithmetic; polynomials; Protocols; public key
                 cryptography; Resistance; side channel attacks;
                 Side-channel attacks",
}


bibtype: article
filename: fparith.bib
label: Diffenderfer:2019:EAZ
title: Error Analysis of ZFP Compression for Floating-Point Data
journal: j-SIAM-J-SCI-COMP
volume: 41
number: 3
pages: A1867--A1898
year: 2019
CODEN: SJOCE3
DOI: https://doi.org/10.1137/18M1168832
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Thu Oct 10 06:58:05 MDT 2019
bibtimestamp: 2019.10.10 06:58:05 MDT
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
onlinedate: January 2019
rawtitle: Error Analysis of {ZFP} Compression for Floating-Point Data
author:
James Diffenderfer and Alyson L. Fox and Jeffrey A. Hittinger and Geoffrey Sanders and Peter G. Lindstrom

bibsource:
http://epubs.siam.org/toc/sjoce3/41/3; https://www.math.utah.edu/pub/tex/bib/datacompression.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

rawauthor:
James Diffenderfer and Alyson L. Fox and Jeffrey A. Hittinger and Geoffrey Sanders and Peter G. Lindstrom

entry:
@Article{Diffenderfer:2019:EAZ,
  author =       "James Diffenderfer and Alyson L. Fox and Jeffrey A.
                 Hittinger and Geoffrey Sanders and Peter G. Lindstrom",
  title =        "Error Analysis of {ZFP} Compression for Floating-Point
                 Data",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "41",
  number =       "3",
  pages =        "A1867--A1898",
  month =        "????",
  year =         "2019",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/18M1168832",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Thu Oct 10 06:58:05 MDT 2019",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/41/3;
                 https://www.math.utah.edu/pub/tex/bib/datacompression.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  onlinedate =   "January 2019",
}


bibtype: inproceedings
filename: fparith.bib
label: Djath:2019:HAR
author: Libey Djath and Karim Bigou and Arnaud Tisserand
title: Hierarchical Approach in RNS Base Extension for Asymmetric Cryptography
crossref: Takagi:2019:ISC
pages: 46--53
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00016
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Libey Djath and Karim Bigou and Arnaud Tisserand
rawtitle: Hierarchical Approach in {RNS} Base Extension for Asymmetric Cryptography
abstract:
Base extension is a critical operation in RNS implementations of asymmetric cryptosystems. In this paper, we propose a new way to perform base extensions using a hierarchical approach for computing the Chinese remainder theorem. For well chosen parameters, it significantly reduces the computational cost and still ensures a high level of internal parallelism. We illustrate the interest of the proposed approach on the cost of typical arithmetic primitives used in asymmetric cryptography. We also demonstrate improvements in FPGA implementations of base extensions on typical elliptic curve cryptography field sizes using high-level synthesis tools.

keywords:
ARITH-26; asymmetric cryptosystems; Cathode ray tubes; Chinese remainder theorem; Computer architecture; computer arithmetic; cryptography; Elliptic curve cryptography; elliptic curve cryptography field sizes; field programmable gate arrays; FPGA implementations; hardware implementation; high level synthesis; high-level synthesis tools; modular reduction; Parallel processing; residue number system; residue number systems; RNS base extension; RNS implementations; Signal processing algorithms; Standards

rawabstract:
Base extension is a critical operation in RNS implementations of asymmetric cryptosystems. In this paper, we propose a new way to perform base extensions using a hierarchical approach for computing the Chinese remainder theorem. For well chosen parameters, it significantly reduces the computational cost and still ensures a high level of internal parallelism. We illustrate the interest of the proposed approach on the cost of typical arithmetic primitives used in asymmetric cryptography. We also demonstrate improvements in FPGA implementations of base extensions on typical elliptic curve cryptography field sizes using high-level synthesis tools.

entry:
@InProceedings{Djath:2019:HAR,
  author =       "Libey Djath and Karim Bigou and Arnaud Tisserand",
  title =        "Hierarchical Approach in {RNS} Base Extension for
                 Asymmetric Cryptography",
  crossref =     "Takagi:2019:ISC",
  pages =        "46--53",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00016",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Base extension is a critical operation in RNS
                 implementations of asymmetric cryptosystems. In this
                 paper, we propose a new way to perform base extensions
                 using a hierarchical approach for computing the Chinese
                 remainder theorem. For well chosen parameters, it
                 significantly reduces the computational cost and still
                 ensures a high level of internal parallelism. We
                 illustrate the interest of the proposed approach on the
                 cost of typical arithmetic primitives used in
                 asymmetric cryptography. We also demonstrate
                 improvements in FPGA implementations of base extensions
                 on typical elliptic curve cryptography field sizes
                 using high-level synthesis tools.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; asymmetric cryptosystems; Cathode ray tubes;
                 Chinese remainder theorem; Computer architecture;
                 computer arithmetic; cryptography; Elliptic curve
                 cryptography; elliptic curve cryptography field sizes;
                 field programmable gate arrays; FPGA implementations;
                 hardware implementation; high level synthesis;
                 high-level synthesis tools; modular reduction; Parallel
                 processing; residue number system; residue number
                 systems; RNS base extension; RNS implementations;
                 Signal processing algorithms; Standards",
}


bibtype: misc
filename: fparith.bib
label: Dockrill:2019:CMH
author: Peter Dockrill
title: Computers Are Making Huge Mistakes Because They Can't Understand Chaos, Scientists Warn
pages: 46--53
day: 27
month: sep
monthnumber: 9
year: 2019
bibdate: Mon Sep 30 11:25:59 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.30 11:25:59 ???
note: See cite Boghosian:2019:NPS.
acknowledgement: ack-nhfb
howpublished: ScienceAlert Web site
rawauthor: Peter Dockrill
rawnote: See \cite{Boghosian:2019:NPS}.
rawtitle: Computers Are Making Huge Mistakes Because They Can't Understand Chaos, Scientists Warn
URL:
https://www.sciencealert.com/computers-are-making-huge-mistakes-because-they-can-t-understand-chaos-scientists-warn

entry:
@Misc{Dockrill:2019:CMH,
  author =       "Peter Dockrill",
  title =        "Computers Are Making Huge Mistakes Because They Can't
                 Understand Chaos, Scientists Warn",
  howpublished = "ScienceAlert Web site",
  day =          "27",
  month =        sep,
  year =         "2019",
  bibdate =      "Mon Sep 30 11:25:59 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Boghosian:2019:NPS}.",
  URL =          "https://www.sciencealert.com/computers-are-making-huge-mistakes-because-they-can-t-understand-chaos-scientists-warn",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Ensor:2019:BNB
author: Andrew Ensor
title: Big Numbers for a Big Universe
crossref: Takagi:2019:ISC
pages: 99--99
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00026
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Andrew Ensor
rawtitle: Big Numbers for a Big Universe
abstract:
The Square Kilometre Array is the world's largest mega-Science project of the next decade aiming to build enormous radio telescope arrays across Western Australia and Southern Africa. With 160 TeraByte/sec data generated in just stage one of the 50 year project and over 260 PetaFLOPS compute requirements it presents unprecedented data movement and processing challenges in its correlators, the detection and timing of pulsars, supercomputing pipelines for generating images, and scalable middleware. This talk will outline the project and its scientific goals, some of the key data processing pipelines, and will discuss the progress made by the design teams toward overcoming its computing challenges.

keywords:
Africa; ARITH-26; Arrays; Australia; big numbers; big universe; computing challenges; design teams; Digital arithmetic; generating images; High performance computing; key data processing pipelines; mega-Science project; middleware; parallel machines; PetaFLOPS compute requirements; Pipelines; processing challenges; Radio astronomy; radio telescope arrays; radiotelescopes; scalable middleware; scientific goals; Southern Africa; Square Kilometre Array; supercomputing pipelines; time 50.0 year; unprecedented data movement; Western Australia

rawabstract:
The Square Kilometre Array is the world's largest mega-Science project of the next decade aiming to build enormous radio telescope arrays across Western Australia and Southern Africa. With 160 TeraByte/sec data generated in just stage one of the 50 year project and over 260 PetaFLOPS compute requirements it presents unprecedented data movement and processing challenges in its correlators, the detection and timing of pulsars, supercomputing pipelines for generating images, and scalable middleware. This talk will outline the project and its scientific goals, some of the key data processing pipelines, and will discuss the progress made by the design teams toward overcoming its computing challenges.

entry:
@InProceedings{Ensor:2019:BNB,
  author =       "Andrew Ensor",
  title =        "Big Numbers for a Big Universe",
  crossref =     "Takagi:2019:ISC",
  pages =        "99--99",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00026",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Square Kilometre Array is the world's largest
                 mega-Science project of the next decade aiming to build
                 enormous radio telescope arrays across Western
                 Australia and Southern Africa. With 160 TeraByte/sec
                 data generated in just stage one of the 50 year project
                 and over 260 PetaFLOPS compute requirements it presents
                 unprecedented data movement and processing challenges
                 in its correlators, the detection and timing of
                 pulsars, supercomputing pipelines for generating
                 images, and scalable middleware. This talk will outline
                 the project and its scientific goals, some of the key
                 data processing pipelines, and will discuss the
                 progress made by the design teams toward overcoming its
                 computing challenges.",
  acknowledgement = ack-nhfb,
  keywords =     "Africa; ARITH-26; Arrays; Australia; big numbers; big
                 universe; computing challenges; design teams; Digital
                 arithmetic; generating images; High performance
                 computing; key data processing pipelines; mega-Science
                 project; middleware; parallel machines; PetaFLOPS
                 compute requirements; Pipelines; processing challenges;
                 Radio astronomy; radio telescope arrays;
                 radiotelescopes; scalable middleware; scientific goals;
                 Southern Africa; Square Kilometre Array; supercomputing
                 pipelines; time 50.0 year; unprecedented data movement;
                 Western Australia",
}


bibtype: article
filename: fparith.bib
label: Fabiano:2019:ATW
author: Nicolas Fabiano and Jean-Michel Muller and Joris Picot
title: Algorithms for Triple-Word Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 11
pages: 1573--1583
month: nov
monthnumber: 11
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2918451
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Oct 29 11:08:44 2019
bibtimestamp: 2019.10.29 11:08:44 ???
URL: https://hal.archives-ouvertes.fr/hal-01869009v2
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Nicolas Fabiano and Jean-Michel Muller and Joris Picot
rawtitle: Algorithms for Triple-Word Arithmetic
abstract:
Triple-word arithmetic consists in representing high-precision numbers as the unevaluated sum of three floating-point numbers (with nonoverlapping constraints that are explicited in the paper). We introduce and analyze various algorithms for manipulating triple-word numbers: rounding a triple-word number to a floating-point number, adding, multiplying, dividing, and computing square-roots of triple-word numbers, etc. We compare our algorithms, implemented in the Campary library, with other solutions of comparable accuracy. It turns out that our new algorithms are significantly faster than what one would obtain by just using the usual floating-point expansion algorithms in the special case of expansions of length 3.

keywords:
Computer arithmetic, floating-point arithmetic, triple-word arithmetic; Floating-point arithmetic; Libraries; Lips; Memory management; Physics; Programming; Standards

rawabstract:
Triple-word arithmetic consists in representing high-precision numbers as the unevaluated sum of three floating-point numbers (with nonoverlapping constraints that are explicited in the paper). We introduce and analyze various algorithms for manipulating triple-word numbers: rounding a triple-word number to a floating-point number, adding, multiplying, dividing, and computing square-roots of triple-word numbers, etc. We compare our algorithms, implemented in the Campary library, with other solutions of comparable accuracy. It turns out that our new algorithms are significantly faster than what one would obtain by just using the usual floating-point expansion algorithms in the special case of expansions of length 3.

entry:
@Article{Fabiano:2019:ATW,
  author =       "Nicolas Fabiano and Jean-Michel Muller and Joris
                 Picot",
  title =        "Algorithms for Triple-Word Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "11",
  pages =        "1573--1583",
  month =        nov,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2918451",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Oct 29 11:08:44 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "https://hal.archives-ouvertes.fr/hal-01869009v2",
  abstract =     "Triple-word arithmetic consists in representing
                 high-precision numbers as the unevaluated sum of three
                 floating-point numbers (with nonoverlapping constraints
                 that are explicited in the paper). We introduce and
                 analyze various algorithms for manipulating triple-word
                 numbers: rounding a triple-word number to a
                 floating-point number, adding, multiplying, dividing,
                 and computing square-roots of triple-word numbers, etc.
                 We compare our algorithms, implemented in the Campary
                 library, with other solutions of comparable accuracy.
                 It turns out that our new algorithms are significantly
                 faster than what one would obtain by just using the
                 usual floating-point expansion algorithms in the
                 special case of expansions of length 3.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Computer arithmetic, floating-point arithmetic,
                 triple-word arithmetic; Floating-point arithmetic;
                 Libraries; Lips; Memory management; Physics;
                 Programming; Standards",
}


bibtype: misc
filename: fparith.bib
label: Feldman:2019:NAC
author: Michael Feldman
title: New Approach Could Sink Floating Point Computation
pages: 1573--1583
day: 8
month: jul
monthnumber: 7
year: 2019
bibdate: Tue Jul 09 10:28:21 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.07.09 10:28:21 ???
URL: https://www.nextplatform.com/2019/07/08/new-approach-could-sink-floating-point-computation/
remark: Interview with John L. Gustafson on Posits (universal numbers).
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Michael Feldman
rawtitle: New Approach Could Sink Floating Point Computation
entry:
@Misc{Feldman:2019:NAC,
  author =       "Michael Feldman",
  title =        "New Approach Could Sink Floating Point Computation",
  howpublished = "Web site",
  day =          "8",
  month =        jul,
  year =         "2019",
  bibdate =      "Tue Jul 09 10:28:21 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.nextplatform.com/2019/07/08/new-approach-could-sink-floating-point-computation/",
  acknowledgement = ack-nhfb,
  remark =       "Interview with John L. Gustafson on Posits (universal
                 numbers).",
}


bibtype: article
filename: fparith.bib
label: Flegar:2019:FCL
title: FloatX: A C++ Library for Customized Floating-Point Arithmetic
journal: j-TOMS
volume: 45
number: 4
pages: 40:1--40:??
month: dec
monthnumber: 12
year: 2019
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3368086
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Fri Dec 27 14:56:25 MST 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2019.12.27 14:56:25 MST
URL: https://dl.acm.org/citation.cfm?id=3368086
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 40
journalURL: https://dl.acm.org/loi/toms
rawtitle: {FloatX}: A {C++} Library for Customized Floating-Point Arithmetic
author:
Goran Flegar and Florian Scheidegger and Vedran Novakovic and Giovani Mariani and Andres E. Tomas and A. Cristiano I. Malossi and Enrique S. Quintana-Orti

abstract:
We present FloatX (Float eXtended), a C ++ framework to investigate the effect of leveraging customized floating-point formats in numerical applications. FloatX formats are based on binary IEEE 754 with smaller significand and exponent bit counts specified by the user. Among other properties, FloatX facilitates an incremental transformation of the code, relies on hardware-supported floating-point types as back-end to preserve efficiency, and incurs no storage overhead. The article discusses in detail the design principles, programming interface, and datatype casting rules behind FloatX. Furthermore, it demonstrates FloatX's usage and benefits via several case studies from well-known numerical dense linear algebra libraries, such as BLAS and LAPACK; the Ginkgo library for sparse linear systems; and two neural network applications related with image processing and text recognition.

rawabstract:
We present FloatX (Float eXtended), a C ++ framework to investigate the effect of leveraging customized floating-point formats in numerical applications. FloatX formats are based on binary IEEE 754 with smaller significand and exponent bit counts specified by the user. Among other properties, FloatX facilitates an incremental transformation of the code, relies on hardware-supported floating-point types as back-end to preserve efficiency, and incurs no storage overhead. The article discusses in detail the design principles, programming interface, and datatype casting rules behind FloatX. Furthermore, it demonstrates FloatX's usage and benefits via several case studies from well-known numerical dense linear algebra libraries, such as BLAS and LAPACK; the Ginkgo library for sparse linear systems; and two neural network applications related with image processing and text recognition.

rawauthor:
Goran Flegar and Florian Scheidegger and Vedran Novakovi{\'c} and Giovani Mariani and Andr{\'e}s E. Tom{\'a}s and A. Cristiano I. Malossi and Enrique S. Quintana-Ort{\'\i}

entry:
@Article{Flegar:2019:FCL,
  author =       "Goran Flegar and Florian Scheidegger and Vedran
                 Novakovi{\'c} and Giovani Mariani and Andr{\'e}s E.
                 Tom{\'a}s and A. Cristiano I. Malossi and Enrique S.
                 Quintana-Ort{\'\i}",
  title =        "{FloatX}: A {C++} Library for Customized
                 Floating-Point Arithmetic",
  journal =      j-TOMS,
  volume =       "45",
  number =       "4",
  pages =        "40:1--40:??",
  month =        dec,
  year =         "2019",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3368086",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Fri Dec 27 14:56:25 MST 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3368086",
  abstract =     "We present FloatX (Float eXtended), a C ++ framework
                 to investigate the effect of leveraging customized
                 floating-point formats in numerical applications.
                 FloatX formats are based on binary IEEE 754 with
                 smaller significand and exponent bit counts specified
                 by the user. Among other properties, FloatX facilitates
                 an incremental transformation of the code, relies on
                 hardware-supported floating-point types as back-end to
                 preserve efficiency, and incurs no storage overhead.
                 The article discusses in detail the design principles,
                 programming interface, and datatype casting rules
                 behind FloatX. Furthermore, it demonstrates FloatX's
                 usage and benefits via several case studies from
                 well-known numerical dense linear algebra libraries,
                 such as BLAS and LAPACK; the Ginkgo library for sparse
                 linear systems; and two neural network applications
                 related with image processing and text recognition.",
  acknowledgement = ack-nhfb,
  articleno =    "40",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: manual
filename: fparith.bib
label: Fog:2019:ITL
author: Agner Fog
organization: Technical University of Denmark
address: Lyngby, Denmark
pages: 367
day: 15
month: aug
monthnumber: 8
year: 2019
bibdate: Thu Jan 30 16:18:42 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.30 16:18:42 ???
URL: https://www.agner.org/optimize/instruction_tables.pdf
acknowledgement: ack-nhfb
rawauthor: Agner Fog
title:
4. Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD, and VIA CPUs

remark:
This is the fourth in a series of five manuals: 1. Optimizing software in C++: An optimization guide for Windows, Linux and Mac platforms. 2. Optimizing subroutines in assembly language: An optimization guide for x86 platforms. 3. The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers. 4. Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs. 5. Calling conventions for different C++ compilers and operating systems. The manuals are copyrighted from 1996 to 2019.

rawtitle:
4. {Instruction} tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for {Intel}, {AMD}, and {VIA CPUs}

entry:
@Manual{Fog:2019:ITL,
  author =       "Agner Fog",
  title =        "4. {Instruction} tables: Lists of instruction
                 latencies, throughputs and micro-operation breakdowns
                 for {Intel}, {AMD}, and {VIA CPUs}",
  organization = "Technical University of Denmark",
  address =      "Lyngby, Denmark",
  pages =        "367",
  day =          "15",
  month =        aug,
  year =         "2019",
  bibdate =      "Thu Jan 30 16:18:42 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.agner.org/optimize/instruction_tables.pdf",
  acknowledgement = ack-nhfb,
  remark =       "This is the fourth in a series of five manuals: 1.
                 Optimizing software in C++: An optimization guide for
                 Windows, Linux and Mac platforms. 2. Optimizing
                 subroutines in assembly language: An optimization guide
                 for x86 platforms. 3. The microarchitecture of Intel,
                 AMD and VIA CPUs: An optimization guide for assembly
                 programmers and compiler makers. 4. Instruction tables:
                 Lists of instruction latencies, throughputs and
                 micro-operation breakdowns for Intel, AMD and VIA CPUs.
                 5. Calling conventions for different C++ compilers and
                 operating systems. The manuals are copyrighted from
                 1996 to 2019.",
}


bibtype: article
filename: fparith.bib
label: Gallin:2019:GFP
author: G. Gallin and A. Tisserand
title: Generation of Finely-Pipelined GF($P$P) Multipliers for Flexible Curve Based Cryptography on FPGAs
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 11
pages: 1612--1622
month: nov
monthnumber: 11
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2920352
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Oct 29 11:08:44 2019
bibtimestamp: 2019.10.29 11:08:44 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: G. Gallin and A. Tisserand
keywords:
arithmetic operator generation; Clocks; Computer architecture; Cryptography; elliptic curve cryptography; Field programmable gate arrays; Hardware; Modular arithmetic; Montgomery multiplication; Pipelines; Tools

rawtitle:
Generation of Finely-Pipelined {GF($P$P)} Multipliers for Flexible Curve Based Cryptography on {FPGAs}

entry:
@Article{Gallin:2019:GFP,
  author =       "G. Gallin and A. Tisserand",
  title =        "Generation of Finely-Pipelined {GF($P$P)} Multipliers
                 for Flexible Curve Based Cryptography on {FPGAs}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "11",
  pages =        "1612--1622",
  month =        nov,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2920352",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Oct 29 11:08:44 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "arithmetic operator generation; Clocks; Computer
                 architecture; Cryptography; elliptic curve
                 cryptography; Field programmable gate arrays; Hardware;
                 Modular arithmetic; Montgomery multiplication;
                 Pipelines; Tools",
}


bibtype: inproceedings
filename: fparith.bib
label: Gorodecky:2019:EIM
author: Danila Gorodecky and Tiziano Villa
title: Efficient Implementation of Modular Division by Input Bit Splitting
crossref: Takagi:2019:ISC
pages: 54--60
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00017
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Danila Gorodecky and Tiziano Villa
rawtitle: Efficient Implementation of Modular Division by Input Bit Splitting
abstract:
Arithmetic operations, such as addition, multiplication, division and modular division, impact on the quality of arithmetic logic units and of the whole processor, with respect to area and delay of the circuit, power consumption, testability. In this article we propose an algorithm to implement efficiently the operation of modular division (X (mod P)), where P is pre-selected. The proposed approach is based on splitting the input operands into smaller binary tuples and then minimizing in parallel the two-level form of each suboperation on the tuples of the decomposition. The experiments show gains in performance and area of our approach vs. to circuits synthesized by state-of-art EDA tools with an advantage in delay and area up to 30 times.

keywords:
ARITH-26; arithmetic logic units; Boolean functions; Complexity theory; computer arithmetic, multiplication, modular division, logic minimization; Delays; digital arithmetic; dividing circuits; EDA tools; input bit splitting; input operands; logic design; Minimization; modular division; Partitioning algorithms; Power demand; smaller binary tuples; Tools

rawabstract:
Arithmetic operations, such as addition, multiplication, division and modular division, impact on the quality of arithmetic logic units and of the whole processor, with respect to area and delay of the circuit, power consumption, testability. In this article we propose an algorithm to implement efficiently the operation of modular division (X (mod P)), where P is pre-selected. The proposed approach is based on splitting the input operands into smaller binary tuples and then minimizing in parallel the two-level form of each suboperation on the tuples of the decomposition. The experiments show gains in performance and area of our approach vs. to circuits synthesized by state-of-art EDA tools with an advantage in delay and area up to 30 times.

entry:
@InProceedings{Gorodecky:2019:EIM,
  author =       "Danila Gorodecky and Tiziano Villa",
  title =        "Efficient Implementation of Modular Division by Input
                 Bit Splitting",
  crossref =     "Takagi:2019:ISC",
  pages =        "54--60",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00017",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Arithmetic operations, such as addition,
                 multiplication, division and modular division, impact
                 on the quality of arithmetic logic units and of the
                 whole processor, with respect to area and delay of the
                 circuit, power consumption, testability. In this
                 article we propose an algorithm to implement
                 efficiently the operation of modular division (X (mod
                 P)), where P is pre-selected. The proposed approach is
                 based on splitting the input operands into smaller
                 binary tuples and then minimizing in parallel the
                 two-level form of each suboperation on the tuples of
                 the decomposition. The experiments show gains in
                 performance and area of our approach vs. to circuits
                 synthesized by state-of-art EDA tools with an advantage
                 in delay and area up to 30 times.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; arithmetic logic units; Boolean functions;
                 Complexity theory; computer arithmetic, multiplication,
                 modular division, logic minimization; Delays; digital
                 arithmetic; dividing circuits; EDA tools; input bit
                 splitting; input operands; logic design; Minimization;
                 modular division; Partitioning algorithms; Power
                 demand; smaller binary tuples; Tools",
}


bibtype: article
filename: fparith.bib
label: Graillat:2019:ATF
author: Stef Graillat and Fabienne Jezequel and Romain Picot and Francois Fevotte and Bruno Lathuiliere
title: Auto-tuning for floating-point precision with Discrete Stochastic Arithmetic
journal: j-J-COMPUT-SCI
volume: 36
pages: ??--??
month: sep
monthnumber: 9
year: 2019
DOI: https://doi.org/10.1016/j.jocs.2019.07.004
ISSN: 1877-7503 (print), 1877-7511 (electronic) OR 18777503 (print), 18777511 (electronic)
ISSNL: 1877-7503 OR 18777503
MRclass: 65Y20 (65C50)
MRnumber: 4007597
bibdate: Tue Sep 19 13:55:19 MDT 2023
bibtimestamp: 2023.09.19 13:55:19 MDT
URL: https://www.sciencedirect.com/science/article/pii/S1877750318309475
fjournal: Journal of Computational Science
acknowledgement: ack-nhfb
ajournal: J. Comput. Sci.
articleno: 101017
journalURL: https://www.sciencedirect.com/journal/journal-of-computational-science
rawtitle: Auto-tuning for floating-point precision with {Discrete Stochastic Arithmetic}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputsci.bib

rawauthor:
Stef Graillat and Fabienne J{\'e}z{\'e}quel and Romain Picot and Fran{\c{c}}ois F{\'e}votte and Bruno Lathuili{\`e}re

entry:
@Article{Graillat:2019:ATF,
  author =       "Stef Graillat and Fabienne J{\'e}z{\'e}quel and Romain
                 Picot and Fran{\c{c}}ois F{\'e}votte and Bruno
                 Lathuili{\`e}re",
  title =        "Auto-tuning for floating-point precision with
                 {Discrete Stochastic Arithmetic}",
  journal =      j-J-COMPUT-SCI,
  volume =       "36",
  pages =        "??--??",
  month =        sep,
  year =         "2019",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1016/j.jocs.2019.07.004",
  ISSN =         "1877-7503 (print), 1877-7511 (electronic)",
  ISSN-L =       "1877-7503",
  MRclass =      "65Y20 (65C50)",
  MRnumber =     "4007597",
  bibdate =      "Tue Sep 19 13:55:19 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputsci.bib",
  URL =          "https://www.sciencedirect.com/science/article/pii/S1877750318309475",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Comput. Sci.",
  articleno =    "101017",
  fjournal =     "Journal of Computational Science",
  journal-URL =  "https://www.sciencedirect.com/journal/journal-of-computational-science",
  pagecount =    "11",
}


bibtype: misc
filename: fparith.bib
label: Grossman:2019:CSC
author: David Grossman
title: Computers Suck at Creating Chaos
pages: ??--??
day: 30
month: sep
monthnumber: 9
year: 2019
bibdate: Tue Oct 01 08:57:55 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.01 08:57:55 ???
note: See cite Boghosian:2019:NPS.
URL: https://www.popularmechanics.com/science/a29271351/computers-chaotic-systems/
acknowledgement: ack-nhfb
howpublished: Popular Mechanics Web site
rawauthor: David Grossman
rawnote: See \cite{Boghosian:2019:NPS}.
rawtitle: Computers Suck at Creating Chaos
entry:
@Misc{Grossman:2019:CSC,
  author =       "David Grossman",
  title =        "Computers Suck at Creating Chaos",
  howpublished = "Popular Mechanics Web site",
  day =          "30",
  month =        sep,
  year =         "2019",
  bibdate =      "Tue Oct 01 08:57:55 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "See \cite{Boghosian:2019:NPS}.",
  URL =          "https://www.popularmechanics.com/science/a29271351/computers-chaotic-systems/",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Gu:2019:GRM
author: Z. Gu and S. Li
title: A Generalized RNS Mclaughlin Modular Multiplication with Non-Coprime Moduli Sets
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 11
pages: 1689--1696
month: nov
monthnumber: 11
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2917433
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Oct 29 11:08:44 2019
bibtimestamp: 2019.10.29 11:08:44 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Z. Gu and S. Li
rawtitle: A Generalized {RNS} {Mclaughlin} Modular Multiplication with Non-Coprime Moduli Sets
keywords:
Digital arithmetic; Elliptic curve cryptography; Indexes; McLaughlin modular multiplication; Microelectronics; Montgomery modular multiplication; Performance evaluation; Residue number systems

entry:
@Article{Gu:2019:GRM,
  author =       "Z. Gu and S. Li",
  title =        "A Generalized {RNS} {Mclaughlin} Modular
                 Multiplication with Non-Coprime Moduli Sets",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "11",
  pages =        "1689--1696",
  month =        nov,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2917433",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Oct 29 11:08:44 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Digital arithmetic; Elliptic curve cryptography;
                 Indexes; McLaughlin modular multiplication;
                 Microelectronics; Montgomery modular multiplication;
                 Performance evaluation; Residue number systems",
}


bibtype: article
filename: fparith.bib
label: Han:2019:FFE
author: Dong Han and Shengyuan Zhou and Tian Zhi and Yibo Wang and Shaoli Liu
title: Float-Fix: An Efficient and Hardware-Friendly Data Type for Deep Neural Network
journal: j-INT-J-PARALLEL-PROG
volume: 47
number: 3
pages: 345--359
month: jun
monthnumber: 6
year: 2019
CODEN: IJPPE5
DOI: https://doi.org/10.1007/s10766-018-00626-7
ISSN: 0885-7458 (print), 1573-7640 (electronic) OR 08857458 (print), 15737640 (electronic)
ISSNL: 0885-7458 OR 08857458
bibdate: Fri Oct 11 08:37:52 MDT 2019
bibtimestamp: 2019.10.11 08:37:52 MDT
fjournal: International Journal of Parallel Programming
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10766
rawauthor: Dong Han and Shengyuan Zhou and Tian Zhi and Yibo Wang and Shaoli Liu
rawtitle: {Float-Fix}: An Efficient and Hardware-Friendly Data Type for Deep Neural Network
bibsource:
http://link.springer.com/journal/10766/47/3; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/intjparallelprogram.bib

entry:
@Article{Han:2019:FFE,
  author =       "Dong Han and Shengyuan Zhou and Tian Zhi and Yibo Wang
                 and Shaoli Liu",
  title =        "{Float-Fix}: An Efficient and Hardware-Friendly Data
                 Type for Deep Neural Network",
  journal =      j-INT-J-PARALLEL-PROG,
  volume =       "47",
  number =       "3",
  pages =        "345--359",
  month =        jun,
  year =         "2019",
  CODEN =        "IJPPE5",
  DOI =          "https://doi.org/10.1007/s10766-018-00626-7",
  ISSN =         "0885-7458 (print), 1573-7640 (electronic)",
  ISSN-L =       "0885-7458",
  bibdate =      "Fri Oct 11 08:37:52 MDT 2019",
  bibsource =    "http://link.springer.com/journal/10766/47/3;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/intjparallelprogram.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of Parallel Programming",
  journal-URL =  "http://link.springer.com/journal/10766",
}


bibtype: article
filename: fparith.bib
label: Hanuman:2019:IMP
author: C. R. S. Hanuman and J. Kamala and A. R. Aruna
journal: j-J-SUPERCOMPUTING
volume: 75
number: 9
pages: 6038--6054
month: sep
monthnumber: 9
year: 2019
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-019-02902-w
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Thu Oct 10 15:31:22 MDT 2019
bibtimestamp: 2019.10.10 15:31:22 MDT
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11227
rawauthor: C. R. S. Hanuman and J. Kamala and A. R. Aruna
title:
Implementation of multi-precision floating point divider for high speed signal processing applications

bibsource:
http://link.springer.com/journal/11227/75/9; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jsuper.bib

rawtitle:
Implementation of multi-precision floating point divider for high speed signal processing applications

entry:
@Article{Hanuman:2019:IMP,
  author =       "C. R. S. Hanuman and J. Kamala and A. R. Aruna",
  title =        "Implementation of multi-precision floating point
                 divider for high speed signal processing applications",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "75",
  number =       "9",
  pages =        "6038--6054",
  month =        sep,
  year =         "2019",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-019-02902-w",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Thu Oct 10 15:31:22 MDT 2019",
  bibsource =    "http://link.springer.com/journal/11227/75/9;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: misc
filename: fparith.bib
label: Harthcock:2019:BUF
author: Jerry D. Harthcock
title: 64-bit-Universal-Floating-Point-ISA-Compute-Engine
pages: 6038--6054
day: 8
month: oct
monthnumber: 10
year: 2019
bibdate: Wed Oct 09 05:34:48 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.09 05:34:48 ???
URL: https://github.com/jerry-D/64-bit-Universal-Floating-Point-ISA-Compute-Engine
acknowledgement: ack-nhfb
howpublished: Github Web site.
rawauthor: Jerry D. Harthcock
rawtitle: {64-bit-Universal-Floating-Point-ISA-Compute-Engine}
abstract:
New 64-bit Universal Floating-Point ISA Compute Engine computes directly with human-readable decimal character sequences, binary64, 32, 16 or bfloat16 formatted numbers in any combination.

rawabstract:
New 64-bit Universal Floating-Point ISA Compute Engine computes directly with human-readable decimal character sequences, binary64, 32, 16 or bfloat16 formatted numbers in any combination.

entry:
@Misc{Harthcock:2019:BUF,
  author =       "Jerry D. Harthcock",
  title =        "{64-bit-Universal-Floating-Point-ISA-Compute-Engine}",
  howpublished = "Github Web site.",
  day =          "8",
  month =        oct,
  year =         "2019",
  bibdate =      "Wed Oct 09 05:34:48 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://github.com/jerry-D/64-bit-Universal-Floating-Point-ISA-Compute-Engine",
  abstract =     "New 64-bit Universal Floating-Point ISA Compute Engine
                 computes directly with human-readable decimal character
                 sequences, binary64, 32, 16 or bfloat16 formatted
                 numbers in any combination.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Harvey:2019:FIM
author: David Harvey and Joris van der Hoeven
title: Faster integer multiplication using plain vanilla FFT primes
journal: j-MATH-COMPUT
volume: 88
number: 315
pages: 501--514
month: jul
monthnumber: 7
year: 2019
CODEN: MCMPAF
DOI: https://doi.org/10.1090/mcom/3328
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Tue Jul 14 06:45:34 MDT 2020
bibtimestamp: 2020.07.14 06:45:34 MDT
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: David Harvey and Joris van der Hoeven
rawtitle: Faster integer multiplication using plain vanilla {FFT} primes
bibsource:
http://www.ams.org/mcom/2019-88-315; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib

URL:
https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03328-2; https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03328-2/S0025-5718-2018-03328-2.pdf; https://www.ams.org/mathscinet/search/authors.html?mrauthid=621578; https://www.ams.org/mathscinet/search/authors.html?mrauthid=734771

entry:
@Article{Harvey:2019:FIM,
  author =       "David Harvey and Joris van der Hoeven",
  title =        "Faster integer multiplication using plain vanilla
                 {FFT} primes",
  journal =      j-MATH-COMPUT,
  volume =       "88",
  number =       "315",
  pages =        "501--514",
  month =        jul,
  year =         "2019",
  CODEN =        "MCMPAF",
  DOI =          "https://doi.org/10.1090/mcom/3328",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Tue Jul 14 06:45:34 MDT 2020",
  bibsource =    "http://www.ams.org/mcom/2019-88-315;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib",
  URL =          "https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03328-2;
                 https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03328-2/S0025-5718-2018-03328-2.pdf;
                 https://www.ams.org/mathscinet/search/authors.html?mrauthid=621578;
                 https://www.ams.org/mathscinet/search/authors.html?mrauthid=734771",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
}


bibtype: techreport
filename: fparith.bib
label: Harvey:2019:IMT
author: David Harvey and Joris Van Der Hoeven
title: Integer multiplication in time $ O(n log n) $
type: Report
number: hal-02070778
address: Sydney, NSW 2052, Australia and 91128 Palaiseau, France
pages: 501--514
day: 18
month: mar
monthnumber: 3
year: 2019
bibdate: Fri Apr 12 14:09:18 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.04.12 14:09:18 ???
URL: https://hal.archives-ouvertes.fr/hal-02070778/document
acknowledgement: ack-nhfb
rawauthor: David Harvey and Joris {Van Der Hoeven}
rawtitle: Integer multiplication in time {$ O(n \log n) $}
institution:
School of Mathematics and Statistics, University of New South Wales, and CNRS, Laboratoire d'informatique, Ecole polytechnique

abstract:
We present an algorithm that computes the product of two $n$-bit integers in $ O(n log n)$ bit operations.

rawabstract:
We present an algorithm that computes the product of two $n$-bit integers in $ O(n \log n)$ bit operations.

entry:
@TechReport{Harvey:2019:IMT,
  author =       "David Harvey and Joris {Van Der Hoeven}",
  title =        "Integer multiplication in time {$ O(n \log n) $}",
  type =         "Report",
  number =       "hal-02070778",
  institution =  "School of Mathematics and Statistics, University of
                 New South Wales, and CNRS, Laboratoire d'informatique,
                 {\'E}cole polytechnique",
  address =      "Sydney, NSW 2052, Australia and 91128 Palaiseau,
                 France",
  day =          "18",
  month =        mar,
  year =         "2019",
  bibdate =      "Fri Apr 12 14:09:18 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.archives-ouvertes.fr/hal-02070778/document",
  abstract =     "We present an algorithm that computes the product of
                 two $n$-bit integers in $ O(n \log n)$ bit
                 operations.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Hayes:2019:DCB
author: Ari B. Hayes and Fei Hua and Jin Huang and Yanhao Chen and Eddy Z. Zhang
editor: Mahmut Taylan Kandemir and Alexandra Jimborean and Tipp Moseley
title: Decoding CUDA Binary
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 229--241
year: 2019
DOI: https://doi.org/10.1109/cgo.2019.8661186
ISBN: 1-72811-436-5, 1-72811-437-3 OR 1728114365, 1728114373
ISBN13: 978-1-72811-436-1, 978-1-72811-437-8 OR 9781728114361, 9781728114378
LCCN: QA76.76.G46 I57 2019
bibdate: Mon Sep 11 06:57:08 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 06:57:08 ???
note: IEEE Catalog Number CFP19CGO-ART.
URL: https://ieeexplore.ieee.org/document/8661186
acknowledgement: ack-nhfb
bookDOI: https://doi.org/10.1109/CGO46174.2019
bookpages: xv + 287
rawauthor: Ari B. Hayes and Fei Hua and Jin Huang and Yanhao Chen and Eddy Z. Zhang
raweditor: Mahmut Taylan Kandemir and Alexandra Jimborean and Tipp Moseley
rawnote: IEEE Catalog Number CFP19CGO-ART.
rawtitle: Decoding {CUDA} Binary
booktitle:
CGO'19: Proceedings of the 2019 IEEE / ACM International Symposium on Code Generation and Optimization, 16--20 February 2019, Washington, DC, USA

abstract:
NVIDIA's software does not offer translation of assembly code to binary for their GPUs, since the specifications are closed-source. This work fills that gap. We develop a systematic method of decoding the Instruction Set Architectures (ISAs) of NVIDIA's GPUs, and generating assemblers for different generations of GPUs. Our framework enables cross-architecture binary analysis and transformation. Making the ISA accessible in this manner opens up a world of opportunities for developers and researchers, enabling numerous optimizations and explorations that are unachievable at the source-code level. Our infrastructure has already benefited and been adopted in important applications including performance tuning, binary instrumentation, resource allocation, and memory protection.

rawabstract:
NVIDIA's software does not offer translation of assembly code to binary for their GPUs, since the specifications are closed-source. This work fills that gap. We develop a systematic method of decoding the Instruction Set Architectures (ISAs) of NVIDIA's GPUs, and generating assemblers for different generations of GPUs. Our framework enables cross-architecture binary analysis and transformation. Making the ISA accessible in this manner opens up a world of opportunities for developers and researchers, enabling numerous optimizations and explorations that are unachievable at the source-code level. Our infrastructure has already benefited and been adopted in important applications including performance tuning, binary instrumentation, resource allocation, and memory protection.

rawbooktitle:
{CGO'19: Proceedings of the 2019 IEEE\slash ACM International Symposium on Code Generation and Optimization, 16--20 February 2019, Washington, DC, USA}

entry:
@InProceedings{Hayes:2019:DCB,
  author =       "Ari B. Hayes and Fei Hua and Jin Huang and Yanhao Chen
                 and Eddy Z. Zhang",
  editor =       "Mahmut Taylan Kandemir and Alexandra Jimborean and
                 Tipp Moseley",
  booktitle =    "{CGO'19: Proceedings of the 2019 IEEE\slash ACM
                 International Symposium on Code Generation and
                 Optimization, 16--20 February 2019, Washington, DC,
                 USA}",
  title =        "Decoding {CUDA} Binary",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  bookpages =    "xv + 287",
  pages =        "229--241",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/cgo.2019.8661186",
  ISBN =         "1-72811-436-5, 1-72811-437-3",
  ISBN-13 =      "978-1-72811-436-1, 978-1-72811-437-8",
  LCCN =         "QA76.76.G46 I57 2019",
  bibdate =      "Mon Sep 11 06:57:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "IEEE Catalog Number CFP19CGO-ART.",
  URL =          "https://ieeexplore.ieee.org/document/8661186",
  abstract =     "NVIDIA's software does not offer translation of
                 assembly code to binary for their GPUs, since the
                 specifications are closed-source. This work fills that
                 gap. We develop a systematic method of decoding the
                 Instruction Set Architectures (ISAs) of NVIDIA's GPUs,
                 and generating assemblers for different generations of
                 GPUs. Our framework enables cross-architecture binary
                 analysis and transformation. Making the ISA accessible
                 in this manner opens up a world of opportunities for
                 developers and researchers, enabling numerous
                 optimizations and explorations that are unachievable at
                 the source-code level. Our infrastructure has already
                 benefited and been adopted in important applications
                 including performance tuning, binary instrumentation,
                 resource allocation, and memory protection.",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1109/CGO46174.2019",
}


bibtype: inproceedings
filename: fparith.bib
label: Henry:2019:LBA
author: Greg Henry and Ping Tak Peter Tang and Alexander Heinecke
title: Leveraging the bfloat16 Artificial Intelligence Datatype For Higher-Precision Computations
crossref: Takagi:2019:ISC
pages: 69--76
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00019
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Greg Henry and Ping Tak Peter Tang and Alexander Heinecke
rawtitle: Leveraging the bfloat16 Artificial Intelligence Datatype For Higher-Precision Computations
abstract:
In recent years fused-multiply-add (FMA) units with lower-precision multiplications and higher-precision accumulation have proven useful in machine learning/artificial intelligence applications, most notably in training deep neural networks due to their extreme computational intensity. Compared to classical IEEE-754 32 bit (FP32) and 64 bit (FP64) arithmetic, these reduced precision arithmetic can naturally be sped up disproportional to their shortened width. The common strategy of all major hardware vendors is to aggressively further enhance their performance disproportionately. One particular FMA operation that multiplies two BF16 numbers while accumulating in FP32 has been found useful in deep learning, where BF16 is the 16-bit floating point datatype with IEEE FP32 numerical range but 8 significant bits of precision. In this paper, we examine the use this FMA unit to implement higher-precision matrix routines in terms of potential performance gain and implications on accuracy. We demonstrate how a decomposition into multiple smaller datatypes can be used to assemble a high-precision result, leveraging the higher precision accumulation of the FMA unit. We first demonstrate that computations of vector inner products and by natural extension, matrix-matrix products can be achieved by decomposing FP32 numbers in several BF16 numbers followed by appropriate computations that can accommodate the dynamic range and preserve accuracy compared to standard FP32 computations, while projecting up to 5.2x speed-up. Furthermore, we examine solution of linear equations formulated in the residual form that allows for iterative refinement. We demonstrate that the solution obtained to be comparable to those offered by FP64 under a large range of linear system condition numbers.

keywords:
ARITH-26; artificial intelligence datatype; bfloat16, float16, mixed precision, combined datatypes; Deep learning; deep learning; deep neural networks; floating point arithmetic; floating point datatype; FMA unit; FP32 computations; fused-multiply-add units; Hardware; higher-precision matrix routines; IEEE-754 32 bit arithmetic; IEEE-754 FP32 arithmetic; IEEE-754 FP64 arithmetic; iterative methods; learning (artificial intelligence); matrix algebra; Matrix decomposition; matrix-matrix products; neural nets; Neural networks; Standards; Task analysis; Training

rawabstract:
In recent years fused-multiply-add (FMA) units with lower-precision multiplications and higher-precision accumulation have proven useful in machine learning/artificial intelligence applications, most notably in training deep neural networks due to their extreme computational intensity. Compared to classical IEEE-754 32 bit (FP32) and 64 bit (FP64) arithmetic, these reduced precision arithmetic can naturally be sped up disproportional to their shortened width. The common strategy of all major hardware vendors is to aggressively further enhance their performance disproportionately. One particular FMA operation that multiplies two BF16 numbers while accumulating in FP32 has been found useful in deep learning, where BF16 is the 16-bit floating point datatype with IEEE FP32 numerical range but 8 significant bits of precision. In this paper, we examine the use this FMA unit to implement higher-precision matrix routines in terms of potential performance gain and implications on accuracy. We demonstrate how a decomposition into multiple smaller datatypes can be used to assemble a high-precision result, leveraging the higher precision accumulation of the FMA unit. We first demonstrate that computations of vector inner products and by natural extension, matrix-matrix products can be achieved by decomposing FP32 numbers in several BF16 numbers followed by appropriate computations that can accommodate the dynamic range and preserve accuracy compared to standard FP32 computations, while projecting up to 5.2x speed-up. Furthermore, we examine solution of linear equations formulated in the residual form that allows for iterative refinement. We demonstrate that the solution obtained to be comparable to those offered by FP64 under a large range of linear system condition numbers.

entry:
@InProceedings{Henry:2019:LBA,
  author =       "Greg Henry and Ping Tak Peter Tang and Alexander
                 Heinecke",
  title =        "Leveraging the bfloat16 Artificial Intelligence
                 Datatype For Higher-Precision Computations",
  crossref =     "Takagi:2019:ISC",
  pages =        "69--76",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00019",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In recent years fused-multiply-add (FMA) units with
                 lower-precision multiplications and higher-precision
                 accumulation have proven useful in machine
                 learning/artificial intelligence applications, most
                 notably in training deep neural networks due to their
                 extreme computational intensity. Compared to classical
                 IEEE-754 32 bit (FP32) and 64 bit (FP64) arithmetic,
                 these reduced precision arithmetic can naturally be
                 sped up disproportional to their shortened width. The
                 common strategy of all major hardware vendors is to
                 aggressively further enhance their performance
                 disproportionately. One particular FMA operation that
                 multiplies two BF16 numbers while accumulating in FP32
                 has been found useful in deep learning, where BF16 is
                 the 16-bit floating point datatype with IEEE FP32
                 numerical range but 8 significant bits of precision. In
                 this paper, we examine the use this FMA unit to
                 implement higher-precision matrix routines in terms of
                 potential performance gain and implications on
                 accuracy. We demonstrate how a decomposition into
                 multiple smaller datatypes can be used to assemble a
                 high-precision result, leveraging the higher precision
                 accumulation of the FMA unit. We first demonstrate that
                 computations of vector inner products and by natural
                 extension, matrix-matrix products can be achieved by
                 decomposing FP32 numbers in several BF16 numbers
                 followed by appropriate computations that can
                 accommodate the dynamic range and preserve accuracy
                 compared to standard FP32 computations, while
                 projecting up to 5.2x speed-up. Furthermore, we examine
                 solution of linear equations formulated in the residual
                 form that allows for iterative refinement. We
                 demonstrate that the solution obtained to be comparable
                 to those offered by FP64 under a large range of linear
                 system condition numbers.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; artificial intelligence datatype; bfloat16,
                 float16, mixed precision, combined datatypes; Deep
                 learning; deep learning; deep neural networks; floating
                 point arithmetic; floating point datatype; FMA unit;
                 FP32 computations; fused-multiply-add units; Hardware;
                 higher-precision matrix routines; IEEE-754 32 bit
                 arithmetic; IEEE-754 FP32 arithmetic; IEEE-754 FP64
                 arithmetic; iterative methods; learning (artificial
                 intelligence); matrix algebra; Matrix decomposition;
                 matrix-matrix products; neural nets; Neural networks;
                 Standards; Task analysis; Training",
}


bibtype: article
filename: fparith.bib
label: Hiasat:2019:DRI
author: Ahmad Hiasat and Leonel Sousa
journal: j-COMP-J
volume: 62
number: 2
pages: 292--300
day: 1
month: feb
monthnumber: 2
year: 2019
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/bxy119
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Mon Feb 11 10:50:41 MST 2019
bibtimestamp: 2019.02.11 10:50:41 MST
URL: http://academic.oup.com/comjnl/article/62/2/292/5224762
fjournal: Computer Journal
keywords: Residue Number System (RNS)
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
rawauthor: Ahmad Hiasat and Leonel Sousa
title:
On the Design of RNS Inter-Modulo Processing Units for the Arithmetic-Friendly Moduli Sets $ 2^n + k $, $ 2^n - 1 $, $ 2^n + 1 - 1 $

bibsource:
https://www.math.utah.edu/pub/tex/bib/compj2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
On the Design of {RNS} Inter-Modulo Processing Units for the Arithmetic-Friendly Moduli Sets $ 2^{n + k} $, $ 2^n - 1 $, $ 2^{n + 1} - 1 $

entry:
@Article{Hiasat:2019:DRI,
  author =       "Ahmad Hiasat and Leonel Sousa",
  title =        "On the Design of {RNS} Inter-Modulo Processing Units
                 for the Arithmetic-Friendly Moduli Sets $ 2^{n + k} $,
                 $ 2^n - 1 $, $ 2^{n + 1} - 1 $",
  journal =      j-COMP-J,
  volume =       "62",
  number =       "2",
  pages =        "292--300",
  day =          "1",
  month =        feb,
  year =         "2019",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/bxy119",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Mon Feb 11 10:50:41 MST 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compj2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://academic.oup.com/comjnl/article/62/2/292/5224762",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "Residue Number System (RNS)",
}


bibtype: inproceedings
filename: fparith.bib
label: Hickmann:2019:EAM
author: Brian Hickmann and Dennis Bradford
title: Experimental Analysis of Matrix Multiplication Functional Units
crossref: Takagi:2019:ISC
pages: 116--119
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00031
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Brian Hickmann and Dennis Bradford
rawtitle: Experimental Analysis of Matrix Multiplication Functional Units
abstract:
The rapid growth of AI has led to the introduction of several new hardware designs to accelerate the matrix multiplication operation at the heart of AI applications. Examples include NVIDIA's Tensor Core*, Google's TPU*, and Intel's Neural Compute Stick*. However, the IEEE 754 standard gives significant implementation-specific flexibility in the definition of the matrix multiplication operation and the precision and compatibility of these new accelerators is not well documented. This paper describes a method exploiting the rounding modes and other features of the IEEE 754 standard in order to gain deeper insight into the design and functionality of matrix multiplication units. We apply this method to the NVIDIA V100 GPU Tensor Core* units and report our findings on the design properties and micro-architecture.

keywords:
AI applications; ARITH-26; Deep learning; Google TPU; Graphics processing units; Hardware; hardware designs; IEEE 754 standard; IEEE standards; implementation-specific flexibility; Intel Neural Compute Stick; learning (artificial intelligence); Machine learning, deep learning, tensor, half precision, single precision, Volta, matrix multiplication; mathematics computing; matrix multiplication; matrix multiplication functional units; matrix multiplication units; Microarchitecture; neural nets; NVIDIA Tensor Core; NVIDIA V100 GPU Tensor Core units; Standards; Testing

rawabstract:
The rapid growth of AI has led to the introduction of several new hardware designs to accelerate the matrix multiplication operation at the heart of AI applications. Examples include NVIDIA's Tensor Core*, Google's TPU*, and Intel's Neural Compute Stick*. However, the IEEE 754 standard gives significant implementation-specific flexibility in the definition of the matrix multiplication operation and the precision and compatibility of these new accelerators is not well documented. This paper describes a method exploiting the rounding modes and other features of the IEEE 754 standard in order to gain deeper insight into the design and functionality of matrix multiplication units. We apply this method to the NVIDIA V100 GPU Tensor Core* units and report our findings on the design properties and micro-architecture.

entry:
@InProceedings{Hickmann:2019:EAM,
  author =       "Brian Hickmann and Dennis Bradford",
  title =        "Experimental Analysis of Matrix Multiplication
                 Functional Units",
  crossref =     "Takagi:2019:ISC",
  pages =        "116--119",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00031",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The rapid growth of AI has led to the introduction of
                 several new hardware designs to accelerate the matrix
                 multiplication operation at the heart of AI
                 applications. Examples include NVIDIA's Tensor Core*,
                 Google's TPU*, and Intel's Neural Compute Stick*.
                 However, the IEEE 754 standard gives significant
                 implementation-specific flexibility in the definition
                 of the matrix multiplication operation and the
                 precision and compatibility of these new accelerators
                 is not well documented. This paper describes a method
                 exploiting the rounding modes and other features of the
                 IEEE 754 standard in order to gain deeper insight into
                 the design and functionality of matrix multiplication
                 units. We apply this method to the NVIDIA V100 GPU
                 Tensor Core* units and report our findings on the
                 design properties and micro-architecture.",
  acknowledgement = ack-nhfb,
  keywords =     "AI applications; ARITH-26; Deep learning; Google TPU;
                 Graphics processing units; Hardware; hardware designs;
                 IEEE 754 standard; IEEE standards;
                 implementation-specific flexibility; Intel Neural
                 Compute Stick; learning (artificial intelligence);
                 Machine learning, deep learning, tensor, half
                 precision, single precision, Volta, matrix
                 multiplication; mathematics computing; matrix
                 multiplication; matrix multiplication functional units;
                 matrix multiplication units; Microarchitecture; neural
                 nets; NVIDIA Tensor Core; NVIDIA V100 GPU Tensor Core
                 units; Standards; Testing",
}


bibtype: article
filename: fparith.bib
label: Higham:2019:NAP
author: Nicholas J. Higham and Theo Mary
title: A New Approach to Probabilistic Rounding Error Analysis
journal: j-SIAM-J-SCI-COMP
volume: 41
number: 5
pages: A2815--A2835
year: 2019
CODEN: SJOCE3
DOI: https://doi.org/10.1137/18M1226312
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Tue Nov 5 05:24:19 MST 2019
bibtimestamp: 2019.11.05 05:24:19 MST
fjournal: SIAM Journal on Scientific Computing
keywords: floating-point arithmetic; MATLAB; numerical linear algebra; rounding error analysis
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
onlinedate: January 2019
rawauthor: Nicholas J. Higham and Theo Mary
rawtitle: A New Approach to Probabilistic Rounding Error Analysis
bibsource:
http://epubs.siam.org/toc/sjoce3/41/5; https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

entry:
@Article{Higham:2019:NAP,
  author =       "Nicholas J. Higham and Theo Mary",
  title =        "A New Approach to Probabilistic Rounding Error
                 Analysis",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "41",
  number =       "5",
  pages =        "A2815--A2835",
  month =        "????",
  year =         "2019",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/18M1226312",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Tue Nov 5 05:24:19 MST 2019",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/41/5;
                 https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "floating-point arithmetic; MATLAB; numerical linear
                 algebra; rounding error analysis",
  onlinedate =   "January 2019",
}


bibtype: article
filename: fparith.bib
label: Higham:2019:SLP
author: Nicholas J. Higham and Srikara Pranesh
title: Simulating Low Precision Floating-Point Arithmetic
journal: j-SIAM-J-SCI-COMP
volume: 41
number: 5
pages: C585--C602
year: 2019
CODEN: SJOCE3
DOI: https://doi.org/10.1137/19M1251308
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Tue Nov 5 05:24:19 MST 2019
bibtimestamp: 2019.11.05 05:24:19 MST
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
onlinedate: January 2019
rawauthor: Nicholas J. Higham and Srikara Pranesh
rawtitle: Simulating Low Precision Floating-Point Arithmetic
bibsource:
http://epubs.siam.org/toc/sjoce3/41/5; https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

keywords:
bfloat16; bit flips; directed rounding; floating-point arithmetic; fp16; half precision; IEEE arithmetic; low precision; MATLAB; mixed precision; round to nearest; rounding error analysis; simulation; stochastic rounding; subnormal numbers

entry:
@Article{Higham:2019:SLP,
  author =       "Nicholas J. Higham and Srikara Pranesh",
  title =        "Simulating Low Precision Floating-Point Arithmetic",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "41",
  number =       "5",
  pages =        "C585--C602",
  month =        "????",
  year =         "2019",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/19M1251308",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Tue Nov 5 05:24:19 MST 2019",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/41/5;
                 https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "bfloat16; bit flips; directed rounding; floating-point
                 arithmetic; fp16; half precision; IEEE arithmetic; low
                 precision; MATLAB; mixed precision; round to nearest;
                 rounding error analysis; simulation; stochastic
                 rounding; subnormal numbers",
  onlinedate =   "January 2019",
}


bibtype: article
filename: fparith.bib
label: Higham:2019:SMH
author: Nicholas J. Higham and Srikara Pranesh and Mawussi Zounon
title: Squeezing a Matrix into Half Precision, with an Application to Solving Linear Systems
journal: j-SIAM-J-SCI-COMP
volume: 41
number: 4
pages: A2536--A2551
year: 2019
CODEN: SJOCE3
DOI: https://doi.org/10.1137/18M1229511
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Thu Oct 10 06:58:08 MDT 2019
bibtimestamp: 2019.10.10 06:58:08 MDT
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
onlinedate: January 2019
rawauthor: Nicholas J. Higham and Srikara Pranesh and Mawussi Zounon
rawtitle: Squeezing a Matrix into Half Precision, with an Application to Solving Linear Systems
bibsource:
http://epubs.siam.org/toc/sjoce3/41/4; https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/matlab.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

keywords:
diagonal scaling; fp16; GMRES; half precision arithmetic; iterative refinement; linear system; MATLAB; mixed precision; overflow; preconditioning; subnormal numbers; underflow

entry:
@Article{Higham:2019:SMH,
  author =       "Nicholas J. Higham and Srikara Pranesh and Mawussi
                 Zounon",
  title =        "Squeezing a Matrix into Half Precision, with an
                 Application to Solving Linear Systems",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "41",
  number =       "4",
  pages =        "A2536--A2551",
  month =        "????",
  year =         "2019",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/18M1229511",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Thu Oct 10 06:58:08 MDT 2019",
  bibsource =    "http://epubs.siam.org/toc/sjoce3/41/4;
                 https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/matlab.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  keywords =     "diagonal scaling; fp16; GMRES; half precision
                 arithmetic; iterative refinement; linear system;
                 MATLAB; mixed precision; overflow; preconditioning;
                 subnormal numbers; underflow",
  onlinedate =   "January 2019",
}


bibtype: article
filename: fparith.bib
label: Horyachyy:2019:SEF
author: Oleh Horyachyy and Leonid Moroz and Viktor Otenko
title: Simple Effective Fast Inverse Square Root Algorithm with Two Magic Constants
journal: International Journal of Computing
volume: 18
number: 4
pages: 461--470
month: dec
monthnumber: 12
year: 2019
ISSN: 1727-6209 (print), 2312-5381 (electronic) OR 17276209 (print), 23125381 (electronic)
ISSNL: 1727-6209 OR 17276209
bibdate: Thu Feb 11 11:01:47 2021
bibtimestamp: 2021.02.11 11:01:47 ???
acknowledgement: ack-nhfb
rawauthor: Oleh Horyachyy and Leonid Moroz and Viktor Otenko
rawtitle: Simple Effective Fast Inverse Square Root Algorithm with Two Magic Constants
URL:
https://www.computingonline.net/computing/article/view/1616; https://www.researchgate.net/publication/349173096_SIMPLE_EFFECTIVE_FAST_INVERSE_SQUARE_ROOT_ALGORITHM_WITH_TWO_MAGIC_CONSTANTS

keywords:
FISR algorithm; floating-point arithmetic; FMA function; Householder.; IEEE 754 standard; initial approximation; inverse square root; magic constant; maximum relative error; Newton-Raphson

entry:
@Article{Horyachyy:2019:SEF,
  author =       "Oleh Horyachyy and Leonid Moroz and Viktor Otenko",
  title =        "Simple Effective Fast Inverse Square Root Algorithm
                 with Two Magic Constants",
  journal =      "International Journal of Computing",
  volume =       "18",
  number =       "4",
  pages =        "461--470",
  month =        dec,
  year =         "2019",
  ISSN =         "1727-6209 (print), 2312-5381 (electronic)",
  ISSN-L =       "1727-6209",
  bibdate =      "Thu Feb 11 11:01:47 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.computingonline.net/computing/article/view/1616;
                 https://www.researchgate.net/publication/349173096_SIMPLE_EFFECTIVE_FAST_INVERSE_SQUARE_ROOT_ALGORITHM_WITH_TWO_MAGIC_CONSTANTS",
  acknowledgement = ack-nhfb,
  keywords =     "FISR algorithm; floating-point arithmetic; FMA
                 function; Householder.; IEEE 754 standard; initial
                 approximation; inverse square root; magic constant;
                 maximum relative error; Newton-Raphson",
}


bibtype: article
filename: fparith.bib
label: Hough:2019:ISO
author: David G. Hough
title: The IEEE Standard 754: One for the History Books
journal: j-COMPUTER
volume: 52
number: 12
pages: 109--112
month: dec
monthnumber: 12
year: 2019
CODEN: CPTRB4
DOI: https://doi.org/10.1109/MC.2019.2926614
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Fri Nov 29 06:16:06 2019
bibtimestamp: 2019.11.29 06:16:06 ???
fjournal: Computer
keywords: Floating-point arithmetic; Hardware; History; IEEE Standards; Microprocessors; Software
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
rawauthor: David G. Hough
rawtitle: The {IEEE Standard 754}: One for the History Books
bibsource:
https://www.math.utah.edu/pub/tex/bib/computer2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://grouper.ieee.org/groups/msc/ANSI_IEEE-Std-754-2019/background/ieee-computer.pdf; https://www.computer.org/csdl/magazine/co/2019/12/08909942/1f8KFWxbTCU

entry:
@Article{Hough:2019:ISO,
  author =       "David G. Hough",
  title =        "The {IEEE Standard 754}: One for the History Books",
  journal =      j-COMPUTER,
  volume =       "52",
  number =       "12",
  pages =        "109--112",
  month =        dec,
  year =         "2019",
  CODEN =        "CPTRB4",
  DOI =          "https://doi.org/10.1109/MC.2019.2926614",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Fri Nov 29 06:16:06 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computer2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://grouper.ieee.org/groups/msc/ANSI_IEEE-Std-754-2019/background/ieee-computer.pdf;
                 https://www.computer.org/csdl/magazine/co/2019/12/08909942/1f8KFWxbTCU",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "Floating-point arithmetic; Hardware; History; IEEE
                 Standards; Microprocessors; Software",
}


bibtype: article
filename: fparith.bib
label: Hrycak:2019:AEC
author: Tomasz Hrycak and Sebastian Schmutzhard
title: Accurate evaluation of Chebyshev polynomials in floating-point arithmetic
journal: j-BIT-NUM-MATH
volume: 59
number: 2
pages: 403--416
month: jun
monthnumber: 6
year: 2019
CODEN: BITTEL, NBITAB
DOI: https://doi.org/10.1007/s10543-018-0738-5
ISSN: 0006-3835 (print), 1572-9125 (electronic) OR 00063835 (print), 15729125 (electronic)
ISSNL: 0006-3835 OR 00063835
bibdate: Fri Sep 6 09:16:11 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/bit.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.09.06 09:16:11 MDT
URL: http://link.springer.com/article/10.1007/s10543-018-0738-5
fjournal: BIT Numerical Mathematics
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10543
rawauthor: Tomasz Hrycak and Sebastian Schmutzhard
rawtitle: Accurate evaluation of {Chebyshev} polynomials in floating-point arithmetic
entry:
@Article{Hrycak:2019:AEC,
  author =       "Tomasz Hrycak and Sebastian Schmutzhard",
  title =        "Accurate evaluation of {Chebyshev} polynomials in
                 floating-point arithmetic",
  journal =      j-BIT-NUM-MATH,
  volume =       "59",
  number =       "2",
  pages =        "403--416",
  month =        jun,
  year =         "2019",
  CODEN =        "BITTEL, NBITAB",
  DOI =          "https://doi.org/10.1007/s10543-018-0738-5",
  ISSN =         "0006-3835 (print), 1572-9125 (electronic)",
  ISSN-L =       "0006-3835",
  bibdate =      "Fri Sep 6 09:16:11 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/bit.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer.com/article/10.1007/s10543-018-0738-5",
  acknowledgement = ack-nhfb,
  fjournal =     "BIT Numerical Mathematics",
  journal-URL =  "http://link.springer.com/journal/10543",
}


bibtype: book
filename: fparith.bib
label: IEEE-754:2019:ISF
author: IEEE-754
title: IEEE 754-2019, Standard for Floating-Point Arithmetic
publisher: pub-IEEE-STD
address: pub-IEEE-STD:adr
pages: 82
day: 13
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/IEEESTD.2019.876622
ISBN: 1-5044-5925-3 (print), 1-5044-5924-5 (e-PDF) OR 1504459253 (print), 1504459245 (ePDF)
ISBN13: 978-1-5044-5925-9 (print), 978-1-5044-5924-2 (e-PDF) OR 9781504459259 (print), 9781504459242 (ePDF)
bibdate: Tue Nov 05 08:49:56 2019
bibtimestamp: 2019.11.05 08:49:56 ???
acknowledgement: ack-nhfb
rawauthor: {IEEE-754}
rawtitle: {IEEE 754-2019, Standard for Floating-Point Arithmetic}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeestd.bib

abstract:
This standard specifies interchange and arithmetic formats and methods for binary and decimal floating-point arithmetic in computer programming environments. This standard specifies exception conditions and their default handling. An implementation of a floating-point system conforming to this standard may be realized entirely in software, entirely in hardware, or in any combination of software and hardware. For operations specified in the normative part of this standard, numerical results and exceptions are uniquely determined by the values of the input data, sequence of operations, and destination formats, all under user control.

entry:
@Book{IEEE-754:2019:ISF,
  author =       "{IEEE-754}",
  title =        "{IEEE 754-2019, Standard for Floating-Point
                 Arithmetic}",
  publisher =    pub-IEEE-STD,
  address =      pub-IEEE-STD:adr,
  pages =        "82",
  day =          "13",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/IEEESTD.2019.876622",
  ISBN =         "1-5044-5925-3 (print), 1-5044-5924-5 (e-PDF)",
  ISBN-13 =      "978-1-5044-5925-9 (print), 978-1-5044-5924-2 (e-PDF)",
  bibdate =      "Tue Nov 05 08:49:56 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeestd.bib",
  abstract =     "This standard specifies interchange and arithmetic
                 formats and methods for binary and decimal
                 floating-point arithmetic in computer programming
                 environments. This standard specifies exception
                 conditions and their default handling. An
                 implementation of a floating-point system conforming to
                 this standard may be realized entirely in software,
                 entirely in hardware, or in any combination of software
                 and hardware. For operations specified in the normative
                 part of this standard, numerical results and exceptions
                 are uniquely determined by the values of the input
                 data, sequence of operations, and destination formats,
                 all under user control.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: IEEE:2019:PDA
author: IEEE
pages: 82
month: apr
monthnumber: 4
year: 2019
bibdate: Thu Jun 20 15:39:16 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.06.20 15:39:16 ???
URL: https://ieeexplore.ieee.org/document/8739150
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: {IEEE}
title:
P754/D2.50, Apr 2019 --- IEEE Approved Draft Standard for Floating-Point Arithmetic: Revision of IEEE Std 754-2008

rawtitle:
{P754/D2.50, Apr 2019 --- IEEE Approved Draft Standard for Floating-Point Arithmetic: Revision of IEEE Std 754-2008}

entry:
@Misc{IEEE:2019:PDA,
  author =       "{IEEE}",
  title =        "{P754/D2.50, Apr 2019 --- IEEE Approved Draft Standard
                 for Floating-Point Arithmetic: Revision of IEEE Std
                 754-2008}",
  howpublished = "Web site",
  month =        apr,
  year =         "2019",
  bibdate =      "Thu Jun 20 15:39:16 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://ieeexplore.ieee.org/document/8739150",
  abstract =     "This standard specifies interchange and arithmetic
                 formats and methods for binary and decimal
                 floating-point arithmetic in computer programming
                 environments. This standard specifies exception
                 conditions and their default handling. An
                 implementation of a floating-point system conforming to
                 this standard may be realized entirely in software,
                 entirely in hardware, or in any combination of software
                 and hardware. For operations specified in the normative
                 part of this standard, numerical results and exceptions
                 are uniquely determined by the values of the input
                 data, sequence of operations, and destination formats,
                 all under user control.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Jaberipur:2019:MPP
author: Ghassem Jaberipur and Sahar Moradi Cherati
title: Modulo-$ (2 n + 3) $ Parallel Prefix Addition via Diminished-3 Representation of Residues
crossref: Takagi:2019:ISC
pages: 135--142
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00035
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Ghassem Jaberipur and Sahar {Moradi Cherati}
rawtitle: Modulo-$ (2 n + 3) $ Parallel Prefix Addition via Diminished-3 Representation of Residues
abstract:
Diminished-1 (D1) representation of modulo-(2n + 1) residues in [1, 2n] uses the n-bit codes [0, 2n - 1] and maintains a zero-indicator bit. Such D1 encoding has led to efficient parallel prefix modulo-(2n + 1) adders that perform as fast as the companion modulo-(2n - 1) and -2n adders with (3 + 2 log n) delay, where denotes the delay of a simple 2-input gate. Also similar, but slower (i.e., with one more delay) and slightly more complex, parallel prefix architectures have been offered for modulo-(2n - 3) adders. On the other hand, reverse conversion schemes for 4and 5-moduli sets that include conjugate moduli pairs 2n pm 1 and 2n pm 3 are already available, while we have not encountered any efficient modulo(2n + 3) adder. Therefore, in this paper, we offer the diminished-3 (D3) representation of modulo-(2n + 3) residues that maps the residue interval [3, 2n + 2] to [0, 2n - 1] and maintains a 2-bit 0,1, 2-indicator. The corresponding parallel prefix adder, which performs as fast as the fastest previous modulo-(2n - 3) adder is designed, where a 3-way compound architecture is devised as the bulk of modular addition that yields sum, sum+1, and sum+2. The proposed architecture is fully synthesized via Synopsis Design Compiler and tested for correctness, and its figures of merit compared with modulo(2n - 3) and -(2n + 1) adders.

keywords:
3-way compound architecture; adders; Adders; ARITH-26; complex prefix architectures; Compounds; Computer architecture; Computer science; D1 representation; D3 representation; Delays; Digital arithmetic; Diminished-1 representation; diminished-3 representation; Encoding; logic design; Modulo-(2n+3) parallel prefix addition; modulo-(2n-3) adders; parallel prefix adder; Residue Number System, Parallel Prefix Adder, Diminished-1, Diminished 3, 3-way compound adder; residue number systems; simple 2-input gate; Synopsis Design Compiler; zero-indicator bit

rawabstract:
Diminished-1 (D1) representation of modulo-(2n + 1) residues in [1, 2n] uses the n-bit codes [0, 2n - 1] and maintains a zero-indicator bit. Such D1 encoding has led to efficient parallel prefix modulo-(2n + 1) adders that perform as fast as the companion modulo-(2n - 1) and -2n adders with (3 + 2 log n) delay, where denotes the delay of a simple 2-input gate. Also similar, but slower (i.e., with one more delay) and slightly more complex, parallel prefix architectures have been offered for modulo-(2n - 3) adders. On the other hand, reverse conversion schemes for 4and 5-moduli sets that include conjugate moduli pairs 2n \pm 1 and 2n \pm 3 are already available, while we have not encountered any efficient modulo(2n + 3) adder. Therefore, in this paper, we offer the diminished-3 (D3) representation of modulo-(2n + 3) residues that maps the residue interval [3, 2n + 2] to [0, 2n - 1] and maintains a 2-bit {0,1, 2}-indicator. The corresponding parallel prefix adder, which performs as fast as the fastest previous modulo-(2n - 3) adder is designed, where a 3-way compound architecture is devised as the bulk of modular addition that yields sum, sum+1, and sum+2. The proposed architecture is fully synthesized via Synopsis Design Compiler and tested for correctness, and its figures of merit compared with modulo(2n - 3) and -(2n + 1) adders.

entry:
@InProceedings{Jaberipur:2019:MPP,
  author =       "Ghassem Jaberipur and Sahar {Moradi Cherati}",
  title =        "Modulo-$ (2 n + 3) $ Parallel Prefix Addition via
                 Diminished-3 Representation of Residues",
  crossref =     "Takagi:2019:ISC",
  pages =        "135--142",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00035",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Diminished-1 (D1) representation of modulo-(2n + 1)
                 residues in [1, 2n] uses the n-bit codes [0, 2n - 1]
                 and maintains a zero-indicator bit. Such D1 encoding
                 has led to efficient parallel prefix modulo-(2n + 1)
                 adders that perform as fast as the companion modulo-(2n
                 - 1) and -2n adders with (3 + 2 log n) delay, where
                 denotes the delay of a simple 2-input gate. Also
                 similar, but slower (i.e., with one more delay) and
                 slightly more complex, parallel prefix architectures
                 have been offered for modulo-(2n - 3) adders. On the
                 other hand, reverse conversion schemes for 4and
                 5-moduli sets that include conjugate moduli pairs 2n
                 \pm 1 and 2n \pm 3 are already available, while we have
                 not encountered any efficient modulo(2n + 3) adder.
                 Therefore, in this paper, we offer the diminished-3
                 (D3) representation of modulo-(2n + 3) residues that
                 maps the residue interval [3, 2n + 2] to [0, 2n - 1]
                 and maintains a 2-bit {0,1, 2}-indicator. The
                 corresponding parallel prefix adder, which performs as
                 fast as the fastest previous modulo-(2n - 3) adder is
                 designed, where a 3-way compound architecture is
                 devised as the bulk of modular addition that yields
                 sum, sum+1, and sum+2. The proposed architecture is
                 fully synthesized via Synopsis Design Compiler and
                 tested for correctness, and its figures of merit
                 compared with modulo(2n - 3) and -(2n + 1) adders.",
  acknowledgement = ack-nhfb,
  keywords =     "3-way compound architecture; adders; Adders; ARITH-26;
                 complex prefix architectures; Compounds; Computer
                 architecture; Computer science; D1 representation; D3
                 representation; Delays; Digital arithmetic;
                 Diminished-1 representation; diminished-3
                 representation; Encoding; logic design; Modulo-(2n+3)
                 parallel prefix addition; modulo-(2n-3) adders;
                 parallel prefix adder; Residue Number System, Parallel
                 Prefix Adder, Diminished-1, Diminished 3, 3-way
                 compound adder; residue number systems; simple 2-input
                 gate; Synopsis Design Compiler; zero-indicator bit",
}


bibtype: article
filename: fparith.bib
label: Jaiswal:2019:PHP
author: Manish Kumar Jaiswal and Hayden K.-H. So
title: PACoGen: a Hardware Posit Arithmetic Core Generator
journal: j-IEEE-ACCESS
volume: 7
pages: 74586--74601
year: 2019
DOI: https://doi.org/10.1109/access.2019.2920936
ISSN: 2169-3536 OR 21693536
ISSNL: 2169-3536 OR 21693536
bibdate: Thu Dec 14 18:07:06 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.14 18:07:06 ???
fjournal: IEEE Access
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639
rawauthor: Manish Kumar Jaiswal and Hayden K.-H. So
rawtitle: {PACoGen}: a Hardware Posit Arithmetic Core Generator
entry:
@Article{Jaiswal:2019:PHP,
  author =       "Manish Kumar Jaiswal and Hayden K.-H. So",
  title =        "{PACoGen}: a Hardware Posit Arithmetic Core
                 Generator",
  journal =      j-IEEE-ACCESS,
  volume =       "7",
  pages =        "74586--74601",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/access.2019.2920936",
  ISSN =         "2169-3536",
  ISSN-L =       "2169-3536",
  bibdate =      "Thu Dec 14 18:07:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}


bibtype: article
filename: fparith.bib
label: Jia:2019:DNT
author: Zhe Jia and Marco Maggioni and Jeffrey Smith and Daniele Paolo Scarpazza
title: Dissecting the NVidia Turing T4 GPU via Microbenchmarking
journal: arXiv.org
pages: 65
day: 18
month: mar
monthnumber: 3
year: 2019
DOI: https://doi.org/10.48550/ARXIV.1903.07486
bibdate: Mon Sep 11 07:00:16 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 07:00:16 ???
URL: https://arxiv.org/abs/1903.07486
acknowledgement: ack-nhfb
rawauthor: Zhe Jia and Marco Maggioni and Jeffrey Smith and Daniele Paolo Scarpazza
rawtitle: Dissecting the {NVidia Turing T4 GPU} via Microbenchmarking
abstract:
In 2019, the rapid rate at which GPU manufacturers refresh their designs, coupled with their reluctance to disclose microarchitectural details, is still a hurdle for those software designers who want to extract the highest possible performance. Last year, these very reasons motivated us to dissect the Volta GPU architecture using microbenchmarks.par The introduction in August 2018 of Turing, NVidia's latest architecture, pressed us to update our study. In this report, we examine Turing and compare it quantitatively against previous NVidia GPU generations. Specifically, we study the T4 GPU: a low-power board aiming at inference applications. We describe its improvements against its inference-oriented predecessor: the P4 GPU based on the Pascal architecture. Both T4 and P4 GPUs achieve significantly higher frequency-per-Watt figures than their full-size counterparts.par We study the performance of the T4's TensorCores, finding a much higher throughput on low-precision operands than on the P4 GPU. We reveal that Turing introduces new instructions that express matrix math more succinctly. We map Turing's instruction space, finding the same encoding as Volta, and additional instructions. We reveal that the Turing TU104 chip has the same memory hierarchy depth as the Volta GV100; cache levels sizes on the TU104 are frequently twice as large as those found on the Pascal GP104. We benchmark each constituent of the T4 memory hierarchy and find substantial overall performance improvements over its P4 predecessor. We studied how clock throttling affects compute-intensive workloads that hit power or thermal limits.par Many of our findings are novel, published here for the first time. All of them can guide high-performance software developers get closer to the GPU's peak performance.

rawabstract:
In 2019, the rapid rate at which GPU manufacturers refresh their designs, coupled with their reluctance to disclose microarchitectural details, is still a hurdle for those software designers who want to extract the highest possible performance. Last year, these very reasons motivated us to dissect the Volta GPU architecture using microbenchmarks.\par The introduction in August 2018 of Turing, NVidia's latest architecture, pressed us to update our study. In this report, we examine Turing and compare it quantitatively against previous NVidia GPU generations. Specifically, we study the T4 GPU: a low-power board aiming at inference applications. We describe its improvements against its inference-oriented predecessor: the P4 GPU based on the Pascal architecture. Both T4 and P4 GPUs achieve significantly higher frequency-per-Watt figures than their full-size counterparts.\par We study the performance of the T4's TensorCores, finding a much higher throughput on low-precision operands than on the P4 GPU. We reveal that Turing introduces new instructions that express matrix math more succinctly. We map Turing's instruction space, finding the same encoding as Volta, and additional instructions. We reveal that the Turing TU104 chip has the same memory hierarchy depth as the Volta GV100; cache levels sizes on the TU104 are frequently twice as large as those found on the Pascal GP104. We benchmark each constituent of the T4 memory hierarchy and find substantial overall performance improvements over its P4 predecessor. We studied how clock throttling affects compute-intensive workloads that hit power or thermal limits.\par Many of our findings are novel, published here for the first time. All of them can guide high-performance software developers get closer to the GPU's peak performance.

entry:
@Article{Jia:2019:DNT,
  author =       "Zhe Jia and Marco Maggioni and Jeffrey Smith and
                 Daniele Paolo Scarpazza",
  title =        "Dissecting the {NVidia Turing T4 GPU} via
                 Microbenchmarking",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "65",
  day =          "18",
  month =        mar,
  year =         "2019",
  DOI =          "https://doi.org/10.48550/ARXIV.1903.07486",
  bibdate =      "Mon Sep 11 07:00:16 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://arxiv.org/abs/1903.07486",
  abstract =     "In 2019, the rapid rate at which GPU manufacturers
                 refresh their designs, coupled with their reluctance to
                 disclose microarchitectural details, is still a hurdle
                 for those software designers who want to extract the
                 highest possible performance. Last year, these very
                 reasons motivated us to dissect the Volta GPU
                 architecture using microbenchmarks.\par

                 The introduction in August 2018 of Turing, NVidia's
                 latest architecture, pressed us to update our study. In
                 this report, we examine Turing and compare it
                 quantitatively against previous NVidia GPU generations.
                 Specifically, we study the T4 GPU: a low-power board
                 aiming at inference applications. We describe its
                 improvements against its inference-oriented
                 predecessor: the P4 GPU based on the Pascal
                 architecture. Both T4 and P4 GPUs achieve significantly
                 higher frequency-per-Watt figures than their full-size
                 counterparts.\par

                 We study the performance of the T4's TensorCores,
                 finding a much higher throughput on low-precision
                 operands than on the P4 GPU. We reveal that Turing
                 introduces new instructions that express matrix math
                 more succinctly. We map Turing's instruction space,
                 finding the same encoding as Volta, and additional
                 instructions. We reveal that the Turing TU104 chip has
                 the same memory hierarchy depth as the Volta GV100;
                 cache levels sizes on the TU104 are frequently twice as
                 large as those found on the Pascal GP104. We benchmark
                 each constituent of the T4 memory hierarchy and find
                 substantial overall performance improvements over its
                 P4 predecessor. We studied how clock throttling affects
                 compute-intensive workloads that hit power or thermal
                 limits.\par

                 Many of our findings are novel, published here for the
                 first time. All of them can guide high-performance
                 software developers get closer to the GPU's peak
                 performance.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Jiang:2019:LPU
author: H. Jiang and L. Liu and F. Lombardi and J. Han
title: Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 11
pages: 1635--1646
month: nov
monthnumber: 11
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2916817
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Oct 29 11:08:44 2019
bibtimestamp: 2019.10.29 11:08:44 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: H. Jiang and L. Liu and F. Lombardi and J. Han
rawtitle: Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation
keywords:
Adaptive approximation; Circuit synthesis; Delays; divider; Error correction; Hardware; image processing; Image reconstruction; low-power; overflow; Power dissipation; SQR circuit

entry:
@Article{Jiang:2019:LPU,
  author =       "H. Jiang and L. Liu and F. Lombardi and J. Han",
  title =        "Low-Power Unsigned Divider and Square Root Circuit
                 Designs Using Adaptive Approximation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "11",
  pages =        "1635--1646",
  month =        nov,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2916817",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Oct 29 11:08:44 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adaptive approximation; Circuit synthesis; Delays;
                 divider; Error correction; Hardware; image processing;
                 Image reconstruction; low-power; overflow; Power
                 dissipation; SQR circuit",
}


bibtype: inproceedings
filename: fparith.bib
label: Johansson:2019:FAP
author: Fredrik Johansson
title: Faster Arbitrary-Precision Dot Product and Matrix Multiplication
crossref: Takagi:2019:ISC
pages: 15--22
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00012
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Fredrik Johansson
rawtitle: Faster Arbitrary-Precision Dot Product and Matrix Multiplication
abstract:
We present algorithms for real and complex dot product and matrix multiplication in arbitrary-precision floating-point and ball arithmetic. A low-overhead dot product is implemented on the level of GMP limb arrays; it is about twice as fast as previous code in MPFR and Arb at precision up to several hundred bits. Up to 128 bits, it is 3-4 times as fast, costing 20-30 cycles per term for floating-point evaluation and 40-50 cycles per term for balls. We handle large matrix multiplications even more efficiently via blocks of scaled integer matrices. The new methods are implemented in Arb and significantly speed up polynomial operations and linear algebra.

keywords:
arbitrary-precision arithmetic, ball arithmetic, dot product, matrix multiplication; arbitrary-precision dot product; arbitrary-precision floating-point; ARITH-26; ball arithmetic; complex dot product; Costing; Digital arithmetic; floating point arithmetic; floating-point evaluation; GMP limb arrays; Indexes; Libraries; Linear algebra; linear algebra; low-overhead dot product; mathematics computing; matrix multiplication; polynomial operations; polynomials; real dot product; scaled integer matrices; Software; Upper bound; word length 128.0 bit

rawabstract:
We present algorithms for real and complex dot product and matrix multiplication in arbitrary-precision floating-point and ball arithmetic. A low-overhead dot product is implemented on the level of GMP limb arrays; it is about twice as fast as previous code in MPFR and Arb at precision up to several hundred bits. Up to 128 bits, it is 3-4 times as fast, costing 20-30 cycles per term for floating-point evaluation and 40-50 cycles per term for balls. We handle large matrix multiplications even more efficiently via blocks of scaled integer matrices. The new methods are implemented in Arb and significantly speed up polynomial operations and linear algebra.

entry:
@InProceedings{Johansson:2019:FAP,
  author =       "Fredrik Johansson",
  title =        "Faster Arbitrary-Precision Dot Product and Matrix
                 Multiplication",
  crossref =     "Takagi:2019:ISC",
  pages =        "15--22",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00012",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present algorithms for real and complex dot product
                 and matrix multiplication in arbitrary-precision
                 floating-point and ball arithmetic. A low-overhead dot
                 product is implemented on the level of GMP limb arrays;
                 it is about twice as fast as previous code in MPFR and
                 Arb at precision up to several hundred bits. Up to 128
                 bits, it is 3-4 times as fast, costing 20-30 cycles per
                 term for floating-point evaluation and 40-50 cycles per
                 term for balls. We handle large matrix multiplications
                 even more efficiently via blocks of scaled integer
                 matrices. The new methods are implemented in Arb and
                 significantly speed up polynomial operations and linear
                 algebra.",
  acknowledgement = ack-nhfb,
  keywords =     "arbitrary-precision arithmetic, ball arithmetic, dot
                 product, matrix multiplication; arbitrary-precision dot
                 product; arbitrary-precision floating-point; ARITH-26;
                 ball arithmetic; complex dot product; Costing; Digital
                 arithmetic; floating point arithmetic; floating-point
                 evaluation; GMP limb arrays; Indexes; Libraries; Linear
                 algebra; linear algebra; low-overhead dot product;
                 mathematics computing; matrix multiplication;
                 polynomial operations; polynomials; real dot product;
                 scaled integer matrices; Software; Upper bound; word
                 length 128.0 bit",
}


bibtype: inproceedings
filename: fparith.bib
label: Jugade:2019:MEE
author: Chaitanya Jugade and Deepak Ingole and Dayaram Sonawane and Michal Kvasnica and John Gustafson
editor: IEEE
booktitle: 2019 Sixth Indian Control Conference (ICC)
title: A Memory-Efficient Explicit Model Predictive Control using Posits
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 188--193
year: 2019
DOI: https://doi.org/10.1109/ICC47138.2019.9123179
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Chaitanya Jugade and Deepak Ingole and Dayaram Sonawane and Michal Kvasnica and John Gustafson
rawbooktitle: {2019 Sixth Indian Control Conference (ICC)}
raweditor: {IEEE}
rawtitle: A Memory-Efficient Explicit Model Predictive Control using Posits
entry:
@InProceedings{Jugade:2019:MEE,
  author =       "Chaitanya Jugade and Deepak Ingole and Dayaram
                 Sonawane and Michal Kvasnica and John Gustafson",
  editor =       "{IEEE}",
  booktitle =    "{2019 Sixth Indian Control Conference (ICC)}",
  title =        "A Memory-Efficient Explicit Model Predictive Control
                 using Posits",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "188--193",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ICC47138.2019.9123179",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kalamkar:2019:SBD
title: A Study of BFLOAT16 for Deep Learning Training
journal: arXiv.org
pages: 1--10
day: 29
month: may
monthnumber: 5
year: 2019
bibdate: Fri Aug 30 17:25:53 2019
bibsource: DBLP archive; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.08.30 17:25:53 ???
URL: http://arxiv.org/abs/1905.12322
acknowledgement: ack-nhfb
rawtitle: A Study of {BFLOAT16} for Deep Learning Training
author:
Dhiraj D. Kalamkar and Dheevatsa Mudigere and Naveen Mellempudi and Dipankar Das and Kunal Banerjee and Sasikanth Avancha and Dharma Teja Vooturi and Nataraj Jammalamadaka and Jianyu Huang and Hector Yuen and Jiyan Yang and Jongsoo Park and Alexander Heinecke and Evangelos Georganas and Sudarshan Srinivasan and Abhisek Kundu and Misha Smelyanskiy and Bharat Kaul and Pradeep Dubey

abstract:
This paper presents the first comprehensive empirical study demonstrating the efficacy of the Brain Floating Point (BFLOAT16) half-precision format for Deep Learning training across image classification, speech recognition, language modeling, generative networks and industrial recommendation systems. BFLOAT16 is attractive for Deep Learning training for two reasons: the range of values it can represent is the same as that of IEEE 754 floating-point format (FP32) and conversion to/from FP32 is simple. Maintaining the same range as FP32 is important to ensure that no hyper-parameter tuning is required for convergence; e.g., IEEE 754 compliant half-precision floating point (FP16) requires hyper-parameter tuning. In this paper, we discuss the flow of tensors and various key operations in mixed precision training, and delve into details of operations, such as the rounding modes for converting FP32 tensors to BFLOAT16. We have implemented a method to emulate BFLOAT16 operations in Tensorflow, Caffe2, IntelCaffe, and Neon for our experiments. Our results show that deep learning training using BFLOAT16 tensors achieves the same state-of-the-art (SOTA) results across domains as FP32 tensors in the same number of iterations and with no changes to hyper-parameters.

rawabstract:
This paper presents the first comprehensive empirical study demonstrating the efficacy of the Brain Floating Point (BFLOAT16) half-precision format for Deep Learning training across image classification, speech recognition, language modeling, generative networks and industrial recommendation systems. BFLOAT16 is attractive for Deep Learning training for two reasons: the range of values it can represent is the same as that of IEEE 754 floating-point format (FP32) and conversion to/from FP32 is simple. Maintaining the same range as FP32 is important to ensure that no hyper-parameter tuning is required for convergence; e.g., IEEE 754 compliant half-precision floating point (FP16) requires hyper-parameter tuning. In this paper, we discuss the flow of tensors and various key operations in mixed precision training, and delve into details of operations, such as the rounding modes for converting FP32 tensors to BFLOAT16. We have implemented a method to emulate BFLOAT16 operations in Tensorflow, Caffe2, IntelCaffe, and Neon for our experiments. Our results show that deep learning training using BFLOAT16 tensors achieves the same state-of-the-art (SOTA) results across domains as FP32 tensors in the same number of iterations and with no changes to hyper-parameters.

rawauthor:
Dhiraj D. Kalamkar and Dheevatsa Mudigere and Naveen Mellempudi and Dipankar Das and Kunal Banerjee and Sasikanth Avancha and Dharma Teja Vooturi and Nataraj Jammalamadaka and Jianyu Huang and Hector Yuen and Jiyan Yang and Jongsoo Park and Alexander Heinecke and Evangelos Georganas and Sudarshan Srinivasan and Abhisek Kundu and Misha Smelyanskiy and Bharat Kaul and Pradeep Dubey

entry:
@Article{Kalamkar:2019:SBD,
  author =       "Dhiraj D. Kalamkar and Dheevatsa Mudigere and Naveen
                 Mellempudi and Dipankar Das and Kunal Banerjee and
                 Sasikanth Avancha and Dharma Teja Vooturi and Nataraj
                 Jammalamadaka and Jianyu Huang and Hector Yuen and
                 Jiyan Yang and Jongsoo Park and Alexander Heinecke and
                 Evangelos Georganas and Sudarshan Srinivasan and
                 Abhisek Kundu and Misha Smelyanskiy and Bharat Kaul and
                 Pradeep Dubey",
  title =        "A Study of {BFLOAT16} for Deep Learning Training",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--10",
  day =          "29",
  month =        may,
  year =         "2019",
  bibdate =      "Fri Aug 30 17:25:53 2019",
  bibsource =    "DBLP archive;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1905.12322",
  abstract =     "This paper presents the first comprehensive empirical
                 study demonstrating the efficacy of the Brain Floating
                 Point (BFLOAT16) half-precision format for Deep
                 Learning training across image classification, speech
                 recognition, language modeling, generative networks and
                 industrial recommendation systems. BFLOAT16 is
                 attractive for Deep Learning training for two reasons:
                 the range of values it can represent is the same as
                 that of IEEE 754 floating-point format (FP32) and
                 conversion to/from FP32 is simple. Maintaining the same
                 range as FP32 is important to ensure that no
                 hyper-parameter tuning is required for convergence;
                 e.g., IEEE 754 compliant half-precision floating point
                 (FP16) requires hyper-parameter tuning. In this paper,
                 we discuss the flow of tensors and various key
                 operations in mixed precision training, and delve into
                 details of operations, such as the rounding modes for
                 converting FP32 tensors to BFLOAT16. We have
                 implemented a method to emulate BFLOAT16 operations in
                 Tensorflow, Caffe2, IntelCaffe, and Neon for our
                 experiments. Our results show that deep learning
                 training using BFLOAT16 tensors achieves the same
                 state-of-the-art (SOTA) results across domains as FP32
                 tensors in the same number of iterations and with no
                 changes to hyper-parameters.",
  acknowledgement = ack-nhfb,
  biburl =       "https://dblp.org/rec/bib/journals/corr/abs-1905-12322",
  eprint =       "1905.12322",
  timestamp =    "Wed Jan  3 07:58:16 2024",
}


bibtype: inproceedings
filename: fparith.bib
label: Katajainen:2019:HMP
author: Jyrki Katajainen
editor: I. Kotsireas and P. Pardalos and K. Parsopoulos and D. Souravlias and A. Tsokas
booktitle: Analysis of Experimental Algorithms. SEA 2019
title: Hacker's Multiple-Precision Integer-Division Program in Close Scrutiny
publisher: pub-SV
address: pub-SV:adr
pages: 376--391
year: 2019
DOI: https://doi.org/10.1007/978-3-030-34029-2_25
bibdate: Thu Jan 28 19:43:12 2021
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2021.01.28 19:43:12 ???
series: ser-LNCS
URL: http://www.cphstl.dk/Paper/Division/division.pdf
acknowledgement: ack-nhfb
rawauthor: Jyrki Katajainen
rawbooktitle: Analysis of Experimental Algorithms. {SEA 2019}
raweditor: I. Kotsireas and P. Pardalos and K. Parsopoulos and D. Souravlias and A. Tsokas
rawtitle: Hacker's Multiple-Precision Integer-Division Program in Close Scrutiny
ORCID: Katajainen, Jyrki/0000-0002-7714-5588
abstract:
Before the era of ubiquitous computers, the long-division method was presented in primary schools as a paper-and-pencil technique to do whole-number division. In the book booktitle Hacker's Delight by Warren [2nd edition, 2013], an implementation of this algorithm was given using the C programming language. In this paper we will report our experiences when converting this program to a generic program-library routine.par The highlights of the paper are as follows: (1) We describe the long-division algorithm this is done for educational purposes. (2) We outline its implementation the goal is to show how to use modern C++ to achieve flexibility, portability, and efficiency. (3) We analyse its computational complexity by paying attention to how the digit width affects the running time. (4) We compare the practical performance of the library routine against Warren's original. It is pleasure to announce that the library routine is faster. (5) We release the developed routine as part of a software package that provides fixed-width integers of arbitrary length, e.g. a number of type Open image in new window has 2019 bits and it supports the same operations with the same semantics as a number of type tt unsigned int

keywords:
Algorithm; Description; Experimentation; Implementation; Long division; Meticulous analysis; Multiple-precision arithmetic; Software library

rawabstract:
Before the era of ubiquitous computers, the long-division method was presented in primary schools as a paper-and-pencil technique to do whole-number division. In the book \booktitle{Hacker's Delight} by Warren [2nd edition, 2013], an implementation of this algorithm was given using the C programming language. In this paper we will report our experiences when converting this program to a generic program-library routine.\par The highlights of the paper are as follows: (1) We describe the long-division algorithm this is done for educational purposes. (2) We outline its implementation the goal is to show how to use modern C++ to achieve flexibility, portability, and efficiency. (3) We analyse its computational complexity by paying attention to how the digit width affects the running time. (4) We compare the practical performance of the library routine against Warren's original. It is pleasure to announce that the library routine is faster. (5) We release the developed routine as part of a software package that provides fixed-width integers of arbitrary length, e.g. a number of type Open image in new window has 2019 bits and it supports the same operations with the same semantics as a number of type {\tt unsigned int}

entry:
@InProceedings{Katajainen:2019:HMP,
  author =       "Jyrki Katajainen",
  editor =       "I. Kotsireas and P. Pardalos and K. Parsopoulos and D.
                 Souravlias and A. Tsokas",
  booktitle =    "Analysis of Experimental Algorithms. {SEA 2019}",
  title =        "Hacker's Multiple-Precision Integer-Division Program
                 in Close Scrutiny",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "376--391",
  year =         "2019",
  DOI =          "https://doi.org/10.1007/978-3-030-34029-2_25",
  bibdate =      "Thu Jan 28 19:43:12 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  series =       ser-LNCS,
  URL =          "http://www.cphstl.dk/Paper/Division/division.pdf",
  abstract =     "Before the era of ubiquitous computers, the
                 long-division method was presented in primary schools
                 as a paper-and-pencil technique to do whole-number
                 division. In the book \booktitle{Hacker's Delight} by
                 Warren [2nd edition, 2013], an implementation of this
                 algorithm was given using the C programming language.
                 In this paper we will report our experiences when
                 converting this program to a generic program-library
                 routine.\par

                 The highlights of the paper are as follows: (1) We
                 describe the long-division algorithm this is done for
                 educational purposes. (2) We outline its implementation
                 the goal is to show how to use modern C++ to achieve
                 flexibility, portability, and efficiency. (3) We
                 analyse its computational complexity by paying
                 attention to how the digit width affects the running
                 time. (4) We compare the practical performance of the
                 library routine against Warren's original. It is
                 pleasure to announce that the library routine is
                 faster. (5) We release the developed routine as part of
                 a software package that provides fixed-width integers
                 of arbitrary length, e.g. a number of type Open image
                 in new window has 2019 bits and it supports the same
                 operations with the same semantics as a number of type
                 {\tt unsigned int}",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithm; Description; Experimentation;
                 Implementation; Long division; Meticulous analysis;
                 Multiple-precision arithmetic; Software library",
  ORCID-numbers = "Katajainen, Jyrki/0000-0002-7714-5588",
}


bibtype: inproceedings
filename: fparith.bib
label: Kaul:2019:OFF
author: Himanshu Kaul and Mark Anders and Sanu Mathew and Seongjong Kim and Ram Krishnamurthy
title: Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators
crossref: Takagi:2019:ISC
pages: 84--87
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00021
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Himanshu Kaul and Mark Anders and Sanu Mathew and Seongjong Kim and Ram Krishnamurthy
rawtitle: Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators
abstract:
This paper describes optimizations for the critical maximum exponent and alignment operations, with scalability for many-term fused floating-point dot-product units. The impact of these optimizations is quantified for up to 32-term BFloat16 weight/activation inputs with single-precision dot-product output, targeted for machine learning accelerators. Area and energy efficiency results are compared across performance targets, design parameters, and data statistics.

keywords:
32-term BFloat16 weight inputs; Adders; alignment operation; ARITH-26; Computer architecture; critical maximum exponent operation; deep neural networks; dot-product; Energy efficiency; floating point arithmetic; floating-point; Hardware; learning (artificial intelligence); Machine learning; machine learning; machine learning accelerators; neural nets; Optimization; optimized fused floating-point many-term dot-product hardware; single-precision dot-product output; Throughput

rawabstract:
This paper describes optimizations for the critical maximum exponent and alignment operations, with scalability for many-term fused floating-point dot-product units. The impact of these optimizations is quantified for up to 32-term BFloat16 weight/activation inputs with single-precision dot-product output, targeted for machine learning accelerators. Area and energy efficiency results are compared across performance targets, design parameters, and data statistics.

entry:
@InProceedings{Kaul:2019:OFF,
  author =       "Himanshu Kaul and Mark Anders and Sanu Mathew and
                 Seongjong Kim and Ram Krishnamurthy",
  title =        "Optimized Fused Floating-Point Many-Term Dot-Product
                 Hardware for Machine Learning Accelerators",
  crossref =     "Takagi:2019:ISC",
  pages =        "84--87",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00021",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper describes optimizations for the critical
                 maximum exponent and alignment operations, with
                 scalability for many-term fused floating-point
                 dot-product units. The impact of these optimizations is
                 quantified for up to 32-term BFloat16 weight/activation
                 inputs with single-precision dot-product output,
                 targeted for machine learning accelerators. Area and
                 energy efficiency results are compared across
                 performance targets, design parameters, and data
                 statistics.",
  acknowledgement = ack-nhfb,
  keywords =     "32-term BFloat16 weight inputs; Adders; alignment
                 operation; ARITH-26; Computer architecture; critical
                 maximum exponent operation; deep neural networks;
                 dot-product; Energy efficiency; floating point
                 arithmetic; floating-point; Hardware; learning
                 (artificial intelligence); Machine learning; machine
                 learning; machine learning accelerators; neural nets;
                 Optimization; optimized fused floating-point many-term
                 dot-product hardware; single-precision dot-product
                 output; Throughput",
}


bibtype: inproceedings
filename: fparith.bib
label: Kim:2019:CEI
author: HyunJin Kim and Min Soo Kim and Alberto A. Del Barrio and Nader Bagherzadeh
title: A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks
crossref: Takagi:2019:ISC
pages: 108--111
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00029
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: HyunJin Kim and Min Soo Kim and Alberto A. {Del Barrio} and Nader Bagherzadeh
rawtitle: A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks
abstract:
This paper proposes a cost-efficient approximate logarithmic multiplication for convolutional neural networks (CNNs), where two truncated logarithmic multipliers are connected for error correction. The proposed iterative logarithmic multiplication achieves low and unbiased average error while the hardware cost is significantly reduced by utilizing the truncated Mitchell multiplier and approximating error terms from the first stage. The proposed design has error characteristics that are suitable for neural network inferences, and the experiments on contemporary CNNs show that the proposed multiplier does not cause significant degradation on accuracy compared to exact multiplication.

keywords:
Adders; approximate multiplier; ARITH-26; convolutional neural nets; convolutional neural network; convolutional neural networks; Convolutional neural networks; cost-efficient approximate logarithmic multiplication; Delays; Detectors; Digital arithmetic; error correction; Hardware; iterative methods; iterative truncated logarithmic multiplication; logarithmic multiplication; Mitchell multiplier; neural network inferences; truncated logarithmic multipliers; truncated Mitchell multiplier

rawabstract:
This paper proposes a cost-efficient approximate logarithmic multiplication for convolutional neural networks (CNNs), where two truncated logarithmic multipliers are connected for error correction. The proposed iterative logarithmic multiplication achieves low and unbiased average error while the hardware cost is significantly reduced by utilizing the truncated Mitchell multiplier and approximating error terms from the first stage. The proposed design has error characteristics that are suitable for neural network inferences, and the experiments on contemporary CNNs show that the proposed multiplier does not cause significant degradation on accuracy compared to exact multiplication.

entry:
@InProceedings{Kim:2019:CEI,
  author =       "HyunJin Kim and Min Soo Kim and Alberto A. {Del
                 Barrio} and Nader Bagherzadeh",
  title =        "A Cost-Efficient Iterative Truncated Logarithmic
                 Multiplication for Convolutional Neural Networks",
  crossref =     "Takagi:2019:ISC",
  pages =        "108--111",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00029",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper proposes a cost-efficient approximate
                 logarithmic multiplication for convolutional neural
                 networks (CNNs), where two truncated logarithmic
                 multipliers are connected for error correction. The
                 proposed iterative logarithmic multiplication achieves
                 low and unbiased average error while the hardware cost
                 is significantly reduced by utilizing the truncated
                 Mitchell multiplier and approximating error terms from
                 the first stage. The proposed design has error
                 characteristics that are suitable for neural network
                 inferences, and the experiments on contemporary CNNs
                 show that the proposed multiplier does not cause
                 significant degradation on accuracy compared to exact
                 multiplication.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; approximate multiplier; ARITH-26;
                 convolutional neural nets; convolutional neural
                 network; convolutional neural networks; Convolutional
                 neural networks; cost-efficient approximate logarithmic
                 multiplication; Delays; Detectors; Digital arithmetic;
                 error correction; Hardware; iterative methods;
                 iterative truncated logarithmic multiplication;
                 logarithmic multiplication; Mitchell multiplier; neural
                 network inferences; truncated logarithmic multipliers;
                 truncated Mitchell multiplier",
}


bibtype: article
filename: fparith.bib
label: Kim:2019:EMA
author: M. S. Kim and A. A. D. Barrio and L. T. Oliveira and R. Hermida and N. Bagherzadeh
title: Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 5
pages: 660--675
month: may
monthnumber: 5
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2880742
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. S. Kim and A. A. D. Barrio and L. T. Oliveira and R. Hermida and N. Bagherzadeh
rawtitle: Efficient {Mitchell}'s Approximate Log Multipliers for Convolutional Neural Networks
keywords:
approximate log multipliers; Approximation algorithms; approximation theory; Arithmetic and logic units; CNN; computer vision; convolutional neural nets; convolutional neural networks; Convolutional neural networks; customizable design; customizable log multiplier; Degradation; design techniques; efficient shift amount calculation; Energy consumption; energy consumption reduction; energy-efficient approximate multipliers; exact zero computation; floating point arithmetic; fully-parallel LOD; ImageNet ILSVRC2012 dataset; Logic gates; low-power design; machine learning; multiplying circuits; object recognition; power aware computing; probability; Training

entry:
@Article{Kim:2019:EMA,
  author =       "M. S. Kim and A. A. D. Barrio and L. T. Oliveira and
                 R. Hermida and N. Bagherzadeh",
  title =        "Efficient {Mitchell}'s Approximate Log Multipliers for
                 Convolutional Neural Networks",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "5",
  pages =        "660--675",
  month =        may,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2880742",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "approximate log multipliers; Approximation algorithms;
                 approximation theory; Arithmetic and logic units; CNN;
                 computer vision; convolutional neural nets;
                 convolutional neural networks; Convolutional neural
                 networks; customizable design; customizable log
                 multiplier; Degradation; design techniques; efficient
                 shift amount calculation; Energy consumption; energy
                 consumption reduction; energy-efficient approximate
                 multipliers; exact zero computation; floating point
                 arithmetic; fully-parallel LOD; ImageNet ILSVRC2012
                 dataset; Logic gates; low-power design; machine
                 learning; multiplying circuits; object recognition;
                 power aware computing; probability; Training",
}


bibtype: inproceedings
filename: fparith.bib
label: Klower:2019:PAF
author: Milan Klower and Peter D. Duben and Tim N. Palmer
title: Posits as an Alternative to Floats for Weather and Climate Models
crossref: Gustafson:2019:CPC
pages: 1:1--1:8
year: 2019
DOI: https://doi.org/10.1145/3316279.3316281
bibdate: Mon Feb 10 12:11:16 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 12:11:16 ???
acknowledgement: ack-nhfb
articleno: 2
rawauthor: Milan Kl{\"o}wer and Peter D. D{\"u}ben and Tim N. Palmer
rawtitle: Posits as an Alternative to Floats for Weather and Climate Models
keywords:
Computational fluid dynamics, floating point, computer arithmetic, posits, reduced precision, climate projections, weather forecast

entry:
@InProceedings{Klower:2019:PAF,
  author =       "Milan Kl{\"o}wer and Peter D. D{\"u}ben and Tim N.
                 Palmer",
  title =        "Posits as an Alternative to Floats for Weather and
                 Climate Models",
  crossref =     "Gustafson:2019:CPC",
  pages =        "1:1--1:8",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316281",
  bibdate =      "Mon Feb 10 12:11:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  keywords =     "Computational fluid dynamics, floating point, computer
                 arithmetic, posits, reduced precision, climate
                 projections, weather forecast",
  location =     "Singapore, Singapore",
  numpages =     "8",
}


bibtype: inproceedings
filename: fparith.bib
label: Kostic:2019:UNV
author: Dusan Kostic and Shay Gueron
title: Using the New VPMADD Instructions for the New Post Quantum Key Encapsulation Mechanism SIKE
crossref: Takagi:2019:ISC
pages: 215--218
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00050
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Dusan Kostic and Shay Gueron
rawtitle: Using the New {VPMADD} Instructions for the New Post Quantum Key Encapsulation Mechanism {SIKE}
abstract:
This paper demonstrates the use of new processor instructions VPMADD, intended to appear in the coming generation of Intel processors (codename ``Cannon Lake''), in order to accelerate the newly proposed key encapsulation mechanism (KEM) named SIKE. SIKE is one of the submissions to the NIST standardization process on post-quantum cryptography, and is based on pseudo-random walks in supersingular isogeny graphs. While very small keys are the main advantage of SIKE, its extreme computational intensiveness makes it one of the slowest KEM proposals. Performance optimizations are needed. We address here the ``Level 1'' parameters that target 64-bit quantum security, and deemed sufficient for the NIST standardization effort. Thus, we focus on SIKE503 that operates over Fp2 with a 503-bit prime p. These short operands pose a significant challenge on using VPMADD effectively. We demonstrate several optimization methods to accelerate Fp, Fp2, and the elliptic curve arithmetic, and predict a potential speedup by a factor of 1.72x.

keywords:
ARITH-26; codename CannonLake; Computer architecture; Encapsulation; extreme computational intensiveness; Intel processors; KEM proposals; key encapsulation mechanism; NIST; NIST standardization effort; NIST standardization process; Optimization; post quantum key encapsulation mechanism SIKE; post-quantum cryptography; processor instructions VPMADD; Proposals; pseudorandom walks; Quantum computing; quantum cryptography; quantum security; Registers; SIKE503; supersingular isogeny graphs; VPMADD instructions; VPMADD processor instructions, software optimization, post quantum cryptography, supersingular isogeny

rawabstract:
This paper demonstrates the use of new processor instructions VPMADD, intended to appear in the coming generation of Intel processors (codename ``Cannon Lake''), in order to accelerate the newly proposed key encapsulation mechanism (KEM) named SIKE. SIKE is one of the submissions to the NIST standardization process on post-quantum cryptography, and is based on pseudo-random walks in supersingular isogeny graphs. While very small keys are the main advantage of SIKE, its extreme computational intensiveness makes it one of the slowest KEM proposals. Performance optimizations are needed. We address here the ``Level 1'' parameters that target 64-bit quantum security, and deemed sufficient for the NIST standardization effort. Thus, we focus on SIKE503 that operates over Fp2 with a 503-bit prime p. These short operands pose a significant challenge on using VPMADD effectively. We demonstrate several optimization methods to accelerate Fp, Fp2, and the elliptic curve arithmetic, and predict a potential speedup by a factor of 1.72x.

entry:
@InProceedings{Kostic:2019:UNV,
  author =       "Dusan Kostic and Shay Gueron",
  title =        "Using the New {VPMADD} Instructions for the New Post
                 Quantum Key Encapsulation Mechanism {SIKE}",
  crossref =     "Takagi:2019:ISC",
  pages =        "215--218",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00050",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper demonstrates the use of new processor
                 instructions VPMADD, intended to appear in the coming
                 generation of Intel processors (codename ``Cannon
                 Lake''), in order to accelerate the newly proposed key
                 encapsulation mechanism (KEM) named SIKE. SIKE is one
                 of the submissions to the NIST standardization process
                 on post-quantum cryptography, and is based on
                 pseudo-random walks in supersingular isogeny graphs.
                 While very small keys are the main advantage of SIKE,
                 its extreme computational intensiveness makes it one of
                 the slowest KEM proposals. Performance optimizations
                 are needed. We address here the ``Level 1'' parameters
                 that target 64-bit quantum security, and deemed
                 sufficient for the NIST standardization effort. Thus,
                 we focus on SIKE503 that operates over Fp2 with a
                 503-bit prime p. These short operands pose a
                 significant challenge on using VPMADD effectively. We
                 demonstrate several optimization methods to accelerate
                 Fp, Fp2, and the elliptic curve arithmetic, and predict
                 a potential speedup by a factor of 1.72x.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; codename CannonLake; Computer architecture;
                 Encapsulation; extreme computational intensiveness;
                 Intel processors; KEM proposals; key encapsulation
                 mechanism; NIST; NIST standardization effort; NIST
                 standardization process; Optimization; post quantum key
                 encapsulation mechanism SIKE; post-quantum
                 cryptography; processor instructions VPMADD; Proposals;
                 pseudorandom walks; Quantum computing; quantum
                 cryptography; quantum security; Registers; SIKE503;
                 supersingular isogeny graphs; VPMADD instructions;
                 VPMADD processor instructions, software optimization,
                 post quantum cryptography, supersingular isogeny",
}


bibtype: inproceedings
filename: fparith.bib
label: Kouya:2019:PEE
author: Tomonori Kouya
crossref: Takagi:2019:ISC
pages: 120--123
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00032
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Tomonori Kouya
title:
Performance Evaluation of an Efficient Double-Double BLAS1 Function With Error-Free Transformation and its Application to Explicit Extrapolation Methods

abstract:
Error-free transformation (EFT) has been recently applied to solve ill-conditioned problems. This transformation can reduce the number of arithmetic operations required compared to multiple precision arithmetic. In this study, we implement double-double (DD) BLAS1 functions with EFT and propose the application of the approach to explicit extrapolation methods for solving initial value problems of ordinary differential equations (ODEs). The presented routines can be effective for a large system of linear ODEs, especially when a harmonic sequence is used.

keywords:
ARITH-26; arithmetic operations; BLAS1 functions; Convergence; differential equations; efficient double-double BLAS1 function; EFT; error-free transformation; error-free transformation, extrapolation, ordinary differential equation; explicit extrapolation methods; extrapolation; Extrapolation; floating point arithmetic; Harmonic analysis; harmonic sequence; ill-conditioned problems; initial value problems; Libraries; mathematics computing; multiple precision arithmetic; ordinary differential equations; performance evaluation; Silicon; Standards

rawabstract:
Error-free transformation (EFT) has been recently applied to solve ill-conditioned problems. This transformation can reduce the number of arithmetic operations required compared to multiple precision arithmetic. In this study, we implement double-double (DD) BLAS1 functions with EFT and propose the application of the approach to explicit extrapolation methods for solving initial value problems of ordinary differential equations (ODEs). The presented routines can be effective for a large system of linear ODEs, especially when a harmonic sequence is used.

rawtitle:
Performance Evaluation of an Efficient Double-Double {BLAS1} Function With Error-Free Transformation and its Application to Explicit Extrapolation Methods

entry:
@InProceedings{Kouya:2019:PEE,
  author =       "Tomonori Kouya",
  title =        "Performance Evaluation of an Efficient Double-Double
                 {BLAS1} Function With Error-Free Transformation and its
                 Application to Explicit Extrapolation Methods",
  crossref =     "Takagi:2019:ISC",
  pages =        "120--123",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00032",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Error-free transformation (EFT) has been recently
                 applied to solve ill-conditioned problems. This
                 transformation can reduce the number of arithmetic
                 operations required compared to multiple precision
                 arithmetic. In this study, we implement double-double
                 (DD) BLAS1 functions with EFT and propose the
                 application of the approach to explicit extrapolation
                 methods for solving initial value problems of ordinary
                 differential equations (ODEs). The presented routines
                 can be effective for a large system of linear ODEs,
                 especially when a harmonic sequence is used.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; arithmetic operations; BLAS1 functions;
                 Convergence; differential equations; efficient
                 double-double BLAS1 function; EFT; error-free
                 transformation; error-free transformation,
                 extrapolation, ordinary differential equation; explicit
                 extrapolation methods; extrapolation; Extrapolation;
                 floating point arithmetic; Harmonic analysis; harmonic
                 sequence; ill-conditioned problems; initial value
                 problems; Libraries; mathematics computing; multiple
                 precision arithmetic; ordinary differential equations;
                 performance evaluation; Silicon; Standards",
}


bibtype: article
filename: fparith.bib
label: Kulisch:2019:MSI
author: Ulrich Kulisch
title: Mathematics and Speed for Interval Arithmetic: A Complement to IEEE 1788
journal: j-TOMS
volume: 45
number: 1
pages: 5:1--5:22
month: mar
monthnumber: 3
year: 2019
CODEN: ACMSCU
DOI: https://doi.org/10.1145/3264448
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Mon May 6 18:23:42 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib
bibtimestamp: 2019.05.06 18:23:42 MDT
URL: https://dl.acm.org/citation.cfm?id=3264448
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 5
journalURL: https://dl.acm.org/loi/toms
rawauthor: Ulrich Kulisch
rawtitle: Mathematics and Speed for Interval Arithmetic: A Complement to {IEEE 1788}
abstract:
After a short introduction, the article begins with an axiomatic definition of rounded arithmetic. The concepts of rounding and of rounded arithmetic operations are defined in an axiomatic manner fully independent of special data formats and encodings. Basic properties of floating-point and interval arithmetic can directly be derived from this abstract mathematical model. Interval operations are defined as set operations for elements of the set IR of closed and connected sets of real numbers. As such, they form an algebraically closed subset of the powerset of the real numbers. This property leads to explicit formulas for the arithmetic operations of floating-point intervals of IF, which are executable on the computer. Arithmetic for intervals of IF forms an exception free calculus, i.e., arithmetic operations for intervals of IF always lead to intervals of IF again. Later sections are concerned with programming support and hardware for interval arithmetic. Both are a must and absolutely necessary to move interval arithmetic more into the center of scientific computing. With some minor hardware additions, interval operations can be made as fast as simple floating-point operations. In vector and matrix spaces for real, complex, and interval data, the dot product is a fundamental arithmetic operation. Computing the dot product of two vectors with floating-point components exactly substantially speeds up floating-point and interval arithmetic as well as the accuracy of the computed result. Hardware needed for the exact dot product is very modest. The exact dot product is essential for long real and long interval arithmetic. Section 9 illustrates that interval arithmetic as developed in this article already has a long tradition. Products based on these ideas have been available since 1980. Implementing what the article advocates would have a profound effect on mathematical software. Modern processor architecture from Intel, for example, comes quite close to what is requested in this article.

rawabstract:
After a short introduction, the article begins with an axiomatic definition of rounded arithmetic. The concepts of rounding and of rounded arithmetic operations are defined in an axiomatic manner fully independent of special data formats and encodings. Basic properties of floating-point and interval arithmetic can directly be derived from this abstract mathematical model. Interval operations are defined as set operations for elements of the set {\=I}R of closed and connected sets of real numbers. As such, they form an algebraically closed subset of the powerset of the real numbers. This property leads to explicit formulas for the arithmetic operations of floating-point intervals of {\=I}F, which are executable on the computer. Arithmetic for intervals of {\=I}F forms an exception free calculus, i.e., arithmetic operations for intervals of {\=I}F always lead to intervals of {\=I}F again. Later sections are concerned with programming support and hardware for interval arithmetic. Both are a must and absolutely necessary to move interval arithmetic more into the center of scientific computing. With some minor hardware additions, interval operations can be made as fast as simple floating-point operations. In vector and matrix spaces for real, complex, and interval data, the dot product is a fundamental arithmetic operation. Computing the dot product of two vectors with floating-point components exactly substantially speeds up floating-point and interval arithmetic as well as the accuracy of the computed result. Hardware needed for the exact dot product is very modest. The exact dot product is essential for long real and long interval arithmetic. Section 9 illustrates that interval arithmetic as developed in this article already has a long tradition. Products based on these ideas have been available since 1980. Implementing what the article advocates would have a profound effect on mathematical software. Modern processor architecture from Intel, for example, comes quite close to what is requested in this article.

entry:
@Article{Kulisch:2019:MSI,
  author =       "Ulrich Kulisch",
  title =        "Mathematics and Speed for Interval Arithmetic: A
                 Complement to {IEEE 1788}",
  journal =      j-TOMS,
  volume =       "45",
  number =       "1",
  pages =        "5:1--5:22",
  month =        mar,
  year =         "2019",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/3264448",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Mon May 6 18:23:42 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  URL =          "https://dl.acm.org/citation.cfm?id=3264448",
  abstract =     "After a short introduction, the article begins with an
                 axiomatic definition of rounded arithmetic. The
                 concepts of rounding and of rounded arithmetic
                 operations are defined in an axiomatic manner fully
                 independent of special data formats and encodings.
                 Basic properties of floating-point and interval
                 arithmetic can directly be derived from this abstract
                 mathematical model. Interval operations are defined as
                 set operations for elements of the set {\=I}R of closed
                 and connected sets of real numbers. As such, they form
                 an algebraically closed subset of the powerset of the
                 real numbers. This property leads to explicit formulas
                 for the arithmetic operations of floating-point
                 intervals of {\=I}F, which are executable on the
                 computer. Arithmetic for intervals of {\=I}F forms an
                 exception free calculus, i.e., arithmetic operations
                 for intervals of {\=I}F always lead to intervals of
                 {\=I}F again. Later sections are concerned with
                 programming support and hardware for interval
                 arithmetic. Both are a must and absolutely necessary to
                 move interval arithmetic more into the center of
                 scientific computing. With some minor hardware
                 additions, interval operations can be made as fast as
                 simple floating-point operations. In vector and matrix
                 spaces for real, complex, and interval data, the dot
                 product is a fundamental arithmetic operation.
                 Computing the dot product of two vectors with
                 floating-point components exactly substantially speeds
                 up floating-point and interval arithmetic as well as
                 the accuracy of the computed result. Hardware needed
                 for the exact dot product is very modest. The exact dot
                 product is essential for long real and long interval
                 arithmetic. Section 9 illustrates that interval
                 arithmetic as developed in this article already has a
                 long tradition. Products based on these ideas have been
                 available since 1980. Implementing what the article
                 advocates would have a profound effect on mathematical
                 software. Modern processor architecture from Intel, for
                 example, comes quite close to what is requested in this
                 article.",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: inproceedings
filename: fparith.bib
label: Laguna:2019:FDF
author: Ignacio Laguna
editor: IEEE / ACM
title: FPChecker: Detecting Floating-Point Exceptions in GPU Applications
publisher: pub-ACM
address: pub-ACM:adr
pages: 1126--1129
month: nov
monthnumber: 11
year: 2019
DOI: https://doi.org/10.1109/ase.2019.00118
ISBN: 1-72812-508-1 OR 1728125081
ISBN13: 978-1-72812-508-4 OR 9781728125084
LCCN: QA76.758 .Z566 2019
bibdate: Mon Sep 11 07:07:01 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.11 07:07:01 ???
acknowledgement: ack-nhfb
bookpages: xxxv + 1296
rawauthor: Ignacio Laguna
raweditor: IEEE\slash ACM
rawtitle: {FPChecker}: Detecting Floating-Point Exceptions in {GPU} Applications
booktitle:
ASE'19: 34th IEEE / ACM International Conference on Automated Software Engineering, San Diego, California, November 10--15, 2019

abstract:
Floating-point arithmetic is widely used in applications from several fields including scientific computing, machine learning, graphics, and finance. Many of these applications are rapidly adopting the use of GPUs to speedup computations. GPUs, however, have limited support to detect floating-point exceptions, which hinders the development of reliable applications in GPU-based systems. We present FPCHECKER, the first tool to automatically detect floating-point exceptions in GPU applications. FPCHECKER uses the clang / LLVM compiler to instrument GPU kernels and to detect exceptions at runtime. Once an exception is detected, it reports to the programmer the code location of the exception as well as other useful information. The programmer can then use this report to avoid the exception, e.g., by modifying the application algorithm or changing the input. We present the design of FPCHECKER, an evaluation of the overhead of the tool, and a real-world case scenario on which the tool is used to identify a hidden exception. The slowdown of FPCHECKER is moderate and the code is publicly available as open source.

rawabstract:
Floating-point arithmetic is widely used in applications from several fields including scientific computing, machine learning, graphics, and finance. Many of these applications are rapidly adopting the use of GPUs to speedup computations. GPUs, however, have limited support to detect floating-point exceptions, which hinders the development of reliable applications in GPU-based systems. We present FPCHECKER, the first tool to automatically detect floating-point exceptions in GPU applications. FPCHECKER uses the clang\slash LLVM compiler to instrument GPU kernels and to detect exceptions at runtime. Once an exception is detected, it reports to the programmer the code location of the exception as well as other useful information. The programmer can then use this report to avoid the exception, e.g., by modifying the application algorithm or changing the input. We present the design of FPCHECKER, an evaluation of the overhead of the tool, and a real-world case scenario on which the tool is used to identify a hidden exception. The slowdown of FPCHECKER is moderate and the code is publicly available as open source.

rawbooktitle:
{ASE'19: 34th IEEE\slash ACM International Conference on Automated Software Engineering, San Diego, California, November 10--15, 2019}

entry:
@InProceedings{Laguna:2019:FDF,
  author =       "Ignacio Laguna",
  editor =       "IEEE\slash ACM",
  booktitle =    "{ASE'19: 34th IEEE\slash ACM International Conference
                 on Automated Software Engineering, San Diego,
                 California, November 10--15, 2019}",
  title =        "{FPChecker}: Detecting Floating-Point Exceptions in
                 {GPU} Applications",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  bookpages =    "xxxv + 1296",
  pages =        "1126--1129",
  month =        nov,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ase.2019.00118",
  ISBN =         "1-72812-508-1",
  ISBN-13 =      "978-1-72812-508-4",
  LCCN =         "QA76.758 .Z566 2019",
  bibdate =      "Mon Sep 11 07:07:01 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Floating-point arithmetic is widely used in
                 applications from several fields including scientific
                 computing, machine learning, graphics, and finance.
                 Many of these applications are rapidly adopting the use
                 of GPUs to speedup computations. GPUs, however, have
                 limited support to detect floating-point exceptions,
                 which hinders the development of reliable applications
                 in GPU-based systems. We present FPCHECKER, the first
                 tool to automatically detect floating-point exceptions
                 in GPU applications. FPCHECKER uses the clang\slash
                 LLVM compiler to instrument GPU kernels and to detect
                 exceptions at runtime. Once an exception is detected,
                 it reports to the programmer the code location of the
                 exception as well as other useful information. The
                 programmer can then use this report to avoid the
                 exception, e.g., by modifying the application algorithm
                 or changing the input. We present the design of
                 FPCHECKER, an evaluation of the overhead of the tool,
                 and a real-world case scenario on which the tool is
                 used to identify a hidden exception. The slowdown of
                 FPCHECKER is moderate and the code is publicly
                 available as open source.",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Laguna:2019:GPD
author: Ignacio Laguna and Paul C. Wood and Ranvijay Singh and Saurabh Bagchi
title: GPUMixer: Performance-Driven Floating-Point Tuning for GPU Scientific Applications
type: Report
institution: Lawrence Livermore National Laboratory
address: Livermore CA 94550, USA
pages: 1126--1129
year: 2019
bibdate: Tue Aug 06 05:54:23 2019
bibtimestamp: 2019.08.06 05:54:23 ???
remark: Best paper award at the 33rd ISC High Performance conference held June 16--20, 2019.
acknowledgement: ack-nhfb
rawauthor: Ignacio Laguna and Paul C. Wood and Ranvijay Singh and Saurabh Bagchi
rawtitle: {GPUMixer}: Performance-Driven Floating-Point Tuning for {GPU} Scientific Applications
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/multithreading.bib; https://www.math.utah.edu/pub/tex/bib/pvm.bib

URL:
http://lagunaresearch.org/docs/isc-2019.pdf; https://www.hpcwire.com/2019/08/05/llnl-purdue-researchers-harness-gpu-mixed-precision-for-accuracy-performance-tradeoff/

abstract:
We present GPUMixer, a tool to perform mixed-precision floating-point tuning on scientific GPU applications. While precision tuning techniques are available, they are designed for serial programs and are accuracy-driven, i.e., they consider configurations that satisfy accuracy constraints, but these configurations may degrade performance. GPUMixer, in contrast, presents a performance-driven approach for tuning. We introduce a novel static analysis that finds Fast Imprecise Sets (FISets), sets of operations on low precision that minimize type conversions, which often yield performance speedups. To estimate the relative error introduced by GPU mixed-precision, we propose shadow computations analysis for GPUs, the first of this class for multi-threaded applications. GPUMixer obtains performance improvements of up to 46.4% of the ideal speedup in comparison to only 20.7% found by state-of-the-art methods.

rawabstract:
We present GPUMixer, a tool to perform mixed-precision floating-point tuning on scientific GPU applications. While precision tuning techniques are available, they are designed for serial programs and are accuracy-driven, i.e., they consider configurations that satisfy accuracy constraints, but these configurations may degrade performance. GPUMixer, in contrast, presents a performance-driven approach for tuning. We introduce a novel static analysis that finds Fast Imprecise Sets (FISets), sets of operations on low precision that minimize type conversions, which often yield performance speedups. To estimate the relative error introduced by GPU mixed-precision, we propose shadow computations analysis for GPUs, the first of this class for multi-threaded applications. GPUMixer obtains performance improvements of up to 46.4\% of the ideal speedup in comparison to only 20.7\% found by state-of-the-art methods.

entry:
@TechReport{Laguna:2019:GPD,
  author =       "Ignacio Laguna and Paul C. Wood and Ranvijay Singh and
                 Saurabh Bagchi",
  title =        "{GPUMixer}: Performance-Driven Floating-Point Tuning
                 for {GPU} Scientific Applications",
  type =         "Report",
  institution =  "Lawrence Livermore National Laboratory",
  address =      "Livermore CA 94550, USA",
  year =         "2019",
  bibdate =      "Tue Aug 06 05:54:23 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/multithreading.bib;
                 https://www.math.utah.edu/pub/tex/bib/pvm.bib",
  URL =          "http://lagunaresearch.org/docs/isc-2019.pdf;
                 https://www.hpcwire.com/2019/08/05/llnl-purdue-researchers-harness-gpu-mixed-precision-for-accuracy-performance-tradeoff/",
  abstract =     "We present GPUMixer, a tool to perform mixed-precision
                 floating-point tuning on scientific GPU applications.
                 While precision tuning techniques are available, they
                 are designed for serial programs and are
                 accuracy-driven, i.e., they consider configurations
                 that satisfy accuracy constraints, but these
                 configurations may degrade performance. GPUMixer, in
                 contrast, presents a performance-driven approach for
                 tuning. We introduce a novel static analysis that finds
                 Fast Imprecise Sets (FISets), sets of operations on low
                 precision that minimize type conversions, which often
                 yield performance speedups. To estimate the relative
                 error introduced by GPU mixed-precision, we propose
                 shadow computations analysis for GPUs, the first of
                 this class for multi-threaded applications. GPUMixer
                 obtains performance improvements of up to 46.4\% of the
                 ideal speedup in comparison to only 20.7\% found by
                 state-of-the-art methods.",
  acknowledgement = ack-nhfb,
  remark =       "Best paper award at the 33rd ISC High Performance
                 conference held June 16--20, 2019.",
}


bibtype: article
filename: fparith.bib
label: Lange:2019:SEP
author: Marko Lange and Siegfried M. Rump
title: Sharp estimates for perturbation errors in summations
journal: j-MATH-COMPUT
volume: 88
number: 315
pages: 349--368
month: jul
monthnumber: 7
year: 2019
CODEN: MCMPAF
DOI: https://doi.org/10.1090/mcom/3355
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
bibdate: Tue Jul 14 06:45:34 MDT 2020
bibtimestamp: 2020.07.14 06:45:34 MDT
fjournal: Mathematics of Computation
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Marko Lange and Siegfried M. Rump
rawtitle: Sharp estimates for perturbation errors in summations
bibsource:
http://www.ams.org/mcom/2019-88-315; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib

URL:
https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03355-5; https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03355-5/S0025-5718-2018-03355-5.pdf; https://www.ams.org/mathscinet/search/authors.html?mrauthid=1082372; https://www.ams.org/mathscinet/search/authors.html?mrauthid=151815

entry:
@Article{Lange:2019:SEP,
  author =       "Marko Lange and Siegfried M. Rump",
  title =        "Sharp estimates for perturbation errors in
                 summations",
  journal =      j-MATH-COMPUT,
  volume =       "88",
  number =       "315",
  pages =        "349--368",
  month =        jul,
  year =         "2019",
  CODEN =        "MCMPAF",
  DOI =          "https://doi.org/10.1090/mcom/3355",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  bibdate =      "Tue Jul 14 06:45:34 MDT 2020",
  bibsource =    "http://www.ams.org/mcom/2019-88-315;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib",
  URL =          "https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03355-5;
                 https://www.ams.org/journals/mcom/2019-88-315/S0025-5718-2018-03355-5/S0025-5718-2018-03355-5.pdf;
                 https://www.ams.org/mathscinet/search/authors.html?mrauthid=1082372;
                 https://www.ams.org/mathscinet/search/authors.html?mrauthid=151815",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
  keywords =     "accurate floating-point summation",
}


bibtype: inproceedings
filename: fparith.bib
label: Lefevre:2019:ACM
author: Vincent Lefevre and Jean-Michel Muller
title: Accurate Complex Multiplication in Floating-Point Arithmetic
crossref: Takagi:2019:ISC
pages: 23--29
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00013
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Vincent Lef{\`e}vre and Jean-Michel Muller
rawtitle: Accurate Complex Multiplication in Floating-Point Arithmetic
abstract:
We deal with accurate complex multiplication in binary floating-point arithmetic, with an emphasis on the case where one of the operands is a ``double-word'' number. We provide an algorithm that returns a complex product with normwise relative error bound close to the best possible one, i.e., the rounding unit u.

keywords:
accurate complex multiplication; Approximation algorithms; ARITH-26; binary floating-point arithmetic; complex product; Digital arithmetic; double-word number; floating point arithmetic; Floating-point arithmetic; Floating-point arithmetic, Complex multiplication, Rounding error analysis; Lips; Parallel processing; Standards; Zirconium

rawabstract:
We deal with accurate complex multiplication in binary floating-point arithmetic, with an emphasis on the case where one of the operands is a ``double-word'' number. We provide an algorithm that returns a complex product with normwise relative error bound close to the best possible one, i.e., the rounding unit u.

entry:
@InProceedings{Lefevre:2019:ACM,
  author =       "Vincent Lef{\`e}vre and Jean-Michel Muller",
  title =        "Accurate Complex Multiplication in Floating-Point
                 Arithmetic",
  crossref =     "Takagi:2019:ISC",
  pages =        "23--29",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00013",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We deal with accurate complex multiplication in binary
                 floating-point arithmetic, with an emphasis on the case
                 where one of the operands is a ``double-word'' number.
                 We provide an algorithm that returns a complex product
                 with normwise relative error bound close to the best
                 possible one, i.e., the rounding unit u.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate complex multiplication; Approximation
                 algorithms; ARITH-26; binary floating-point arithmetic;
                 complex product; Digital arithmetic; double-word
                 number; floating point arithmetic; Floating-point
                 arithmetic; Floating-point arithmetic, Complex
                 multiplication, Rounding error analysis; Lips; Parallel
                 processing; Standards; Zirconium",
}


bibtype: article
filename: fparith.bib
label: Lemire:2019:FRD
author: Daniel Lemire and Owen Kaser and Nathan Kurz
title: Faster remainder by direct computation: Applications to compilers and software libraries
journal: j-SPE
volume: 49
number: 6
pages: 953--970
month: jun
monthnumber: 6
year: 2019
CODEN: SPEXBL
DOI: https://doi.org/10.1002/spe.2689
ISSN: 0038-0644 (print), 1097-024X (electronic) OR 00380644 (print), 1097024X (electronic)
ISSNL: 0038-0644 OR 00380644
bibdate: Sat Oct 12 09:43:47 MDT 2019
bibtimestamp: 2019.10.12 09:43:47 MDT
fjournal: Software --- Practice and Experience
keywords: integer division; integer remainder
acknowledgement: ack-nhfb
journalURL: http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X
onlinedate: 27 February 2019
rawauthor: Daniel Lemire and Owen Kaser and Nathan Kurz
rawtitle: Faster remainder by direct computation: Applications to compilers and software libraries
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/spe.bib

remark:
Paul Zimmermann reported on the gmp-devel mailing list on Tue, 15 Oct 2019 10:40:48 +0200 that the remainder algorithm in this report was described earlier in unpublished work in cite Bernstein:2004:SRT.

entry:
@Article{Lemire:2019:FRD,
  author =       "Daniel Lemire and Owen Kaser and Nathan Kurz",
  title =        "Faster remainder by direct computation: Applications
                 to compilers and software libraries",
  journal =      j-SPE,
  volume =       "49",
  number =       "6",
  pages =        "953--970",
  month =        jun,
  year =         "2019",
  CODEN =        "SPEXBL",
  DOI =          "https://doi.org/10.1002/spe.2689",
  ISSN =         "0038-0644 (print), 1097-024X (electronic)",
  ISSN-L =       "0038-0644",
  bibdate =      "Sat Oct 12 09:43:47 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/spe.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Software --- Practice and Experience",
  journal-URL =  "http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1097-024X",
  keywords =     "integer division; integer remainder",
  onlinedate =   "27 February 2019",
  remark =       "Paul Zimmermann reported on the gmp-devel mailing list
                 on Tue, 15 Oct 2019 10:40:48 +0200 that the remainder
                 algorithm in this report was described earlier in
                 unpublished work in \cite{Bernstein:2004:SRT}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Lindstrom:2019:UCR
author: Peter Lindstrom
title: Universal Coding of the Reals Using Bisection
crossref: Gustafson:2019:CPC
pages: 7:1--7:10
year: 2019
DOI: https://doi.org/10.1145/3316279.3316286
bibdate: Mon Feb 10 12:11:16 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.10 12:11:16 ???
acknowledgement: ack-nhfb
articleno: 7
rawauthor: Peter Lindstrom
rawtitle: Universal Coding of the Reals Using Bisection
keywords:
wobbling accuracy, floating point, bracketing, binary search, bisection, Universal coding, posits, unbounded search

entry:
@InProceedings{Lindstrom:2019:UCR,
  author =       "Peter Lindstrom",
  title =        "Universal Coding of the Reals Using Bisection",
  crossref =     "Gustafson:2019:CPC",
  pages =        "7:1--7:10",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316286",
  bibdate =      "Mon Feb 10 12:11:16 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "7",
  keywords =     "wobbling accuracy, floating point, bracketing, binary
                 search, bisection, Universal coding, posits, unbounded
                 search",
  location =     "Singapore, Singapore",
  numpages =     "10",
}


bibtype: article
filename: fparith.bib
label: Liu:2019:DAA
author: W. Liu and T. Cao and P. Yin and Y. Zhu and C. Wang and E. E. Swartzlander and F. Lombardi
title: Design and Analysis of Approximate Redundant Binary Multipliers
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 6
pages: 804--819
month: jun
monthnumber: 6
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2890222
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: W. Liu and T. Cao and P. Yin and Y. Zhu and C. Wang and E. E. Swartzlander and F. Lombardi
rawtitle: Design and Analysis of Approximate Redundant Binary Multipliers
keywords:
adders; Adders; approximate arithmetic designs; approximate Booth encoders; approximate circuits; approximate computing; Approximate computing; approximate NB Booth multipliers; approximate product arrays; approximate RB multipliers; approximate redundant binary multiplier design; Compressors; Delays; Error analysis; error analysis; error characteristics; error-resilient applications; error-tolerant applications; exact regular partial product arrays; Hardware; hardware simulation; logic design; low power; low power circuits; modified Booth encoder; multiplying circuits; partial product array; Power demand; RB 4:2 compressors; RB adders; RB compressor; RB compressors; RB-NB converter; RB-normal binary converter; redundant binary (RB) multiplier

entry:
@Article{Liu:2019:DAA,
  author =       "W. Liu and T. Cao and P. Yin and Y. Zhu and C. Wang
                 and E. E. Swartzlander and F. Lombardi",
  title =        "Design and Analysis of Approximate Redundant Binary
                 Multipliers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "6",
  pages =        "804--819",
  month =        jun,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2890222",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "adders; Adders; approximate arithmetic designs;
                 approximate Booth encoders; approximate circuits;
                 approximate computing; Approximate computing;
                 approximate NB Booth multipliers; approximate product
                 arrays; approximate RB multipliers; approximate
                 redundant binary multiplier design; Compressors;
                 Delays; Error analysis; error analysis; error
                 characteristics; error-resilient applications;
                 error-tolerant applications; exact regular partial
                 product arrays; Hardware; hardware simulation; logic
                 design; low power; low power circuits; modified Booth
                 encoder; multiplying circuits; partial product array;
                 Power demand; RB 4:2 compressors; RB adders; RB
                 compressor; RB compressors; RB-NB converter; RB-normal
                 binary converter; redundant binary (RB) multiplier",
}


bibtype: article
filename: fparith.bib
label: Lourenco:2019:ESS
author: Christopher Lourenco and Adolfo R. Escobedo and Erick Moreno-Centeno and Timothy A. Davis
journal: j-SIAM-J-MAT-ANA-APPL
volume: 40
number: 2
pages: 609--638
year: 2019
CODEN: SJMAEL
DOI: https://doi.org/10.1137/18M1202499
ISSN: 0895-4798 (print), 1095-7162 (electronic) OR 08954798 (print), 10957162 (electronic)
ISSNL: 0895-4798 OR 08954798
bibdate: Thu Oct 10 08:00:32 MDT 2019
bibtimestamp: 2019.10.10 08:00:32 MDT
fjournal: SIAM Journal on Matrix Analysis and Applications
keywords: exact rational arithmetic; Sparse Left-looking Integer-Preserving (SLIP) LU factorization
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/simax
onlinedate: January 2019
rawauthor: Christopher Lourenco and Adolfo R. Escobedo and Erick Moreno-Centeno and Timothy A. Davis
title:
Exact Solution of Sparse Linear Systems via Left-Looking Roundoff-Error-Free $ L U $ Factorization in Time Proportional to Arithmetic Work

bibsource:
http://epubs.siam.org/sam-bin/dbq/toc/SIMAX/40/2; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjmatanaappl.bib

rawtitle:
Exact Solution of Sparse Linear Systems via Left-Looking Roundoff-Error-Free {$ L U $} Factorization in Time Proportional to Arithmetic Work

entry:
@Article{Lourenco:2019:ESS,
  author =       "Christopher Lourenco and Adolfo R. Escobedo and Erick
                 Moreno-Centeno and Timothy A. Davis",
  title =        "Exact Solution of Sparse Linear Systems via
                 Left-Looking Roundoff-Error-Free {$ L U $}
                 Factorization in Time Proportional to Arithmetic Work",
  journal =      j-SIAM-J-MAT-ANA-APPL,
  volume =       "40",
  number =       "2",
  pages =        "609--638",
  month =        "????",
  year =         "2019",
  CODEN =        "SJMAEL",
  DOI =          "https://doi.org/10.1137/18M1202499",
  ISSN =         "0895-4798 (print), 1095-7162 (electronic)",
  ISSN-L =       "0895-4798",
  bibdate =      "Thu Oct 10 08:00:32 MDT 2019",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SIMAX/40/2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjmatanaappl.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Matrix Analysis and Applications",
  journal-URL =  "http://epubs.siam.org/simax",
  keywords =     "exact rational arithmetic; Sparse Left-looking
                 Integer-Preserving (SLIP) LU factorization",
  onlinedate =   "January 2019",
}


bibtype: inproceedings
filename: fparith.bib
label: Lu:2019:TDN
author: Jinming Lu and Siyuan Lu and Zhisheng Wang and Chao Fang and Jun Lin and Zhongfeng Wang and Li Du
editor: IEEE
booktitle: 2019 32nd IEEE International System-on-Chip Conference (SOCC)
title: Training Deep Neural Networks Using Posit Number System
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 62--67
year: 2019
DOI: https://doi.org/10.1109/SOCC46988.2019.1570558530
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Jinming Lu and Siyuan Lu and Zhisheng Wang and Chao Fang and Jun Lin and Zhongfeng Wang and Li Du
rawbooktitle: {2019 32nd IEEE International System-on-Chip Conference (SOCC)}
raweditor: {IEEE}
rawtitle: Training Deep Neural Networks Using Posit Number System
entry:
@InProceedings{Lu:2019:TDN,
  author =       "Jinming Lu and Siyuan Lu and Zhisheng Wang and Chao
                 Fang and Jun Lin and Zhongfeng Wang and Li Du",
  editor =       "{IEEE}",
  booktitle =    "{2019 32nd IEEE International System-on-Chip
                 Conference (SOCC)}",
  title =        "Training Deep Neural Networks Using Posit Number
                 System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "62--67",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/SOCC46988.2019.1570558530",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lutz:2019:AFP
author: David Lutz
title: ARM Floating Point 2019: Latency, Area, Power
crossref: Takagi:2019:ISC
pages: 97--98
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00025
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: David Lutz
rawtitle: {ARM} Floating Point 2019: Latency, Area, Power
abstract:
We have had little or no speed increase from process in the past few years, but latency continues to decrease due to algorithmic improvements [1] and a decision to spend more area on CPU datapaths [2]. A binary64 floating-point (FP) add now takes two cycles when done as part of a 2+2-cycle FMA, and even one cycle when done as part of an in-order vector reduction. Smaller and more specialized FP operations (bfloat16) are even faster. Finally, the decision to spend more area on datapath logic took a new twist this year when we applied it to GPUs, cutting dynamic power there by a third.

keywords:
2+2-cycle FMA; adders; Adders; ARITH-26; ARM floating point 2019; bfloat16; binary64 floating-point; Clocks; CPU datapaths; datapath logic; Digital arithmetic; floating point arithmetic; in-order vector reduction; Microarchitecture; Pipelines; random number generation; Security; Standards; vectors

rawabstract:
We have had little or no speed increase from process in the past few years, but latency continues to decrease due to algorithmic improvements [1] and a decision to spend more area on CPU datapaths [2]. A binary64 floating-point (FP) add now takes two cycles when done as part of a 2+2-cycle FMA, and even one cycle when done as part of an in-order vector reduction. Smaller and more specialized FP operations (bfloat16) are even faster. Finally, the decision to spend more area on datapath logic took a new twist this year when we applied it to GPUs, cutting dynamic power there by a third.

entry:
@InProceedings{Lutz:2019:AFP,
  author =       "David Lutz",
  title =        "{ARM} Floating Point 2019: Latency, Area, Power",
  crossref =     "Takagi:2019:ISC",
  pages =        "97--98",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00025",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We have had little or no speed increase from process
                 in the past few years, but latency continues to
                 decrease due to algorithmic improvements [1] and a
                 decision to spend more area on CPU datapaths [2]. A
                 binary64 floating-point (FP) add now takes two cycles
                 when done as part of a 2+2-cycle FMA, and even one
                 cycle when done as part of an in-order vector
                 reduction. Smaller and more specialized FP operations
                 (bfloat16) are even faster. Finally, the decision to
                 spend more area on datapath logic took a new twist this
                 year when we applied it to GPUs, cutting dynamic power
                 there by a third.",
  acknowledgement = ack-nhfb,
  keywords =     "2+2-cycle FMA; adders; Adders; ARITH-26; ARM floating
                 point 2019; bfloat16; binary64 floating-point; Clocks;
                 CPU datapaths; datapath logic; Digital arithmetic;
                 floating point arithmetic; in-order vector reduction;
                 Microarchitecture; Pipelines; random number generation;
                 Security; Standards; vectors",
}


bibtype: misc
filename: fparith.bib
label: Lutz:2019:AMP
author: David Raymond Lutz and Neil Burgess and Christopher Neal Hinds and Andreas Due Engh-Halstvedt
title: Apparatus and method for performing arithmetic operations to accumulate floating-point numbers
pages: 97--98
day: 26
month: feb
monthnumber: 2
year: 2019
bibdate: Thu Oct 17 11:34:51 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.17 11:34:51 ???
URL: https://patents.google.com/patent/US10216479B2
acknowledgement: ack-nhfb
howpublished: US Patent 10,216,479
rawauthor: David Raymond Lutz and Neil Burgess and Christopher Neal Hinds and Andreas Due Engh-Halstvedt
rawtitle: Apparatus and method for performing arithmetic operations to accumulate floating-point numbers
abstract:
An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions. A convert and accumulate instruction is provided, and the decoder circuitry is responsive to decoding the convert and accumulate instruction to generate one or more control signals to control the execution circuitry to convert at least one floating-point operand identified by the convert and accumulate instruction into a corresponding N-bit fixed-point operand having M fraction bits, where M is less than N and M is dependent on a format of the floating-point operand. The execution circuitry accumulates each corresponding N bit fixed-point operand and a P bit fixed-point operand identified by the convert and accumulate instruction in order to generate a P bit fixed-point result value, where P is greater than N and also has M fraction bits.

remark:
Patent filed 6 December 2016, granted to Arm Ltd. on 26 February 2019, expected expiration 2 February 2037 (in 17th year of grant).

rawabstract:
An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions. A convert and accumulate instruction is provided, and the decoder circuitry is responsive to decoding the convert and accumulate instruction to generate one or more control signals to control the execution circuitry to convert at least one floating-point operand identified by the convert and accumulate instruction into a corresponding N-bit fixed-point operand having M fraction bits, where M is less than N and M is dependent on a format of the floating-point operand. The execution circuitry accumulates each corresponding N bit fixed-point operand and a P bit fixed-point operand identified by the convert and accumulate instruction in order to generate a P bit fixed-point result value, where P is greater than N and also has M fraction bits.

entry:
@Misc{Lutz:2019:AMP,
  author =       "David Raymond Lutz and Neil Burgess and Christopher
                 Neal Hinds and Andreas Due Engh-Halstvedt",
  title =        "Apparatus and method for performing arithmetic
                 operations to accumulate floating-point numbers",
  howpublished = "US Patent 10,216,479",
  day =          "26",
  month =        feb,
  year =         "2019",
  bibdate =      "Thu Oct 17 11:34:51 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://patents.google.com/patent/US10216479B2",
  abstract =     "An apparatus and method are provided for performing
                 arithmetic operations to accumulate floating-point
                 numbers. The apparatus comprises execution circuitry to
                 perform arithmetic operations, and decoder circuitry to
                 decode a sequence of instructions. A convert and
                 accumulate instruction is provided, and the decoder
                 circuitry is responsive to decoding the convert and
                 accumulate instruction to generate one or more control
                 signals to control the execution circuitry to convert
                 at least one floating-point operand identified by the
                 convert and accumulate instruction into a corresponding
                 N-bit fixed-point operand having M fraction bits, where
                 M is less than N and M is dependent on a format of the
                 floating-point operand. The execution circuitry
                 accumulates each corresponding N bit fixed-point
                 operand and a P bit fixed-point operand identified by
                 the convert and accumulate instruction in order to
                 generate a P bit fixed-point result value, where P is
                 greater than N and also has M fraction bits.",
  acknowledgement = ack-nhfb,
  remark =       "Patent filed 6 December 2016, granted to Arm Ltd. on
                 26 February 2019, expected expiration 2 February 2037
                 (in 17th year of grant).",
}


bibtype: inproceedings
filename: fparith.bib
label: Mach:2019:FSB
author: Stefan Mach and Fabian Schuiki and Florian Zaruba and Luca Benini
editor: IEEE
booktitle: 2019 IFIP / IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 95--98
year: 2019
DOI: https://doi.org/10.1109/VLSI-SoC.2019.8920307
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawauthor: Stefan Mach and Fabian Schuiki and Florian Zaruba and Luca Benini
rawbooktitle: {2019 IFIP\slash IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)}
raweditor: {IEEE}
title:
A 0.80pJ / flop, 1.24Tflop / sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI

rawtitle:
A {0.80pJ\slash flop, 1.24Tflop\slash sW} 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit {RISC-V} Processor in 22nm {FD-SOI}

entry:
@InProceedings{Mach:2019:FSB,
  author =       "Stefan Mach and Fabian Schuiki and Florian Zaruba and
                 Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2019 IFIP\slash IEEE 27th International Conference on
                 Very Large Scale Integration (VLSI-SoC)}",
  title =        "A {0.80pJ\slash flop, 1.24Tflop\slash sW} 8-to-64 bit
                 Transprecision Floating-Point Unit for a 64 bit
                 {RISC-V} Processor in 22nm {FD-SOI}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "95--98",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/VLSI-SoC.2019.8920307",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Magron:2019:CRE
author: V. Magron and A. Rocca and T. Dang
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 7
pages: 953--966
month: jul
monthnumber: 7
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2851235
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: V. Magron and A. Rocca and T. Dang
title:
Certified Roundoff Error Bounds Using Bernstein Expansions and Sparse Krivine--Stengle Representations

keywords:
Algebra; Bernstein expansions; Convergence; embedded systems; embedded systems implementation; error analysis; floating point arithmetic; FPBern software package; FPKriSten software package; Krivine-Stengle representations; linear programming; linear programming relaxations; nonlinear programs; Optimization; Polynomial optimization; polynomials; rational functions; rigorous upper bounds; roundoff error bounds; roundoff errors; Roundoff errors; Software algorithms; Tools; Upper bound

rawtitle:
Certified Roundoff Error Bounds Using {Bernstein} Expansions and Sparse {Krivine--Stengle} Representations

entry:
@Article{Magron:2019:CRE,
  author =       "V. Magron and A. Rocca and T. Dang",
  title =        "Certified Roundoff Error Bounds Using {Bernstein}
                 Expansions and Sparse {Krivine--Stengle}
                 Representations",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "7",
  pages =        "953--966",
  month =        jul,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2851235",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Algebra; Bernstein expansions; Convergence; embedded
                 systems; embedded systems implementation; error
                 analysis; floating point arithmetic; FPBern software
                 package; FPKriSten software package; Krivine-Stengle
                 representations; linear programming; linear programming
                 relaxations; nonlinear programs; Optimization;
                 Polynomial optimization; polynomials; rational
                 functions; rigorous upper bounds; roundoff error
                 bounds; roundoff errors; Roundoff errors; Software
                 algorithms; Tools; Upper bound",
}


bibtype: inproceedings
filename: fparith.bib
label: Martins:2019:HHR
author: Paulo Martins and Jeremy Marrez and Jean-Claude Bajard and Leonel Sousa
title: HyPoRes: An Hybrid Representation System for ECC
crossref: Takagi:2019:ISC
pages: 207--214
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00049
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Paulo Martins and Jeremy Marrez and Jean-Claude Bajard and Leonel Sousa
rawtitle: {HyPoRes}: An Hybrid Representation System for {ECC}
abstract:
The Residue Number System (RNS) is a numeral representation enabling for more efficient addition and multiplication implementations. However, due its non-positional nature, modular reductions, required for example by Elliptic Curve (EC) Cryptography (ECC), become costlier. Traditional approaches to RNS modular reduction resort to the Montgomery algorithm, underpinned by large basis extensions. Recently, Hybrid-Positional Residue Number Systems (HPRs) have been proposed, providing a trade-off between the efficiency of RNS and the flexibility of positional number representations. Numbers are represented in a positional representation with the coefficients represented in RNS. By crafting primes of a special form, the complexity of reductions modulo those primes is mitigated, relying on extensions of smaller bases. Due to the need of crafting special primes, this approach is not directly extensible to group operations over currently standardised elliptic curves. In this paper, the Hybrid-Polynomial Residue Number System (HyPoRes) is proposed, enabling for improved modular reductions for any prime. Experimental results show that the modular reduction of HyPoRes, although at most 1.4 times slower than HPR for HPR-crafted primes, is up to 1.4 times faster than a generic RNS approach for primes of ECC standards.

keywords:
ARITH-26; Art; Complexity theory; Dynamic range; ECC standards; Elliptic Curve Cryp-tography; Elliptic curve cryptography; elliptic curve cryptography; Elliptic curves; generic RNS approach; HPR-crafted primes; hybrid representation system; hybrid-polynomial residue number system; hybrid-positional residue number systems; HyPoRes; improved modular reductions; Lattices; Modular Arithmetic; Montgomery algorithm; multiplication implementations; polynomials; positional number representations; public key cryptography; Residue Number System; residue number systems; RNS modular reduction

rawabstract:
The Residue Number System (RNS) is a numeral representation enabling for more efficient addition and multiplication implementations. However, due its non-positional nature, modular reductions, required for example by Elliptic Curve (EC) Cryptography (ECC), become costlier. Traditional approaches to RNS modular reduction resort to the Montgomery algorithm, underpinned by large basis extensions. Recently, Hybrid-Positional Residue Number Systems (HPRs) have been proposed, providing a trade-off between the efficiency of RNS and the flexibility of positional number representations. Numbers are represented in a positional representation with the coefficients represented in RNS. By crafting primes of a special form, the complexity of reductions modulo those primes is mitigated, relying on extensions of smaller bases. Due to the need of crafting special primes, this approach is not directly extensible to group operations over currently standardised elliptic curves. In this paper, the Hybrid-Polynomial Residue Number System (HyPoRes) is proposed, enabling for improved modular reductions for any prime. Experimental results show that the modular reduction of HyPoRes, although at most 1.4 times slower than HPR for HPR-crafted primes, is up to 1.4 times faster than a generic RNS approach for primes of ECC standards.

entry:
@InProceedings{Martins:2019:HHR,
  author =       "Paulo Martins and Jeremy Marrez and Jean-Claude Bajard
                 and Leonel Sousa",
  title =        "{HyPoRes}: An Hybrid Representation System for {ECC}",
  crossref =     "Takagi:2019:ISC",
  pages =        "207--214",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00049",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The Residue Number System (RNS) is a numeral
                 representation enabling for more efficient addition and
                 multiplication implementations. However, due its
                 non-positional nature, modular reductions, required for
                 example by Elliptic Curve (EC) Cryptography (ECC),
                 become costlier. Traditional approaches to RNS modular
                 reduction resort to the Montgomery algorithm,
                 underpinned by large basis extensions. Recently,
                 Hybrid-Positional Residue Number Systems (HPRs) have
                 been proposed, providing a trade-off between the
                 efficiency of RNS and the flexibility of positional
                 number representations. Numbers are represented in a
                 positional representation with the coefficients
                 represented in RNS. By crafting primes of a special
                 form, the complexity of reductions modulo those primes
                 is mitigated, relying on extensions of smaller bases.
                 Due to the need of crafting special primes, this
                 approach is not directly extensible to group operations
                 over currently standardised elliptic curves. In this
                 paper, the Hybrid-Polynomial Residue Number System
                 (HyPoRes) is proposed, enabling for improved modular
                 reductions for any prime. Experimental results show
                 that the modular reduction of HyPoRes, although at most
                 1.4 times slower than HPR for HPR-crafted primes, is up
                 to 1.4 times faster than a generic RNS approach for
                 primes of ECC standards.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Art; Complexity theory; Dynamic range; ECC
                 standards; Elliptic Curve Cryp-tography; Elliptic curve
                 cryptography; elliptic curve cryptography; Elliptic
                 curves; generic RNS approach; HPR-crafted primes;
                 hybrid representation system; hybrid-polynomial residue
                 number system; hybrid-positional residue number
                 systems; HyPoRes; improved modular reductions;
                 Lattices; Modular Arithmetic; Montgomery algorithm;
                 multiplication implementations; polynomials; positional
                 number representations; public key cryptography;
                 Residue Number System; residue number systems; RNS
                 modular reduction",
}


bibtype: inproceedings
filename: fparith.bib
label: Matula:2019:PCG
author: David W. Matula and Zizhen Chen
title: Precise and Concise Graphical Representation of the Natural Numbers
crossref: Takagi:2019:ISC
pages: 100--103
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00027
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: David W. Matula and Zizhen Chen
rawtitle: Precise and Concise Graphical Representation of the Natural Numbers
abstract:
A graphical number representation system based on the formal logic foundation of a recursively defined function is presented. The function exposes a one-to-one correspondence between the natural numbers and the set of rooted trees. Secondly, a relation between pairs of natural numbers is shown to partition the integers into disjoint finite sets each visualized as a tree in the forest of all finite trees. This relation encapsulates in visual form the natural structure and distribution of primes in a manner not previously investigated. These representations allow arithmeticians to visually experience natural numbers in a 2D graphical layout. This form is free of cultural choices such as the number of symbols in an alphabet and/or one-dimensional symbol strings. The fundamental nature of these mappings is argued to be accessible to a creative mind independent of formal schooling. This short note includes examples illustrating the simplicity of the constructions.

keywords:
2D graphical layout; ARITH-26; Computer science; disjoint finite sets; finite trees; Forestry; formal logic foundation; graphical number representation system; graphical representation; Labeling; natural numbers; natural structure; number fonts; one-dimensional symbol strings; one-to-one correspondence; prime factorization; prime number function; recursive function; recursive functions; recursively defined function; rooted trees; trees (mathematics); Two dimensional displays; Vegetation; Visualization

rawabstract:
A graphical number representation system based on the formal logic foundation of a recursively defined function is presented. The function exposes a one-to-one correspondence between the natural numbers and the set of rooted trees. Secondly, a relation between pairs of natural numbers is shown to partition the integers into disjoint finite sets each visualized as a tree in the forest of all finite trees. This relation encapsulates in visual form the natural structure and distribution of primes in a manner not previously investigated. These representations allow arithmeticians to visually experience natural numbers in a 2D graphical layout. This form is free of cultural choices such as the number of symbols in an alphabet and/or one-dimensional symbol strings. The fundamental nature of these mappings is argued to be accessible to a creative mind independent of formal schooling. This short note includes examples illustrating the simplicity of the constructions.

entry:
@InProceedings{Matula:2019:PCG,
  author =       "David W. Matula and Zizhen Chen",
  title =        "Precise and Concise Graphical Representation of the
                 Natural Numbers",
  crossref =     "Takagi:2019:ISC",
  pages =        "100--103",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00027",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A graphical number representation system based on the
                 formal logic foundation of a recursively defined
                 function is presented. The function exposes a
                 one-to-one correspondence between the natural numbers
                 and the set of rooted trees. Secondly, a relation
                 between pairs of natural numbers is shown to partition
                 the integers into disjoint finite sets each visualized
                 as a tree in the forest of all finite trees. This
                 relation encapsulates in visual form the natural
                 structure and distribution of primes in a manner not
                 previously investigated. These representations allow
                 arithmeticians to visually experience natural numbers
                 in a 2D graphical layout. This form is free of cultural
                 choices such as the number of symbols in an alphabet
                 and/or one-dimensional symbol strings. The fundamental
                 nature of these mappings is argued to be accessible to
                 a creative mind independent of formal schooling. This
                 short note includes examples illustrating the
                 simplicity of the constructions.",
  acknowledgement = ack-nhfb,
  keywords =     "2D graphical layout; ARITH-26; Computer science;
                 disjoint finite sets; finite trees; Forestry; formal
                 logic foundation; graphical number representation
                 system; graphical representation; Labeling; natural
                 numbers; natural structure; number fonts;
                 one-dimensional symbol strings; one-to-one
                 correspondence; prime factorization; prime number
                 function; recursive function; recursive functions;
                 recursively defined function; rooted trees; trees
                 (mathematics); Two dimensional displays; Vegetation;
                 Visualization",
}


bibtype: article
filename: fparith.bib
label: Maynard:2019:MPA
author: C. M. Maynard and D. N. Walters
journal: j-COMP-PHYS-COMM
volume: 244
pages: 69--75
month: nov
monthnumber: 11
year: 2019
CODEN: CPHCBZ
ISSN: 0010-4655 (print), 1879-2944 (electronic) OR 00104655 (print), 18792944 (electronic)
ISSNL: 0010-4655 OR 00104655
bibdate: Fri Sep 6 11:03:48 MDT 2019
bibtimestamp: 2019.09.06 11:03:48 MDT
URL: https://www.sciencedirect.com/science/article/pii/S0010465519302127
fjournal: Computer Physics Communications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00104655
rawauthor: C. M. Maynard and D. N. Walters
title:
Mixed-precision arithmetic in the ENDGame dynamical core of the Unified Model, a numerical weather prediction and climate model code

bibsource:
https://www.math.utah.edu/pub/tex/bib/compphyscomm2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
Mixed-precision arithmetic in the {ENDGame} dynamical core of the {Unified Model}, a numerical weather prediction and climate model code

entry:
@Article{Maynard:2019:MPA,
  author =       "C. M. Maynard and D. N. Walters",
  title =        "Mixed-precision arithmetic in the {ENDGame} dynamical
                 core of the {Unified Model}, a numerical weather
                 prediction and climate model code",
  journal =      j-COMP-PHYS-COMM,
  volume =       "244",
  number =       "??",
  pages =        "69--75",
  month =        nov,
  year =         "2019",
  CODEN =        "CPHCBZ",
  ISSN =         "0010-4655 (print), 1879-2944 (electronic)",
  ISSN-L =       "0010-4655",
  bibdate =      "Fri Sep 6 11:03:48 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compphyscomm2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.sciencedirect.com/science/article/pii/S0010465519302127",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Physics Communications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00104655",
}


bibtype: article
filename: fparith.bib
label: McCullough:2019:WTS
author: B. D. McCullough and Taha Mokfi and Mahsa Almaeenjad
title: Wilkinson's Tests and SQL Packages
journal: j-SIGMOD
volume: 48
number: 3
pages: 17--22
month: sep
monthnumber: 9
year: 2019
CODEN: SRECD8
DOI: https://doi.org/10.1145/3377391.3377395
ISSN: 0163-5808 (print), 1943-5835 (electronic) OR 01635808 (print), 19435835 (electronic)
ISSNL: 0163-5808 OR 01635808
bibdate: Sat Dec 21 07:26:01 MST 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigmod.bib
bibtimestamp: 2019.12.21 07:26:01 MST
fjournal: SIGMOD Record (ACM Special Interest Group on Management of Data)
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J689
rawauthor: B. D. McCullough and Taha Mokfi and Mahsa Almaeenjad
rawtitle: {Wilkinson}'s Tests and {SQL} Packages
abstract:
Wilkinson's Tests are used to benchmark the accuracy of some statistical functions in six SQL packages: Apache Hive, Microsoft Access, Microsoft SQL Server, MySQL, Oracle 11g SQL, and SAP Hana. Using the best choice of data type, we find that different packages use different rounding schemes, two packages use unreliable algorithms to compute the sample variance, one package returns the population standard deviation when the sample standard deviation is called, and one package has an unstable algorithm for computing the correlation coefficient. Using the wrong data type all but guarantees inaccurate results.

remark:
This paper looks at statistical software inside six widely-used SQL databases, and find serious errors in most of them, and poor numerical implementations for standard deviations and other well-understood computational algorithms. See also earlier work recorded in fparith.bib cite McCullough:1998:ARS,McCullough:1999:ARS,McCullough:1999:NRE.

rawabstract:
Wilkinson's Tests are used to benchmark the accuracy of some statistical functions in six SQL packages: Apache Hive, Microsoft Access, Microsoft SQL Server, MySQL, Oracle 11g SQL, and SAP Hana. Using the best choice of data type, we find that different packages use different rounding schemes, two packages use unreliable algorithms to compute the sample variance, one package returns the population standard deviation when the sample standard deviation is called, and one package has an unstable algorithm for computing the correlation coefficient. Using the wrong data type all but guarantees inaccurate results.

entry:
@Article{McCullough:2019:WTS,
  author =       "B. D. McCullough and Taha Mokfi and Mahsa Almaeenjad",
  title =        "{Wilkinson}'s Tests and {SQL} Packages",
  journal =      j-SIGMOD,
  volume =       "48",
  number =       "3",
  pages =        "17--22",
  month =        sep,
  year =         "2019",
  CODEN =        "SRECD8",
  DOI =          "https://doi.org/10.1145/3377391.3377395",
  ISSN =         "0163-5808 (print), 1943-5835 (electronic)",
  ISSN-L =       "0163-5808",
  bibdate =      "Sat Dec 21 07:26:01 MST 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigmod.bib",
  abstract =     "Wilkinson's Tests are used to benchmark the accuracy
                 of some statistical functions in six SQL packages:
                 Apache Hive, Microsoft Access, Microsoft SQL Server,
                 MySQL, Oracle 11g SQL, and SAP Hana. Using the best
                 choice of data type, we find that different packages
                 use different rounding schemes, two packages use
                 unreliable algorithms to compute the sample variance,
                 one package returns the population standard deviation
                 when the sample standard deviation is called, and one
                 package has an unstable algorithm for computing the
                 correlation coefficient. Using the wrong data type all
                 but guarantees inaccurate results.",
  acknowledgement = ack-nhfb,
  fjournal =     "SIGMOD Record (ACM Special Interest Group on
                 Management of Data)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J689",
  remark =       "This paper looks at statistical software inside six
                 widely-used SQL databases, and find serious errors in
                 most of them, and poor numerical implementations for
                 standard deviations and other well-understood
                 computational algorithms. See also earlier work
                 recorded in fparith.bib
                 \cite{McCullough:1998:ARS,McCullough:1999:ARS,McCullough:1999:NRE}.",
}


bibtype: inproceedings
filename: fparith.bib
label: Melquiond:2019:FVS
author: Guillaume Melquiond and Raphael Rieu-Helft
title: Formal Verification of a State-of-the-Art Integer Square Root
crossref: Takagi:2019:ISC
pages: 183--186
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00041
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Guillaume Melquiond and Raphael Rieu-Helft
rawtitle: Formal Verification of a State-of-the-Art Integer Square Root
abstract:
We present the automatic formal verification of a state-of-the-art algorithm from the GMP library that computes the square root of a 64-bit integer. Although it uses only integer operations, the best way to understand the program is to view it as a fixed-point arithmetic algorithm that implements Newton's method. The C code is short but intricate, involving magic constants and intentional arithmetic overflows. We have verified the algorithm using the Why3 tool and automated solvers such as Gappa.

keywords:
64-bit integer; Approximation algorithms; ARITH-26; automatic formal verification; C code; C language; Convergence; Digital arithmetic; electronic engineering computing; fixed point arithmetic; Fixed-point arithmetic; fixed-point arithmetic algorithm; floating point arithmetic; Floors; Formal verification; GMP library; integer operations; integer square root; intentional arithmetic overflows; Libraries; Newton method; program verification; programming; Tools; Why3 tool

rawabstract:
We present the automatic formal verification of a state-of-the-art algorithm from the GMP library that computes the square root of a 64-bit integer. Although it uses only integer operations, the best way to understand the program is to view it as a fixed-point arithmetic algorithm that implements Newton's method. The C code is short but intricate, involving magic constants and intentional arithmetic overflows. We have verified the algorithm using the Why3 tool and automated solvers such as Gappa.

entry:
@InProceedings{Melquiond:2019:FVS,
  author =       "Guillaume Melquiond and Raphael Rieu-Helft",
  title =        "Formal Verification of a State-of-the-Art Integer
                 Square Root",
  crossref =     "Takagi:2019:ISC",
  pages =        "183--186",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00041",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present the automatic formal verification of a
                 state-of-the-art algorithm from the GMP library that
                 computes the square root of a 64-bit integer. Although
                 it uses only integer operations, the best way to
                 understand the program is to view it as a fixed-point
                 arithmetic algorithm that implements Newton's method.
                 The C code is short but intricate, involving magic
                 constants and intentional arithmetic overflows. We have
                 verified the algorithm using the Why3 tool and
                 automated solvers such as Gappa.",
  acknowledgement = ack-nhfb,
  keywords =     "64-bit integer; Approximation algorithms; ARITH-26;
                 automatic formal verification; C code; C language;
                 Convergence; Digital arithmetic; electronic engineering
                 computing; fixed point arithmetic; Fixed-point
                 arithmetic; fixed-point arithmetic algorithm; floating
                 point arithmetic; Floors; Formal verification; GMP
                 library; integer operations; integer square root;
                 intentional arithmetic overflows; Libraries; Newton
                 method; program verification; programming; Tools; Why3
                 tool",
}


bibtype: phdthesis
filename: fparith.bib
label: Melquiond:2019:NVN
author: Guillaume Melquiond
title: Normal Verification for Numerical Computations, and the Other Way Around
type: Habilitation a Diriger des Recherches
school: Universite Paris Sud, 2
address: Paris, France
pages: x + 163
day: 25
month: jul
monthnumber: 7
year: 2019
bibdate: Fri Sep 22 16:46:42 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.22 16:46:42 ???
URL: https://theses.hal.science/tel-02194683/document
acknowledgement: ack-nhfb
rawauthor: Guillaume Melquiond
rawtitle: Normal Verification for Numerical Computations, and the Other Way Around
entry:
@PhdThesis{Melquiond:2019:NVN,
  author =       "Guillaume Melquiond",
  title =        "Normal Verification for Numerical Computations, and
                 the Other Way Around",
  type =         "{Habilitation {\`a} Diriger des Recherches}",
  school =       "Universit{\'e} Paris Sud, 2",
  address =      "Paris, France",
  pages =        "x + 163",
  day =          "25",
  month =        jul,
  year =         "2019",
  bibdate =      "Fri Sep 22 16:46:42 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://theses.hal.science/tel-02194683/document",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Mian:2019:CAE
author: Riaz-ul-haque Mian and Michihiro Shintani and Michiko Inoue
editor: IEEE
booktitle: 2019 32nd IEEE International System-on-Chip Conference (SOCC)
title: Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 412--417
year: 2019
DOI: https://doi.org/10.1109/SOCC46988.2019.1570559752
bibdate: Sat Dec 16 15:51:40 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/risc-v.bib
bibtimestamp: 2023.12.16 15:51:40 ???
acknowledgement: ack-nhfb
rawauthor: Riaz-ul-haque Mian and Michihiro Shintani and Michiko Inoue
rawbooktitle: {2019 32nd IEEE International System-on-Chip Conference (SOCC)}
raweditor: {IEEE}
keywords:
Decimal arithmetic; Decimal multiplication; Evaluation framework; Hardware accelerator; RISC-V; RoCC; Rocket chip

rawtitle:
Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in {RISC-V} Ecosystem

entry:
@InProceedings{Mian:2019:CAE,
  author =       "Riaz-ul-haque Mian and Michihiro Shintani and Michiko
                 Inoue",
  editor =       "{IEEE}",
  booktitle =    "{2019 32nd IEEE International System-on-Chip
                 Conference (SOCC)}",
  title =        "Cycle-Accurate Evaluation of Software-Hardware
                 Co-Design of Decimal Computation in {RISC-V}
                 Ecosystem",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "412--417",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/SOCC46988.2019.1570559752",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Decimal arithmetic; Decimal multiplication; Evaluation
                 framework; Hardware accelerator; RISC-V; RoCC; Rocket
                 chip",
}


bibtype: misc
filename: fparith.bib
label: Moler:2019:CCF
author: Cleve Moler
title: Cleve's Corner: Floating Point Arithmetic Before IEEE 754
pages: 412--417
day: 18
month: jan
monthnumber: 1
year: 2019
bibdate: Sat Jan 19 15:18:17 2019
bibtimestamp: 2019.01.19 15:18:17 ???
URL: https://blogs.mathworks.com/cleve/2019/01/18/floating-point-arithmetic-before-ieee-754/
acknowledgement: ack-nhfb
howpublished: MathWorks Web site.
rawauthor: Cleve Moler
rawtitle: {Cleve}'s Corner: Floating Point Arithmetic Before {IEEE 754}
bibsource:
https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib; https://www.math.utah.edu/pub/bibnet/authors/m/moler-cleve-b.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
In a comment following my post about half-precision arithmetic, ``Raj C'' asked how the parameters for IEEE Standard 754 floating point arithmetic were chosen. I replied that I didn't know but would try to find out. I called emeritus U. C. Berkeley Professor W. (Velvel) Kahan, who was the principle architect of 754. Here is what I learned.

rawabstract:
In a comment following my post about half-precision arithmetic, ``Raj C'' asked how the parameters for IEEE Standard 754 floating point arithmetic were chosen. I replied that I didn't know but would try to find out. I called emeritus U. C. Berkeley Professor W. (Velvel) Kahan, who was the principle architect of 754. Here is what I learned.

entry:
@Misc{Moler:2019:CCF,
  author =       "Cleve Moler",
  title =        "{Cleve}'s Corner: Floating Point Arithmetic Before
                 {IEEE 754}",
  howpublished = "MathWorks Web site.",
  day =          "18",
  month =        jan,
  year =         "2019",
  bibdate =      "Sat Jan 19 15:18:17 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib;
                 https://www.math.utah.edu/pub/bibnet/authors/m/moler-cleve-b.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://blogs.mathworks.com/cleve/2019/01/18/floating-point-arithmetic-before-ieee-754/",
  abstract =     "In a comment following my post about half-precision
                 arithmetic, ``Raj C'' asked how the parameters for IEEE
                 Standard 754 floating point arithmetic were chosen. I
                 replied that I didn't know but would try to find out. I
                 called emeritus U. C. Berkeley Professor W. (Velvel)
                 Kahan, who was the principle architect of 754. Here is
                 what I learned.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Moler:2019:CCV
author: Cleve Moler
title: Cleve's Corner: Variable Format Half Precision Floating Point Arithmetic
pages: 412--417
day: 16
month: jan
monthnumber: 1
year: 2019
bibdate: Sat Jan 19 15:14:03 2019
bibtimestamp: 2019.01.19 15:14:03 ???
acknowledgement: ack-nhfb
howpublished: MathWorks Web site.
rawauthor: Cleve Moler
rawtitle: {Cleve}'s Corner: Variable Format Half Precision Floating Point Arithmetic
URL:
https://blogs.mathworks.com/cleve/2019/01/16/variable-format-half-precision-floating-point-arithmetic/

abstract:
A year and a half ago I wrote a post about ``half precision'' 16-bit floating point arithmetic, Moler on fp16. I followed this with a bug fix, bug in fp16. Both posts were about fp16, defined in IEEE standard 754. This is only one of 15 possible 16-bit formats. In this post I am going to consider all 15.

rawabstract:
A year and a half ago I wrote a post about ``half precision'' 16-bit floating point arithmetic, Moler on fp16. I followed this with a bug fix, bug in fp16. Both posts were about fp16, defined in IEEE standard 754. This is only one of 15 possible 16-bit formats. In this post I am going to consider all 15.

entry:
@Misc{Moler:2019:CCV,
  author =       "Cleve Moler",
  title =        "{Cleve}'s Corner: Variable Format Half Precision
                 Floating Point Arithmetic",
  howpublished = "MathWorks Web site.",
  day =          "16",
  month =        jan,
  year =         "2019",
  bibdate =      "Sat Jan 19 15:14:03 2019",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/m/moler-cleve-b.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://blogs.mathworks.com/cleve/2019/01/16/variable-format-half-precision-floating-point-arithmetic/",
  abstract =     "A year and a half ago I wrote a post about ``half
                 precision'' 16-bit floating point arithmetic, Moler on
                 fp16. I followed this with a bug fix, bug in fp16. Both
                 posts were about fp16, defined in IEEE standard 754.
                 This is only one of 15 possible 16-bit formats. In this
                 post I am going to consider all 15.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Moriai:2019:PPD
author: Shiho Moriai
title: Privacy-Preserving Deep Learning via Additively Homomorphic Encryption
crossref: Takagi:2019:ISC
pages: 198--198
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00047
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Shiho Moriai
rawtitle: Privacy-Preserving Deep Learning via Additively Homomorphic Encryption
abstract:
We aim at creating a society where we can resolve various social challenges by incorporating the innovations of the fourth industrial revolution (e.g. IoT, big data, AI, robot, and the sharing economy) into every industry and social life. By doing so the society of the future will be one in which new values and services are created continuously, making people's lives more conformable and sustainable. This is Society 5.0, a super-smart society. Security and privacy are key issues to be addressed to realize Society 5.0. Privacy-preserving data analytics will play an important role. In this talk we show our recent works on privacy-preserving data analytics such as privacy-preserving logistic regression and privacy-preserving deep learning. Finally, we show our ongoing research project under JST CREST AI . In this project we are developing privacy-preserving financial data analytics systems that can detect fraud with high security and accuracy. To validate the systems, we will perform demonstration tests with several financial institutions and solve the problems necessary for their implementation in the real world.

keywords:
additively homomorphic encryption; ARITH-26; Big Data; data analysis; Data analysis; data privacy; Deep learning; Digital arithmetic; Encryption; financial data processing; financial institutions; fourth industrial revolution; fraud; Information and communication technology; IoT; JST CREST AI; neural nets; privacy issues; privacy-preserving deep learning; privacy-preserving financial data analytics systems; privacy-preserving logistic regression; regression analysis; social challenges; social life; social sciences computing; Society 5.0; super-smart society

rawabstract:
We aim at creating a society where we can resolve various social challenges by incorporating the innovations of the fourth industrial revolution (e.g. IoT, big data, AI, robot, and the sharing economy) into every industry and social life. By doing so the society of the future will be one in which new values and services are created continuously, making people's lives more conformable and sustainable. This is Society 5.0, a super-smart society. Security and privacy are key issues to be addressed to realize Society 5.0. Privacy-preserving data analytics will play an important role. In this talk we show our recent works on privacy-preserving data analytics such as privacy-preserving logistic regression and privacy-preserving deep learning. Finally, we show our ongoing research project under JST CREST AI . In this project we are developing privacy-preserving financial data analytics systems that can detect fraud with high security and accuracy. To validate the systems, we will perform demonstration tests with several financial institutions and solve the problems necessary for their implementation in the real world.

entry:
@InProceedings{Moriai:2019:PPD,
  author =       "Shiho Moriai",
  title =        "Privacy-Preserving Deep Learning via Additively
                 Homomorphic Encryption",
  crossref =     "Takagi:2019:ISC",
  pages =        "198--198",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00047",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We aim at creating a society where we can resolve
                 various social challenges by incorporating the
                 innovations of the fourth industrial revolution (e.g.
                 IoT, big data, AI, robot, and the sharing economy) into
                 every industry and social life. By doing so the society
                 of the future will be one in which new values and
                 services are created continuously, making people's
                 lives more conformable and sustainable. This is Society
                 5.0, a super-smart society. Security and privacy are
                 key issues to be addressed to realize Society 5.0.
                 Privacy-preserving data analytics will play an
                 important role. In this talk we show our recent works
                 on privacy-preserving data analytics such as
                 privacy-preserving logistic regression and
                 privacy-preserving deep learning. Finally, we show our
                 ongoing research project under JST CREST AI . In this
                 project we are developing privacy-preserving financial
                 data analytics systems that can detect fraud with high
                 security and accuracy. To validate the systems, we will
                 perform demonstration tests with several financial
                 institutions and solve the problems necessary for their
                 implementation in the real world.",
  acknowledgement = ack-nhfb,
  keywords =     "additively homomorphic encryption; ARITH-26; Big Data;
                 data analysis; Data analysis; data privacy; Deep
                 learning; Digital arithmetic; Encryption; financial
                 data processing; financial institutions; fourth
                 industrial revolution; fraud; Information and
                 communication technology; IoT; JST CREST AI; neural
                 nets; privacy issues; privacy-preserving deep learning;
                 privacy-preserving financial data analytics systems;
                 privacy-preserving logistic regression; regression
                 analysis; social challenges; social life; social
                 sciences computing; Society 5.0; super-smart society",
}


bibtype: article
filename: fparith.bib
label: Munoz-Coreas:2019:QCD
author: E. Munoz-Coreas and H. Thapliyal
title: Quantum Circuit Design of a $T$-count Optimized Integer Multiplier
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 5
pages: 729--739
month: may
monthnumber: 5
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2882774
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: E. Mu{\~n}oz-Coreas and H. Thapliyal
rawtitle: Quantum Circuit Design of a {$T$}-count Optimized Integer Multiplier
keywords:
adders; Adders; Clifford+T gates; conditional adder; fault tolerance; Fault tolerance; fault tolerant implementations; Fault tolerant systems; integer multiplication; logic design; Logic gates; quantum arithmetic; quantum circuit design; quantum circuits; Quantum computing; quantum conditional adder circuit; quantum gates; quantum hardware resources; quantum multiplier design; qubits; Registers; reliable quantum circuits; scalable quantum circuits; T-count optimized quantum circuit; T-count savings; Toffoli gate array

entry:
@Article{Munoz-Coreas:2019:QCD,
  author =       "E. Mu{\~n}oz-Coreas and H. Thapliyal",
  title =        "Quantum Circuit Design of a {$T$}-count Optimized
                 Integer Multiplier",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "5",
  pages =        "729--739",
  month =        may,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2882774",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "adders; Adders; Clifford+T gates; conditional adder;
                 fault tolerance; Fault tolerance; fault tolerant
                 implementations; Fault tolerant systems; integer
                 multiplication; logic design; Logic gates; quantum
                 arithmetic; quantum circuit design; quantum circuits;
                 Quantum computing; quantum conditional adder circuit;
                 quantum gates; quantum hardware resources; quantum
                 multiplier design; qubits; Registers; reliable quantum
                 circuits; scalable quantum circuits; T-count optimized
                 quantum circuit; T-count savings; Toffoli gate array",
}


bibtype: article
filename: fparith.bib
label: Nannarelli:2019:TFP
author: A. Nannarelli
title: Tunable Floating-Point Adder
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 10
pages: 1553--1560
month: oct
monthnumber: 10
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2019.2906907
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Sep 12 13:33:25 2019
bibtimestamp: 2019.09.12 13:33:25 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Nannarelli
rawtitle: Tunable Floating-Point Adder
keywords:
Adders; addition; Computer architecture; energy efficiency; Floating-point; Google; Hardware; IEEE rounding; Indexes; Standards; Tuning

remark:
From the abstract: ``TFP is a variable precision format in which a given precision can be chosen for a single operation by selecting a specific number of bits for significand and exponent in the floating-point representation. By tuning the precision of an algorithm to the minimum precision achieving an acceptable target error, we can make the computation more power efficient.''

entry:
@Article{Nannarelli:2019:TFP,
  author =       "A. Nannarelli",
  title =        "Tunable Floating-Point Adder",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "10",
  pages =        "1553--1560",
  month =        oct,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2906907",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Sep 12 13:33:25 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adders; addition; Computer architecture; energy
                 efficiency; Floating-point; Google; Hardware; IEEE
                 rounding; Indexes; Standards; Tuning",
  remark =       "From the abstract: ``TFP is a variable precision
                 format in which a given precision can be chosen for a
                 single operation by selecting a specific number of bits
                 for significand and exponent in the floating-point
                 representation. By tuning the precision of an algorithm
                 to the minimum precision achieving an acceptable target
                 error, we can make the computation more power
                 efficient.''",
}


bibtype: inproceedings
filename: fparith.bib
label: Pandey:2019:UFP
author: Kumar Sambhav Pandey and Dinesh Kumar B and Neeraj Goel and Hitesh Shrimali
title: An Ultra-Fast Parallel Prefix Adder
crossref: Takagi:2019:ISC
pages: 125--134
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00034
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Kumar Sambhav Pandey and Dinesh Kumar B and Neeraj Goel and Hitesh Shrimali
rawtitle: An Ultra-Fast Parallel Prefix Adder
abstract:
Parallel Prefix adders are arguably the most commonly used arithmetic units. They have been extensively investigated at architecture level, register transfer level (RTL), gate level, circuit level as well as layout level giving rise to a plethora of mathematical formulations, topologies and implementations. This paper contributes significantly to the understanding of these parallel prefix adders in a couple of ways. Firstly, it attempts to describe various such parallel prefix adders in elegant and consistent formulations. Secondly, a new family of parallel prefix adders is proposed at architecture level. The estimates of the area-throughput characteristics for an instance of this family are also presented. While the speeds achieved by this instance match those achieved by the state of the art adders, their area characteristics exhibit upto 26% improvement.

keywords:
adder recurrence relations; Adders; adders; architecture level; area-throughput characteristics; ARITH-26; arithmetic units; Computer architecture; Digital arithmetic; digital arithmetic; integrated circuit layout; integrated logic circuits; logic design; Logic gates; Microprocessors; Parallel prefix adders; Terminology; Topology; ultrafast parallel prefix adder

rawabstract:
Parallel Prefix adders are arguably the most commonly used arithmetic units. They have been extensively investigated at architecture level, register transfer level (RTL), gate level, circuit level as well as layout level giving rise to a plethora of mathematical formulations, topologies and implementations. This paper contributes significantly to the understanding of these parallel prefix adders in a couple of ways. Firstly, it attempts to describe various such parallel prefix adders in elegant and consistent formulations. Secondly, a new family of parallel prefix adders is proposed at architecture level. The estimates of the area-throughput characteristics for an instance of this family are also presented. While the speeds achieved by this instance match those achieved by the state of the art adders, their area characteristics exhibit upto 26\% improvement.

entry:
@InProceedings{Pandey:2019:UFP,
  author =       "Kumar Sambhav Pandey and Dinesh Kumar B and Neeraj
                 Goel and Hitesh Shrimali",
  title =        "An Ultra-Fast Parallel Prefix Adder",
  crossref =     "Takagi:2019:ISC",
  pages =        "125--134",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00034",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Parallel Prefix adders are arguably the most commonly
                 used arithmetic units. They have been extensively
                 investigated at architecture level, register transfer
                 level (RTL), gate level, circuit level as well as
                 layout level giving rise to a plethora of mathematical
                 formulations, topologies and implementations. This
                 paper contributes significantly to the understanding of
                 these parallel prefix adders in a couple of ways.
                 Firstly, it attempts to describe various such parallel
                 prefix adders in elegant and consistent formulations.
                 Secondly, a new family of parallel prefix adders is
                 proposed at architecture level. The estimates of the
                 area-throughput characteristics for an instance of this
                 family are also presented. While the speeds achieved by
                 this instance match those achieved by the state of the
                 art adders, their area characteristics exhibit upto
                 26\% improvement.",
  acknowledgement = ack-nhfb,
  keywords =     "adder recurrence relations; Adders; adders;
                 architecture level; area-throughput characteristics;
                 ARITH-26; arithmetic units; Computer architecture;
                 Digital arithmetic; digital arithmetic; integrated
                 circuit layout; integrated logic circuits; logic
                 design; Logic gates; Microprocessors; Parallel prefix
                 adders; Terminology; Topology; ultrafast parallel
                 prefix adder",
}


bibtype: article
filename: fparith.bib
label: Parhi:2019:CAF
author: Keshab K. Parhi and Yin Liu
title: Computing Arithmetic Functions Using Stochastic Logic by Series Expansion
journal: j-IEEE-TRANS-EMERG-TOP-COMPUT
volume: 7
number: 1
pages: 44--59
month: jan
monthnumber: 1
year: 2019
DOI: https://doi.org/10.1109/TETC.2016.2618750
ISSN: 2168-6750 (print), 2376-4562 (electronic) OR 21686750 (print), 23764562 (electronic)
bibdate: Thu Sep 21 14:02:06 2023
bibtimestamp: 2023.09.21 14:02:06 ???
fjournal: IEEE Transactions on Emerging Topics in Computing
acknowledgement: ack-nhfb
journalURL: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516
rawauthor: Keshab K. Parhi and Yin Liu
rawtitle: Computing Arithmetic Functions Using Stochastic Logic by Series Expansion
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib

abstract:
Stochastic logic implementations of complex arithmetic functions, such as trigonometric, exponential, and sigmoid, are derived based on truncated versions of their Maclaurin series expansions. This paper makes three contributions. First, it is shown that a polynomial can be implemented using multiple levels of NAND gates based on Horner's rule, if the coefficients are alternately positive and negative and their magnitudes are monotonically decreasing. Truncated Maclaurin series expansions of arithmetic functions are used to generate polynomials which satisfy these constraints. The input and output in these functions are represented by unipolar representation. Functions including sine, cosine, tangent hyperbolic, logarithm and exponential can be implemented using this method. Second, for a polynomial that does not satisfy these constraints, it still can be implemented based on Horner's rule if each factor of the polynomial satisfies these constraints. It is shown that functions such as $ sin pi x / pi $, $ e^-a x $, $ tanh a x $ and $ sigmoid (a x^3) $ (for values of $ a > 1$) can be implemented using stochastic logic using factorization in combination with Horner's rule. Third, format conversion is proposed for arithmetic functions with input and output represented in different formats, such as $ cos pi x$ given $ x in [0, 1]$ and $ sigmoid (x)$ given $ x in [ - 1, 1]$. Polynomials are transformed to equivalent forms that naturally exploit format conversions. The proposed stochastic logic circuits outperform the well-known Bernstein polynomial based and finite-state-machine (FSM) based implementations. Furthermore, the hardware complexity and the critical path of the proposed implementations are less than the well-known Bernstein polynomial based and FSM based implementations for most cases

rawabstract:
Stochastic logic implementations of complex arithmetic functions, such as trigonometric, exponential, and sigmoid, are derived based on truncated versions of their Maclaurin series expansions. This paper makes three contributions. First, it is shown that a polynomial can be implemented using multiple levels of NAND gates based on Horner's rule, if the coefficients are alternately positive and negative and their magnitudes are monotonically decreasing. Truncated Maclaurin series expansions of arithmetic functions are used to generate polynomials which satisfy these constraints. The input and output in these functions are represented by unipolar representation. Functions including sine, cosine, tangent hyperbolic, logarithm and exponential can be implemented using this method. Second, for a polynomial that does not satisfy these constraints, it still can be implemented based on Horner's rule if each factor of the polynomial satisfies these constraints. It is shown that functions such as $ \sin \pi x / \pi $, $ e^{-a x} $, $ \tanh a x $ and $ \sigmoid (a x^3) $ (for values of $ a > 1$) can be implemented using stochastic logic using factorization in combination with Horner's rule. Third, format conversion is proposed for arithmetic functions with input and output represented in different formats, such as $ \cos \pi x$ given $ x \in [0, 1]$ and $ \sigmoid (x)$ given $ x \in [ - 1, 1]$. Polynomials are transformed to equivalent forms that naturally exploit format conversions. The proposed stochastic logic circuits outperform the well-known Bernstein polynomial based and finite-state-machine (FSM) based implementations. Furthermore, the hardware complexity and the critical path of the proposed implementations are less than the well-known Bernstein polynomial based and FSM based implementations for most cases

entry:
@Article{Parhi:2019:CAF,
  author =       "Keshab K. Parhi and Yin Liu",
  title =        "Computing Arithmetic Functions Using Stochastic Logic
                 by Series Expansion",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "7",
  number =       "1",
  pages =        "44--59",
  month =        jan # "\slash " # mar,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/TETC.2016.2618750",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Thu Sep 21 14:02:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib",
  abstract =     "Stochastic logic implementations of complex arithmetic
                 functions, such as trigonometric, exponential, and
                 sigmoid, are derived based on truncated versions of
                 their Maclaurin series expansions. This paper makes
                 three contributions. First, it is shown that a
                 polynomial can be implemented using multiple levels of
                 NAND gates based on Horner's rule, if the coefficients
                 are alternately positive and negative and their
                 magnitudes are monotonically decreasing. Truncated
                 Maclaurin series expansions of arithmetic functions are
                 used to generate polynomials which satisfy these
                 constraints. The input and output in these functions
                 are represented by unipolar representation. Functions
                 including sine, cosine, tangent hyperbolic, logarithm
                 and exponential can be implemented using this method.
                 Second, for a polynomial that does not satisfy these
                 constraints, it still can be implemented based on
                 Horner's rule if each factor of the polynomial
                 satisfies these constraints. It is shown that functions
                 such as $ \sin \pi x / \pi $, $ e^{-a x} $, $ \tanh a x
                 $ and $ \sigmoid (a x^3) $ (for values of $ a > 1$) can
                 be implemented using stochastic logic using
                 factorization in combination with Horner's rule. Third,
                 format conversion is proposed for arithmetic functions
                 with input and output represented in different formats,
                 such as $ \cos \pi x$ given $ x \in [0, 1]$ and $
                 \sigmoid (x)$ given $ x \in [ - 1, 1]$. Polynomials are
                 transformed to equivalent forms that naturally exploit
                 format conversions. The proposed stochastic logic
                 circuits outperform the well-known Bernstein polynomial
                 based and finite-state-machine (FSM) based
                 implementations. Furthermore, the hardware complexity
                 and the critical path of the proposed implementations
                 are less than the well-known Bernstein polynomial based
                 and FSM based implementations for most cases",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}


bibtype: inproceedings
filename: fparith.bib
label: Parry:2019:PSO
author: Katherine Parry
title: A Perspective into Squarer Optimization
crossref: Takagi:2019:ISC
pages: 124--124
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00033
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Katherine Parry
rawtitle: A Perspective into Squarer Optimization
abstract:
Artificial Intelligence applications do millions of square calculations, such as within Gradient Descent or Principle Component Analysis (PCA). Any time measured or observed data is analyzed; the error, residual, or a comparison against a norm, it is evaluated using a square operation. Squarers are special purpose multipliers that can be employed when the operands are identical. Most calculations use slower multipliers, even though squarers calculate faster, use less power, and occupy less area. Multiplication is composed of a series of partial products that are accumulated to result in the multiplied product. Multiplier and squarer propagation delay is assessed using the number of partial products, or more their addition. The calculation of partial products can occur in parallel, thus does not significantly tax the propagation delay, but carries from their addition create computational dependencies. A standard 8-bit multiplier requires 56 partial product additions and previous work has reduced a squarer to 22 partial products sums. This paper reviews the previous technology and illustrates further Boolean optimizations that minimize the number of additions to 15 partial products.

keywords:
8-bit multiplier; ARITH-26; Artificial intelligence; artificial intelligence applications; Boolean functions; Boolean optimizations; Digital arithmetic; digital arithmetic; gradient descent; Measurement uncertainty; multiplied product; multiplying circuits; optimisation; Optimization; partial product additions; partial products sums; Principal component analysis; principle component analysis; Propagation delay; special purpose multipliers; square calculations; square operation; squarer optimization; squarer propagation delay; Urban areas

rawabstract:
Artificial Intelligence applications do millions of square calculations, such as within Gradient Descent or Principle Component Analysis (PCA). Any time measured or observed data is analyzed; the error, residual, or a comparison against a norm, it is evaluated using a square operation. Squarers are special purpose multipliers that can be employed when the operands are identical. Most calculations use slower multipliers, even though squarers calculate faster, use less power, and occupy less area. Multiplication is composed of a series of partial products that are accumulated to result in the multiplied product. Multiplier and squarer propagation delay is assessed using the number of partial products, or more their addition. The calculation of partial products can occur in parallel, thus does not significantly tax the propagation delay, but carries from their addition create computational dependencies. A standard 8-bit multiplier requires 56 partial product additions and previous work has reduced a squarer to 22 partial products sums. This paper reviews the previous technology and illustrates further Boolean optimizations that minimize the number of additions to 15 partial products.

entry:
@InProceedings{Parry:2019:PSO,
  author =       "Katherine Parry",
  title =        "A Perspective into Squarer Optimization",
  crossref =     "Takagi:2019:ISC",
  pages =        "124--124",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00033",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Artificial Intelligence applications do millions of
                 square calculations, such as within Gradient Descent or
                 Principle Component Analysis (PCA). Any time measured
                 or observed data is analyzed; the error, residual, or a
                 comparison against a norm, it is evaluated using a
                 square operation. Squarers are special purpose
                 multipliers that can be employed when the operands are
                 identical. Most calculations use slower multipliers,
                 even though squarers calculate faster, use less power,
                 and occupy less area. Multiplication is composed of a
                 series of partial products that are accumulated to
                 result in the multiplied product. Multiplier and
                 squarer propagation delay is assessed using the number
                 of partial products, or more their addition. The
                 calculation of partial products can occur in parallel,
                 thus does not significantly tax the propagation delay,
                 but carries from their addition create computational
                 dependencies. A standard 8-bit multiplier requires 56
                 partial product additions and previous work has reduced
                 a squarer to 22 partial products sums. This paper
                 reviews the previous technology and illustrates further
                 Boolean optimizations that minimize the number of
                 additions to 15 partial products.",
  acknowledgement = ack-nhfb,
  keywords =     "8-bit multiplier; ARITH-26; Artificial intelligence;
                 artificial intelligence applications; Boolean
                 functions; Boolean optimizations; Digital arithmetic;
                 digital arithmetic; gradient descent; Measurement
                 uncertainty; multiplied product; multiplying circuits;
                 optimisation; Optimization; partial product additions;
                 partial products sums; Principal component analysis;
                 principle component analysis; Propagation delay;
                 special purpose multipliers; square calculations;
                 square operation; squarer optimization; squarer
                 propagation delay; Urban areas",
}


bibtype: inproceedings
filename: fparith.bib
label: Pasca:2019:HDP
author: Bogdan Pasca
title: Hybrid Dot-Product Design for FP-Enabled FPGAs
crossref: Takagi:2019:ISC
pages: 194--196
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00045
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Bogdan Pasca
rawtitle: Hybrid Dot-Product Design for {FP}-Enabled {FPGAs}
abstract:
FPGAs are becoming interesting solutions for neural network training acceleration. Efficient implementation of dot-products, as part of matrix-matrix multiply engines, plays a key role towards this. The now de facto standard involves the matrix multiplication on bfloat16 inputs, with all reductions be performed in single-precision arithmetic. We present here a generic hybrid dot-product implementation that: (1) has a user-defined accuracy knob and (2) targets a user-defined logic/DSP ratio. Since our architecture is very specialized to a given target device, we discuss the challenges in generating this architecture automatically.

keywords:
Adders; ARITH-26; arithmetic; Bandwidth; bfloat16; dot product; dot-products; Field programmable gate arrays; field programmable gate arrays; floating point; floating point arithmetic; FP-enabled FPGA; FPGA; generator; hybrid; hybrid dot-product design; hybrid dot-product implementation; Lead; logic design; matrix multiplication; matrix-matrix multiply engines; multiplying circuits; neural nets; neural network training; Neural networks; single precision; single-precision arithmetic; Tools; Training

rawabstract:
FPGAs are becoming interesting solutions for neural network training acceleration. Efficient implementation of dot-products, as part of matrix-matrix multiply engines, plays a key role towards this. The now de facto standard involves the matrix multiplication on bfloat16 inputs, with all reductions be performed in single-precision arithmetic. We present here a generic hybrid dot-product implementation that: (1) has a user-defined accuracy knob and (2) targets a user-defined logic/DSP ratio. Since our architecture is very specialized to a given target device, we discuss the challenges in generating this architecture automatically.

entry:
@InProceedings{Pasca:2019:HDP,
  author =       "Bogdan Pasca",
  title =        "Hybrid Dot-Product Design for {FP}-Enabled {FPGAs}",
  crossref =     "Takagi:2019:ISC",
  pages =        "194--196",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00045",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "FPGAs are becoming interesting solutions for neural
                 network training acceleration. Efficient implementation
                 of dot-products, as part of matrix-matrix multiply
                 engines, plays a key role towards this. The now de
                 facto standard involves the matrix multiplication on
                 bfloat16 inputs, with all reductions be performed in
                 single-precision arithmetic. We present here a generic
                 hybrid dot-product implementation that: (1) has a
                 user-defined accuracy knob and (2) targets a
                 user-defined logic/DSP ratio. Since our architecture is
                 very specialized to a given target device, we discuss
                 the challenges in generating this architecture
                 automatically.",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; ARITH-26; arithmetic; Bandwidth; bfloat16; dot
                 product; dot-products; Field programmable gate arrays;
                 field programmable gate arrays; floating point;
                 floating point arithmetic; FP-enabled FPGA; FPGA;
                 generator; hybrid; hybrid dot-product design; hybrid
                 dot-product implementation; Lead; logic design; matrix
                 multiplication; matrix-matrix multiply engines;
                 multiplying circuits; neural nets; neural network
                 training; Neural networks; single precision;
                 single-precision arithmetic; Tools; Training",
}


bibtype: article
filename: fparith.bib
label: Pranesh:2019:LPF
author: Srikara Pranesh
title: Low Precision Floating-Point Formats: The Wild West of Computer Arithmetic
journal: j-SIAM-NEWS
volume: 52
number: 9
pages: 12--12
month: nov
monthnumber: 11
year: 2019
ISSN: 0036-1437 OR 00361437
bibdate: Mon Nov 04 14:49:07 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.11.04 14:49:07 ???
fjournal: SIAM News
acknowledgement: ack-nhfb
journalURL: http://www.siam.org/news/
rawauthor: Srikara Pranesh
rawtitle: Low Precision Floating-Point Formats: The {Wild West} of Computer Arithmetic
URL:
https://sinews.siam.org/Details-Page/low-precision-floating-point-formats-the-wild-west-of-computer-arithmetic

entry:
@Article{Pranesh:2019:LPF,
  author =       "Srikara Pranesh",
  title =        "Low Precision Floating-Point Formats: The {Wild West}
                 of Computer Arithmetic",
  journal =      j-SIAM-NEWS,
  volume =       "52",
  number =       "9",
  pages =        "12--12",
  month =        nov,
  year =         "2019",
  DOI =          "",
  ISSN =         "0036-1437",
  bibdate =      "Mon Nov 04 14:49:07 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://sinews.siam.org/Details-Page/low-precision-floating-point-formats-the-wild-west-of-computer-arithmetic",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM News",
  journal-URL =  "http://www.siam.org/news/",
}


bibtype: article
filename: fparith.bib
label: Reyhani-Masoleh:2019:NMI
author: A. Reyhani-Masoleh and H. El-Razouk and A. Monfared
title: New Multiplicative Inverse Architectures Using Gaussian Normal Basis
journal: j-IEEE-TRANS-COMPUT
volume: 68
number: 7
pages: 991--1006
month: jul
monthnumber: 7
year: 2019
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2018.2859941
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Jul 11 09:46:20 2019
bibtimestamp: 2019.07.11 09:46:20 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: A. Reyhani-Masoleh and H. El-Razouk and A. Monfared
rawtitle: New Multiplicative Inverse Architectures Using {Gaussian} Normal Basis
keywords:
application specific integrated circuits; arithmetic operations; binary fields; classic inversion scheme; classic-based addition chains; classical-interleaved architecture; classical-interleaved inverter; CMOS integrated circuits; Computer architecture; cryptography; Digit-level multiplier; digital arithmetic; field inversion; field programmable gate arrays; finite field; FSISM; FSISM processor; fully-serial-in square-multiply processor; Galois fields; Gaussian normal basis; Gaussian processes; hybrid-double multiplication; input registers; inversion architecture; inversion architectures; Inverters; invertors; Itoh-Tsujii algorithm; latency; Logic gates; multiplication cycle; multiplicative inverse architectures; multiplying circuits; NIST; Propagation delay; size 65.0 nm; ternary Itoh-Tsujii algorithm

entry:
@Article{Reyhani-Masoleh:2019:NMI,
  author =       "A. Reyhani-Masoleh and H. El-Razouk and A. Monfared",
  title =        "New Multiplicative Inverse Architectures Using
                 {Gaussian} Normal Basis",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "7",
  pages =        "991--1006",
  month =        jul,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2018.2859941",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Jul 11 09:46:20 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "application specific integrated circuits; arithmetic
                 operations; binary fields; classic inversion scheme;
                 classic-based addition chains; classical-interleaved
                 architecture; classical-interleaved inverter; CMOS
                 integrated circuits; Computer architecture;
                 cryptography; Digit-level multiplier; digital
                 arithmetic; field inversion; field programmable gate
                 arrays; finite field; FSISM; FSISM processor;
                 fully-serial-in square-multiply processor; Galois
                 fields; Gaussian normal basis; Gaussian processes;
                 hybrid-double multiplication; input registers;
                 inversion architecture; inversion architectures;
                 Inverters; invertors; Itoh-Tsujii algorithm; latency;
                 Logic gates; multiplication cycle; multiplicative
                 inverse architectures; multiplying circuits; NIST;
                 Propagation delay; size 65.0 nm; ternary Itoh-Tsujii
                 algorithm",
}


bibtype: inproceedings
filename: fparith.bib
label: Rohloff:2019:CAR
author: Kurt Rohloff
crossref: Takagi:2019:ISC
pages: 197--197
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00046
bibdate: Fri Jan 31 08:18:07 2020
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Kurt Rohloff
title:
Computer Arithmetic Research to Accelerate Privacy-Protecting Encrypted Computing Such as Homomorphic Encryption

abstract:
One of the first major breakthroughs of computer science in the 21st century has been the discovery and practical demonstration of encrypted computing technologies such as Fully Homomorphic Encryption (FHE). Encrypted computing technologies allow sensitive data to be encrypted such that arbitrary programs can be securely run over the encrypted data where the output, when decrypted, is equivalent to the result of running the original algorithm on the unencrypted data. In this talk we focus on the use of and potential for computer arithmetic research to enable more practical encrypted computing, such as to accelerate advanced encryption implementations on custom hardware. These technologies are ground-breaking in their ability for privacy-preserving data science on sensitive data sets with minimal costs in terms of engineering effort, power, compute resources, etc. ldots . We discuss theory, design, algorithmic, hardware, software engineering and systems research that is enabling applications of encrypted computing in regulated data industries, such as in medical and financial domains. We use our work using accelerating the PALISADE open-source homomorphic encryption software library for practical applications in case studies.

keywords:
Acceleration; advanced encryption implementations; ARITH-26; computer arithmetic research; computer science; Computer science; Computers; cryptography; data privacy; Digital arithmetic; encrypted computing technologies; encrypted data; Encryption; fully homomorphic encryption; Hardware; PALISADE open-source homomorphic encryption software library; privacy-preserving data science; privacy-protecting encrypted computing; public domain software; regulated data industries; sensitive data sets; software engineering; software libraries; unencrypted data

rawabstract:
One of the first major breakthroughs of computer science in the 21st century has been the discovery and practical demonstration of encrypted computing technologies such as Fully Homomorphic Encryption (FHE). Encrypted computing technologies allow sensitive data to be encrypted such that arbitrary programs can be securely run over the encrypted data where the output, when decrypted, is equivalent to the result of running the original algorithm on the unencrypted data. In this talk we focus on the use of and potential for computer arithmetic research to enable more practical encrypted computing, such as to accelerate advanced encryption implementations on custom hardware. These technologies are ground-breaking in their ability for privacy-preserving data science on sensitive data sets with minimal costs in terms of engineering effort, power, compute resources, etc. \ldots{}. We discuss theory, design, algorithmic, hardware, software engineering and systems research that is enabling applications of encrypted computing in regulated data industries, such as in medical and financial domains. We use our work using accelerating the PALISADE open-source homomorphic encryption software library for practical applications in case studies.

rawtitle:
Computer Arithmetic Research to Accelerate Privacy-Protecting Encrypted Computing Such as Homomorphic Encryption

entry:
@InProceedings{Rohloff:2019:CAR,
  author =       "Kurt Rohloff",
  title =        "Computer Arithmetic Research to Accelerate
                 Privacy-Protecting Encrypted Computing Such as
                 Homomorphic Encryption",
  crossref =     "Takagi:2019:ISC",
  pages =        "197--197",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00046",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "One of the first major breakthroughs of computer
                 science in the 21st century has been the discovery and
                 practical demonstration of encrypted computing
                 technologies such as Fully Homomorphic Encryption
                 (FHE). Encrypted computing technologies allow sensitive
                 data to be encrypted such that arbitrary programs can
                 be securely run over the encrypted data where the
                 output, when decrypted, is equivalent to the result of
                 running the original algorithm on the unencrypted data.
                 In this talk we focus on the use of and potential for
                 computer arithmetic research to enable more practical
                 encrypted computing, such as to accelerate advanced
                 encryption implementations on custom hardware. These
                 technologies are ground-breaking in their ability for
                 privacy-preserving data science on sensitive data sets
                 with minimal costs in terms of engineering effort,
                 power, compute resources, etc. \ldots{}. We discuss
                 theory, design, algorithmic, hardware, software
                 engineering and systems research that is enabling
                 applications of encrypted computing in regulated data
                 industries, such as in medical and financial domains.
                 We use our work using accelerating the PALISADE
                 open-source homomorphic encryption software library for
                 practical applications in case studies.",
  acknowledgement = ack-nhfb,
  keywords =     "Acceleration; advanced encryption implementations;
                 ARITH-26; computer arithmetic research; computer
                 science; Computer science; Computers; cryptography;
                 data privacy; Digital arithmetic; encrypted computing
                 technologies; encrypted data; Encryption; fully
                 homomorphic encryption; Hardware; PALISADE open-source
                 homomorphic encryption software library;
                 privacy-preserving data science; privacy-protecting
                 encrypted computing; public domain software; regulated
                 data industries; sensitive data sets; software
                 engineering; software libraries; unencrypted data",
}


bibtype: article
filename: fparith.bib
label: Roughan:2019:PSS
author: Matthew Roughan
title: Practically surreal: Surreal arithmetic in Julia
journal: j-SOFTWAREX
volume: 9
pages: 293--298
month: jan
monthnumber: 1
year: 2019
ISSN: 2352-7110 OR 23527110
ISSNL: 2352-7110 OR 23527110
bibdate: Mon Oct 14 09:45:43 MDT 2019
bibtimestamp: 2019.10.14 09:45:43 MDT
URL: http://www.sciencedirect.com/science/article/pii/S2352711018302152
fjournal: SoftwareX
keywords: Conway's surreal numbers
acknowledgement: ack-nhfb
journalURL: https://www.sciencedirect.com/journal/softwarex/issues
rawauthor: Matthew Roughan
rawtitle: Practically surreal: {Surreal} arithmetic in {Julia}
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/softwarex.bib

entry:
@Article{Roughan:2019:PSS,
  author =       "Matthew Roughan",
  title =        "Practically surreal: {Surreal} arithmetic in {Julia}",
  journal =      j-SOFTWAREX,
  volume =       "9",
  number =       "??",
  pages =        "293--298",
  month =        jan # "\slash " # jun,
  year =         "2019",
  CODEN =        "????",
  ISSN =         "2352-7110",
  ISSN-L =       "2352-7110",
  bibdate =      "Mon Oct 14 09:45:43 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/softwarex.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S2352711018302152",
  acknowledgement = ack-nhfb,
  fjournal =     "SoftwareX",
  journal-URL =  "https://www.sciencedirect.com/journal/softwarex/issues",
  keywords =     "Conway's surreal numbers",
}


bibtype: inproceedings
filename: fparith.bib
label: Rump:2019:EBC
author: Siegfried M. Rump
title: Error Bounds for Computer Arithmetics
crossref: Takagi:2019:ISC
pages: 1--14
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00011
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Siegfried M. Rump
rawtitle: Error Bounds for Computer Arithmetics
abstract:
This note summarizes recent progress in error bounds for compound operations performed in some computer arithmetic. Given a general set of real numbers together with some operations satisfying the first standard model, we identify three types A, B, and C of weak sufficient assumptions implying new results and sharper error estimates. Those include linearized error estimates in the number of operations, faithfully rounded and reproducible results. All types of assumptions are satisfied for an IEEE-754 p-digit base- floating-point arithmetic.

keywords:
ARITH-26; Compounds; Computational modeling; computer arithmetic; CREST; Digital arithmetic; error analysis; error bounds; floating point arithmetic; IEEE-754 p-digit base- floating-point arithmetic; Japan Science and Technology Agency; Kernel; Standards; Switches; Vegetation

rawabstract:
This note summarizes recent progress in error bounds for compound operations performed in some computer arithmetic. Given a general set of real numbers together with some operations satisfying the first standard model, we identify three types A, B, and C of weak sufficient assumptions implying new results and sharper error estimates. Those include linearized error estimates in the number of operations, faithfully rounded and reproducible results. All types of assumptions are satisfied for an IEEE-754 p-digit base- floating-point arithmetic.

entry:
@InProceedings{Rump:2019:EBC,
  author =       "Siegfried M. Rump",
  title =        "Error Bounds for Computer Arithmetics",
  crossref =     "Takagi:2019:ISC",
  pages =        "1--14",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00011",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This note summarizes recent progress in error bounds
                 for compound operations performed in some computer
                 arithmetic. Given a general set of real numbers
                 together with some operations satisfying the first
                 standard model, we identify three types A, B, and C of
                 weak sufficient assumptions implying new results and
                 sharper error estimates. Those include linearized error
                 estimates in the number of operations, faithfully
                 rounded and reproducible results. All types of
                 assumptions are satisfied for an IEEE-754 p-digit base-
                 floating-point arithmetic.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Compounds; Computational modeling; computer
                 arithmetic; CREST; Digital arithmetic; error analysis;
                 error bounds; floating point arithmetic; IEEE-754
                 p-digit base- floating-point arithmetic; Japan Science
                 and Technology Agency; Kernel; Standards; Switches;
                 Vegetation",
}


bibtype: article
filename: fparith.bib
label: Salamati:2019:MEM
author: Mahmoud Salamati and Rocco Salvia and Eva Darulova and Sadegh Soudjani and Rupak Majumdar
title: Memory-Efficient Mixed-Precision Implementations for Robust Explicit Model Predictive Control
journal: j-TECS
volume: 18
number: 5s
pages: 100:1--100:??
month: oct
monthnumber: 10
year: 2019
DOI: https://doi.org/10.1145/3358223
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Thu Oct 17 18:16:44 MDT 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tecs.bib
bibtimestamp: 2019.10.17 18:16:44 MDT
URL: https://dl.acm.org/ft_gateway.cfm?id=3358223
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
articleno: 100
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J840
rawauthor: Mahmoud Salamati and Rocco Salvia and Eva Darulova and Sadegh Soudjani and Rupak Majumdar
rawtitle: Memory-Efficient Mixed-Precision Implementations for Robust Explicit Model Predictive Control
abstract:
We propose an optimization for space-efficient implementations of explicit model-predictive controllers (MPC) for robust control of linear time-invariant (LTI) systems on embedded platforms. We obtain an explicit-form robust model-predictive controller as a solution to a multi-parametric linear programming problem. The structure of the controller is a polyhedral decomposition of the control domain, with an affine map for each domain. While explicit MPC is suited for embedded devices with low computational power, the memory requirements for such controllers can be high. We provide an optimization algorithm for a mixed-precision implementation of the controller, where the deviation of the implemented controller from the original one is within the robustness margin of the robust control problem. The core of the mixed-precision optimization is an iterative static analysis that co-designs a robust controller and a low-bitwidth approximation that is statically guaranteed to always be within the robustness margin of the original controller. We have implemented our algorithm and show on a set of benchmarks that our optimization can reduce space requirements by up to 20.9% and on average by 12.6% compared to a minimal uniform precision implementation of the original controller.

rawabstract:
We propose an optimization for space-efficient implementations of explicit model-predictive controllers (MPC) for robust control of linear time-invariant (LTI) systems on embedded platforms. We obtain an explicit-form robust model-predictive controller as a solution to a multi-parametric linear programming problem. The structure of the controller is a polyhedral decomposition of the control domain, with an affine map for each domain. While explicit MPC is suited for embedded devices with low computational power, the memory requirements for such controllers can be high. We provide an optimization algorithm for a mixed-precision implementation of the controller, where the deviation of the implemented controller from the original one is within the robustness margin of the robust control problem. The core of the mixed-precision optimization is an iterative static analysis that co-designs a robust controller and a low-bitwidth approximation that is statically guaranteed to always be within the robustness margin of the original controller. We have implemented our algorithm and show on a set of benchmarks that our optimization can reduce space requirements by up to 20.9\% and on average by 12.6\% compared to a minimal uniform precision implementation of the original controller.

entry:
@Article{Salamati:2019:MEM,
  author =       "Mahmoud Salamati and Rocco Salvia and Eva Darulova and
                 Sadegh Soudjani and Rupak Majumdar",
  title =        "Memory-Efficient Mixed-Precision Implementations for
                 Robust Explicit Model Predictive Control",
  journal =      j-TECS,
  volume =       "18",
  number =       "5s",
  pages =        "100:1--100:??",
  month =        oct,
  year =         "2019",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3358223",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Thu Oct 17 18:16:44 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tecs.bib",
  URL =          "https://dl.acm.org/ft_gateway.cfm?id=3358223",
  abstract =     "We propose an optimization for space-efficient
                 implementations of explicit model-predictive
                 controllers (MPC) for robust control of linear
                 time-invariant (LTI) systems on embedded platforms. We
                 obtain an explicit-form robust model-predictive
                 controller as a solution to a multi-parametric linear
                 programming problem. The structure of the controller is
                 a polyhedral decomposition of the control domain, with
                 an affine map for each domain. While explicit MPC is
                 suited for embedded devices with low computational
                 power, the memory requirements for such controllers can
                 be high. We provide an optimization algorithm for a
                 mixed-precision implementation of the controller, where
                 the deviation of the implemented controller from the
                 original one is within the robustness margin of the
                 robust control problem. The core of the mixed-precision
                 optimization is an iterative static analysis that
                 co-designs a robust controller and a low-bitwidth
                 approximation that is statically guaranteed to always
                 be within the robustness margin of the original
                 controller. We have implemented our algorithm and show
                 on a set of benchmarks that our optimization can reduce
                 space requirements by up to 20.9\% and on average by
                 12.6\% compared to a minimal uniform precision
                 implementation of the original controller.",
  acknowledgement = ack-nhfb,
  articleno =    "100",
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J840",
}


bibtype: inproceedings
filename: fparith.bib
label: Sarkar:2019:RAP
author: Souradip Sarkar and Purushotham Murugappa Velayuthan and Manil Dev Gomony
editor: IEEE
booktitle: 2019 22nd Euromicro Conference on Digital System Design (DSD)
title: A Reconfigurable Architecture for Posit Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 82--87
year: 2019
DOI: https://doi.org/10.1109/DSD.2019.00022
bibdate: Fri Dec 15 09:21:55 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.15 09:21:55 ???
acknowledgement: ack-nhfb
rawauthor: Souradip Sarkar and Purushotham Murugappa Velayuthan and Manil Dev Gomony
rawbooktitle: {2019 22nd Euromicro Conference on Digital System Design (DSD)}
raweditor: {IEEE}
rawtitle: A Reconfigurable Architecture for Posit Arithmetic
entry:
@InProceedings{Sarkar:2019:RAP,
  author =       "Souradip Sarkar and Purushotham Murugappa Velayuthan
                 and Manil Dev Gomony",
  editor =       "{IEEE}",
  booktitle =    "{2019 22nd Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "A Reconfigurable Architecture for Posit Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "82--87",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/DSD.2019.00022",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Seo:2019:HTM
author: Jihee Seo and Dae Hyun Kim
title: High-Throughput Multiplier Architectures Enabled by Intra-Unit Fast Forwarding
crossref: Takagi:2019:ISC
pages: 143--150
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00036
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Jihee Seo and Dae Hyun Kim
rawtitle: High-Throughput Multiplier Architectures Enabled by Intra-Unit Fast Forwarding
abstract:
In this paper, we propose a pipelined multiplier architecture that can resolve data dependencies. The proposed architecture generates partial results in the pipeline stages of the multiplier and forwards the partial results back to the pipeline stages through so-called fast-forwarding paths, thereby enabling an execution of dependent multiplications with a minimum delay penalty. We apply the architecture to a normal binary multiplier (NBBE-2) and two redundant binary multipliers (RBBE-4 and CRBBE-4) and compare the execution time, clock period, area, and power consumption of the multipliers. The simulation results show that the proposed architecture achieves up to 30% execution time reduction.

keywords:
ARITH-26; Clocks; Computer architecture; data dependencies; Delays; dependent multiplications; digital arithmetic; execution time reduction; Fast Forwarding; fast-forwarding paths; high-throughput multiplier architectures; intra-unit fast forwarding; minimum delay penalty; Multiplexing; Multiplication; Multiplier; multiplying circuits; normal binary multiplier; pipeline processing; Pipeline processing; pipeline stages; pipelined multiplier architecture; Pipelines; redundant binary multipliers; Throughput

rawabstract:
In this paper, we propose a pipelined multiplier architecture that can resolve data dependencies. The proposed architecture generates partial results in the pipeline stages of the multiplier and forwards the partial results back to the pipeline stages through so-called fast-forwarding paths, thereby enabling an execution of dependent multiplications with a minimum delay penalty. We apply the architecture to a normal binary multiplier (NBBE-2) and two redundant binary multipliers (RBBE-4 and CRBBE-4) and compare the execution time, clock period, area, and power consumption of the multipliers. The simulation results show that the proposed architecture achieves up to 30\% execution time reduction.

entry:
@InProceedings{Seo:2019:HTM,
  author =       "Jihee Seo and Dae Hyun Kim",
  title =        "High-Throughput Multiplier Architectures Enabled by
                 Intra-Unit Fast Forwarding",
  crossref =     "Takagi:2019:ISC",
  pages =        "143--150",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00036",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper, we propose a pipelined multiplier
                 architecture that can resolve data dependencies. The
                 proposed architecture generates partial results in the
                 pipeline stages of the multiplier and forwards the
                 partial results back to the pipeline stages through
                 so-called fast-forwarding paths, thereby enabling an
                 execution of dependent multiplications with a minimum
                 delay penalty. We apply the architecture to a normal
                 binary multiplier (NBBE-2) and two redundant binary
                 multipliers (RBBE-4 and CRBBE-4) and compare the
                 execution time, clock period, area, and power
                 consumption of the multipliers. The simulation results
                 show that the proposed architecture achieves up to 30\%
                 execution time reduction.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Clocks; Computer architecture; data
                 dependencies; Delays; dependent multiplications;
                 digital arithmetic; execution time reduction; Fast
                 Forwarding; fast-forwarding paths; high-throughput
                 multiplier architectures; intra-unit fast forwarding;
                 minimum delay penalty; Multiplexing; Multiplication;
                 Multiplier; multiplying circuits; normal binary
                 multiplier; pipeline processing; Pipeline processing;
                 pipeline stages; pipelined multiplier architecture;
                 Pipelines; redundant binary multipliers; Throughput",
}


bibtype: inproceedings
filename: fparith.bib
label: Serre:2019:DBM
author: Francois Serre and Markus Puschel
title: DSL-Based Modular IP Core Generators: Example FFT and Related Structures
crossref: Takagi:2019:ISC
pages: 190--191
month: jun
monthnumber: 6
year: 2019
DOI: https://doi.org/10.1109/ARITH.2019.00043
bibdate: Fri Jan 31 08:18:07 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 08:18:07 ???
acknowledgement: ack-nhfb
rawauthor: Fran{\c{c}}ois Serre and Markus P{\"u}schel
rawtitle: {DSL}-Based Modular {IP} Core Generators: Example {FFT} and Related Structures
abstract:
We present a hardware generator for signal processing algorithms that consist of a network of small processing elements, including the fast Fourier transform and sorting networks. The generator is implemented in Scala and uses a principled design that leverages modern language features to generate an entire design space of hardware implementations. Examples include the use of embedded domain-specific languages and staging to represent and optimize the designs at different levels of abstraction, and the use of Scala's type system to efficiently encode different degrees of hardware reuse and arithmetic formats.

keywords:
ARITH-26; arithmetic formats; Design automation; design space; digital arithmetic; Domain specific language; DSL; DSL-based modular IP core generators; electronic engineering computing; embedded domain-specific languages; embedded systems; fast Fourier transform; fast Fourier transforms; FFT; Generators; Hardware; hardware generator; Hardware generator; hardware implementations; hardware reuse; microprocessor chips; object-oriented programming; Optimization; processing elements; Random access memory; Scala type system; signal processing; signal processing algorithms; Sorting; sorting; sorting networks; specification languages; Staging; Streaming hardware

rawabstract:
We present a hardware generator for signal processing algorithms that consist of a network of small processing elements, including the fast Fourier transform and sorting networks. The generator is implemented in Scala and uses a principled design that leverages modern language features to generate an entire design space of hardware implementations. Examples include the use of embedded domain-specific languages and staging to represent and optimize the designs at different levels of abstraction, and the use of Scala's type system to efficiently encode different degrees of hardware reuse and arithmetic formats.

entry:
@InProceedings{Serre:2019:DBM,
  author =       "Fran{\c{c}}ois Serre and Markus P{\"u}schel",
  title =        "{DSL}-Based Modular {IP} Core Generators: Example
                 {FFT} and Related Structures",
  crossref =     "Takagi:2019:ISC",
  pages =        "190--191",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00043",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present a hardware generator for signal processing
                 algorithms that consist of a network of small
                 processing elements, including the fast Fourier
                 transform and sorting networks. The generator is
                 implemented in Scala and uses a principled design that
                 leverages modern language features to generate an
                 entire design space of hardware implementations.
                 Examples include the use of embedded domain-specific
                 languages and staging to represent and optimize the
                 designs at different levels of abstraction, and the use
                 of Scala's type system to efficiently encode different
                 degrees of hardware reuse and arithmetic formats.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; arithmetic formats; Design automation;
                 design space; digital arithmetic; Domain specific
                 language; DSL; DSL-based modular IP core generators;
                 electronic engineering computing; embedded
                 domain-specific languages; embedded systems; fast
                 Fourier transform; fast Fourier transforms; FFT;
                 Generators; Hardware; hardware generator; Hardware
                 generator; hardware implementations; hardware reuse;
                 microprocessor chips; object-oriented programming;
                 Optimization; processing elements; Random access
                 memory; Scala type system; signal processing; signal
                 processing algorithms; Sorting; sorting; sorting
                 networks; specification languages; Staging; Streaming
                 hardware",
}


