Entry Bevan:1989:PDD from compj1980.bib

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BibTeX entry

@Article{Bevan:1989:PDD,
  author =       "D. I. Bevan and G. L. Burn and R. J. Karia and J. D.
                 Robson",
  title =        "Principles for the design of a distributed memory
                 architecture for parallel graph reduction",
  journal =      j-COMP-J,
  volume =       "32",
  number =       "5",
  pages =        "461--469",
  month =        oct,
  year =         "1989",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/32.5.461",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Tue Dec 4 14:48:27 MST 2012",
  bibsource =    "http://comjnl.oxfordjournals.org/content/32/5.toc;
                 http://www.math.utah.edu/pub/tex/bib/compj1980.bib;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_05/;
                 Misc/Functional.bib",
  URL =          "http://comjnl.oxfordjournals.org/content/32/5/461.full.pdf+html;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_05/tiff/461.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_05/tiff/462.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_05/tiff/463.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_05/tiff/464.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_05/tiff/465.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_05/tiff/466.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_05/tiff/467.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_05/tiff/468.tif;
                 http://www3.oup.co.uk/computer_journal/hdb/Volume_32/Issue_05/tiff/469.tif",
  abstract =     "Many models for the parallel reduction of lazy
                 functional languages have been proposed in the
                 literature. The one we have chosen to implement is
                 based on evaluation transformers. An evaluation
                 transformer says how much evaluation can be done to an
                 argument expression in a function application, given
                 the amount of evaluation that can be done to the
                 application. Rather than just selecting a distributed
                 memory architecture and trying to support parallel
                 graph reduction, we investigate the implication of a
                 minimally specified distributed memory architecture for
                 parallel graph reduction. The results of the
                 investigation are incorporated into an abstract machine
                 which is able to support the communication and
                 synchronisation needs of the parallel reduction model
                 on a distributed memory architecture. Certain flags are
                 needed on the nodes in the program graph in order to
                 support the model. These are motivated and described.",
  acknowledgement = ack-nhfb,
  affiliation =  "GEC Hirst Res. Centre, Wembley, UK",
  classcodes =   "C5220 (Computer architecture); C6110 (Systems analysis
                 and programming)",
  classification = "C5220 (Computer architecture); C6110 (Systems
                 analysis and programming)",
  corpsource =   "GEC Hirst Res. Centre, Wembley, UK",
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
  keywords =     "abstract machine; Abstract machine; architectures;
                 distributed memory architecture; evaluation; Evaluation
                 transformers; functional combinators supercombinators;
                 functional programming; lazy functional languages; Lazy
                 functional languages; memory architecture; parallel;
                 parallel graph reduction; Parallel graph reduction;
                 parallel reduction; Parallel reduction; transformers",
  thesaurus =    "Functional programming; Memory architecture; Parallel
                 architectures",
  treatment =    "P Practical",
}

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