%%% -*-BibTeX-*-
%%% ====================================================================
%%% BibTeX-file{
%%%     author          = "Nelson H. F. Beebe",
%%%     version         = "1.18",
%%%     date            = "18 March 2014",
%%%     time            = "06:30:43 MST",
%%%     filename        = "microchip.bib",
%%%                        University of Utah
%%%                        Department of Mathematics, 110 LCB
%%%                        155 S 1400 E RM 233
%%%                        Salt Lake City, UT 84112-0090
%%%                        USA",
%%%     telephone       = "+1 801 581 5254",
%%%     FAX             = "+1 801 581 4148",
%%%     URL             = "http://www.math.utah.edu/~beebe",
%%%     checksum        = "29595 6456 26334 276817",
%%%     email           = "beebe at math.utah.edu, beebe at acm.org,
%%%                        beebe at computer.org (Internet)",
%%%     codetable       = "ISO/ASCII",
%%%     keywords        = "bibliography; BibTeX; microprocessors",
%%%     license         = "public domain",
%%%     supported       = "yes",
%%%     docstring       = "This is a selected bibliography of
%%%                        publications about current microprocessors
%%%                        possibly suitable for desktop and cluster
%%%                        computing.  Preference is given to book
%%%                        references, rather than research articles,
%%%                        unless the architecture is so new that book
%%%                        coverage is limited or unavailable.
%%%
%%%                        At version 1.18, the year coverage looked
%%%                        like this:
%%%
%%%                             1985 (   2)    1992 (  19)    1999 (  22)
%%%                             1986 (   0)    1993 (   8)    2000 (  36)
%%%                             1987 (   3)    1994 (  30)    2001 (   5)
%%%                             1988 (   9)    1995 (  17)    2002 (   2)
%%%                             1989 (  13)    1996 (  18)    2003 (   2)
%%%                             1990 (  24)    1997 (  24)
%%%                             1991 (  16)    1998 (  14)
%%%
%%%                             Article:         77
%%%                             Book:           128
%%%                             InProceedings:    7
%%%                             Manual:          12
%%%                             MastersThesis:    1
%%%                             Misc:             6
%%%                             Proceedings:     16
%%%                             TechReport:      17
%%%
%%%                             Total entries:  264
%%%
%%%                        The checksum field above contains a CRC-16
%%%                        checksum as the first value, followed by the
%%%                        equivalent of the standard UNIX wc (word
%%%                        count) utility output of lines, words, and
%%%                        characters.  This is produced by Robert
%%%                        Solovay's checksum utility.",
%%%  }
%%% ====================================================================

@Preamble{"\input bibnames.sty "
 # "\input path.sty "
 # "\hyphenation{
                }"
}

%%% ====================================================================
%%% Acknowledgement abbreviations:

@String{ack-nhfb = "Nelson H. F. Beebe,
                    University of Utah,
                    Department of Mathematics, 110 LCB,
                    155 S 1400 E RM 233,
                    Salt Lake City, UT 84112-0090, USA,
                    Tel: +1 801 581 5254,
                    FAX: +1 801 581 4148,
                    e-mail: \path|beebe@math.utah.edu|,
                            \path|beebe@acm.org|,
                            \path|beebe@computer.org| (Internet),
                    URL: \path|http://www.math.utah.edu/~beebe/|"}

%%% ====================================================================
%%% Journal abbreviations:

@String{j-BYTE                  = "Byte Magazine"}

@String{j-CACM                  = "Communications of the ACM"}

@String{j-COMP-ARCH-NEWS        = "ACM SIGARCH Computer Architecture News"}

@String{j-COMPUTER              = "Computer"}

@String{j-DDJ                   = "Dr. Dobb's Journal of Software Tools"}

@String{j-HEWLETT-PACKARD-J     = "Hew\-lett-Pack\-ard Journal: technical
                                  information from the laboratories of
                                  Hew\-lett-Pack\-ard Company"}

@String{j-IBM-JRD               = "IBM Journal of Research and Development"}

@String{j-IEEE-CGA              = "IEEE Computer Graphics and Applications"}

@String{j-IEEE-CONCURR          = "IEEE Concurrency"}

@String{j-IEEE-MICRO            = "IEEE Micro"}

@String{j-INT-J-HIGH-SPEED-COMPUTING = "International Journal of High Speed Computing"}

@String{j-LECT-NOTES-COMP-SCI   = "Lecture Notes in Computer Science"}

@String{j-LINUX-J               = "Linux Journal"}

@String{j-MICROPROC-MICROSYS    = "Microprocessors and Microsystems"}

@String{j-SIGPLAN               = "ACM SIG{\-}PLAN Notices"}

%%% ====================================================================
%%% Publishers and their addresses:

@String{pub-ACM                 = "ACM Press"}
@String{pub-ACM:adr             = "New York, NY 10036, USA"}

@String{pub-AMD                 = "Advanced Micro Devices, Inc."}
@String{pub-AMD:adr             = "One AMD Place, P.O. Box 3453, Sunnyvale,
                                   California, USA"}

@String{pub-AP-PROFESSIONAL     = "AP Professional"}
@String{pub-AP-PROFESSIONAL:adr = "Boston, MA, USA"}

@String{pub-AW                  = "Ad{\-d}i{\-s}on-Wes{\-l}ey"}
@String{pub-AW:adr             = "Reading, MA, USA"}

@String{pub-AW-LONGMAN          = "Ad{\-d}i{\-s}on-Wes{\-l}ey Longman"}
@String{pub-AW-LONGMAN:adr      = "Harlow, Essex CM20 2JE, England"}

@String{pub-AWDP                = "Ad{\-d}i{\-s}on-Wes{\-l}ey Developers Press"}
@String{pub-AWDP:adr            = "Reading, MA, USA"}

@String{pub-BUTTERWORTH-HEINEMANN = "Butterworth-Heinemann"}
@String{pub-BUTTERWORTH-HEINEMANN:adr = "Boston, MA, USA"}

@String{pub-CRC                 = "CRC Press"}
@String{pub-CRC:adr             = "2000 N.W. Corporate Blvd., Boca Raton,
                                  FL 33431-9868, USA"}

@String{pub-DP                  = "Digital Press"}
@String{pub-DP:adr              = "12 Crosby Drive, Bedford, MA 01730, USA"}

@String{pub-HP                  = "Hewlett--Packard Corporation"}
@String{pub-HP:adr              = "Rockville, MD 20850, USA"}

@String{pub-IBM                 = "IBM Corporation"}
@String{pub-IBM:adr             = "San Jose, CA, USA"}

@String{pub-IBM-REDBOOKS        = "IBM Redbooks"}
@String{pub-IBM-REDBOOKS:adr    = "11400 Burnet Road, Austin, TX 78758-3493,
                                   USA"}

@String{pub-IEEE                = "IEEE Computer Society Press"}
@String{pub-IEEE:adr            = "1109 Spring Street, Suite 300, Silver
                                   Spring, MD 20910, USA"}

@String{pub-INTEL               = "Intel Corporation"}
@String{pub-INTEL:adr           = "Santa Clara, CA, USA"}

@String{pub-IOS                 = "IOS Press"}
@String{pub-IOS:adr             = "Amsterdam, The Netherlands"}

@String{pub-KLUWER              = "Kluwer Academic Publishers"}
@String{pub-KLUWER:adr          = "Dordrecht, The Netherlands"}

@String{pub-MACMILLAN          = "Macmillan Publishing Co., Inc."}
@String{pub-MACMILLAN:adr      = "New York, NY, USA"}

@String{pub-MCGRAW-HILL         = "Mc{\-}Graw-Hill"}
@String{pub-MCGRAW-HILL:adr     = "New York, NY, USA"}

@String{pub-MORGAN-KAUFMANN = "Morgan Kaufmann Publishers"}
@String{pub-MORGAN-KAUFMANN:adr = "Los Altos, CA 94022, USA"}
@String{pub-MORGAN-KAUFMANN:adrnew = "2929 Campus Drive, Suite 260, San
                                  Mateo, CA 94403, USA"}

@String{pub-MOTOROLA            = "Motorola Corporation"}
@String{pub-MOTOROLA:adr        = "Phoenix, AZ, USA"}

@String{pub-MT                  = "M\&T Books"}
@String{pub-MT:adr              = "M\&T Publishing, Inc., 501 Galveston Drive,
                                    Redwood City, CA 94063, USA"}

@String{pub-OHMSHA              = "Ohmsha, Ltd."}
@String{pub-OHMSHA:adr          = "3-1 Kanda Nishiki-cho, Chiyoda-ku, Tokyo 101, Japan"}

@String{pub-ORA                 = "O'Reilly \& {Associates, Inc.}"}
@String{pub-ORA:adr             = "981 Chestnut Street, Newton, MA 02164, USA"}

@String{pub-OXFORD              = "Oxford University Press"}
@String{pub-OXFORD:adr          = "Walton Street, Oxford OX2 6DP, UK"}

@String{pub-PEREGRINUS          = "Peter Peregrinus Ltd"}
@String{pub-PEREGRINUS:adr      = "Michael Faraday House, Six Hills Way,
                                   Stevenage, Herts SG1 2AY, UK"}

@String{pub-PH                  = "Pren{\-}tice-Hall"}
@String{pub-PH:adr              = "Upper Saddle River, NJ 07458, USA"}

@String{pub-PHI                 = "Pren{\-}tice-Hall International"}
@String{pub-PHI:adr             = "Englewood Cliffs, NJ 07632, USA"}

@String{pub-PHPTR               = "Pren{\-}tice-Hall PTR"}
@String{pub-PHPTR:adr           = "Upper Saddle River, NJ 07458, USA"}

@String{pub-PITMAN              = "Pitman Publishing Ltd."}
@String{pub-PITMAN:adr          = "London, UK"}

@String{pub-QUE                 = "Que Corporation"}
@String{pub-QUE:adr             = "Indianapolis, IN, USA"}

@String{pub-SAMS                = "Howard W. Sams"}
@String{pub-SAMS:adr            = "Indianapolis, IN 46268, USA"}

@String{pub-SAUNDERS            = "Saunders College Pub."}
@String{pub-SAUNDERS:adr        = "Fort Worth, TX, USA"}

@String{pub-SIEMENS             = "Siemens Aktiengesellschaft"}
@String{pub-SIEMENS:adr         = "Berlin and Munich, Germany"}

@String{pub-SUN                 = "Sun Microsystems"}
@String{pub-SUN:adr             = "901 San Antonio Road, Palo Alto,
                                   CA 94303-4900, USA"}

@String{pub-SV                  = "Spring{\-}er-Ver{\-}lag"}
@String{pub-SV:adr              = "Berlin, Germany~/ Heidelberg, Germany~/ London, UK~/ etc."}

@String{pub-TELOS               = "TELOS division of Springer-Verlag"}
@String{pub-TELOS:adr           = "Santa Clara, CA, USA and New York, NY, USA"}

@String{pub-UNIV-VIDEO-COMM     = "University Video Communications"}
@String{pub-UNIV-VIDEO-COMM:adr = "Stanford, CA, USA"}

@String{pub-VNR                = "Van Nostrand Reinhold Co."}
@String{pub-VNR:adr            = "New York, NY, USA"}

@String{pub-WILEY-INTERSCIENCE = "Wiley-In{\-}ter{\-}sci{\-}ence"}
@String{pub-WILEY-INTERSCIENCE:adr = "New York, NY, USA"}

@String{pub-WINDCREST          = "Windcrest/McGraw-Hill"}
@String{pub-WINDCREST:adr      = "Blue Ridge Summit, PA, USA"}

%%% ====================================================================
%%% Bibliography entries, sorted by citation key.

@Article{Ahi:1992:DVH,
  author =       "Ali M. Ahi and Gregory D. Burroughs and Audrey B. Gore
                 and Steve W. LaMar and Chi-Yen R. Lin and A. L.
                 Wiemann",
  title =        "Design verification of the {HP 9000 Series 700
                 PA-RISC} workstations",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "43",
  number =       "4",
  pages =        "34--42",
  month =        aug,
  year =         "1992",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Tue Mar 25 14:12:15 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "First a high-level system model was simulated and
                 compared with a reference machine running both HP
                 standard and pseudorandom test programs. Then the same
                 tests were run on hardware prototypes. All chips were
                 able to boot the operating system on first silicon.",
  acknowledgement = ack-nhfb,
  affiliation =  "Hewlett Packard Co., Palo Alto, CA, USA",
  classcodes =   "C5430 (Microcomputers); C5470 (Performance evaluation
                 and testing)",
  classification = "C5430 (Microcomputers); C5470 (Performance
                 evaluation and testing)",
  corpsource =   "Hewlett Packard Co., Palo Alto, CA, USA",
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
  keywords =     "computer testing; computers; formal verification;
                 Hardware prototypes; hardware prototypes; Hewlett
                 Packard; high-level system; High-level system model; HP
                 9000 Series 700 PA-RISC workstations; model; Operating
                 system; operating system; Pseudorandom test programs;
                 pseudorandom test programs; reduced instruction set
                 computing; Reference machine; reference machine;
                 workstations",
  thesaurus =    "Computer testing; Formal verification; Hewlett Packard
                 computers; Reduced instruction set computing;
                 Workstations",
  treatment =    "P Practical",
  xxnote =       "Check authors??",
}

@Manual{AMD:2000:AKE,
  title =        "{AMD-K62-E+} Embedded Processor Data Sheet",
  organization = pub-AMD,
  address =      pub-AMD:adr,
  pages =        "xxii + 346",
  month =        sep,
  year =         "2000",
  bibdate =      "Tue Jan 16 16:55:41 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "Order number 23542A/0",
  URL =          "http://www.amd.com/products/epd/processors/6.32bitproc/8.amdk6fami/28.amdk62e/23542/23542a.pdf",
  acknowledgement = ack-nhfb,
}

@Manual{AMD:2000:TM,
  title =        "{3DNow!} Technology Manual",
  organization = pub-AMD,
  address =      pub-AMD:adr,
  pages =        "x + 62",
  month =        mar,
  year =         "2000",
  bibdate =      "Tue Jan 16 16:55:41 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "Order number 21928G/0.",
  URL =          "http://www.amd.com/products/epd/processors/6.32bitproc/8.amdk6fami/26.amdk62e/21928/21928.pdf",
  acknowledgement = ack-nhfb,
}

@Book{Anderson:1995:PPS,
  author =       "Don Anderson and Tom Shanley",
  title =        "{Pentium} processor system architecture",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  edition =      "Second",
  pages =        "xxvii + 433",
  year =         "1995",
  ISBN =         "0-201-40992-5",
  ISBN-13 =      "978-0-201-40992-5",
  LCCN =         "QA76.8.P46 A63 1995",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  series =       "PC system architecture series",
  acknowledgement = ack-nhfb,
  keywords =     "Pentium (microprocessor)",
}

@Article{Anonymous:1992:HSP,
  author =       "Anonymous",
  title =        "{HP} Standard {PA-RISC} Test Programs",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "43",
  number =       "4",
  pages =        "35--??",
  month =        aug,
  year =         "1992",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Sun May 26 09:44:33 MDT 1996",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
}

@Article{Anonymous:1992:PPM,
  author =       "Anonymous",
  title =        "{PA-RISC} Performance Modeling and Simulation",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "43",
  number =       "4",
  pages =        "21--??",
  month =        aug,
  year =         "1992",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Sun May 26 09:44:33 MDT 1996",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
}

@Article{Anonymous:1997:OI,
  author =       "Anonymous",
  title =        "Optimizing the {IA-64}",
  journal =      j-IEEE-MICRO,
  volume =       "17",
  number =       "5",
  pages =        "6--6",
  month =        "????",
  year =         "1997",
  CODEN =        "IEMIDZ",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}

@Book{Antonakos:1997:PM,
  author =       "James L. Antonakos",
  title =        "The Pentium microprocessor",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "xv + 539",
  year =         "1997",
  ISBN =         "0-02-303614-1",
  ISBN-13 =      "978-0-02-303614-9",
  LCCN =         "QA76.8.P46 A64 1997",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "Includes index.",
  acknowledgement = ack-nhfb,
  keywords =     "Pentium (microprocessor)",
}

@Book{Apple:1994:IMPa,
  author =       "{Apple Computer, Inc}",
  title =        "Inside {Macintosh}. {PowerPC} Numerics",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "various",
  year =         "1994",
  ISBN =         "0-201-40728-0",
  ISBN-13 =      "978-0-201-40728-0",
  LCCN =         "QA76.8.M3 I5622 1994",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  price =        "US\$28.95, CDN\$37.95",
  series =       "Apple technical library",
  acknowledgement = ack-nhfb,
  keywords =     "Macintosh (computer); PowerPC microprocessors",
}

@Book{Apple:1994:IMPb,
  author =       "{Apple Computer, Inc}",
  title =        "Inside {Macintosh}. {PowerPC} system software",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "various",
  year =         "1994",
  ISBN =         "0-201-40727-2",
  ISBN-13 =      "978-0-201-40727-3",
  LCCN =         "QA76.8.M3 I528 1994",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  price =        "US\$24.95, CDN\$31.95",
  series =       "Apple technical library",
  acknowledgement = ack-nhfb,
  keywords =     "Macintosh (computer); PowerPC microprocessors; systems
                 software",
}

@Book{Apple:1995:PMC,
  author =       "{Apple Computer, Inc.} and {IBM Corporation} and
                 {Motorola, Inc.}",
  title =        "{PowerPC} Microprocessor Common Hardware Reference
                 Platform: {A} System Architecture",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  pages =        "xxiv + 309",
  year =         "1995",
  ISBN =         "1-55860-394-8",
  ISBN-13 =      "978-1-55860-394-3",
  LCCN =         "QA76.89.P67P74 1995",
  bibdate =      "Fri Jan 19 08:14:50 1996",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$39.95",
  acknowledgement = ack-nhfb,
}

@Article{Asprey:1993:PFP,
  author =       "T. Asprey and G. S. Averill and E. DeLano and R. Mason
                 and B. Weiner and J. Yetter",
  title =        "Performance Features of the {PA7100} Microprocessor",
  journal =      j-IEEE-MICRO,
  volume =       "13",
  number =       "3",
  pages =        "22--35",
  month =        jun,
  year =         "1993",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.216746",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  acknowledgement = ack-nhfb,
  classcodes =   "C5220 (Computer architecture)",
  corpsource =   "Hewlett--Packard, Fort Collins, CO, USA",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "cache design; computer; floating-point unit; interface
                 bus; microprocessor chips; microprocessor instruction
                 execution; PA-RISC; PA7100 CPU; pipeline;
                 precision-architecture; reduced instruction set
                 computing; reduced-instruction-set-; system;
                 translation look-aside buffer; verification; virtual
                 address translation",
  treatment =    "P Practical",
}

@Article{Atkins:1991:PIM,
  author =       "Mark Atkins",
  title =        "Performance and the {i860} Microprocessor",
  journal =      j-IEEE-MICRO,
  volume =       "11",
  number =       "5",
  pages =        "24--27, 72--78",
  month =        oct,
  year =         "1991",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.108548",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  abstract =     "Pipelining, parallelism, and internal caches help this
                 million-transistor chip enhance performance",
  acknowledgement = ack-nhfb,
  affiliation =  "Intel Corp, Santa Clara, CA, USA",
  classcodes =   "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture);
                 C5470 (Performance evaluation and testing)",
  classification = "714.2; 721.3; 722.4",
  corpsource =   "Intel Corp., Santa Clara, CA, USA",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "Cache memory; caches; Computer architecture; digital
                 signal; Explicit pipelines; Floating-point pipelines;
                 graphics; high-bandwidth registers; I860 cpu; i860 CPU;
                 I860 microprocessor; instruction set computing;
                 instructions; Intel microprocessor; memory-performance
                 optimizations; microprocessor; Microprocessor chips;
                 microprocessor chips; Parallel processing systems;
                 parallelism; performance evaluation; Pipeline
                 processing systems; pipelining; processing; reduced;
                 RISC; simultaneous floating-point operations; Six-stage
                 pipelines; two-instruction-per-clock mode",
  treatment =    "P Practical",
}

@Book{ATT:1990:SVA,
  author =       "{American Telephone and Telegraph Company}",
  title =        "{System V} application binary interface: {SPARC}
                 processor supplement",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "various",
  year =         "1990",
  ISBN =         "0-13-877630-X",
  ISBN-13 =      "978-0-13-877630-5",
  LCCN =         "QA76.76.O63 S9745 1990 Bar",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "UNIX System V (computer file)",
}

@Book{ATT:1991:SVA,
  author =       "{American Telephone and Telegragh Company}",
  title =        "{System V} application binary interface: {MIPS}
                 processor supplement: {UNIX System V}",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "various",
  year =         "1991",
  ISBN =         "0-13-880170-3",
  ISBN-13 =      "978-0-13-880170-0",
  LCCN =         "QA76.76.O63 S9742 1991 Bar",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "MIPS-x (microprocessor); UNIX System V (computer
                 file)",
}

@Article{Averill:1999:CIM,
  author =       "R. M. {Averill III} and K. G. Barkley and M. A. Bowen
                 and P. J. Camporese and A. H. Dansky and R. F. Hatch
                 and D. E. Hoffman and M. D. Mayo and S. A. McCabe and
                 T. G. McNamara and T. J. McPherson and G. A. Northrop
                 and L. Sigal and H. H. Smith and D. A. Webber and P. M.
                 Williams",
  title =        "Chip integration methodology for the {IBM S/390 G5}
                 and {G6} custom microprocessors",
  journal =      j-IBM-JRD,
  volume =       "43",
  number =       "5/6",
  pages =        "681--706",
  month =        "????",
  year =         "1999",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Wed Apr 19 18:58:23 MDT 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ibmjrd.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.research.ibm.com/journal/rd/435/averill.html",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
}

@Article{Bakoglu:1990:IRS,
  author =       "H. B. Bakoglu and G. F. Grohoski and R. K. Montoye",
  title =        "The {IBM RISC System}\slash 6000 processor: Hardware
                 overview",
  journal =      j-IBM-JRD,
  volume =       "34",
  number =       "1",
  pages =        "12--22",
  month =        jan,
  year =         "1990",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Tue Mar 25 14:26:59 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ibmjrd.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "A highly concurrent superscalar second-generation
                 family of RISC workstations and servers is described.
                 The RISC System\slash 6000 family is based on the new
                 IBM POWER (performance optimization with enhanced RISC)
                 architecture; the hardware implementation takes
                 advantage of this powerful RISC architecture and
                 employs sophisticated design techniques to achieve a
                 short cycle time and a low cycles-per-instruction (CPI)
                 ratio. The RS\slash 6000 CPU features
                 multiple-instruction dispatch, multiple functional
                 units that operate concurrently, separate instruction
                 and data caches, and zero-cycle branches. In this
                 superscalar implementation, at a given cycle the
                 equivalent of five operations can be executed
                 simultaneously (a branch, a condition-register
                 operation, and a floating-point multiply-add). The
                 RS\slash 6000 family supports the IBM Micro Channel
                 architecture as well as high-speed serial optical links
                 to provide a high-bandwidth I/O subsystem.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Adv. Workstations Div., Austin, TX, USA",
  classcodes =   "C5440 (Multiprocessor systems and techniques); C5220
                 (Computer architecture)",
  classification = "C5220 (Computer architecture); C5440 (Multiprocessor
                 systems and techniques)",
  corpsource =   "IBM Adv. Workstations Div., Austin, TX, USA",
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "architecture; branch; Branch; caches; concurrent
                 superscalar second-generation family; Concurrent
                 superscalar second-generation family;
                 condition-register; Condition-register operation; CPI
                 ratio; Cycle time; cycle time; cycles-per-instruction;
                 Cycles-per-instruction ratio; data; Data caches;
                 floating-point multiply-add; Floating-point
                 multiply-add; high-bandwidth I/O; High-bandwidth I/O
                 subsystem; High-bandwidth I/O subsystem, RISC servers;
                 IBM computers; IBM Micro Channel; IBM Micro Channel
                 architecture; IBM POWER architecture; IBM RISC
                 System/6000; IBM RISC System/6000 processor; IBM RISC
                 System\slash 6000 processor; instruction caches;
                 Instruction caches; instruction dispatch; Multiple
                 functional units; multiple functional units; multiple-;
                 Multiple-instruction dispatch; multiprocessing systems;
                 operation; performance optimization with enhanced;
                 Performance optimization with enhanced RISC; processor;
                 ratio; reduced instruction; RISC; RISC architecture;
                 RISC servers; RISC workstations; RS/6000 CPU; RS\slash
                 6000 CPU; serial optical links; Serial optical links;
                 set computing; subsystem; zero-cycle branches;
                 Zero-cycle branches",
  thesaurus =    "IBM computers; Multiprocessing systems; Reduced
                 instruction set computing",
  treatment =    "P Practical",
}

@Book{Bhandarkar:1996:AIA,
  author =       "Dileep P. Bhandarkar",
  title =        "{Alpha} implementations and architecture: complete
                 reference and guide",
  publisher =    pub-DP,
  address =      pub-DP:adr,
  pages =        "xviii + 328",
  year =         "1996",
  ISBN =         "1-55558-130-7",
  ISBN-13 =      "978-1-55558-130-5",
  LCCN =         "QA76.8.A176B47 1996",
  bibdate =      "Thu Aug 07 13:42:54 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$41.95",
  acknowledgement = ack-nhfb,
}

@Article{Bharadwaj:2000:IIC,
  author =       "Jay Bharadwaj and William Y. Chen and Weihaw Chuang
                 and Gerolf Hoflehner and Kishore Menezes and Kalyan
                 Muthukumar and Jim Pierce",
  title =        "The {Intel IA-64} Compiler Code Generator",
  journal =      j-IEEE-MICRO,
  volume =       "20",
  number =       "5",
  pages =        "44--53",
  month =        sep # "\slash " # oct,
  year =         "2000",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.877949",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Tue Oct 10 06:00:40 MDT 2000",
  bibsource =    "http://www.computer.org/micro/mi2000/;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://dlib.computer.org/mi/books/mi2000/pdf/m5044.pdf;
                 http://www.computer.org/micro/mi2000/m5044abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}

@Article{Birman:1990:DWS,
  author =       "Mark Birman and Allen Samuels and George Chu and Ting
                 Chuk and Larry Hu and John McLeod and John Barnes",
  title =        "Developing the {WTL3170\slash 3171 Sparc}
                 Floating-Point Coprocessors",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "1",
  pages =        "55--64",
  month =        feb,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.46769",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database;
                 garbo.uwasa.fi:/pc/doc-soft/fpbiblio.txt;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  abstract =     "Contending with dual floating-point interfaces at both
                 25 and 40 MHz posed an extraordinary challenge in
                 coprocessor development.",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  affiliation =  "Weitek Corp, Sunnyvale, CA, USA",
  classcodes =   "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5230 (Digital arithmetic
                 methods)",
  classification = "721; 722; 723",
  conference =   "First Annual Hot Chips Symposium",
  corpsource =   "Weitek Corp., Sunnyvale, CA, USA",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "64-b ALU; bus organization; Circuits; Computer
                 Architecture; Computer Interfaces; Computers,
                 Microcomputer; digital arithmetic; divide/square-root;
                 Divide/Square-Root Unit; floating-point; Floating-Point
                 Adder; floating-point controller functions;
                 Floating-Point Multiplier; integer; microprocessor
                 chips; multiplier; register files; Sparc Floating-Point
                 Coprocessors; system behavioral-level modeling; unit;
                 units; WTL3170/3171 Sparc floating-point coprocessors",
  meetingabr =   "First Annu Hot Chips Symp",
  meetingaddress = "Palo Alto, CA, USA",
  meetingdate =  "Jun 26--27 1989",
  meetingdate2 = "06/26--27/89",
  sponsor =      "IEEE Computer Soc, Palo Alto, CA, USA",
  treatment =    "P Practical",
}

@Article{Bishop:1996:PAA,
  author =       "J. W. Bishop and M. J. Campion and T. L. Jeremiah and
                 S. J. Mercier and E. J. Mohring and K. P. Pfarr and B.
                 G. Rudolph and G. S. Still and T. S. White",
  title =        "{PowerPC AS A10} 64-bit {RISC} microprocessor",
  journal =      j-IBM-JRD,
  volume =       "40",
  number =       "4",
  pages =        "495--505",
  month =        "????",
  year =         "1996",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Fri Sep 20 13:33:11 1996",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ibmjrd.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.almaden.ibm.com/journal/rd40-4.html#10",
  abstract =     "The PowerPC AS* A10 64-bit RISC microprocessor is a
                 4.7-million-transistor integrated circuit design, using
                 IBM CMOS 5L 0.5-$ \mu $ m, 3-V, four-level-metal ASIC
                 technology. Support for the PowerPC AS architecture is
                 implemented in a 213-mm$^2$ die using a semicustom
                 design methodology. Chip density and speed are enhanced
                 through the use of custom macros and multiport arrays.
                 An on-chip phase-locked-loop circuit is used to reduce
                 chip-to-chip clock skew. Full utilization of the
                 four-level-metal interconnect technology was achieved
                 through architectural floorplanning, performance
                 clustering, and timing-driven placement and wiring,
                 with a total wire length of over 102 meters placed on
                 the 14.6 $ \times $ 14.6-mm die. The microprocessor is
                 a pipelined, superscalar design with five separate
                 functional units, a 4KB instruction cache, and an 8KB
                 data cache. The design includes parity,
                 error-correction, and error-logging functions, as well
                 as self-test for logic and arrays during power-on. The
                 design is robust and implements a wide range of
                 performance configurations at the system level,
                 allowing direct attachment of DRAM to the processor, or
                 high-performance L2 cache options using high-speed
                 SRAM. An on-chip system I/O bus and bus controller are
                 provided for attachment of peripherals.",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  xxlibnote =    "Issue missing from UofUtah Marriott Library",
}

@Book{Blaauw:1997:CAC,
  author =       "Gerrit A. Blaauw and Frederick P. {Brooks, Jr.}",
  title =        "Computer architecture: concepts and evolution",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "xlviii + 1213",
  year =         "1997",
  ISBN =         "0-201-10557-8",
  ISBN-13 =      "978-0-201-10557-5",
  LCCN =         "QA76.9.A73 B57 1997",
  bibdate =      "Wed Jul 09 17:22:33 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$59.95",
  acknowledgement = ack-nhfb,
}

@Article{Blinn:1997:JBCa,
  author =       "James F. Blinn",
  title =        "{Jim Blinn}'s Corner: Fugue for {MMX}",
  journal =      j-IEEE-CGA,
  volume =       "17",
  number =       "2",
  pages =        "88--93",
  month =        mar # "\slash " # apr,
  year =         "1997",
  CODEN =        "ICGADZ",
  DOI =          "http://dx.doi.org/10.1109/38.574688",
  ISSN =         "0272-1716 (print), 1558-1756 (electronic)",
  ISSN-L =       "0272-1716",
  bibdate =      "Mon Mar 03 09:18:04 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "Makes several cogent comments about deficiencies in
                 the Intel MMX pixel-processing instruction set
                 \cite{Peleg:1997:IMM} for use in image compositing.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Computer Graphics and Applications",
  journal-URL =  "http://www.computer.org/portal/web/csdl/magazines/cga",
}

@Article{Bockhaus:1997:EVH,
  author =       "J. W. Bockhaus and R. Bhatia and C. M. Ramsey and J.
                 R. Butler and D. J. Ljung",
  title =        "Electrical Verification of the {HP PA 8000}
                 Processor",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "48",
  number =       "4",
  pages =        "32--39",
  month =        aug,
  year =         "1997",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Wed Mar 25 15:17:10 MST 1998",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.hp.com/hpj/97aug/au97a4.htm",
  abstract =     "Electrical verification applies techniques from both
                 functional verification and reliability and
                 environmental testing to improve the quality of the
                 CPU. Electrical verification checks that the CPU
                 functions correctly under stressful environmental
                 conditions, well outside the normal operating
                 environment.",
  acknowledgement = ack-nhfb,
  classification = "B0170E (Production facilities and engineering)C5130
                 (Microprocessor chips); B0170N (Reliability); B1265F
                 (Microprocessors and microcomputers); C5470
                 (Performance evaluation and testing)",
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
  keywords =     "computer testing; electrical verification;
                 environmental testing; functional verification; Hewlett
                 Packard computers; HP PA 8000 processor; microprocessor
                 chips; normal operating environment; reliability;
                 stressful environmental conditions",
  treatment =    "A Application; P Practical",
}

@Article{Bollinger:1992:PHK,
  author =       "D. E. Bollinger and F. P. Lemmon and D. L. Yamine",
  title =        "Providing {HP-UX} kernel functionality on a new
                 {PA-RISC} architecture",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "43",
  number =       "3",
  pages =        "11--14",
  month =        jun,
  year =         "1992",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Tue Mar 25 14:12:15 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "The aggressive schedule for the development of the HP
                 9000 Series 700 systems required the development team
                 in the HP-UX kernel laboratory to consider some
                 modifications to the normal software development
                 process, the number of product features, and the
                 management structure. The goals for the product
                 features were to change or add the minimum number of
                 HP-UX kernel functions that would ensure customer
                 satisfaction, meet performance goals, and adapt to a
                 new I/O system. This version of the HP-UX kernel code
                 became known as minimum core functionality, or MCF.",
  acknowledgement = ack-nhfb,
  affiliation =  "Hewlett--Packard Co., Palo Alto., CA, USA",
  classcodes =   "C0310F (Software development management); C6110B
                 (Software engineering techniques); C6150J (Operating
                 systems)",
  classification = "C0310F (Software development management); C6110B
                 (Software engineering techniques); C6150J (Operating
                 systems)",
  corpsource =   "Hewlett--Packard Co., Palo Alto., CA, USA",
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
  keywords =     "(computers); development process; Development team;
                 development team; DP management; engineering;
                 functionality; Hewlett Packard computers; HP 9000
                 Series 700 systems; HP-UX 8.0; HP-UX kernel
                 functionality; Management structure; management
                 structure; minimum core; Minimum core functionality;
                 operating systems; PA-RISC architecture; reduced
                 instruction set computing; software; Software
                 development process",
  thesaurus =    "DP management; Hewlett Packard computers; Operating
                 systems [computers]; Reduced instruction set computing;
                 Software engineering",
  treatment =    "P Practical",
}

@Book{Brey:1995:IMP,
  author =       "Barry B. Brey",
  title =        "The {Intel} 32-bit microprocessors: 80386, 80486, and
                 {Pentium} microprocessors",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "xii + 801",
  year =         "1995",
  ISBN =         "0-02-314260-X",
  ISBN-13 =      "978-0-02-314260-4",
  LCCN =         "QA 76.8 I2684 B74 1995",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "Intel 80386 (microprocessor); Intel 80486
                 (microprocessor); Pentium (microprocessor)",
}

@Book{Brey:1996:PPP,
  author =       "Barry B. Brey",
  title =        "Programming the 80286, 80386, 80486, and
                 {Pentium}-based personal computer",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "x + 786",
  year =         "1996",
  ISBN =         "0-02-314263-4",
  ISBN-13 =      "978-0-02-314263-5",
  LCCN =         "QA76.8.I2674 B77 1996",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "Intel 80xxx series microprocessors --- programming;
                 Pentium (microprocessor) --- programming",
}

@Book{Brey:1997:IMP,
  author =       "Barry B. Brey",
  title =        "The {Intel} microprocessors: 8086\slash 8088,
                 80186\slash 80188, 80286, 80386, 80486, {Pentium}, and
                 {Pentium Pro} processor",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  edition =      "Fourth",
  pages =        "xv + 907",
  year =         "1997",
  ISBN =         "0-13-260670-4",
  ISBN-13 =      "978-0-13-260670-7",
  LCCN =         "QA76.8.I2674 B75 1997",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "Intel 80xxx series microprocessors; Pentium
                 (microprocessor)",
}

@Book{Brey:2000:IMP,
  author =       "Barry B. Brey",
  title =        "The {Intel} microprocessors: 8086\slash 8088,
                 80186\slash 80188, 80286, 80386, 80486, {Pentium},
                 {Pentium Pro}, and {Pentium II} processors:
                 architecture, programming, and interfacing",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  edition =      "Fifth",
  pages =        "ix + 966",
  year =         "2000",
  ISBN =         "0-13-995408-2",
  ISBN-13 =      "978-0-13-995408-5",
  LCCN =         "QA76.8.I2674 B76 2000",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "Intel 80xxx series microprocessors; Pentium
                 (microprocessor)",
}

@Book{Brookes:1989:IOT,
  author =       "Graham R. Brookes and Andrew J. Stewart",
  title =        "Introduction to occam 2 on the transputer",
  publisher =    pub-MACMILLAN,
  address =      pub-MACMILLAN:adr,
  pages =        "vii + 102",
  year =         "1989",
  ISBN =         "0-333-45340-9 (paperback)",
  ISBN-13 =      "978-0-333-45340-7 (paperback)",
  LCCN =         "QA76.73.O212 B76 1989 Bar",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  price =        "UK\pounds8.95",
  series =       "Macmillan computer science series",
  acknowledgement = ack-nhfb,
  keywords =     "occam2 (computer program language)",
}

@Article{Brown:1990:ISE,
  author =       "Emil W. Brown and Anant Agrawal and Trevor Creary and
                 Michael F. Klein and David Murata and Joseph Petolino",
  title =        "Implementing {Sparc} in {ECL}",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "1",
  pages =        "10--22",
  month =        feb,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.46764",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  abstract =     "Two companies successfully joined - forces to design a
                 small, low-cost system capables of large mainframe
                 performance.",
  acknowledgement = ack-nhfb,
  affiliation =  "Sun Microsystems Inc, USA",
  classcodes =   "B1265F (Microprocessors and microcomputers); B2570B
                 (Bipolar integrated circuits); C5130 (Microprocessor
                 chips); C5220 (Computer architecture)",
  classification = "714; 721; 722; 723",
  conference =   "First Annual Hot Chips Symposium",
  corpsource =   "Sun Microsyst. Inc., Mountain View, CA, USA",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "B5000 Microprocessor; bipolar emitter-; bipolar
                 integrated circuits; Cache Design; computer
                 architecture; Computer Interfaces; Computers,
                 Microcomputer; coprocessor interface; coupled logic;
                 ECL; ecl Inverter; emitter-; Integer Unit Pipeline;
                 integer unit pipeline; Integrated Circuits, VLSI; Logic
                 Circuits, Emitter Coupled; microprocessor chips; RISC
                 Architecture; scalable processor architecture; Scalable
                 Processor Architecture (Sparc); signals; Sparc; system
                 interface; Transistors, Bipolar",
  meetingabr =   "First Annu Hot Chips Symp",
  meetingaddress = "Palo Alto, CA, USA",
  meetingdate =  "Jun 26--27 1989",
  meetingdate2 = "06/26--27/89",
  sponsor =      "IEEE Computer Soc, Palo Alto, CA, USA",
  treatment =    "P Practical",
  xxauthor =     "E. W. Brown and A. Agrawal and T. Creary and M. F.
                 Klein and D. Murata and J. Petolino",
}

@TechReport{Broy:1995:FSA,
  author =       "M. Broy",
  title =        "A functional specification of the {Alpha AXP} shared
                 memory model",
  type =         "SRC research report",
  number =       "136",
  institution =  "Digital Systems Research Center",
  address =      "Palo Alto, CA, USA",
  pages =        "34",
  day =          "3",
  month =        apr,
  year =         "1995",
  LCCN =         "TK7895.M4 B76 1994",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "computer architecture; computer storage devices;
                 reduced instruction set computers",
}

@Book{Bruss:1991:RMF,
  author =       "Rolf-Jurgen Bruss",
  title =        "{RISC}: the {MIPS-R3000} family",
  publisher =    pub-SIEMENS,
  address =      pub-SIEMENS:adr,
  pages =        "360",
  year =         "1991",
  LCCN =         "QA76.5.R49 1991",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "computer architecture; microcomputer workstations;
                 risc microprocessors",
}

@Book{Bunda:1995:PMD,
  author =       "John Bunda and Terence Potter and Robert Shadowen",
  title =        "{PowerPC} microprocessor developer's guide",
  publisher =    pub-SAMS,
  address =      pub-SAMS:adr,
  pages =        "xii + 400",
  year =         "1995",
  ISBN =         "0-672-30543-7",
  ISBN-13 =      "978-0-672-30543-6",
  LCCN =         "QA76.8.P67 B86 1995",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  price =        "US\$35.00, CDN\$47.95",
  series =       "Sams developer's guide",
  acknowledgement = ack-nhfb,
  keywords =     "PowerPC microprocessors --- programming",
}

@Book{Carling:1988:PPO,
  author =       "Alison Carling",
  title =        "Parallel processing: Occam and the transputer",
  publisher =    "Sigma",
  address =      "Wilmslow, Cheshire, UK",
  pages =        "156",
  year =         "1988",
  ISBN =         "1-85058-077-4 (paperback)",
  ISBN-13 =      "978-1-85058-077-5 (paperback)",
  LCCN =         "QA76.6 .C375 1988 Bar",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  price =        "UK\pounds12.95",
  acknowledgement = ack-nhfb,
  keywords =     "occam (computer program language); parallel processing
                 (electronic computers)",
}

@Book{Catanzaro:1991:STP,
  editor =       "Ben J. Catanzaro",
  title =        "The {SPARC} Technical Papers",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "xvi + 501",
  year =         "1991",
  ISBN =         "0-387-97634-5, 3-540-97634-5",
  ISBN-13 =      "978-0-387-97634-1, 978-3-540-97634-9",
  LCCN =         "QA76.9.A73 S65 1991",
  bibdate =      "Wed Feb 9 01:57:02 1994",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  series =       "Sun technical reference library",
  acknowledgement = ack-nhfb,
}

@Book{Catanzaro:1994:MSA,
  author =       "Ben J. Catanzaro",
  title =        "Multiprocessor system architectures: a technical
                 survey of multiprocessor\slash multithreaded systems
                 using {SPARC}, multilevel bus architectures and
                 {Solaris} {(SunOS)}",
  publisher =    pub-PHPTR,
  address =      pub-PHPTR:adr,
  pages =        "xxxii + 493",
  year =         "1994",
  ISBN =         "0-13-089137-1",
  ISBN-13 =      "978-0-13-089137-2",
  LCCN =         "QA76.5.C3864 1994",
  bibdate =      "Fri Aug 7 08:29:38 MDT 1998",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 http://www.math.utah.edu/pub/tex/bib/multithreading.bib",
  acknowledgement = ack-nhfb,
  keywords =     "computer architecture; multiprocessors; Sun
                 computers",
}

@Article{Cates:1988:PAC,
  author =       "Ron Cates",
  title =        "Processor architecture considerations for embedded
                 controller applications",
  journal =      j-IEEE-MICRO,
  volume =       "8",
  number =       "3",
  pages =        "28--38",
  month =        jun,
  year =         "1988",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.538",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  acknowledgement = ack-nhfb,
  affiliationaddress = "VLSI Technology Inc, Tempe, AZ, USA",
  classcodes =   "C5130 (Microprocessor chips); C5220 (Computer
                 architecture)",
  classification = "722; 723; 731",
  corpsource =   "VLSI Technol. Inc., Tempe, AZ, USA",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "32 bit; 32-bit VL86C010; Acorn RISC; Applications;
                 computer architecture; computer networks --- Control;
                 computers, microcomputer; control systems, digital ---
                 Computer Interfaces; direct memory access controller
                 (DMAC); embedded controller; embedded controller
                 applications; general-purpose cpu; general-purpose CPU;
                 latency; microprocessor chips; network interface;
                 processor architecture; reduced instruction set
                 computing; reduced-instruction-set computer;
                 reduced-instruction-set computer (RISC); system; system
                 latency impact",
  treatment =    "P Practical",
}

@Book{Chakravarty:1994:PCA,
  author =       "Dipto Chakravarty and Casey Cannon",
  title =        "{PowerPC} --- concepts, architecture, and design",
  publisher =    pub-MCGRAW-HILL,
  address =      pub-MCGRAW-HILL:adr,
  pages =        "xx + 362",
  year =         "1994",
  ISBN =         "0-07-11192-8 (invalid checksum??)",
  ISBN-13 =      "0-07-11192-8 (invalid checksum??)",
  LCCN =         "QA76.8.P67 C48 1994",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  price =        "US\$34.95",
  series =       "J. Ranade workstation series",
  acknowledgement = ack-nhfb,
  keywords =     "PowerPC microprocessors",
}

@Article{Check:1999:CGG,
  author =       "M. A. Check and T. J. Slegel",
  title =        "Custom {S/390 G5} and {G6} microprocessors",
  journal =      j-IBM-JRD,
  volume =       "43",
  number =       "5/6",
  pages =        "671--680",
  month =        "????",
  year =         "1999",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Wed Apr 19 18:58:23 MDT 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ibmjrd.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.research.ibm.com/journal/rd/435/check.html",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
}

@Book{Chow:1989:MXR,
  author =       "Paul Chow",
  title =        "The {MIPS-X RISC} microprocessor",
  publisher =    pub-KLUWER,
  address =      pub-KLUWER:adr,
  pages =        "xxiv + 231",
  year =         "1989",
  ISBN =         "0-7923-9045-8",
  ISBN-13 =      "978-0-7923-9045-9",
  LCCN =         "QA76.8.M524 M57 1989",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  series =       "The Kluwer international series in engineering and
                 computer science",
  acknowledgement = ack-nhfb,
  keywords =     "MIPS-X (microprocessor); VLSI, computer architecture,
                 and digital signal processing SECS 81",
}

@Article{Cmelik:1991:AMS,
  author =       "Robert F. Cmelik and Shing I. Kong and David R. Ditzel
                 and Edmund J. Kelly",
  title =        "An Analysis of {MIPS} and {SPARC} Instruction Set
                 Utilization on the {SPEC} Benchmarks",
  journal =      j-SIGPLAN,
  volume =       "26",
  number =       "4",
  pages =        "290--301 (or 290--302??)",
  month =        apr,
  year =         "1991",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "The dynamic instruction counts of MIPS and SPARC are
                 compared using the SPEC benchmarks. MIPS typically
                 executes more user-level instructions than SPARC. This
                 difference can be accounted for by architectural
                 differences, compiler differences, and library
                 differences. The most significant differences are that
                 SPARC's double-precision floating point load/store is
                 an architectural advantage in the SPEC floating point
                 benchmarks while MIPS's compare-and-branch instruction
                 is an architectural advantage in the SPEC integer
                 benchmarks. After the differences in the two
                 architectures are isolated, it appears that although
                 MIPS and SPARC each have strengths and weaknesses in
                 their compilers and library routines, the combined
                 effect of compilers and library routines does not give
                 either MIPS or SPARC a clear advantage in these
                 areas.",
  acknowledgement = ack-nhfb,
  affiliation =  "Sun Microsyst. Inc., Mountain View, CA, USA",
  classification = "C5220 (Computer architecture); C5470 (Performance
                 evaluation and testing); C6140B (Machine-oriented
                 languages)",
  confdate =     "8-11 April 1991",
  conflocation = "Santa Clara, CA, USA",
  confsponsor =  "IEEE; ACM",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "Architectural differences; Compare-and-branch
                 instruction; Compiler differences; Double-precision
                 floating point load/store; Dynamic instruction counts;
                 Instruction set utilization; Library differences; MIPS;
                 SPARC; SPEC floating point benchmarks; SPEC integer
                 benchmarks; User-level instructions",
  thesaurus =    "Instruction sets; Performance evaluation; Reduced
                 instruction set computing",
}

@Book{Cockcroft:1998:SPT,
  author =       "Adrian Cockcroft",
  title =        "{Sun} Performance and Tuning: {SPARC} and {Solaris}",
  publisher =    pub-PHPTR,
  address =      pub-PHPTR:adr,
  edition =      "Second",
  pages =        "xxxvi + 587",
  year =         "1998",
  ISBN =         "0-13-095249-4",
  ISBN-13 =      "978-0-13-095249-3",
  LCCN =         "QA76.8.S86C63 1998",
  bibdate =      "Fri Jan 22 09:54:46 1999",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 http://www.math.utah.edu/pub/tex/bib/unix.bib",
  URL =          "http://www.fdds.com/books/catalog/books_comingsoon.html",
  acknowledgement = ack-nhfb,
}

@Book{Cok:1991:PPT,
  author =       "Ronald S. Cok",
  title =        "Parallel programs for the transputer",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "xii + 242",
  year =         "1991",
  ISBN =         "0-13-651480-4 (paperback)",
  ISBN-13 =      "978-0-13-651480-0 (paperback)",
  LCCN =         "QA76.6 .C6245 1991 Bar",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "parallel programming (computer science); transputers
                 --- programming",
}

@Book{Dandamudi:1998:IAL,
  author =       "Sivarama P. Dandamudi",
  title =        "Introduction to assembly language programming: from
                 8086 to {Pentium} processors",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "xxii + 644",
  year =         "1998",
  ISBN =         "0-387-98530-1",
  ISBN-13 =      "978-0-387-98530-5",
  LCCN =         "QA76.73.A8 D36 1998",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  series =       "Undergraduate texts in computer science",
  acknowledgement = ack-nhfb,
  keywords =     "assembler language (computer program language);
                 microprocessors --- programming",
}

@Article{Darley:1990:TFC,
  author =       "Merrick Darley and Bill Kronlage and David Bural and
                 Bob Churchill and David Pulling and Paul Wang and Rick
                 Iwamoto and Larry Yang",
  title =        "The {TMS390C602A} Floating-Point Coprocessor for
                 {Sparc} Systems",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "3",
  pages =        "36--47",
  month =        jun,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.56324",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "A recent Sparc (scalable processor architecture)
                 processor consists of a two-chip configuration,
                 containing the TMS390C601 integer unit (IU) and the
                 TMS390C602A floating-point unit (FPU). The second
                 device, an innovative coprocessor that lets the
                 processor execute single- or double-precision
                 floating-point instructions concurrently with IU
                 operations is described. Dedicated floating-point
                 hardware in the FPU increases the performance of the
                 system. Running at clock periods as small as 20 ns, the
                 chip should deliver 5.5 million double-precision
                 floating-point operations per second under the Linpack
                 benchmark (50-MHz clock rate). The FPU provides single-
                 and double-precision arithmetic functions: addition,
                 subtraction, multiplication, division, square root,
                 compare, and convert. To minimize its math unit's
                 latency, the FPU uses a highly parallel architecture
                 requiring separate math units to optimize additions and
                 multiplications. Traps stop the execution of a program
                 to jump to software routine for handling data-dependent
                 errors or to execute instructions not implemented in
                 the hardware. Benchmark results are presented. (4
                 Refs.)",
  acknowledgement = ack-nhfb,
  affiliation =  "Texas Instrum. Inc., Dallas, TX, USA",
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5230 (Digital arithmetic
                 methods)",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "Addition; Compare; Convert; Division; Linpack
                 benchmark; Multiplication; Sparc systems; Square root;
                 Subtraction; TMS390C601 integer unit; TMS390C602A
                 floating-point coprocessor; TMS390C602A floating-point
                 unit; Two-chip configuration",
  language =     "English",
  pubcountry =   "USA",
  thesaurus =    "Digital arithmetic; Microprocessor chips",
}

@Article{Darley:1990:TFP,
  author =       "Merrick Darley and Bill Kronlage and David Bural and
                 Bob Churchill and David Pulling and Paul Wang and Rick
                 Iwamoto and Larry Yang",
  title =        "The {TMS390C602A} Floating-Point Coprocessor for
                 {Sparc} Systems",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "3",
  pages =        "36--47",
  month =        jun,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.56324",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database;
                 garbo.uwasa.fi:/pc/doc-soft/fpbiblio.txt;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  abstract =     "A recent Sparc (scalable processor architecture)
                 processor consists of a two-chip configuration,
                 containing the TMS390C601 integer unit (IU) and the
                 TMS390C602A floating-point unit (FPU). The second
                 device, an innovative coprocessor that lets the
                 processor execute single- or double-precision
                 floating-point instructions concurrently with IU
                 operations is described. Dedicated floating-point
                 hardware in the FPU increases the performance of the
                 system. Running at clock periods as small as 20 ns, the
                 chip should deliver 5.5 million double-precision
                 floating-point operations per second under the Linpack
                 benchmark (50-MHz clock rate). The FPU provides single-
                 and double-precision arithmetic functions: addition,
                 subtraction, multiplication, division, square root,
                 compare, and convert. To minimize its math unit's
                 latency, the FPU uses a highly parallel architecture
                 requiring separate math units to optimize additions and
                 multiplications. Traps stop the execution of a program
                 to jump to software routine for handling data-dependent
                 errors or to execute instructions not implemented in
                 the hardware. Benchmark results are presented. (4
                 Refs.)",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  affiliation =  "Texas Instruments Inc, Dallas, TX, USA",
  classcodes =   "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5230 (Digital arithmetic
                 methods)",
  classification = "721; 722; 723; B1265F (Microprocessors and
                 microcomputers); C5130 (Microprocessor chips); C5230
                 (Digital arithmetic methods)",
  conference =   "First Annual Hot Chips Symposium",
  corpsource =   "Texas Instrum. Inc., Dallas, TX, USA",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "Addition; addition; chip configuration; Compare;
                 compare; Computer Architecture--Reduced Instruction Set
                 Computing; Computer Systems, Digital--Parallel
                 Processing; Convert; convert; digital arithmetic;
                 Division; division; Floating-Point Coprocessor;
                 floating-point unit; Highly Parallel Architecture;
                 Linpack benchmark; Microprocessor Chips; microprocessor
                 chips; Multiplication; multiplication; Multiplier Data
                 Path; Sparc systems; Sparc Systems; Sparc systems;
                 Square root; square root; Subtraction; subtraction;
                 TMS390C601 integer unit; TMS390C602A; TMS390C602A
                 floating-point coprocessor; TMS390C602A floating-point
                 unit; two-; Two-chip configuration",
  meetingabr =   "First Annu Hot Chips Symp",
  meetingaddress = "Palo Alto, CA, USA",
  meetingdate =  "Jun 26--27 1989",
  meetingdate2 = "06/26--27/89",
  sponsor =      "IEEE Computer Soc, Palo Alto, CA, USA",
  thesaurus =    "Digital arithmetic; Microprocessor chips",
  treatment =    "P Practical",
}

@TechReport{Demshki:2000:DII,
  author =       "Michael Demshki and Melvin Benedict and Dong Wei and
                 Tomm Aldridge",
  title =        "Designing Interoperability into {IA-64} Systems:
                 {DIG64} Guidelines",
  type =         "Technical Report",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "56",
  year =         "2000",
  bibdate =      "Fri Jan 05 10:53:56 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/idfdIG2/",
  acknowledgement = ack-nhfb,
}

@Book{Dewar:1990:MPV,
  author =       "Robert B. K. Dewar and Matthew Smosna",
  title =        "Microprocessors: a programmer's view",
  publisher =    pub-MCGRAW-HILL,
  address =      pub-MCGRAW-HILL:adr,
  pages =        "xvii + 462",
  year =         "1990",
  ISBN =         "0-07-016638-2, 0-07-016639-0 (soft)",
  ISBN-13 =      "978-0-07-016638-7, 978-0-07-016639-4 (soft)",
  LCCN =         "????",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  annote =       "Includes bibliographical references. Microprocessors
                 --- Introduction to the 80386 --- Addressing and memory
                 on the 80386 --- Tasking, virtual memory, and
                 exceptions to the 80386 --- Microprocessors and
                 floating-point arithmetic --- 68030 user programming
                 model --- 68030 supervisor state --- Introduction to
                 RISC architectures --- MIPS processors --- SPARC
                 architecture --- Intel i860 --- IBM RISC chips ---
                 INMOS transputer - - Future of microprocessor design.",
  keywords =     "Microprocessors --- Programming.",
}

@Article{Diefendorff:1994:EPA,
  author =       "Keith Diefendorff and Rich Oehler and Ron Hochsprung",
  title =        "Evolution of the {PowerPC} Architecture",
  journal =      j-IEEE-MICRO,
  volume =       "14",
  number =       "2",
  pages =        "34--49",
  month =        apr,
  year =         "1994",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.272836",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  abstract =     "Building on the POWER architecture to support a new
                 generation of high-performance, low-cost computers",
  acknowledgement = ack-nhfb,
  classcodes =   "C5220 (Computer architecture)",
  corpsource =   "Motorola Inc., Austin, TX, USA",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "architecture; computer architecture; IBM's POWER;
                 multiprocessor support; opcode assignments; PowerPC
                 architecture; programming model; reduced instruction
                 set computing; RISC architecture",
  treatment =    "P Practical",
}

@Article{Diefendorff:2000:AEP,
  author =       "Keith Diefendorff and Pradeep K. Dubey and Ron
                 Hochsprung and Hunter Scales",
  title =        "{AltiVec} Extension to {PowerPC} Accelerates Media
                 Processing",
  journal =      j-IEEE-MICRO,
  volume =       "20",
  number =       "2",
  pages =        "85--95",
  month =        mar # "\slash " # apr,
  year =         "2000",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.848475",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.computer.org/micro/mi2000/;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  URL =          "http://dlib.computer.org/mi/books/mi2000/pdf/m2085.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}

@Misc{Ditzel:1992:SVA,
  author =       "David Roger Ditzel",
  title =        "{SPARC} Version 9: adding 64-bit addressing and
                 robustness to an existing {RISC} architecture",
  publisher =    pub-UNIV-VIDEO-COMM,
  address =      pub-UNIV-VIDEO-COMM:adr,
  year =         "1992",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "Video sponsored by Sun Microsystems Laboratories, Inc.
                 Includes bibliographical references (on container for
                 videocassette). Recorded on Sept. 18, 1992.\par

                 From the videocassette container: ``SPARC started as a
                 32-bit RISC Instruction Set Architecture. This talk
                 describes the evolution of SPARC to a full 64-bit
                 architecture, and the design decisions that drove those
                 changes. In addition to extending the address range, a
                 number of changes were made to better support
                 compilers, operating systems, superscalar
                 implementations, context switching, and fault tolerant
                 systems.''",
  series =       "Leaders in computer science and electrical
                 engineering",
  acknowledgement = ack-nhfb,
  keywords =     "computer architecture",
}

@TechReport{Doran:1999:EFI,
  author =       "Mark Doran",
  title =        "{Extensible Firmware Interface}: booting the new
                 generation of {Intel Architecture} platforms",
  type =         "Technical report",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "45",
  day =          "1",
  month =        sep,
  year =         "1999",
  bibdate =      "Fri Jan 05 10:58:29 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/downloads/IDFEFI.htm",
  acknowledgement = ack-nhfb,
}

@Article{Dorweiler:1997:DMC,
  author =       "P. J. Dorweiler and F. E. Moore and D. D. Josephson
                 and G. T. Colon-Bonet",
  title =        "Design Methodologies and Circuit Design Trade-Offs for
                 the {HP PA 8000} Processor",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "48",
  number =       "4",
  pages =        "16--21",
  month =        aug,
  year =         "1997",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Wed Mar 25 15:17:10 MST 1998",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.hp.com/hpj/97aug/au97a2.htm",
  abstract =     "The increasing demands for greater processor
                 performance to remain competitive in today's computer
                 market necessitate careful attention to the methods
                 used in designing processors to achieve these
                 performance goals. Processor designs are increasing in
                 complexity to meet performance goals, with such
                 features as out-of-order execution and super-scalar
                 operation. Design cycles are decreasing in length, so
                 design quality must increase as well. All of these
                 factors call for new design techniques to ensure
                 continued success. This paper presents some of the
                 design methodologies and choices used in the design of
                 the HP PA 8000 CPU, the first HP processor to implement
                 the PA-RISC 2.0 architecture and the first capable of
                 64-bit operation. The various design methods used in
                 the PA 8000, specific design techniques for the new
                 packaging technology used, the clock distribution
                 scheme, and cross-chip signal integrity issues are
                 discussed. We also present some of the new tools and
                 techniques employed by HP to ensure a high level of
                 quality on first silicon, based in large part on our
                 experiences with previous PA-RISC microprocessor
                 designs.",
  acknowledgement = ack-nhfb,
  classification = "B0170J (Product packaging); B1130B (Computer-aided
                 circuit analysis and design); B1265B (Logic circuits);
                 B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5210B (Computer-aided logic
                 design); C7410D (Electronic engineering computing)",
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
  keywords =     "circuit design trade-offs; clock distribution scheme;
                 design methodologies; design quality; HP PA 8000 CPU;
                 HP PA 8000 processor; logic CAD; microprocessor chips;
                 out-of-order execution; PA-RISC 2.0 architecture;
                 packaging; performance goals; processor performance;
                 signal integrity issues; super-scalar operation",
  treatment =    "A Application; P Practical",
}

@TechReport{Doshi:1999:UIA,
  author =       "Gautam Doshi",
  title =        "Understanding the {IA-64} Architecture",
  type =         "Technical report",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "65",
  day =          "31",
  month =        aug,
  year =         "1999",
  bibdate =      "Fri Jan 05 09:43:01 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/idfisa/index.htm",
  acknowledgement = ack-nhfb,
}

@TechReport{Doshi:2000:IPP,
  author =       "{Intel Corporation}",
  title =        "{Itanium} Processor Program Update",
  type =         "Technical report",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  year =         "2000",
  bibdate =      "Fri Jan 05 09:45:51 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/IDFprogram_progress/",
  acknowledgement = ack-nhfb,
}

@InProceedings{Dubey:1997:ATA,
  author =       "Pradeep Dubey",
  title =        "Afternoon Tutorial: Architectural and Design
                 Implications of Mediaprocessing",
  crossref =     "IEEE:1997:HCI",
  pages =        "??--??",
  year =         "1997",
  bibdate =      "Mon Jan 08 16:33:30 2001",
  bibsource =    "ftp://www.hotchips.org/pub/hotc7to11cd/hc97/pdf_images/hc97nav.txt;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
}

@TechReport{Dubey:1998:ADI,
  author =       "Pradeep Dubey",
  title =        "Architectural and Design Implications of
                 Mediaprocessing",
  type =         "Technical Report",
  institution =  pub-IBM,
  address =      pub-IBM:adr,
  day =          "20",
  month =        may,
  year =         "1998",
  bibdate =      "Tue Jan 09 14:22:55 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.research.ibm.com/people/p/pradeep/media_tutorial/",
  acknowledgement = ack-nhfb,
}

@Article{Dulong:1998:IAW,
  author =       "Carole Dulong",
  title =        "The {IA-64} Architecture at Work",
  journal =      j-COMPUTER,
  volume =       "31",
  number =       "7",
  pages =        "24--32",
  month =        jul,
  year =         "1998",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Tue Jul 7 07:46:32 MDT 1998",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/computer1990.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://dlib.computer.org/co/books/co1998/pdf/r7024.pdf;
                 http://www.computer.org/computer/co1998/r7024abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
}

@Book{Edwards:1991:OTC,
  author =       "Janet Edwards",
  title =        "Occam and the transputer, current developments",
  publisher =    pub-IOS,
  address =      pub-IOS:adr,
  pages =        "viii + 247",
  year =         "1991",
  ISBN =         "90-5199-063-4",
  ISBN-13 =      "978-90-5199-063-8",
  ISSN =         "0925-4986",
  LCCN =         "QA76.73.O2 W67 1991 Bar",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  price =        "UK\pounds47.00",
  series =       "Transputer and occam engineering series",
  acknowledgement = ack-nhfb,
  keywords =     "occam (computer program language) congresses;
                 transputers --- congresses",
}

@Book{Ellison:1990:UOT,
  author =       "D. Ellison",
  title =        "Understanding {Occam} and the transputer: through
                 complete, working programs",
  publisher =    "Sigma",
  address =      "London, UK",
  pages =        "v + 204",
  year =         "1990",
  ISBN =         "1-85058-206-8 (paperback)",
  ISBN-13 =      "978-1-85058-206-9 (paperback)",
  LCCN =         "QA76.73.O3E54 1990",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "occam (computer program language)",
}

@Book{Engel:1999:PJV,
  author =       "Joshua Engel",
  title =        "Programming for the {Java} Virtual Machine",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "352",
  year =         "1999",
  ISBN =         "0-201-30972-6",
  ISBN-13 =      "978-0-201-30972-0",
  LCCN =         "QA76.73.J38E543 1999",
  bibdate =      "Tue May 11 08:13:32 1999",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$39.95",
  acknowledgement = ack-nhfb,
}

@Book{Evans:1999:ARA,
  author =       "James S. Evans and Richard H. Eckhouse",
  title =        "{Alpha RISC} architecture for programmers",
  publisher =    pub-PHPTR,
  address =      pub-PHPTR:adr,
  pages =        "xviii + 426",
  year =         "1999",
  ISBN =         "0-13-081438-5",
  ISBN-13 =      "978-0-13-081438-8",
  LCCN =         "QA 76.8 A176 E93 1999",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "Alpha (microprocessor); assembler language (computer
                 program language); computer architecture; RISC
                 microprocessors",
}

@Book{Farquhar:1994:MPH,
  author =       "Erin Farquhar and Philip Bunce",
  title =        "The {MIPS} programmer's handbook",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  pages =        "viii + 408",
  year =         "1994",
  ISBN =         "1-55860-297-6",
  ISBN-13 =      "978-1-55860-297-7",
  LCCN =         "QA76.6 .F375 1994",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "embedded computer systems --- programming; MIPS1
                 (microprocessor)",
}

@Book{Fleming:1988:PPC,
  author =       "P. J. Fleming",
  title =        "Parallel processing in control: the transputer and
                 other architectures",
  volume =       "38",
  publisher =    pub-PEREGRINUS,
  address =      pub-PEREGRINUS:adr,
  pages =        "xiv + 243",
  year =         "1988",
  ISBN =         "0-86341-136-3",
  ISBN-13 =      "978-0-86341-136-6",
  LCCN =         "TJ223.M53 P37 1988",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  series =       "IEE control engineering series",
  acknowledgement = ack-nhfb,
  keywords =     "digital control systems; parallel processing
                 (electronic computers)",
}

@Article{Fong:1997:SII,
  author =       "J. C. Fong and Hoi-Kuen Chan and M. D. Kruckenberg",
  title =        "Solving {IC} Interconnect Routing for an Advanced
                 {PA-RISC} Processor",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "48",
  number =       "4",
  pages =        "40--45",
  month =        aug,
  year =         "1997",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Wed Mar 25 15:17:10 MST 1998",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.hp.com/hpj/97aug/au97a5.htm;
                 http://www.hp.com/hpj/97aug/tc-08-97.htm",
  abstract =     "This paper discusses some important new block routing
                 technologies that were required for the HP PA 8000
                 processor chip. These technologies are implemented in a
                 new block routing system called PA Route.",
  acknowledgement = ack-nhfb,
  classification = "B1130B (Computer-aided circuit analysis and design);
                 B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C7410D (Electronic engineering
                 computing)",
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
  keywords =     "advanced PA-RISC processor; block routing
                 technologies; circuit layout CAD; Hewlett Packard
                 computers; HP PA 8000 processor chip; IC interconnect
                 routing; microprocessor chips; PA Route",
  treatment =    "P Practical",
}

@Article{Frink:1992:HDL,
  author =       "Craig R. Frink and Robert J. Hammond and John A.
                 Dykstal and Don C. {Soltis, Jr.}",
  title =        "High-performance designs for the low-cost {PA-RISC}
                 desktop",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "43",
  number =       "4",
  pages =        "55--63",
  month =        aug,
  year =         "1992",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Tue Mar 25 14:12:15 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "The paper presents the processor, memory, graphics,
                 multimedia, and built-in core I/O design of the new HP
                 9000 Models 705 and 710 entry-level, scalable, PA-RISC
                 workstations. The use of a buffered CPU/memory
                 interconnect is important for scaling the
                 high-frequency, high-performance processor design to
                 the entry-level desktop.",
  acknowledgement = ack-nhfb,
  affiliation =  "Hewlett Packard Co., Palo Alto, CA, USA",
  classcodes =   "C5430 (Microcomputers)",
  classification = "C5430 (Microcomputers)",
  corpsource =   "Hewlett Packard Co., Palo Alto, CA, USA",
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
  keywords =     "Buffered CPU/memory interconnect; buffered CPU/memory
                 interconnect; Built-in core I/O design; built-in core
                 I/O design; computer evaluation; desktop; entry-level;
                 Entry-level desktop; Graphics; graphics; Hewlett
                 Packard computers; HP 9000 Model 710; HP 9000 Models
                 705; instruction set computing; Memory; memory;
                 Multimedia; multimedia; PA-RISC; PA-RISC workstations;
                 Processor; processor; reduced; workstations",
  thesaurus =    "Computer evaluation; Hewlett Packard computers;
                 Reduced instruction set computing; Workstations",
  treatment =    "P Practical; R Product Review",
}

@TechReport{Fuller:1998:MAT,
  author =       "Sam Fuller",
  title =        "{Motorola}'s {AltiVec} Technology",
  type =         "Technical Report",
  number =       "ALTIVECWP/D",
  institution =  pub-MOTOROLA,
  address =      pub-MOTOROLA:adr,
  pages =        "4",
  year =         "1998",
  bibdate =      "Tue Jan 09 11:25:58 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://a1888.g.akamai.net/7/1888/787/83ade987b85512/www.motorola.com/SPS/PowerPC/teksupport/teklibrary/papers/altivec_wp.pdf",
  acknowledgement = ack-nhfb,
}

@Book{Furber:2000:ASC,
  author =       "Steve Furber",
  title =        "{ARM} System-on-Chip Architecture",
  publisher =    pub-AW-LONGMAN,
  address =      pub-AW-LONGMAN:adr,
  edition =      "Second",
  pages =        "xii + 449",
  year =         "2000",
  ISBN =         "0-201-67519-6",
  ISBN-13 =      "978-0-201-67519-1",
  LCCN =         "QA76.5 .F8643 2000",
  bibdate =      "Tue Jan 09 13:20:08 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "Also available in Japanese translation, {\em ARM
                 Processor}, C Q Publishing Co., Ltd. ISBN
                 4-7898-3351-8.",
  price =        "US\$39.95",
  acknowledgement = ack-nhfb,
}

@Article{Gleason:1992:VCL,
  author =       "Craig A. Gleason and Leith Johnson and Steven T.
                 Mangelsdorf and Thomas O. Meyer and Mark A. Forsyth",
  title =        "{VLSI} circuits for low-end and midrange {PA-RISC}
                 computers",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "43",
  number =       "4",
  pages =        "12--22",
  month =        aug,
  year =         "1992",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Tue Mar 25 14:12:15 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "The major VLSI chips for the HP 9000 Series 700
                 workstations include a central processing unit with
                 577000 transistors, a floating-point coprocessor with
                 640000 transistors, and a memory and input/output
                 controller with 185000 transistors.",
  acknowledgement = ack-nhfb,
  affiliation =  "Hewlett Packard Co., Palo Alto., CA, USA",
  classcodes =   "B1265F (Microprocessors and microcomputers); B1265D
                 (Memory circuits); C5130 (Microprocessor chips); C5430
                 (Microcomputers); C5220 (Computer architecture); C5320G
                 (Semiconductor storage)",
  classification = "B1265D (Memory circuits); B1265F (Microprocessors
                 and microcomputers); C5130 (Microprocessor chips);
                 C5220 (Computer architecture); C5320G (Semiconductor
                 storage); C5430 (Microcomputers)",
  corpsource =   "Hewlett Packard Co., Palo Alto., CA, USA",
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
  keywords =     "Central processing unit; central processing unit;
                 computer architecture; coprocessor; floating-point;
                 Floating-point coprocessor; Hewlett Packard computers;
                 HP 9000 Series 700; HP 9000 Series 700 workstations;
                 Input/output controller; input/output controller;
                 integrated; Memory; memory; memory circuits;
                 microprocessor chips; PA-RISC computers; VLSI; VLSI
                 circuits; workstations",
  thesaurus =    "Computer architecture; Hewlett Packard computers;
                 Integrated memory circuits; Microprocessor chips; VLSI;
                 Workstations",
  treatment =    "P Practical",
}

@Book{Goldenberg:1994:OAI,
  author =       "Ruth E. Goldenberg and Saro Saravanan",
  title =        "{OpenVMS AXP} internals and data structures: version
                 1.5",
  publisher =    pub-DP,
  address =      pub-DP:adr,
  pages =        "xxvi + 1672",
  year =         "1994",
  ISBN =         "1-55558-120-X",
  ISBN-13 =      "978-1-55558-120-6",
  LCCN =         "QA76.76.O63 G6378 1994",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "openvms; operating systems (computers)",
}

@Book{Goodman:1993:PVC,
  author =       "James (James L.) Goodman and Karen Miller",
  title =        "A programmer's view of computer architecture: with
                 Assembly Language examples from the {MIPS RISC}
                 architecture",
  publisher =    pub-SAUNDERS,
  address =      pub-SAUNDERS:adr,
  pages =        "xi + 402",
  year =         "1993",
  ISBN =         "0-03-097219-1",
  ISBN-13 =      "978-0-03-097219-5",
  LCCN =         "QA76.9.A73 G63 1993",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "computer architecture; Reduced Instruction Set
                 Computers (RISC)",
}

@Book{Graham:1990:TH,
  author =       "Ian Graham and Tim King",
  title =        "The transputer handbook",
  publisher =    pub-PHI,
  address =      pub-PHI:adr,
  pages =        "xi + 200",
  year =         "1990",
  ISBN =         "0-13-929134-2",
  ISBN-13 =      "978-0-13-929134-0",
  LCCN =         "TK7895.T73 G73 1990",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "transputers",
}

@InProceedings{Greenley:1995:UNG,
  author =       "D. Greenley and others",
  title =        "{UltraSPARC}: the next generation superscalar 64-bit
                 {SPARC}",
  crossref =     "IEEE:1995:DPC",
  pages =        "442--451",
  month =        mar,
  year =         "1995",
  bibdate =      "Thu Apr 2 08:38:35 1998",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-sfo # " and " # ack-nhfb,
}

@Article{Grimes:1989:IIP,
  author =       "Jack D. Grimes and Les Kohn and Rajeev Bharadhwaj",
  title =        "The {Intel i860} 64-Bit Processor: a General-Purpose
                 {CPU} with {3D} Graphics Capabilities",
  journal =      j-IEEE-CGA,
  volume =       "9",
  number =       "4",
  pages =        "85--94",
  month =        jul,
  year =         "1989",
  CODEN =        "ICGADZ",
  DOI =          "http://dx.doi.org/10.1109/38.31467",
  ISSN =         "0272-1716 (print), 1558-1756 (electronic)",
  ISSN-L =       "0272-1716",
  bibdate =      "Sat Jan 25 06:42:48 MST 1997",
  bibsource =    "Compendex database; Graphics/siggraph/89.bib;
                 http://www.math.utah.edu/pub/tex/bib/ieeecga.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  affiliation =  "Intel Corp, Santa Clara, CA, USA",
  annote =       "This chip and others like it are changing the shape of
                 the computer industry. General purpose CPU optimized
                 for graphics, with multiple processing units on board.
                 Yesterday's supercomputer on a chip.",
  classification = "722; 723",
  fjournal =     "IEEE Computer Graphics and Applications",
  journal-URL =  "http://www.computer.org/portal/web/csdl/magazines/cga",
  journalabr =   "IEEE Comput Graphics Appl",
  keywords =     "3D Graphics Rendering Instructions; 3D Graphics
                 Workstations; Computer Graphics; Computer Systems,
                 Digital --- Parallel Processing; Computers, Personal;
                 Data Processing --- Natural Sciences Applications; Fine
                 Grained Parallelism; Interactive Scientific
                 Visualization; parallel processing; Three Dimensional
                 Graphics",
}

@Article{Halfhill:1998:II,
  author =       "Tom R. Halfhill",
  title =        "Inside {IA-64}",
  journal =      j-BYTE,
  volume =       "23",
  number =       "6",
  pages =        "81--??",
  month =        jun,
  year =         "1998",
  CODEN =        "BYTEDJ",
  ISSN =         "0360-5280",
  ISSN-L =       "0360-5280",
  bibdate =      "Thu Dec 10 19:10:07 1998",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/byte1995.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "Behind Intel\slash HP's chip for tomorrow are ideas
                 from yesterday, like long instruction words and
                 parallel processing.",
  acknowledgement = ack-nhfb,
  fjournal =     "BYTE Magazine",
}

@Article{Hangal:1999:PAV,
  author =       "Sudheendra Hangal and Mike O'Connor",
  title =        "Performance Analysis and Validation of the {picoJava}
                 Processor",
  journal =      j-IEEE-MICRO,
  volume =       "19",
  number =       "3",
  pages =        "66--72",
  month =        may # "\slash " # jun,
  year =         "1999",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.768505",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.computer.org/micro/mi1999/;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  URL =          "http://dlib.computer.org/mi/books/mi1999/pdf/m3066.pdf;
                 http://www.computer.org/micro/mi1999/m3066abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  xxpages =      "66--72",
}

@Article{Hansen:1992:NOP,
  author =       "R. C. Hansen",
  title =        "New optimizations for {PA-RISC} compilers",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "43",
  number =       "3",
  pages =        "15--23",
  month =        jun,
  year =         "1992",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Tue Mar 25 14:12:15 MST 1997",
  bibsource =    "Compiler/Compiler.Lins.bib;
                 http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "The first release of the PA-RISC 1.1 architecture is
                 found in the HP 9000 Series 700 workstations running
                 HP-UX 8.05. This article presents a brief discussion
                 about the architecture extensions, followed by an
                 overview of the enhancements made to the compilers to
                 exploit these extensions. In addition to enhancements
                 made to the compilers to support architecture
                 extensions, there were a number of enhancements to
                 traditional optimizations performed by the compilers
                 that improve application performance, independent of
                 the underlying architecture. These generic enhancements
                 are also covered. Finally, performance data and an
                 analysis are presented.",
  acknowledgement = ack-nhfb,
  affiliation =  "Hewlett--Packard Co., Palo Alto, CA, USA",
  classcodes =   "C6150C (Compilers, interpreters and other processors);
                 C6140D (High level languages); C5220 (Computer
                 architecture)",
  classification = "C5220 (Computer architecture); C6140D (High level
                 languages); C6150C (Compilers, interpreters and other
                 processors)",
  corpsource =   "Hewlett--Packard Co., Palo Alto, CA, USA",
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
  keywords =     "700 workstations; Architecture extensions;
                 architecture extensions; computing; evaluation; Hewlett
                 Packard computers; HP 9000 Series; HP 9000 Series 700
                 workstations; HP-UX 8.05; optimisation; PA-RISC 1.1
                 architecture; PA-RISC compilers; performance;
                 Performance data; performance data; program compilers;
                 reduced instruction set",
  thesaurus =    "Hewlett Packard computers; Optimisation; Performance
                 evaluation; Program compilers; Reduced instruction set
                 computing",
  treatment =    "P Practical",
}

@Book{Harp:1989:TA,
  author =       "Gordon Harp",
  title =        "Transputer applications",
  publisher =    pub-PITMAN,
  address =      pub-PITMAN:adr,
  pages =        "x + 273",
  year =         "1989",
  ISBN =         "0-273-02852-9 (paperback)",
  ISBN-13 =      "978-0-273-02852-9 (paperback)",
  LCCN =         "QA76.6 .T722 1989 Bar",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "parallel processing (electronic computers)",
}

@Book{Heath:1994:PPC,
  author =       "Steve Heath",
  title =        "{PowerPC}: a practical companion",
  publisher =    pub-BUTTERWORTH-HEINEMANN,
  address =      pub-BUTTERWORTH-HEINEMANN:adr,
  pages =        "x + 388",
  year =         "1994",
  ISBN =         "0-7506-1801-9 (paperback)",
  ISBN-13 =      "978-0-7506-1801-4 (paperback)",
  LCCN =         "QA76.8.P67 H68 1994",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  acknowledgement = ack-nhfb,
  keywords =     "microprocessors design",
}

@Book{Heinrich:1994:MRM,
  author =       "Joe Heinrich",
  title =        "{MIPS R4000} Microprocessor User's Manual",
  publisher =    "MIPS Technologies, Inc.",
  address =      "2011 N. Shoreline Blvd., Mountain View, CA
                 94039-7311",
  edition =      "Second",
  pages =        "xxx + 724",
  year =         "1994",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Sat Jan 06 09:09:01 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.mips.com/Documentation/R4400_Uman_book_Ed2.pdf",
  acknowledgement = ack-nhfb,
}

@Book{Hennessy:1990:CAQ,
  author =       "John L. Hennessy and David A. Patterson",
  title =        "Computer Architecture\emdash {A} Quantitative
                 Approach",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  pages =        "xxviii + 594",
  year =         "1990",
  ISBN =         "1-55860-069-8",
  ISBN-13 =      "978-1-55860-069-0",
  LCCN =         "QA76.9.A73 P377 1990",
  bibdate =      "Mon Jan 31 08:47:46 1994",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
}

@Book{Hennessy:1994:COD,
  author =       "John L. Hennessy and David A. Patterson",
  title =        "Computer Organization and Design\emdash The
                 Hardware\slash Software Interface",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adrnew,
  pages =        "xxiv + 648",
  year =         "1994",
  ISBN =         "1-55860-281-X",
  ISBN-13 =      "978-1-55860-281-6",
  LCCN =         "QA76.9 .C643 P37 1994",
  bibdate =      "Wed Feb 2 00:08:32 1994",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$74.75",
  acknowledgement = ack-nhfb,
}

@Book{Hennessy:1996:CAQ,
  author =       "John L. Hennessy and David A. Patterson",
  title =        "Computer Architecture\emdash {A} Quantitative
                 Approach",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  edition =      "Second",
  pages =        "xxiii + 760 + A-77 + B-47 + C-26 + D-26 + E-13 + R-16
                 + I-14",
  year =         "1996",
  ISBN =         "1-55860-329-8",
  ISBN-13 =      "978-1-55860-329-5",
  LCCN =         "QA76.9.A73P377 1995",
  bibdate =      "Mon May 20 10:01:59 2002",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$69.95",
}

@Book{Hennessy:1997:COH,
  author =       "John L. Hennessy and David A. Patterson",
  title =        "Computer Organization: The Hardware\slash Software
                 Interface",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adrnew,
  edition =      "Second",
  pages =        "1000",
  year =         "1997",
  ISBN =         "1-55860-428-6 (hardcover), 1-55860-491-X (softcover)",
  ISBN-13 =      "978-1-55860-428-5 (hardcover), 978-1-55860-491-9
                 (softcover)",
  LCCN =         "QA76.9.C643H46 1997",
  bibdate =      "Thu Sep 11 07:05:47 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$78.95",
  acknowledgement = ack-nhfb,
}

@Book{Hennessy:2002:CAQ,
  author =       "John L. Hennessy and David A. Patterson",
  title =        "Computer Architecture\emdash {A} Quantitative
                 Approach",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  edition =      "Third",
  pages =        "xxi + 883 + A-87 + B-42 + C-1 + D-1 + E-1 + F-1 + G-1
                 + H-1 + I-1 + R-22 + I-44",
  year =         "2002",
  ISBN =         "1-55860-596-7",
  ISBN-13 =      "978-1-55860-596-1",
  LCCN =         "????",
  bibdate =      "Fri May 31 15:46:29 2002",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$89.95",
  URL =          "http://www.mkp.com/books_catalog/catalog.asp?ISBN=1-55860-596-7;
                 http://www.mkp.com/CA3",
}

@Book{Hinton:1993:THS,
  author =       "Jeremy Hinton and Alan Pinder",
  title =        "Transputer hardware and system design",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "x + 286",
  year =         "1993",
  ISBN =         "0-13-953001-0",
  ISBN-13 =      "978-0-13-953001-2",
  LCCN =         "TK7895.T73 H56 1993 Bar",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "system design; transputers",
}

@Book{Holt:1988:BRE,
  author =       "Wayne E. Holt and Steven M. Cooper",
  title =        "Beyond {RISC}: an essential guide to {Hewlet-Packard}
                 precision architecture",
  publisher =    "Software Research Northwest",
  address =      "Vashon Island, WA",
  pages =        "xvii + 342",
  year =         "1988",
  ISBN =         "0-9618813-7-2",
  ISBN-13 =      "978-0-9618813-7-5",
  LCCN =         "QA 76.8 H66 B49 1988",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "Hewlett--Packard computers; HP 3000 (computer)",
}

@Article{Homewood:1987:ITT,
  author =       "Mark Homewood and David May and David Shepherd and
                 Roger Shepherd",
  title =        "The {IMS} {T800} transputer",
  journal =      j-IEEE-MICRO,
  volume =       "7",
  number =       "5",
  pages =        "10--26",
  month =        oct,
  year =         "1987",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/MM.1987.305012",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database;
                 garbo.uwasa.fi:/pc/doc-soft/fpbiblio.txt;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Parallel/transputer.bib; Science Citation Index
                 database (1980--2000)",
  acknowledgement = ack-nj # " and " # ack-nhfb,
  affiliationaddress = "Inmos Ltd, Bristol, Engl",
  classcodes =   "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips)",
  classification = "714; 722; 723; 921",
  corpsource =   "Inmos Ltd., Bristol, UK",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "architecture; capability; communication links;
                 computer architecture; computer graphics; computer
                 programming languages; computers, microcomputer;
                 Design; floating-point arithmetic; floating-point unit
                 design; graphics; IMS T800 transputer; integrated
                 circuits, VLSI; microprocessor chips; performance;
                 scientific computer; supercomputers; telecommunication
                 links",
  treatment =    "P Practical; R Product Review",
}

@Manual{HP:1994:PRAa,
  title =        "{PA-RISC 1.1} Architecture and Instruction Set
                 Reference Manual",
  organization = pub-HP,
  edition =      "Third",
  pages =        "424",
  month =        feb,
  year =         "1994",
  bibdate =      "Tue Jan 09 11:56:43 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "HP Part Number: 09740-90039. Previous editions
                 November 1990 and September 1992.",
  URL =          "http://devresource.hp.com/devresource/Docs/Refs/PA1_1;
                 http://devresource.hp.com/devresource/Docs/Refs/PA1_1/acd.pdf;
                 http://devresource.hp.com/devresource/Docs/Refs/PA1_1/pdf.html",
  abstract =     pub-HP:adr,
  acknowledgement = ack-nhfb,
}

@Misc{HP:1994:PRAb,
  author =       "{Hewlett--Packard Corporation}",
  title =        "{PA-RISC 2.0} Architecture Reference",
  howpublished = "World-Wide Web document.",
  year =         "1994",
  bibdate =      "Tue Jan 09 11:56:43 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "See \cite{Kane:1996:PRA} for a printed version.",
  URL =          "http://devresource.hp.com/devresource/Docs/Refs/PA2_0/",
  acknowledgement = ack-nhfb,
}

@Manual{HP:2000:IAD,
  title =        "{IA-64} Architecture Disclosures",
  organization = pub-HP,
  address =      pub-HP:adr,
  pages =        "??",
  year =         "2000",
  bibdate =      "Tue Jan 09 12:53:32 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.ia64.hp.com/infolibrary/whitepapers/ia64_arch_wp.pdf",
  acknowledgement = ack-nhfb,
}

@Manual{HP:2000:OIA,
  title =        "Overview of {IA-64} Architecture",
  organization = pub-HP,
  address =      pub-HP:adr,
  pages =        "10",
  year =         "2000",
  bibdate =      "Tue Jan 09 12:53:32 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "This document is part of the HP-UX 11.x Software
                 Transition Kit.",
  URL =          "http://devresource.hp.com/STK/partner/ia64bkgnd.pdf",
  acknowledgement = ack-nhfb,
}

@Book{Hsu:2001:CAS,
  author =       "John Y. Hsu",
  title =        "Computer Architecture: Software Aspects, Coding,
                 Hardware",
  publisher =    pub-CRC,
  address =      pub-CRC:adr,
  pages =        "416 (est.)",
  year =         "2001",
  ISBN =         "0-8493-1026-1",
  ISBN-13 =      "978-0-8493-1026-3",
  LCCN =         "A76.9.A73 H758 2001",
  bibdate =      "Fri Jan 19 15:47:59 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$89.95, UK\pounds 59.99",
  acknowledgement = ack-nhfb,
  keywords =     "Compaq/DEC Alpha; floating-point arithmetic; Intel
                 x86; Java Virtual Machine; multimedia instructions;
                 Pentium",
  libnote =      "Not yet in my library.",
}

@Article{Huck:2000:IIA,
  author =       "Jerry Huck and Dale Morris and Jonathan Ross and Allan
                 Knies and Hans Mulder and Rumi Zahir",
  title =        "Introducing the {IA-64} Architecture",
  journal =      j-IEEE-MICRO,
  volume =       "20",
  number =       "5",
  pages =        "12--23",
  month =        sep # "\slash " # oct,
  year =         "2000",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.877947",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Tue Oct 10 06:00:40 MDT 2000",
  bibsource =    "http://www.computer.org/micro/mi2000/;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://dlib.computer.org/mi/books/mi2000/pdf/m5012.pdf;
                 http://www.computer.org/micro/mi2000/m5012abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}

@Book{Hull:1994:PPT,
  author =       "M. E. C. Hull and Danny Crookes and P. J. Sweeney",
  title =        "Parallel processing: the transputer and its
                 applications",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "xii + 328",
  year =         "1994",
  ISBN =         "0-201-62755-8",
  ISBN-13 =      "978-0-201-62755-8",
  LCCN =         "QA76.58 .P3783 1994",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  series =       "International computer science series",
  acknowledgement = ack-nhfb,
  keywords =     "parallel processing (electronic computers);
                 transputers",
}

@Book{Inmos:1988:TIS,
  author =       "{INMOS Limited}",
  title =        "Transputer instruction set: a compiler writer's
                 guide",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "vii + 167",
  year =         "1988",
  ISBN =         "0-13-929100-8",
  ISBN-13 =      "978-0-13-929100-5",
  LCCN =         "QA76.76.C65 T73 1988 Sci-Eng",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "Includes indexes.",
  acknowledgement = ack-nhfb,
  keywords =     "compiling (electronic computers); transputers --
                 programming",
}

@Book{Inmos:1988:TRM,
  author =       "{INMOS Limited}",
  title =        "Transputer reference manual",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "xviii + 346",
  year =         "1988",
  ISBN =         "0-13-929001-X",
  ISBN-13 =      "978-0-13-929001-5",
  LCCN =         "TK7895.T73 T73 1988 Annex",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "Includes index. Bibliography: p. 315-324.",
  acknowledgement = ack-nhfb,
  keywords =     "occam (computer program language); transputers",
}

@Book{Inmos:1989:TD,
  author =       "{INMOS Limited}",
  title =        "Transputer databook",
  publisher =    "INMOS Limited",
  address =      "Colorado Springs, CO, USA",
  edition =      "Second",
  pages =        "xxii + 582",
  year =         "1989",
  LCCN =         "TK7895.T73 I55 1989 Sci-Eng",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "transputers --- handbooks, manuals, etc",
}

@Book{Inmos:1990:TDS,
  author =       "{INMOS Limited}",
  title =        "Transputer development system",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  edition =      "Second",
  pages =        "xv + 465",
  year =         "1990",
  ISBN =         "0-13-929068-0",
  ISBN-13 =      "978-0-13-929068-8",
  LCCN =         "TK 7895 T73 T69 1990",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "INMOS document number: 72 TRN 011 01.",
  acknowledgement = ack-nhfb,
  keywords =     "occam (computer program language); transputers",
}

@Book{Intel:1990:IBM,
  author =       "Intel",
  title =        "i860 64-bit Microprocessor Hardware Reference Manual",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  year =         "1990",
  ISBN =         "1-55512-106-3",
  ISBN-13 =      "978-1-55512-106-8",
  LCCN =         "TK7895.M5 I57662 1990",
  bibdate =      "Wed Dec 15 10:35:21 1993",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
}

@Book{Intel:1991:IBM,
  author =       "Intel",
  title =        "i860 64-bit Microprocessor Family Programmer's
                 Reference Manual",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  year =         "1991",
  ISBN =         "1-55512-135-7",
  ISBN-13 =      "978-1-55512-135-8",
  LCCN =         "QA76.8.I57 I44 1991",
  bibdate =      "Wed Dec 15 10:35:26 1993",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
}

@Book{Intel:1991:IKK,
  author =       "{Intel Corporation}",
  title =        "{i960 KA\slash KB} microprocessor programmer's
                 reference manual",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "various",
  year =         "1991",
  ISBN =         "1-55512-137-3",
  ISBN-13 =      "978-1-55512-137-2",
  LCCN =         "QA76.8.I2932 I29 1991",
  bibdate =      "Fri Jan 5 08:00:52 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "computer programming --- handbooks, manuals, etc;
                 Intel i960 (microprocessor) --- programming",
}

@Book{Intel:1991:IMM,
  author =       "{Intel Corporation}",
  title =        "{i960 MC} microprocessor reference manual",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "various",
  year =         "1991",
  ISBN =         "1-55512-136-5",
  ISBN-13 =      "978-1-55512-136-5",
  LCCN =         "QA76.8.I29284 I2 1991",
  bibdate =      "Fri Jan 5 08:00:52 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "computer programming; Intel 80960 (microprocessor);
                 microprocessors -- programming",
}

@Manual{Intel:1991:OIX,
  title =        "Overview of the {i860 XP} supercomputing
                 microprocessor",
  organization = pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "various",
  year =         "1991",
  bibdate =      "Fri Aug 30 08:01:51 MDT 1996",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 http://www.math.utah.edu/pub/tex/bib/super.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Intel i860 (Microprocessor)",
}

@Book{Intel:1992:IXM,
  author =       "{Intel Corporation}",
  title =        "{i860 XP} microprocessor hardware reference manual,
                 1992",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "various",
  year =         "1992",
  ISBN =         "1-55512-166-7",
  ISBN-13 =      "978-1-55512-166-2",
  LCCN =         "QA76.6.I39 1992",
  bibdate =      "Fri Jan 5 08:00:52 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "Intel i860 (microprocessor)",
}

@Book{Intel:1993:III,
  author =       "{Intel Corporation}",
  title =        "{i750}, {i860}, {i960} processors and related
                 products",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "various",
  year =         "1993",
  ISBN =         "1-55512-185-3",
  ISBN-13 =      "978-1-55512-185-3",
  LCCN =         "TK7895.M5 I57667 1993",
  bibdate =      "Fri Jan 5 08:00:52 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "Order number: 272084-002.",
  acknowledgement = ack-nhfb,
  keywords =     "microprocessors --- catalogs",
}

@Book{Intel:1993:PPU,
  author =       "{Intel Corporation}",
  title =        "{Pentium} processor user's manual",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "",
  year =         "1993",
  ISBN =         "1-55512-193-4 (vol. 1), 1-55512-194-2 (vol. 2)",
  ISBN-13 =      "978-1-55512-193-8 (vol. 1), 978-1-55512-194-5 (vol.
                 2)",
  LCCN =         "QA76.8.P46P465 1993 Library has: vol. 1-3",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "Contents: vol. 1. Pentium processor data abook ---
                 vol. 2. 82496 cache controller and 82491 cache SRAM
                 data book --- vol. 3. Architecture and programming
                 manual.",
  acknowledgement = ack-nhfb,
  keywords =     "cache memory; multiprocessors; Pentium
                 (microprocessor)",
}

@Book{Intel:1994:ICC,
  author =       "{Intel Corporation}",
  title =        "{i960 CA\slash CF} microprocessor user's manual",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "various",
  month =        mar,
  year =         "1994",
  ISBN =         "1-55512-224-8",
  ISBN-13 =      "978-1-55512-224-9",
  LCCN =         "QA76.8.I29282 I55 1994",
  bibdate =      "Fri Jan 5 08:00:52 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "Includes i960 Cx Microprocessor User's Guide
                 Instruction Set Quick Reference (18 p.) in pocket.",
  acknowledgement = ack-nhfb,
  keywords =     "computer programming --- handbooks, manuals, etc;
                 Intel i960 (microprocessor) --- programming handbooks,
                 manuals, etc",
}

@Book{Intel:1994:III,
  author =       "{Intel Corporation}",
  title =        "{i750}, {i860}, {i960} processors and related
                 products",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "various",
  year =         "1994",
  ISBN =         "1-55512-217-5",
  ISBN-13 =      "978-1-55512-217-1",
  LCCN =         "TK7895.M5 I588 1994 Sci-Eng",
  bibdate =      "Fri Jan 5 08:00:52 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "Order number 272084-003.",
  acknowledgement = ack-nhfb,
  keywords =     "microprocessors --- catalogs",
}

@Book{Intel:1994:PPU,
  author =       "{Intel Corporation}",
  title =        "{Pentium} processor user's manual",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "various",
  year =         "1994",
  ISBN =         "1-55512-222-1 (vol. 2: paperback), 1-55512-221-3 (vol.
                 1: paperback)",
  ISBN-13 =      "978-1-55512-222-5 (vol. 2: paperback),
                 978-1-55512-221-8 (vol. 1: paperback)",
  LCCN =         "QA76.8.P46 P46 1994",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "Order numbers 241428, 241429, and 241430. Contents:
                 vol. 1. Pentium processor data book --- vol. 2. 82496
                 cache controller and 82491 cache SRAM data book -- vol.
                 3. Architecture and programming manual.",
  acknowledgement = ack-nhfb,
  keywords =     "cache memory; multiprocessors; Pentium
                 (microprocessor)",
}

@Book{Intel:1995:PPF,
  author =       "{Intel Corporation}",
  title =        "{Pentium} processor family developer's manual",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "various",
  year =         "1995",
  LCCN =         "QA76.8.P46 P458 1995",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "Contents: vol. 1. Pentium processors --- vol. 2.
                 82496/82497/82498 cache controller and
                 82491/82492/82493 cache SRAM --- vol. 3. Architecture
                 and programming manual.",
  acknowledgement = ack-nhfb,
  keywords =     "cache memory; multiprocessors; Pentium
                 (microprocessor)",
}

@Book{Intel:1996:PPF,
  author =       "{Intel Corporation}",
  title =        "{Pentium pro} family developer's manual",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "various",
  year =         "1996",
  ISBN =         "1-55512-259-0 (vol. 1), 1-55512-260-4 (vol. 2),
                 1-55512-261-2 (vol. 3)",
  ISBN-13 =      "978-1-55512-259-1 (vol. 1), 978-1-55512-260-7 (vol.
                 2), 978-1-55512-261-4 (vol. 3)",
  LCCN =         "QA76.8.P46 P455 1996 LIBRARY HAS vol. 2",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "Three volumes: vol. 1: Specifications: order number
                 242690; vol. 2. Programmer's reference manual: order
                 number 242691; vol. 3. Operating system writer's guide:
                 order number 242692.",
  acknowledgement = ack-nhfb,
  keywords =     "cache memory; multiprocessors; Pentium
                 (microprocessor)",
}

@TechReport{Intel:1997:PIP,
  author =       "{Intel Corporation}",
  title =        "{Pentium II} Processor Performance Brief",
  type =         "Technical Report",
  number =       "XXX-001",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  month =        may,
  year =         "1997",
  bibdate =      "Fri Jan 05 09:11:07 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
}

@Book{Intel:1999:IAD,
  author =       "{Intel Corporation}",
  title =        "{IA-64} Application Developer's Architecture Guide",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "476",
  month =        may,
  year =         "1999",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Fri Jan 05 08:45:35 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/downloads/ADAG.pdf",
  acknowledgement = ack-nhfb,
}

@TechReport{Intel:2000:AIC,
  author =       "{Intel Corporation}",
  title =        "The Advantages of {IA-64} for Cache Server Software
                 Information for Software Developers and {IT} Managers",
  type =         "Technical report",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "5",
  year =         "2000",
  bibdate =      "Fri Jan 05 09:38:22 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/downloads/ia-64_cache2.htm",
  acknowledgement = ack-nhfb,
  alttitle =     "Cache Tech Brief for {Itanium} Processor Family
                 Architecture",
}

@TechReport{Intel:2000:DIG,
  author =       "{Intel Corporation}",
  title =        "Developer's Interface Guide for {IA-64} Servers",
  type =         "Technical report",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  year =         "2000",
  bibdate =      "Fri Jan 05 11:04:27 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "This document is a directory of pointers to white
                 papers on the DIG-64 (Developer's Interface Guide)
                 specifications.",
  URL =          "http://developer.intel.com/design/servers/dev_guides/content/doc_lib/index.htm",
  acknowledgement = ack-nhfb,
}

@Book{Intel:2000:IBL,
  author =       "{Intel Corporation}",
  title =        "{Itanium}-Based {Linux} Developer's Kit",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "????",
  year =         "2000",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Fri Jan 05 09:25:31 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/linux.htm",
  acknowledgement = ack-nhfb,
}

@Book{Intel:2000:IIAa,
  author =       "{Intel Corporation}",
  title =        "{Intel IA-64} Architecture Software Developer's
                 Manual: Volume 1: {IA-64} Application Architecture",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "216",
  month =        jan,
  year =         "2000",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Fri Jan 05 08:45:35 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/downloads/245317.htm",
  acknowledgement = ack-nhfb,
}

@Book{Intel:2000:IIAb,
  author =       "{Intel Corporation}",
  title =        "{Intel IA-64} Architecture Software Developer's
                 Manual: Volume 2: {IA-64} System Architecture",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "536",
  month =        jan,
  year =         "2000",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Fri Jan 05 08:45:35 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/downloads/245318.htm",
  acknowledgement = ack-nhfb,
}

@Book{Intel:2000:IIAc,
  author =       "{Intel Corporation}",
  title =        "{Intel IA-64} Architecture Software Developer's
                 Manual: Volume 3: Instruction Set Reference",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "926",
  month =        jan,
  year =         "2000",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Fri Jan 05 08:45:35 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/downloads/245319.htm",
  acknowledgement = ack-nhfb,
}

@Book{Intel:2000:IIAd,
  author =       "{Intel Corporation}",
  title =        "{Intel IA-64} Architecture Software Developer's
                 Manual: Volume 4: {Itanium} Processor Programmer's
                 Guide",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "76",
  month =        jan,
  year =         "2000",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Fri Jan 05 08:45:35 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/downloads/245320.htm",
  acknowledgement = ack-nhfb,
}

@TechReport{Intel:2000:IIP,
  author =       "{Intel Corporation}",
  title =        "{Intel Itanium} Processor: High Performance On
                 Security Algorithms ({RSA} Decryption Kernel)",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "8",
  year =         "2000",
  bibdate =      "Fri Jan 05 09:27:38 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/downloads/itaniumssl_seg_103.htm",
  acknowledgement = ack-nhfb,
}

@Book{Intel:2000:IPMa,
  author =       "{Intel Corporation}",
  title =        "{Itanium} Processor Microarchitecture Reference for
                 Software Optimization",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "32",
  month =        mar,
  year =         "2000",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Fri Jan 05 08:45:35 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/downloads/245473.htm",
  acknowledgement = ack-nhfb,
}

@Book{Intel:2000:IPMb,
  author =       "{Intel Corporation}",
  title =        "{Itanium} Processor Microarchitecture Reference for
                 Software Optimization",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "34",
  month =        aug,
  year =         "2000",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Fri Jan 05 09:23:17 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/downloads/245474.htm",
  acknowledgement = ack-nhfb,
}

@Book{Intel:2000:ISAa,
  author =       "{Intel Corporation}",
  title =        "{IA-64 System Abstraction Layer (SAL)} Specification",
  publisher =    pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "120",
  month =        jul,
  year =         "2000",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Fri Jan 05 10:50:32 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/downloads/24535902.htm",
  acknowledgement = ack-nhfb,
}

@TechReport{Intel:2000:ISAb,
  author =       "{Intel Corporation}",
  title =        "The {IA-64} System Architecture: Tutorial for
                 Hardware, {OS}, and Application Developers",
  type =         "Technical report",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  year =         "2000",
  bibdate =      "Fri Jan 05 09:35:44 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/archSysSoftware/",
  acknowledgement = ack-nhfb,
}

@Article{Jennings:1998:MCS,
  author =       "Matthew D. Jennings and Thomas M. Conte",
  title =        "Mobile Computing: Subword extensions for video
                 processing on mobile systems",
  journal =      j-IEEE-CONCURR,
  volume =       "6",
  number =       "3",
  pages =        "13--16",
  month =        jul # "\slash " # sep,
  year =         "1998",
  CODEN =        "IECMFX",
  DOI =          "http://dx.doi.org/10.1109/4434.708250",
  ISSN =         "1092-3063 (print), 1558-0849 (electronic)",
  ISSN-L =       "1092-3063",
  bibdate =      "Mon Jun 7 07:52:29 MDT 1999",
  bibsource =    "http://www.computer.org/concurrency/pd1998/;
                 http://www.math.utah.edu/pub/tex/bib/ieeeconcurrency.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://dlib.computer.org/pd/books/pd1998/pdf/p3013.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Concurrency",
  keywords =     "3DNow!; AltiVec; MAX-2; MIPS Digital Media Extensions
                 (MDMX); MMX; VIS",
}

@Article{Jessani:1996:FPU,
  author =       "R. M. Jessani and C. H. Olson",
  title =        "The floating point unit of the {PowerPC} 603e
                 microprocessor",
  journal =      j-IBM-JRD,
  volume =       "40",
  number =       "5",
  pages =        "559--566",
  month =        sep,
  year =         "1996",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Tue Mar 25 14:26:59 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ibmjrd.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.almaden.ibm.com/journal/rd40-5.html#four",
  abstract =     "The IBM PowerPC 603e* floating-point unit (FPU) is an
                 on-chip functional unit to support IEEE 754 standard
                 single- and double-precision binary floating-point
                 arithmetic operations. The design objectives are to be
                 a low-cost, low-power, high-performance engine in a
                 single-chip superscalar microprocessor. Using less than
                 15 mm$^2$ of the available silicon area on the chip
                 (the size of the PowerPC 603e microprocessor is 98
                 mm$^2$ ) and operating at the peak clock frequency of
                 100 MHz, an average single-pumping multiply-add-fuse
                 instruction has one-cycle throughput and four-cycle
                 latency. An average double-pumping multiply-add-fuse
                 instruction has two-cycle throughput and five-cycle
                 latency. The estimated performance at 100 MHz is 105
                 against the SPECfp92** benchmark.",
  acknowledgement = ack-nhfb,
  classcodes =   "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5230 (Digital arithmetic
                 methods)",
  corpsource =   "Somerset Design Center, Motorola Inc., Austin, TX,
                 USA",
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "add-fuse instruction; design objectives; digital
                 arithmetic; double-pumping multiply-add-fuse; floating
                 point unit; functional unit; IEEE 754 standard;
                 instruction; microprocessor chips; on-chip; peak clock
                 frequency; PowerPC 603e microprocessor; silicon area;
                 single-pumping multiply-",
  treatment =    "A Application; P Practical",
  xxlibnote =    "Issue missing from UofUtah Marriott Library",
}

@Book{Kacmarcik:1995:OPC,
  author =       "Gary Kacmarcik",
  title =        "Optimizing {PowerPC} code: programming the {PowerPC}
                 chip in assembly language",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "viii + 694",
  year =         "1995",
  ISBN =         "0-201-40839-2",
  ISBN-13 =      "978-0-201-40839-3",
  LCCN =         "QA76.8.P67 K33 1995",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  acknowledgement = ack-nhfb,
  keywords =     "PowerPC microprocessors",
}

@Article{Kahaner:1992:TD,
  author =       "D. K. Kahaner",
  title =        "Transputers and Databases",
  journal =      j-IEEE-MICRO,
  volume =       "12",
  number =       "6",
  pages =        "88--89",
  month =        dec,
  year =         "1992",
  CODEN =        "IEMIDZ",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}

@Book{Kane:1987:MRR,
  author =       "Gerry Kane",
  title =        "{MIPS R2000 RISC} architecture",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "various",
  year =         "1987",
  ISBN =         "0-13-584749-4 (paperback)",
  ISBN-13 =      "978-0-13-584749-7 (paperback)",
  LCCN =         "QA76.8.M52 K36 1988",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "computer architecture; MIPS R2000 series
                 microprocessors; reduced instruction set computers",
}

@Book{Kane:1989:MRR,
  author =       "Gerry Kane",
  title =        "{MIPS R2000 RISC} Architecture",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "various",
  year =         "1989",
  ISBN =         "0-13-584293-X",
  ISBN-13 =      "978-0-13-584293-5",
  LCCN =         "QA76.8.M52 K37 1988",
  bibdate =      "Wed Dec 15 17:51:38 1993",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  keywords =     "computer architecture; MIPS R2000 series
                 microprocessors",
}

@Book{Kane:1992:MRA,
  author =       "Gerry Kane and Joe Heinrich",
  title =        "{MIPS RISC} Architecture",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "various",
  year =         "1992",
  ISBN =         "0-13-590472-2",
  ISBN-13 =      "978-0-13-590472-5",
  LCCN =         "QA76.8.M52 K37 1992",
  bibdate =      "Wed Dec 15 10:35:45 1993",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  keywords =     "computer architecture; MIPS R2000 series
                 microprocessors; reduced instruction set computers",
}

@Book{Kane:1996:PRA,
  author =       "Gerry Kane",
  title =        "{PA-RISC 2.0} architecture",
  publisher =    pub-PHPTR,
  address =      pub-PHPTR:adr,
  pages =        "various",
  year =         "1996",
  ISBN =         "0-13-182734-0",
  ISBN-13 =      "978-0-13-182734-9",
  LCCN =         "QA76.8.H48K36 1996",
  bibdate =      "Tue Jan 09 12:34:37 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$34.40",
  URL =          "http://devresource.hp.com/devresource/Docs/Refs/PA2_0/index.html;
                 http://devresource.hp.com/devresource/Docs/Refs/PA2_0/updates/index.html",
  acknowledgement = ack-nhfb,
  keywords =     "Hewlett--Packard computers; PA-RISC microprocessors",
}

@Article{Keltcher:2003:AOP,
  author =       "Chetana N. Keltcher and Kevin J. McGrath and Ardsher
                 Ahmed and Pat Conway",
  title =        "The {AMD Opteron} Processor for Multiprocessor
                 Servers",
  journal =      j-IEEE-MICRO,
  volume =       "23",
  number =       "2",
  pages =        "66--76",
  month =        mar # "\slash " # apr,
  year =         "2003",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/MM.2003.1196116",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Wed Apr 23 18:57:11 MDT 2003",
  bibsource =    "http://www.computer.org/micro/mi2003/;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://dlib.computer.org/mi/books/mi2003/pdf/m2066.pdf;
                 http://www.computer.org/micro/mi2003/m2066abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}

@Article{Kerschen:1992:HOS,
  author =       "K. Kerschen and J. R. Glasson",
  title =        "{HP-UX} operating system kernel support for the {HP}
                 9000 series 700 workstations",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "43",
  number =       "3",
  pages =        "6--10",
  month =        jun,
  year =         "1992",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Tue Mar 25 14:12:15 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "Summarizes the architectural enhancements of PA-RISC
                 1.1 and tells how the kernel of the HP-UX operating
                 system was modified to take advantage of them. The
                 software release for the Series 700 operating system
                 was designed to address key features of the CPU chip.
                 To tailor the kernel to the CPU's capabilities required
                 the following changes: emulation of floating-point
                 instructions, which also supports the floating-point
                 coprocessor enhancements; cache flush instructions to
                 the I/O and memory controller for the benefit of
                 graphics applications; shadow registers for improved
                 TLB (translation lookaside buffer) miss handling;
                 4K-byte page size to reduce TLB miss rate; sparse PDIR
                 (page directory), which reduces overhead for the EISA
                 I/O address space and is faster; and new block TLB
                 entries to map the kernel and graphics frame buffers.",
  acknowledgement = ack-nhfb,
  affiliation =  "Hewlett--Packard Co., Palo Alto, CA, USA",
  classcodes =   "C6150J (Operating systems); C5420 (Mainframes and
                 minicomputers); C5220 (Computer architecture)",
  classification = "C5220 (Computer architecture); C5420 (Mainframes and
                 minicomputers); C6150J (Operating systems)",
  corpsource =   "Hewlett--Packard Co., Palo Alto, CA, USA",
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
  keywords =     "4K-byte page size; applications; Block TLB entries;
                 block TLB entries; buffer; Cache flush instructions;
                 cache flush instructions; directory; EISA I/O address
                 space; Floating-point instructions; floating-point
                 instructions; graphics; Graphics applications; Graphics
                 frame buffers; graphics frame buffers; Hewlett Packard
                 computers; HP 9000 series 700; HP 9000 series 700
                 workstations; HP-UX operating system kernel; Memory
                 controller; memory controller; operating systems
                 (computers); PA-RISC 1.1; page; Page directory; reduced
                 instruction set computing; Shadow registers; shadow
                 registers; Sparse PDIR; sparse PDIR; storage
                 management; TLB miss rate; translation lookaside;
                 Translation lookaside buffer; workstations",
  thesaurus =    "Hewlett Packard computers; Operating systems
                 [computers]; Reduced instruction set computing; Storage
                 management",
  treatment =    "P Practical",
}

@Book{Koerner:1996:PIV,
  author =       "Michael Koerner and Chak Ming Fai and Joe Ruthven",
  title =        "{PowerPC}: an inside view",
  publisher =    pub-PHPTR,
  address =      pub-PHPTR:adr,
  pages =        "various",
  year =         "1996",
  ISBN =         "0-13-255753-3 (paperback)",
  ISBN-13 =      "978-0-13-255753-5 (paperback)",
  LCCN =         "QA76.8.P67 K63 1996",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  acknowledgement = ack-nhfb,
  keywords =     "PowerPC microprocessors",
}

@Article{Kohn:1989:III,
  author =       "Les Kohn and Neal Margulis",
  title =        "Introducing the {Intel i860} 64-Bit Microprocessor",
  journal =      j-IEEE-MICRO,
  volume =       "9",
  number =       "4",
  pages =        "15--30",
  month =        aug,
  year =         "1989",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.31485",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  acknowledgement = ack-nhfb,
  affiliation =  "Intel Corp, Santa Clara, CA, USA",
  classcodes =   "C5130 (Microprocessor chips); C5220 (Computer
                 architecture)",
  classification = "714; 721; 722; 723",
  corpsource =   "Intel Corp., Santa Clara, CA, USA",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "64; architectural concepts; balanced integer; bit; bus
                 interface; Computer Architecture; Computers,
                 Microcomputer; core; Evaluation; floating-;
                 floating-point; graphics; instruction set computing;
                 instructions; Intel i860; interfacing; memory
                 management; microprocessor chips; parallel; parallel
                 architectures; point unit; reduced;
                 reduced-instruction-set-computer;
                 Reduced-Instruction-Set-Computer (RISC); RISC; software
                 support; Supercomputers",
  treatment =    "P Practical",
}

@InProceedings{Kohn:1989:ISM,
  author =       "L. Kohn and N. Margulis",
  title =        "The {i860} 64-bit supercomputing microprocessor",
  crossref =     "ACM:1989:PSN",
  pages =        "450--456",
  year =         "1989",
  bibdate =      "Wed Apr 15 19:32:44 MDT 1998",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture)",
  corpsource =   "Intel Corp., Santa Clara, CA, USA",
  keywords =     "64 bit; caches; floating point unit; i860 64-bit
                 supercomputing microprocessor; Intel; memory
                 management; microprocessor chips; multiplier units;
                 parallel architectures; parallelism; pipelined adder;
                 pipelining; reduced instruction set computing; RISC
                 based microprocessor; three-dimensional graphics",
  sponsororg =   "ACM; IEEE",
  treatment =    "P Practical",
}

@Article{Krishnaiyer:2000:AOI,
  author =       "Rakesh Krishnaiyer and Dattatraya Kulkarni and Daniel
                 Lavery and Wei Li and Chu-cheow Lim and John Ng and
                 David Sehr",
  title =        "An Advanced Optimizer for the {IA-64} Architecture",
  journal =      j-IEEE-MICRO,
  volume =       "20",
  number =       "6",
  pages =        "60--68",
  month =        nov # "\slash " # dec,
  year =         "2000",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.888704",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 05:20:47 2000",
  bibsource =    "http://www.computer.org/micro/mi2000/;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://dlib.computer.org/mi/books/mi2000/pdf/m6060.pdf;
                 http://www.computer.org/micro/mi2000/m6060abs.htm",
  abstract =     "Predication and large register files and control and
                 data speculation and an advanced branch architecture
                 all help IA-64 to enable more aggressive compiler
                 optimizations.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}

@Article{Kumar:1997:HPR,
  author =       "Ashok Kumar",
  title =        "The {HP PA-8000 RISC CPU}",
  journal =      j-IEEE-MICRO,
  volume =       "17",
  number =       "2",
  pages =        "27--32",
  month =        mar # "\slash " # apr,
  year =         "1997",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.592310",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture);
                 C5430 (Microcomputers)",
  corpsource =   "Syst. Performance Lab., Hewlett--Packard Co.,
                 Cupertino, CA, USA",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "computer architecture; dynamic instruction reordering;
                 Hewlett Packard computers; Hewlett--Packard
                 microprocessors; high-end systems; instruction
                 reordering; microprocessor chips; PA-8000; PA-8000 RISC
                 CPU; PA-RISC; Precision Architecture; primary caches;
                 reduced instruction set computing; Runway system bus",
  treatment =    "P Practical; R Product Review",
}

@Article{Lee:1991:FPPa,
  author =       "Roland L. Lee and Alex Y. Kwok and Fay{\'e} A.
                 Briggs",
  title =        "The Floating Point Performance of a superscalar
                 {SPARC} Processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "28--37",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
}

@Article{Lee:1991:FPPb,
  author =       "Roland L. Lee and Alex Y. Kwok and Fay{\'e} A.
                 Briggs",
  title =        "The Floating-Point Performance of a Superscalar
                 {SPARC} Processor",
  journal =      j-SIGPLAN,
  volume =       "26",
  number =       "4",
  pages =        "28--37",
  month =        apr,
  year =         "1991",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Tue Dec 12 09:20:21 MST 1995",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "The floating point performance of superscalar SPARC
                 processors is evaluated based on empirical data from 12
                 benchmarks. This evaluation is done in the context of
                 two software instruction scheduling optimizations: loop
                 unrolling and software pipelining, and for three
                 machine models: 1-scalar, 2-scalar and 4-scalar. The
                 authors also consider the effect of the memory system
                 on the performance improvements. Superscalar hardware
                 alone exhibit little performance improvement without
                 software optimization. Of the two scheduling methods,
                 software pipelining more effectively takes advantage of
                 increased hardware parallelism, and achieves near
                 optimal speedup on the 4-scalar machine model. The
                 performance of loop unrolling is restricted by the
                 limited number of floating point registers in the SPARC
                 architecture. The best performance level is obtained by
                 applying both optimization techniques. A superscalar
                 SPARC processor can provide improved floating point
                 performance but with significant software and hardware
                 development costs.",
  acknowledgement = ack-nhfb,
  affiliation =  "Sun Microsyst. Inc., Mountain View, CA, USA",
  classification = "C5220 (Computer architecture); C5470 (Performance
                 evaluation and testing)",
  confdate =     "8-11 April 1991",
  conflocation = "Santa Clara, CA, USA",
  confsponsor =  "IEEE; ACM",
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  keywords =     "Benchmarks; Development costs; Floating point
                 performance; Floating point registers; Hardware
                 parallelism; Loop unrolling; Memory system; N-scalar
                 machine models; Optimal speedup; Software instruction
                 scheduling optimizations; Software pipelining; SPARC
                 architecture; Superscalar SPARC processor",
  language =     "English",
  pubcountry =   "USA",
  thesaurus =    "Optimisation; Parallel architectures; Performance
                 evaluation; Pipeline processing; Scheduling",
}

@Article{Lee:1992:FPP,
  author =       "K. Lee",
  title =        "On the Floating Point Performance of the i860
                 Microprocessor",
  journal =      j-INT-J-HIGH-SPEED-COMPUTING,
  volume =       "4",
  number =       "4",
  pages =        "251--268",
  month =        dec,
  year =         "1992",
  CODEN =        "IHSCEZ",
  ISSN =         "0129-0533",
  bibdate =      "Sat Feb 24 15:01:45 MST 1996",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "International Journal of High Speed Computing",
}

@Article{Lee:1996:SPM,
  author =       "Ruby B. Lee",
  title =        "Subword Parallelism with {MAX-2}: Accelerating media
                 processing with a minimal set of instruction extensions
                 supporting efficient subword parallelism",
  journal =      j-IEEE-MICRO,
  volume =       "16",
  number =       "4",
  pages =        "51--59",
  month =        aug,
  year =         "1996",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.526925",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  acknowledgement = ack-nhfb,
  classcodes =   "C6130M (Multimedia); C6150N (Distributed systems
                 software); C6140B (Machine-oriented languages)",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "computation; instruction extensions; instruction sets;
                 MAX-2; media processing; multimedia computing;
                 parallel; parallel processing; subword parallelism;
                 word-oriented general-purpose processor",
  treatment =    "P Practical",
}

@Book{Levine:1994:RSP,
  author =       "Frank Levine and Steve Thurber",
  title =        "{RISC} System\slash 6000 {PowerPC} System
                 Architecture",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  pages =        "xxiv + 320",
  year =         "1994",
  ISBN =         "1-55860-344-1",
  ISBN-13 =      "978-1-55860-344-8",
  LCCN =         "QA76.5.R46 1994",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  note =         "Contents: Introduction --- PowerPC processor
                 architecture --- Architected system memory map --
                 Bring-up and configuration architecture --- NVRAM
                 contents and mapping --- Bus Unit Controller (BUC)
                 architecture --- IOCC architecture --- System resources
                 --- External interrupt architecture --- System
                 exception processing --- System bus architecture ---
                 Bring-up function and IPLCB --- Vital Product Data
                 (VPD) --- AIX based diagnostics requirements.",
  acknowledgement = ack-nhfb,
  keywords =     "computer architecture; IBM RISC System/6000 computers;
                 RISC microprocessors",
}

@Article{Lewis:1999:BCFb,
  author =       "Ted Lewis",
  title =        "Binary Critic: Fast, Expensive, and Horribly Complex",
  journal =      j-COMPUTER,
  volume =       "32",
  number =       "9",
  pages =        "120, 118--119",
  month =        sep,
  year =         "1999",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Tue Sep 7 19:41:32 MDT 1999",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/computer1990.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia64/index.htm;
                 http://dlib.computer.org/co/books/co1999/pdf/r9120.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "Intel IA-64; Merced",
}

@Book{Lindholm:1997:JVM,
  author =       "Tim Lindholm and Frank Yellin",
  title =        "The {Java} Virtual Machine Specification",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "xvi + 475",
  month =        jan,
  year =         "1997",
  ISBN =         "0-201-63452-X",
  ISBN-13 =      "978-0-201-63452-5",
  LCCN =         "QA76.73.J38L56 1997",
  bibdate =      "Wed Jun 17 22:05:06 MDT 1998",
  bibsource =    "http://www.amazon.com/exec/obidos/ISBN=020163452X/wholesaleproductA/;
                 http://www.aw.com/;
                 http://www.javaworld.com/javaworld/books/jw-books-alphabytitle.html;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$36.53",
  series =       "The Java Series",
  URL =          "http://www.aw.com/cp/javaseries.html;
                 http://www.aw.com/cseng/titles/0-201-63452-X",
  acknowledgement = ack-nhfb,
  dimensions =   "9.20in x 7.36in x 1.03in",
  keywords =     "Internet (Computer network); Java (Computer program
                 language); Java (computer program language);
                 programming languages (electronic computers); systems;
                 virtual computer; Virtual computer systems",
  lccnalt =      "96-015897",
}

@Book{Lindholm:1999:JVM,
  author =       "Tim Lindholm and Frank Yellin",
  title =        "The {Java} Virtual Machine Specification",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  edition =      "Second",
  pages =        "xv + 473",
  year =         "1999",
  ISBN =         "0-201-43294-3",
  ISBN-13 =      "978-0-201-43294-7",
  LCCN =         "QA76.73.J38L56 1999",
  bibdate =      "Tue May 11 07:30:11 1999",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$42.95",
  acknowledgement = ack-nhfb,
}

@InProceedings{Maher:1996:MIS,
  author =       "Robert Maher",
  title =        "Multimedia Instruction Set Extensions for a
                 Sixth-Generation x86 Processor",
  crossref =     "IEEE:1996:HCV",
  pages =        "163--170",
  year =         "1996",
  bibdate =      "Sat Jan 6 19:21:13 MST 2001",
  bibsource =    "ftp://www.hotchips.org/pub/hotc7to11cd/hc96/hc8_pdf/5.3.pdf;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  keywords =     "Cyrix M2 processor",
}

@Misc{Mahon:1987:HPA,
  author =       "Michael Mahon",
  title =        "{H-P Precision Architecture}",
  volume =       "3",
  publisher =    pub-UNIV-VIDEO-COMM,
  address =      pub-UNIV-VIDEO-COMM:adr,
  year =         "1987",
  LCCN =         "VT1783 Protect",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "Sponsored by Information Technology Group,
                 Hewlett--Packard Company. Bibliography on front and its
                 verso of container. Credits: CREDITS: Hosts and
                 executive producers: Karen Mathews and Judith Lemon.
                 Recorded at Melchor Productions, October 13, 1987,
                 Mountain View, Calif. ``This lecture presents the
                 reduced complexity H-P precision architecture. Design
                 tradeoffs are explored with particular attention paid
                 to the rationale for architectural choices which
                 deviate from accepted CISC and RISC practice.''---front
                 of cover of container. Targeted courses: Computer
                 architecture.---front cover, container.",
  series =       "Distinguished lecture series, industry leaders in
                 computer science",
  acknowledgement = ack-nhfb,
  keywords =     "computer architecture; computer engineering",
}

@Book{Malone:1991:GPM,
  author =       "Michael S. (Michael Shawn) Malone",
  title =        "Going public: {MIPS} computer and the entrepreneurial
                 dream",
  publisher =    "E. Burlingame Books",
  address =      "New York, NY, USA",
  pages =        "viii + 291",
  year =         "1991",
  ISBN =         "0-06-016519-7",
  ISBN-13 =      "978-0-06-016519-2",
  LCCN =         "HG4028.S7 M19 1991",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  price =        "US\$22.95, CDN\$29.95",
  acknowledgement = ack-nhfb,
  keywords =     "computer industry -- case studies; entrepreneurship
                 --- case studies; going public (securities) --- case
                 studies",
}

@Book{Malone:1995:MB,
  author =       "Michael S. Malone",
  title =        "The microprocessor: a biography",
  publisher =    pub-TELOS,
  address =      pub-TELOS:adr,
  pages =        "xiv + 333",
  year =         "1995",
  ISBN =         "0-387-94145-2, 0-387-94342-0",
  ISBN-13 =      "978-0-387-94145-5, 978-0-387-94342-8",
  LCCN =         "TK7895.M5 M35 1995",
  bibdate =      "Wed Jan 10 08:22:23 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$49.95",
  acknowledgement = ack-nhfb,
  libnote =      "Not yet in my library. Listed as out-of-print.",
}

@Article{Mangelsdorf:1997:FVH,
  author =       "S. T. Mangelsdorf and R. P. Gratias and R. M. Blumberg
                 and R. Bhatia",
  title =        "Functional Verification of the {HP PA 8000}
                 Processor",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "48",
  number =       "4",
  pages =        "22--31",
  month =        aug,
  year =         "1997",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Wed Mar 25 15:17:10 MST 1998",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.hp.com/hpj/97aug/au97a3.htm",
  abstract =     "The advanced microarchitecture of the HP PA 8000 CPU
                 has many features that presented significant new
                 verification challenges. These include out-of-order
                 instruction execution, register renaming, speculative
                 execution, four-way superscalar operation, decoupled
                 instruction fetch, concurrent system bus interface, and
                 PA-RISC 2.0 architecture enhancements. Enhanced
                 functional verification tools and processes were
                 required to address this microarchitectural
                 complexity.",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture);
                 C6110F (Formal methods)",
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
  keywords =     "concurrent system bus interface; decoupled instruction
                 fetch; formal verification; four-way superscalar
                 operation; functional verification; Hewlett Packard
                 computers; HP PA 8000 processor; microarchitectural
                 complexity; microarchitecture; microprocessor chips;
                 out-of-order instruction execution; PA-RISC 2.0
                 architecture enhancements; reduced instruction set
                 computing; register renaming; speculative execution;
                 verification challenges",
  treatment =    "A Application; P Practical",
}

@Book{Margulis:1990:IMA,
  author =       "Neal Margulis",
  title =        "i860 Microprocessor Architecture",
  publisher =    pub-MCGRAW-HILL,
  address =      pub-MCGRAW-HILL:adr,
  pages =        "xxiii + 631",
  year =         "1990",
  ISBN =         "0-07-881645-9",
  ISBN-13 =      "978-0-07-881645-1",
  LCCN =         "QA76.5.M37 1990",
  bibdate =      "Wed Dec 15 10:38:45 1993",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  libnote =      "Not yet in my library.",
}

@Article{Margulis:1990:IMI,
  author =       "N. Margulis",
  title =        "i860 microprocessor internal architecture",
  journal =      j-MICROPROC-MICROSYS,
  volume =       "14",
  number =       "2",
  pages =        "89--96",
  month =        mar,
  year =         "1990",
  CODEN =        "MIMID5",
  ISSN =         "0141-9331",
  ISSN-L =       "0141-9331",
  bibdate =      "Wed Sep 7 22:32:42 1994",
  bibsource =    "garbo.uwasa.fi:/pc/doc-soft/fpbiblio.txt;
                 http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nj,
  fjournal =     "Microprocessors and Microsystems",
}

@Book{Markstein:2000:IEF,
  author =       "Peter Markstein",
  title =        "{IA-64} and elementary functions: speed and
                 precision",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "xix + 298",
  year =         "2000",
  ISBN =         "0-13-018348-2",
  ISBN-13 =      "978-0-13-018348-4",
  LCCN =         "QA76.9.A73 M365 2000",
  bibdate =      "Fri Jan 5 08:00:52 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  series =       "Hewlett--Packard professional books",
  acknowledgement = ack-nhfb,
  keywords =     "IA-64 (computer architecture)",
}

@Book{May:1994:PAS,
  editor =       "Cathy May and Ed Silha and Rick Simpson and Hank
                 Warren",
  title =        "The {PowerPC} Architecture: {A} Specification for a
                 New Family of {RISC} Processors",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  edition =      "Second",
  pages =        "xxxi + 518",
  year =         "1994",
  ISBN =         "1-55860-316-6",
  ISBN-13 =      "978-1-55860-316-5",
  LCCN =         "QA76.8.P67 P68 1994",
  bibdate =      "Sat Feb 24 10:55:16 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$49.95",
  acknowledgement = ack-nhfb,
  oldlabel =     "IBM:1994:PAS",
}

@TechReport{McComas:2001:CPR,
  author =       "Bert McComas",
  title =        "Can the {Pentium 4} Recover?: Also, new complexities
                 uncovered regarding {P4} bandwidth utilization and
                 power consumption",
  type =         "Technical report",
  institution =  "InQuest Market Research",
  address =      "16114 E. Fairview Lane, Higley, AZ 85236, USA",
  day =          "11",
  month =        apr,
  year =         "2001",
  bibdate =      "Fri May 18 07:28:45 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.inqst.com/articles/p4bandwidth/p4bandwidthmain.htm",
  acknowledgement = ack-nhfb,
}

@TechReport{McComas:2001:WEA,
  author =       "Bert McComas and Van Smith",
  title =        "The War Escalates: {Athlon4} takes on {Pentium4}",
  type =         "Technical report",
  institution =  "InQuest Market Research",
  address =      "16114 E. Fairview Lane, Higley, AZ 85236, USA",
  month =        may,
  year =         "2001",
  bibdate =      "Fri May 18 07:15:57 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "This report contains performance data comparing the
                 AMD Athlon4 (Palomino core) with the Intel Pentium4
                 (Willamette core). The Pentium4 CPU contains a thermal
                 sensor that automatically reduces the CPU clock rate
                 when the chip gets too hot. At 1.7GHz clock rates, but
                 not at 1.4GHz, this throttling occurs after a few
                 minutes of operation, and performance drops by 30\% to
                 75\%. The Athlon4 shows no such behavior. The Pentium4
                 also shows different benchmark behavior under different
                 operating systems, while the Athlon4 does not. The
                 report also discusses the Pentium4's `Compatible FPU
                 OPCODE' feature, and shows that vendors are shipping
                 systems with the feature disabled, giving up to a 10\%
                 performance gain.",
  URL =          "http://www.inqst.com/articles/athlon4/0516main.htm",
  acknowledgement = ack-nhfb,
}

@Article{McGhan:1998:CPP,
  author =       "Harlan McGhan and Mike O'Connor",
  title =        "Computing Practices: {PicoJava}: {A} Direct Execution
                 Engine For {Java} Bytecode",
  journal =      j-COMPUTER,
  volume =       "31",
  number =       "10",
  pages =        "22--30",
  month =        oct,
  year =         "1998",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Tue Oct 6 18:50:08 MDT 1998",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/computer1990.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://dlib.computer.org/co/books/co1998/pdf/rx022.pdf;
                 http://www.computer.org/computer/co1998/rx022abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
}

@Article{McNairy:2003:IPM,
  author =       "Cameron McNairy and Don Soltis",
  title =        "{Itanium 2} Processor Microarchitecture",
  journal =      j-IEEE-MICRO,
  volume =       "23",
  number =       "2",
  pages =        "44--55",
  month =        mar # "\slash " # apr,
  year =         "2003",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/MM.2003.1196114",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Wed Apr 23 18:57:11 MDT 2003",
  bibsource =    "http://www.computer.org/micro/mi2003/;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://dlib.computer.org/mi/books/mi2003/pdf/m2044.pdf;
                 http://www.computer.org/micro/mi2003/m2044abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}

@Book{Messmer:1995:IPB,
  author =       "Hans-Peter Messmer",
  title =        "The indispensable {Pentium} book",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "496",
  year =         "1995",
  ISBN =         "0-201-87727-9",
  ISBN-13 =      "978-0-201-87727-4",
  LCCN =         "QA76.8.P46 M48 1995",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "Pentium (microprocessor)",
}

@Book{Meyer:1997:JVM,
  author =       "Jon Meyer and Troy Downing",
  title =        "The {Java} Virtual Machine",
  publisher =    pub-ORA,
  address =      pub-ORA:adr,
  pages =        "xxiv + 426",
  year =         "1997",
  ISBN =         "1-56592-194-1",
  ISBN-13 =      "978-1-56592-194-8",
  LCCN =         "QA76.73.J38M49 1997",
  bibdate =      "Wed Jun 17 22:05:06 MDT 1998",
  bibsource =    "http://www.amazon.com/exec/obidos/ISBN=1565921941/wholesaleproductA/;
                 http://www.javaworld.com/javaworld/books/jw-books-alphabytitle.html;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 http://www.ora.com/",
  price =        "US\$32.95",
  URL =          "http://www.ora.com/www/item/javavm.html",
  acknowledgement = ack-nhfb,
  dimensions =   "9.18in x 7.08in x 1.15in",
  keywords =     "computer systems; Java (computer program language);
                 technology -- computers and computer technology;
                 virtual",
  paperback =    "yes",
}

@Book{Miller:1999:ALI,
  author =       "Karen Miller",
  title =        "An assembly language introduction to computer
                 architecture: using the {Intel Pentium}",
  publisher =    pub-OXFORD,
  address =      pub-OXFORD:adr,
  pages =        "335",
  year =         "1999",
  ISBN =         "0-19-512376-X (cloth)",
  ISBN-13 =      "978-0-19-512376-0 (cloth)",
  LCCN =         "QA76.9.A73 M55 1999",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "assembler language (computer program language);
                 computer architecture",
}

@Manual{MIPS:1996:MED,
  title =        "{MIPS} Extensions for Digital Media with {$3$D}",
  organization = "MIPS Technologies, Inc.",
  address =      "930 Arques Avenue, Sunnyvale, CA 94086-3650, USA",
  pages =        "26",
  year =         "1996",
  bibdate =      "Tue Jan 09 06:52:48 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  keywords =     "MIPS Digital Media eXtension (MDMX), pronounced
                 MaDMaX",
}

@Manual{MIPS:1996:MRM,
  title =        "{MIPS R10000} Microprocessor User's Manual",
  organization = "MIPS Technologies, Inc.",
  address =      "2011 North Shoreline Mountain View, California
                 94039-7311, USA",
  pages =        "424",
  year =         "1996",
  bibdate =      "Tue Jan 09 19:10:55 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "Version 2.0",
  URL =          "ftp://ftp.sgi.com/sgi/doc/R10000/User_Manual/t5.ver.2.0.book.pdf",
  acknowledgement = ack-nhfb,
}

@Book{Misra:1990:IRS,
  editor =       "Mamata Misra",
  title =        "{IBM RISC} System\slash 6000 Technology, publication
                 {SA23-2619-00}",
  publisher =    pub-IBM,
  address =      pub-IBM:adr,
  year =         "1990",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
}

@Book{Mitchell:1990:IT,
  author =       "David A. P. Mitchell",
  title =        "Inside the transputer",
  publisher =    "Publishers' Business Services",
  address =      "Brookline Village, MA, USA",
  pages =        "viii + 234",
  year =         "1990",
  ISBN =         "0-632-01689-2",
  ISBN-13 =      "978-0-632-01689-1",
  LCCN =         "TK7895.T73 I55 1990",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  series =       "Computer science texts",
  acknowledgement = ack-nhfb,
  keywords =     "transputers",
}

@Article{Morrow:2001:MUL,
  author =       "Mike Morrow",
  title =        "Microarchitecture Uses a Low-Power Core",
  journal =      j-COMPUTER,
  volume =       "34",
  number =       "4",
  pages =        "55--55",
  month =        apr,
  year =         "2001",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Sat Apr 07 09:45:32 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
}

@Book{Motorola:1985:MBM,
  author =       "Motorola",
  title =        "{MC68020} 32-Bit Microprocessor User's Manual",
  publisher =    pub-MOTOROLA,
  address =      pub-MOTOROLA:adr,
  edition =      "Second",
  year =         "1985",
  ISBN =         "0-13-566878-6",
  ISBN-13 =      "978-0-13-566878-8",
  LCCN =         "QA76.8.M6897 M37 1985",
  bibdate =      "Wed Jul 6 13:48:43 1994",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
}

@Book{Motorola:1985:MFP,
  author =       "Motorola",
  title =        "{MC68881} Floating-Point Coprocessor User's Manual",
  publisher =    pub-MOTOROLA,
  address =      pub-MOTOROLA:adr,
  edition =      "Second",
  year =         "1985",
  bibdate =      "Fri Sep 02 23:38:03 1994",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nj,
}

@Book{Motorola:1989:MRM,
  author =       "Motorola",
  title =        "{MC88100 RISC} Microprocessor User's Manual",
  publisher =    pub-MOTOROLA,
  address =      pub-MOTOROLA:adr,
  edition =      "Second",
  year =         "1989",
  ISBN =         "0-13-567090-X",
  ISBN-13 =      "978-0-13-567090-3",
  LCCN =         "QA76.8.M75 M3 1990",
  bibdate =      "Wed Jul 6 14:23:15 1994",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
}

@Book{Motorola:1993:PTD,
  author =       "{Motorola, Inc.}",
  title =        "{PowerPC} tools: development tools for {PowerPC}
                 microprocessors",
  publisher =    pub-MOTOROLA,
  address =      pub-MOTOROLA:adr,
  edition =      "Second",
  pages =        "x + 178",
  year =         "1993",
  LCCN =         "QA76.89.P67 P75 1993 Sci-Eng",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  acknowledgement = ack-nhfb,
  keywords =     "PowerPC microprocessors; PowerPC microprocessors --
                 programming",
}

@Manual{Motorola:1998:ATP,
  title =        "{AltiVec} Technology Programming Environments Manual",
  organization = pub-MOTOROLA,
  address =      pub-MOTOROLA:adr,
  pages =        "350",
  month =        nov,
  year =         "1998",
  bibdate =      "Tue Jan 09 11:20:43 2001",
  bibsource =    "http://a2016.g.akamai.net/7/2016/787/5087c1b5def3b1/www.motorola.com/SPS/PowerPC/teksupport/teklibrary/manuals/altivec_pem.pdf;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "Order number ALTIVECPEM/D 11/1998 Rev. 0.1.",
  acknowledgement = ack-nhfb,
}

@Misc{Motorola:1999:APE,
  author =       "{Motorola, Inc.}",
  title =        "{AltiVec} Programming Examples",
  howpublished = "World-Wide Web document.",
  day =          "9",
  month =        dec,
  year =         "1999",
  bibdate =      "Tue Jan 09 08:07:17 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.motorola.com/SPS/PowerPC/AltiVec/CodeMain.html",
  acknowledgement = ack-nhfb,
  keywords =     "complex finite impulse response (FIR) filter; encoding
                 a signal to improve its redundancy for transmission;
                 real delayed least mean squared (LMS) FIR filter; real
                 finite impulse response (FIR) filter; RGB to YCbCr
                 color space conversion; scaling values in the range
                 -2040..2040 into the range -127..127; Soft-Decision
                 Viterbi decoder for GSM CC(2,1,5) TCH frames; Sum of
                 Absolute Differences (SOAD or SAD) kernel; transforming
                 values from the range -127..127 to -2048..2047;
                 two-dimensional Discrete Cosine Transform;
                 two-dimensional Inverse Discrete Cosine Transform",
}

@Manual{Motorola:1999:ATP,
  title =        "{AltiVec} Technology Programming Interface Manual",
  organization = pub-MOTOROLA,
  address =      pub-MOTOROLA:adr,
  pages =        "262",
  month =        jun,
  year =         "1999",
  bibdate =      "Tue Jan 09 11:20:43 2001",
  bibsource =    "http://a1008.g.akamai.net/7/1008/787/66cefa0933a341/www.motorola.com/SPS/PowerPC/teksupport/teklibrary/manuals/altivecpim.pdf;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "Order number ALTIVECPIM/D 6/1999 Rev. 0",
  acknowledgement = ack-nhfb,
}

@Misc{Motorola:1999:ATT,
  author =       "{Motorola, Inc.}",
  title =        "{AltiVec} Technology Tour",
  howpublished = "World-Wide Web document.",
  day =          "9",
  month =        dec,
  year =         "1999",
  bibdate =      "Tue Jan 09 08:07:17 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.motorola.com/SPS/PowerPC/AltiVec/technology.html",
  acknowledgement = ack-nhfb,
}

@Article{Mudge:2001:PFC,
  author =       "Trevor Mudge",
  title =        "Power: {A} First-Class Architectural Design
                 Constraint",
  journal =      j-COMPUTER,
  volume =       "34",
  number =       "4",
  pages =        "52--58",
  month =        apr,
  year =         "2001",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Sat Apr 7 07:21:35 MDT 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://dlib.computer.org/co/books/co2001/pdf/r4052.pdf;
                 http://www.computer.org/computer/co2001/r4052abs.htm",
  acknowledgement = ack-nhfb,
  annote =       "This article is a good survey on power consumption
                 issues. Information technology consumes about 8\% of
                 power in the US. Some new low-power CPUs use 20 to 200
                 times less power than current desktop system CPUs, and
                 include the ability to drop into a `drowsy' mode,
                 consuming less than 1mW, but can wake up in 20$ \mu $ s
                 and then run at up to 1GHz.",
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
}

@Book{Myers:1988:MA,
  author =       "Glenford J. Myers and David L. Budde",
  title =        "The 80960 Microprocessor Architecture",
  publisher =    pub-WILEY-INTERSCIENCE,
  address =      pub-WILEY-INTERSCIENCE:adr,
  pages =        "xiii + 255",
  year =         "1988",
  ISBN =         "0-471-61857-8",
  ISBN-13 =      "978-0-471-61857-7",
  LCCN =         "QA76.8.I29284 M941 1988",
  bibdate =      "Wed Dec 15 10:39:54 1993",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
}

@Article{Nicoud:1989:TTI,
  author =       "Jean-Daniel D. Nicoud and Andrew Martin Tyrrell",
  title =        "The Transputer-{T414} Instruction Set",
  journal =      j-IEEE-MICRO,
  volume =       "9",
  number =       "3",
  pages =        "60--75",
  month =        jun,
  year =         "1989",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.31478",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Parallel/transputer.bib; Science Citation Index
                 database (1980--2000)",
  acknowledgement = ack-nhfb,
  affiliation =  "Ecole Polytech Fed de Lausanne, Lausanne, Switz",
  classcodes =   "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips)",
  classification = "722; 723",
  corpsource =   "Lab. de Microinformatique, Ecole Polytech. Federal de
                 Lausanne, Switzerland",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "addressing modes; assembly language notations;
                 communication; Computer Operating Systems--Program
                 Compilers; Computer Systems, Digital--Multiprocessing;
                 Computers, Microcomputer; Concurrent Processes;
                 concurrent processes; Data Communication Systems; data
                 types; instruction sets; memory; Occam Compiler;
                 programming philosophy; Reduced Instruction Set
                 Computer; registers; set; Timer Queue; transputer T414
                 instruction; Transputer T414 Instruction Set;
                 transputers",
  treatment =    "P Practical",
}

@InProceedings{Oberman:1998:ATK,
  author =       "Stuart Oberman and Fred Weber and Norbert Juffa and
                 Greg Favor",
  title =        "{AMD 3DNow!} Technology and the {K6-2}
                 Microprocessor",
  crossref =     "IEEE:1998:HCC",
  pages =        "245--254",
  year =         "1998",
  bibdate =      "Mon Jan 08 17:02:55 2001",
  bibsource =    "ftp://www.hotchips.org/pub/hotc7to11cd/hc98/pdf_1up/hc98_10c_oberman_1up.txt;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
}

@Article{Oberman:1999:ATA,
  author =       "Stuart Oberman and Greg Favor and Fred Weber",
  title =        "{AMD 3DNow!} Technology: Architecture and
                 Implementations",
  journal =      j-IEEE-MICRO,
  volume =       "19",
  number =       "2",
  pages =        "37--48",
  month =        mar # "\slash " # apr,
  year =         "1999",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.755466",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.computer.org/micro/mi1999/;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  URL =          "http://dlib.computer.org/mi/books/mi1999/pdf/m2037.pdf;
                 http://www.computer.org/micro/mi1999/m2037abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}

@Article{OConnell:2000:PNG,
  author =       "F. P. O'Connell and S. W. White",
  title =        "{POWER3}: The next generation of {PowerPC}
                 processors",
  journal =      j-IBM-JRD,
  volume =       "44",
  number =       "6",
  pages =        "873--884",
  month =        "????",
  year =         "2000",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Sat Feb 24 09:44:45 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 http://www.research.ibm.com/journal/",
  URL =          "http://www.research.ibm.com/journal/rd/446/oconnell.html",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  ordernumber =  "G322-0224",
}

@Article{OConnor:1997:PJV,
  author =       "J. Michael O'Connor and Marc Tremblay",
  title =        "{Picojava-I} --- The {Java Virtual Machine} in
                 Hardware",
  journal =      j-IEEE-MICRO,
  volume =       "17",
  number =       "2",
  pages =        "45--53",
  month =        mar # "\slash " # apr,
  year =         "1997",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.592314",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  acknowledgement = ack-nhfb,
  classification = "C5220 (Computer architecture); C6150C (Compilers,
                 interpreters and other processors); C7430 (Computer
                 engineering)",
  corpsource =   "Sun Microsyst., Mountain View, CA, USA",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "byte codes; computer architecture; dynamic
                 distribution; Java virtual machine; microarchitecture;
                 microarchitecture trade-offs; performance; picoJava-I;
                 program compilers; virtual machines",
  treatment =    "P Practical",
}

@Misc{Patterson:1989:SSA,
  author =       "David Patterson and Wayne Rosing",
  title =        "Story of {SPARC} architecture",
  volume =       "2",
  publisher =    pub-UNIV-VIDEO-COMM,
  address =      pub-UNIV-VIDEO-COMM:adr,
  year =         "1989",
  LCCN =         "VT1148 Protect",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "Title on container: The design and development of
                 SPARC. Sponsored by Sun Microsystems. Recorded July 19,
                 1989. Rosing presents the background of the business
                 environment during the development and introduction of
                 SPARC. Patterson discusses principles of RISC design
                 and interesting features of SPARC architecture.
                 Comments on historical perspectives and future
                 directions; also shows three SPARC boards running at
                 three clock rates progressively taking much more power
                 and board area.",
  series =       "Distinguished lecture series, industry leaders in
                 computer science and electrical engineering",
  acknowledgement = ack-nhfb,
  keywords =     "computer architecture",
}

@Book{Patterson:1990:CAQ,
  author =       "David A. Patterson and John L. Hennessy",
  title =        "Computer Architecture\emdash {A} Quantitative
                 Approach",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  pages =        "xxviii + 594",
  year =         "1990",
  ISBN =         "1-55860-069-8",
  ISBN-13 =      "978-1-55860-069-0",
  LCCN =         "QA76.9.A73 P377 1990",
  bibdate =      "Mon Jan 31 08:47:46 1994",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
}

@Book{Patterson:1994:COD,
  author =       "David A. Patterson and John L. Hennessy",
  title =        "Computer Organization and Design\emdash The
                 Hardware\slash Software Interface",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adrnew,
  pages =        "xxiv + 648",
  year =         "1994",
  ISBN =         "1-55860-281-X",
  ISBN-13 =      "978-1-55860-281-6",
  LCCN =         "QA76.9 .C643 P37 1994",
  bibdate =      "Wed Feb 2 00:08:32 1994",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$74.75",
  acknowledgement = ack-nhfb,
}

@Book{Patterson:1996:CAQ,
  author =       "David A. Patterson and John L. Hennessy",
  title =        "Computer Architecture\emdash {A} Quantitative
                 Approach",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  edition =      "Second",
  pages =        "xxiii + 760 + A-77 + B-47 + C-26 + D-26 + E-13 + R-16
                 + I-14",
  year =         "1996",
  ISBN =         "1-55860-329-8",
  ISBN-13 =      "978-1-55860-329-5",
  LCCN =         "QA76.9.A73P377 1995",
  bibdate =      "Mon May 20 10:01:59 2002",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$69.95",
}

@Book{Patterson:1997:COH,
  author =       "David A. Patterson and John L. Hennessy",
  title =        "Computer Organization: The Hardware\slash Software
                 Interface",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adrnew,
  edition =      "Second",
  pages =        "1000",
  year =         "1997",
  ISBN =         "1-55860-428-6 (hardcover), 1-55860-491-X (softcover)",
  ISBN-13 =      "978-1-55860-428-5 (hardcover), 978-1-55860-491-9
                 (softcover)",
  LCCN =         "QA76.9.C643H46 1997",
  bibdate =      "Thu Sep 11 07:05:47 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$78.95",
  acknowledgement = ack-nhfb,
}

@Book{Patterson:2002:CAQ,
  author =       "David A. Patterson and John L. Hennessy",
  title =        "Computer Architecture\emdash {A} Quantitative
                 Approach",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  edition =      "Third",
  pages =        "xxi + 883 + A-87 + B-42 + C-1 + D-1 + E-1 + F-1 + G-1
                 + H-1 + I-1 + R-22 + I-44",
  year =         "2002",
  ISBN =         "1-55860-596-7",
  ISBN-13 =      "978-1-55860-596-1",
  LCCN =         "????",
  bibdate =      "Fri May 31 15:46:29 2002",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$89.95",
  URL =          "http://www.mkp.com/books_catalog/catalog.asp?ISBN=1-55860-596-7;
                 http://www.mkp.com/CA3",
}

@Book{Paul:2000:SAA,
  author =       "Richard P. Paul",
  title =        "{SPARC} architecture, assembly language programming,
                 and {C}",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  edition =      "Second",
  pages =        "xviii + 505",
  year =         "2000",
  ISBN =         "0-13-025596-3 (paperback)",
  ISBN-13 =      "978-0-13-025596-9 (paperback)",
  LCCN =         "QA76.9.A73 P38 2000",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "assembler language (computer program language); C
                 (computer program language); Reduced Instruction Set
                 Computers",
}

@Article{Peleg:1996:MTE,
  author =       "Alex Peleg and Uri Weiser",
  title =        "{MMX} Technology Extension to the {Intel} Architecture
                 --- Improving multimedia and communications application
                 performance by 1.5 to 2 times",
  journal =      j-IEEE-MICRO,
  volume =       "16",
  number =       "4",
  pages =        "42--50",
  month =        aug,
  year =         "1996",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.526924",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  acknowledgement = ack-nhfb,
  classcodes =   "C5220P (Parallel architecture); C5130 (Microprocessor
                 chips)",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "communications; compatibility; Intel architecture;
                 microprocessor chips; MMX; multimedia; operating
                 systems; parallel architectures; SIMD",
  treatment =    "P Practical",
}

@Article{Peleg:1997:IMM,
  author =       "Alex Peleg and Sam Wilkie and Uri Weiser",
  title =        "{Intel MMX} for Multimedia {PCs}",
  journal =      j-CACM,
  volume =       "40",
  number =       "1",
  pages =        "24--38",
  month =        jan,
  year =         "1997",
  CODEN =        "CACMA2",
  ISSN =         "0001-0782 (print), 1557-7317 (electronic)",
  ISSN-L =       "0001-0782",
  bibdate =      "Mon Mar 03 09:22:52 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "See also Blinn's comments \cite{Blinn:1997:JBCa} about
                 MMX instruction set deficiencies",
  acknowledgement = ack-nhfb,
  fjournal =     "Communications of the ACM",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J79",
}

@InProceedings{Phillip:1998:ATS,
  author =       "Mike Phillip",
  title =        "{AltiVec} Technology: {A} Second Generation {SIMD}
                 Microprocessor Architecture",
  crossref =     "IEEE:1998:HCC",
  pages =        "??--??",
  year =         "1998",
  bibdate =      "Mon Jan 08 17:02:55 2001",
  bibsource =    "ftp://www.hotchips.org/pub/hotc7to11cd/hc98/pdf_1up/hc98_5c_phillip_1up.txt;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
}

@Article{Piepho:1989:CRA,
  author =       "Richard S. Piepho and William S. Wu",
  title =        "A Comparison of {RISC} Architectures",
  journal =      j-IEEE-MICRO,
  volume =       "9",
  number =       "4",
  pages =        "51--62",
  month =        aug,
  year =         "1989",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.31487",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  acknowledgement = ack-nhfb,
  affiliation =  "AT\&T Comput Syst, Naperville, IL, USA",
  classcodes =   "C5220 (Computer architecture)",
  classification = "714; 721; 722; 723",
  corpsource =   "AT\&T Comput. Syst., Naperville, IL, USA",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "architectural comparison; Computer Architecture;
                 Computer Operating Systems--Storage Allocation;
                 Computers, Microcomputer--Evaluation; Intel i860;
                 Microsystems Sparc; Motorola 88000; Performance
                 Evaluation; Reduced Instruction Set Computer (RISC);
                 reduced instruction set computing; RISC architectures;
                 Sun",
  treatment =    "P Practical",
}

@Book{Rahmel:1995:IPM,
  author =       "Ron Rahmel and Dan Rahmel",
  title =        "Interfacing to the {PowerPC} microprocessor",
  publisher =    pub-SAMS,
  address =      pub-SAMS:adr,
  pages =        "xiii + 476",
  year =         "1995",
  ISBN =         "0-672-30548-8",
  ISBN-13 =      "978-0-672-30548-1",
  LCCN =         "QA76.5.R2788 1995",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  acknowledgement = ack-nhfb,
  keywords =     "computer interfaces; PowerPC microprocessors",
}

@Article{Ramakrishnan:1992:SPP,
  author =       "S. Ramakrishnan",
  title =        "Software pipelining in {PA-RISC} compilers",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "43",
  number =       "3",
  pages =        "39--45",
  month =        jun,
  year =         "1992",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Tue Mar 25 14:12:15 MST 1997",
  bibsource =    "Compiler/Compiler.Lins.bib;
                 http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "The performance of programs with loops can be improved
                 by having the compiler generate code that overlaps
                 instructions from multiple iterations to exploit the
                 available instruction-level parallelism. This software
                 pipelining is supported on the HP 9000 Series 700 and
                 800 systems.",
  acknowledgement = ack-nhfb,
  affiliation =  "Hewlett--Packard Co., Palo Alto, CA, USA",
  classcodes =   "C6150C (Compilers, interpreters and other processors);
                 C6110P (Parallel programming)",
  classification = "C6110P (Parallel programming); C6150C (Compilers,
                 interpreters and other processors)",
  corpsource =   "Hewlett--Packard Co., Palo Alto, CA, USA",
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
  keywords =     "compilers; Hewlett Packard computers; HP 9000; HP 9000
                 Series 700; Instruction-level parallelism;
                 instruction-level parallelism; PA-RISC compilers;
                 pipeline processing; program; Series 700",
  thesaurus =    "Hewlett Packard computers; Pipeline processing;
                 Program compilers",
  treatment =    "P Practical",
}

@Book{Roberts:1992:TAL,
  author =       "John Roberts",
  title =        "Transputer assembly language programming",
  publisher =    pub-VNR,
  address =      pub-VNR:adr,
  pages =        "xiii + 288",
  year =         "1992",
  ISBN =         "0-442-00872-4",
  ISBN-13 =      "978-0-442-00872-7",
  LCCN =         "QA76.6 .R625 1992",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "parallel programming (computer science); transputers
                 --- programming",
}

@Book{Sanchez:1995:NPP,
  author =       "Julio Sanchez and Maria P. Canton",
  title =        "Numerical programming the 387, 486, and {Pentium}",
  publisher =    pub-MCGRAW-HILL,
  address =      pub-MCGRAW-HILL:adr,
  pages =        "xii + 511",
  year =         "1995",
  ISBN =         "0-07-911832-1",
  ISBN-13 =      "978-0-07-911832-5",
  LCCN =         "QA76.8.I2688 S36 1995",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "Intel 80387 (microprocessor) --- programming; Intel
                 80486 (microprocessor) --- programming; Pentium
                 (microprocessor) --- programming",
}

@Article{Santhanam:1992:RRP,
  author =       "V. Santhanam",
  title =        "Register reassociation in {PA-RISC} compilers",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "43",
  number =       "3",
  pages =        "33--38",
  month =        jun,
  year =         "1992",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Tue Mar 25 14:12:15 MST 1997",
  bibsource =    "Compiler/Compiler.Lins.bib;
                 http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "Register reassociation is a code improving
                 transformation that is applicable to program loops. The
                 basic idea is to rearrange expressions found within
                 loops to increase optimization opportunities, while
                 preserving the results computed. In particular,
                 register reassociation can expose loop-invariant
                 partial expressions in which intermediate results can
                 be computed outside the loop body and reused within the
                 loop. These optimization techniques added to PA-RISC
                 compilers result in the use of fewer machine
                 instructions to handle program loops.",
  acknowledgement = ack-nhfb,
  affiliation =  "Hewlett--Packard Co., Palo Alto, CA, USA",
  classcodes =   "C6150C (Compilers, interpreters and other
                 processors)",
  classification = "C6150C (Compilers, interpreters and other
                 processors)",
  corpsource =   "Hewlett--Packard Co., Palo Alto, CA, USA",
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
  keywords =     "code improving; Code improving transformation;
                 expressions; Intermediate results; intermediate
                 results; loop-invariant partial; Loop-invariant partial
                 expressions; optimisation; PA-RISC compilers; program
                 compilers; Program loops; program loops; storage
                 management; Subscript commutation; subscript
                 commutation; transformation",
  thesaurus =    "Optimisation; Program compilers; Storage management",
  treatment =    "P Practical",
}

@Article{Schlansker:2000:EEP,
  author =       "Michael S. Schlansker and B. Ramakrishna Rau Cover",
  title =        "{EPIC}: Explicitly Parallel Instruction Computing",
  journal =      j-COMPUTER,
  volume =       "33",
  number =       "2",
  pages =        "37--45",
  month =        feb,
  year =         "2000",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Mon Oct 30 19:18:20 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/computer2000.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://dlib.computer.org/co/books/co2000/pdf/r2037.pdf;
                 http://www.computer.org/computer/co2000/r2037abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "HP/Intel IA-64",
}

@Book{Schmit:1995:PPO,
  author =       "Michael L. Schmit",
  title =        "{Pentium} processor optimization tools",
  publisher =    pub-AP-PROFESSIONAL,
  address =      pub-AP-PROFESSIONAL:adr,
  pages =        "xv + 389",
  year =         "1995",
  ISBN =         "0-12-627230-1",
  ISBN-13 =      "978-0-12-627230-7",
  LCCN =         "QA 76.8 P46 S36 1995",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "Pentium (microprocessor)",
}

@MastersThesis{Schreiber:1995:CGP,
  author =       "David Schreiber",
  title =        "A code generator for the {PowerPC 601}",
  type =         "Thesis (M.S.)",
  school =       "University of California, Santa Cruz",
  address =      "Santa Cruz, CA, USA",
  pages =        "viii + 62",
  year =         "1995",
  LCCN =         "QA76.76.G46 S37 1995",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  acknowledgement = ack-nhfb,
  keywords =     "code generators; compiling (electronic computers);
                 Masters Theses --- University of California, Santa Cruz
                 -- 1995; programming languages (electronic computers)",
}

@Article{Schwarz:1999:GFP,
  author =       "E. M. Schwarz and C. A. Krygowski",
  title =        "The {S/390 G5} floating-point unit",
  journal =      j-IBM-JRD,
  volume =       "43",
  number =       "5/6",
  pages =        "707--721",
  month =        "????",
  year =         "1999",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Wed Apr 19 18:58:23 MDT 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ibmjrd.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.research.ibm.com/journal/rd/435/schwarz.html",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
}

@Article{Scott:1997:FSP,
  author =       "A. P. Scott and K. P. Burkhart and A. Kumar and R. M.
                 Blumberg and G. L. Ranson",
  title =        "Four-Way Superscalar {PA-RISC} Processors",
  journal =      j-HEWLETT-PACKARD-J,
  volume =       "48",
  number =       "4",
  pages =        "8--15",
  month =        aug,
  year =         "1997",
  CODEN =        "HPJOAX",
  ISSN =         "0018-1153",
  bibdate =      "Wed Mar 25 15:17:10 MST 1998",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/hpj.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.hp.com/hpj/97aug/au97a1.htm",
  abstract =     "The HP PA 8000 and PA 8200 PA-RISC CPUs are the first
                 implementations of a new generation of microprocessors
                 from Hewlett--Packard. The PA 8000 is among the world's
                 most powerful and advanced microprocessors, and at the
                 time of introduction in January 1996, the undisputed
                 performance leader. The PA 8200, introduced in June
                 1997, continues this performance leadership with higher
                 frequency larger caches, and several other
                 enhancements. Both processors feature an aggressive
                 four-way superscalar implementation, combining
                 speculative execution with on-the-fly instruction
                 reordering. This paper discusses the objectives for the
                 design of these processors, some of the key
                 architectural features, implementation details, and
                 system performance. The operation of the instruction
                 reorder buffer (IRB), which provides out-of-order
                 execution capability, is also described.",
  acknowledgement = ack-nhfb,
  classification = "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips); C5220 (Computer architecture)",
  fjournal =     "Hewlett-Packard Journal: technical information from
                 the laboratories of Hewlett-Packard Company",
  keywords =     "architectural features; CPUs; Hewlett Packard
                 computers; Hewlett--Packard; HP PA 8000; instruction
                 reorder buffer; microprocessor chips; microprocessors;
                 on-the-fly instruction reordering; out-of-order
                 execution capability; PA 8200; reduced instruction set
                 computing; speculative execution; superscalar PA-RISC
                 processors; system performance",
  treatment =    "P Practical",
}

@Book{Seal:2000:AAR,
  author =       "David Seal",
  title =        "{ARM} Architecture Reference Manual",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "????",
  year =         "2000",
  ISBN =         "0-201-73719-1",
  ISBN-13 =      "978-0-201-73719-6",
  LCCN =         "????",
  bibdate =      "Tue Jan 09 13:19:20 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$54.95",
  acknowledgement = ack-nhfb,
}

@Book{Shanley:1995:PSA,
  author =       "Tom Shanley",
  title =        "{PowerPC} system architecture",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "xli + 609",
  year =         "1995",
  ISBN =         "0-201-40990-9",
  ISBN-13 =      "978-0-201-40990-1",
  LCCN =         "QA76.8.P67 S47 1995",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  price =        "US\$34.95, CDN\$44.95",
  series =       "PC system architecture series",
  acknowledgement = ack-nhfb,
  keywords =     "computer architecture; PowerPC microprocessors",
}

@Book{Shanley:1997:PPP,
  author =       "Tom Shanley",
  title =        "{Pentium Pro} processor system architecture",
  publisher =    pub-AWDP,
  address =      pub-AWDP:adr,
  pages =        "xxxi + 526",
  year =         "1997",
  ISBN =         "0-201-47953-2",
  ISBN-13 =      "978-0-201-47953-9",
  LCCN =         "QA76.8.P46 P46 1997",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  series =       "PC system architecture series",
  acknowledgement = ack-nhfb,
  keywords =     "Pentium (microprocessor)",
}

@Book{Shanley:1998:PPP,
  author =       "Tom Shanley",
  title =        "{Pentium Pro} and {Pentium II} system architecture",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  edition =      "Second",
  pages =        "xxxv + 588",
  year =         "1998",
  ISBN =         "0-201-30973-4",
  ISBN-13 =      "978-0-201-30973-7",
  LCCN =         "QA76.8.P46 S48 1998",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  series =       "PC system architecture series",
  acknowledgement = ack-nhfb,
  keywords =     "Pentium (microprocessor)",
}

@Book{Shapiro:1999:IRS,
  author =       "Carl Shapiro and Hal R. Varian",
  title =        "Information Rules: {A} Strategic Guide to the Network
                 Economy",
  publisher =    "Harvard Business School Press",
  address =      "Boston, MA, USA",
  pages =        "x + 352",
  year =         "1999",
  ISBN =         "0-87584-863-X",
  ISBN-13 =      "978-0-87584-863-1",
  LCCN =         "HC79.I55 S53 1999",
  bibdate =      "Mon Dec 06 16:24:14 1999",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$29.95",
  acknowledgement = ack-nhfb,
}

@TechReport{Sharangpani:2000:IIP,
  author =       "Harsh Sharangpani",
  title =        "{Intel Itanium} Processor Microarchitecture Overview",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  year =         "2000",
  bibdate =      "Fri Jan 05 09:02:41 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/downloads/microarch_ovw.pdf",
  acknowledgement = ack-nhfb,
}

@Book{Sites:1995:AAA,
  author =       "Richard L. Sites and Richard L. Witek",
  title =        "{Alpha AXP} architecture reference manual",
  publisher =    pub-DP,
  address =      pub-DP:adr,
  edition =      "Second",
  pages =        "various",
  year =         "1995",
  ISBN =         "1-55558-145-5",
  ISBN-13 =      "978-1-55558-145-9",
  LCCN =         "QA76.9.A73A46 1995",
  bibdate =      "Thu Aug 07 13:41:17 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$52.95",
  acknowledgement = ack-nhfb,
}

@Article{Slegel:1999:IGM,
  author =       "Timothy J. Slegel and Robert M. {Averill III} and Mark
                 A. Check and Bruce C. Giamei and Barry W. Krumm and
                 Christopher A. Krygowski and Wen H. Li and John S.
                 Liptay and John D. MacDougall and Thomas J. McPherson
                 and Jennifer A. Navarro and Eric M. Schwarz and Kevin
                 Shum and Charles F. Webb",
  title =        "{IBM}'s {S/390 G5} Microprocessor Design",
  journal =      j-IEEE-MICRO,
  volume =       "19",
  number =       "2",
  pages =        "12--23",
  month =        mar # "\slash " # apr,
  year =         "1999",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.755464",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.computer.org/micro/mi1999/;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  URL =          "http://dlib.computer.org/mi/books/mi1999/pdf/m2012.pdf;
                 http://www.computer.org/micro/mi1999/m2012abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  xxtitle =      "{IBM's S/390 G5} Microprocessor",
}

@Article{Smith:1994:PAT,
  author =       "James E. Smith and Shlomo Weiss",
  title =        "{PowerPC} 601 and {Alpha} 21064: {A} Tale of Two
                 {RISCs}",
  journal =      j-COMPUTER,
  volume =       "27",
  number =       "6",
  pages =        "46--58",
  month =        jun,
  year =         "1994",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Mon Feb 3 07:28:57 MST 1997",
  bibsource =    "Compendex database;
                 http://www.math.utah.edu/pub/tex/bib/computer1990.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  abstract =     "Both PowerPC and Alpha are RISC architectures, but
                 they have little in common beyond that. The design
                 philosophy of one emphasizes powerful instructions, the
                 other simplicity.",
  acknowledgement = ack-nhfb,
  affiliation =  "Cray Res. Inc., Chippewa Falls, WI, USA",
  affiliationaddress = "Chippewa Falls, WI, USA",
  classification = "721.3; 722.1; 722.4; 723.1; C5220P (Parallel
                 architecture); C5440 (Multiprocessor systems and
                 techniques); C6140B (Machine-oriented languages)",
  conferenceyear = "1994",
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  journalabr =   "Computer",
  keywords =     "Access memory; Alpha 21064; Buffering; Cache memory;
                 Computer software; Data storage equipment; Digital
                 arithmetic; Digital Equipment Corporation; Floating
                 point instructions; High performance;
                 IBM/Motorola/Apple; Implementation philosophies;
                 Instruction sets; Load/store architecture;
                 Microprocessor chips; Out of order dispatch; Parallel
                 processing systems; Performance; Philosophical aspects;
                 Pipeline processing systems; Pipelined implementations;
                 PowerPC 601; Processing order; Program compilers;
                 Program debugging; Reduced instruction set computing;
                 RISC implementations; RISC microprocessors; Streamlined
                 implementation structure; Superscalar implementations;
                 User interfaces; Very fast clock; Virtual storage",
  publisherinfo = "IEEE Service Center",
  thesaurus =    "Instruction sets; Pipeline processing; Reduced
                 instruction set computing",
}

@Book{Somogyi:1994:PMB,
  author =       "Stephan Somogyi",
  title =        "The {PowerPC Macintosh} book: the inside story on the
                 new {RISC}-based {Macintosh}",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "xxiii + 227",
  year =         "1994",
  ISBN =         "0-201-62650-0",
  ISBN-13 =      "978-0-201-62650-6",
  LCCN =         "QA76.8.M3 S665 1994",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  acknowledgement = ack-nhfb,
  keywords =     "Macintosh (computer); RISC microprocessors",
}

@Book{Sparc:1992:SAM,
  author =       "{SPARC International}",
  title =        "The {SPARC} architecture manual: Version 8",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "xxix + 316",
  year =         "1992",
  ISBN =         "0-13-825001-4",
  ISBN-13 =      "978-0-13-825001-0",
  LCCN =         "QA76.9.A73 S63 1992 Bar",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  keywords =     "computer architecture",
}

@InProceedings{Story:1999:NAI,
  author =       "Shane Story and Ping Tak Peter Tang",
  title =        "New Algorithms for Improved Transcendental Functions
                 on {IA-64}",
  crossref =     "Koren:1999:ISC",
  pages =        "4--11",
  year =         "1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://developer.intel.com/design/ia-64/downloads/paper-118.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-118.pdf;
                 http://euler.ecs.umass.edu/paper/final/paper-118.ps",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH; computer arithmetic; IEEE",
}

@TechReport{Sun:1996:ACN,
  author =       "{Sun Microsystems}",
  title =        "Accelerating Core Networking Functions Using the
                 {UltraSPARC VIS} Instruction Set",
  type =         "Technical Report",
  number =       "{WPR-0013}",
  institution =  pub-SUN,
  address =      pub-SUN:adr,
  month =        aug,
  year =         "1996",
  bibdate =      "Tue Jan 09 14:17:53 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "Demonstrates speedups of 2x to 5x on key networking
                 kernels from use of the VIS instruction set.",
  URL =          "http://www.sun.com/microelectronics/whitepapers/wpr-0013/index.html",
  acknowledgement = ack-nhfb,
}

@TechReport{Sun:1996:UVI,
  author =       "{Sun Microsystems}",
  title =        "{UltraSPARC}: The {Visual Instruction Set} ({VIS}): On
                 Chip Support for New-Media Processing",
  type =         "Technical Report",
  number =       "{WPR-0004}",
  institution =  pub-SUN,
  address =      pub-SUN:adr,
  year =         "1996",
  bibdate =      "Tue Jan 09 14:20:20 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.sun.com/microelectronics/whitepapers/wpr-0004;
                 http://www.sun.com/microelectronics/whitepapers/wpr-0004/wpr-0004.pdf",
  acknowledgement = ack-nhfb,
}

@Manual{Sun:2000:SAL,
  title =        "{SPARC} Assembly Language Reference Manual",
  organization = pub-SUN,
  address =      pub-SUN:adr,
  month =        feb,
  year =         "2000",
  bibdate =      "Tue Jan 09 07:38:42 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "Part Number 806-3774. See Appendix E.6 for UltraSPARC
                 and VIS Instruction Set Extensions.",
  URL =          "ftp://192.18.99.138/806-3774/806-3774.pdf",
  acknowledgement = ack-nhfb,
}

@Book{Sweetman:1999:SMR,
  author =       "Dominic Sweetman",
  title =        "See {MIPS} run",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  pages =        "xviii + 488",
  year =         "1999",
  ISBN =         "1-55860-410-3",
  ISBN-13 =      "978-1-55860-410-0",
  LCCN =         "QA76.9.A73 S88 1999",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "embedded computer systems --- programming; MIPS
                 (computer architecture); RISC microprocessors",
}

@Manual{Sydow:1994:PP,
  author =       "Dan Parks Sydow",
  title =        "Programming the {PowerPC}",
  publisher =    pub-MT,
  address =      pub-MT:adr,
  pages =        "xxi + 410",
  year =         "1994",
  ISBN =         "1-55851-400-7",
  ISBN-13 =      "978-1-55851-400-3",
  LCCN =         "QA76.8.M3 S965 1994",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  series =       "New technology building blocks",
  acknowledgement = ack-nhfb,
  keywords =     "Macintosh (computer) --- programming; PowerPC
                 microprocessors --- programming",
}

@Article{Talia:1993:MRS,
  author =       "D. Talia",
  title =        "Message-Routing Systems for Transputer-Based
                 Multicomputers",
  journal =      j-IEEE-MICRO,
  volume =       "13",
  number =       "3",
  pages =        "62--72",
  month =        jun,
  year =         "1993",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.216749",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  acknowledgement = ack-nhfb,
  classcodes =   "C5220P (Parallel architecture); C5470 (Performance
                 evaluation and testing); C4230M (Multiprocessor
                 interconnection)",
  corpsource =   "CRAI, Rende, Italy",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "adaptivity; computer architecture; CSN; deadlock
                 freedom; freedom; generality; interval labeling;
                 livelock; message routing; Multiple Rings;
                 multiprocessor interconnection; network latency;
                 networks; Ordered Dimensions; performance evaluation;
                 routing; Tiny; transputer systems; transputer-based
                 multicomputers",
  treatment =    "P Practical",
}

@Article{Tremblay:1996:VSN,
  author =       "Marc Tremblay and J. Michael O'Connor and Venkatesh
                 Narayanan and Liang He",
  title =        "{VIS} Speeds New Media Processing --- Enhancing
                 conventional {RISC} instruction sets to significantly
                 accelerate media-processing algorithms",
  journal =      j-IEEE-MICRO,
  volume =       "16",
  number =       "4",
  pages =        "10--20",
  month =        aug,
  year =         "1996",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.526921",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  acknowledgement = ack-nhfb,
  classcodes =   "C6130B (Graphics techniques); C6140B (Machine-oriented
                 languages); C5220 (Computer architecture)",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "3D graphics environments; computer graphics;
                 computing; instruction sets; media processing;
                 media-processing algorithms; reduced instruction set;
                 RISC-; style instructions; UltraSparc; VIS; Visual
                 Instruction Set",
  treatment =    "P Practical",
}

@Article{Tremblay:2000:MAS,
  author =       "Marc Tremblay and Jeffrey Chan and Shailender Chaudhry
                 and Andrew W. Conigliaro and Shing Sheung Tse",
  title =        "The {MAJC} Architecture: {A} Synthesis of Parallelism
                 and Scalability",
  journal =      j-IEEE-MICRO,
  volume =       "20",
  number =       "6",
  pages =        "12--25",
  month =        nov # "\slash " # dec,
  year =         "2000",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.888700",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Tue Dec 12 15:27:04 MST 2000",
  bibsource =    "http://www.computer.org/micro/mi2000/;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://dlib.computer.org/mi/books/mi2000/pdf/m6012.pdf;
                 http://www.computer.org/micro/mi2000/m6012abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}

@Book{Triebel:1997:MPI,
  author =       "Walter A. Triebel and Avtar Singh",
  title =        "The 8088 and 8086 microprocessors: programming,
                 interfacing, software, hardware, and applications:
                 including the 80286, 80386, 80486, and the {Pentium}
                 processors",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  edition =      "Second",
  pages =        "x + 950",
  year =         "1997",
  ISBN =         "0-13-367897-0",
  ISBN-13 =      "978-0-13-367897-0",
  LCCN =         "QA76.8.I292 T77 1997",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "Intel 8086 (microprocessor); Intel 8088
                 (microprocessor)",
}

@Book{Triebel:1998:PPH,
  author =       "Walter A. Triebel",
  title =        "The 80386, 80486, and {Pentium} processors: hardware,
                 software, and interfacing",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "xii + 915",
  year =         "1998",
  ISBN =         "0-13-533225-7",
  ISBN-13 =      "978-0-13-533225-2",
  LCCN =         "QA76.8.I2684 T75 1998",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "Intel 80386 (microprocessor); Intel 80486
                 (microprocessor); Pentium (microprocessor)",
}

@Book{Triebel:2000:MPI,
  author =       "Walter A. Triebel and Avtar Singh",
  title =        "The 8088 and 8086 microprocessors: programming,
                 interfacing, software, hardware, and applications:
                 including the 80286, 80386, 80486, and Pentium
                 processors",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  edition =      "Third",
  pages =        "xiii + 978",
  year =         "2000",
  ISBN =         "0-13-010560-0",
  ISBN-13 =      "978-0-13-010560-8",
  LCCN =         "QA76.8.I29283 T74 2000",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "Intel 8086 (microprocessor); Intel 8088
                 (microprocessor)",
}

@Book{Tucker:1991:PM,
  author =       "Michael Tucker and Bruce Coorpender",
  title =        "Programming the {Motorola 88000}",
  publisher =    pub-WINDCREST,
  address =      pub-WINDCREST:adr,
  pages =        "xvii + 366",
  year =         "1991",
  ISBN =         "0-8306-3533-5",
  ISBN-13 =      "978-0-8306-3533-7",
  LCCN =         "QA76.8.M73 T83 1991",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  price =        "US\$24.95",
  acknowledgement = ack-nhfb,
  keywords =     "Motorola 88000 (microprocessor) --- programming",
}

@Article{Undy:1994:LCG,
  author =       "Steve Undy and Mick Bass and Dave Hollenbeck and Wayne
                 Kever and Larry Thayer",
  title =        "A Low-Cost Graphics and Multimedia Workstation Chip
                 Set",
  journal =      j-IEEE-MICRO,
  volume =       "14",
  number =       "2",
  pages =        "10--22",
  month =        apr,
  year =         "1994",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.272834",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Science Citation Index database (1980--2000)",
  abstract =     "Using system-level design and a high degree of
                 integration to introduce entry-level workstations based
                 on the PA7100LC processor",
  acknowledgement = ack-nhfb,
  classcodes =   "C5540 (Terminals and graphic displays); C5430
                 (Microcomputers); C5130 (Microprocessor chips)",
  corpsource =   "Hewlett--Packard Co., Fort Collins, CO, USA",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "Artist graphics controller; computer graphic
                 equipment; controller; graphical user interface;
                 graphics workstation; Hewlett Packard computers;
                 Hewlett--Packard; Hummingbird microprocessor;
                 microprocessor chips; multimedia workstation chip set;
                 video; workstations",
  treatment =    "P Practical",
  xxauthor =     "S. Undy and M. Mass and D. Hollenbeck and W. Kever and
                 L. Thayer",
}

@Article{Vaden:1994:DCP,
  author =       "M. T. Vaden and L. J. Merkel and C. R. Moore and T. M.
                 Potter and R. J. Reese",
  title =        "Design considerations for the {PowerPC} 601
                 microprocessor",
  journal =      j-IBM-JRD,
  volume =       "38",
  number =       "5",
  pages =        "605--620",
  month =        sep,
  year =         "1994",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Tue Mar 25 14:26:59 MST 1997",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/ibmjrd.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://www.almaden.ibm.com/journal/rd38-5.html#eleven",
  abstract =     "The PowerPC 601* microprocessor (601) is the first
                 member of a family of processors that support IBM's
                 PowerPC Architecture*. The 601 is a general-purpose
                 processor based on a superscalar design point. As with
                 any development effort, the 601 development program had
                 several different, often conflicting, design goals. The
                 most important requirements were support for the
                 PowerPC Architecture, a short development cycle,
                 competitive performance and cost, compatibility with
                 existing POWER applications, and support for
                 multiprocessing. This paper describes several aspects
                 of the 601 design and discusses some of the design
                 trade-offs considered in those areas.",
  acknowledgement = ack-nhfb,
  affiliation =  "IBM Corp., Austin, TX, USA",
  classcodes =   "C5430 (Microcomputers); C5440 (Multiprocessing
                 systems); C5220P (Parallel architecture)",
  classification = "C5220P (Parallel architecture); C5430
                 (Microcomputers); C5440 (Multiprocessing systems)",
  corpsource =   "IBM Corp., Austin, TX, USA",
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "architectures; competitive performance; Competitive
                 performance; design considerations; Design
                 considerations; design point; general-purpose
                 processor; General-purpose processor; IBM; IBM
                 computers; IBM PowerPC Architecture; multiprocessing;
                 Multiprocessing; multiprocessing systems; parallel;
                 PowerPC 601 microprocessor; PowerPC Architecture;
                 superscalar; Superscalar design point; workstations",
  thesaurus =    "IBM computers; Multiprocessing systems; Parallel
                 architectures; Workstations",
  treatment =    "P Practical; R Product Review",
}

@Book{vanSomeron:1993:ARC,
  author =       "Alex van Someron and Carol Atack",
  title =        "The {ARM RISC} Chip, {A} Programmer's Guide",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  pages =        "346 (est.)",
  year =         "1993",
  ISBN =         "0-201-62410-9",
  ISBN-13 =      "978-0-201-62410-6",
  LCCN =         "????",
  bibdate =      "Tue Jan 09 13:22:09 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$34.95",
  acknowledgement = ack-nhfb,
}

@Book{Venners:1997:IJV,
  author =       "Bill Venners",
  title =        "Inside the {Java} Virtual Machine",
  publisher =    pub-MCGRAW-HILL,
  address =      pub-MCGRAW-HILL:adr,
  pages =        "384",
  month =        nov,
  year =         "1997",
  ISBN =         "0-07-913248-0",
  ISBN-13 =      "978-0-07-913248-2",
  LCCN =         "QA76.73.J38 V46 1998",
  bibdate =      "Wed Jun 17 22:05:06 MDT 1998",
  bibsource =    "http://www.javaworld.com/javaworld/books/jw-books-alphabytitle.html;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 http://www.mcgraw-hill.com/",
  price =        "US\$39.95",
  URL =          "http://mcgraw-hill.inforonics.com/cgi/getarec?mgh31406%comp",
  acknowledgement = ack-nhfb,
}

@Book{VLSITechnology:1990:ARM,
  author =       "{VLSI Technology, Inc. Application Specific Logic
                 Products Division}",
  title =        "{Acorn RISC} machine {(ARM)} family data manual",
  publisher =    pub-PH,
  address =      pub-PH:adr,
  pages =        "various",
  year =         "1990",
  ISBN =         "0-13-781618-9",
  ISBN-13 =      "978-0-13-781618-7",
  LCCN =         "QA76.9.A73 A26 1990",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "computer architecture; Reduced Instruction Set
                 Computers (RISC)",
}

@Book{Weaver:1994:SAM,
  author =       "David L. Weaver and Tom Germond",
  title =        "The {SPARC} Architecture Manual{}\emdash{}Version 9",
  publisher =    pub-PHPTR,
  address =      pub-PHPTR:adr,
  pages =        "xxii + 357",
  year =         "1994",
  ISBN =         "0-13-099227-5",
  ISBN-13 =      "978-0-13-099227-7",
  LCCN =         "QA76.9.A73S648 1992",
  bibdate =      "Fri Jul 22 08:37:56 1994",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$33.00",
  acknowledgement = ack-nhfb,
}

@Article{Webb:2000:MD,
  author =       "C. F. Webb",
  title =        "{S/390} microprocessor design",
  journal =      j-IBM-JRD,
  volume =       "44",
  number =       "6",
  pages =        "899--907",
  month =        "????",
  year =         "2000",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Sat Feb 24 09:44:45 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 http://www.research.ibm.com/journal/",
  URL =          "http://www.research.ibm.com/journal/rd/446/webb.html",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  ordernumber =  "G322-0224",
}

@Book{Weiss:1994:PP,
  author =       "Shlomo Weiss and James E. Smith",
  title =        "{POWER} and {PowerPC}",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  pages =        "xvi + 408",
  year =         "1994",
  ISBN =         "1-55860-279-8",
  ISBN-13 =      "978-1-55860-279-3",
  LCCN =         "QA76.8.P67 W45 1994",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  acknowledgement = ack-nhfb,
  keywords =     "Power microprocessors; PowerPC microprocessors",
}

@Book{Weiss:1994:PPP,
  author =       "Shlomo Weiss and James E. Smith",
  title =        "{Power} and {PowerPC}: Principles, Architecture,
                 Implementation",
  publisher =    pub-MORGAN-KAUFMANN,
  address =      pub-MORGAN-KAUFMANN:adr,
  pages =        "xvi + 408",
  year =         "1994",
  ISBN =         "1-55860-279-8",
  ISBN-13 =      "978-1-55860-279-3",
  LCCN =         "QA76.8.P67 W45 1994",
  bibdate =      "Wed Aug 10 10:06:55 1994",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  price =        "US\$54.95",
  acknowledgement = ack-nhfb,
  keywords =     "Power microprocessors; PowerPC microprocessors",
}

@Article{Whitby-Strevens:1990:TPP,
  author =       "Colin Whitby-Strevens",
  title =        "Transputers --- Past, Present, and Future",
  journal =      j-IEEE-MICRO,
  volume =       "10",
  number =       "6",
  pages =        "16--19, 76--82",
  month =        dec,
  year =         "1990",
  CODEN =        "IEMIDZ",
  DOI =          "http://dx.doi.org/10.1109/40.62725",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Dec 14 06:08:58 MST 2000",
  bibsource =    "Compendex database;
                 http://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 Parallel/transputer.bib; Science Citation Index
                 database (1980--2000)",
  abstract =     "Enhancing performance of existing transputers, the
                 ESPRIT projects continue to develop the all-around
                 capabilities of this chip-- with a vision for its
                 future in general-purpose computing.",
  acknowledgement = ack-nhfb,
  affiliation =  "INMOS Ltd, Bristol, UK",
  classcodes =   "B1265F (Microprocessors and microcomputers); C5130
                 (Microprocessor chips)",
  classification = "718; 721; 722; 723",
  corpsource =   "INMOS Ltd., Bristol, UK",
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
  keywords =     "Computer Architecture--Research; Computer Systems,
                 Digital; Computers, Digital--Data Communication
                 Systems; esprit; ESPRIT Supernode project; European
                 MIMD architecture; European-led Open Microsystems; H1
                 transputers; high-; Initiative; mimd Architecture;
                 Modular Construction; Parallel Processing; performance
                 computer system; Supernode RTP; T800 floating-point
                 transputer; transputer development; transputers;
                 Transputers; virtual communications; VLSI
                 capabilities",
  treatment =    "G General Review; P Practical",
}

@Book{White:1994:IRS,
  editor =       "Steve White and John Reysa",
  title =        "{IBM RISC System\slash 6000} Technology: Volume {II}",
  publisher =    pub-IBM,
  address =      pub-IBM:adr,
  year =         "1994",
  bibdate =      "Fri Mar 18 10:25:19 1994",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "A partial draft is available via anonymous ftp to
                 \path|ibminet.awdpa.ibm.com| in the PostScript file
                 \path|/pub/rs6kpapers/techbook.ps|.",
  acknowledgement = ack-nhfb,
}

@Book{White:1994:PPT,
  editor =       "Steve White and John Reysa",
  title =        "{PowerPC} and {Power2}: Technical Aspects of the New
                 {IBM RISC System\slash 6000}",
  publisher =    pub-IBM-REDBOOKS,
  address =      pub-IBM-REDBOOKS:adr,
  pages =        "x + 237",
  year =         "1994",
  bibdate =      "Fri Jan 05 07:16:07 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/master.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "IBM order number SA23-2737-00.",
  acknowledgement = ack-nhfb,
  xxISBN =       "none",
  xxLCCN =       "none",
}

@Article{Wilkinson:1992:IBI,
  author =       "B. Wilkinson and L. S. Mulholland",
  title =        "An Implementation of the {BLAS} on the {i860}: {A
                 RISC} Approach to Software for {RISC} Devices",
  journal =      j-LECT-NOTES-COMP-SCI,
  volume =       "634",
  pages =        "283--??",
  year =         "1992",
  CODEN =        "LNCSD9",
  ISSN =         "0302-9743 (print), 1611-3349 (electronic)",
  ISSN-L =       "0302-9743",
  bibdate =      "Mon May 13 11:46:24 MDT 1996",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/lncs1992.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Lecture Notes in Computer Science",
}

@Article{Wu:1997:CSI,
  author =       "Amy Wu",
  title =        "Chip Shots {II}",
  journal =      j-DDJ,
  volume =       "22",
  number =       "1",
  pages =        "12--12",
  month =        jan,
  year =         "1997",
  CODEN =        "DDJOEB",
  ISSN =         "1044-789X",
  bibdate =      "Mon Dec 02 08:05:58 1996",
  bibsource =    "http://www.ddj.com/index/author/index.htm;
                 http://www.math.utah.edu/pub/tex/bib/dr-dobbs-1990.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "Short note about Sun's JavaChip silicon project, and
                 the picoJava I chip.",
  acknowledgement = ack-nhfb,
  fjournal =     "Dr. Dobb's Journal of Software Tools",
}

@Book{Young:1994:IGP,
  author =       "Jerry L. Young",
  title =        "Insider's guide to {PowerPC} computing",
  publisher =    pub-QUE,
  address =      pub-QUE:adr,
  pages =        "xvii + 362",
  year =         "1994",
  ISBN =         "1-56529-625-7 (paperback)",
  ISBN-13 =      "978-1-56529-625-1 (paperback)",
  LCCN =         "QA76.8.P67 Y68 1994",
  bibdate =      "Fri Jan 5 07:23:44 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog",
  price =        "US\$29.99",
  acknowledgement = ack-nhfb,
  keywords =     "microprocessors; PowerPC microprocessors",
}

@Article{Zahir:2000:CCD,
  author =       "Rumi Zahir and Jonathan Ross and Dale Morris and Drew
                 hess",
  title =        "{OS} and Compiler Considerations in the Design of the
                 {IA-64} Architecture",
  journal =      j-SIGPLAN,
  volume =       "35",
  number =       "11",
  pages =        "212--221",
  month =        nov,
  year =         "2000",
  CODEN =        "SINODQ",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Tue Jan 09 12:44:50 2001",
  bibsource =    "http://foothill.lcs.mit.edu/asplos2k/program.html;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 http://www.math.utah.edu/pub/tex/bib/sigplan2000.bib",
  URL =          "http://devresource.hp.com/devresource/Docs/TechPapers/IA64/IA64oscompilercon.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
}

@Article{Zheng:2000:PRI,
  author =       "Cindy Zheng and Carol Thompson",
  title =        "{PA-RISC} to {IA-64}: Transparent Execution, No
                 Recompilation",
  journal =      j-COMPUTER,
  volume =       "33",
  number =       "3",
  pages =        "47--52",
  month =        mar,
  year =         "2000",
  CODEN =        "CPTRB4",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Mon Oct 30 19:18:20 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/computer2000.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  URL =          "http://dlib.computer.org/co/books/co2000/pdf/r3047.pdf;
                 http://www.computer.org/computer/co2000/r3047abs.htm",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "Hewlett--Packard's Aries dynamic translator",
}

%%% ====================================================================
%%% Cross-referenced entries must come last:

@Proceedings{ACM:1989:PSN,
  editor =       "{ACM}",
  booktitle =    "Proceedings, Supercomputing '89: November 13--17,
                 1989, Reno, Nevada",
  title =        "Proceedings, Supercomputing '89: November 13--17,
                 1989, Reno, Nevada",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "xviii + 849",
  year =         "1989",
  ISBN =         "0-89791-341-8",
  ISBN-13 =      "978-0-89791-341-6",
  LCCN =         "QA 76.5 S87 1989",
  bibdate =      "Wed Aug 28 06:48:31 MDT 1996",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "IEEE 89CH2802-7.",
  acknowledgement = ack-nhfb,
  annote =       "89CM2802-7. ACM Order Number 415892. IEEE 89CH2802-7.
                 IEEE Computer Society Order Number 2021.",
  classification = "A0130C (Conference proceedings); A0270
                 (Computational techniques); A0500 (Statistical physics
                 and thermodynamics); A4700 (Fluid dynamics); B0100
                 (General electrical engineering topics); B0290
                 (Numerical analysis); B1130B (Computer-aided circuit
                 analysis and design); C4100 (Numerical analysis); C4240
                 (Programming and algorithm theory); C5440
                 (Multiprocessor systems and techniques); C5470
                 (Performance evaluation and testing); C6110B (Software
                 engineering techniques); C6150J (Operating systems);
                 C7000 (Computer applications)",
  keywords =     "benchmarking; computer applications; parallel
                 algorithms; parallel processing; performance
                 evaluation; performance measurements; performance
                 tools; pipeline processing; software environments;
                 supercomputer architectures; supercomputers ---
                 congresses; technology integration; vector algorithms",
}

@Proceedings{Annell:1992:NTA,
  editor =       "Lars Annell and Martin Torngren",
  booktitle =    "{Nordic} transputer applications: proceedings of the
                 {1st and 2nd Nordic Transputer Seminars}",
  title =        "{Nordic} transputer applications: proceedings of the
                 {1st and 2nd Nordic Transputer Seminars}",
  publisher =    pub-IOS,
  address =      pub-IOS:adr,
  pages =        "165",
  year =         "1992",
  ISBN =         "90-5199-070-7",
  ISBN-13 =      "978-90-5199-070-6",
  ISSN =         "0925-4986",
  LCCN =         "TK7895.T73 N67 1990",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  note =         "The First Nordic Transputer Seminar was held in Turku,
                 Finland, Oct. 6-7, 1990; the Second Nordic Transputer
                 Seminar was held in Trondheim, Norway, Nov. 8--9,
                 1991.",
  series =       "Transputer and occam engineering series",
  acknowledgement = ack-nhfb,
  keywords =     "transputers --- congresses",
}

@Proceedings{Askew:1988:OTR,
  editor =       "Charlie Askew",
  booktitle =    "{Occam} and the transputer: research and applications:
                 {OUG-9}: proceedings of the {9th occam User Group
                 Technical Meeting, 19--21 September [i.e., August]
                 1988, Southampton, UK}",
  title =        "{Occam} and the transputer: research and applications:
                 {OUG-9}: proceedings of the {9th occam User Group
                 Technical Meeting, 19--21 September [i.e., August]
                 1988, Southampton, UK}",
  publisher =    pub-IOS,
  address =      pub-IOS:adr,
  pages =        "viii + 175",
  year =         "1988",
  LCCN =         "QA 76.73 O2 O23 1988a",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "occam (computer program language) congresses; parallel
                 programming (computer science) --- congresses",
}

@Proceedings{Board:1990:TRA,
  editor =       "John A. Board",
  booktitle =    "Transputer research and applications 2: {NATUG-2},
                 proceedings of the {Second Conference of the North
                 American Transputer Users Group, October 18--19, 1989,
                 Durham, NC}",
  title =        "Transputer research and applications 2: {NATUG-2},
                 proceedings of the {Second Conference of the North
                 American Transputer Users Group, October 18--19, 1989,
                 Durham, NC}",
  publisher =    pub-IOS,
  address =      pub-IOS:adr,
  pages =        "ix + 451",
  year =         "1990",
  ISBN =         "90-5199-627-8",
  ISBN-13 =      "978-90-5199-627-2",
  LCCN =         "TK7895.N67 T74 1989a",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "computer input-output equipment; transputers ---
                 congresses",
}

@Proceedings{Cook:1999:ALT,
  editor =       "Barry M. Cook",
  booktitle =    "Architectures, languages and techniques for concurrent
                 systems: {WoTUG-22, proceedings of the 22nd World Occam
                 and Transputer User Group Technical Meeting, 11--14
                 April 1999, Keele, United Kingdom}",
  title =        "Architectures, languages and techniques for concurrent
                 systems: {WoTUG-22, proceedings of the 22nd World Occam
                 and Transputer User Group Technical Meeting, 11--14
                 April 1999, Keele, United Kingdom}",
  volume =       "57",
  publisher =    pub-OHMSHA,
  address =      pub-OHMSHA:adr,
  pages =        "viii + 279",
  year =         "1999",
  ISBN =         "90-5199-480-X (IOS Press), 4-274-90285-4 (Ohmsha)",
  ISBN-13 =      "978-90-5199-480-3 (IOS Press), 978-4-274-90285-7
                 (Ohmsha)",
  ISSN =         "1383-7575",
  LCCN =         "QA76.58 .W585 1999",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  series =       "Concurrent systems engineering series",
  acknowledgement = ack-nhfb,
  keywords =     "occam (computer program language) congresses; parallel
                 processing (electronic computers) -- congresses",
}

@Proceedings{Grebe:1990:PDT,
  editor =       "R. Grebe",
  booktitle =    "Parallele Datenverarbeitung mit dem {Transputer}: 1
                 {Transputer-Anwender-Treffen, TAT '89, Aachen, 25./26.
                 September 1989: proceedings}",
  title =        "Parallele Datenverarbeitung mit dem {Transputer}: 1
                 {Transputer-Anwender-Treffen, TAT '89, Aachen, 25./26.
                 September 1989: proceedings}",
  volume =       "237",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "viii + 240",
  year =         "1990",
  ISBN =         "0-387-52366-9 (U.S.)",
  ISBN-13 =      "978-0-387-52366-8 (U.S.)",
  LCCN =         "TK7895.T73 T729 1989 Bar",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  series =       "Informatik-Fachberichte",
  acknowledgement = ack-nhfb,
  keywords =     "parallel processing (electronic computers) --
                 congresses; transputers --- congresses",
}

@Proceedings{Grebe:1991:PDT,
  editor =       "R. Grebe and C. Ziemann",
  booktitle =    "Parallele Datenverarbeitung mit dem {Transputer}: 2
                 {Transputer-Anwender-Treffen, TAT '90, Aachen, 17./18.
                 September 1990: proceedings}",
  title =        "Parallele Datenverarbeitung mit dem {Transputer}: 2
                 {Transputer-Anwender-Treffen, TAT '90, Aachen, 17./18.
                 September 1990: proceedings}",
  volume =       "272",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "x + 300",
  year =         "1991",
  ISBN =         "0-387-53976-X (U.S.)",
  ISBN-13 =      "978-0-387-53976-8 (U.S.)",
  LCCN =         "QA76.58 .T73 1990 Bar",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  series =       "Informatik-Fachberichte",
  acknowledgement = ack-nhfb,
  keywords =     "parallel processing (electronic computers) --
                 congresses; transputers --- congresses",
}

@Proceedings{IEEE:1995:DPC,
  editor =       "{IEEE}",
  booktitle =    "{Digest of papers: Compcon '95: technologies for the
                 information superhighway: March 5--9, 1995, San
                 Francisco, CA, USA}",
  title =        "{Digest of papers: Compcon '95: technologies for the
                 information superhighway: March 5--9, 1995, San
                 Francisco, CA, USA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "xiv + 491",
  year =         "1995",
  ISBN =         "0-7803-2657-1 (hardcover), 0-8186-7029-0 (paperback),
                 0-7803-2658-X (microfiche)",
  ISBN-13 =      "978-0-7803-2657-6 (hardcover), 978-0-8186-7029-9
                 (paperback), 978-0-7803-2658-3 (microfiche)",
  ISSN =         "1063-6390",
  LCCN =         "QA 75.5 C58 1995",
  bibdate =      "Mon Aug 26 10:38:41 MDT 1996",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "IEEE Computer Society Press order number PR07029. IEEE
                 catalog number 95CH35737.",
  acknowledgement = ack-nhfb,
  sponsor =      "IEEE; Computer Society.",
}

@Proceedings{IEEE:1996:HCV,
  editor =       "IEEE",
  booktitle =    "Hot chips VIII: symposium record: Stanford University,
                 Stanford, California, August 18--20, 1996",
  title =        "Hot chips {VIII}: symposium record: Stanford
                 University, Stanford, California, August 18--20, 1996",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "????",
  year =         "1996",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Sat Jan 6 19:21:13 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 OCLC Proceedings database",
  acknowledgement = ack-nhfb,
  keywords =     "hot chips",
}

@Proceedings{IEEE:1997:HCI,
  editor =       "{IEEE}",
  booktitle =    "Hot Chips IX: Stanford University, Stanford,
                 California, August 24--26, 1997",
  title =        "Hot Chips {IX}: Stanford University, Stanford,
                 California, August 24--26, 1997",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "????",
  year =         "1997",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Mon Jan 08 05:05:12 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
}

@Proceedings{IEEE:1998:HCC,
  editor =       "{IEEE}",
  booktitle =    "Hot chips 10: conference record: August 16--18, 1998,
                 Memorial Auditorium, Stanford University, Palo Alto,
                 California",
  title =        "Hot chips 10: conference record: August 16--18, 1998,
                 Memorial Auditorium, Stanford University, Palo Alto,
                 California",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "????",
  year =         "1998",
  ISBN =         "????",
  ISBN-13 =      "????",
  LCCN =         "????",
  bibdate =      "Mon Jan 08 05:06:55 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  acknowledgement = ack-nhfb,
}

@Proceedings{Koren:1999:ISC,
  editor =       "Israel Koren and Peter Kornerup",
  booktitle =    "14th IEEE Symposium on Computer Arithmetic:
                 proceedings: April 14--16, 1999, Adelaide, Australia",
  title =        "14th {IEEE} Symposium on Computer Arithmetic:
                 proceedings: April 14--16, 1999, Adelaide, Australia",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "xi + 274",
  year =         "1999",
  ISBN =         "0-7803-5609-8, 0-7695-0116-8, 0-7695-0118-4",
  ISBN-13 =      "978-0-7803-5609-2, 978-0-7695-0116-1,
                 978-0-7695-0118-5",
  ISSN =         "1063-6889",
  LCCN =         "QA76.6 .S887 1999",
  bibdate =      "Mon Feb 7 07:28:26 MST 2000",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/microchip.bib",
  note =         "IEEE Computer Society Order Number PR00116. IEEE Order
                 Plan Catalog Number 99CB36336.",
  URL =          "http://computer.org/conferen/home/arith/;
                 http://www.ecs.umass.edu/ece/arith14/program.html",
  acknowledgement = ack-nhfb,
  annote =       "Also known as ARITH-14.",
  source =       "Computer arithmetic",
  sponsor =      "IEEE.",
}

@Proceedings{Kunii:1990:TOJ,
  editor =       "Toshiyasu Kunii and D. May",
  title =        "{Transputer\slash Occam Japan 3: proceedings of the
                 3rd Transputer\slash Occam International Conference,
                 17--18 May 1990, Tokyo, Japan}",
  publisher =    pub-IOS,
  address =      pub-IOS:adr,
  pages =        "ix + 308",
  year =         "1990",
  ISBN =         "90-5199-032-4",
  ISBN-13 =      "978-90-5199-032-4",
  LCCN =         "TK7895.T73 T728 1990",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  series =       "Transputer and occam engineering",
  acknowledgement = ack-nhfb,
  keywords =     "occam2 (computer program language) congresses;
                 parallel processing (electronic computers) ---
                 congresses; transputers --- congresses",
}

@Proceedings{Muntean:1988:PPT,
  editor =       "Traian Muntean",
  booktitle =    "Parallel programming of transputer based machines:
                 {OUG-7}: proceedings of the 7th occam User Group
                 Technical Meeting, 14-16 September 1987, Grenoble,
                 France",
  title =        "Parallel programming of transputer based machines:
                 {OUG-7}: proceedings of the 7th occam User Group
                 Technical Meeting, 14-16 September 1987, Grenoble,
                 France",
  publisher =    pub-IOS,
  address =      pub-IOS:adr,
  pages =        "x + 479",
  year =         "1988",
  LCCN =         "QA 76.73 O2 023 1987",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "occam (computer program language) congresses; parallel
                 programming (computer science) --- congresses",
}

@Proceedings{Stiles:1990:TRA,
  editor =       "G. S. Stiles",
  booktitle =    "Transputer research and applications 1: {NATUG-1,
                 proceedings of the First Conference of the North
                 American Transputer Users Group, April 5--6, 1989, Salt
                 Lake City, Utah}",
  title =        "Transputer research and applications 1: {NATUG-1,
                 proceedings of the First Conference of the North
                 American Transputer Users Group, April 5--6, 1989, Salt
                 Lake City, Utah}",
  publisher =    pub-IOS,
  address =      pub-IOS:adr,
  pages =        "viii + 158",
  year =         "1990",
  ISBN =         "90-5199-026-x",
  ISBN-13 =      "978-90-5199-026-3",
  LCCN =         "TK7895.N67 T74 1989",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "computer input-output equipment; transputers ---
                 congresses",
}

@Proceedings{Turner:1990:TTT,
  editor =       "Stephen J. Turner",
  booktitle =    "Tools and techniques for transputer applications:
                 {OUG-12: proceedings of the 12th occam User Group
                 Technical Meeting, 2--4 April 1990, Exeter, England}",
  title =        "Tools and techniques for transputer applications:
                 {OUG-12: proceedings of the 12th occam User Group
                 Technical Meeting, 2--4 April 1990, Exeter, England}",
  publisher =    pub-IOS,
  address =      pub-IOS:adr,
  pages =        "244",
  year =         "1990",
  ISBN =         "90-5199-029-4",
  ISBN-13 =      "978-90-5199-029-4",
  LCCN =         "TK7895.T73 O23 1990",
  bibdate =      "Fri Jan 5 11:51:46 MST 2001",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/microchip.bib;
                 University of California MELVYL catalog.",
  acknowledgement = ack-nhfb,
  keywords =     "occam (computer program language) congresses;
                 transputers --- congresses",
}