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Volume C-29, Number 1, January, 1980Anonymous Editor's Notice . . . . . . . . . . . . 1--1 T. G. Rauscher and P. M. Adams Microprogramming: a Tutorial and Survey of Recent Developments . . . . . . . . . 2--20 C. R. Jesshope The Implementation of Fast Radix $2$ Transforms on Array Processors . . . . . 20--27 H. Samet Efficient On-Line Proofs of Equalities and Inequalities of Formulas . . . . . . 28--32 A. Goundan and J. P. Hayes Design of Totally Fault Locatable Combinational Networks . . . . . . . . . 33--44 S. K. Mehra and J. W. Wong and J. C. Majithia A Comparative Study of Some Two-Processor Organizations . . . . . . 44--49 P. Cull Tours of Graphs, Digraphs, and Sequential Machines . . . . . . . . . . 50--54 K. L. Kodandapani and D. K. Pradhan Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets . . 55--59 R. M. M. Oberman Comments on ``Modular Replacement of Combinational Switching Networks'' . . . 59--60 D. C. Schmidt and G. Metze Authors' Reply . . . . . . . . . . . . . 60--61 Anonymous Call for Papers . . . . . . . . . . . . 61--61 Anonymous Call for Papers . . . . . . . . . . . . 61--61 Anonymous Call for Papers . . . . . . . . . . . . 61--61 Anonymous Information for Authors . . . . . . . . 61--61 Anonymous IEEE Computer Society Publications . . . 61--61
Anonymous Table of Contents . . . . . . . . . . . 65--65 Anonymous Foreword . . . . . . . . . . . . . . . . 66--67 G. L. Haviland and A. A. Tuszynski A CORDIC Arithmetic Processor Chip . . . 68--79 M. C. Rahier and P. G. A. Jespers Dedicated LSI for a Microprocessor-Controlled Hand-Carried OCR System . . . . . . . . . . . . . . . 79--88 Y. Kita and N. Yamaguchi and M. Sugie and S. Yoshizama The Development of a Bubble Memory Controller for Low-Cost File Use . . . . 89--96 M. Townsend and M. E. Hoff, Jr. and R. E. Holm An NMOS Microprocessor for Analog Signal Processing . . . . . . . . . . . . . . . 97--102 T. Funabashi and K. Takagi and T. Tsukada and H. Nakamura and M. Hara An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter . . . . . . 102--107 D. A. Patterson and C. H. Sequin Design Considerations for Single-Chip Computers of the Future . . . . . . . . 108--116 A. J. Weissberger An LSI Implementation of an Intelligent CRC Computer and Programmable Character Comparator . . . . . . . . . . . . . . . 116--124 R. A. Cliff Acceptable Testing of VLSI Components Which Contain Error Correctors . . . . . 125--134 J. Zeman and H. T. Nagle, Jr. A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic . . . . . . . . . . . . . . . 134--144 A. Mathialagan and N. N. Biswas Optimal Interconnections in the Design of Microprocessors and Digital Systems 145--149 J. A. Arulpragasam and R. A. Giggi and R. F. Lary and D. T. Sullivan and Chin-Chang Wu Modular Minicomputers Using Microprocessors . . . . . . . . . . . . 149--160 J. J. Lenahan and F. K. Fung Performance of Cooperative Loosely Coupled Microprocessor Architectures in an Interactive Data Base Task . . . . . 161--180 D. Tabak and G. J. Lipovski Move Architecture in Digital Controllers 180--190 K. W. Current High Density Integrated Computing Circuitry with Multiple Valued Logic . . 191--195 R. J. Inkol and S. G. Chamberlain Design and Realization of a Two-Level 64K Byte CCD Memory System for Microcomputer Applications . . . . . . . 195--199 R. A. Cliff Digital Multiplexing of Analog Data in a Microprocessor Controlled Data Acquisition System . . . . . . . . . . . 200--202 M. Kameyama and T. Higuchi Design of Dependent-Failure-Tolerant Microcomputer System Using Triple-Modular Redundancy . . . . . . . 202--206 J. F. Burnell and S. C. Crist and M. Arozullah Microprocessor Utilization in Satellite-Born Packet Switching . . . . 206--208 M. J. Ellis and G. R. Hovey and T. E. Stapinski MTEC: a Microprocessor System for Astronomical Telescope and Instrument Control . . . . . . . . . . . . . . . . 208--211 Anonymous Call for Papers . . . . . . . . . . . . 211--211 Anonymous Call for Papers . . . . . . . . . . . . 211--211 Anonymous IEEE Computer Society Publications . . . 211--211
D. S. Parker, Jr. Notes on Shuffle/Exchange-Type Switching Networks . . . . . . . . . . . . . . . . 213--222 M. A. Breuer and A. D. Friedman Functional Level Primitives in Test Generation . . . . . . . . . . . . . . . 223--235 J. D. Lesser and J. J. Shedletsky An Experimental Delay Test Generator for LSI Logic . . . . . . . . . . . . . . . 235--248 J. P. Hayes Testing Memories for Single-Cell Pattern-Sensitive Faults . . . . . . . . 249--254 S. Y. H. Su and E. DuCasse A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures . . . . . . . . . . . . . . . . 254--258 E. L. Johnson A Digital Quarter Square Multiplier . . 258--261 I. Koren and E. Sadeh A New Approach to the Evaluation of the Reliability of Digital Systems . . . . . 261--267 Anonymous Call for Papers . . . . . . . . . . . . 267--267 Anonymous Call for Papers . . . . . . . . . . . . 267--267 Anonymous IEEE Computer Society Publications . . . 267--267
M. D. Wagh and H. Ganesh A New Algorithm for Discrete Cosine Transform of Arbitrary Number of Points 269--277 A. P. Reeves A Systematically Designed Binary Array Processor . . . . . . . . . . . . . . . 278--287 V. K. Agarwal and G. M. Masson Generic Fault Characterizations for Table Look-Up Coverage Bounding . . . . 288--299 J. H. Jenkins and J. A. Howard Control Overhead --- A Performance Metric for Evaluating Control-Unit Designs . . . . . . . . . . . . . . . . 300--308 J. Bruno and J. W. Jones III and Kimming So Deterministic Scheduling with Pipelined Processors . . . . . . . . . . . . . . . 308--316 H. Kitajima A Symmetric Cosine Transform . . . . . . 317--323 R. V. Book and Sai Choi Kwan On Uniquely Decipherable Codes with Two Codewords . . . . . . . . . . . . . . . 324--325 R. W. Holgate and R. N. Ibbett An Analysis of Instruction-Fetching Strategies in Pipelined Computers . . . 325--329 V. E. Vickers and J. Silverman A Technique for Generating Specialized Gray Codes . . . . . . . . . . . . . . . 329--331 D. P. Maher On Fourier Transforms Over Extensions of Finite Rings . . . . . . . . . . . . . . 331--333 Anonymous IEEE Computer Society Publications . . . 333--333 Anonymous The 10th International Symposium on Multiple-Valued Logic . . . . . . . . . 333--333 P. S. Kamat Comments on ``An Algorithm for Fast Evaluation of Time Functions'' . . . . . 333--333 Anonymous 254: Proceedings: COMPCON 79 Fall ``Using Microprocessors --- Extending our Reach'' . . . . . . . . . . . . . . 333--b Anonymous Proceedings of the Conference on Specifications of Reliable Software . . 333--a Anonymous 256 Proceedings: Symposium on Machine Processing of Remotely Sensed Data . . . 333--c
M. R. Brown and D. P. Dobkin An Improved Lower Bound on Polynomial Multiplication . . . . . . . . . . . . . 337--340 E. E. Swartzlander, Jr. and B. K. Gilbert Arithmetic for Ultra-High-Speed Tomography . . . . . . . . . . . . . . . 341--353 Y. Wallach and V. Konrad On Block-Parallel Methods for Solving Linear Equations . . . . . . . . . . . . 354--359 R. A. Finkel and M. H. Solomon Processor Interconnection Strategies . . 360--371 Chin-Hwa Lee Queueing Analysis of Global Locking Synchronization Schemes for Multicopy Databases . . . . . . . . . . . . . . . 371--384 H. Jafari and T. G. Lewis and J. D. Spragins Simulation of a Class of Ring-Structured Networks . . . . . . . . . . . . . . . . 385--392 D. D. Gajski Parallel Compressors . . . . . . . . . . 393--398 W. W. Warlick, Jr. and J. E. Hershey High-Speed $M$-Sequence Generators . . . 398--400 K. W. Current Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders . . . . . . . . . . . . . . . . . 400--403 K. W. Current A High Data-Rate Digital Output Correlator Design . . . . . . . . . . . 403--405 T. Tamesada Sequential Machines Having Quasi-Stable States . . . . . . . . . . . . . . . . . 405--408 D. R. Morgan Autocorrelation Function of Sequential $M$-Bit Words Taken from an $N$-Bit Shift Register (PN) Sequence . . . . . . 408--410 J. Savir Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection . . . 410--416 Anonymous Call for papers . . . . . . . . . . . . 416--416 Anonymous IEEE Computer Society Publications . . . 416--416
J. J. Stiffler Fault-Tolerant Computing: An Introduction . . . . . . . . . . . . . . 417--419 D. S. Suk and S. M. Reddy Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories . . 419--429 S. M. Thatte and J. A. Abraham Test Generation for Microprocessors . . 429--441 J. Savir Syndrome-Testable Design of Combinational Circuits . . . . . . . . . 442--451 M. Abramovici and M. A. Breuer Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis . . . . . . . . . 451--460 S. Mallela and G. M. Masson Diagnosis Without Repair for Hybrid Fault Situations . . . . . . . . . . . . 461--470 D. K. Pradhan A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications . . 471--481 B. E. Ossfeldt and I. Jonsson Recovery and Diagnostics in the Central Control of the AXE Switching System . . 482--491 R. M. Sedmak and H. L. Liebergot Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration . . . . . . . . . . . . . . 492--500 J. F. Meyer and D. G. Furchtgott and L. T. Wu Performability Evaluation of the SIFT Computer . . . . . . . . . . . . . . . . 501--509 J. E. Smith Measures of the Effectiveness of Fault Signature Analysis . . . . . . . . . . . 510--514 R. David and P. Thevenod-Fosse Minimal Detecting Transition Sequences: Application to Random Testing . . . . . 514--518 V. K. Agarwal Multiple Fault Detection in Programmable Logic Arrays . . . . . . . . . . . . . . 518--522 M. Karpovsky and S. Y. H. Su Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines . . . . . . . . . . . . . . 523--527 J. Galiay and Y. Crouzet and M. Vergniault Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability . . . . . . . . . . . . . . 527--531 Y. Crouzet and C. Landrault Design of Self-Checking MOS--LSI Circuits: Application to a Four-Bit Microprocessor . . . . . . . . . . . . . 532--537 D. Etiemble Multivalued I$^2$L Circuits for TSC Checkers . . . . . . . . . . . . . . . . 537--540 L. Simoncini and F. Saheban and A. D. Friedman Design of Self-Diagnosable Multiprocessor Systems with Concurrent Computation and Diagnosis . . . . . . . 540--546 P. A. Lee and N. Ghani and K. Heron A Recovery Cache for the PDP-11 . . . . 546--549 Anonymous Call for Papers . . . . . . . . . . . . 549--549 Anonymous IEEE Computer Society Publications . . . 549--549 Anonymous 249 4th International Conference on Software Engineering . . . . . . . . . . 549--c Anonymous 254: Proceedings: COMPCON 79 Fall ``Using Microprocessors --- Extending our Reach'' . . . . . . . . . . . . . . 549--a Anonymous Proceedings of the Conference on Specifications of Reliable Software . . 549--b
Kin-Man Chung and F. Luccio and C. K. Wong On the Complexity of Sorting in Magnetic Bubble Memory Systems . . . . . . . . . 553--563 F. L. Van Scoy The Parallel Recognition of Classes of Graphs . . . . . . . . . . . . . . . . . 563--570 J. L. Bentley and D. Wood An Optimal Worst Case Algorithm for Reporting Intersections of Rectangles 571--577 H. Hagiwara and S. Tomita and S. Oyanagi and K. Shibayama A Dynamically Microprogrammable Computer with Low-Level Parallelism . . . . . . . 577--595 S. S. Lam Packet Broadcast Networks --- A Performance Analysis of the R-ALOHA Protocol . . . . . . . . . . . . . . . . 596--603 T. T. Dao and M. Davio and C. Gossart Complex Number Arithmetic with Odd-Valued Logic . . . . . . . . . . . . 604--611 S. T. Chanson and P. S. Sinha Optimization of Memory Hierarchies in Multiprogrammed Computer Systems With Fixed Cost Constraint . . . . . . . . . 611--618 F. Y. Chin and K. S. Fok Fast Sorting Algorithms on Uniform Ladders (Multiple Shift-Register Loops) 618--631 O. Wing and J. W. Huang A Computation Model of Parallel Solution of Linear Equations . . . . . . . . . . 632--638 B. I. Dervisoglu and H. A. Sholl Theory and Design of Mixed-Mode Sequential Machines . . . . . . . . . . 639--648 J. C. Sutton III and J. G. Bredeson Minimal Redundant Logic for High Reliability and Irredundant Testability 648--656 W. A. Porter Polylogic Realization of Switching Functions . . . . . . . . . . . . . . . 657--659 C. R. Jesshope Some Results Concerning Data Routing in Array Processors . . . . . . . . . . . . 659--662 M. A. Tapia and J. H. Tucker Complete Solution of Boolean Equations 662--665 B. Bose and T. R. N. Rao Separating and Completely Separating Systems and Linear Codes . . . . . . . . 665--668 R. David Testing by Feedback Shift Register . . . 668--673 J. Savir Detection of Single Intermittent Faults in Sequential Circuits . . . . . . . . . 673--678 Anonymous Compcon 80 Fall . . . . . . . . . . . . 678--678 Anonymous IEEE Computer Society Publications . . . 678--678 Anonymous 254: Proceedings: COMPCON 79 Fall ``Using Microprocessors --- Extending our Reach'' . . . . . . . . . . . . . . 678--a Anonymous Proceedings of the Conference on Specifications of Reliable Software . . 678--b
I. Nishioka and T. Kurimoto and S. Yamamoto and T. Chiba and I. Shirakawa and H. Ozaki An Approach to Gate Assignment and Module Placement for Printed Wiring Boards . . . . . . . . . . . . . . . . . 681--688 S. S. L. Chang Multiple-Read Single-Write Memory and Its Applications . . . . . . . . . . . . 689--694 Chuan-Lin Wu and Tse-Yun Feng On a Class of Multistage Interconnection Networks . . . . . . . . . . . . . . . . 694--702 J. Weglarz Multiprocessor Scheduling with Memory Allocation --- a Deterministic Approach 703--709 G. P. Engelberg and J. A. Howard and D. A. Mellichamp Job Scheduling in a Single-Node Hierarchical Network for Process Control 710--719 J. F. Meyer On Evaluating the Performability of Degradable Computing Systems . . . . . . 720--731 M. Yamamoto A Method for Minimizing Incompletely Specified Sequential Machines . . . . . 732--736 J. H. Patel An Alternative to the Distributed Pipeline . . . . . . . . . . . . . . . . 736--737 P. Klein and M. S. Paterson Asymptotically Optimal Circuit for a Storage Access Function . . . . . . . . 737--738 R. W. Heuft and W. D. Little Convolution Computer . . . . . . . . . . 738--740 C. K. Yuen Negabinary A/D Conversion . . . . . . . 740--741 K. E. Stoffers Test Sets for Combinational Logic --- The Edge-Tracing Approach . . . . . . . 741--746 E. W. Page Minimally Testable Reed--Muller Canonical Forms . . . . . . . . . . . . 746--750 J. C. Muzio Composite Spectra and the Analysis of Switching Circuits . . . . . . . . . . . 750--753 N. M. Martin and S. P. Hufnagel Conditional-Sum Early Completion Adder Logic . . . . . . . . . . . . . . . . . 753--756 Ya. I. Fet Comments on ``A Design of a Fast Cellular Associative Memory for Ordered Retrieval'' . . . . . . . . . . . . . . 756--757 C. V. Ramamoorthy and J. L. Turner and B. W. Wah Authors' Reply . . . . . . . . . . . . . 757--757 W. Coy A Remark on the Nonminimality of Certain Multiple Fault Detection Algorithms . . 757--759 Anonymous Advance Announcement: Tutorial Week 80 759--759 Anonymous Call for Papers . . . . . . . . . . . . 759--759 Anonymous IEEE Computer Society Publications . . . 759--759 D. C. Bossen and S. J. Hong Author's Reply . . . . . . . . . . . . . 759--759 P. Corsini and G. Frosini Correction to ``Properties of the Multidimensional Generalized Discrete Fourier Transform'' . . . . . . . . . . 759--759
Anonymous Editor's Notice . . . . . . . . . . . . 761--761 O. N. Garcia Foreword Parallel Processing Today . . . 762--763 D. A. Padua and D. J. Kuck and D. H. Lawrie High-Speed Multiprocessors and Compilation Techniques . . . . . . . . . 763--776 D. K. Pradhan and K. L. Kodandapani A Uniform Representation of Single-and Multistage Interconnection Networks Used in SIMD Machines . . . . . . . . . . . . 777--791 H. J. Siegel The Theory Underlying the Partitioning of Permutation Networks . . . . . . . . 791--801 Chuan-Lin Wu and Tse-Yun Feng The Reverse-Exchange Interconnection Network . . . . . . . . . . . . . . . . 801--811 C. S. Ellis Concurrent Search and Insertion in AVL Trees . . . . . . . . . . . . . . . . . 811--817 O. I. El-Dessouki and W. H. Huen Distributed Enumeration on Between Computers . . . . . . . . . . . . . . . 818--825 S. J. Allan and A. E. Oldehoeft A Flow Analysis Procedure for the Translation of High-Level Languages to a Data Flow Language . . . . . . . . . . . 826--831 K. Hwang and L. M. Ni Resource Optimization of a Parallel Computer for Multiple Vector Processing 831--836 K. E. Batcher Design of a Massively Parallel Processor 836--840 A. P. Reeves and J. D. Bruner Efficient Function Implementation for Bit-Serial Parallel Processors . . . . . 841--844 Anonymous Advance Announcement: Tutorial Week 80 844--844 Anonymous IEEE Computer Society Publications . . . 844--844
King-Sun Fu Recent Developments in Pattern Recognition . . . . . . . . . . . . . . 845--854 G. Bongiovanni and F. Luccio Maintaining Sorted Files in a Magnetic Bubble Memory . . . . . . . . . . . . . 855--863 K. M. Chung and F. Luccio and C. K. Wong A Tree Storage Scheme for Magnetic Bubble Memories . . . . . . . . . . . . 864--874 R. B. Tilove Set Membership Classification: a Unified Approach to Geometric Intersection Problems . . . . . . . . . . . . . . . . 874--883 P. G. Jansen and J. L. W. Kessels The DIMOND: a Component for the Modular Construction of Switching Networks . . . 884--889 A. S. Wojcik and Kwang-Ya Fang On the Design of Three-Valued Asynchronous Modules . . . . . . . . . . 889--898 G. A. Jullien Implementation of Multiplication, Modulo a Prime Number, with Applications to Number Theoretic Transforms . . . . . . 899--905 K. P. Gostelow and R. E. Thomas Performance of a Simulated Dataflow Computer . . . . . . . . . . . . . . . . 905--919 S. A. Elkind and D. P. Siewiorek Reliability and Performance of Error-Correcting Memory and Register Arrays . . . . . . . . . . . . . . . . . 920--927 G. Lotti and F. Romani Application of Approximating Algorithms to Boolean Matrix Multiplication . . . . 927--928 H. T. Mouftah and K. C. Smith and Z. G. Vranesic Ternary Rate-Multipliers . . . . . . . . 929--931 M. Davio Read-Only Memory Implementation of Discrete Functions . . . . . . . . . . . 931--934 U. Manber System Diagnosis with Repair . . . . . . 934--937 J. R. Armstrong The Complexity of Computational Circuits Versus Radix . . . . . . . . . . . . . . 937--941 L. Dadda Composite Parallel Counters . . . . . . 942--946 E. E. Swartzlander, Jr. Merged Arithmetic . . . . . . . . . . . 946--950 S. Leinward and T. Lamdan Dynamic Boolean Algebras . . . . . . . . 950--953 Anonymous Advance Announcement: Tutorial Week 80 953--953 Anonymous IEEE Computer Society Press . . . . . . 953--953 Anonymous IEEE Computer Society Publications . . . 953--953 Anonymous IEEE Computer Society Press . . . . . . 953--953 Anonymous IEEE Computer Society Publications . . . 953--953 J. W. Stoughton Modification of ``A Least Mean Squares Cubic Algorithm for On-Line Differential of Sampled Analog Signals'' . . . . . . 953--953
K. L. Doty and J. D. Greenblatt and Stanley Y. W. Su Magnetic Bubble Memory Architectures for Supporting Associative Searching of Relational Databases . . . . . . . . . . 957--970 W. W. Chu and M. Y.-C. Shen A Hierarchical Routing and Flow Control Policy (HRFC) for Packet Switched Networks . . . . . . . . . . . . . . . . 971--977 A. Goundan and J. P. Hayes Identification of Equivalent Faults in Logic Networks . . . . . . . . . . . . . 978--985 A. Kandel and J. M. Francioni On the Properties and Applications of Fuzzy-Valued Switching Functions . . . . 986--994 N. K. Samari and G. M. Schneider A Queueing Theory-Based Analytic Model of a Distributed Computer Network . . . 994--1001 Ying Wang and A. A. Avizienis A Unified Reliability Model for Fault-Tolerant Computers . . . . . . . . 1002--1011 Anonymous Correction to ``Syndrome-Testable Design of Combinational Circuits'' . . . . . . 1012--1013 S. C. Crist Synthesis of Combinational Logic Using Decomposition and Probability . . . . . 1013--1016 J. M. Glass An Efficient Method for Improving Reliability of a Pipeline FFT . . . . . 1017--1020 K. K. Saluja Synchronous Sequential Machines: a Modular and Testable Design . . . . . . 1020--1025 S. Dasgupta and C. R. P. Hartmann and L. D. Rudolph Dual-Mode Logic for Function-Independent Fault Testing . . . . . . . . . . . . . 1025--1029 K. M. Chung and C. K. Wong Construction of a Generalized Connector with $5.8 n \log_2 n$ Edges . . . . . . 1029--1032 D. P. Agrawal On Negabinary-Binary Arithmetic Relationships and Their Hardware Reciprocity . . . . . . . . . . . . . . 1032--1035 Anonymous Advance Announcement: Tutorial Week 80 1035--1035 Anonymous IEEE Computer Society Publications . . . 1035--1035 Anonymous Machine Processing of Remotely Sensed Data . . . . . . . . . . . . . . . . . . 1035--a
W. W. Chu Introduction . . . . . . . . . . . . . . 1037--1038 R. R. Razouk and G. Estrin Modeling and Verification of Communication Protocols in Sara: The X.21 Interface . . . . . . . . . . . . . 1038--1052 P. Kermani and L. Kleinrock A Tradeoff Study of Switching Systems in Computer Communication Networks . . . . 1052--1060 G. Gardarin and W. W. Chu A Distributed Control Algorithm for Reliably and Consistently Updating Replicated Databases . . . . . . . . . . 1060--1068 P. P.-S. Chen and J. Akoka Optimal Design of Distributed Information Systems . . . . . . . . . . 1068--1080 M. J. Flynn and J. L. Hennessy Parallelism and Representation Problems in Distributed Systems . . . . . . . . . 1080--1086 M. J. Gonzalez, Jr. and B. W. Jordan, Jr. A Framework for the Quantitative Evaluation of Distributed Computer Systems . . . . . . . . . . . . . . . . 1087--1094 J. R. McGraw Data Flow Computing --- Software Development . . . . . . . . . . . . . . 1095--1103 R. G. Smith The Contract Net Protocol: High-Level Communication and Control in a Distributed Problem Solver . . . . . . . 1104--1113 S. I. Kartashev and S. P. Kartashev Problems of Designing Supersystems with Dynamic Architectures . . . . . . . . . 1114--1132 L. D. Wittle and A. M. Van Tilborg MICROS, A Distributed Operating System for Micronet, A Reconfigurable Network Computer . . . . . . . . . . . . . . . . 1133--1144 V. R. Lesser and L. D. Erman Distributed Interpretation: a Model and Experiment . . . . . . . . . . . . . . . 1144--1163 Anonymous Announcement & Call for Papers . . . . . 1163--1163 Anonymous Call for Papers . . . . . . . . . . . . 1163--1163 Anonymous Call for Papers Trends and Applications 1163--1163 Anonymous IEEE Computer Society Publications . . . 1163--1163 Anonymous 1980 Index IEEE Transactions on Computers Vol. C-29 . . . . . . . . . . 1163--1163
Anonymous Editor's Notice . . . . . . . . . . . . 169--171 L. Snyder Formal Models of Capability-Based Protection Systems . . . . . . . . . . . 172--181 T. Ibaraki and T. Kameda and S. Toida On Minimal Test Sets for Locating Single Link Failures in Networks . . . . . . . 182--190 D. D. Gajski An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines . . . . . . . . . . . 190--206 S. H. Bokhari On the Mapping Problem . . . . . . . . . 207--214 P. Goel An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits . . . . . . . . . . . . . . . . 215--222 W. F. McColl Planar Crossovers . . . . . . . . . . . 223--225 W. R. English Synthesis of Finite State Algorithms in a Galois Field $\mathrm{GF}[p^n]$ . . . 225--229 M. Tanaka and S. Ozawa and S. Mori Rewritable Programmable Logic Array of Current Mode Logic . . . . . . . . . . . 229--234 Sung Je Hong Existence Algorithms for Synchronizing/Distinguishing Sequences 234--237 A. Sengupta and D. K. Chattopadhyay and A. Palit and A. K. Bandyopadhyay and A. K. Choudhury Realization of Fault-Tolerant Machines --- Linear Code Application . . . . . . 237--240 Anonymous Advance Announcement: Tutorial Week East 81 . . . . . . . . . . . . . . . . . . . 241--241 Anonymous Call for Papers . . . . . . . . . . . . 241--241 Anonymous Call for Papers . . . . . . . . . . . . 241--241 Anonymous IEEE Computer Society Publications . . . 241--241 G. Wustmann Comments on ``Autocorrelation Function of Sequential $M$-Bit Words Taken from an $N$-Bit Shift Register (PN) Sequence'' . . . . . . . . . . . . . . . 241--241 Anonymous Computer Software Professional . . . . . 241--c
H. J. Siegel Interconnection Networks for Parallel and Distributed Processing: An Overview 245--246 E. Horowitz and A. Zorat The Binary Tree as an Interconnection Network: Applications to Multiprocessor Systems and VLSI . . . . . . . . . . . . 247--253 S. B. Wu and M. T. Liu A Cluster Structure as an Interconnection Network for Large Multimicrocomputer Systems . . . . . . . 254--264 L. D. Wittie Communication Structures for Large Networks of Microcomputers . . . . . . . 264--273 D. M. Dias and J. R. Jump Analysis and Simulation of Buffered Delta Networks . . . . . . . . . . . . . 273--282 M. A. Franklin VLSI Performance Comparison of Banyan and Crossbar Communications Networks . . 283--291 B. W. Arden and Hikyu Lee Analysis of Chordal Ring Network . . . . 291--295 Pen-Chung Yew and D. H. Lawrie An Easily Controlled Network for Frequently Used Permutations . . . . . . 296--298 J. E. Wirsching and T. Kishi CONET: a Connection Network Model . . . 298--301 Anonymous Call for Papers . . . . . . . . . . . . 301--301 Anonymous Call for Papers . . . . . . . . . . . . 301--301 Anonymous Call for Papers Special Issue on Supersystems . . . . . . . . . . . . . . 301--301 Anonymous IEEE Computer Society Publications . . . 301--301 Anonymous Computer Software Professional . . . . . 301--c
T. Uehara and W. M. Vancleemput Optimal Layout of CMOS Functional Arrays 305--312 I. Koren and Y. Maliniak On Classes of Positive, Negative, and Imaginary Radix Number Systems . . . . . 312--317 W. W. Chu and G. Fayolle and D. G. Hibbits An Analysis of a Tandem Queueing System for Flow Control in Computer Networks 318--324 Chuan-Lin Wu and Tse-Yun Feng The Universality of the Shuffle-Exchange Network . . . . . . . . . . . . . . . . 324--332 D. Nassimi and S. Sahni A Self-Routing Benes Network and Parallel Permutation Algorithms . . . . 332--340 W. Abu-Sufah and D. J. Kuck and D. H. Lawrie On the Performance Enhancement of Paging Systems Through Program Analysis and Transformations . . . . . . . . . . . . 341--356 Se June Hong and D. L. Ostapko A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks 356--358 D. M. Kodek Conditions for the Existence of Fast Number Theoretic Transforms . . . . . . 359--360 N. V. Murray Some Observations on Equivalence Handling Methods . . . . . . . . . . . . 361--362 A. Proskurowski Minimum Broadcast Trees . . . . . . . . 363--366 P. S.-P. Wang Finite-Turn Repetitive Checking Automata and Sequential/Parallel Matrix Languages 366--370 A. Y. Wu and A. Rosenfeld SIMD Machines and Cellular $d$-Graph Automata . . . . . . . . . . . . . . . . 370--372 Anonymous Call for Papers . . . . . . . . . . . . 372--372 Anonymous IEEE Computer Society Publications . . . 372--372 R. G. Smith Correction to ``The Contract Net Protocol: High-Level Communication and Control in a Distributed Problem Solver'' . . . . . . . . . . . . . . . . 372--372
T. Baba and H. Hagiwara The MPG System: a Machine-Independent Efficient Microprogram Generator . . . . 373--395 D. T. Lee and Hsu Chang and C. K. Wong An On-Chip Compare/Steer Bubble Sorter 396--405 J. Labetoulle and G. Pujolle HDLC Throughput and Response Time for Bidirectional Data Flow with Nonuniform Frame Sizes . . . . . . . . . . . . . . 405--413 Kyung-Yong Chwa and S. L. Hakimi On Fault Identification in Diagnosable Systems . . . . . . . . . . . . . . . . 414--422 A. C. Parker and J. J. Wallace Slide: An I/O Hardware Descriptive Language . . . . . . . . . . . . . . . . 423--439 M. Imase and M. Itoh Design to Minimize Diameter on Building-Block Network . . . . . . . . . 439--442 E. A. Snow and D. P. Siewiorek Implementation and Performance Evaluation of Computer Families . . . . 443--447 S. H. Uuger Double-Edge-Triggered Flip-Flops . . . . 447--451 A. M. Despain Author's Reply . . . . . . . . . . . . . 452--452 S. Prakash and V. V. Rao Comments on ``Very Fast Fourier Transform Algorithms Hardware for Implementation'' . . . . . . . . . . . . 452--452 I. S. Reed and T. K. Truong and B. Benjauthrit Addendum to ``A New Hybrid Algorithm for Computing a Fast Discrete Fourier Transform'' . . . . . . . . . . . . . . 453--454 D. S. Parker, Jr. Correction to ``Combinatorial Merging and Huffman's Algorithm'' . . . . . . . 454--454 G. Persky and B. N. Tien and B. S. Ting Comments on ``An Optimal Solution for the Channel-Assignment Problem'' . . . . 454--454 Anonymous Call for Papers . . . . . . . . . . . . 455--455 Anonymous Call for Papers . . . . . . . . . . . . 455--455 Anonymous IEEE Computer Society Publications . . . 455--455 U. I. Gupta and D. T. Lee and J. Y.-T. Leung Authors' Reply . . . . . . . . . . . . . 455--455 U. Lauther Additional Comments on ``An Optimal Solution for the Channel-Assignment Problem'' . . . . . . . . . . . . . . . 455--455 F. Rubin Further Comments on ``An Optimal Solution for the Channel-Assignment Problem'' . . . . . . . . . . . . . . . 455--455
T. G. Lewis and B. D. Shriver Introduction . . . . . . . . . . . . . . 457--459 S. Davidson and D. Landskov and B. D. Shriver and P. W. Mallett Some Experiments in Local Microcode Compaction for Horizontal Machines . . . 460--477 J. A. Fisher Trace Scheduling: a Technique for Global Microcode Compaction . . . . . . . . . . 478--490 M. Tokoro and E. Tamura and T. Takizuka Optimization of Microprograms . . . . . 491--504 J. A. Stankovic The Types and Interactions of Vertical Migrations of Functions in a Multilevel Interpretive System . . . . . . . . . . 505--513 A. Van Dam and M. Barbacci and C. Halatsis and J. Joosten and M. Letheren Simulation of a Horizontal Bit-Sliced Processor Using the ISPS Architecture Simulation Facility . . . . . . . . . . 513--519 G. J. Myers and D. G. Hocker The Use of Software Simulators in the Testing and Debugging of Microprogram Logic . . . . . . . . . . . . . . . . . 519--523 Anonymous Call for Papers . . . . . . . . . . . . 523--523 Anonymous Call for Papers . . . . . . . . . . . . 523--523 Anonymous IEEE Computer Society Publications . . . 523--523
J. R. VanAken and G. L. Zick The Expression Processor: a Pipelined, Multiple- Processor Architecture . . . . 525--536 G. Bongiovanni and C. K. Wong Tree Search in Major/Minor Loop Magnetic Bubble Memories . . . . . . . . . . . . 537--545 S. Thanawastien and V. P. Nelson Interference Analysis of Shuffle/Exchange Networks . . . . . . . 545--556 H. Fujiwara On Closedness and Test Complexity of Logic Circuits . . . . . . . . . . . . . 556--562 T. Sridhar and J. P. Hayes A Functional Approach to Testing Bit-Sliced Microprocessors . . . . . . . 563--571 I. Shirakawa and N. Okuda and T. Harada and S. Tani and H. Ozaki A Layout System for the Random Logic Portion of an MOS LSI Chip . . . . . . . 572--581 V. D. Agrawal An Information Theoretic Approach to Digital Fault Testing . . . . . . . . . 582--587 J. R. Armstrong and F. G. Gray Fault Diagnosis in a Boolean $n$ Cube Array of Microprocessors . . . . . . . . 587--590 J. T. Butler Speed-Efficiency-Complexity Tradeoffs in Universal Diagnosis Algorithms . . . . . 590--596 A. B. Hayes Stored State Asynchronous Sequential Circuits . . . . . . . . . . . . . . . . 596--600 Y. K. Malaiya and S. Y. H. Su Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults . . . . 600--604 G. Markowsky Syndrome-Testability Can be Achieved by Circuit Modification . . . . . . . . . . 604--606 J. Savir Syndrome-Testing of ``Syndrome-Untestable'' Combinational Circuits . . . . . . . . . . . . . . . . 606--608 J. Worlton Comments on ``Parallelism and Representation Problems in Distributed Systems'' . . . . . . . . . . . . . . . 608--609 J. B. Surjaatmadja An Algebra for Switching Circuits . . . 609--613 Anonymous Call for Papers . . . . . . . . . . . . 613--613 Anonymous Call for Papers . . . . . . . . . . . . 613--613 Anonymous Call for Papers Special Issue on Computer Architecture for Pattern Analysis and Image Database Management 613--613 Anonymous Call for Papers Special Issue on Reliable and Fault-Tolerant Computing 613--613 Anonymous IEEE Computer Society Publications . . . 613--613
J. T. Butler and A. S. Wojcik Guest Editors' Comments . . . . . . . . 617--618 K. C. Smith The Prospects for Multivalued Logic: a Technology and Applications View . . . . 619--634 T. Sasao Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays 635--643 H. G. Kerkhoff and M. L. Tervoert Multiple-Valued Logic Charge-Coupled Devices . . . . . . . . . . . . . . . . 644--652 M. Davio and J.-P. Deschamps Synthesis of Discrete Functions Using I$^2$L Technology . . . . . . . . . . . 653--661 T. T. Dao SEC--DED Nonbinary Code for Fault-Tolerant Byte-Organized Memory Implemented with Quaternary Logic . . . 662--666 W. C. Kabat and A. S. Wojcik On the Design of $4$-Valued Digital Systems . . . . . . . . . . . . . . . . 666--671 A. D. Singh and F. G. Gray and J. R. Armstrong Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules . . . . . . . . . . . 671--674 G. Pomper and J. R. Armstrong Representation of Multivalued Functions Using the Direct Cover Method . . . . . 674--679 C. S. Holt and J. E. Smith Diagnosis of Systems with Asymmetric Invalidation . . . . . . . . . . . . . . 679--690 J. H. P. Zurawski and J. B. Gosling Design of High-Speed Digital Divider Units . . . . . . . . . . . . . . . . . 691--699 S. Dormido and M. A. Canto Synthesis of Generalized Parallel Counters . . . . . . . . . . . . . . . . 699--703 Anonymous Planned Special Issues IEEE Transactions on Computers . . . . . . . . . . . . . . 704--704 Anonymous Advance Announcement: Tutorial Week West 81 . . . . . . . . . . . . . . . . . . . 705--705 Anonymous Call for Papers . . . . . . . . . . . . 705--705 Anonymous IEEE Computer Society Publications . . . 705--705 Anonymous Students in Computer Science and Engineering! . . . . . . . . . . . . . . 705--705
D. Gelernter A DAG-Based Algorithm for Prevention of Store-and-Forward Deadlock in Packet Networks . . . . . . . . . . . . . . . . 709--715 D. W. Clark and B. W. Lampson and K. A. Pier The Memory System of a High-Performance Personal Computer . . . . . . . . . . . 715--733 S. S. Lam and Y. C. L. Lien Congestion Control of Packet Communication Networks by Input Buffer Limits --- A Simulation Study . . . . . 733--742 Tse-Yun Feng and Chuan-Lin Wu Fault-Diagnosis for a Class of Multistage Interconnection Networks . . 743--758 Nai-Kuan Tsao Error Complexity Analysis of Algorithms for Matrix Multiplication and Matrix Chain Product . . . . . . . . . . . . . 758--771 J. H. Patel Performance of Processor-Memory Interconnections for Multiprocessors . . 771--780 J. G. Shanthikumar On the Buffer Behavior with Poisson Arrivals, Priority Service, and Random Server Interruptions . . . . . . . . . . 781--786 C. V. Ramamoorthy and B. W. Wah An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor . . . . . . . . . . 787--800 B. I. Dervisoglu and D. J. Criscione A Hard Programmable Control Unit Design Using VLSI Technology . . . . . . . . . 800--810 T. Kanai An Improvement of Reliability of Memory System with Skewing Reconfiguration . . 811--812 D. Almer and M. A. Tapia and J. H. Tucker Correction to ``Complete Solution of Boolean Equations'' . . . . . . . . . . 812--812 A. Gottlieb Comments on ``Concurrent Search and Insertion in AVL Trees'' . . . . . . . . 812--812 C. V. Ramamoorthy and B. W. Wah The Degradation in Memory Utilization Due to Dependencies . . . . . . . . . . 813--818 Anonymous Correction to ``The MPG System: A Machine-Independent Efficient Microprogram Generator'' . . . . . . . . 818--818 Anonymous Correction to ``Dual-Mode Logic for Function-Independent Fault Testing'' . . 819--819 Anonymous Correction to ``An Efficient Method for Improving Reliability of a Pipeline FFT'' . . . . . . . . . . . . . . . . . 819--819 Anonymous Call for Papers Trends and Applications 819--819 Anonymous IEEE Computer Society Publications . . . 819--819 Anonymous Planned Special Issues IEEE Transactions on Computers . . . . . . . . . . . . . . 819--819
Anonymous Introduction . . . . . . . . . . . . . . 821--822 H. Fujiwara and K. Kinoshita A Design of Programmable Logic Arrays with Universal Tests . . . . . . . . . . 823--828 W. Daehin and J. Mucha A Hardware Approach to Self-Testing of Large Programmable Logic Arrays . . . . 829--833 R. Parthasarathy and S. M. Reddy A Testable Design of Iterative Logic Arrays . . . . . . . . . . . . . . . . . 833--841 T. Sridhar and J. P. Hayes Design of Easily Testable Bit-Sliced Systems . . . . . . . . . . . . . . . . 842--854 V. K. Agarwal and A. S. F. Fung Multiple Fault Testing of Large Circuits by Single Fault Test Sets . . . . . . . 855--865 E. J. McCluskey and S. Bozorgui-Nesbat Design for Autonomous Test . . . . . . . 866--875 J. A. Abraham and D. D. Gajski Design of Testable Structures Defined by Simple Loops . . . . . . . . . . . . . . 875--884 R. W. Priester and J. B. Clary New Measures of Testability and Test Complexity for Linear Analog Failure Analysis . . . . . . . . . . . . . . . . 884--888 V. Visvanathan and A. Sangiovanni-Vincentelli Diagnosability of Nonlinear Circuits and Systems --- Part I: The dc Case . . . . 889--898 R. Saeks and A. Sangiovanni-Vincentelli and V. Visvanathan Diagnosability of Nonlinear Circuits and Systems --- Part II: Dynamical Systems 899--904 Anonymous Call for Papers Trends and Applications 904--904 Anonymous IEEE Computer Society Publications . . . 904--904 Anonymous IEEE Transactions on Computers Planned Special Issues . . . . . . . . . . . . . 904--904 Anonymous Students in Computer Science and Engineering! . . . . . . . . . . . . . . 904--904
T. L. Booth In Memoriam: Richard E. Merwin, President of the IEEE Computer Society 909--909 D. Avis and G. T. Toussaint An Optimal Algorithm for Determining the Visibility of a Polygon from an Edge . . 910--914 G. Gopal and J. W. Wong Delay Analysis of Broadcast Routing in Packet-Switching Networks . . . . . . . 915--922 J. R. Goodman and C. H. Sequin Hypertree: a Multiprocessor Interconnection Topology . . . . . . . . 923--933 H. J. Siegel and L. J. Siegel and F. C. Kemmerer and P. T. Mueller, Jr. and H. E. Smalley, Jr. and S. D. Smith PASM: a Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition . . . . . . . . . . . . . . 934--947 M. Karpovsky An Approach for Error Detection and Error Correction in Distributed Systems Computing Numerical Functions . . . . . 947--953 S. M. Walters and F. G. Gray and R. A. Thompson Self-Diagnosing Cellular Implementations of Finite-State Machines . . . . . . . . 953--959 R. A. Finkel and M. H. Solomon The Lens Interconnection Strategy . . . 960--965 Yih-Chyun Jenq Digital Convolution Algorithm for Pipelining Multiprocessor Systems . . . 966--973 S. C. Seth and K. Narayanaswamy A Graph Model for Pattern-Sensitive Faults in Random Access Memories . . . . 973--977 D. Steinberg and M. Rodeh A layout for the shuffle-exchange network with $O(N^2/\log^{3/2}N)$ area 977--982 D. S. Suk and S. M. Reddy A March Test for Functional Faults in Semiconductor Random Access Memories . . 982--985 S. L. Hurst Comments on ``Design of a Dynamically Programmable Logic Gate'' . . . . . . . 986--987 R. E. Suarez and O. Chang and V. Adam Authors' Reply . . . . . . . . . . . . . 987--987 T. W. Williams and N. C. Brown Defect Level as a Function of Fault Coverage . . . . . . . . . . . . . . . . 987--988 Chi-Chang Liaw and S. Y. H. Su and Y. K. Malaiya Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits . . . . . . . . . . 989--995 Z. Barzilai and J. Savir and G. Markowsky and M. G. Smith The Weighted Syndrome Sums Approach to VLSI Testing . . . . . . . . . . . . . . 996--1000 Anonymous Advance Announcement: Tutorial Week East 82 . . . . . . . . . . . . . . . . . . . 1000--1000 Anonymous Call for Papers . . . . . . . . . . . . 1000--1000 Anonymous IEEE Computer Society Publications . . . 1000--1000 Anonymous 1981 Index IEEE Transactions on Computers Vol. C-30 . . . . . . . . . . 1000--1000 Anonymous IEEE Transactions on Computers Planned Special Issues . . . . . . . . . . . . . 1000--1000
Anonymous Editor's Notice . . . . . . . . . . . . 1--1 T. W. Williams and K. P. Parker Design for Testability --- A Survey . . 2--15 R. R. Shively Architecture of a Programmable Digital Signal Processor . . . . . . . . . . . . 16--22 V. K. Vaishnavi Computing Point Enclosures . . . . . . . 22--29 M. Feuer Connectivity of Random Logic . . . . . . 29--33 A. Thayse Synthesis and Optimization of Programs by Means of $P$-Functions . . . . . . . 34--40 Perng-Yi Richard Ma and E. Y. S. Lee and M. Tsuchiya A Task Allocation Model for Distributed Computing Systems . . . . . . . . . . . 41--47 H. Garcia-Molina Elections in a Distributed Computing System . . . . . . . . . . . . . . . . . 48--59 B. W. Arden and Hikyu Lee A Regular Network for Multicomputer Systems . . . . . . . . . . . . . . . . 60--69 V. G. Oklobdzija and M. D. Ercegovac An On-Line Square Root Algorithm . . . . 70--75 G. Wustmann Autocorrelation Function of Filtered $p$-Level Maximal-Length Sequences . . . 75--77 G. Lacroix and P. Marchegay and G. Piel Comments on ``The Anomalous Behavior of Flip-Flops in Synchronizer Circuits'' 77--78 R. W. Heuft and W. D. Little Improved Time and Parallel Processor Bounds for Fortran-Like Loops . . . . . 78--81 Anonymous List of Referees January 1, 1980--June 1981 . . . . . . . . . . . . . . . . . . 82--85 Anonymous IEEE Transactions on Computers Planned Special Issues . . . . . . . . . . . . . 86--86 Anonymous Call for Papers . . . . . . . . . . . . 87--87 Anonymous Information for Authors . . . . . . . . 87--87 Anonymous IEEE Copyright Form . . . . . . . . . . 87--87 Anonymous IEEE Computer Society Publications . . . 87--87 Anonymous Students In Computer Science And Engineering! . . . . . . . . . . . . . . 87--87
L. J. Hafer and A. C. Parker Automated Synthesis of Digital Hardware 93--109 D. D. Riley and R. J. Baron Design and Evaluation of a Synchronous Triangular Interconnection Scheme for Interprocessor Communications . . . . . 110--118 S. Ceri and G. Pelagatti Allocation of Operations in Distributed Database Access . . . . . . . . . . . . 119--129 Y. M. El-Ziq and S. Y. H. Su Fault Diagnosis of MOS Combinational Networks . . . . . . . . . . . . . . . . 129--139 X. Chen and S. L. Hurst A Comparison of Universal-Logic-Module Realizations and Their Application in the Synthesis of Combinatorial and Sequential Logic Networks . . . . . . . 140--147 D. Nassimi and S. Sahni Parallel Algorithms to Set Up the Benes Permutation Network . . . . . . . . . . 148--154 M. De Prycker A Performance Analysis of the Implementation of Addressing Methods in Block-Structured Languages . . . . . . . 155--163 M. J. O'Donnell and C. H. Smith A Combinatorial Problem Concerning Processor Interconnection Networks . . . 163--164 P. K. Varshney and C. R. P. Hartmann and J. M. De Faria, Jr. Application of Information Theory to Sequential Fault Diagnosis . . . . . . . 164--170 K. Y. Liu Architecture for VLSI Design of Reed--Solomon Encoders . . . . . . . . . 170--175 P. R. Roeser and M. E. Jernigan Fast Haar Transform Algorithms . . . . . 175--177 Anonymous Advance Announcement: Tutorial Week East 82 . . . . . . . . . . . . . . . . . . . 177--177 Anonymous Call for Papers . . . . . . . . . . . . 177--177 Anonymous IEEE Computer Society Press Checklist of New Titles December 1981 . . . . . . . . 177--177 Anonymous IEEE Computer Society Publications . . . 177--177 Anonymous IEEE Transactions on Computers Planned Special Issues . . . . . . . . . . . . . 177--177
H. W. Six and D. Wood Counting and Reporting Intersections of $d$-Ranges . . . . . . . . . . . . . . . 181--187 T. Ibaraki and T. Kameda Deadlock-Free Systems for a Bounded Number of Processes . . . . . . . . . . 188--193 W. E. Kluge and K. Lautenbach The Orderly Resolution of Memory Access Conflicts Among Competing Channel Processes . . . . . . . . . . . . . . . 194--207 L. J. Siegel and H. J. Siegel and A. E. Feather Parallel Processing Approaches to Image Correlation . . . . . . . . . . . . . . 208--218 W. E. Leland and M. H. Solomon Dense Trivalent Graphs for Processor Interconnection . . . . . . . . . . . . 219--222 G. V. Bochmann Hardware Specification with Temporal Logic: An Example . . . . . . . . . . . 223--231 J. A. G. Jess and H. G. M. Kees A Data Structure for Parallel $L/U$ Decomposition . . . . . . . . . . . . . 231--239 M. A. Marsan and M. Gerla Markov Models for Multiple Bus Multiprocessor Systems . . . . . . . . . 239--248 R. M. Geist and K. S. Trivedi Optimal Design of Multilevel Storage Hierarchies . . . . . . . . . . . . . . 249--260 R. P. Brent and H. T. Kung A Regular Layout for Parallel Adders . . 260--264 M. Kubale Comments on ``Decomposition of Permutation Networks'' . . . . . . . . . 265--265 N. R. Strader II Comments on ``Magnetic Bubble Memory Architectures for Supporting Associative Searching of Relational Databases'' . . 265--266 Anonymous Innovation . . . . . . . . . . . . . . . 266--266 Anonymous IEEE Computer Society Press Checklist of New Titles December 1981 . . . . . . . . 266--266 Anonymous IEEE Computer Society Publications . . . 266--266 Anonymous IEEE Transactions on Computers Planned Special Issues . . . . . . . . . . . . . 266--266
Anonymous Editor's Notice . . . . . . . . . . . . 269--269 G. B. Adams III and H. J. Siegel On the Number of Permutations Performable by the Augmented Data Manipulator Network . . . . . . . . . . 270--277 J. Deminet Experience with Multiprocessor Algorithms . . . . . . . . . . . . . . . 278--288 J. P. Fishburn and R. A. Finkel Quotient Networks . . . . . . . . . . . 288--295 J. H. Patel Analysis of Multiprocessors with Private Cache Memories . . . . . . . . . . . . . 296--304 G. M. Silberman Determining Fault Ratios in Multilevel Delayed Staging Storage Hierarchies . . 305--310 C. Bellon and G. Saucier Protection Against External Errors in a Dedicated System . . . . . . . . . . . . 311--317 Chung Ho Chen An Algebraic Model of Arithmetic Codes 318--321 F. J. Taylor and C. H. Huang An Autoscale Residue Multiplier . . . . 321--325 H. J. Sips Comments on ``An $O(n)$ Parallel Multiplier with Bit-Sequential Input and Output'' . . . . . . . . . . . . . . . . 325--327 E. Tanaka and King Sun Fu Correction to ``Error-Correcting Parsers for Formal Languages'' . . . . . . . . . 327--328 A. Feldstein and R. Goodman Loss of Significance in Floating Point Subtraction and Addition . . . . . . . . 328--335 L. N. Bhuyan and D. P. Agarwal On the Generalized Binary System . . . . 335--338 D. Nassimi and S. Sahni Optimal BPC Permutations on a Cube Connected SIMD Computer . . . . . . . . 338--341 Anonymous IEEE Transactions on Computers Planned Special Issues . . . . . . . . . . . . . 342--342 Anonymous Call for Papers . . . . . . . . . . . . 343--343 Anonymous IEEE Computer Society Press Checklist of New Titles December 1982 . . . . . . . . 343--343 Anonymous IEEE Computer Society Publications . . . 343--343 Anonymous Preliminary Program Ninth Annual International Symposium on Computer Architecture . . . . . . . . . . . . . . 343--343
S. P. Kartashev Supersystems: Current State-of-the-Art Guest Editor's Introduction . . . . . . 345--348 N. R. Lincoln Technology and Design Tradeoffs in the Creation of a Modern Supercomputer . . . 349--362 D. J. Kuck and R. A. Stokes The Burroughs Scientific Processor (BSP) 363--376 K. E. Batcher Bit-Serial Parallel Processing Systems 377--384 R. G. Arnold and R. O. Berg and J. W. Thomas A Modular Approach to Real-Time Supersystems . . . . . . . . . . . . . . 385--398 E. E. Swartzlander, Jr. and B. K. Gilbert Supersystems: Technology and Architecture . . . . . . . . . . . . . . 399--409 J. P. Ignizio and D. F. Palmer and C. M. Murphy A Multicriteria Approach to Supersystem Architecture Definition . . . . . . . . 410--418 K. B. Irani and N. G. Khabbaz A Methodology for the Design of Communication Networks and the Distribution of Data in Distributed Supercomputer Systems . . . . . . . . . 419--434 D. H. Lawrie and C. R. Vora The Prime Memory System for Array Access 435--442 G. B. Adams III and H. J. Siegel The Extra Stage Cube: a Fault-Tolerant Interconnection Network for Supersystems 443--454 B. W. Arden and R. Ginosar MP/C: a Multiprocessor/Computer Architecture . . . . . . . . . . . . . . 455--473 Anonymous Call for Papers . . . . . . . . . . . . 474--474 Anonymous Innovation . . . . . . . . . . . . . . . 474--474 Anonymous IEEE Computer Society Press Checklist of New Titles December 1982 . . . . . . . . 474--474 Anonymous IEEE Computer Society Publications . . . 474--474 Anonymous IEEE Transactions on Computers Planned Special Issues . . . . . . . . . . . . . 474--474
Anonymous Announcement . . . . . . . . . . . . . . 477--477 Der-Tsai Lee On $k$-Nearest Neighbor Voronoi Diagrams in the Plane . . . . . . . . . . . . . . 478--487 S. P. Kartashev and S. I. Kartashev Distribution of Programs for a System with Dynamic Architecture . . . . . . . 488--514 H. W. Trickey Good Layouts for Pattern Recognizers . . 514--520 B. Bose and T. R. N. Rao Theory of Unidirectional Error Correcting/Detecting Codes . . . . . . . 521--530 F. Cristian Exception Handling and Software Fault Tolerance . . . . . . . . . . . . . . . 531--540 F. J. Taylor A VLSI Residue Arithmetic Multiplier . . 540--546 D. M. Dias and M. Kumar Comments on ``Interference Analysis of Shuffle/Exchange Networks'' . . . . . . 546--547 J. J. Metzner Convolutionally Encoded Memory Protection . . . . . . . . . . . . . . . 547--551 W. A. Porter Error Tolerant Design of Multivalued Logic Functions . . . . . . . . . . . . 551--554 A. Shiozaki Single Asymmetric Error-Correcting Cyclic AN Codes . . . . . . . . . . . . 554--555 H. Fujiwara and S. Toida The Complexity of Fault Detection Problems for Combinational Logic Circuits . . . . . . . . . . . . . . . . 555--560 W. F. Mikhail and R. W. Bartoldus and R. A. Rutledge The Reliability of Memory with Single-Error Correction . . . . . . . . 560--564 B. Bose and D. K. Pradhan Optimal Unidirectional Error Detecting/Correcting Codes . . . . . . . 564--568 Anonymous Announcing The 3rd International Conference on Distributed Computing Systems . . . . . . . . . . . . . . . . 568--568 Anonymous Call for Papers . . . . . . . . . . . . 568--568 Anonymous Call for Papers . . . . . . . . . . . . 568--568 Anonymous IEEE Computer Society Press Checklist of New Titles December 1982 . . . . . . . . 568--568 Anonymous IEEE Computer Society Publications . . . 568--568 Anonymous IEEE Transactions on Computers Planned Special Issues . . . . . . . . . . . . . 568--568
Anonymous Editor's Notice . . . . . . . . . . . . 573--574 Se June Hong Preface: Reliable and Fault-Tolerant Computing . . . . . . . . . . . . . . . 575--577 Y. H. Levendel and P. R. Menon Test Generation Algorithms for Computer Hardware Description Languages . . . . . 577--588 J. H. Patel and L. Y. Fung Concurrent Error Detection in ALU's by Recomputing with Shifted Operands . . . 589--595 S. Kaneda and E. Fujiwara Single Byte Error Correcting--Double Byte Error Detecting Codes for Memory Systems . . . . . . . . . . . . . . . . 596--602 D. J. Taylor and J. P. Black Principles of Data Structure Error Correction . . . . . . . . . . . . . . . 602--608 T. E. Mangir and A. Avizienis Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs . . . . . . 609--616 P. M. Melliar-Smith and R. L. Schwartz Formal Specification and Mechanical Verification of SIFT: a Fault-Tolerant Flight Control System . . . . . . . . . 616--630 H. Rudin and C. H. West A Validation Technique for Tightly Coupled Protocols . . . . . . . . . . . 630--636 J.-M. Ayache and J.-P. Courtiat and M. Diaz REBUS, A Fault-Tolerant Distributed System for Industrial Real-Time Control 637--647 J. F. Meyer Closed-Form Solutions of Performability 648--657 X. Castillo and S. R. McConnel and D. P. Siewiorek Derivation and Calibration of a Transient Error Reliability Model . . . 658--671 M. Abramovici A Hierarchical, Path-Oriented Approach to Fault Diagnosis in Modular Combinational Circuits . . . . . . . . . 672--677 J. Khakbaz Totally Self-Checking Checker for 1-out-of-$n$ Code Using Two-Rail Codes 677--681 D. J. Lu Watchdog Processors and Structural Integrity Checking . . . . . . . . . . . 681--685 A. Mili Self-Stabilizing Programs: The Fault-Tolerant Capability of Self-Checking Programs . . . . . . . . . 685--689 R. E. Glaser and G. M. Masson The Containment Set Approach to Upsets in Digital Systems . . . . . . . . . . . 689--692 S. K. Shrivastava and F. Panzieri The Design of a Reliable Remote Procedure Call Mechanism . . . . . . . . 692--697 R. K. Iyer and S. E. Butner and E. J. Mccluskey A Statistical Failure/Load Relationship: Results of a Multicomputer Study . . . . 697--706 Anonymous Information for Authors . . . . . . . . 706--706 Anonymous IEEE Copyright Form . . . . . . . . . . 706--706 Anonymous IEEE Computer Society Publications . . . 706--706
G. W. Gerrity Computer Representation of Real Numbers 709--714 D. Towsley and G. Venkatesh Window Random Access Protocols for Local Computer Networks . . . . . . . . . . . 715--722 P. D. Amer A Measurement Center for the NBS Local Area Computer Network . . . . . . . . . 723--729 G. J. Holzmann A Theory for Protocol Validation . . . . 730--738 Jinpo Wang Delay and Throughput Analysis for Computer Communications with Balanced HDLC Procedures . . . . . . . . . . . . 739--746 To-Yat Cheung A Method for Equijoin Queries in Distributed Relational Databases . . . . 746--751 V. Kini and D. P. Siewiorek Automatic Generation of Symbolic Reliability Functions for Processor-Memory-Switch Structures . . . 752--771 E. M. Clarke and C. N. Nikolaou Distributed Reconfiguration Strategies for Fault-Tolerant Multiprocessor Systems . . . . . . . . . . . . . . . . 771--784 G. Memmi and Y. Raillard Some New Results About the $(d, k)$ Graph Problem . . . . . . . . . . . . . 784--791 N. R. Strader and V. T. Rhyne A Canonical Bit-Sequential Multiplier 791--795 J. M. Herron and J. Farley and K. Preston, Jr. and H. Sellner A General-Purpose High-Speed Logical Transform Image Processor . . . . . . . 795--800 J. P. Robinson and Chia-Lung Yeh A Method for Modulo-$2$ Minimization . . 800--801 S. Dormido and M. A. Canto An Upper Bound for the Synthesis of Generalized Parallel Counters . . . . . 802--805 Anonymous Advance Announcement: Tutorial Week West 82 . . . . . . . . . . . . . . . . . . . 805--805 Anonymous Call for Papers . . . . . . . . . . . . 805--805 Anonymous Call for Papers . . . . . . . . . . . . 805--805 Anonymous IEEE Computer Society Publications . . . 805--805 Anonymous IEEE Transactions on Computers Planned Special Issues . . . . . . . . . . . . . 805--805
P. M. Flanders A Unified Approach to a Class of Data Movements on an Array Processor . . . . 809--819 M. Sowa and T. Murata A Data Flow Computer Architecture with Program and Token Memories . . . . . . . 820--824 Forbes J. Burkowski A hardware hashing scheme in the design of a multiterm string comparator . . . . 825--834 W. W. Chu and P. Hurley Optimal Query Processing for Distributed Database Systems . . . . . . . . . . . . 835--850 M. C. Wei and H. A. Sholl An Expression Model for Extraction and Evaluation of Parallelism in Control Structures . . . . . . . . . . . . . . . 851--863 D. K. Pradhan and S. M. Reddy A Fault-Tolerant Communication Architecture for Distributed Systems . . 863--870 Hung Chi Lai and S. Muroga Logic Networks of Carry-Save Adders . . 870--882 M. De Prycker On the Development of a Measurement System for High Level Language Program Statistics . . . . . . . . . . . . . . . 883--891 T. A. Ottmann and A. L. Rosenberg and L. J. Stockmeyer A Dictionary Machine (for VLSI) . . . . 892--897 V. A. Signaevskii Comments on ``Multiprocessor Scheduling with Memory Allocation --- A Deterministic Approach'' . . . . . . . . 898--898 J. Weglarz Author's Reply . . . . . . . . . . . . . 898--898 C. C. Chen A Distributed Algorithm for Shortest Paths . . . . . . . . . . . . . . . . . 898--899 F. A. Kamangar and K. R. Rao Fast Algorithms for the $2$-D Discrete Cosine Transform . . . . . . . . . . . . 899--906 R. Aleliunas and A. L. Rosenberg On Embedding Rectangular Grids in Square Grids . . . . . . . . . . . . . . . . . 907--913 M. K. Molloy Performance Analysis Using Stochastic Petri Nets . . . . . . . . . . . . . . . 913--917 Anonymous Advance Announcement: Tutorial Week West 82 . . . . . . . . . . . . . . . . . . . 917--917 Anonymous 7th Conference on Local Computer Networks . . . . . . . . . . . . . . . . 917--917 Anonymous Call for Papers 1983 Trends and Applications Conference . . . . . . . . 917--917 Anonymous IEEE Computer Society Publications . . . 917--917
Y. T. Chien and E. A. Parrish Special Issue on Computer Architecture for Pattern Analysis and Image Database Management . . . . . . . . . . . . . . . 921--922 Chuan-Lin Wu and Tse-Yun Feng and Min-Chang Lin Star: a Local Network System for Real-Time Management of Imagery Data . . 923--933 M. R. Warpenburg and L. J. Siegel SIMD Image Resampling . . . . . . . . . 934--942 T. Kushner and A. Y. Wu and A. Rosenfeld Image Processing on ZMOB . . . . . . . . 943--951 D. P. Agrawal and R. Jain A Pipelined Pseudoparallel System Architecture for Real-Time Dynamic Scene Analysis . . . . . . . . . . . . . . . . 952--962 W. E. Snyder and C. D. Savage Content-Addressable Read/Write Memories for Image Analysis . . . . . . . . . . . 963--968 F. A. Briggs and King-Sun Fu and Kai Hwang and B. W. Wah PUMPS Architecture for Pattern Analysis and Image Database Management . . . . . 969--983 K. Yamaguchi and T. L. Kunil PICCOLO Logic for a Picture Database Computer and Its Implementation . . . . 983--996 D. Antonsson and B. Gudmundsson and T. Hedblom and B. Kruse and A. Linge and P. Lord and T. Ohlsson PICAP --- A System Approach to Image Processing . . . . . . . . . . . . . . . 997--1000 A. V. Kulkarni and D. W. L. Yen Systolic Processing and an Implementation for Signal and Image Processing . . . . . . . . . . . . . . . 1000--1009 H. A. Sholl and K. Morris and J. Norris A Multimicroprocessor System for Real-Time Classification of Railroad Track Flaws . . . . . . . . . . . . . . 1009--1017 L. M. Ni and K. Y. Wong and D. T. Lee and R. K. Poon A Microprocessor-Based Office Image Processing System . . . . . . . . . . . 1017--1022 L. Uhr Comparing Serial Computers, Arrays, and Networks Using Measures of ``Active Resources'' . . . . . . . . . . . . . . 1022--1025 P. D. Vaidya and L. G. Shapiro and R. M. Haralick and G. J. Minden Design and Architectural Implications of a Spatial Information System . . . . . . 1025--1031 Anonymous Call for Papers . . . . . . . . . . . . 1031--1031 Anonymous Call for Papers . . . . . . . . . . . . 1031--1031 Anonymous IEEE Computer Society Publications . . . 1031--1031
Anonymous Introduction: Parallel and Distributed Processing . . . . . . . . . . . . . . . 1033--1035 R. E. Buehrer and H. Brundiers and H. Benz and B. Bron and H. Friess and W. Haelg and H. J. Halin and A. Isacson and M. Tadian The ETH-Multiprocessor Empress: a Dynamically Configurable MIMD System . . 1035--1044 K. G. Shin and Yann-Hang Lee and J. Sasidhar Design of HM$^2p$ --- A Hierarchical Multimicroprocessor for General-Purpose Applications . . . . . . . . . . . . . . 1045--1053 Sun-Yuan Kung and K. S. Arun and R. J. Gal-Ezer and D. V. Bhaskar Rao Wavefront Array Processor: Language, Architecture, and Applications . . . . . 1054--1066 K. B. Irani and Kuo-Wei Chen Minimization of Interprocessor Communication for Parallel Computation 1067--1075 R. K. Montoye and D. H. Lawrie A Practical Algorithm for the Solution of Triangular Systems on a Parallel Processing System . . . . . . . . . . . 1076--1082 M. Dubois and F. A. Briggs Effects of Cache Coherency in Multiprocessors . . . . . . . . . . . . 1083--1099 P. Heidelberger and K. S. Trivedi Queueing Network Models for Parallel Processing with Asynchronous Tasks . . . 1099--1109 M. A. Franklin and D. F. Wann and W. J. Thomas Pin Limitations and Partitioning of VLSI Interconnection Networks . . . . . . . . 1109--1116 D. W. L. Yen and J. H. Patel and E. S. Davidson Memory Interference in Synchronous Multiprocessor Systems . . . . . . . . . 1116--1121 D. I. Moldovan On the Analysis and Synthesis of VLSI Algorithms . . . . . . . . . . . . . . . 1121--1126 B. W. Weide Modeling Unusual Behavior of Parallel Algorithms . . . . . . . . . . . . . . . 1126--1130 Anonymous Advance Announcement: Tutorial Week East 83 . . . . . . . . . . . . . . . . . . . 1130--1130 Anonymous Call for Papers 1983 Trends and Applications Conference . . . . . . . . 1130--1130 Anonymous 1983 International Conference on Parallel Processing . . . . . . . . . . 1130--1130 Anonymous IEEE Computer Society Publications . . . 1130--1130
L. A. Hollaar Direct Implementation of Asynchronous Control Units . . . . . . . . . . . . . 1133--1141 T. Baba and K. Ishikawa and K. Okuda A Two-Level Microprogrammed Multiprocessor Computer with Nonnumeric Functions . . . . . . . . . . . . . . . 1142--1156 E. Gelenbe and A. Lichnewsky and A. Staphylopatis Experience with the Parallel Solution of Partial Differential Equations on a Distributed Computing System . . . . . . 1157--1164 M. Abramovici and M. A. Breuer Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect--Cause Analysis . . . . . . . . . 1165--1172 S. Nakamura and G. M. Masson Lower Bounds on Crosspoints in Concentrators . . . . . . . . . . . . . 1173--1179 M. A. Marsan and G. Balbo and G. Conte Comparative Performance Analysis of Single Bus Multiprocessor Architectures 1179--1191 H. Yasuura and N. Takagi and S. Yajima The Parallel Enumeration Sorting Scheme for VLSI . . . . . . . . . . . . . . . . 1192--1201 R. J. McMillen and H. J. Siegel Routing Schemes for the Augmented Data Manipulator Network in an MIMD System 1202--1214 Kai Hwang and Yeng-Heng Cheng Partitioned Matrix Algorithms for VLSI Arithmetic Systems . . . . . . . . . . . 1215--1224 D. T. Lee and C. B. Silio, Jr. An Optimal Illumination Region Algorithm for Convex Polygons . . . . . . . . . . 1225--1227 T. Lang and M. Valero and I. Alegre Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors . . . . 1227--1234 Anonymous Call for Papers Eighth Data Communications Symposium --- 1983 . . . 1234--1234 Anonymous Call for Papers 1983 Trends and Applications Conference . . . . . . . . 1234--1234 Anonymous 1983 International Conference on Parallel Processing . . . . . . . . . . 1234--1234 Anonymous IEEE Computer Society Publications . . . 1234--1234 Anonymous 1982 Index IEEE Transactions on Computers Vol. C-31 . . . . . . . . . . 1234--1234
Anonymous Editor's Notice . . . . . . . . . . . . 1--1 Anonymous Guest Editors' Introduction Performance Evaluation of Multiple Processor Systems 2--3 Z. Segall and A. Singh and R. T. Snodgrass and A. K. Jones and D. P. Siewiorek An Integrated Instrumentation Environment for Multiprocessors . . . . 4--14 H. Fromm and U. Hercksen and U. Herzog and K.-H. John and R. Klar and W. Kleinoder Experiences with Performance Measurement and Modeling of a Processor Array . . . 15--31 D. Parkinson and H. M. Liddell The Measurement of Performance on a Highly Parallel System . . . . . . . . . 32--37 P. C. C. Yeh and J. H. Patel and E. S. Davidson Shared Cache for Multiple-Stream Computer Systems . . . . . . . . . . . . 38--47 F. A. Briggs and M. Dubois Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories . . . . . . 48--59 M. A. Marsan and G. Balbo and G. Conte and F. Gregoretti Modeling Bus Contention and Memory Interference in a Multiprocessor System 60--72 P. Heidelberger and K. S. Trivedi Analytic Queueing Models for Programs with Internal Concurrency . . . . . . . 73--82 D. A. Reed and H. D. Schwetman Cost-Performance Bounds for Multimicrocomputer Networks . . . . . . 83--95 I. Mitrani and P. J. B. King Multiserver Systems Subject to Breakdowns: An Empirical Study . . . . . 96--98 Anonymous Information for Authors . . . . . . . . 98--98 Anonymous IEEE Copyright Form . . . . . . . . . . 98--98 Anonymous IEEE Computer Society Publications . . . 98--98
G. K. Lin and P. R. Menon Totally Preset Checking Experiments for Sequential Machines . . . . . . . . . . 101--108 T. Lozano-Perez Spatial Planning: a Configuration Space Approach . . . . . . . . . . . . . . . . 108--120 G. V. Bochmann and M. Raynal Structured Specification of Communicating Systems . . . . . . . . . 120--133 Y. I. Gold and W. R. Franta and S. Moran A Distributed Channel-Access Protocol for Fully-Connected Networks with Mobile Nodes . . . . . . . . . . . . . . . . . 133--147 G. H. Garcia and W. J. Kubitz Minimum Mean Running Time Function Generation Using Read-Only Memory . . . 147--156 M. J. Flynn and L. W. Hoevel Execution Architecture: The DELtran Experiment . . . . . . . . . . . . . . . 156--175 A. Gottlieb and R. Grishman and C. P. Kruskal and K. P. McAuliffe and L. Rudolph and M. Snir The NYU Ultracomputer --- Designing an MIMD Shared Memory Parallel Computer . . 175--189 Z. Barzilai and D. Coppersmith and A. L. Rosenberg Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing 190--194 F. P. Preparata A Mesh-Connected Area-Time Optimal VLSI Multiplier of Large Integers . . . . . . 194--198 A. K. Susskind Testing by Verifying Walsh Coefficients 198--201 J. P. Robinson Addendum to ``Optimum Golomb Rulers'' 201--201 D. J. Evans and R. C. Dunbar The Parallel Solution of Triangular Systems of Equations . . . . . . . . . . 201--204 A. R. Bazelow and J. Raamot On the Microprocessor Solution of Ordinary Differential Equations Using Integer Arithmetic . . . . . . . . . . . 204--207 Anonymous Call for Papers . . . . . . . . . . . . 207--207 Anonymous IEEE Computer Society Publications . . . 207--207 Anonymous The 1983 International Symposium on Multiple-Valued Logic . . . . . . . . . 207--207
R. Raghavan and S. Sahni Single Row Routing . . . . . . . . . . . 209--220 C. V. Ramamoorthy and B. W. Wah The Isomorphism of Simple File Allocation . . . . . . . . . . . . . . . 221--232 L. J. Laning and M. S. Leonard File Allocation in a Distributed Computer Communication Network . . . . . 232--244 C. A. Niznik A Quantization Approximation for Modeling Computer Network Nodal Queueing Delay . . . . . . . . . . . . . . . . . 245--253 M. Kumar and D. S. Hirschberg An Efficient Implementation of Batcher's Odd-Even Merge Algorithm and Its Application in Parallel Sorting Schemes 254--264 C. P. Arnold and M. I. Parr and M. B. Dewe An Efficient Parallel Algorithm for the Solution of Large Sparse Linear Matrix Equations . . . . . . . . . . . . . . . 265--273 N. Gaitanis and C. Halatsis A New Design Method for $m$-Out-of-$n$ TSC Checkers . . . . . . . . . . . . . . 273--283 D. F. Wann and M. A. Franklin Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks . . . . . . . . 284--293 J. Vuillemin A Combinatorial Limit to the Computing Power of VLSI Circuits . . . . . . . . . 294--300 T. K. Truong and K. Y. Liu and I. S. Reed A Parallel-Pipeline Architecture of the Fast Polynomial Transform for Computing a Two-Dimensional Cyclic Convolution . . 301--306 E. Dekel and S. Sahni Binary Trees and Parallel Scheduling Algorithms . . . . . . . . . . . . . . . 307--315 Kuang-Wei Chiang and Z. G. Vranesic A Tree Representation of Combinational Networks . . . . . . . . . . . . . . . . 315--319 D. K. Pradhan Sequential Network Design Using Extra Inputs for Fault Detection . . . . . . . 319--323 A. Bhattacharyya On a Novel Approach of Fault Detection in an Easily Testable Sequential Machine with Extra Inputs and Extra Outputs . . 323--325 C. Halatsis and N. Gaitanis and M. Sigala Error-Correcting Codes in Binary-Coded Radix-$r$ Arithmetic . . . . . . . . . . 326--328 Anonymous Call for Papers . . . . . . . . . . . . 328--328 Anonymous IEEE Computer Society Publications . . . 328--328
D. P. Agrawal and T. R. N. Rao Introduction: Computer Arithmetic . . . 329--330 E. V. Krishnamurthy On the Conversion of Hensel Codes to Farey Rationals . . . . . . . . . . . . 331--337 A. Froment Error Free Computation: a Direct Method to Convert Finite-Segment $p$-Adic Numbers into Rational Numbers . . . . . 337--343 Nai-Kuan Tsao A Simple Approach to the Error Analysis of Division-Free Numerical Algorithms 343--351 Osaaki Watanuki and Milo\vs D. Ercegovac Error analysis of certain floating-point on-line algorithms . . . . . . . . . . . 352--358 Shauchi Ong and D. E. Atkins A Basis for the Quantitative Comparison of Computer Number Systems . . . . . . . 359--369 Marty S. Cohen and T. E. Hull and V. Carl Hamacher CADAC: a Controlled-Precision Decimal Arithmetic Unit . . . . . . . . . . . . 370--377 Peter Kornerup and David W. Matula Finite precision rational arithmetic: An arithmetic unit . . . . . . . . . . . . 378--388 W. K. Jenkins The Design of Error Checkers for Self-Checking Residue Number Arithmetic 388--396 E. V. Krishnamurthy and V. K. Murthy Fast Iterative Division of $p$-adic Numbers . . . . . . . . . . . . . . . . 396--398 C. H. Huang A Fully Parallel Mixed-Radix Conversion Algorithm for Residue Number Applications . . . . . . . . . . . . . . 398--402 M. J. Irwin and R. M. Owens Fully Digit On-Line Networks . . . . . . 402--406 R. M. Owens Techniques to Reduce the Inherent Limitations of Fully Digit On-Line Arithmetic . . . . . . . . . . . . . . . 406--411 Daniel W. Lozier The use of floating-point and interval arithmetic in the computation of error bounds . . . . . . . . . . . . . . . . . 411--417 J. H. Patel and L. Y. Fung Concurrent Error Detection in Multiply and Divide Arrays . . . . . . . . . . . 417--422 Anonymous Call for Papers . . . . . . . . . . . . 422--422 Anonymous Call for Papers 4th Jerusalem Conference on Information Technology (JCIT) . . . . 422--422 Anonymous IEEE Computer Society Publications . . . 422--422
J. E. Requa and J. R. McGraw The Piecewise Data Flow Architecture: Architectural Concepts . . . . . . . . . 425--438 K. S. Ramanatha and N. N. Biswas An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays . . . . . . . . . . . . . . . . . 438--444 D. Steinberg Invariant Properties of the Shuffle-Exchange and a Simplified Cost-Effective Version of the Omega Network . . . . . . . . . . . . . . . . 444--450 A. Brandwajn Models of DASD Subsystems with Multiple Access Paths: a Throughput-Driven Approach . . . . . . . . . . . . . . . . 451--463 K. V. S. S. Prasad Rao and D. Basu Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains . . . . . . . . . . . . . . . . 464--475 J. L. Keedy An Instruction Set for Evaluating Expressions . . . . . . . . . . . . . . 476--478 M. Mezzalama and P. Prinetto A Hierarchical Description Model for Microcode . . . . . . . . . . . . . . . 478--487 P. W. Besslich A Method for the Generation and Processing of Dyadic Indexed Data . . . 487--494 N. Gaitanis and C. Halatsis Near-Perfect Codes for Binary-Coded Radix-$r$ Arithmetic Units . . . . . . . 494--497 G. R. Blakely A Computer Algorithm for Calculating the Product $A B$ Modulo $M$ . . . . . . . . 497--500 F. J. Taylor An Overflow-Free Residue Multiplier . . 501--504 V. Ramachandran Single Residue Error Correction in Residue Number Systems . . . . . . . . . 504--507 C. Halatsis and N. Gaitanis and M. Sigala Fast and Efficient Totally Self-Checking Checkers for $m$-out-of-$(2m \pm 1)$ Codes . . . . . . . . . . . . . . . . . 507--511 T. Yamada and T. Nanya Comments on ``Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines'' . . . . . . . . 511--512 D. Amar On the Connectivity of Some Telecommunications Networks . . . . . . 512--519 Anonymous Call for Papers . . . . . . . . . . . . 520--520 Anonymous IEEE Computer Society Publications . . . 520--520 Anonymous IEEE Transactions on Computers Planned Special Issues . . . . . . . . . . . . . 520--520
L. B. Bushard A Minimum Table Size Result for Higher Radix Nonrestoring Division . . . . . . 521--526 E. E. Swartzlander, Jr. and D. V. Satish Chandra and H. T. Nagle, Jr. and S. A. Starks Sign/Logarithm Arithmetic for FFT Implementation . . . . . . . . . . . . . 526--534 L. A. Dunning and M. R. Varanasi Code Constructions for Error Control in Byte Organized Memory Systems . . . . . 535--542 K. N. Oikonomou and R. Y. Kain Abstractions for Node Level Passive Fault Detection in Distributed Systems 543--550 K. S. Ramanatha and N. N. Biswas A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays . . . . . . . . . . . . . . . . . 551--557 R. J. Sheraga and J. L. Gieser Experiments in Automatic Microcode Generation . . . . . . . . . . . . . . . 557--569 D. Nath and S. N. Maheshwari and P. C. P. Bhatt Efficient VLSI Networks for Parallel Processing Based on Orthogonal Trees . . 569--581 E. Horowitz and A. Zorat Divide-and-Conquer for Parallel Processing . . . . . . . . . . . . . . . 582--585 D. A. Carlson Time-Space Tradeoffs on Back-to-Back FFT Algorithms . . . . . . . . . . . . . . . 585--589 Z. D. Ulman Sign Detection and Implicit-Explicit Conversion of Numbers in Residue Arithmetic . . . . . . . . . . . . . . . 590--594 A. R. Virupakshia and V. C. V. Pratapa Reddy A Simple Random Test Procedure for Detection of Single Intermittent Fault in Combinational Circuits . . . . . . . 594--597 R. G. Cantarella The Reliability of Periodically Repaired $n - 1/n$ Parallel Redundant Systems . . 597--598 Anonymous Call for Papers . . . . . . . . . . . . 598--598 Anonymous Call for Papers . . . . . . . . . . . . 598--598 Anonymous Call for Papers Special Issue on Reliable and Fault-Tolerant Computing 598--598 Anonymous IEEE Computer Society . . . . . . . . . 598--598
Anonymous Editor's Notice . . . . . . . . . . . . 601--602 J. C. Barros and B. W. Johnson Equivalence of the Arbiter, the Synchronizer, the Latch, and the Inertial Delay . . . . . . . . . . . . . 603--614 Chin-Long Chen Error-Correcting Codes with Byte Error-Detection Capability . . . . . . . 615--621 M. C. McFarland and A. C. Parker An Abstract Model of Behavior for Hardware Descriptions . . . . . . . . . 621--637 D. P. Agrawal Graph Theoretical Analysis and Design of Multistage Interconnection Networks . . 637--648 G. M. Masson and S. B. Morris Expected Capacity of ($m2$)-Networks . . 649--657 C. Von Conta Torus and Other Networks as Communication Networks With Up to Some Hundred Points . . . . . . . . . . . . . 657--666 J.-L. Baer and Hung-Chang Du and R. E. Lander Binary Search in a Multiprocessing Environment . . . . . . . . . . . . . . 667--677 L. E. Winslow and Yuan-Chieh Chow The Analysis and Design of Some New Sorting Machines . . . . . . . . . . . . 677--683 G. M. Baudet and F. P. Preparata and J. E. Vuillemin Area--Time Optimal VLSI Circuits for Convolution . . . . . . . . . . . . . . 684--688 K. O. Siomalas and B. A. Bowen Performance of Cross-Bar Multiprocessor Systems . . . . . . . . . . . . . . . . 689--695 A. Miczo A Self-Test Hardwired Control Section 695--696 Anonymous Information for Authors . . . . . . . . 696--696 Anonymous IEEE Computer Society Publications . . . 696--696
B. Chazelle The Bottom-Left Bin-Packing Heuristic: An Efficient Implementation . . . . . . 697--707 T. Lang and M. Valero and M. A. Fiol Reduction of Connections for Multibus Organization . . . . . . . . . . . . . . 707--716 S. Tasaka Stability and Performance of the R-Aloha Packet Broadcast System . . . . . . . . 717--726 J. J. Metzner A Parity Structure for Large Remotely Located Replicated Data Files . . . . . 727--730 N. Weste and D. J. Burr and B. D. Ackland Dynamic Time Warp Pattern Matching Using an Integrated Multiprocessing Array . . 731--744 N. Bandeira and K. Vaccaro and J. A. Howard A Two's Complement Array Multiplier Using True Values of the Operands . . . 745--747 R. Chaudhuri and Son Pham and O. N. Garcia Solution of an Open Problem on Probabilistic Grammars . . . . . . . . . 748--750 G. Bongiovanni Two VLSI Structures for the Discrete Fourier Transform . . . . . . . . . . . 750--754 S. C. Seth and L. Lipsky A Simplified Method to Calculate Failure Times in Fault-Tolerant Systems . . . . 754--756 G. Bongiovanni A VLSI Network for Variable Size FFT's 756--760 W. Bux Analysis of a Local-Area Bus System with Controlled Access . . . . . . . . . . . 760--763 W. W. Chu and W. Haller and K. K. Leung Reservation Channel Access Protocol for High Speed Local Networks with Star Configurations . . . . . . . . . . . . . 763--766 P. V. Afshari and S. C. Brueli and R. Y. Kain On the Load Balancing Bus Accessing Scheme . . . . . . . . . . . . . . . . . 766--770 C. Abbott A Symbolic Simulator for Microprogram Development . . . . . . . . . . . . . . 770--774 A. F. Bashir and V. Susarla and K. Vairavan A Statistical Study of the Performance of a Task Scheduling Algorithm . . . . . 774--777 A. T. Dahbura and G. M. Masson Greedy Diagnosis of Hybrid Fault Situations . . . . . . . . . . . . . . . 777--782 M. Imase and M. Itoh A Design for Directed Graphs with Minimum Diameter . . . . . . . . . . . . 782--784 Anonymous Compsac83 . . . . . . . . . . . . . . . 784--784 Anonymous IEEE Computer Society Publications . . . 784--784
W. S. Wojciechowski and A. S. Wojcik Automated Design of Multiple-Valued Logic Circuits by Automatic Theorem Proving Techniques . . . . . . . . . . . 785--798 T. C. K. Chou and J. A. Abraham Load Redistribution Under Failure in Distributed Systems . . . . . . . . . . 799--808 T. F. Schwab and S. S. Yau An Algebraic Model of Fault-Masking Logic Circuits . . . . . . . . . . . . . 809--825 Q. F. Stout Mesh-Connected Computers with Broadcasting . . . . . . . . . . . . . . 826--830 J. E. Smith and P. Lam A Theory of Totally Self-Checking System Design . . . . . . . . . . . . . . . . . 831--844 I. S. Gopal and D. Coppersmith and C. K. Wong Optimal Wiring of Movable Terminals . . 845--858 M. Kobayashi Dynamic Profile of Instruction Sequences for the IBM System/370 . . . . . . . . . 859--861 L. G. Valiant Optimality of a Two-Phase Strategy for Routing in Interconnection Networks . . 861--863 C. D. V. P. Rao and N. N. Biswas On the Minimization of Wordwidth in the Control Memory of a Microprogrammed Digital Computer . . . . . . . . . . . . 863--868 M. De Prycker Representing the Effect of Instruction Prefetch in a Microprocessor Performance Model . . . . . . . . . . . . . . . . . 868--872 M. R. Varanasi and T. R. N. Rao and Son Pham Memory Package Error Detection and Correction . . . . . . . . . . . . . . . 872--874 T. K. Truong and I. S. Reed and C.-S. Yeh and H. M. Shao A Parallel Architecture for Digital Filtering Using Fermat Number Transforms 874--877 W. W. Chu and P. Hurley Correction to ``Optimal Query Processing for Distributed Database Systems'' . . . 878--878 R. Gnanasekaran On a Bit-Serial Input and Bit-Serial Output Multiplier . . . . . . . . . . . 878--880 Anonymous Acknowledgment of Prior Work . . . . . . 880--880 Anonymous Compsac83 . . . . . . . . . . . . . . . 880--880 Anonymous IEEE Computer Society Publications . . . 880--880
E. M. Aupperle Merit's Evolution --- Statistically Speaking . . . . . . . . . . . . . . . . 881--902 A. L. Rosenberg The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors . . 902--910 A. Pedar and V. V. S. Sarma Architecture Optimization of Aerospace Computing Systems . . . . . . . . . . . 911--922 S. Isoda and Y. Kobayashi and T. Ishida Global Compaction of Horizontal Microprograms Based on the Generalized Data Dependency Graph . . . . . . . . . 922--933 R. W. Hockney Characterizing Computers and Optimizing the FACR($\ell$) Poisson Solver on Parallel Unicomputers . . . . . . . . . 933--941 C. P. Kruskal Searching, Merging, and Sorting in Parallel Computation . . . . . . . . . . 942--946 D. Brand Redundancy and Don't Cares in Logic Synthesis . . . . . . . . . . . . . . . 947--952 A. T. Dahbura and G. M. Masson Greedy Diagnosis as the Basis of an Intermittent-Fault/Transient-Upset Tolerant System Design . . . . . . . . . 953--957 M. E. Aboulhamid and E. Cerny A Class of Test Generators for Built-In Testing . . . . . . . . . . . . . . . . 957--959 J. Savir A New Empirical Test for the Quality of Random Integer Generators . . . . . . . 960--961 C. A. Papachristou Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: a Programmable Array Logic Approach . . . . . . . . . . . . . . . . 961--968 A. Sakura and S. Muroga Parallel Binary Adders with a Minimum Number of Connections . . . . . . . . . 969--976 Anonymous Compsac 83 . . . . . . . . . . . . . . . 976--976 Anonymous IEEE Computer Society Publications . . . 976--976
Y. Tamir and C. H. Sequin Strategies for Managing the Register File in RISC . . . . . . . . . . . . . . 977--989 H. K. Nagpal and G. A. Jullien and W. C. Miller Processor Architectures for Two-Dimensional Convolvers Using a Single Multiplexed Computational Element with Finite Field Arithmetic . . . . . . 989--1001 W. E. Kluge Cooperating Reduction Machines . . . . . 1002--1012 D. D. Miller and J. N. Polky A Residue Number System Implementation of the LMS Algorithm Using Optical Waveguide Circuits . . . . . . . . . . . 1013--1028 G. M. Silberman Delayed-Staging Hierarchy Optimization 1029--1037 K. K. Saluja and K. Kinoshita and H. Fujiwara An Easily Testable Design of Programmable Logic Arrays for Multiple Faults . . . . . . . . . . . . . . . . . 1038--1046 C. D. Thompson Fourier Transforms in VLSI . . . . . . . 1047--1057 D. M. Miller and J. C. Muzio Spectral Fault Signatures for Internally Unate Combinational Networks . . . . . . 1058--1062 S. S. Lam A Simple Derivation of the MVA and LBANC Algorithms from the Convolution Algorithm . . . . . . . . . . . . . . . 1062--1064 W. R. Franklin Efficient Iterated Rotation of an Object 1064--1067 P. E. Danielsson A Variable-Length Shift-Register . . . . 1067--1069 S. C. Kak A Structural Redundancy in $d$-Sequences 1069--1070 K. V. S. Bhat An Efficient Approach for Fault Diagnosis in a Boolean $n$-Cube Array of Microprocessors . . . . . . . . . . . . 1070--1071 Anonymous Information for Authors . . . . . . . . 1072--1072 Anonymous IEEE Computer Society Publications . . . 1072--1072 Meng-Hee Teng Comments on ``The Prime Memory Systems for Array Access'' . . . . . . . . . . . 1072--1072
V. Pitchumani and E. P. Stabler An Inductive Assertion Method for Register Transfer Level Design Verification . . . . . . . . . . . . . . 1073--1080 L. N. Bhuyan and D. P. Agrawal Design and Performance of Generalized Interconnection Networks . . . . . . . . 1081--1090 C. P. Kruskal and M. Snir The Performance of Multistage Interconnection Networks for Multiprocessors . . . . . . . . . . . . 1091--1098 K. Padmanabhan and D. H. Lawrie A Class of Redundant Path Multistage Interconnection Networks . . . . . . . . 1099--1108 M. A. Srinivas Optimal Parallel Scheduling of Gaussian Elimination DAG's . . . . . . . . . . . 1109--1117 R. M. Geist and K. S. Trivedi Ultrahigh Reliability Prediction for Fault-Tolerant Computer Systems . . . . 1118--1127 P. Chow and Z. Vranesic and Jui Lin Yen A Pipelined Distributed Arithmetic PFFT Processor . . . . . . . . . . . . . . . 1128--1136 H. Fujiwara and T. Shimono On the Acceleration of Test Generation Algorithms . . . . . . . . . . . . . . . 1137--1144 D. T. Tang and L. S. Woo Exhaustive Test Pattern Generation with Constant Weight Vectors . . . . . . . . 1145--1150 O. Babaoglu and D. Ferrari Two-Level Replacement Decisions in Paging Stores . . . . . . . . . . . . . 1151--1159 P. S. Liu and T. Y. Young VLSI Array Design Under Constraint of Limited I/O Bandwidth . . . . . . . . . 1160--1170 C. D. Thompson The VLSI Complexity of Sorting . . . . . 1171--1184 D. W. Twigg Transposition of Matrix Stored on Sequential File . . . . . . . . . . . . 1185--1188 S. M. Kramer and D. P. Sidhu Security Information Flow in Multidimensional Arrays . . . . . . . . 1188--1191 R. Grishman and Su Bogong A Preliminary Evaluation of Trace Scheduling for Global Microcode Compaction . . . . . . . . . . . . . . . 1191--1194 M. Karpovksy Universal Tests for Detection of Input/Output Stuck-At and Bridging Faults . . . . . . . . . . . . . . . . . 1194--1198 J. Savir Good Controllability and Observability Do Not Guarantee Good Testability . . . 1198--1200 C. E. Veni Madhavan and S. Krishna Comments on ``Optimal Design of Distributed Information Systems'' . . . 1200--1201 K. W. Bowyer and C. F. Starmer Optimizing Contiguous-Element Region Selection for Virtual Memory Systems . . 1201--1203 F. Chin and Cao An Wang Optimal Algorithms for the Intersection and the Minimum Distance Problems Between Planar Polygons . . . . . . . . 1203--1207 T. J. Chaney Measured Flip-Flop Responses to Marginal Triggering . . . . . . . . . . . . . . . 1207--1209 R. Kallman A Faster $8$-Bit Carry Circuit . . . . . 1209--1211 B. M. E. Moret and M. G. Thomason and R. C. Gonzalez Symmetric and Threshold Boolean Functions Are Exhaustive . . . . . . . . 1211--1212 Anonymous Information for Authors . . . . . . . . 1212--1212 Anonymous IEEE Computer Society Publications . . . 1212--1212 Anonymous 1983 Index IEEE Transactions on Computers Vol. C-32 . . . . . . . . . . 1212--1212
Tse-Yun Feng Editor's Notice . . . . . . . . . . . . 1--1 D. T. Lee and Joseph Y-T. Leung On the 2-Dimensional Channel Assignment Problem . . . . . . . . . . . . . . . . 2--6 Henk J. Sips Bit-Sequential Arithmetic for Parallel Processors . . . . . . . . . . . . . . . 7--20 Israel Koren and Melvin A. Breuer On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays . . 21--27 Svetlana P. Kartashev and Steven I. Kartashev Memory Allocations for Multiprocessor Systems That Incorporate Content-Addressable Memories . . . . . . 28--44 Vasilii Zakharov Parallelism and Array Processing . . . . 45--78 Jacob Savir and Gary S. Ditlow and Paul H. Bardell Random Pattern Testability . . . . . . . 79--90 Giuseppe Caruso A Local Selection Algorithm for Switching Function Minimization . . . . 91--97 Corina Reischer and Dan A. Simovici Graph Functions of Boolean Functions . . 97--99 Carla Savage A Systolic Design for Connectivity Problems . . . . . . . . . . . . . . . . 99--104 Dan Gordon and Israel Koren and Gabriel M. Silberman Embedding Tree Structures in VLSI Hexagonal Arrays . . . . . . . . . . . . 104--107 Anonymous Advertisement . . . . . . . . . . . . . 108--108 Anonymous IEEE Copyright Form . . . . . . . . . . 109--109 Anonymous Advertisement . . . . . . . . . . . . . 110--110 Anonymous IEEE Copyright Form . . . . . . . . . . 111--112
Yann-Hang Lee and K. G. Shin Design and Evaluation of a Fault-Tolerant Multiprocessor Using Hardware Recovery Blocks . . . . . . . . 113--124 M. Kobayashi Dynamic Characteristics of Loops . . . . 125--132 S. H. Bokhari Finding Maximum on an Array Processor with a Global Bus . . . . . . . . . . . 133--139 S. W. White and N. R. Strader II and V. T. Rhyne A VLSI-Based I/O Formatting Device . . . 140--149 C. A. Niznik Performance Evaluation of the Computer Network Dynamic Congestion Table Algorithm . . . . . . . . . . . . . . . 150--159 R. E. Bryant A Switch-Level Model and Simulator for MOS Digital Systems . . . . . . . . . . 160--177 Kuang Yung Liu Architecture for VLSI Design of Reed--Solomon Decoders . . . . . . . . . 178--189 M. R. Jerrum and S. Skyum Families of Fixed Degree Graphs for Processor Interconnection . . . . . . . 190--194 P. K. Varshney and C. R. P. Hartmann Sequential Fault Diagnosis of Modular Systems . . . . . . . . . . . . . . . . 194--197 R. K. Iyer Reliability Evaluation of Fault-Tolerant Systems---Effect of Variability in Failure Rates . . . . . . . . . . . . . 197--200 Anonymous Information for Authors . . . . . . . . 200--200 Anonymous IEEE Computer Society Publications . . . 200--200
J. E. Cuny and L. Snyder Testing the Coordination Predicate . . . 201--208 Kyu-Young Whang and G. Wiederhold and D. Sagalowicz Separability ---An Approach to Physical Database Design . . . . . . . . . . . . 209--222 S. H. Hosseini and J. G. Kuhl and S. M. Reddy A Diagnosis Algorithm for Distributed Computing Systems with Dynamic Failure and Repair . . . . . . . . . . . . . . . 223--233 S. L. Hakimi and K. Nakajima On Adaptive System Diagnosis . . . . . . 234--240 J. P. Shen and J. P. Hayes Fault-Tolerance of Dynamic-Full-Access Interconnection Networks . . . . . . . . 241--248 W. R. Franta and J. R. Heath Measurement and Analysis of HYPERchannel Networks . . . . . . . . . . . . . . . . 249--260 Benjamin W. Wah and Kuo-Liang Chen A Partitioning Approach to the Design of Selection Networks . . . . . . . . . . . 261--268 Guang Xing Wang and G. R. Redinbo Probability of State Transition Errors in a Finite State Machine Containing Soft Failures . . . . . . . . . . . . . 269--277 F. W. Burton and M. M. Huntbach Virtual Tree Machines . . . . . . . . . 278--280 P. Markenscoff A Deterministic Model for Evaluating the Performance of a Multiple Processor System with a Shared Bus . . . . . . . . 281--285 P. Golan Design of Totally Self-Checking Checker for 1-out-of-3 Code . . . . . . . . . . 285--285 D. Richards Complexity of Single-Layer Routing . . . 286--288 Anonymous Correction to ``A Pipelined Distributed Arithmetic PFFT Processor'' . . . . . . 288--288 Anonymous Information for Authors . . . . . . . . 288--288 Anonymous IEEE Computer Society Publications . . . 288--288
A. Thayse A Matrix Formalism for Asynchronous Implementation of Algorithms . . . . . . 289--300 F. U. Rosenberger and D. F. Wann A Computer Aided Procedure for Performing Static Loading Validation of Digital Logic Systems . . . . . . . . . 301--313 R. M. Tanner Fault-Tolerant 256K Memory Designs . . . 314--322 L. N. Bhuyan and D. P. Agrawal Generalized Hypercube and Hyperbus Structures for a Computer Network . . . 323--333 V. K. Vaishnavi Multidimensional Height-Balanced Trees 334--343 N. H. Christ and A. E. Terrano A Very Fast Parallel Processor . . . . . 344--350 A. K. Agrawala and E. G. Coffman, Jr. and M. R. Garey and S. K. Tripathi A Stochastic Optimization Algorithm Minimizing Expected Flow Times on Uniform Processors . . . . . . . . . . . 351--356 C.-S. Yeh and I. S. Reed and T. K. Truong Systolic Multipliers for Finite Fields $\mathrm{GF}(2^m)$ . . . . . . . . . . . 357--360 A. Apostolico and A. Negro Systolic Algorithms for String Manipulations . . . . . . . . . . . . . 361--364 K. Fukunaga and S. Yamada and H. S. Stone and T. Kasai A Representation of Hypergraphs in the Euclidean Space . . . . . . . . . . . . 364--367 D. S. Parker and C. S. Raghavendra The Gamma Network . . . . . . . . . . . 367--373 T. Rhyne Limitations on Carry Lookahead Networks 373--374 R. H. Mendez Benchmarks on Japanese and American Supercomputers --- Preliminary Results 374--374 F. J. Burkowski Correction to ``A Hardware Hashing Scheme in the Design of a Multiterm String Comparator'' . . . . . . . . . . 375--375 Anonymous Call for Papers Special Issue on Sorting 376--376 Anonymous Information for Authors . . . . . . . . 376--376 Anonymous IEEE Computer Society Publications . . . 376--376
B. W. Wah and Y. W. E. Ma MANIP --- A Multicomputer Architecture for Solving Combinatorial Extremum-Search Problems . . . . . . . . 377--390 H. Garcia-Molina and R. J. Lipton and J. Valdes A Massive Memory Machine . . . . . . . . 391--399 M. A. Fiol and J. L. A. Yebra and I. A. De Miquel Line Digraph Iterations and the (d, k) Digraph Problem . . . . . . . . . . . . 400--403 E. D. Karnin A Parallel Algorithm for the Knapsack Problem . . . . . . . . . . . . . . . . 404--408 R. A. Whiteside and N. S. Ostlund and P. G. Hibbard A Parallel Jacobi Diagonalization Algorithm for a Loop Multiple Processor System . . . . . . . . . . . . . . . . . 409--413 E. H. Wold and A. M. Despain Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations . . 414--426 F. P. Preparata and W. Lipski, Jr. Optimal Three-Layer Channel Routing . . 427--437 B. Krishnamurthy An Improved Min-Cut Algorithm for Partitioning VLSI Networks . . . . . . . 438--446 K. W. Doty New Designs for Dense Processor Interconnection Networks . . . . . . . . 447--450 F. S. Wong and M. R. Ito A Loop-Structured Switching Network . . 450--455 K. Wada and K. Hagihara and N. Tokura Area-Time Optimal Fast Implementation of Several Functions in a VLSI Model . . . 455--462 A. H. Karp Exponential and Logarithm by Sequential Squaring . . . . . . . . . . . . . . . . 462--464 Anonymous Information for Authors . . . . . . . . 464--464 Anonymous IEEE Computer Society Publications . . . 464--464
J. P. Hayes Foreword---liable and Fault-Tolerant Computing . . . . . . . . . . . . . . . 465--466 J. Savir and P. H. Bardell On Random Pattern Test Length . . . . . 467--474 D. Brahme and J. A. Abraham Functional Testing of Microprocessors 475--485 A. T. Dahbura and G. M. Masson An 0(n $^{2.5}$ ) Fault Identification Algorithm for Diagnosable Systems . . . 486--492 Y. Tamir and C. H. Sequin Design and Application of Self-Testing Comparators Implemented with MOS PLA's 493--506 T. S. Liu The Role of a Maintenance Processor for a General-Purpose Computer System . . . 507--517 Kuang-Hua Huang and J. A. Abraham Algorithm-Based Fault Tolerance for Matrix Operations . . . . . . . . . . . 518--528 K. G. Shin and Yann-Hang Lee Error Detection Process---Model, Design, and Its Impact on Computer Performance 529--540 E. J. McCluskey Verification Testing---A Pseudoexhaustive Test Technique . . . . 541--546 J. L. A. Hughes and E. J. McCluskey and D. J. Lu Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs . . . . . . . . . . . . . . . . . 546--550 D. G. Furchtgott and J. F. Meyer A Performability Solution Method for Degradable Nonrepairable Systems . . . . 550--554 J. P. Shen and F. J. Ferguson The Design of Easily Testable VLSI Array Multipliers . . . . . . . . . . . . . . 554--560 E. M. Aboulhamid and E. Cerny Built-In Testing of One-Dimensional Unilateral Iterative Arrays . . . . . . 560--564 P. Velaardi and R. K. Iyer A Study of Software Failures and Recovery in the MVS Operating System . . 564--568 C. S. Raghavendra and A. Avizienis and M. D. Ercegovac Fault Tolerance in Binary Tree Architectures . . . . . . . . . . . . . 568--572 Hao Dong Modified Berger Codes for Detection of Unidirectional Errors . . . . . . . . . 572--575 B. Bose and T. R. N. Rao Unidirectional Error Codes for Shift-Register Memories . . . . . . . . 575--578 E. Fujiwara and N. Mutoh and K. Matsuoka A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing 578--583 B. Bose and Der Jei Lin PLA Implementation of $k$-out-of-n Code TSC Checker . . . . . . . . . . . . . . 583--588 Anonymous Information for Authors . . . . . . . . 588--588 Anonymous IEEE Computer Society Publications . . . 588--588
T. Y. Feng Editor's Notice . . . . . . . . . . . . 589--589 Anonymous List of Referees . . . . . . . . . . . . 590--591 Jack B. Dennis and Guang-Rong Gao and Kenneth W. Todd Modeling the Weather with a Data Flow Supercomputer . . . . . . . . . . . . . 592--603 Harold S. Stone Database Applications of the FETCH-AND-ADD Instruction . . . . . . . 604--612 Wael Adi Fast Burst Error-Correction Scheme with Fire Code . . . . . . . . . . . . . . . 613--618 Robert R. Seban and Howard Jay Siegel Shuffling with the Illiac and PM2I SIMD Networks . . . . . . . . . . . . . . . . 619--625 Reinhard Manner Hardware Task/Processor Scheduling in a Polyprocessor Environment . . . . . . . 626--636 Sartaj Sahni Scheduling Multipipeline and Multiprocessor Computers . . . . . . . . 637--645 Gianfranco Bilardi and Franco P. Preparata An Architecture for Bitonic Sorting with Optimal VLSI Performance . . . . . . . . 646--651 Per E. Danielsson Serial/Parallel Convolvers . . . . . . . 652--667 Joseph Ja'Ja' and Robert Michael Owens VLSI Sorting with Reduced Hardware . . . 668--671 Ralf Hartmut Guting and Derick Wood Finding Rectangle Intersections by Divide-and-Conquer . . . . . . . . . . . 671--675 Farhad Hemmati and Donald L. Schilling and George Eichmann Adjacencies Between the Cycles of a Shift Register with Characteristic Polynomial (1 + x) $^n$ . . . . . . . . 675--677 R. R. Shively and W. V. Robinson and D. E. Orton Cascading Transmission Gates to Enhance Multiplier Performance . . . . . . . . . 677--679 Xu Zhiwei Multivalued Logic and Fuzzy Logic--Their Relationship, Minimization, and Application to Fault Diagnosis . . . . . 679--681 Arne A. Nilsson Comments on ``The Reliability of Periodically Repaired $n - 1 / n$ Parallel Redundant Systems'' . . . . . . 681--681 Peter Kornerup and David W. Matula Correction to ``Finite Precision Rational Arithmetic: An Arithmetic Unit'' . . . . . . . . . . . . . . . . . 682--682 Anonymous IEEE Copyright Form . . . . . . . . . . 683--684
Oliver Aberth Precise Scientific Computation with a Microprocessor . . . . . . . . . . . . . 685--690 Wesley W. Chu and Min-Tsung Lan and Joseph Hellerstein Estimation of Intermodule Communication (IMC) and Its Applications in Distributed Processing Systems . . . . . 691--699 Benjamin W. Wah A Comparative Study of Distributed Resource Sharing on Multiprocessors . . 700--711 Butler W. Lampson and Gene McDaniel and Severo M. Ornstein An Instruction Fetch Unit for a High-Performance Personal Computer . . . 712--730 Richard P. Brent and H. T. Kung Systolic VLSI Arrays for Polynomial GCD Computation . . . . . . . . . . . . . . 731--736 Shigeo Kaneda A Class of Odd-Weight-Column SEC--DED--SbED Codes for Memory System Applications . . . . . . . . . . . . . . 737--739 M. C. Er On Generating the $N$-ary Reflected Gray Codes . . . . . . . . . . . . . . . . . 739--741 James E. Smith On Separable Unordered Codes . . . . . . 741--743 Javad Khakbaz A Testable PLA Design with Low Overhead and High Fault Coverage . . . . . . . . 743--745 Hideo Fujiwara A New PLA Design for Universal Testability . . . . . . . . . . . . . . 745--750 Balakrishnan Krishnamurthy and Sheldon B. Akers On the Complexity of Estimating the Size of a Test Set . . . . . . . . . . . . . 750--753 Javad Khakbaz and Edward J. McCluskey Self-Testing Embedded Parity Checkers 753--756 Gerard G. L. Meyer A Diagnosis Algorithm for the BGM System Level Fault Model . . . . . . . . . . . 756--758 Teruhiko Yamada and Takashi Nanya Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults . . . . . . 758--761 Syed Zahoor Hassan Signature Testing of Sequential Machines 762--764 D. M. Miller and J. C. Muzio Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks . . . . . . . . . . . . . . . . 765--769 A. Yavuz Oruc A Classification of Cube-Connected Networks with a Simple Control Scheme 769--772 Carol A. Niznik Correction to ``Performance Evaluation of the Computer Network Dynamic Congestion Table Algorithm'' . . . . . . 772--772
Anonymous Editor's Notice . . . . . . . . . . . . 773--773 B. Chazelle Computational Geometry on a Systolic Chip . . . . . . . . . . . . . . . . . . 774--785 L. Lopriore Capability Based Tagged Architectures 786--803 P. Scheuermann and G. Wu Heuristic Algorithms for Broadcasting in Point-to-Point Computer Networks . . . . 804--811 S. S. Yau and Wonmo Hong Performance Optimization of a CSMA Protocol for Local Computer Networks . . 812--817 E. L. Leiss Data Integrity in Digital Optical Disks 818--827 John G. Cleary Compact Hash Tables Using Bidirectional Linear Probing . . . . . . . . . . . . . 828--834 A. M. Van Tilborg and L. D. Wittie Wave Scheduling---Decentralized Scheduling of Task Forces in Multicomputers . . . . . . . . . . . . . 835--844 D. T. Tang and Chin-Long Chen Logic Test Pattern Generation Using Linear Codes . . . . . . . . . . . . . . 845--850 Kei Hiraki and Kenji Nishida and Toshio Shimada Evaluation of Associative Memory Using Parallel Chained Hashing . . . . . . . . 851--855 G. D. Lakani An Improved Distribution Algorithm for Shortest Paths Problem . . . . . . . . . 855--857 C. Delorme and G. Farhi Large Graphs with Given Degree and Diameter---Part I . . . . . . . . . . . 857--860 Anonymous Information for Authors . . . . . . . . 860--860 Anonymous IEEE Computer Society Publications . . . 860--860
A. Thayse Synthesis and Asynchronous Implementation of Algorithms Using a Generalized $P$-Function Concept . . . . 861--868 H. D. Kirrmann and F. Kaufmann Poolpo --- A Pool of Processors for Process Control Applications . . . . . . 869--878 T. Sasao Input Variable Assignment and Output Phase Optimization of PLA's . . . . . . 879--894 D. L. Tuomenoksa and H. J. Siegel Task Preloading Schemes for Reconfigurable Parallel Processing Systems . . . . . . . . . . . . . . . . 895--905 In-Shek Hsu and I. S. Reed and T. K. Truong and Ke Wang and Chiunn-Shyong Yeh and L. J. Deutsch The VLSI Implementation of a Reed--Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm . . . . 906--911 J. L. W. Kessels Two Designs of a Fault-Tolerant Clocking System . . . . . . . . . . . . . . . . . 912--919 P. J. Varman and I. V. Ramakrishnan and D. S. Fussell A Robust Matrix-Multiplication Array . . 919--922 B. R. Iyer and J. B. Sinclair Dynamic Memory Interconnections for Rapid Access . . . . . . . . . . . . . . 923--927 C. C. Guest and M. M. Mirsalehi and T. K. Gaylord Residue Number System Truth-Table Look-Up Processing --- Moduli Selection and Logical Minimization . . . . . . . . 927--931 M. A. Bonuccelli and E. Lodi and L. Pagli External Sorting in VLSI . . . . . . . . 931--934 Ten-Chuan Hsiao and S. C. Seth An Analysis of the Use of Rademacher--Walsh Spectrum in Compact Testing . . . . . . . . . . . . . . . . 934--937 R. A. Mueller and V. H. Allan and J. Varghese The Complexity of Horizontal Word Encoding in Microprogrammed Machines . . 938--939 A. Y. Oruc and D. Prakash Routing Algorithms for Cellular Interconnection Arrays . . . . . . . . . 939--942 J. A. McPherson and C. R. Kime Diagnosis in the Presence of Known Faults . . . . . . . . . . . . . . . . . 943--947 Kuang-Wei Chiang and Z. G. Vranesic Comments on ``Fault Diagnosis of MOS Combinational Networks'' . . . . . . . . 947--947 Anonymous Call For Papers . . . . . . . . . . . . 948--948 Anonymous Information for Authors . . . . . . . . 948--948 Anonymous IEEE Computer Society Publications . . . 948--948
H. J. Segel and L. H. Jamieson Guest Editors' Introduction Parallel Processing . . . . . . . . . . . . . . . 949--951 Anonymous List of Referees . . . . . . . . . . . . 951--951 I. V. Ramakrishnan and P. J. Varman Modular Matrix Multiplication on a Linear Array . . . . . . . . . . . . . . 952--958 A. L. P. Chen and V. O. K. Li Improvement Algorithms for Semijoin Query Processing Programs in Distributed Database Systems . . . . . . . . . . . . 959--967 A. Nicolau and J. A. Fisher Measuring the Parallelism Available for Very Long Instruction Word Architectures 968--976 S. P. Kartashev and S. I. Kartashev Efficient Internode Communications in Reconfigurable Binary Trees . . . . . . 977--990 Chi-Yuan Chin and Kai Hwang Packet Switching Networks for Multiprocessors and Data Flow Computers 991--1003 K. B. Irani and I. H. Onyuksel A Closed-Form Solution for the Performance Analysis of Multiple-Bus Multiprocessor Systems . . . . . . . . . 1004--1012 S. Weiss and J. E. Smith Instruction Issue Logic in Pipelined Supercomputers . . . . . . . . . . . . . 1013--1022 H. Kasahara and S. Narita Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Processing . . . . . . . . . . . . . . . 1023--1029 U. Banerjee and D. D. Gajski Fast Execution of Loops with IF Statements . . . . . . . . . . . . . . . 1030--1033 T. N. Mudge and H. B. Al-Sadoun Memory Interference Models with Variable Connection Time . . . . . . . . . . . . 1033--1038 M. J. Carey and C. D. Thompson An Efficient Implementation of Search Trees on $[\lg {N} + 1]$ Processors . . 1038--1041 S. L. Stepoway and D. L. Wells and G. R. Kane A Multiprocessor Architecture for Generating Fractal Surfaces . . . . . . 1041--1045 D. A. Reed The Performance of Multimicrocomputer Networks Supporting Dynamic Workloads 1045--1048 Anonymous Information for Authors . . . . . . . . 1048--1048 Anonymous IEEE Computer Society Publications . . . 1048--1048
Tse-Yun Feng Preface . . . . . . . . . . . . . . . . 1049--1049 S. R. Vegdahl A Survey of Proposed Architectures for the Execution of Functional Languages 1050--1071 D. T. Lee and F. P. Preparata Computational Geometry --- A Survey . . 1072--1101 J. A. Stankovic A Perspective on Distributed Computer Systems . . . . . . . . . . . . . . . . 1102--1115 D. A. Rennels Fault-Tolerant Computing---Concepts and Examples . . . . . . . . . . . . . . . . 1116--1129 M. Fine and F. A. Tobagi Demand Assignment Multiple Access Schemes in Broadcast Bus Local Area Networks . . . . . . . . . . . . . . . . 1130--1159 S. L. Hurst Multiple-Valued Logic---its Status and its Future . . . . . . . . . . . . . . . 1160--1179 D. B. Gannon and J. Van Rosendale On the Impact of Communication Complexity on the Design of Parallel Numerical Algorithms . . . . . . . . . . 1180--1194 P. Heidelberger and S. S. Lavenberg Computer Performance Evaluation Methodology . . . . . . . . . . . . . . 1195--1220 J. L. Hennessy VLSI Processor Architecture . . . . . . 1221--1246 C. L. Seitz Concurrent VLSI Architectures . . . . . 1247--1265 Anonymous Information for Authors . . . . . . . . 1265--1265 Anonymous IEEE Copyright Form . . . . . . . . . . 1265--1265 Anonymous IEEE Computer Society Publications . . . 1265--1265 Anonymous 1984 Index IEEE Transactions on Computers Vol. C-33 . . . . . . . . . . 1265--1265
Anonymous Editor's Notice . . . . . . . . . . . . 1--1 Anonymous Membership Application . . . . . . . . . 2--2 David W. Matula and Peter Kornerup Finite Precision Rational Arithmetic: Slash Number Systems . . . . . . . . . . 3--18 C. S. Holt and J. E. Smith Self-Diagnosis in Distributed Systems 19--32 D. K. Pradhan Fault-Tolerant Multiprocessor Link and Bus Network Architectures . . . . . . . 33--45 C. S. Raghavendra and M. Gerla and A. Avizienis Reliable Loop Topologies for Large Local Computer Networks . . . . . . . . . . . 46--55 W. C. Yen and D. W. L. Yen and King-Sun Fu Data Coherence Problem in a Multicache System . . . . . . . . . . . . . . . . . 56--65 Guo-Jie Li and B. W. Wah The Design of Optimal Systolic Arrays 66--77 J. H. Tucker and M. A. Tapia and A. W. Bennett Boolean Integral Calculus for Digital Systems . . . . . . . . . . . . . . . . 78--81 T. Siegenthaler Decrypting a Class of Stream Ciphers Using Ciphertext Only . . . . . . . . . 81--85 F. Somenzi and S. Gai and M. Mezzalama and P. Prinetto Testing Strategy and Technique for Macro-Based Circuits . . . . . . . . . . 85--90 M. Rios and N. D. Georganas A Hybrid Multiple-Access Protocol for Data and Voice-Packet Over Local Area Networks . . . . . . . . . . . . . . . . 90--94 T. Kawaoka and Y. Takahashi Test Procedure Optimization for Layered Protocol Implementations . . . . . . . . 94--97 E. Best and F. Cristian Comments on ``Self-Stabilizing Programs: The Fault-Tolerant Capability of Self-Checking Programs'' . . . . . . . . 97--98 Anonymous Correction to Centennial Issue . . . . . 98--98 A. Mili Author's Reply . . . . . . . . . . . . . 98--98 Anonymous Information for Authors . . . . . . . . 99--99 Anonymous IEEE Copyright Form . . . . . . . . . . 99--99 Anonymous IEEE Computer Society Publications . . . 99--99
C. E. Leiserson Fat-trees: Universal Networks for Hardware-Efficient Supercomputing . . . 892--901 Nathaniel J. Davis IV and William Tsun-Yuk Hsu and Howard Jay Siegel Fault Location Techniques for Distributed Control Interconnection Networks . . . . . . . . . . . . . . . . 902--910 Jim Crammond A Comparative Study of Unification algorithms for OR-parallel Execution of Logic Languages . . . . . . . . . . . . 911--917 T. N. Mudge and H. B. Al-Sadoun A semi-Markov model for the performance of multiple-bus systems . . . . . . . . 934--942 G. F. Pfister and V. A. Norton ``Hot Spot'' Contention and Combining in Multistage Interconnection Networks . . 943--948
H. Garcia-Molina and J. Kent Evaluating Response Time in a Faulty Distributed Computing System . . . . . . 101--109 C. A. Papachristou and N. B. Sahgal An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories . . . . . . . . . 110--116 J. A. Stankovic An Application of Bayesian Decision Theory to Decentralized Control of Job Scheduling . . . . . . . . . . . . . . . 117--130 T. Sasao An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs . . . . . . . . . . . . . . . . . 131--140 N. J. Dimopoulos On the Structure of the Homogeneous Multiprocessor . . . . . . . . . . . . . 141--150 M. J. Atallah and S. Rao Kosaraju A Generalized Dictionary Machine for VLSI . . . . . . . . . . . . . . . . . . 151--155 M. Calzarossa and G. Serazzi A Characterization of the Variation in Time of Workload Arrival Patterns . . . 156--162 V. C. Jaswa and C. E. Thomas and J. T. Pedicone CPAC --- Concurrent Processor Architecture for Control . . . . . . . . 163--169 E. O. Nwachukwu Address Generation in an Array Processor 170--173 M. Arango and H. Badr and D. Gelernter Staged Circuit Switching . . . . . . . . 174--180 M. Kumar and D. M. Dias and J. R. Jump Switching Strategies in Shuffle-Exchange Packet-Switched Networks . . . . . . . . 180--186 B. P. Sinha and B. B. Bhattacharya On the Numerical Complexity of Short-Circuit Faults in Logic Networks 186--190 O. Ersoy Semisystolic Array Implementation of Circular, Skew Circular, and Linear Convolutions . . . . . . . . . . . . . . 190--196 Anonymous Information for Authors . . . . . . . . 196--196 Anonymous IEEE Computer Society Publications . . . 196--196
Chien-Chung Shen and Wen-Hsiang Tsai A Graph Matching Approach to Optimal Task Assignment in Distributed Computing Systems Using a Minimax Criterion . . . 197--203 Yung-Terng Wang and R. J. T. Morris Load Sharing in Distributed Systems . . 204--217 E. E. Lindstrom and J. S. Vitter The Design and Analysis of BucketSort for Bubble Memory Secondary Storage . . 218--233 J. E. Smith and J. R. Goodman Instruction Cache Replacement Policies and Organizations . . . . . . . . . . . 234--241 M. J. Flynn and J. D. Johnson and S. P. Wakefield On Instruction Sets and Their Fornmts 242--254 D. P. Agrawal and Ja-Song Leu Dynamic Accessibility Testing and Path Length Optimization of Multistage Interconnection Networks . . . . . . . . 255--266 M. Imase and T. Soneoka and K. Okada Connectivity of Regular Directed Graphs with Small Diameters . . . . . . . . . . 267--273 D. C. Sorensen Analysis of Pairwise Pivoting in Gaussian Elimination . . . . . . . . . . 274--278 L. N. Bhuyan An Analysis of Processor-Memory Interconnection Networks . . . . . . . . 279--283 K. K. Saluja and K. Kinoshita Test Pattern Generation for API Faults in RAM . . . . . . . . . . . . . . . . . 284--287 T. H. Spencer and J. Savir Layout Influences Testability . . . . . 287--290 K. R. Sloan, Jr. Comments on ``A Computer Algorithm for Calculating the Product $A B$ Modulo $M$'' . . . . . . . . . . . . . . . . . 290--292 Anonymous Information for Authors . . . . . . . . 292--292 Anonymous IEEE Computer Society Publications . . . 292--292
Eugene E. Lindstrom and Jeffrey Scott Vitter and C. K. Wong Introduction --- Sorting . . . . . . . . 293--295 Anonymous List of Referees . . . . . . . . . . . . 295--295 Howard B. Demuth Electronic Data Sorting . . . . . . . . 296--310 Eric Dittert and Michael J. O'Donnell Lower Bounds for Sorting with Realistic Instruction Sets . . . . . . . . . . . . 311--317 Heikki Mannila Measures of Presortedness and Optimal Sorting Algorithms . . . . . . . . . . . 318--325 Larry Rudolph A Robust Sorting Network . . . . . . . . 326--335 Gianfranco Bilardi and Franco P. Preparata A Minimum Area VLSI Network for $O(\log n)$ Time Sorting . . . . . . . . . . . . 336--343 Tom Leighton Tight Bounds on the Complexity of Parallel Sorting . . . . . . . . . . . . 344--354 Alan R. Siegel Minimum Storage Sorting Networks . . . . 355--361 Lutz M. Wegner Quicksort for Equal Keys . . . . . . . . 362--367 Philip J. Janus and Edmund A. Lamagna An Adaptive Method for Unknown Distributions in Distributive Partitioned Sorting . . . . . . . . . . 367--372 Doron Rotem and Nicola Santoro and Jeffrey B. Sidney Distributed Sorting . . . . . . . . . . 372--376 Shmuel Zaks Optimal Distributed Algorithms for Sorting and Ranking . . . . . . . . . . 376--379 Robert Michael Owens and Joseph Ja'Ja' Parallel Sorting with Serial Memories 379--383 Sai Choi Kwan and Jean-Loup Baer The I/O Performance of Multiway Mergesort and Tag Sort . . . . . . . . . 383--387 C. M. McCulloch Why merge? --- An examination of disk sorting strategy . . . . . . . . . . . . 387--391 Anonymous Calls for Papers . . . . . . . . . . . . 392--392
H. M. Shao and T. K. Truong and L. J. Deutsch and J. H. Yuen and I. S. Reed A VLSI Design of a Pipeline Reed--Solomon Decoder . . . . . . . . . 393--403 L. M. Ni and Kai Hwang Vector-Reduction Techniques for Arithmetic Pipelines . . . . . . . . . . 404--411 Kyungsook Yoon Lee On the Rearrangeability of $2(\log_2 {N}) - 1$ Stage Permutation Networks . . 412--425 S. K. Jain and V. D. Agrawal Modeling and Test Generation Algorithms for MOS Circuits . . . . . . . . . . . . 426--433 D. K. Pradhan Dynamically Restructurable Fault-Tolerant Processor Network Architectures . . . . . . . . . . . . . 434--447 T. Leighton and C. E. Leiserson Wafer-Scale Integration of Systolic Arrays . . . . . . . . . . . . . . . . . 448--461 Hung-Chang Du On the Performance of Synchronous Multiprocessors . . . . . . . . . . . . 462--466 J. P. Robinson Segmented Testing . . . . . . . . . . . 467--471 H. Schmeck and H. Schroder Dictionary Machines for Different Models of VLSI . . . . . . . . . . . . . . . . 472--475 J. H. Lang and C. A. Zukowski and R. O. Lamaire and Chae Han Integrated-Circuit Logarithmic Arithmetic Units . . . . . . . . . . . . 475--483 S. Ashtaputre and C. D. Savage Systolic Arrays with Embedded Tree Structures for Connectivity Problems . . 483--484 P. S. Moharir Extending the Scope of Golub's Method Beyond Complex Multiplication . . . . . 484--487 Anonymous Call for Papers Special Issue on Fault-Tolerant Computing . . . . . . . . 488--488 Anonymous Information for Authors . . . . . . . . 488--488 Anonymous IEEE Computer Society Publications . . . 488--488
Wesley W. Chu and Joseph Hellerstein The Exclusive-Writer Approach to Updating Replicated Files in Distributed Processing Systems . . . . . . . . . . . 489--500 Harry A. G. Wijshoff and Jan van Leeuwen The Structure of Periodic Storage Schemes for Parallel Memories . . . . . 501--505 Jacques Lenfant A Versatile Mechanism to Move Data in an Array Processor . . . . . . . . . . . . 506--522 Ming Huei Young and Saburo Muroga Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables 523--541 Vladimir Cherkassky and Miroslaw Malek On Permuting Properties of Regular Rectangular SW-Banyans . . . . . . . . . 542--546 M. Ashraf Chughtai Complete Binary Spanning Trees of the Eight Nearest Neighbor Array . . . . . . 547--549 Janusz Rajski and Jerzy Tyszer Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays . . . . . . . . . . . . . . 549--553 Shiyi Xu and Stephen Y. H. Su Detecting I/O and Internal Feedback Bridging Faults . . . . . . . . . . . . 553--557 Larry A. Dunning SEC--BED--DED Codes for Error Control in Byte-Organized Memory Systems . . . . . 557--562 Martin Cohn Counting Sequences with Large Local Distance . . . . . . . . . . . . . . . . 562--562 Abha Moitra and S. Sitharama Iyengar A Maximally Parallel Balancing Algorithm for Obtaining Complete Balanced Binary Trees . . . . . . . . . . . . . . . . . 563--565 M. Davio and C. Ronse Insertion Networks . . . . . . . . . . . 565--570 Peter M. Fenwick Some Aspects of the Dynamic Behavior of Hierarchical Memories . . . . . . . . . 570--573 F. J. Taylor and G. Papadourakis and A. Skavantzos and A. Stouraitis A Radix-$4$ FFT Using Complex RNS Arithmetic . . . . . . . . . . . . . . . 573--576 Stanislaw H. Zak and Kai Hwang Polynomial Division on Systolic Arrays 577--578 Arnold L. Rosenberg A Hypergraph Model for Fault-Tolerant VLSI Processor Arrays . . . . . . . . . 578--584 D. T. Lee and Franco P. Preparata Correction to ``Computational Geometry --- A Survey'' . . . . . . . . . . . . . 584--584
Anonymous Editor's Notice . . . . . . . . . . . . 585--587 Yang-Chang Hong Efficient Computing of Relational Algebraic Primitives in a Database Machine Architecture . . . . . . . . . . 588--595 N. Gaitanis Totally Self-Checking Checkers for Low-Cost Arithmetic Codes . . . . . . . 596--601 J. McGough and M. Smotherman and K. S. Trivedi The Conservativeness of Reliability Estimates Based on Instantaneous Coverage . . . . . . . . . . . . . . . . 602--609 W. C. Kabat and A. S. Wojcik Automated Synthesis of Combinational Logic Using Theorem-Proving Techniques 610--632 Z. Rosberg Process Scheduling in a Computer System 633--645 Thu Van Vu Efficient Implementations of the Chinese Remainder Theorem for Sign Detection and Residue Decoding . . . . . . . . . . . . 646--651 H.-W. Lang and M. Schimmler and H. Schmeck and H. Schroder Systolic Sorting on a Mesh-Connected Network . . . . . . . . . . . . . . . . 652--658 M. Abramovici and P. R. Menon A Practical Approach to Fault Simulation and Test Generation for Bridging Faults 658--663 M. J. Atallah On Symmetry Detection . . . . . . . . . 663--666 M. Chlamtac and I. Harary The Shift X Parity Watch Algorithm for Raster Scan Displays . . . . . . . . . . 666--673 H. S. Ranganath and S. G. Shiva Correlation of Adjacent Pixels for Multiple Image Registration . . . . . . 674--677 L. W. Hawkes A Regular Fault-Tolerant Architecture for Interconnection Networks . . . . . . 677--680 Anonymous Correction to ``Modeling and Test Generation Algorithms for MOS Circuits'' 680--680 Anonymous Information for Authors . . . . . . . . 680--680 Anonymous IEEE Computer Society Publications . . . 680--680
Hao-Yung Lo and Y. Aoki Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array . . . . . . . . . . . . . . 681--691 D. B. Aspinwall and Y. N. Patt Retrofitting the VAX-11/780 Microarchitecture for IEEE Floating Point Arithmetic --- Implementation Issues, Measurements, and Analysis . . . 692--708 C. C. Wang and T. K. Troung and H. M. Shao and L. J. Deutsch and J. K. Omura and I. S. Reed VLSI Architectures for Computing Multiplications and Inverses in $\mathrm{GF}(2^m)$ . . . . . . . . . . . 709--717 A. T. Dahbura and G. M. Masson and Che-Liang Yang Self-Implicating Structures for Diagnosable Systems . . . . . . . . . . 718--723 S. Majerski Square-Rooting Algorithms for High-Speed Digital Circuits . . . . . . . . . . . . 724--733 A. L. Fisher and H. T. Kung Synchronizing Large VLSI Processor Arrays . . . . . . . . . . . . . . . . . 734--740 R. Gnanasekaran A Fast Serial-Parallel Binary Multiplier 741--744 B. Smilauer General Model for Memory Interference in Multiprocessors and Mean Value Analysis 744--751 C. M. Krishna and K. G. Shin and R. W. Butler Ensuring Fault Tolerance of Phase-Locked Clocks . . . . . . . . . . . . . . . . . 752--756 George Marsaglia Note on a Proposed Test for Random Number Generators . . . . . . . . . . . 756--758 N. Gaitanis A Totally Self-Checking Error Indicator 758--761 V. Pitchumani and E. P. Stabler Verification of Register Transfer Level Parallel Control Sequences . . . . . . . 761--765 Nam Sung Woo and A. Agrawala A Symmetric Tree Structure Interconnection Network and its Message Traffic . . . . . . . . . . . . . . . . 765--769 G. E. Carlsson and J. E. Cruthirds and H. B. Sexton and C. G. Wright Interconnection Networks Based on a Generalization of Cube-Connected Cycles 769--772 A. Y. Oruc and M. Y. Oruc and N. Balabanian Reconfiguration Algorithms for Interconnection Networks . . . . . . . . 773--776 Anonymous Information for Authors . . . . . . . . 776--776 Anonymous IEEE Computer Society Publications . . . 776--776
A.-H. Esfahanian and S. L. Hakimi Fault-Tolerant Routing in DeBruijn Communication Networks . . . . . . . . . 777--788 N. Takagi and H. Yasuura and S. Yajima High-speed VLSI multiplication algorithm with a redundant binary addition tree 789--796 S. J. Mackinnon and P. D. Taylor and H. Meijer and S. G. Akl An Optimal Algorithm for Assigning Cryptographic Keys to Control Access in a Hierarchy . . . . . . . . . . . . . . 797--802 Subhash C. Kak Encryption and error-correction coding using $D$ sequences . . . . . . . . . . 803--809 V. S. Iyengar and L. L. Kinney Concurrent Fault Detection in Microprogrammed Control Units . . . . . 810--821 J. H. Applegate and M. R. Douglas and Y. Gursel and P. Hunter and C. L. Seitz and G. J. Sussman A Digital Orrery . . . . . . . . . . . . 822--831 D. Quammen and J. P. Kearns and M. L. Soffa Efficient Storage Management for Temporary Values in Concurrent Programming Languages . . . . . . . . . 832--840 A. K. Somani and V. K. Agarwal An Efficient Unsorted VLSI Dictionary Machine . . . . . . . . . . . . . . . . 841--852 D. Z. Du and D. F. Hsu and F. K. Hwang Doubly Linked Ring Networks . . . . . . 853--855 D. Lee Comparator with Completion Signal . . . 855--857 Jean-Michel Muller Discrete basis and computation of elementary functions . . . . . . . . . . 857--862 K. J. Stelzer and M. A. Gordon Implementation of a Constrained Regularization Program (CONTIN) on a Desktop Computer . . . . . . . . . . . . 862--863 J. W. Wong and M. H. Ammar Analysis of Broadcast Delivery in a Videotex System . . . . . . . . . . . . 863--866 S.-Y. R. Li Fast Constant Division Routines . . . . 866--869 H. Krawczyk and M. Kubale An Approximation Algorithm for Diagnostic Test Scheduling in Multicomputer Systems . . . . . . . . . 869--872 Anonymous Information for Authors . . . . . . . . 872--872 Anonymous IEEE Computer Society Publications . . . 872--872
J. T. Mccall and J. G. Tront and F. G. Gray and R. M. Haralick and W. M. McCormack Parallel Computer Architectures and Problem Solving Strategies for the Consistent Labeling Problem . . . . . . 973--980 S. Arya An Optimal Instruction-Scheduling Model for a Class of Vector Processors . . . . 981--995 R. Klatte and C. P. Ullrich and J. W. Von Gudenberg Arithmetic Specification for Scientific Computation in ADA . . . . . . . . . . . 996--1005 W. M. Loucks and V. C. Hamacher and B. R. Preiss and L. Wong Short-Packet Transfer Performance in Local Area Ring Networks . . . . . . . . 1006--1014 G. Z. Qadah and K. B. Irani A Database Machine for Very Large Relational Databases . . . . . . . . . . 1015--1025 B. Bose and Der Jei Lin Systematic Unidirectional Error-Detecting Codes . . . . . . . . . 1026--1032 J. A. B. Fortes and C. S. Raghavendra Gracefully Degradable Processor Arrays 1033--1044 K. Kant Finding Interferences Between Rectangular Paths . . . . . . . . . . . 1045--1049 R. Shimada and Y. Ohkura and J. Aoe Nonbinary Arithmetic AN Codes Using Odd Radix Expressions . . . . . . . . . . . 1050--1056 N. N. Biswas On Bit Steering in the Minimization of the Control Memory of Microprogrammed Processors . . . . . . . . . . . . . . . 1057--1061 J. H. Graham and T. F. Kadela Parallel Algorithms and Architectures for Optimal State Estimation . . . . . . 1061--1068 Anonymous Information for Authors . . . . . . . . 1068--1068 Anonymous IEEE Computer Society Publications . . . 1068--1068 J. H. Wensley Further Comments on ``The Reliability of Periodically Repaired $n - 1 / n$ Parallel Redundant Systems'' . . . . . . 1068--1068
D. Hoffman The Specification of Communication Protocols . . . . . . . . . . . . . . . 1102--1113 T. J. LeBlanc and S. A. Friedberg HPC: A Model of Structure and Change in Distributed Systems . . . . . . . . . . 1114--1129 J. Stankovic and K. Ramamritham and S. Chang Evaluation of a flexible task scheduling algorithm for distributed hard real-time systems . . . . . . . . . . . . . . . . 1130--1143 B. Wah and J. Juang Resource scheduling for local computer systems with a multiaccess network . . . 1144--1157 S. K. Sarin and B. Blaustein and C. Kaufman System Architecture for Partition-Tolerant Distributed Databases 1158--1163 W. Zwaenepoel Implementation and performance of pipes in the V-System . . . . . . . . . . . . 1174--1178 Carla Schlatter Ellis Distributed Data Structures: a Case Study . . . . . . . . . . . . . . . . . 1178--1185 M. Livny and U. Manber Distributed Computation Via Active Messages . . . . . . . . . . . . . . . . 1185--1190
D. I. Moldovan and J. A. B. Fortes Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays . . . . . . . 1--12 A. Vergis and K. Steiglitz Testability Conditions for Bilateral Arrays of Combinational Cells . . . . . 13--22 I. Hartimo and K. Kronlof and O. Simula and J. Skytta DFSP: a Data Flow Signal Processor . . . 23--33 A. Bilgory and D. D. Gajski A Heuristic for Suffix Solutions . . . . 34--42 D. L. Tuomenoksa and H. J. Siegel Determining an Optimal Secondary Storage Service Rate for the PASM Control System 43--53 P. G. Harrison An Enhanced Approximation by Pair-Wise Analysis of Servers for Time Delay Distributions in Queueing Networks . . . 54--61 A. Aggarwal Optimal Bounds for Finding Maximum on Array of Processors with $k$ Global Buses . . . . . . . . . . . . . . . . . 62--64 J. Savir The Bidirectional Double Latch (BDDL) 65--66 J. Calvo and J. I. Acha and M. Valencia Asynchronous Modular Arbiter . . . . . . 67--70 F. Ozguner Deductive Fault Simulation of Internal Faults of Inverter-Free Circuits and Programmable Logic Arrays . . . . . . . 70--73 M. Journeau A Note on the Restricted Range Cutting Algorithm . . . . . . . . . . . . . . . 73--73 C. Guerra Systolic Algorithms for Local Operations on Images . . . . . . . . . . . . . . . 73--77 L. Trevillyan and W. Joyner and L. Berman Global Flow Analysis in Automatic Logic Design . . . . . . . . . . . . . . . . . 77--81 J. Rajski and J. Tyszer The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's . . . . . . . . . . . . . 81--85 B. B. Bhattacharya and B. Gupta On the Impossible Class of Faulty Functions in Logic Networks Under Short Circuit Faults . . . . . . . . . . . . . 85--90 A. Sengupta and A. Sen and S. Bandyopadhyay On System Diagnosability in the Presence of Hybrid Faults . . . . . . . . . . . . 90--93 I. Koren Comments on ``The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors'' . . . . . . . . . . . . . . 93--93 A. L. Rosenberg Author's Reply . . . . . . . . . . . . . 93--94 D. K. Pradhan Correction to ``Fault-Tolerant Multiprocessor Link and Bus Architectures'' . . . . . . . . . . . . 94--94 Anonymous Information for Authors . . . . . . . . 95--95 Anonymous IEEE Copyright Form . . . . . . . . . . 95--95 Anonymous IEEE Computer Society Publications . . . 95--95
J. C. Muzio and I. C. Rosenberg Introduction --- Multiple-Valued Logic 97--98 D. A. Rich A Survey of Multivalued Memories . . . . 99--106 J. P. Hayes Uncertainty, Energy, and Multiple-Valued Logics . . . . . . . . . . . . . . . . . 107--114 A. Maruoka Complexity Based on Partitioning of Boolean Circuits and their Relation to Multivalued Circuits . . . . . . . . . . 115--123 M. H. Abd-El Barr and S. G. Zaky and Z. G. Vranesic Synthesis of Multivalued Multithreshold Functions for CCD Implementation . . . . 124--133 P. W. Besslich Heuristic Minimization of MVL Functions: a Direct Cover Approach . . . . . . . . 134--144 T. L. Huntsberger and C. Rangarajan and S. N. Jayaramamurthy Representation of Uncertainty in Computer Vision Using Fuzzy Sets . . . . 145--156 J. L. Mangin and K. W. Current Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits . . . . . . . . . . . . . . . . 157--161 T. Yamakawa and T. Miki The Current Mode Fuzzy Logic Integrated Circuits Fabricated by the Standard CMOS Process . . . . . . . . . . . . . . . . 161--167 Mou Hu and K. C. Smith Ternary Scan Design for VLSI Testability 167--170 A. Sengupta and A. Sen On the Diagnosability of a General Model of System with Three-Valued Test Outcomes . . . . . . . . . . . . . . . . 170--173 C. Reischer and D. A. Simovici Iteration Properties of Multivalued Switching Functions . . . . . . . . . . 173--178 M. Mukaidono Regular Ternary Logic Functions --- Ternary Logic Functions Suitable for Treating Ambiguity . . . . . . . . . . . 179--183 C. Moraga Design of a Multiple-Valued Systolic System for the Computation of the Chrestenson Spectrum . . . . . . . . . . 183--188 Anonymous Information for Authors . . . . . . . . 188--188 Anonymous IEEE Computer Society Publications . . . 188--188
I. V. Ramakrishnan and D. S. Fussell and A. Silberschatz Mapping Homogeneous Graphs on Linear Arrays . . . . . . . . . . . . . . . . . 189--209 R. Dechter and L. Kleinrock Broadcast Communications and Distributed Algorithms . . . . . . . . . . . . . . . 210--219 D. Towsley Approximate Models of Multiple Bus Multiprocessor Systems . . . . . . . . . 220--228 L. M. Patnaik and R. Govindarajan and N. S. Ramadoss Design and Performance Evaluation of EXMAN: An EXtended MANchester Data Flow Computer . . . . . . . . . . . . . . . . 229--244 F. Baccelli and P. Mussi An Asynchronous Parallel Interpreter for Arithmetic Expressions and Its Evaluation . . . . . . . . . . . . . . . 245--256 B. Trees and S. P. Kartashev and S. I. Kartashev Data Exchange Optimization in Reconfigurable . . . . . . . . . . . . . 257--273 D. Brand Detecting Sneak Paths in Transistor Networks . . . . . . . . . . . . . . . . 274--278 C. V. Ramamoorthy and Y. W. E. Ma Optimal Reconfiguration Strategies for Reconfigurable Computer Systems with no Repair . . . . . . . . . . . . . . . . . 278--280 S. Guha and A. Sen On Fault-Tolerant Distributor Communication Architecture . . . . . . . 281--283 L. M. Casey Comments on ``The Design of a Reliable Remote Procedure Call Mechanism'' . . . 283--284 Anonymous Information for Authors . . . . . . . . 284--284 Anonymous IEEE Computer Society Publications . . . 284--284
Anonymous Editor's Notice . . . . . . . . . . . . 285--285 S. B. Akers and D. K. Pradhan Fault-Tolerant Computing: An Introduction . . . . . . . . . . . . . . 285--287 Anonymous List of Referees . . . . . . . . . . . . 287--287 D. J. Taylor and C.-J. H. Seger Robust Storage Structures for Crash Recovery . . . . . . . . . . . . . . . . 288--295 P. Banerjee and J. A. Abraham Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems 296--306 C. S. Raghavendra and A. Varma Fault-Tolerant Multiprocessors with Redundant-Path Interconnection Networks 307--316 N. R. Saxena and J. P. Robinson Accumulator Compression Testing . . . . 317--321 E. De Souza e Silva and H. R. Gail Calculating Cumulative Operational Time Distributions of Repairable Computer Systems . . . . . . . . . . . . . . . . 322--332 M. Smotherman and R. M. Geist and K. S. Trivedi Provably Conservative Approximations to Complex Reliability Models . . . . . . . 333--338 T. Krol and T. Krol $(N, K)$ Concept Fault Tolerance . . . . 339--349 B. Bose Burst Unidirectional Error-Detecting Codes . . . . . . . . . . . . . . . . . 350--353 A. T. Dahbura An Efficient Algorithm for Identifying the Most Likely Fault Set in a Probabilistically Diagnosable System . . 354--356 A. S. Mahmudul Hassan and V. K. Agarwal A Fault-Tolerant Modular Architecture for Binary Trees . . . . . . . . . . . . 356--361 M. S. Abadir and M. A. Breuer Test Schedules for VLSI Circuits Having Built-In Test Hardware . . . . . . . . . 361--367 Laung-Terng Wang and E. J. McCluskey Condensed Linear Feedback Shift Register (LFSR) Testing --- A Pseudoexhaustive Test Technique . . . . . . . . . . . . . 367--370 K. G. Shin and Yann-Hang Lee Measurement and Application of Fault Latency . . . . . . . . . . . . . . . . 370--375 M. S. Abadir and H. K. Reghbati Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams . . . . . . . . . . . . . . . . 375--379 S. Bozorgui-Nesbat and E. J. McCluskey Lower Overhead Design for Testability of Programmable Logic Arrays . . . . . . . 379--383 K. K. Saluja and R. Dandapani An Alternative to Scan Design Methods for Sequential Machines . . . . . . . . 384--388 Anonymous Information for Authors . . . . . . . . 388--388 Anonymous IEEE Computer Society Publications . . . 388--388
J. Blazewicz and M. Drabowski and J. Weglarz Scheduling Multiprocessor Tasks to Minimize Schedule Length . . . . . . . . 389--393 D. Nikolos and N. Gaitanis and G. Philokyprou Systematic $t$-Error Correcting/All Unidirectional Error Detecting Codes . . 394--402 J. S. Vitter and R. A. Simons New Classes for Parallel Complexity: a Study of Unification and Other Complete Problems for P . . . . . . . . . . . . . 403--418 E. De Souza e Silva and S. S. Lavenberg and R. R. Muntz A Clustering Approximation Technique for Queueing Network Models with a Large Number of Chains . . . . . . . . . . . . 419--430 H. V. Jagadish and R. G. Mathews and T. Kailath and J. A. Newkirk A Study of Pipelining in Computing Arrays . . . . . . . . . . . . . . . . . 431--440 I. P. Page and J. Hagins Improving the Performance of Buddy Systems . . . . . . . . . . . . . . . . 441--447 C. M. Krishna and K. G. Shin On Scheduling Tasks with a Quick Recovery from Failure . . . . . . . . . 448--455 W. A. Davis and De-Lei Lee Fast Search Algorithms for Associative Memories . . . . . . . . . . . . . . . . 456--461 V. Ramachandran Algorithmic Aspects of MOS VLSI Switch-Level Simulation with Race Detection . . . . . . . . . . . . . . . 462--475 J. P. Roth Minimization by the D Algorithm . . . . 476--478 J. J. Thomas and J. M. Keller and G. N. Larsen The Calculation of Multiplicative Inverses Over $\mathrm{GF}(P)$ Efficiently Where $P$ is a Mersenne Prime . . . . . . . . . . . . . . . . . 478--482 Wang Hongyuan and S. C. Lee Comments on ``Sign/Logarithm Arithmetic for FFT Implementation'' . . . . . . . . 482--484 Anonymous Information for Authors . . . . . . . . 484--484 Anonymous IEEE Computer Society Publications . . . 484--484 E. E. Swartzlander, Jr. and D. V. Satish Chandra and H. T. Nagle, Jr. Authors' Reply . . . . . . . . . . . . . 484--484
Anonymous Editor's Notice . . . . . . . . . . . . 485--485 Anonymous 1985 Referee List . . . . . . . . . . . 486--488 Jean-Luc Gaudlot Structure Handling in Data-Flow Systems 489--502 Che-Liang Yang and Gerald M. Masson A Fault Identification Algorithm for ti-Diagnosable Systems . . . . . . . . . 503--510 Ravishankar K. Iyer and David J. Rossetti A Measurement-Based Model for Workload Dependence of CPU Errors . . . . . . . . 511--519 Walid Abu-Sufah and Harlan E. Husmann and David J. Kuck On Input/Output Speedup in Tightly Coupled Multiprocessors . . . . . . . . 520--530 Oscar H. Ibarra and Sam M. Kim and Michael A. Palis Designing Systolic Algorithms Using Sequential Machines . . . . . . . . . . 531--542 Teofilo F. Gonzalez and Sing-Ling Lee Routing Multiterminal Nets Around a Rectangle . . . . . . . . . . . . . . . 543--549 Yahiko Kambayashi and Saburo Muroga Properties of Wired Logic . . . . . . . 550--563 Timothy C. K. Chou and Jacob A. Abraham Distributed Control of Computer Systems 564--567 Guo-Jie Li and Benjamin W. Wah Coping with Anomalies in Parallel Branch-and-Bound Algorithms . . . . . . 568--573 Manoj Kumar and J. R. Jump Performance of Unbuffered Shuffle-Exchange Networks . . . . . . . 573--578 L. Ciminiera and A. Serra A Connecting Network with Fault Tolerance Capabilities . . . . . . . . . 578--580
Anonymous Editor's Notice . . . . . . . . . . . . 581--582 B. Gavish and H. Pirkul Computer and Database Location in Distributed Computer Systems . . . . . . 583--590 Shing-Tsaan Huang and S. K. Tripathi Finite State Model and Compatibility Theory: New Analysis Tools for Permutation Networks . . . . . . . . . . 591--601 J. P. Hayes Pseudo-Boolean Logic Circuits . . . . . 602--612 Tony Cheung and James E. Smith A Simulation Study of the CRAY X-MP Memory System . . . . . . . . . . . . . 613--622 W. J. Van Gils A Triple Modular Redundancy Technique Providing Multiple-Bit Error Protection Without Using Extra Redundancy . . . . . 623--631 C. E. McDowell and W. F. Appelbe Processor Scheduling for Linearly Connected Parallel Processors . . . . . 632--638 Che-Liang Yang and G. M. Masson and R. A. Leonetti On Fault Isolation and Identification in t1/t1-Diagnosable Systems . . . . . . . 639--643 L. Kleeman and A. Cantoni Can Redundancy and Masking Improve the Performance of Synchronizers? . . . . . 643--646 C. L. Chen Byte-Oriented Error-Correcting Codes for Semiconductor Memory Systems . . . . . . 646--648 M. Sousa and F. Taylor Complex Integer to Complex Residue Encoding . . . . . . . . . . . . . . . . 648--650 V. Konard Efficient Computation of the Maximum of the Sum of Two Sequences and Applications . . . . . . . . . . . . . . 651--653 P. H. Bardell and W. H. McAnney Pseudorandom Arrays for Built-In Tests 653--658 K. K. Saluja and R. Dandapani Testable Design of Single-Output Sequential Machines Using Checking Experiments . . . . . . . . . . . . . . 658--662 C. S. Raghavendra and V. K. Prasanna Kumar Permutations on Illiac IV-Type Networks 662--669 Jong Won Park An Efficient Memory System for Image Processing . . . . . . . . . . . . . . . 669--674 Anonymous Information for Authors . . . . . . . . 675--675 Anonymous IEEE Copyright Form . . . . . . . . . . 675--675 Anonymous IEEE Computer Society Publications . . . 675--675
R. E. Bryant Graph-Based Algorithms for Boolean Function Manipulation . . . . . . . . . 677--691 J. E. Smith and S. Weiss and N. Y. Pang A Simulation Study of Decoupled Architecture Computers . . . . . . . . . 692--702 I. Koren and Z. Koren and S. Y. H. Su Analysis of a Class of Recovery Procedures . . . . . . . . . . . . . . . 703--712 S. Nakamura Algorithms for Iterative Array Multiplication . . . . . . . . . . . . . 713--719 M. Kobayashi An Empirical Study of Task Switching Locality in MVS . . . . . . . . . . . . 720--731 A. Hlawiczka Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer . . . . . . . . . . . 732--741 S. M. Reddy and M. K. Reddy Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits . . . . . . . . . . . . . . . . 742--754 A. Pal An Algorithm for Optimal Logic Design Using Multiplexers . . . . . . . . . . . 755--757 S. H. Bokhari and A. D. Raza Reducing the Diameters of Computer Networks . . . . . . . . . . . . . . . . 757--761 C. McMullen and J. Shearer Prime Implicants, Minimum Covers, and the Complexity of Logic Simplification 761--762 N. B. Chakraborti and J. S. Soundararajan and A. L. N. Reddy An Implementation of Mixed-Radix Conversion for Residue Number Applications . . . . . . . . . . . . . . 762--764 Y. H. Tsin Finding Lowest Common Ancestors in Parallel . . . . . . . . . . . . . . . . 764--769 M. Abramovici and P. R. Menon and D. T. Miller Checkpoint Faults are not Sufficient Target Faults for Test Generation . . . 769--771 Anonymous Calls for Papers Special Issue on Parallel and Distributed Processing . . 772--772 Anonymous Information for Authors . . . . . . . . 772--772 Anonymous IEEE Computer Society Publications . . . 772--772
V. K. Vaishnavi On the Height of Multidimensional Height-Balanced Trees . . . . . . . . . 773--780 I. S. Reed and T. K. Truong and J. M. Jensen and In-Shek Hsu The VLSI Design of an Error-Trellis Syndrome Decoder for Certain Convolutional Codes . . . . . . . . . . 781--789 C. K. Baru and S. Y. W. Su The Architecture of SM3: a Dynamically Partitionable Multicomputer System . . . 790--802 A. Bobbio and K. S. Trivedi An Aggregation Technique for the Transient Analysis of Stiff Markov Chains . . . . . . . . . . . . . . . . . 803--814 R. D. Acosta and J. Kjelstrup and H. C. Torng An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors . . . . . . . 815--828 M. M. Mirsalehi and T. K. Gaylord Comments on ``Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach'' . . . . . . . . . . . . 829--830 R. David Signature Analysis for Multiple-Output Circuits . . . . . . . . . . . . . . . . 830--837 N. F. Maxemchuk and A. T. Dahbura Optimal Diagnosable System Design Using Full-Difference Triangles . . . . . . . 837--839 R. B. Hagmann A Crash Recovery Scheme for a Memory-Resident Database System . . . . 839--843 M. J. Atallah and S. E. Hambrusch Optimal Rotation Problems in Channel Routing . . . . . . . . . . . . . . . . 843--847 Tang Jian An $O(2^{0.304n})$ Algorithm for Solving Maximum Independent Set Problem . . . . 847--851 V. Ramachandran Corrections to ``Algorithmic Aspects of MOS VLSI Switch-Level Simulation with Race Detection'' . . . . . . . . . . . . 851--851 Anonymous Calls for Papers Special Issue on Real-Time Systems . . . . . . . . . . . 852--852 Anonymous Information for Authors . . . . . . . . 852--852 Anonymous IEEE Computer Society Publications . . . 852--852
D. Snyers and A. Thayse Algorithmic State Machine Design and Automatic Theorem Proving: Two Dual Approaches to the Same Activity . . . . 853--861 K. Kinoshita and K. K. Saluja Built-In Testing of Memory Using an On-Chip Compact Testing Scheme . . . . . 862--870 R. M. Yanney and J. P. Hayes Distributed Recovery in Fault-Tolerant Multiprocessor Networks . . . . . . . . 871--879 S. H. Unger and Chung-Jen Tan Clocking Schemes for High-Speed Digital Systems . . . . . . . . . . . . . . . . 880--895 T. Rhyne and N. R. Strader II A Signed Bit-Sequential Multiplier . . . 896--901 B. R. Iyer and L. Donatiello and P. Heidelberger Analysis of Performability for Stochastic Models of Fault-Tolerant Systems . . . . . . . . . . . . . . . . 902--907 J. R. Goodman and H. C. Young Comments on ``A Massive Memory Machine'' 907--910 Woei Lin and Chuan-Lin Wu Reconfiguration Procedures for a Polymorphic and Partitionable Multiprocessor . . . . . . . . . . . . . 910--916 G. E. Bridges and W. Pries and R. D. McLeod and M. Yunik and P. G. Gulak and H. C. Card Dual Systolic Architectures for VLSI Digital Signal Processing Systems . . . 916--923 E. Lodi and L. Pagli A VLSI Solution to the Vertical Segment Visibility Problem . . . . . . . . . . . 923--928 R. N. Gorgui-Naguib and R. A. King Comments on ``Matrix Processors Using $p$-Adic Arithmetic for Exact Linear Computations'' . . . . . . . . . . . . . 928--930 Liang Ye-Wei and Jin Wei Comments on ``Detection of Faults in Programmable Logic Arrays'' . . . . . . 930--931 J. E. Smith Author's Reply . . . . . . . . . . . . . 931--931 Anonymous Information for Authors . . . . . . . . 932--932 Anonymous IEEE Computer Society Publications . . . 932--932 E. Dittert and M. J. O'Donnell Correction to ``Lower Bounds for Sorting with Realistic Instruction Sets'' . . . 932--932 A. A. Nilsson Author's Reply . . . . . . . . . . . . . 932--932
M. A. Breuer and A. A. Ismaeel Roving Emulation as a Fault Detection Mechanism . . . . . . . . . . . . . . . 933--939 K. M. Kavi and B. P. Buckles and U. N. Bhat A Formal Definition of Data Flow Graph Models . . . . . . . . . . . . . . . . . 940--948 V. Carchiolo and A. Faro and O. Mirabella and G. Pappalardo and G. Scollo A LOTOS Specification of the PROWAY Highway Service . . . . . . . . . . . . 949--968 T. F. Chan and Y. Saad Multigrid Algorithms on the Hypercube Multiprocessor . . . . . . . . . . . . . 969--977 M. Y. Kim Synchronized Disk Interleaving . . . . . 978--988 P. J. Varman and I. V. Ramakrishnan Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays . . . . . . . . . . . . . . . . . 989--996 T. Fuja and C. Heegard Row/Column Replacement for the Control of Hard Defects in Semiconductor RAM's 996--1000 B. P. Sinha and B. B. Bhattacharya and S. Ghose and P. K. Srimani A Parallel Algorithm to Compute the Shortest Paths and Diameter of a Graph and Its VLSI Implementation . . . . . . 1000--1004 J. Narasimhan and K. Nakajima An Algorithm for Determining the Fault Diagnosability of a System . . . . . . . 1004--1008 T. K. Truong and J. J. Chang and I. S. Hsu and D. Y. Pei and I. S. Reed Techniques for Computing the Discrete Fourier Transform Using the Quadratic Residue Fermat Number Systems . . . . . 1008--1012 Anonymous Information for Authors . . . . . . . . 1012--1012 Anonymous IEEE Computer Society Publications . . . 1012--1012
W. Pries and A. Thanailakis and H. C. Card Group Properties of Cellular Automata and VLSI Applications . . . . . . . . . 1013--1024 C.-T. A. Lea The Load-Sharing Banyan Network . . . . 1025--1034 M. C. Browne and E. M. Clarke and D. L. Dill and B. Mishra Automatic Verification of Sequential Circuits Using Temporal Logic . . . . . 1035--1044 A. Thomasian and P. F. Bay Analytic Queueing Network Models for Parallel Processing of Task Systems . . 1045--1054 M. S. Krishnan and J. P. Hayes An Array Layout Methodology for VLSI Circuits . . . . . . . . . . . . . . . . 1055--1067 Chuen-Liang Chen and Min-Wen Du Multiple Stuck-Fault Detection and Location in Multivalued Linear Circuits 1068--1071 L. Raschid and T. Fei and H. Lam and S. Y. W. Su A Special-Function Unit for Sorting and Sort-Based Database Operations . . . . . 1071--1077 S. Pramanik Performance Analysis of a Database Filter Search Hardware . . . . . . . . . 1077--1082 Kaiyuan Huang and Tinghuai Chen On the Diagnosis of System Faults with Propagation . . . . . . . . . . . . . . 1082--1086 C. L. Chen Linear Dependencies in Linear Feedback Shift Registers . . . . . . . . . . . . 1086--1088 P. K. Lui and J. C. Muzio Spectral Signature Testing of Multiple Stuck-at Faults in Irredundant Combinational Networks . . . . . . . . . 1088--1092 Anonymous 1986 Index IEEE Transactions on Computers Vol. C-35 . . . . . . . . . . 1093--1102 Anonymous Information for Authors . . . . . . . . 1103--1103 Anonymous IEEE Computer Society Publications . . . 1103--1103
Anonymous Editor's Notice . . . . . . . . . . . . 1--1 Kang G. Shin and P. Ramanathan Clock Synchronization of a Large Multiprocessor System in the Presence of Malicious Faults . . . . . . . . . . . . 2--12 J. H. P. Zurawski and J. B. Gosling Design of a High-Speed Square Root Multiply and Divide Unit . . . . . . . . 13--23 Edward Ashford Lee and David G. Messerschmitt Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing . . . . . . . . . . . . . . . 24--35 Richard J. Zaccone and Jesse L. Barlow Eliminating the Normalization Problem in Digit On-Line Arithmetic . . . . . . . . 36--46 G. Robert Redinbo Fault-Tolerant Decoders for Cyclic Error-Correcting Codes . . . . . . . . . 47--63 Jik H. Chang and Oscar H. Ibarra and Michael A. Palis Parallel Parsing on a One-Way Array of Finite-State Machines . . . . . . . . . 64--75 Mark A. Holliday and Mary K. Vernon Exact Performance Estimates for Multiprocessor Memory and Bus Interference . . . . . . . . . . . . . . 76--85 Eiji Fujiwara and Kohji Matsuoka A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing 86--93 John P. Robinson and Nirmal R. Saxena A Unified View of Test Compression Methods . . . . . . . . . . . . . . . . 94--99 Alan M. Schwartz and Michael C. Loui Dictionary Machines on Cube-Class Networks . . . . . . . . . . . . . . . . 100--105 Zhiyuan Li and Walid Abu-Sufah On Reducing Data Synchronization in Multiprocessed Loops . . . . . . . . . . 105--109 Lindsay Kleeman and Antonio Cantoni On the Unavoidability of Metastable Behavior in Digital Systems . . . . . . 109--112 Howard C. Card and P. Glenn Gulak and Robert D. McLeod and Werner Pries ($\lambda T$) Complexity Measures for VLSI Computations in Constant Chip Area 112--117 Dianne P. O'Leary Systolic Arrays for Matrix Transpose and Other Reorderings . . . . . . . . . . . 117--122 I. F. Akyildiz Exact Product Form Solution for Queueing Networks with Blocking . . . . . . . . . 122--125 Anonymous Calls for Papers . . . . . . . . . . . . 126--126
K. G. Shin and Ming-Syan Chen Performance Analysis of Distributed Routing Strategies Free of Ping-Pong-Type Looping . . . . . . . . . 129--137 I. Chlamtac and O. Ganz Performance Models of Asynchronous Multitrunk HYPERchannel Networks . . . . 138--146 H. S. Hou The Fast Hartley Transform Algorithm . . 147--156 Hung Chi Lai and S. Muroga Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of $n$ Variables . . . . . . . . . . . . . 157--166 P. J. Eberlein On the Schur Decomposition of a Matrix for Parallel Computation . . . . . . . . 167--174 L. D. Coraor and P. T. Hulina and O. A. Morean A General Model for Memory-Based Finite-State Machines . . . . . . . . . 175--184 K. N. Oikonomou Abstractions of Finite-State Machines Optimal with Respect to Single Undetectable Output Faults . . . . . . . 185--200 S. M. Reddy and Dong Sam Ha A New Approach to the Design of Testable PLA's . . . . . . . . . . . . . . . . . 201--211 A. H. Chan Using Decision Trees to Derive the Complement of a Binary Function with Multiple-Valued Inputs . . . . . . . . . 212--214 M. Karpovsky Multilevel Logical Networks . . . . . . 215--226 K. Nakamura Inverter-Minimum Networks . . . . . . . 226--230 R. Hockney Algorithmic Phase Diagrams . . . . . . . 231--233 H. A. G. Wijshoff and J. Van Leeuwen On Linear Skewing Schemes and $d$-Ordered Vectors . . . . . . . . . . 233--239 Y. S. Abu-Mostafa On the Time-Bandwidth Proof in VLSI Complexity . . . . . . . . . . . . . . . 239--240 A. A. Bertossi and M. A. Bonuccelli A VLSI Implementation of the Simplex Algorithm . . . . . . . . . . . . . . . 241--247 H. Fleisher and M. Tavel and J. Yeager A Computer Algorithm for Minimizing Reed--Muller Canonical Forms . . . . . . 247--250 Wenlong Zang and J. K. Wolf Rate $1/2$ and $2/3$ Majority Logic Decodable Binary Burst Error-Correcting Codes . . . . . . . . . . . . . . . . . 250--252 C. K. Chin and E. J. McCluskey Test Length for Pseudorandom Testing . . 252--256 Anonymous Information for Authors . . . . . . . . 256--256 Anonymous IEEE Computer Society Publications . . . 256--256 D. J. Taylor and C.-J. H. Seger Correction to ``Robust Storage Structures for Crash Recovery'' . . . . 256--256
G. S. Stiles and Dong-Lih Denq A Quantitative Comparison of the Performance of Three Discrete Distributed Associative Memory Models 257--263 M. A. Schuette and J. P. Shen Processor Control Flow Monitoring Using Signatured Instruction Streams . . . . . 264--276 R. B. Cutler and S. Muroga Derivation of Minimal Sums for Completely Specified Functions . . . . . 277--292 D. H. Bailey Vector Computer Memory Bank Contention 293--298 L. G. Birta and O. Abou-Rabia Parallel Block Predictor--Corrector Methods for ODE's . . . . . . . . . . . 299--311 D. H.-C. Du and Lee-Chin Hsu Liu Heuristic Algorithms for Single Row Routing . . . . . . . . . . . . . . . . 312--320 Ying-Fung Wu and P. Widmayer and M. D. F. Schlag and C. K. Wong Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles . . . . . . . . . 321--331 K. D. Wagner and C. K. Chin and E. J. McCluskey Pseudorandom Testing . . . . . . . . . . 332--343 I. Koren and D. K. Pradhan Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems 344--355 Y. S. Kuo Generating Essential Primes for a Boolean Function with Multiple-Valued Inputs . . . . . . . . . . . . . . . . . 356--359 A. G. Greenberg and U. Manber A Probabilistic Pipeline Algorithm for $K$ Selection on the Tree Machine . . . 359--362 B. Mossberg Vectorization of the Calculation of a Moving Sum . . . . . . . . . . . . . . . 362--365 P. Mazumder Evaluation of On-Chip Static Interconnection Networks . . . . . . . . 365--369 R. Treuer and V. K. Agarwal and H. Fujiwara A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead . . . . . . . . . . . . . . . . 369--373 A. T. Dahbura and K. K. Sabnani and L. L. King The Comparison Approach to Multiprocessor Fault Diagnosis . . . . . 373--378 Che-Liang Yang and G. M. Masson A New Measure for Hybrid Fault Diagnosability . . . . . . . . . . . . . 378--383 F. K. Hwang Comments on ``Reliable Loop Topologies for Large Local Computer Networks'' . . 383--384 Anonymous Information for Authors . . . . . . . . 384--384 Anonymous IEEE Computer Society Publications . . . 384--384
J. A. Stankovic Introduction --- Parallel and Distributed Computing . . . . . . . . . 385--386 Anonymous List of Referees . . . . . . . . . . . . 387--387 Pen-Chung Yew and Nian-Feng Tzeng and D. H. Lawrie Distributing Hot-Spot Addressing in Large-Scale Multiprocessors . . . . . . 388--395 R. P. Bianchini, Jr. and J. P. Shen Interprocessor Traffic Scheduling Algorithm for Multiple-Processor Networks . . . . . . . . . . . . . . . . 396--409 C. D. Polychoronopoulos and U. Banerjee Processor Allocation for Horizontal and Vertical Parallelism and Related Speedup Bounds . . . . . . . . . . . . . . . . . 410--420 Z. Cvetanovic The Effects of Problem Partitioning, Allocation, and Granularity on the Performance of Multiple-Processor Systems . . . . . . . . . . . . . . . . 421--432 Soo-Young Lee and J. K. Aggarwal A Mapping Strategy for Parallel Processing . . . . . . . . . . . . . . . 433--442 M. Herlihy Extending Multiversion Time-Stamping Protocols to Exploit Type Information 443--448 R. A. Volz and T. N. Mudge Timing Issues in the Distributed Execution of Ada Programs . . . . . . . 449--459 K. A. Doshi and P. J. Varman Optimal Graph Algorithms on a Fixed-Size Linear Array . . . . . . . . . . . . . . 460--470 T. J. Leblanc and J. M. Mellor-Crummey Debugging Parallel Programs with Instant Replay . . . . . . . . . . . . . . . . . 471--482 A. E. Kamal Star Local Area Networks: a Performance Study . . . . . . . . . . . . . . . . . 483--499 D. Peng and K. G. Shin Modeling of Concurrent Task Execution in a Distributed System for Real-Time Control . . . . . . . . . . . . . . . . 500--516 Anonymous Information for Authors . . . . . . . . 516--516 Anonymous IEEE Computer Society Publications . . . 516--516
H. R. Kanakia and F. A. Tobagi On Distributed Computations with Limited Resources . . . . . . . . . . . . . . . 517--528 R. Chillarege and R. K. Iyer Measurement-Based Analysis of Error Latency . . . . . . . . . . . . . . . . 529--537 A. K. Somani and V. K. Agarwal and D. Avis A Generalized Theory for System Level Diagnosis . . . . . . . . . . . . . . . 538--546 W. J. Dally and C. L. Seitz Deadlock-Free Message Routing in Multiprocessor Interconnection Networks 547--553 P. J. B. King and I. Mitrani Modeling a Slotted Ring Local Area Network . . . . . . . . . . . . . . . . 554--561 Y. I. Gold and W. R. Franta A Scheduling-Function-Based Distributed Access Protocol that Uses CDM to Relay Control Information in a Network with Hidden Nodes . . . . . . . . . . . . . . 562--569 Marsha J. Berger and Shahid H. Bokhari A Partitioning Strategy for Non-Uniform Problems on Multiprocessors . . . . . . 570--580 A. Norton and A. J. Silberger Parallelization and Performance Analysis of the Cooley--Tukey FFT Algorithm for Shared-Memory Architectures . . . . . . 581--591 J. Savir and W. H. McAnney and S. R. Vecchio Fault Propagation Through Embedded Multiport Memories . . . . . . . . . . . 592--602 Sun-Yuan Kung and Sheng-Chun Lo and P. S. Lewis Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems . . . . . . . . . . . . . . . . 603--614 L. Melkemi and M. Tchuente Complexity of Matrix Product on a Class of Orthogonally Connected Systolic Arrays . . . . . . . . . . . . . . . . . 615--619 A. Sengupta and A. Sen and S. Bandyopadhyay On an Optimally Fault-Tolerant Multiprocessor Network Architecture . . 619--623 Franti\vsek Kremla General Criterion for Essential Nonfault Locatability of Logical Functions . . . 623--629 S. J. Piestrak Design of Fast Self-Testing Checkers for a Class of Berger Codes . . . . . . . . 629--634 A. Mukhopadhyay A Solution to the Polynomial Hensel Code Conversion Problem . . . . . . . . . . . 634--637 Chun-Fu Huang and Wen-Tsuen Chen Fault-Tolerant Single-Stage Interconnection Networks . . . . . . . . 637--640 C. N. Purdy and G. B. Purdy Integer Division in Linear Time with Bounded Fan-In . . . . . . . . . . . . . 640--644 Anonymous Information for Authors . . . . . . . . 644--644 Anonymous IEEE Computer Society Publications . . . 644--644
Anonymous Editor's Notice . . . . . . . . . . . . 645--646 Anonymous IEEE Transactions on Computers Referee List for 1986--1987 . . . . . . . . . . 646--649 T. Baba and S. B. Yao and A. R. Hevner Design of a Functionally Distributed, Multiprocessor Database Machine Using Data Flow Analysis . . . . . . . . . . . 650--666 W. W. Chu and L. M.-T. Lan Task Allocation and Precedence Relations for Distributed Real-Time Systems . . . 667--679 S. Yalamanchili and J. K. Aggarwal A Characterization and Analysis of Parallel Processor Interconnection Networks . . . . . . . . . . . . . . . . 680--691 T. K. Apostolopoulos and E. D. Sykas and E. N. Protonotarios Analysis of a New Retransmission Control Algorithm for Slotted CSMA/CD LAN's . . 692--701 M. A. Fiol and J. L. A. Yebra and I. Alegre and M. Valero Discrete Optimization Problem in Local Networks and Data Alignment . . . . . . 702--713 V. Milutinovic and N. Lopez-Benitez A GaAs-Based Microprocessor Architecture for Real-Time Applications . . . . . . . 714--727 I. Chlamtac and S. S. Pinter Distributed Nodes Organization Algorithm for Channel Access in a Multihop Dynamic Radio Network . . . . . . . . . . . . . 728--737 A. Goyal and A. N. Tantawi Evaluation of Performability for Degradable Computer Systems . . . . . . 738--744 W. K. Luk and P. Sipala and C. K. Wong Minimum-Area Wiring for Slicing Structures . . . . . . . . . . . . . . . 745--760 Yu-Cheng Liu and Chi-Jiunn Jou Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems . . . . . . . . . . . . . . . . 761--764 J. J. Thomas and S. R. Parker Implementing Exact Calculations in Hardware . . . . . . . . . . . . . . . . 764--768 Kyungsook Yoon Lee A New Benes Network Control Algorithm 768--772 Anonymous Information for Authors . . . . . . . . 772--772 Anonymous IEEE Computer Society Publications . . . 772--772
B. Gavish Optimization Models for Configuring Distributed Computer Systems . . . . . . 773--793 A. Seznec A New Interconnection Network for SIMD Computers: The Sigma Network . . . . . . 794--801 A. Y. Oruc and M. Y. Oruc Programming Cellular Permutation Networks Through Decomposition of Symmetric Groups . . . . . . . . . . . . 802--809 T. H. Szymanski and V. C. Hamacher On the Permutation Capability of Multistage Interconnection Networks . . 810--822 S. P. Kartashev and S. I. Kartashev Analysis and Synthesis of Dynamic Multicomputer Networks that Reconfigure into Rings, Trees, and Stars . . . . . . 823--844 D. A. Reed and L. M. Adams and M. L. Patrick Stencils and Problem Partitionings: Their Influence on the Performance of Multiple Processor Systems . . . . . . . 845--858 P. G. Emma and E. S. Davidson Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance . . . . . . . . . . 859--875 J. H. Kim and W. E. Alexander A Multiprocessor Architecture for Two-Dimensional Digital Filters . . . . 876--884 S. B. Akers and B. Krishnamurthy On Group Graphs and Their Fault Tolerance . . . . . . . . . . . . . . . 885--888 K. Fukunaga and S. Yamada and T. Kasai Assignment of Job Modules onto Array Processors . . . . . . . . . . . . . . . 888--891 Wu-Tung Cheng and J. H. Patel A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders . . . . 891--895 M. D. Ercegovac and T. Lang On-the-fly conversion of redundant into conventional representations . . . . . . 895--897 Anonymous Call for Papers Special Issue on Architectural Support for Programming Languages and Operating Systems . . . . 898--898 Anonymous Information for Authors . . . . . . . . 899--899 Anonymous IEEE Copyright Form . . . . . . . . . . 899--899 Anonymous IEEE Computer Society Publications . . . 899--899
Kang G. Shin Introduction to the Special Issue on Real-Time Systems . . . . . . . . . . . 901--902 Anonymous Reviewers Special Issue on Real-Time Systems August 1987 . . . . . . . . . . 903--903 Karsten Schwan and Prabha Gopinath and Win Bo CHAOS-Kernel Support for Objects in the Real-Time Domain . . . . . . . . . . . . 904--916 Michael F. Coulas and Glenn H. MacEwen and Genevieve Marquis RNet: a Hard Real-Time Distributed Programming System . . . . . . . . . . . 917--932 Hermann Kopetz and Wilhelm Ochsenreiter Clock Synchronization in Distributed Real-Time Systems . . . . . . . . . . . 933--940 Insup Lee and Susan B. Davidson Adding Time to Synchronous Process Communications . . . . . . . . . . . . . 941--948 Wei Zhao and Krithi Ramamritham and John A. Stankovic Preemptive Scheduling Under Time and Resource Constraints . . . . . . . . . . 949--960 Farnam Jahanian and Aloysius K.-L. Mok A Graph-Theoretic Approach for Timing Analysis and its Implementation . . . . 961--975 Yann-Hang Lee and Philip S. Yu and Balakrishna R. Iyer Progressive Transaction Recovery in Distributed DB/DC Systems . . . . . . . 976--987 Richard A. Volz and Trevor N. Mudge Instruction Level Timing Mechanisms for Accurate Real-Time Task Scheduling . . . 988--993 James F. Kurose and Renu Chipalkatti Load Sharing in Soft Real-Time Distributed Computer Systems . . . . . . 993--1000 Frederic L. Swern and Salvatore J. Bavuso and Anna L. Martensen and Paul S. Miner The Effects of Latent Faults on Highly Reliable Computer Systems . . . . . . . 1000--1005 Anonymous Call for Papers . . . . . . . . . . . . 1006--1006
Dan Gordon Efficient Embeddings of Binary Trees in VLSI Arrays . . . . . . . . . . . . . . 1009--1018 Michael Granski and Israel Koren and Gabriel M. Silberman The Effect of Operation Scheduling on the Performance of a Data Flow Computer 1019--1029 C. M. Krishna and Kang G. Shin and Inderpal S. Bhandari Processor Tradeoffs in Distributed Real-Time Systems . . . . . . . . . . . 1030--1040 Victor O. K. Li Performance Models of Timestamp-Ordering Concurrency Control Algorithms in Distributed Databases . . . . . . . . . 1041--1051 Menachem Berg and Israel Koren On Switching Policies for Modular Redundancy Fault-Tolerant Computing Systems . . . . . . . . . . . . . . . . 1052--1062 Alan Jay Smith Line (Block) Size Choice for CPU Cache Memories . . . . . . . . . . . . . . . . 1063--1075 Hidenori Umeno and Shunji Tanaka New Methods for Realizing Plural Near-Native Performance Virtual Machines 1076--1087 Eberhard Lange Implementation and Test of the ACRITH Facility in a System/370 . . . . . . . . 1088--1096 M. Serra and J. C. Muzio Testing Programmable Logic Arrays by Sum of Syndromes . . . . . . . . . . . . . . 1097--1101 Rami G. Melhem A Study of Data Interlock in Computational Networks for Sparse Matrix Multiplication . . . . . . . . . . . . . 1101--1107 M. M. Srinivasan Successively Improving Bounds on Performance Measures for Single Class Product Form Queueing Networks . . . . . 1107--1112 Balakrishnan Krishnamurthy Constructing Test Cases for Partitioning Heuristics . . . . . . . . . . . . . . . 1112--1114 Jan Gecsei and Eduard Cerny Self-Adjusting Networks for VLSI Simulation . . . . . . . . . . . . . . . 1114--1120 Takashi Nanya and Toshiaki Kawamura A Note on Strongly Fault-Secure Sequential Circuits . . . . . . . . . . 1121--1123 R. I. Damper and N. Burgess MOS Test Pattern Generation Using Path Algebras . . . . . . . . . . . . . . . . 1123--1128 Steven S. Liu and Q. C. Chow Performance Analysis of a Multiprocessor-Based Packet Switch in Networks with Link-Level Sliding-Window Flow Control . . . . . . . . . . . . . . 1128--1132 Seiichi Nishihara and Hiroji Nishino Binary Search Revisited: Another Advantage of Fibonacci Search . . . . . 1132--1135 Hsieh S. Hou Correction to ``The Fast Hartley Transform Algorithm'' . . . . . . . . . 1135--1136
A. T. Fam Optimal Partitioning and Redundancy Removal in Computing Partial Sums . . . 1137--1143 A. Guyot and B. Hochet and J.-M. Muller A Way to Build Efficient Carry-Skip Adders . . . . . . . . . . . . . . . . . 1144--1152 C. T. Yu and Keh-Chang Guh and Weining Zhang and M. Templeton and D. Brill and A. L. P. Chen Algorithms to Process Distributed Queries in Fast Local Networks . . . . . 1153--1164 H. Okano and H. Imai A Construction Method of High-Speed Decoders Using ROM's for Bose--Chaudhuri--Hocquenghem and Reed--Solomon Codes . . . . . . . . . . 1165--1171 M. B. Lowrie and W. K. Fuchs Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance . . . . 1172--1182 K. M. Nichols and D. G. Messerschmitt Traffic-Specific Interconnection Networks for Multicomputers . . . . . . 1183--1196 D. Barbara and H. Garcia-Molina The Reliability of Voting Mechanisms . . 1197--1208 I. Chlamtac and S. Kutten Tree-Based Broadcasting in Multihop Radio Networks . . . . . . . . . . . . . 1209--1223 S. Hariri and C. S. Raghavendra SYREL: a Symbolic Reliability Algorithm Based on Path and Cutset Methods . . . . 1224--1232 B. Parhami On the Complexity of Table Lookup for Iterative Division . . . . . . . . . . . 1233--1236 G. R. Redinbo Finite Field Fault-Tolerant Digital Filtering Architectures . . . . . . . . 1236--1242 I-Chen wu A Fast $1$-D Serial-Parallel Systolic Multiplier . . . . . . . . . . . . . . . 1243--1247 G. Markowsky Bounding Signal Probabilities in Combinational Circuits . . . . . . . . . 1247--1251 D. M. Chapiro Reliable High-Speed Arbitration and Synchronization . . . . . . . . . . . . 1251--1255 H. C. Shyu and T. K. Truong and I. S. Reed A Complex Integer Multiplier Using the Quadratic-Polynomial Residue Number System with Numbers of Form $22n + 1$ 1255--1258 B. Awerbuch and Y. Shiloach New Connectivity and MSF Algorithms for Shuffle-Exchange Network and PRAM . . . 1258--1263 Anonymous THE Computer Society . . . . . . . . . . 1264--1264 Anonymous Information for Authors . . . . . . . . 1264--1264 Anonymous IEEE Computer Society Publications . . . 1264--1264
Izidor Gertner and Moshe Shamash VLSI Architectures for Multidimensional Fourier Transform Processing . . . . . . 1265--1274 Edmund H. Durfee and Victor R. Lesser and Daniel D. Corkill Coherent Cooperation Among Communicating Problem Solvers . . . . . . . . . . . . 1275--1291 Stephen F. Lundstrom Applications Considerations in the System Design of Highly Concurrent Multiprocessors . . . . . . . . . . . . 1292--1309 Naofumi Takagi and Shuzo Yajima On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic . . 1310--1317 Janusz A. Brzozowski and Carl-Johan Seger A Characterization of Ternary Simulation of Gate Networks . . . . . . . . . . . . 1318--1327 Kang G. Shin and Tein-Hsiang Lin and Yann-Hang Lee Optimal Checkpointing of Real-Time Tasks 1328--1341 Robert Michael Owens and Mary Jane Irwin The Arithmetic Cube . . . . . . . . . . 1342--1348 Bernard Chazelle and Herbert Edelsbrunner An Improved Algorithm for Constructing $k$th-Order Voronoi Diagrams . . . . . . 1349--1354 D. P. O'Leary and G. W. Stewart From Determinacy to Systaltic Arrays . . 1355--1359 Robert H. Deng and Daniel J. Costello Decoding of DBEC--TBED Reed--Solomon Codes . . . . . . . . . . . . . . . . . 1359--1363 Hao-Yung Lo and Jau-Ling Chen A Hardwired Generalized Algorithm for Generating the Logarithm Base-$k$ by Iteration . . . . . . . . . . . . . . . 1363--1367 Selim G. Akl and Nicola Santoro Optimal Parallel Merging and Sorting Without Memory Conflicts . . . . . . . . 1367--1369 Che-Liang Yang and Gerald M. Masson A Generalization of Hybrid Fault Diagnosability . . . . . . . . . . . . . 1369--1374 R. Conterno and R. Melen An Analytical Model for a Class of Processor-Memory Interconnection Networks . . . . . . . . . . . . . . . . 1374--1378 S. H. Hosseini and J. G. Kuhl and S. M. Reddy Distributed Fault-Tolerance of Tree Structures . . . . . . . . . . . . . . . 1378--1382 M. Ilyas and H. T. Mouftah End-to-End Flow Control in Computer Networks with Noisy Channels and Quasi-Cut-Through Switching . . . . . . 1382--1386 Chwan-Chia Wu Time Redundant Fault-Location in Bit-Sliced ALU's . . . . . . . . . . . . 1387--1389 Takashi Nanya and Toshiaki Kawamura On Error Indication for Totally Self-Checking Systems . . . . . . . . . 1389--1392
H. C. Torng Introduction to the Special Issue on Supercomputing . . . . . . . . . . . . . 1393--1394 Anonymous Referee List . . . . . . . . . . . . . . 1395--1395 Ming-Syan Chen and Kang G. Shin Processor Allocation in an $N$-Cube Multiprocessor Using Gray Codes . . . . 1396--1407 Ponnuswamy Sadayappan and Fikret Ercal Nearest-Neighbor Mapping of Finite Element Graphs onto Processor Meshes . . 1408--1424 Constantine D. Polychronopoulos and David J. Kuck Guided Self-Scheduling: a Practical Scheduling Scheme for Parallel Supercomputers . . . . . . . . . . . . . 1425--1439 David T. Harper and J. Robert Jump Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme 1440--1449 Kai Hwang and Joydeep Ghosh Hypernet: a Communication-Efficient Architecture for Constructing Massively Parallel Computers . . . . . . . . . . . 1450--1466 Stanley Y. W. Su and Arun K. Thakore Matrix Operations on a Multicomputer System with Switchable Main Memory Modules and Dynamic Control . . . . . . 1467--1484 Samuel P. Midkiff and David A. Padua Compiler Algorithms for Synchronization 1485--1495 Wen-Mei W. Hwu and Yale N. Patt Checkpoint Repair for High-Performance Out-of-Order Execution Machines . . . . 1496--1514 Richard Buehrer and Kattamuri Ekanadham Incorporating Data Flow Ideas into von Neumann Processors for Parallel Execution . . . . . . . . . . . . . . . 1515--1522 Marco Annaratone and Emmanuel Arnould and Thomas Gross and H. T. Kung and Monica Lam and Onat Menzilcioglu and Jon A. Webb The Warp Computer: Architecture, Implementation, and Performance . . . . 1523--1538 Anonymous 1987 Index IEEE Transactions on Computers Vol. C-36 . . . . . . . . . . 1539--1550 Anonymous Membership Application . . . . . . . . . 1551--1551
B. J. Oommen and D. C. Y. Ma Deterministic learning automata solutions to the equipartitioning problem . . . . . . . . . . . . . . . . 2--13 T. Nanya and T. Kawamura Error secure/propagating concept and its application to the design of strongly fault-secure processors . . . . . . . . 14--24 A. Goyal and A. N. Tantawi A measure of guaranteed availability and its numerical evaluation . . . . . . . . 25--32 K. Hwang and Z. Xu Multipipeline networking for compound vector processing . . . . . . . . . . . 33--47 S. H. Bokhari Partitioning problems in parallel, pipeline, and distributed computing . . 48--57 M. Dubois Throughput analysis of cache-based multiprocessors with multiple buses . . 58--70 S. E. Kreutzer and S. L. Hakimi Distributed diagnosis and the system user . . . . . . . . . . . . . . . . . . 71--78 G. Thuau and G. Saucier Optimized layout of MOS cells . . . . . 79--87 J. C. Harden and N. R. Strader II Architectural yield optimization for WSI 88--110 E. Cerny and J. Gecesi Functional description of connector-switch-attenuator networks . . 111--114 M. Blaum and R. Goodman and R. McEliece The reliability of single-error protected computer memories . . . . . . 114--119 Y. J. Kang and J. H. Herzog and J. Spragins FISHNET: a distributed architecture for high-performance local computer networks 119--123 W. K. Stewart and S. A. Ward A solution to a special case of the synchronization problem . . . . . . . . 123--125
J. G. Nash and S. Hansen Modified Faddeeva algorithm for concurrent execution of linear algebraic operations . . . . . . . . . . . . . . . 129--137 K. Steiglitz and I. Kamal and A. Watson Embedding computation in one-dimensional automata by phase coding solitons . . . 138--145 L. Sha and J. P. Lehoczky and E. D. Jensen Modular concurrency control and failure recovery . . . . . . . . . . . . . . . . 146--159 A. Mahmood and E. J. McCluskey Concurrent error detection using watchdog processors --- a survey . . . . 160--174 C.-L. Yang and G. M. Masson Hybrid fault diagnosability with unreliable communication links . . . . . 175--181 R. Rom and N. Shacham A reconfiguration algorithm for a double-loop token ring local area network . . . . . . . . . . . . . . . . 182--189 F. J. Taylor and R. Gill and J. Joseph and J. Radke A 20 Bit Logarithmic Number System Processor . . . . . . . . . . . . . . . 190--200 W. Lin and C.-L. Wu A distributed resource management mechanism for a partitionable multiprocessor system . . . . . . . . . 201--210 D. C. Fisher Your favorite parallel algorithms might not be as fast as you think . . . . . . 211--213 M. H. Woodbury and K. G. Shin Performance modeling and measurements of real time multiprocessors with time-shared buses . . . . . . . . . . . 214--224 C. L. Chen Exhaustive test pattern generation using cyclic codes . . . . . . . . . . . . . . 225--228 C.-H. Tung and J. P. Robinson A fast algorithm for optimum syndrome space compression . . . . . . . . . . . 228--232 D. P. Agrawal and S.-C. Kim and N. K. Swain Analysis and design of nonequivalent multistage interconnection networks . . 232--237 K. Walczak Deductive fault simulation for sequential module circuits . . . . . . . 237--239 K. V. S. Ramarao Distributed sorting on local area networks . . . . . . . . . . . . . . . . 239--243 B. P. Miller DPM: a measurement system for distributed programs . . . . . . . . . . 243--248 S. H. Hosseini and J. G. Kuhl and S. M. Reddy On self-fault diagnosis of the distributed systems . . . . . . . . . . 248--251 S.-T. Huang and S. K. Tripathi Self-routing technique in perfect-shuffle networks using control tags . . . . . . . . . . . . . . . . . . 251--256
N. Gaitanis The design of TSC error C/D circuits for SEC/DED codes . . . . . . . . . . . . . 258--265 T. K. Truong and I. S. Reed and I.-S. Hsu and H.-C. Shyu and H. M. Shao A pipeline design of a fast prime factor DFT on a finite field . . . . . . . . . 266--273 S. Nakamura and K.-Y. Chu A single chip parallel multiplier by MOS technology . . . . . . . . . . . . . . . 274--282 B. C. McKinney and F. El Guibaly A multiple-access pipeline architecture for digital signal processing . . . . . 283--290 J. Savir and W. H. McAnney Random pattern testability of delay faults . . . . . . . . . . . . . . . . . 291--300 A. M. Paschalis and D. Nikolos and C. Halatsis Efficient modular design of TSC checkers for $m$-out-of-$2 m$ codes . . . . . . . 301--309 D. M. Dias and B. R. Iyer and P. S. Yu Tradeoffs between coupling small and large processors for transaction processing . . . . . . . . . . . . . . . 310--320 F. W. Burton Storage management in virtual tree machines . . . . . . . . . . . . . . . . 321--328 M. C. Chen The generation of a class of multipliers: synthesizing highly parallel algorithms in VLSI . . . . . . 329--338 P. S. Yu and C. M. Krishna and Y.-H. Lee Optimal design and sequential analysis of VLSI testing strategy . . . . . . . . 339--347 S. Thanawastien and P. K. Srimani The universality of a class of modified single-stage shuffle/exchange networks 348--352 C. S. Raghavendra and V. K. P. Kumar and S. Hariri Reliability analysis in distributed systems . . . . . . . . . . . . . . . . 352--358 P. Agrawal Fault tolerance in multiprocessor systems without dedicated redundancy . . 358--362 E. Regener A transition sequence generator for RAM fault detection . . . . . . . . . . . . 362--368 D.-L. Lee and W. A. Davis An $O(n + k)$ algorithm for ordered retrieval from an associative memory . . 368--371 U. Garg and Y.-P. Huang Decomposing banyan networks for performance analysis . . . . . . . . . . 371--376 S. A. Koubias and G. D. Papadopoulos Further results on the performance evaluation of the split channel reservation multiple access protocol ATP-2 for local area networks . . . . . 376--383
G. F. Sullivan A $O(t^3 + |E|)$ fault identification algorithm for diagnosable systems . . . 388--397 R. M. Keichafer and C. J. Walter and A. M. Finn and P. M. Thambidurai The MAFT architecture for distributed fault tolerance . . . . . . . . . . . . 398--404 R. M. Smith and K. S. Trivedi and A. V. Ramesh Performability analysis: measures, an algorithm, and a case study . . . . . . 406--417 P. E. Ammann and J. C. Knight Data diversity: an approach to software fault tolerance . . . . . . . . . . . . 418--425 N. K. Jha Multiple stuck-open fault detection in CMOS logic circuits . . . . . . . . . . 426--432 D. J. Lin and B. Bose Theory and design of $t$-error correcting and $d$ ($d > t$)-unidirectional error detecting ($t$-EC $d$-UED) codes . . . . . . . . . 433--439 N. Vasanthavada and P. N. Marinos Synchronization of fault-tolerant clocks in the presence of malicious failures 440--448 H. H. Abu-Amara Fault-tolerant distributed algorithm for election in complete networks . . . . . 449--453 M. Blaum Systematic unidirectional burst detecting codes . . . . . . . . . . . . 453--457 N.-F. Tzeng and P.-C. Yew and C.-Q. Zhu Realizing fault-tolerant interconnection networks via chaining . . . . . . . . . 458--462 M. C. Howells and V. K. Agarwal A reconfiguration scheme for yield enhancement of large area binary tree architectures . . . . . . . . . . . . . 463--468 Dong Sam Ha and S. M. Reddy On the design of pseudoexhaustive testable PLAs . . . . . . . . . . . . . 468--472 F. J. Meyer Flip-trees: fault-tolerant graphs with wide containers . . . . . . . . . . . . 472--478 M. C. Hseuh and R. K. Iyer and K. S. Trivedi Performance modeling based on real data: a case study . . . . . . . . . . . . . . 478--484 J. M. Char and V. Cherkassy and H. Wechsler and G. L. Zimmerman Distributed and fault-tolerant computation for retrieval tasks using distributed associative memories . . . . 484--490 P. L'Ecuyer and J. Malenfant Computing optimal checkpointing strategies for rollback and recovery systems . . . . . . . . . . . . . . . . 491--496 P. Golan and O. Novak and J. Hlavicka Pseudoexhaustive test pattern generator with enhanced fault coverage . . . . . . 496--500 J. F. Meyer and L. Wei Influence of workload on error recovery in random access memories . . . . . . . 500--507
A. Padegs and B. B. Moore and R. M. Smith and W. Buchholz The IBM System/370 vector architecture: design considerations . . . . . . . . . 509--520 James B. Sinclair Optimal Assignments in Broadcast Networks . . . . . . . . . . . . . . . . 521--531 G. Chiola and M. A. Marsan and G. Balbo Product-form solution techniques for the performance analysis of multiple-bus multiprocessor systems with nonuniform memory references . . . . . . . . . . . 532--540 B. R. Badrinath and K. Ramamritham Synchronizing transactions on objects 541--547 J.-Y. Jou and J. A. Abraham Fault-tolerant FFT networks . . . . . . 548--561 J. E. Smith and A. R. Pleszkun Implementing precise interrupts in pipelined processors . . . . . . . . . . 562--573 K. Y. Lee and D. Lee On the augmented data manipulator network in SIMD environments . . . . . . 574--584 A. Fukuda Equilibrium point analysis of memory interference in multiprocessor systems 585--593 M. R. Fellows and M. A. Langston Processor utilization in a linearly connected parallel processing system . . 594--603 H. P. Katseff Incomplete hypercubes . . . . . . . . . 604--608 J. W. Watterson and J. J. Hallenbeck Modulo $3$ residue checker: new results on performance and cost . . . . . . . . 608--612 S. C. Kothari and G. M. Prabhu and R. Roberts The Kappa network with fault-tolerant destination tag algorithm . . . . . . . 612--617 Y.-H. Choi and M. Malek A fault-tolerant FFT processor . . . . . 617--621 Y.-H. Choi and M. Malek A fault-tolerant systolic sorter . . . . 621--624 K. C. Chang and H. C. Du Layer assignment problem for three-layer routing . . . . . . . . . . . . . . . . 625--632 P. Banerjee The cubical ring connected cycles: a fault tolerant parallel computation network . . . . . . . . . . . . . . . . 632--636
W. S. Wong and R. J. T. Morris Benchmark synthesis using the LRU cache hit function . . . . . . . . . . . . . . 637--645 P. M. Lenders A generalized message-passing mechanism for communicating sequential processes 646--651 L. A. Glasser and C. A. Zukowski Continuous models for communication density constraints on multiprocessor performance . . . . . . . . . . . . . . 652--656 P. R. Capello and W. L. Miranker Systolic super summation . . . . . . . . 657--677 N. Park and A. C. Parker Theory of clocking for maximum execution overlap of high-speed digital systems 678--690 I. Lee and D. Smitley A synthesis algorithm for reconfigurable interconnection networks . . . . . . . . 691--699 K. So and R. N. Rechtschaffen Cache operations by MRU change . . . . . 700--709 D. K. Probst and H. F. Li Abstract specification of synchronous data types for VLSI and proving the correctness of systolic network implementations . . . . . . . . . . . . 710--720 H. C. Du and O. H. Ibarra and J. F. Naveda On two-dimensional via assignment for single-row routing . . . . . . . . . . . 721--727 J. H. Chang and O. H. Ibarra and M. J. Chung and K. K. Rao Systolic tree implementation of data structures . . . . . . . . . . . . . . . 727--735 I. S. Hsu and T. K. Truong and L. J. Deutsch and I. S. Reed A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases . . . . . . . 735--739 R. Nelson and A. N. Tantawi Approximate analysis of fork/join synchronization in parallel queues . . . 739--743 M. I. Irshid A simple method for determining Hadamard sequency vectors . . . . . . . . . . . . 743--745 I. Jansch and B. Courtois Definition and design of strongly language disjoint checkers . . . . . . . 745--748 B. B. Zhou A new bit-serial systolic multiplier over $\mathrm{GF}(2^m)$ . . . . . . . . 749--751 M. Nicolaidis and B. Courtois Strongly code disjoint checkers . . . . 751--756 V. Pitchumani and S. S. Soman Functional test generation based on unate function theory . . . . . . . . . 756--760 L. A. Ferrari and P. V. Sankar Minimum complexity FIR filters and sparse systolic arrays . . . . . . . . . 760--764
M. Beck and D. Bitton and W. K. Wilkinson Sorting large files on a backend multiprocessor . . . . . . . . . . . . . 769--778 B. A. Sanders An asynchronous, distributed flow control algorithm for rate allocation in computer networks . . . . . . . . . . . 779--787 I. Gazit and M. Malek Fault tolerance capabilities in multistage network-based multicomputer systems . . . . . . . . . . . . . . . . 788--798 Y. Yamamoto and M. Mukaidono Meaningful special classes of ternary logic functions-regular ternary logic functions and ternary majority functions 799--806 D. Nikolos and A. M. Paschalis and G. Philokyprou Efficient design of totally self-checking checkers for all low-cost arithmetic codes . . . . . . . . . . . . 807--814 C. Lin and D. C. Marinescu Stochastic high-level Petri nets and applications . . . . . . . . . . . . . . 815--825 W.-Y. Cheng and J. W. S. Liu Performance of ARQ schemes on token ring networks . . . . . . . . . . . . . . . . 826--834 C. Berthet and E. Cerny An algebraic model for asynchronous circuits verification . . . . . . . . . 835--847 Q. Yang and S. G. Zaky Communication performance in multiple-bus systems . . . . . . . . . . 848--853 C. R. Bisbee and V. P. Nelson Failure dependent bandwidth in shuffle-exchange networks . . . . . . . 853--858 Thanos Stouraitis and Fred J. Taylor Floating-point to logarithmic encoder error analysis . . . . . . . . . . . . . 858--863 Y. Min and J. Li Strongly fault secure PLAs and totally self-checking checkers . . . . . . . . . 863--867 Y. Saad and M. H. Schultz Topological Properties of Hypercubes . . 867--872 S. J. Upadhyaya and K. K. Saluja An experimental study to determine task size for rollback recovery systems . . . 872--877 A. T. Fam Efficient complex matrix multiplication 877--879 D. L. Tao and C. R. P. Hartmann and P. K. Lala An efficient class of unidirectional error detecting/correcting codes . . . . 879--882 M. Wainer Generating fractal-like surfaces on general purpose mesh-connected computers 882--886 R. J. Cosentino Fault tolerance in a systolic residue arithmetic processor array . . . . . . . 886--890
R. Rashid and A. Tevanian, Jr. and M. Young and D. Golub and R. Baron and D. Black and W. J. Bolosky and J. Chew Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures . . . . . . 896--908 C. P. Thacker and L. C. Stewart and E. H. Satterthwaite, Jr. Firefly: a multiprocessor workstation 909--920 S. Ahuja and N. J. Carriero and D. H. Gelernter and V. Krishnaswamy Matching language and hardware for parallel computation in the Linda Machine . . . . . . . . . . . . . . . . 921--929 R. Bisiani and A. Forin Multilanguage parallel programming of heterogeneous machines . . . . . . . . . 930--945 Y.-H. Wei and J.-L. Gaudiot Demand-driven interpretation of FP programs on a data-flow multiprocessor 946--966 R. P. Colwell and R. P. Nix and J. J. O'Donnell and D. B. Papworth and P. K. Rodman A VLIW architecture for a trace scheduling compiler . . . . . . . . . . 967--979 Daniel J. Magenheimer and Liz Peters and Karl W. Peters and Dan Zuras Integer Multiplication and Division on the HP Precision Architecture . . . . . 980--990 C. D. Polychronopoulos Compiler optimizations for enhancing parallelism and their impact on architecture design . . . . . . . . . . 991--1004
F. U. Rosenberger and C. E. Molnar and T. J. Chaney and T.-P. Fang Q-modules: internally clocked delay-insensitive modules . . . . . . . 1005--1018 M. Jeng and H. J. Siegel Design and analysis of dynamic redundancy networks . . . . . . . . . . 1019--1029 T. Fuja and C. Heegard and R. Goodman Linear sum codes for random access memories . . . . . . . . . . . . . . . . 1030--1042 T. J. Brosnan and N. R. Strader II Modular error detection for bit-serial multiplication . . . . . . . . . . . . . 1043--1052 K. G. Shin and T.-H. Lin Modeling and measurement of error propagation in a multimodule computing system . . . . . . . . . . . . . . . . . 1053--1066 B. A. Sanders An incentive compatible flow control algorithm for rate allocation in computer networks . . . . . . . . . . . 1067--1072 D. M. Nicol and J. H. Saltz Dynamic remapping of parallel computations with varying resource demands . . . . . . . . . . . . . . . . 1073--1087 M. Kumar Measuring parallelism in computation-intensive scientific/engineering applications . . 1088--1098 G. L. Craig and C. R. Kine and K. K. Saluja Test scheduling and control for VLSI built-in self-test . . . . . . . . . . . 1099--1109 R. W. Doran Variants of an improved carry look-ahead adder . . . . . . . . . . . . . . . . . 1110--1113 B. Becker Efficient testing of optimal time adders 1113--1121 S. Dhawan and R. C. De Vries Design of self-checking iterative networks . . . . . . . . . . . . . . . . 1121--1125 E. de Souza e Silva and R. R. Muntz Simple relationships among moments of queue lengths in product form queueing networks . . . . . . . . . . . . . . . . 1125--1129 K. S. Ramanatha and N. N. Biswas Design of crosspoint-irredundant PLAs using minimal number of control inputs 1130--1134 D. A. Calahan An analysis of vector startup access delays . . . . . . . . . . . . . . . . . 1134--1137 P. W. Dowd and K. Jabbour Spanning multiaccess channel hypercube computer interconnection . . . . . . . . 1137--1142 W. H. McAnney and J. Savir Built-in checking of the correct self-test signature . . . . . . . . . . 1142--1145 G. F. Taylor and R. H. Steinvorth and J. F. McDonald An architecture for a video rate two-dimensional fast Fourier transform processor . . . . . . . . . . . . . . . 1145--1148 D. B. West and P. Banerjee On the construction of communication networks satisfying bounded fan-in of service ports . . . . . . . . . . . . . 1148--1151 S. M. Reddy and K. K. Saluja and M. G. Karpovsky A data compression technique for built-in self-test . . . . . . . . . . . 1151--1156 Y. I. Gold and S. Moran Estimating metrical change in fully connected mobile networks --- a least upper bound on the worst case . . . . . 1156--1162
L.-S. Lin and S. Sahni Maximum alignment of interchangeable terminals . . . . . . . . . . . . . . . 1166--1177 N. Chandrasekharan and S. S. Iyengar NC algorithms for recognizing chordal graphs and $k$ trees . . . . . . . . . . 1178--1183 C. G. Prohazka Bounding the maximum size of a packet radio network . . . . . . . . . . . . . 1184--1190 M. U. Uyar and A. P. Reeves Dynamic fault reconfiguration in a mesh-connected MIMD environment . . . . 1191--1205 N. Gaitanis Totally self-checking checkers with separate internal fault indication . . . 1206--1213 A. Hopper and R. M. Needham The Cambridge fast ring networking system . . . . . . . . . . . . . . . . . 1214--1223 V. Rego and L. M. Ni Analytic models of cyclic service systems and their application to token-passing local networks . . . . . . 1224--1234 N. T. Jarwala and D. K. Pradhan TRAM: a design methodology for high-performance, easily testable, multimegabit RAMs . . . . . . . . . . . 1235--1250 G. Balbo and S. C. Bruell and S. Ghanta Combining queueing networks and generalized stochastic Petri nets for the solution of complex models of system behavior . . . . . . . . . . . . . . . . 1251--1268 V. S. Cherkassky Performance evaluation of nonrectangular multistage interconnection networks . . 1269--1272 H. M. Shao and I. S. Reed On the VLSI design of a pipeline Reed--Solomon decoder using systolic arrays . . . . . . . . . . . . . . . . . 1273--1280 S. Dhawan and R. C. De Vries Design of self-checking sequential machines . . . . . . . . . . . . . . . . 1280--1284 D. S. Scott and J. Brandenburg Minimal mesh embeddings in binary hypercubes . . . . . . . . . . . . . . . 1284--1285 M. Y. Chan and F. Y. L. Chin On embedding rectangular grids in hypercubes . . . . . . . . . . . . . . . 1285--1288 L. Shen and S. Y. H. Su A functional testing method for microprocessors . . . . . . . . . . . . 1288--1293 K.-Y. Fang and A. S. Wojcik Modular decomposition of combinatorial multiple-values circuits . . . . . . . . 1293--1301 L.-T. Wang and E. J. McCluskey Linear feedback shift register design using cyclic codes . . . . . . . . . . . 1302--1306 M. J. Atallah On multidimensional arrays of processors 1306--1309 D. Brand and V. S. Iyengar Timing analysis using functional analysis . . . . . . . . . . . . . . . . 1309--1314 D. M. Mandelbaum On subsequences of arithmetic sequences 1314--1315 D. A. Carlson Modified-mesh connected parallel computers . . . . . . . . . . . . . . . 1315--1321
S. Laha and J. H. Patel and R. K. Iyer Accurate low-cost methods for performance evaluation of cache memory systems . . . . . . . . . . . . . . . . 1325--1336 Clyde P. Kruskal and Marc Snir and Alan Weiss The Distribution of Waiting Times in Clocked Multistage Interconnection Networks . . . . . . . . . . . . . . . . 1337--1352 D. F. Vrsalovic and D. P. Siewiorek and Z. Z. Segall and E. F. Gehringer Performance prediction and calibration for a class of multiprocessors . . . . . 1353--1365 D. Bernstein and H. Boral and R. Y. Pinter Optimal Chaining in Expression Trees . . 1366--1374 J. Naganuma and T. Ogura and S.-I. Yamada and T. Kimura High-speed CAM-based architecture for a Prolog machine (ASCA) . . . . . . . . . 1375--1383 Virginia Mary Lo Heuristic Algorithms for Task Assignment in Distributed Systems . . . . . . . . . 1384--1397 A. D. Singh Interstitial redundancy: an area efficient fault tolerance scheme for large area VLSI processor arrays . . . . 1398--1410 P. C. Maxwell Comparative analysis of different implementations of multiple-input signature analyzers . . . . . . . . . . 1411--1414 J. Tyszer A multiple fault-tolerant processor network architecture for pipeline computing . . . . . . . . . . . . . . . 1414--1418 H. Krawczyk and W. E. Kozlowski On the diagnosability of multicomputer systems with homogeneous and incomplete tests . . . . . . . . . . . . . . . . . 1419--1421 U. Schwiegelshohn and L. Thiele A systolic array for the assignment problem . . . . . . . . . . . . . . . . 1422--1425 P. de Jong and A. J. van de Goor Test pattern generation for API faults in RAM . . . . . . . . . . . . . . . . . 1426--1428 Ferng-ching Lin and I-Chen Wu Broadcast normalization in systolic design . . . . . . . . . . . . . . . . . 1428--1434 F. T. Luk and H. Park Fault-tolerant matrix triangularizations on systolic arrays . . . . . . . . . . . 1434--1438 Wen-tsuen Chen and Jang-ping Sheu Performance analysis of multistage interconnection networks with hierarchical requesting model . . . . . 1438--1442 Y. Yamamoto and S. Fujita Relationship between $P$-valued majority functions and $P$-valued threshold functions . . . . . . . . . . . . . . . 1442--1445 Kyungsook Yoon Lee and W. Hegazy The extra stage Gamma network . . . . . 1445--1450 N. Gaitanis The design of totally self-checking TMR fault-tolerant systems . . . . . . . . . 1450--1454 A. K. Elmagarmid and A. K. Datta Two-phase deadlock detection algorithm 1454--1458 N. Homobono and C. Peyrat Connectivity of Imase and Itoh digraphs 1459--1461 S. Aborhey Binary decision tree test functions . . 1461--1465 K. G. Shin and P. Ramanathan Transmission delays in hardware clock synchronization . . . . . . . . . . . . 1465--1467 D. B. Skillicorn A new class of fault-tolerant static interconnection networks . . . . . . . . 1468--1470 B. Parhami Carry-free addition of recoded binary signed-digit numbers . . . . . . . . . . 1470--1476 Che-liang Yang and G. M. Masson A distributed algorithm for fault diagnosis in systems with soft failures 1476--1480 D. Sciuto and F. Lombardi On functional testing of array processors . . . . . . . . . . . . . . . 1480--1484
W. E. Weihl Commutativity-based concurrency control for abstract data types . . . . . . . . 1488--1505 B. Bloom Constructing two-writer atomic registers 1506--1514 Mark G. Staskaukas The Formal Specification and Design of a Distributed Electronic Funds-Transfer System . . . . . . . . . . . . . . . . . 1515--1528 M. G. Staskauskas The formal specification and design of a distributed electronic funds-transfer system . . . . . . . . . . . . . . . . . 1515--1528 Greg. N. Frederickson and Ravi Janardan Space-Efficient and Fault-Tolerant Message Routing in Outerplanar Networks 1529--1541 B. A. Coan A compiler that increases the fault tolerance of asynchronous protocols . . 1541--1553 C. Aykanat and F. Ozguner and F. Ercal and P. Sadayappan Iterative algorithms for solution of large sparse systems of linear equations on hypercubes . . . . . . . . . . . . . 1554--1568 P. Bose A novel technique for efficient parallel implementation of a classical logic/fault simulation problem . . . . . 1569--1577 Lee Peizong and Z. M. Kedem Synthesizing linear array algorithms from nested FOR loop algorithms . . . . 1578--1598 C. J. Anfinson and F. T. Luk A linear algebraic model of algorithm-based fault tolerance . . . . 1599--1604 R. Miller and Q. F. Stout Efficient parallel convex hull algorithms . . . . . . . . . . . . . . . 1605--1618 R. S. Francis and I. D. Mathieson A benchmark parallel sort for shared memory multiprocessors . . . . . . . . . 1619--1626 R. Agrawal and H. V. Jagadish Partitioning techniques for large-grained parallelism . . . . . . . 1627--1634 P. Sadayappan and V. Visvanathan Circuit simulation on shared-memory multiprocessors . . . . . . . . . . . . 1634--1642 R. Miller and Q. F. Stout Simulating essential pyramids . . . . . 1642--1648 T. A. Davis and E. S. Davidson Pairwise reduction for the direct, parallel solution of sparse, unsymmetric sets of linear equations . . . . . . . . 1648--1654 P. Ramanathan and K. G. Shin Reliable broadcast in hypercube multicomputers . . . . . . . . . . . . . 1654--1657 R. V. Nageshwara and V. Kumar Concurrent access of priority queues . . 1657--1665 V. K. Janakiram and D. P. Agrawal and R. Mehrotra A randomized parallel backtracking algorithm . . . . . . . . . . . . . . . 1665--1676
A. P. W. Bohm and J. Sargeant Code optimization for tagged-token dataflow machines . . . . . . . . . . . 4--14 A. E. Barbour and A. S. Wojcik A general constructive approach to fault-tolerant design using redundancy 15--29 P. Banerjee and A. Dugar The design, analysis and simulation of a fault-tolerant interconnection network supporting the fetch-and-add primitive 30--46 K. Hwang and P.-S. Tseng and D. Kim An orthogonal multiprocessor for parallel scientific computations . . . . 47--61 L. A. Sanchis Multiple-way network partitioning . . . 62--81 E. A. Bender and J. T. Butler On the size of PLAs required to realize binary and multiple-valued functions . . 82--98 I. F. Akyildiz Product form approximations for queueing networks with multiple servers and blocking . . . . . . . . . . . . . . . . 99--114 J.-Y. Juang and B. W. Wah Resource sharing interconnection networks in multiprocessors . . . . . . 115--129 M. Miyakawa Criteria for selecting a variable in the construction of efficient decision trees 130--141 J. Bhasker and S. Sahni Via assignment in single-row routing . . 142--148 C. J. Zarowski and R. D. McLeod and H. C. Card Primitive cellular automata, threshold decomposition, and ranked order operations . . . . . . . . . . . . . . . 148--149 H. V. Jagadish and T. Kailath A family of new efficient arrays for matrix multiplication . . . . . . . . . 149--155 R. P. Cook An empirical analysis of the Lilith instruction set . . . . . . . . . . . . 156--158
F. El Guibaly Design and analysis of arbitration protocols . . . . . . . . . . . . . . . 161--171 S. Vassiliadis and E. M. Schwarz and D. J. Hanrahan A General Proof for Overlapped Multiple-Bit Scanning Multiplications 172--183 Zhixi Fang and Xiaobo Li and L. M. Ni On the communication complexity of generalized $2$-D convolution on array processors . . . . . . . . . . . . . . . 184--194 A. K. Somani and V. K. Agarwal and D. Avis On the complexity of single fault set diagnosability and diagnosis problems 195--201 J.-C. Liu and K. G. Shin Polynomial Testing of Packet Switching Networks . . . . . . . . . . . . . . . . 202--217 J. Gait A kernel for high-performance multicast communications . . . . . . . . . . . . . 218--226 Woei Lin and C.-L. Wu A fault-tolerant mapping scheme for a configurable multiprocessor system . . . 227--237 I. D. Scherson and S. Sen Parallel sorting in two-dimensional VLSI models of computation . . . . . . . . . 238--249 C. Kim and A. K. Agrawala Analysis of the fork-join queue . . . . 250--255 R. F. Molyneaux and A. Albicki Comments on ``Ternary scan design for VLSI testability'' by M. Hu and K. C. Smith . . . . . . . . . . . . . . . . . 256--263 W. Helbig and V. Milutinovic A DCFL E/D-MESFET GaAs experimental RISC machine . . . . . . . . . . . . . . . . 263--274 V. Cherkassky and M. Malek Partitioning and permuting properties of CC-banyan networks . . . . . . . . . . . 274--278 P. J. Varman and I. V. Ramakrishnan Optimal matrix multiplication on fault-tolerant VLSI arrays . . . . . . . 278--283 T. Nakatani and S.-T. Huang and B. W. Arden and S. K. Tripathi $K$-way bitonic sort . . . . . . . . . . 283--288 A. V. Gelder PRAM processor allocation: a hidden bottleneck in sublogarithmic algorithms 289--292 A. P. Shenoy and R. Kumaresan Fast base extension using a redundant modulus in RNS . . . . . . . . . . . . . 292--297 I. Gazit and M. Malek On the number of permutations performable by extra-stage multistage interconnection networks . . . . . . . . 297--302 K. Y. Lee and H. Yoon The PM221 interconnection network . . . 302--307 H. F. Li and R. Jayakumar and C. Lam Restructuring for fault-tolerant systolic arrays . . . . . . . . . . . . 307--311 A. I. Concepcion A hierarchical computer architecture for distributed simulation . . . . . . . . . 311--319
R. Miller and Q. F. Stout Mesh computer algorithms for computational geometry . . . . . . . . . 321--340 J. A. Stankovic Decentralized decision-making for task reallocation in a hard real-time system 341--355 F. J. Meyer and D. K. Pradhan Dynamic testing strategy for distributed systems . . . . . . . . . . . . . . . . 356--365 J. Kljaich, Jr. and B. T. Smith and A. S. Wojcik Formal verification of fault tolerance using theorem-proving techniques . . . . 366--376 A. S. Noetzel An interpolating memory unit for function evaluation: analysis and design 377--384 A. Varma and C. S. Raghavendra Fault-tolerant routing in multistage interconnection networks . . . . . . . . 385--393 P. Mazumder and J. H. Patel Parallel testing for pattern-sensitive faults in semiconductor random-access memories . . . . . . . . . . . . . . . . 394--407 D. L. Eager and J. Zahorjan and E. D. Lazowska Speedup versus efficiency in parallel systems . . . . . . . . . . . . . . . . 408--423 B. P. Sinha and P. K. Srimani Fast parallel algorithms for binary multiplication and their implementation on systolic architectures . . . . . . . 424--431 A. E. Conway and E. de Souza e Silva and S. S. Lavenberg Mean value analysis by chain of product form queueing networks . . . . . . . . . 432--442 T. A. Rice and L. H. Jamieson A highly parallel algorithm for root extraction . . . . . . . . . . . . . . . 443--449 A. El-Amawy A systolic architecture for fast dense matrix inversion . . . . . . . . . . . . 449--455 C. G. Prohazka Decoupling link scheduling constraints in multi-hop packet radio networks . . . 455--458 Y.-C. Hong and T. H. Payne Parallel sorting in a ring network of processors . . . . . . . . . . . . . . . 458--464 B. L. Bodnar and A. C. Liu Modeling and performance analysis of single-bus tightly-coupled multiprocessors . . . . . . . . . . . . 464--470 V. K. P. Kumar and Y.-C. Tsai On mapping algorithms to linear and fault-tolerant systolic arrays . . . . . 470--478 M. A. Kennedy and G. G. L. Meyer The PMC system level fault model: cardinality properties of the implied faulty sets . . . . . . . . . . . . . . 478--480
G. S. Sohi Cache memory organization to enhance the yield of high performance VLSI processors . . . . . . . . . . . . . . . 484--492 M.-F. Chang and W. K. Fuchs and J. H. Patel Diagnosis and repair of memory with coupling faults . . . . . . . . . . . . 493--500 S.-Y. Kung and S.-N. Jean and C.-W. Chang Fault-tolerant array processors using single-track switches . . . . . . . . . 501--514 J. H. Kim and S. M. Reddy On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement . . . . . . . . . . . 515--525 H. Y. Youn and A. D. Singh On implementing large binary tree architectures in VLSI and WSI . . . . . 526--537 F. J. Meyer and D. K. Pradhan Modeling defect spatial distribution . . 538--546 M. Wang and M. Cutler and S. Y. H. Su Reconfiguration of VLSI/WSI mesh array processors with two-level redundancy . . 547--554 S. B. Akers and B. Krishnamurthy A group-theoretic model for symmetric interconnection networks . . . . . . . . 555--566 M. R. Samatham and D. K. Pradhan The de Bruijn multiprocessor network: a versatile parallel processing and sorting network for VLSI . . . . . . . . 567--581 T. Sasao On the optimal design of multiple-valued PLAs . . . . . . . . . . . . . . . . . . 582--592 H. Fleisher and J. Giraldi and R. Phoenix and M. Tavel Minimizability of random Boolean functions . . . . . . . . . . . . . . . 593--595 Corinna Lee Multistep Gradual Rounding . . . . . . . 595--600 A. Mukherjee Hardware algorithms for determining similarity between two strings . . . . . 600--603 L. C. Liu and H. C. Du A near-optimal heuristic algorithm for single-flow routing . . . . . . . . . . 603--608
H. P. Lin and H. E. Stoval, III Self-Synchronizing Communication Protocols . . . . . . . . . . . . . . . 609--625 K. H. Kim and H. O. Welch Distributed execution of recovery blocks: an approach for uniform treatment of hardware and software faults in real-time applications . . . . 626--636 R. David and A. Fuentes and B. Courtois Random pattern testing versus deterministic testing of RAMs . . . . . 637--650 M. Singhal A heuristically-aided algorithm for mutual exclusion in distributed systems 651--662 A. Nicolau Run-time disambiguation: coping with statically unpredictable dependencies 663--678 V. V. Karmarkar and J. G. Kuhl An integrated approach to distributed demand assignment in multiple-bus local networks . . . . . . . . . . . . . . . . 679--695 I. Suzuki and H. Lu Temporal Petri nets and their application to modeling and analysis of a handshake daisy chain arbiter . . . . 696--704 J. F. Kurose and R. Simha A microeconomic approach to optimal resource allocation in distributed computer systems . . . . . . . . . . . . 705--717 I. J. Davis Local correction of helix($k$) lists . . 718--724 H. Burkhart and R. Millen Performance-measurement tools in a multiprocessor environment . . . . . . . 725--737 H. Masuyama and T. Ichimori Tolerance of double-loop computer networks to multinode failures . . . . . 738--741 P. S. P. Wang and Y. Y. Zhang A fast and flexible thinning algorithm 741--745 W. Liu and T. H. Hildebrandt and R. Cavin III Hamiltonian cycles in the shuffle-exchange network . . . . . . . . 745--750 A. El-Amawy Comments, with reply, on ``Can redundancy and masking improve the performance of synchronizers?'' by L. Kleeman and A. Cantoni . . . . . . . . . 750--753 M. J. Foster Avoiding latch formation in regular expression recognizers . . . . . . . . . 754--756 L. Lin and S. Sahni Fair edge deletion problems . . . . . . 756--761 R. S. Roberts and S. C. Kothari On computing the combinatorial power of SW-banyan networks . . . . . . . . . . . 761--765 I. Parberry A note on nondeterminism in small, fast parallel computers . . . . . . . . . . . 766--767
P. D. Hortensius and H. C. Card and R. D. McLeod and W. Pries Importance sampling for Ising computers using one-dimensional cellular automata 769--774 J. B. Dugan and K. S. Trivedi Coverage modeling for dependability analysis of fault-tolerant systems . . . 775--787 T. R. Damarla and M. Karpovsky Fault detection in combinational networks by Reed--Muller transforms . . 788--797 M. Kobayashi and M. H. MacDougall The stack growth function: cache line reference models . . . . . . . . . . . . 798--805 F. T. Luk and H. Park A proof of convergence for two parallel Jacobi SVD algorithms . . . . . . . . . 806--811 S. Utku and M. Salama and R. J. Melosh A family of permutations for concurrent factorization of block tridiagonal matrices . . . . . . . . . . . . . . . . 812--824 K. Shimizu and E. Goto and S. Ichikawa CPC (cyclic pipeline computer)-an architecture suited for Josephson and pipelined-memory machines . . . . . . . 825--832 C. W. H. Lam and H. F. Li and R. Jayakumar A study of two approaches for reconfiguring fault-tolerant systolic arrays . . . . . . . . . . . . . . . . . 833--844 G. M. Brown and M. G. Gouda and C.-L. Wu Token systems that self-stabilize . . . 845--852 A. A. Bertossi and M. A. Bonuccelli A gracefully degradable VLSI system for linear programming . . . . . . . . . . . 853--861 S. Chakravarty and H. B. Hunt III A note on detecting sneak paths in transistor networks . . . . . . . . . . 861--864 S. Chakravarty and H. B. Hunt III and S. S. Ravi and D. J. Rosenkrantz The complexity of generating minimum test sets for PLA's and monotone combinational circuits . . . . . . . . . 865--869 R. Chillarege and R. K. Iyer An experimental study of memory fault latency . . . . . . . . . . . . . . . . 869--874 V. Milutinovic and M. Bettinger and W. Helbig Multiplier/shifter design tradeoffs in a 32-bit microprocessor . . . . . . . . . 874--880 L. Vroomen and P. Zsombor-Murray and P. Baracos and R. Hudson Comments on `Algorithmic state machine design and automatic theorem proving: dual approaches to the same activity' 880--881 A. T. Dahbura and K. K. Sabnani and W. J. Hery Spare capacity as a means of fault detection and diagnosis in multiprocessor systems . . . . . . . . . 881--891 N. Santoro and E. Suen Reduction techniques for selection in distributed files . . . . . . . . . . . 891--896 J. Jaja and S.-M. Wu A new approach to realizing partially symmetric functions . . . . . . . . . . 896--898 D. C. Schmidt An analytic model of printed circuit wiring distributions . . . . . . . . . . 898--903 M. A. Sridhar A fast algorithm for testing isomorphism of permutation networks . . . . . . . . 903--909 A. Park and K. Balasubramanian and R. J. Lipton Array access bounds for block storage memory systems . . . . . . . . . . . . . 909--913 S.-C. Chu and J. R. Armstrong $t$-TDA-diagnosable systems . . . . . . 914--920 C. K. Baru and O. Frieder Database operations in a cube-connected multicomputer system . . . . . . . . . . 920--927
S. H. Hosseini On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors . . . . 932--942 S. M. Sharrock and D. H.-C. Du Efficient CSMA/CD-based protocols for multiple priority classes . . . . . . . 943--954 R. M. Dewan and B. Gavish Models for the combined logical and physical design of databases . . . . . . 955--967 V. K. Vaishnavi Multidimensional balanced binary trees 968--985 R. T. Boute Representational and denotational semantics of digital systems . . . . . . 986--999 S. Abraham and K. Padmanabhan Performance of the direct binary $n$-cube network for multiprocessors . . 1000--1011 D. Thiebaut On the fractal dimension of computer programs and its application to the prediction of the cache miss ratio . . . 1012--1026 L. N. Bhuyan and D. Ghosal and Q. Yang Approximate analysis of single and multiple ring networks . . . . . . . . . 1027--1040 B. Krishnamurthy and I. G. Tollis Improved techniques for estimating signal probabilities . . . . . . . . . . 1041--1045 A. Pincin A new algorithm for multiplication in finite fields . . . . . . . . . . . . . 1045--1049 M. Scott Fast rounding in multiprecision floating-slash arithmetic . . . . . . . 1049--1052 H. Schmeck and H. Schroder and C. Starke Systolic $s^2$-way merge sort is optimal 1052--1056
W. T. Tsai and C. V. Ramamoorthy and W. K. Tsai and O. Nishiguchi An Adaptive Hierarchical Routing Protocol . . . . . . . . . . . . . . . . 1059--1075 S. Saito and H. Yoshida and T. L. Junii The CrossoverNet LAN System Using an Intelligent Head-End . . . . . . . . . . 1076--1085 S. Saito and H. Yoshida and T. L. Kunii The Crossover Net LAN system using an intelligent head-end . . . . . . . . . . 1076--1085 W. Lin and T.-L. Sheu and C. R. Das and T.-Y. Feng and C.-L. Wu A Conflict Free Routing Scheme on Multistage Interconnection networks . . 1086--1097 K. M. Baumgartner and B. W. Wah GAMMON: a Load Balancing Strategy for Local Computer Systems with Multiaccess Networks . . . . . . . . . . . . . . . . 1098--1109 K. Ramamritham and J. A. Stankovic and W. Zhao Distributed Scheduling of Tasks With Deadlines and Resource Requirements . . 1110--1123 K. G. Shin and Y.-C. Chang Load Sharing in Distributed Real-Time Systems with State-Change Broadcasts . . 1124--1143 Q. Yang and L. N. Bhuyan and B.-C. Liu Analysis and comparison of cache coherence protocols for a packet-switched multiprocessor . . . . . 1143--1153 C. Scheurich and M. Dubois Dynamic page migration in multiprocessors with distributed global memory . . . . . . . . . . . . . . . . . 1154--1163 A. Ghafoor and P. Sole Performance of fault-tolerant diagnostics in the hypercube systems . . 1164--1172 K. Ravindran and S. T. Chanson Failure Transparency in Remote Procedure Calls . . . . . . . . . . . . . . . . . 1173--1187 K. H. Kim and S. M. Yang Performance Impacts of Look-Ahead Execution in the Conversation Scheme . . 1188--1202 J.-K. Peir and R. Cytron Minimum distance: a method for partitioning recurrences for multiprocessors . . . . . . . . . . . . 1203--1211 M. Roesler and W. A. Burkhard Resolution of Deadlocks in Object-Oriented Distributed Systems . . 1212--1224
J.-L. Gaudiot and Y.-H. Wei Token relabeling in a tagged token data-flow architecture . . . . . . . . . 1225--1239 K. V. S. Ramarao Distributed algorithms for network recognition problems . . . . . . . . . . 1240--1248 S. L. Johnsson and C.-T. Ho Optimum broadcasting and personalized communication in hypercubes . . . . . . 1249--1268 M. A. Yoder and L. H. Jamieson Simulation of a word recognition system on two parallel architectures . . . . . 1269--1284 C. D. Polychronopoulos and D. J. Kuck and D. A. Padua Utilizing multidimensional loop parallelism on large scale parallel processor systems . . . . . . . . . . . 1285--1296 R. Gupta and A. Zorat and I. V. Ramakrishnan Reconfigurable multipipelines for vector supercomputers . . . . . . . . . . . . . 1297--1307 D. Bernstein and M. Rodeh and I. Gertner On the complexity of scheduling problems for parallel/pipelined machines . . . . 1308--1313 H. S. Stone Optimal search policies for searches with I/O bound tasks . . . . . . . . . . 1314--1320 B. Hochet and P. Quinton and Y. Robert Systolic Gaussian elimination over $\mathrm{GF}(p)$ with partial pivoting 1321--1324 S. G. Smith Incremental computation of squares and sums of squares . . . . . . . . . . . . 1325--1328 S. G. Smith Comments on ``A signed bit-sequential multiplier'' by T. Rhyne and N. R. Strader II . . . . . . . . . . . . . . . 1328--1330 D. M. Topkis All-to-All Broadcast by Flooding in Communications Networks . . . . . . . . 1330--1333 M. Furer and K. Mehlhorn AT$^2$-optimal Galois field multiplier for VLSI . . . . . . . . . . . . . . . . 1333--1336 B. Ciciani and G. Cantone Comments on ``Design and evaluation of a fault-tolerant multiprocessor using hardware recovery blocks'' by Y.-H. Lee and K. G. Shin . . . . . . . . . . . . . 1336--1337 M. Lu and D. Zhang and T. Murata A design approach for self-diagnosis of fault-tolerant clock synchronization . . 1337--1341 L. Dadda On serial-input multipliers for two's complement numbers . . . . . . . . . . . 1341--1345 H. Li and M. Maresca Polymorphic-torus network . . . . . . . 1345--1351
I. Cidon and M. Sidi Distributed assignment algorithms for multihop packet radio networks . . . . . 1353--1361 H. G. Badr and S. Podar An optimal shortest-path routing policy for network computers with regular mesh-connected topologies . . . . . . . 1362--1371 A. Ganz and I. Chlamtac Path allocation access control in fiber optic communication systems . . . . . . 1372--1382 G.-L. Feng A VLSI architecture for fast inversion in $\mathrm{GF}(2^m)$ . . . . . . . . . 1383--1386 G. Lee A performance bound of multistage combining networks . . . . . . . . . . . 1387--1395 G. Bilardi Merging and sorting networks with the topology of the omega network . . . . . 1396--1403 S. Muroga and Y. Kambayashi and H. C. Lai and J. N. Culliney The transduction method-design of logic networks based on permissible functions 1404--1424 A. Ghafoor and T. R. Bashkow and I. Ghafoor Bisectional Fault-Tolerant Communication Architecture for Supercomputer Systems 1425--1446 A. Y. Oruc and A. Thirumalai A systematic design of cellular permutation arrays . . . . . . . . . . . 1447--1451 W. Shen and A. Y. Oruc On systolic contractions of program graphs . . . . . . . . . . . . . . . . . 1451--1457 C. C. Wang An algorithm to design finite field multipliers using a self-dual normal basis . . . . . . . . . . . . . . . . . 1457--1460 P. R. Chalasani and S. Bhawmik and A. Acharya and P. Palchaudhuri Design of testable VLSI circuits with minimum area overhead . . . . . . . . . 1460--1462 C. K. Chang and T. M. Jiang A binary single-key-lock system for access control . . . . . . . . . . . . . 1462--1466 P. D. Hortensius and R. D. McLeod and H. C. Card Parallel random number generation for VLSI systems using cellular automata . . 1466--1473 D. M. Mandelbaum On iterative arrays for the Euclidean algorithm over finite fields . . . . . . 1473--1478
C.-C. J. Li and P. P. Chen and W. K. Fuchs Local concurrent error detection and correction in data structures using virtual backpointers . . . . . . . . . . 1481--1492 M. Blaum and H. Van Tilborg On $t$-error correcting/all unidirectional error detecting codes . . 1493--1501 A. Kumar Adaptive load control of the central processor in a distributed system with a star topology . . . . . . . . . . . . . 1502--1512 R. Mirchandaney and D. Towsley and J. A. Stankovic Analysis of the effects of delays on load sharing . . . . . . . . . . . . . . 1513--1525 G. E. Blelloch Scans as primitive parallel operations 1526--1538 G. Alaghband and H. F. Jordan Sparse Gaussian elimination with controlled fill-in on a shared memory multiprocessor . . . . . . . . . . . . . 1539--1557 L. Lipsky and S. C. Seth Signal probabilities in AND-OR trees . . 1558--1563 Y.-L. Wang and R. C. T. Lee and J. S. Chang The number of intersections between two rectangular paths . . . . . . . . . . . 1564--1571 A. Kapralski The maximum and minimum selector SELRAM and its application for developing fast sorting machines . . . . . . . . . . . . 1572--1577 S. S. S. P. Rao and J. R. Isaac Interface optimization: an algorithm for the detection of data path redundancy and reconfigurability towards obtaining minimal bus interfaces . . . . . . . . . 1577--1580 B. B. Bhattacharya and S. C. Seth Design of parity testable combinational circuits . . . . . . . . . . . . . . . . 1580--1584 A. R. Calderbank and E. G. Coffman, Jr. and L. Flatto A note extending the analysis of two-head disk systems to more general seek-time characteristics . . . . . . . 1584--1586 A.-H. Esfahanian Generalized measures of fault tolerance with application to $N$-cube networks 1586--1591 R. Melham A systolic accelerator for the iterative solution of sparse linear systems . . . 1591--1595 S. Ghosh and M.-L. Yu A preemptive scheduling mechanism for accurate behavioral simulation of digital designs . . . . . . . . . . . . 1595--1600 J. T. Blake and K. S. Trivedi Multistage interconnection network reliability . . . . . . . . . . . . . . 1600--1604 N. J. Naclerio and S. Masuda and K. Nakajima The via minimization problem is NP-complete . . . . . . . . . . . . . . 1604--1608
M. D. Hill and A. J. Smith Evaluating associativity in CPU caches 1612--1630 T. E. Anderson and E. D. Lazowska and H. M. Levy The performance implications of thread management alternatives for shared-memory multiprocessors . . . . . 1631--1644 N. P. Jouppi The nonuniform distribution of instruction-level and machine parallelism and its effect on performance . . . . . . . . . . . . . . 1645--1658 R. H. Saavedra-Barrera and A. J. Smith and E. Miya Machine characterization based on an abstract high-level language machine . . 1659--1679 A. L. N. Reddy and P. Banerjee An evaluation of multiple-disk I/O systems . . . . . . . . . . . . . . . . 1680--1690 D. D. E. Long and J. L. Carroll and K. Stewart Estimating the reliability of regeneration-based replica control protocols . . . . . . . . . . . . . . . 1691--1702 V. P. Kumar and A. L. Reibman Failure dependent performance analysis of a fault-tolerant multistage interconnection network . . . . . . . . 1703--1713 R. R. Muntz and E. De Souza e Silva and A. Goyal Bounding availability of repairable systems . . . . . . . . . . . . . . . . 1714--1723 S. Shenker and A. Weinrib The optimal control of heterogeneous queueing systems: a paradigm for load-sharing and routing . . . . . . . . 1724--1735 J. Hong and X. Tan and D. Towsley A performance analysis of minimum laxity and earliest deadline scheduling in a real-time system . . . . . . . . . . . . 1736--1744
P. Geffe How to protect data with ciphers that are really hard to break . . . . . . . . 99--101