Table of contents for issues of IEEE Transactions on Computers

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Volume 49, Number 1, January, 2000
Volume 49, Number 2, February, 2000
Volume 49, Number 3, March, 2000
Volume 49, Number 4, April, 2000
Volume 49, Number 5, May, 2000
Volume 49, Number 6, June, 2000
Volume 49, Number 7, July, 2000
Volume 49, Number 8, August, 2000
Volume 49, Number 9, September, 2000
Volume 49, Number 10, October, 2000
Volume 49, Number 11, November, 2000
Volume 49, Number 12, December, 2000
Volume 50, Number 1, January, 2001
Volume 50, Number 2, February, 2001
Volume 50, Number 3, March, 2001
Volume 50, Number 4, April, 2001
Volume 50, Number 5, May, 2001
Volume 50, Number 6, June, 2001
Volume 50, Number 7, July, 2001
Volume 50, Number 8, August, 2001
Volume 50, Number 9, September, 2001
Volume 50, Number 10, October, 2001
Volume 50, Number 11, November, 2001
Volume 50, Number 12, December, 2001
Volume 51, Number 1, January, 2002
Volume 51, Number 2, February, 2002
Volume 51, Number 3, March, 2002
Volume 51, Number 4, April, 2002
Volume 51, Number 5, May, 2002
Volume 51, Number 6, June, 2002
Volume 51, Number 7, July, 2002
Volume 51, Number 8, August, 2002
Volume 51, Number 9, September, 2002
Volume 51, Number 10, October, 2002
Volume 51, Number 11, November, 2002
Volume 51, Number 12, December, 2002
Volume 52, Number 1, January, 2003
Volume 52, Number 2, February, 2003
Volume 52, Number 3, March, 2003
Volume 52, Number 4, April, 2003
Volume 52, Number 5, May, 2003
Volume 52, Number 6, June, 2003
Volume 52, Number 7, July, 2003
Volume 52, Number 8, August, 2003
Volume 52, Number 9, September, 2003
Volume 52, Number 10, October, 2003
Volume 52, Number 11, November, 2003
Volume 52, Number 12, December, 2003
Volume 53, Number 1, January, 2004
Volume 53, Number 2, February, 2004
Volume 53, Number 3, March, 2004
Volume 53, Number 4, April, 2004
Volume 53, Number 5, May, 2004
Volume 53, Number 6, June, 2004
Volume 53, Number 7, July, 2004
Volume 53, Number 8, August, 2004
Volume 53, Number 9, September, 2004
Volume 53, Number 10, October, 2004
Volume 53, Number 11, November, 2004
Volume 53, Number 12, December, 2004
Volume 54, Number 1, January, 2005
Volume 54, Number 2, February, 2005
Volume 54, Number 3, March, 2005
Volume 54, Number 4, April, 2005
Volume 54, Number 5, May, 2005
Volume 54, Number 6, June, 2005
Volume 54, Number 7, July, 2005
Volume 54, Number 8, August, 2005
Volume 54, Number 9, September, 2005
Volume 54, Number 10, October, 2005
Volume 54, Number 11, November, 2005
Volume 54, Number 12, December, 2005
Volume 55, Number 1, January, 2006
Volume 55, Number 2, February, 2006
Volume 55, Number 3, March, 2006
Volume 55, Number 4, April, 2006
Volume 55, Number 5, May, 2006
Volume 55, Number 6, June, 2006
Volume 55, Number 7, July, 2006
Volume 55, Number 8, August, 2006
Volume 55, Number 9, September, 2006
Volume 55, Number 10, October, 2006
Volume 55, Number 11, November, 2006
Volume 55, Number 12, December, 2006
Volume 56, Number 1, January, 2007
Volume 56, Number 2, February, 2007
Volume 56, Number 3, March, 2007
Volume 56, Number 4, April, 2007
Volume 56, Number 5, May, 2007
Volume 56, Number 6, June, 2007
Volume 56, Number 7, July, 2007
Volume 56, Number 8, August, 2007
Volume 56, Number 9, September, 2007
Volume 56, Number 10, October, 2007
Volume 56, Number 11, November, 2007
Volume 56, Number 12, December, 2007
Volume 57, Number 1, January, 2008
Volume 57, Number 2, February, 2008
Volume 57, Number 3, March, 2008
Volume 57, Number 4, April, 2008
Volume 57, Number 5, May, 2008
Volume 57, Number 6, June, 2008
Volume 57, Number 7, July, 2008
Volume 57, Number 8, August, 2008
Volume 57, Number 9, September, 2008
Volume 57, Number 10, October, 2008
Volume 57, Number 11, November, 2008
Volume 57, Number 12, December, 2008
Volume 58, Number 1, January, 2009
Volume 58, Number 2, February, 2009
Volume 58, Number 3, March, 2009
Volume 58, Number 4, April, 2009
Volume 58, Number 5, May, 2009
Volume 58, Number 6, June, 2009
Volume 58, Number 7, July, 2009
Volume 58, Number 8, August, 2009
Volume 58, Number 9, September, 2009
Volume 58, Number 10, October, 2009
Volume 58, Number 11, November, 2009
Volume 58, Number 12, December, 2009
Volume 61, Number 4, April, 2012
Volume 62, Number 1, January, 2013


IEEE Transactions on Computers
Volume 49, Number 1, January, 2000

                     J. Kin and   
                   M. Gupta and   
           W. H. Mangione-Smith   Filtering memory references to increase
                                  energy efficiency  . . . . . . . . . . . 1--15
              M. Chatterjee and   
                S. Banerjee and   
                  D. K. Pradhan   Buffer assignment algorithms on data
                                  driven ASICs . . . . . . . . . . . . . . 16--32
         Asger Munk Nielsen and   
            David W. Matula and   
              Chung Nan Lyu and   
                       Guy Even   An IEEE compliant floating-point adder
                                  that conforms with the pipeline
                                  packet-forwarding paradigm . . . . . . . 33--47
             Wei Kang Huang and   
                F. J. Meyer and   
                    F. Lombardi   An approach for detecting multiple
                                  faulty FPGA logic blocks . . . . . . . . 48--54
                 Hagbae Kim and   
                     K. G. Shin   Evaluation of fault tolerance latency
                                  from real-time application's
                                  perspectives . . . . . . . . . . . . . . 55--64
                S. Tongsima and   
               E. H.-M. Sha and   
         C. Chantrapornchai and   
                D. R. Surma and   
                   N. L. Passos   Probabilistic loop scheduling for
                                  applications with uncertain execution
                                  time . . . . . . . . . . . . . . . . . . 65--80
           T. F. Abdelzaher and   
                     K. G. Shin   Period-based load partitioning and
                                  assignment for large real-time
                                  applications . . . . . . . . . . . . . . 81--87
                I. Pomeranz and   
                    S. M. Reddy   On finding a minimal functional
                                  description of a finite-state machine
                                  for test generation for adjacent
                                  machines . . . . . . . . . . . . . . . . 88--94
                      Anonymous   1999 reviewers list  . . . . . . . . . . 95--96

IEEE Transactions on Computers
Volume 49, Number 2, February, 2000

                 S. Poledna and   
                   A. Burns and   
                A. Wellings and   
                     P. Barrett   Replica determinism and flexible
                                  scheduling in hard real-time dependable
                                  systems  . . . . . . . . . . . . . . . . 100--111
                Tei-Wei Kuo and   
                   Shao-Juen Ho   Similarity-based load adjustment for
                                  static real-time transaction systems . . 112--126
                Lin-Wen Lee and   
             P. Scheuermann and   
                   R. Vingralek   File assignment in parallel I/O systems
                                  with minimal variance of service time    127--140
             V. S. Dimitrov and   
              G. A. Jullien and   
                   W. C. Miller   Complexity and fast algorithms for
                                  multiexponentiations . . . . . . . . . . 141--147
                Yi-Bing Lin and   
                 Wei-Ru Lai and   
                 Rong-Jaye Chen   Performance analysis for dual band PCS
                                  networks . . . . . . . . . . . . . . . . 148--159
                   A. Patel and   
                 A. Kusalik and   
                    C. McCrosky   Area-efficient VLSI layouts for binary
                                  hypercubes . . . . . . . . . . . . . . . 160--169
                   A. A. Hiasat   New efficient structure for a modular
                                  multiplier for RNS . . . . . . . . . . . 170--174
                I. Pomeranz and   
                    S. M. Reddy   On the use of fully specified initial
                                  states for testing of synchronous
                                  sequential circuits  . . . . . . . . . . 175--182
               K. M. Zuberi and   
                     K. G. Shin   Design and implementation of efficient
                                  message scheduling for controller area
                                  network  . . . . . . . . . . . . . . . . 182--188

IEEE Transactions on Computers
Volume 49, Number 3, March, 2000

                S. Cotofana and   
                 S. Vassiliadis   Signed digit addition and related
                                  operations with threshold logic  . . . . 193--207
                     Z. Luo and   
                   M. Martonosi   Accelerating pipelined integer and
                                  floating-point accumulations in
                                  configurable hardware with delayed
                                  addition techniques  . . . . . . . . . . 208--218
                  N. Takagi and   
                   K. Nakashima   Discrete interval truth values logic and
                                  its application  . . . . . . . . . . . . 219--229
              A. Bondavalli and   
             S. Chiaradonna and   
         F. Di Giandomenico and   
                    F. Grandoni   Threshold-based mechanisms to
                                  discriminate transient from intermittent
                                  faults . . . . . . . . . . . . . . . . . 230--245
              San-Yuan Wang and   
                  Yu-Chee Tseng   Algebraic foundations and broadcasting
                                  algorithms for wormhole-routed all-port
                                  tori . . . . . . . . . . . . . . . . . . 246--258
             M. C. Azizoglu and   
                   O. Egecioglu   Lower bounds on communication loads and
                                  optimal placements in torus networks . . 259--266
                   U. Kalay and   
                 D. V. Hall and   
                M. A. Perkowski   A minimal universal test set for
                                  self-test of EXOR-Sum-of-Products
                                  circuits . . . . . . . . . . . . . . . . 267--276
            R. C. Tekumalla and   
                    P. R. Menon   On redundant path delay faults in
                                  synchronous sequential circuits  . . . . 277--282
                  S. D. Stoller   Leader election in asynchronous
                                  distributed systems  . . . . . . . . . . 283--284

IEEE Transactions on Computers
Volume 49, Number 4, April, 2000

                   F. Fummi and   
                      D. Sciuto   A hierarchical test generation approach
                                  for large controllers  . . . . . . . . . 289--302
               M. Di Natale and   
                J. A. Stankovic   Scheduling distributed real-time tasks
                                  with minimum jitter  . . . . . . . . . . 303--316
              T. Ramalingom and   
            K. Thulasiraman and   
                         A. Das   A matroid-theoretic solution to an
                                  assignment problem in the conformance
                                  testing of communication protocols . . . 317--330
                   J. Huang and   
                    D. J. Lilja   Extending value reuse to basic blocks
                                  with compiler support  . . . . . . . . . 331--347
               Michael Shyu and   
              Guang-Ming Wu and   
              Yu-Dong Chang and   
                  Yao-Wen Chang   Generic universal switch blocks  . . . . 348--359
          L. Heinrich-Litan and   
                     P. Molitor   Least upper bounds for the size of OBDDs
                                  using symmetry properties  . . . . . . . 360--368
                T. C. Mowry and   
                      C.-K. Luk   Understanding why correlation profiling
                                  improves the predictability of data
                                  cache misses in nonnumeric applications  369--384

IEEE Transactions on Computers
Volume 49, Number 5, May, 2000

              M. J. Schulte and   
        E. E. Swartzlander, Jr.   A Family of Variable-Precision, Interval
                                  Arithmetic Processors  . . . . . . . . . 387--397
                    G. Even and   
                     W. J. Paul   On the design of IEEE compliant floating
                                  point units  . . . . . . . . . . . . . . 398--413
                   C. Morin and   
            A.-M. Kermarrec and   
                 M. Banatre and   
                    A. Gefflaut   An efficient and scalable approach for
                                  implementing fault-tolerant DSM
                                  architectures  . . . . . . . . . . . . . 414--430
                       N. Tsuda   Fault-tolerant processor arrays using
                                  additional bypass linking allocated by
                                  Graph-Node coloring  . . . . . . . . . . 431--442
               Shi-Yu Huang and   
           Kwang-Ting Cheng and   
           Kuang-Chien Chen and   
           Chung-Yang Huang and   
                      F. Brewer   AQUILA: an equivalence checking system
                                  for large sequential designs . . . . . . 443--464
                   H. Singh and   
               Ming-Hau Lee and   
               Guangming Lu and   
              F. J. Kurdahi and   
             N. Bagherzadeh and   
             E. M. Chaves Filho   MorphoSys: an integrated reconfigurable
                                  system for data-parallel and
                                  computation-intensive applications . . . 465--481
                   A. Datta and   
                  S. H. Son and   
                       V. Kumar   Is a bird in the hand worth more than
                                  two in the bush? Limitations of priority
                                  cognizance in conflict resolution for
                                  firm real-time database systems  . . . . 482--502
          A. Halbutogullari and   
                      C. K. Koc   Mastrovito multiplier for general
                                  irreducible polynomials  . . . . . . . . 503--518
                F. M. Assis and   
                 C. E. Pedreira   An architecture for computing Zech's
                                  logarithms in $\mathrm{GF}(2^m)$ . . . . 519--524
                      Anonymous   Correction to ``A minimum universal test
                                  set for self-test of
                                  EXOR-sum-of-products circuits''  . . . . 525--525

IEEE Transactions on Computers
Volume 49, Number 6, June, 2000

                F. Lombardi and   
                        M. Sami   Guest editors' introduction  . . . . . . 529--531
                   I. Koren and   
                       Z. Koren   Incorporating yield enhancement into the
                                  floorplanning process  . . . . . . . . . 532--541
                  T. Horita and   
                    I. Takanami   Fault-tolerant processor arrays based on
                                  the 1$1/2$-track switches with flexible
                                  spare distributions  . . . . . . . . . . 542--552
                  Chor Ping Low   An efficient reconfiguration algorithm
                                  for degradable VLSI/WSI arrays . . . . . 553--559
                   C. Metra and   
                 M. Favalli and   
                       B. Ricco   Self-checking detection and diagnosis of
                                  transient, delay, and crosstalk faults
                                  affecting bus lines  . . . . . . . . . . 560--574
                   C. Thibeault   On the adaptation of Viterbi algorithm
                                  for diagnosis of multiple bridging
                                  faults . . . . . . . . . . . . . . . . . 575--587
            W. L. Gallagher and   
        E. E. Swartzlander, Jr.   Fault-tolerant Newton--Raphson and
                                  Goldschmidt dividers using time shared
                                  TMR  . . . . . . . . . . . . . . . . . . 588--595
                I. Pomeranz and   
                    S. M. Reddy   Procedures for static compaction of test
                                  sequences for synchronous sequential
                                  circuits . . . . . . . . . . . . . . . . 596--607
               B. J. Oommen and   
                  T. D. Roberts   Continuous learning automata solutions
                                  to the capacity assignment problem . . . 608--620

IEEE Transactions on Computers
Volume 49, Number 7, July, 2000

               Israel Koren and   
                 Peter Kornerup   Guest Editors' Introduction: Special
                                  Issue on Computer Arithmetic . . . . . . 625--627
       Milo\vs D. Ercegovac and   
          Tomás Lang and   
         Jean-Michel Muller and   
               Arnaud Tisserand   Reciprocation, Square Root, Inverse
                                  Square Root, and Some Elementary
                                  Functions Using Small Multipliers  . . . 628--637
                    G. Even and   
                   P.-M. Seidel   A Comparison of Three Rounding
                                  Algorithms for IEEE Floating-Point
                                  Multiplication . . . . . . . . . . . . . 638--650
                       M. Parks   Number-Theoretic Test Generation for
                                  Directed Rounding  . . . . . . . . . . . 651--658
            Fu-Chiung Cheng and   
                S. H. Unger and   
                    M. Theobald   Self-Timed Carry-Lookahead Adders  . . . 659--672
             L. Kalampoukas and   
                 D. Nikolos and   
              C. Efstathiou and   
               H. T. Vergos and   
                J. Kalamatianos   High-Speed Parallel-Prefix Modulo $2^n -
                                  1$ Adders  . . . . . . . . . . . . . . . 673--680
              M. J. Schulte and   
              P. I. Balzola and   
                   A. Akkas and   
                  R. W. Brocato   Integer Multiplication with Overflow
                                  Detection or Saturation  . . . . . . . . 681--691
              Wen-Chang Yeh and   
                  Chein-Wei Jen   High-Speed Booth Encoded Parallel
                                  Multiplier Design  . . . . . . . . . . . 692--701
              J. N. Coleman and   
              E. I. Chester and   
              C. I. Softley and   
                      J. Kadlec   Arithmetic on the European Logarithmic
                                  Microprocessor . . . . . . . . . . . . . 702--715
             Chichyang Chen and   
               Rui-Lin Chen and   
                 Chih-Huan Yang   Pipelined Computation of Very Large
                                  Word-Length LNS Addition/Subtraction
                                  with Polynomial Hardware Cost  . . . . . 716--726
                  E. Antelo and   
                    T. Lang and   
                 J. D. Bruguera   Very-High Radix Circular CORDIC:
                                  Vectoring and Unified Rotation/Vectoring 727--739
                    M. Joye and   
                  Sung-Ming Yen   Optimal Left-to-Right Binary
                                  Signed-Digit Recoding  . . . . . . . . . 740--748
               M. Anwarul Hasan   Look-Up Table-Based Large Finite Field
                                  Multiplication in Memory Constrained
                                  Cryptosystems  . . . . . . . . . . . . . 749--758
       Milo\vs D. Ercegovac and   
             Laurent Imbert and   
            David W. Matula and   
         Jean-Michel Muller and   
                    Guoheng Wei   Improving Goldschmidt Division, Square
                                  Root, and Square Root Reciprocal . . . . 759--763
                   E. Savas and   
        Ç. K. Koç   The Montgomery Modular
                                  Inverse---Revisited  . . . . . . . . . . 763--766

IEEE Transactions on Computers
Volume 49, Number 8, August, 2000

             S. Hosseini-Khayat   On optimal replacement of nonuniform
                                  cache objects  . . . . . . . . . . . . . 769--778
                 R. R. Iyer and   
                   L. N. Bhuyan   Design and evaluation of a switch cache
                                  architecture for CC-NUMA multiprocessors 779--797
                  G. R. Gao and   
                      V. Sarkar   Location consistency --- a new memory
                                  model and cache consistency protocol . . 798--813
                T. M. Conte and   
                     S. Sathaye   Properties of rescheduling size
                                  invariance for dynamic
                                  rescheduling-based VLIW cross-generation
                                  compatibility  . . . . . . . . . . . . . 814--825
              P. Bertolazzi and   
             G. Di Battista and   
                      W. Didimo   Computing orthogonal drawings with the
                                  minimum number of bends  . . . . . . . . 826--840
                   B. Field and   
                T. F. Znati and   
                       D. Mosse   V-NET: a versatile network architecture
                                  for flexible delay guarantees in
                                  real-time networks . . . . . . . . . . . 841--858
                     C. Frougny   On-the-fly algorithms and sequential
                                  machines . . . . . . . . . . . . . . . . 859--863

IEEE Transactions on Computers
Volume 49, Number 9, September, 2000

         G. Lakshminarayana and   
             A. Raghunathan and   
                      N. K. Jha   Behavioral synthesis of fault secure
                                  controller/datapaths based on aliasing
                                  probability analysis . . . . . . . . . . 865--885
              C. Constantinescu   Teraflops supercomputer: architecture
                                  and validation of the fault tolerance
                                  mechanisms . . . . . . . . . . . . . . . 886--894
                    H. Fujiwara   A new class of sequential circuits with
                                  combinational test generation complexity 895--905
                F. Liberato and   
                  R. Melhem and   
                       D. Mosse   Tolerance to multiple transient faults
                                  for aperiodic tasks in hard real-time
                                  systems  . . . . . . . . . . . . . . . . 906--914
                    Xing Du and   
             Xiaodong Zhang and   
                    Zhichun Zhu   Memory hierarchy considerations for
                                  cost-effective cluster computing . . . . 915--933
              Chia-Lin Yang and   
                    B. Sano and   
                   A. R. Lebeck   Exploiting parallelism in geometry
                                  processing with general purpose
                                  processors and floating-point SIMD
                                  instructions . . . . . . . . . . . . . . 934--946
             Ching-Chih Han and   
                 K. G. Shin and   
                  Sang Kyun Yun   On load balancing in
                                  multicomputer/distributed systems
                                  equipped with circuit or cut-through
                                  switching capability . . . . . . . . . . 947--957
               Meng-Lai Yin and   
               D. M. Blough and   
                         L. Bic   A dependability analysis for systems
                                  with global spares . . . . . . . . . . . 958--963
                   S. Al-Bassam   Another method for constructing
                                  $t$-EC/AUED codes  . . . . . . . . . . . 964--966
              Sung-Ming Yen and   
                        M. Joye   Checking before output may not be enough
                                  against fault-based cryptanalysis  . . . 967--970
             Pao-Yuan Chang and   
              Deng-Jyi Chen and   
                     K. M. Kavl   Multimedia file allocation on VC
                                  networks using multipath routing . . . . 971--977
              Chiuyuan Chen and   
                F. K. Hwang and   
          Hsien-Sheng Hsiao and   
               Yeh-Hao Chin and   
                  Wei-Pang Yang   The minimum distance diagram of
                                  double-loop networks . . . . . . . . . . 977--979
             S. Charcranoon and   
           T. G. Robertazzi and   
                       S. Luryi   Parallel processor configuration design
                                  with processing/transmission costs . . . 987--991
                  D. K. Das and   
         U. K. Bhattacharya and   
             B. B. Bhattacharya   Isomorph-redundancy in sequential
                                  circuits . . . . . . . . . . . . . . . . 992--997
                  C. C. Fan and   
                       J. Bruck   Tolerating multiple faults in multistage
                                  interconnection networks with minimal
                                  extra stages . . . . . . . . . . . . . . 998--1004
                   Li Sheng and   
                         Jie Wu   A note on ``A tight lower bound on the
                                  number of channels required for
                                  deadlock-free wormhole routing'' . . . . 1005--1005

IEEE Transactions on Computers
Volume 49, Number 10, October, 2000

                M. Crovella and   
                   J. Duato and   
                K. Ebcioglu and   
               L. P. Gewali and   
               P. Montuschi and   
                   T. Nanya and   
                  K. Schwan and   
         A. Sivasubramaniam and   
               I. G. Tollis and   
                     U. Vishkin   Editor's note  . . . . . . . . . . . . . 1009--1012
                E. Kranakis and   
                        A. Pelc   Better adaptive diagnosis of hypercubes  1013--1020
                      K. Li and   
                         Y. Pan   Probabilistic analysis of scheduling
                                  precedence constrained parallel tasks on
                                  multicomputers with contiguous processor
                                  allocation . . . . . . . . . . . . . . . 1021--1030
           M. H. Azadmanesh and   
               R. M. Kieckhafer   Exploiting omissive faults in
                                  synchronous approximate agreement  . . . 1031--1042
               B. Balkenhol and   
                       S. Kurtz   Universal data compression based on the
                                  Burrows--Wheeler transformation: theory
                                  and practice . . . . . . . . . . . . . . 1043--1053
                    J. Zhao and   
                 S. Irrinki and   
                    M. Puri and   
                    F. Lombardi   Testing SRAM-based content addressable
                                  memories . . . . . . . . . . . . . . . . 1054--1063
                M. A. Hasan and   
                   A. G. Wassal   VLSI algorithms, architectures, and
                                  implementation of a versatile
                                  $\mathrm{GF}(2^m)$ processor . . . . . . 1064--1073
                  N. Takagi and   
                    S. Kuwahara   A VLSI algorithm for computing the
                                  Euclidean norm of a $3$D vector  . . . . 1074--1082
                M. Psarakis and   
              D. Gizopoulos and   
               A. Paschalis and   
                      Y. Zorian   Sequential fault modeling and test
                                  pattern generation for CMOS iterative
                                  logic arrays . . . . . . . . . . . . . . 1083--1099
                J. D. Golic and   
                   A. Clark and   
                      E. Dawson   Generalized inversion attack on
                                  nonlinear filter generators  . . . . . . 1100--1109
             Ching-Chih Han and   
                Chao-Ju Hou and   
               Kar Sun Tsoi and   
                          S. Ho   Dynamic establishment and termination of
                                  real-time message streams in dual-bus
                                  networks . . . . . . . . . . . . . . . . 1110--1119
            Chin-Liang Wang and   
                   Jyh-Huei Guo   New systolic arrays for $C + AB^2$,
                                  inversion, and division in
                                  $\mathrm{GF}(2^m)$ . . . . . . . . . . . 1120--1125
                       A. Kumar   An efficient SuperGrid protocol for high
                                  availability and load balancing  . . . . 1126--1133
                  Sangho Oh and   
              Chang Han Kim and   
                 Jongin Lim and   
               Dong Hyeon Cheon   Efficient normal basis multipliers in
                                  composite fields . . . . . . . . . . . . 1133--1138
                Kun-Jin Lin and   
                   Cheng-Wen Wu   A low-power CAM design for LZ data
                                  compression  . . . . . . . . . . . . . . 1139--1145
               M. Tomassini and   
                  M. Sipper and   
                   M. Perrenoud   On the generation of high-quality random
                                  numbers by two-dimensional cellular
                                  automata . . . . . . . . . . . . . . . . 1146--1151
              J. N. Coleman and   
              E. I. Chester and   
              C. I. Softley and   
                      J. Kadlec   Corrections to ``Arithmetic on the
                                  European Logarithmic Microprocessor''    1152--1152

IEEE Transactions on Computers
Volume 49, Number 11, November, 2000

                    R. Rajkumar   Guest editor's introduction: 1997 IEEE
                                  real-time technologies and applications
                                  symposium  . . . . . . . . . . . . . . . 1153--1154
               Dong-In Kang and   
                  R. Gerber and   
                     M. Saksena   Parametric design synthesis of
                                  distributed embedded systems . . . . . . 1155--1169
           T. F. Atdelzater and   
               E. M. Atkins and   
                     K. G. Shin   QoS negotiation in real-time systems and
                                  its application to automated flight
                                  control  . . . . . . . . . . . . . . . . 1170--1183
              M. Brockmeyer and   
                F. Jahanlan and   
               C. Heitmeyer and   
                      E. Winner   A flexible, extensible simulation
                                  environment for testing real-time
                                  specifications . . . . . . . . . . . . . 1184--1201
                  Chia Shen and   
                    I. Mizumuma   RT-CRM: real-time channel-based
                                  reflective memory  . . . . . . . . . . . 1202--1214
             Sung-Whan Moon and   
                 J. Rexford and   
                     K. G. Shin   Scalable hardware priority queue
                                  architectures for high-speed packet
                                  switches . . . . . . . . . . . . . . . . 1215--1227
              R. Srinivasan and   
                S. K. Gupta and   
                   M. A. Breuer   Novel test pattern generators for
                                  pseudoexhaustive testing . . . . . . . . 1228--1240
                 Te-Wei Kuo and   
                      A. K. Mok   Real-time data semantics and
                                  similarity-based concurrency control . . 1241--1254
                S. A. McKee and   
                 W. A. Wulf and   
                J. H. Aylor and   
               R. H. Klenke and   
              M. H. Salinas and   
                 S. I. Hong and   
                D. A. B. Weikle   Dynamic access ordering for streamed
                                  computations . . . . . . . . . . . . . . 1255--1271
                   R. Karri and   
                     K. Kim and   
                   M. Potkonjak   Computer aided design of fault-tolerant
                                  application specific programmable
                                  processors . . . . . . . . . . . . . . . 1272--1284
              E. V. Dubrova and   
                    J. C. Muzio   Easily testable multiple-valued logic
                                  circuits derived from Reed--Muller
                                  circuits . . . . . . . . . . . . . . . . 1285--1289
                 E. Dubrova and   
                 L. Macchiarulo   A comment on ``Graph-based algorithm for
                                  Boolean function manipulation''  . . . . 1290--1292

IEEE Transactions on Computers
Volume 49, Number 12, December, 2000

                Hyesook Lim and   
                   V. Piuri and   
        E. E. Swartzlander, Jr.   A serial-parallel architecture for
                                  two-dimensional discrete cosine and
                                  inverse discrete cosine transforms . . . 1297--1309
                  S. Olarlu and   
              M. C. Pinotti and   
                  Si Qing Zheng   An optimal hardware-algorithm for
                                  sorting using a fixed-size parallel
                                  sorting device . . . . . . . . . . . . . 1310--1324
            U. Krishnaswamy and   
                 I. D. Scherson   A framework for computer performance
                                  evaluation using benchmark sets  . . . . 1325--1338
             Tsan-Sheng Hsu and   
                  J. C. Lee and   
                D. R. Lopez and   
                    W. A. Royce   Task allocation on a network of
                                  processors . . . . . . . . . . . . . . . 1339--1353
                W. E. Cohen and   
                 D. W. Hyde and   
                    R. K. Gaede   An optical bus-based distributed dynamic
                                  barrier mechanism  . . . . . . . . . . . 1354--1365
                      S. Fujita   Neighbourhood information dissemination
                                  in the star graph  . . . . . . . . . . . 1366--1370
                Yu-Liang Wu and   
               Hongbing Fan and   
          M. Marek-Sadowska and   
                     C. K. Wong   OBDD minimization based on two-level
                                  representation of Boolean functions  . . 1371--1379
                      Anonymous   Author Index . . . . . . . . . . . . . . 1380--1384
                      Anonymous   Subject Index  . . . . . . . . . . . . . 1384--1392


IEEE Transactions on Computers
Volume 50, Number 1, January, 2001

             V. C. Hamacher and   
                     Hong Jiang   Hierarchical ring network configuration
                                  and performance modeling . . . . . . . . 1--12
               P. Montuschi and   
                        T. Lang   Boosting very-high radix division with
                                  prescaling and selection by rounding . . 13--27
                       S. Ghosh   P$^2$EDAS: asynchronous, distributed
                                  event driven simulation algorithm with
                                  inconsistent event preemption for
                                  accurate execution of VHDL descriptions
                                  on parallel processors . . . . . . . . . 28--50
             Chih-Wen Hsueh and   
                   Kwei-Jay Lin   Scheduling real-time systems with
                                  end-to-end timing constraints using the
                                  distributed pinwheel model . . . . . . . 51--66
                L. Codrescu and   
                D. S. Wills and   
                      J. Meindl   Architecture of the Atlas
                                  chip-multiprocessor: dynamically
                                  parallelizing irregular applications . . 67--82
                   B. Sunar and   
                      C. K. Koc   An efficient optimal normal basis type
                                  II multiplier  . . . . . . . . . . . . . 83--87
                 A. A. Rescigno   Optimally balanced spanning tree of the
                                  star network . . . . . . . . . . . . . . 88--91
                      Anonymous   2000 reviewers list  . . . . . . . . . . 92--95

IEEE Transactions on Computers
Volume 50, Number 2, February, 2001

             C. C. Aggarwal and   
                 J. L. Wolf and   
                       P. S. Yu   The maximum factor queue length batching
                                  scheme for video-on-demand systems . . . 97--110
                   H. Aydin and   
                  R. Melhem and   
                   D. Mosse and   
               P. Mejia-Alvarez   Optimal reward-based scheduling for
                                  periodic real-time tasks . . . . . . . . 111--130
           R. Radhakrishnan and   
           N. Vijaykrishnan and   
                 L. K. John and   
         A. Sivasubramaniam and   
                   J. Rubio and   
                J. Sabarinathan   Java runtime systems: characterization
                                  and architectural implications . . . . . 131--146
                D. Jankovic and   
            R. S. Stankovic and   
                   R. Drechsler   Decision diagram method for calculation
                                  of pruned Walsh transform  . . . . . . . 147--157
              E. E. Johnson and   
                  Jiheng Ha and   
                 M. Baqar Zaidi   Lossless trace compression . . . . . . . 158--173
                G. D. Cohen and   
                 L. Honkala and   
                    A. Lobstein   On codes identifying vertices in the
                                  two-dimensional square lattice with
                                  diagonals  . . . . . . . . . . . . . . . 174--176
                P. Dasgupta and   
           S. Chattopadhyay and   
            P. P. Chaudhuri and   
                    I. Sengupta   Cellular automata-based recursive
                                  pseudoexhaustive test pattern generator  177--185
                 S. Koppolu and   
                  A. Chatterjee   Hierarchical diagnosis of identical
                                  units in a system  . . . . . . . . . . . 186--191

IEEE Transactions on Computers
Volume 50, Number 3, March, 2001

                  M. J. Atallah   On estimating the large entries of a
                                  convolution  . . . . . . . . . . . . . . 193--196
             Hung-Ying Tyan and   
                  J. C. Hou and   
                   Bin Wang and   
                 Ching-Chih Han   On supporting temporal quality of
                                  service in WDMA-based star-coupled
                                  optical networks . . . . . . . . . . . . 197--214
                Junhyung Um and   
                    Taewhan Kim   An optimal allocation of
                                  carry-save-adders in arithmetic circuits 215--233
                   J. Llosa and   
                 E. Ayguade and   
                A. Gonzalez and   
                  M. Valero and   
                    J. Eckhardt   Lifetime-sensitive modulo scheduling in
                                  a production environment . . . . . . . . 234--249
                  S. Haynal and   
                      F. Brewer   Automata-based symbolic scheduling for
                                  looping DFGs . . . . . . . . . . . . . . 250--267
               V. V. Zyuban and   
                    P. M. Kogge   Inherently lower-power high-performance
                                  superscalar architectures  . . . . . . . 268--285

IEEE Transactions on Computers
Volume 50, Number 4, April, 2001

               K. M. Wilson and   
                    K. Olukotun   High bandwidth on-chip cache design  . . 292--307
                  G. Bernat and   
                   A. Burns and   
                     A. Liamosi   Weakly hard real-time systems  . . . . . 308--321
                   W. T. Ng and   
                     P. M. Chen   The design and verification of the Rio
                                  file cache . . . . . . . . . . . . . . . 322--337
                 G. Reinman and   
                  B. Calder and   
                      T. Austin   Optimizations enabled by a decoupled
                                  front-end architecture . . . . . . . . . 338--355
                    Yi-Bing Lin   Eliminating overflow for large-scale
                                  mobility databases in cellular telephone
                                  networks . . . . . . . . . . . . . . . . 356--370
              Hee Yong Youn and   
              Choong Gun Oh and   
             Hyunseung Choo and   
             Jin-Wook Chung and   
                    Dongman Lee   An efficient algorithm-based fault
                                  tolerance design using the weighted
                                  data-check relationship  . . . . . . . . 371--383

IEEE Transactions on Computers
Volume 50, Number 5, May, 2001

              Chiou-Yng Lee and   
                Erl-Huei Lu and   
                   Jau-Yien Lee   Bit-parallel systolic multipliers for
                                  $\mathrm{GF}(2^m)$ fields defined by
                                  all-one and equally spaced polynomials   385--393
                  N. Takagi and   
                 J. Yoshiki and   
                      K. Takagi   A fast algorithm for multiplicative
                                  inversion in $\mathrm{GF}(2^m)$ using
                                  normal basis . . . . . . . . . . . . . . 394--398
                 S. Mahevas and   
                      G. Rubino   Bound computation of dependability and
                                  performance measures . . . . . . . . . . 399--413
             Ching-Chih Han and   
                 K. G. Shin and   
                    Chao-Ju Hou   Synchronous bandwidth allocation for
                                  real-time communications with the
                                  timed-token MAC protocol . . . . . . . . 414--431
                  E. Pastor and   
              J. Cortadella and   
                        O. Roig   Symbolic analysis of bounded Petri nets  432--448
                  A. Antola and   
                F. Ferrandi and   
                   V. Piuri and   
                        M. Sami   Semiconcurrent error detection in data
                                  paths  . . . . . . . . . . . . . . . . . 449--465
                    A. Shum and   
        P. M. Melliar-Smith and   
                    L. E. Moser   Design and evaluation of the Fibonacci
                                  optical ATM switch . . . . . . . . . . . 466--481
                   B. Jacob and   
                       T. Mudge   Uniprocessor virtual memory without TLBs 482--499
               Yu-Liang Liu and   
                Yue-Li Wang and   
                     D. J. Guan   An optimal fault-tolerant routing
                                  algorithm for double-loop networks . . . 500--505
                 O. Ercetin and   
                   L. Tassiulas   Push-based information delivery in two
                                  stage satellite-terrestrial wireless
                                  systems  . . . . . . . . . . . . . . . . 506--518
                   Keqin Li and   
                      V. Y. Pan   Parallel matrix multiplication on a
                                  linear array with a reconfigurable
                                  pipelined bus system . . . . . . . . . . 519--525
              Kyunghee Choi and   
                    Gihyun Jung   Comment on ``On-line scheduling policies
                                  for a class of IRIS real-time tasks''    526--528

IEEE Transactions on Computers
Volume 50, Number 6, June, 2001

                    Wei Hsu and   
                        V. Bala   Guest Editors' introduction  . . . . . . 527--528
                K. Ebcioglu and   
                  E. Altman and   
                M. Gschwind and   
                     S. Sathaye   Dynamic binary translation and
                                  optimization . . . . . . . . . . . . . . 529--548
                 T. Kistler and   
                       M. Franz   Continuous program optimization: Design
                                  and evaluation . . . . . . . . . . . . . 549--566
               M. C. Merten and   
                A. R. Trick and   
               R. D. Barnes and   
              E. M. Nystrom and   
               C. N. George and   
           J. C. Gyllenhaal and   
                   W.-M. W. Hwu   An architectural framework for runtime
                                  optimization . . . . . . . . . . . . . . 567--589
                S. J. Patel and   
                  S. S. Lumetta   rePLay: a hardware framework for dynamic
                                  optimization . . . . . . . . . . . . . . 590--608
              K. Karagianni and   
               V. Paliouras and   
             G. Diamantakos and   
                  T. Stouraitis   Operation-saving VLSI architectures for
                                  $3$D geometrical transformations . . . . 609--622

IEEE Transactions on Computers
Volume 50, Number 7, July, 2001

            H. Sarbazi-Azad and   
             M. Ould-Khaoua and   
                L. M. Mackenzie   Analytical modeling of wormhole-routed
                                  $k$-ary $n$-cubes in the presence of
                                  hot-spot traffic . . . . . . . . . . . . 623--634
             Chih-Fang Wang and   
                       S. Sahni   Matrix multiplication on the OTIS-Mesh
                                  optoelectronic computer  . . . . . . . . 635--646
                D. R. Kumar and   
               W. A. Najjar and   
                  P. K. Srimani   A new adaptive hardware tree-based
                                  multicast routing in $k$-ary $n$-cubes   647--659
                Tei-Wei Kuo and   
           Ming-Chung Liang and   
                   LihChyun Shu   Abort-oriented concurrency control for
                                  real-time databases  . . . . . . . . . . 660--673
               N. Mukherjee and   
                  J. Rajski and   
                      J. Tyszer   Testing schemes for FIR filter
                                  structures . . . . . . . . . . . . . . . 674--688
               N. Bianchini and   
                 S. Fanelli and   
                        M. Gori   Optimal algorithms for well-conditioned
                                  nonlinear systems of equations . . . . . 689--698
                 Yibei Ling and   
                     Jie Mi and   
                     Xiaola Lin   A variational calculus approach to
                                  optimal checkpoint placement . . . . . . 699--708
               Sangyeun Cho and   
              Pen-Chung Yew and   
                    Gyungho Lee   A high-bandwidth memory pipeline for
                                  wide issue processors  . . . . . . . . . 709--723
                    J. F. Meyer   Performability of an algorithm for
                                  connection admission control . . . . . . 724--733
                 Tong Zhang and   
                    K. K. Parhi   Systematic design of original and
                                  modified Mastrovito multipliers for
                                  general irreducible polynomials  . . . . 734--749
                    Lu Ruan and   
                 Dingzhu Du and   
                Xiaodong Hu and   
                Xiaohua Jia and   
                  Deying Li and   
                      Zheng Sun   Converter placement supporting broadcast
                                  in WDM optical networks  . . . . . . . . 750--758
                    T. Blum and   
                        C. Paar   High-radix Montgomery modular
                                  exponentiation on reconfigurable
                                  hardware . . . . . . . . . . . . . . . . 759--764
                      Anonymous   Correction to Editor's note  . . . . . . 765--765

IEEE Transactions on Computers
Volume 50, Number 8, August, 2001

               A. R. Hurson and   
                    B. Childers   Message from the Guest Editors . . . . . 767--768
                G. S. Tyson and   
             M. Smelyanskiy and   
                 E. S. Davidson   Evaluating the use of register queues in
                                  software pipelined loops . . . . . . . . 769--783
               W. M. Meleis and   
         A. E. Eichenberger and   
                     I. D. Baev   Scheduling superblocks with bound-based
                                  branch trade-offs  . . . . . . . . . . . 784--797
                M. Kandemir and   
                   J. Ramanujam   Data relation vectors: a new abstraction
                                  for data optimizations . . . . . . . . . 798--810
                Sangman Moh and   
                  Chansu Yu and   
                     B. Lee and   
              Hee Yong Youn and   
                Dongsoo Han and   
                    Dongman Lee   Four-ary tree-based barrier
                                  synchronization for $2$D meshes without
                                  nonmember involvement  . . . . . . . . . 811--823
                 Jaejin Lee and   
                    D. A. Padua   Hiding relaxed memory consistency with a
                                  compiler . . . . . . . . . . . . . . . . 824--833
                 K. M. Kavi and   
                  R. Giorgi and   
                        J. Arul   Scheduled dataflow: execution paradigm,
                                  architecture, and performance evaluation 834--846
             Sang-Jeong Lee and   
                  Pen-Chung Yew   On table bandwidth and its update delay
                                  for value prediction on wide-issue ILP
                                  processors . . . . . . . . . . . . . . . 847--852
                   L. Lopes and   
          V. T. Vasconcelos and   
                       F. Silva   Fine-grained multithreading with process
                                  calculi  . . . . . . . . . . . . . . . . 852--862

IEEE Transactions on Computers
Volume 50, Number 9, September, 2001

                     J. Gaudiot   Editor's note  . . . . . . . . . . . . . 863--864
                  L. Schwiebert   Deadlock-free oblivious wormhole routing
                                  with cyclic dependencies . . . . . . . . 865--876
                   Gang Han and   
               R. H. Klenke and   
                    J. H. Aylor   Performance modeling of hierarchical
                                  crossbar-based multicomputer systems . . 877--890
                B. D. Brown and   
                     H. C. Card   Stochastic neural computation. I.
                                  Computational elements . . . . . . . . . 891--905
                B. D. Brown and   
                     H. C. Card   Stochastic neural computation. II. Soft
                                  competitive learning . . . . . . . . . . 906--920
                     Tao Li and   
                     L. K. John   ADir$_p$NB: a cost-effective way to
                                  implement full map directory-based cache
                                  coherence protocols  . . . . . . . . . . 921--934
                   T. Sasao and   
                   J. T. Butler   Worst and best irredundant
                                  sum-of-products expressions  . . . . . . 935--948
                K. H. Yeung and   
                      T. S. Yum   Dynamic multiple parity (DMP) disk array
                                  for serial transaction processing  . . . 949--959
             Sun-Yuan Hsieh and   
              Gen-Huey Chen and   
                    Chin-Wen Ho   Longest fault-free paths in star graphs
                                  with edge faults . . . . . . . . . . . . 960--971
                  J. Kiniwa and   
                  T. Hamada and   
                   D. Mizoguchi   Lookahead scheduling requests for
                                  multisize page caching . . . . . . . . . 972--983
              A. Bernasconi and   
               B. Codenottl and   
                J. M. Vanderkam   A characterization of bent functions in
                                  terms of strongly regular graphs . . . . 984--985
                Sungwook Yu and   
        E. E. Swartzlander, Jr.   DCT implementation with distributed
                                  arithmetic . . . . . . . . . . . . . . . 985--991
             Chiu-Sing Choy and   
                   J. Butas and   
               J. Povazanic and   
                Cheong-Fat Chan   A new control circuit for asynchronous
                                  micropipelines . . . . . . . . . . . . . 992--997
                     C. Liu and   
                 W.-B. Gong and   
                  C. M. Krishna   Rational interpolation examples in
                                  performance analysis . . . . . . . . . . 997--1003

IEEE Transactions on Computers
Volume 50, Number 10, October, 2001

                K. Sasidhar and   
              A. Chatterjee and   
                      Y. Zorian   Boundary scan-based relay wave
                                  propagation test of arrays of identical
                                  structures . . . . . . . . . . . . . . . 1007--1019
              Yuanyuan Yang and   
                  Jianchao Wang   Pipelined all-to-all broadcast in
                                  all-port meshes and tori . . . . . . . . 1020--1032
                   D. Lopez and   
                   J. Llosa and   
                  M. Valero and   
                     E. Ayguade   Cost-conscious strategies to increase
                                  performance of numerical programs on
                                  aggressive VLIW architectures  . . . . . 1033--1051
                O. Beaumont and   
                  V. Boudet and   
                 A. Petitet and   
                F. Rastello and   
                      Y. Robert   A proposal for a heterogeneous cluster
                                  ScaLAPACK (dense linear solvers) . . . . 1052--1070
                    M. A. Hasan   Power analysis attacks and algorithmic
                                  approaches to their countermeasures for
                                  Koblitz curve cryptosystems  . . . . . . 1071--1083
            J.-M. Parcerisa and   
                    A. Gonzalez   Improving latency tolerance of
                                  multithreading through decoupling  . . . 1084--1094
                  S. Chessa and   
                   P. Maestrini   Correct and almost complete diagnosis of
                                  processor grids  . . . . . . . . . . . . 1095--1102

IEEE Transactions on Computers
Volume 50, Number 11, November, 2001

              H. Hadimioglu and   
                   D. Kaeli and   
                    F. Lombardi   Introduction to the special section on
                                  high performance memory systems  . . . . 1103--1104
                   M. V. Wilkes   High performance memory systems  . . . . 1105--1105
           C. D. Benveniste and   
            P. A. Franaszek and   
                 J. T. Robinson   Cache-memory interfaces in compressed
                                  memory systems . . . . . . . . . . . . . 1106--1116
                Lixin Zhang and   
                  Zhen Fang and   
                  M. Parker and   
               B. K. Mathew and   
              L. Schaelicke and   
               J. B. Carter and   
                W. C. Hsieh and   
                    S. A. McKee   The Impulse memory controller  . . . . . 1117--1132
                   V. Cuppu and   
                   B. Jacob and   
                   B. Davis and   
                       T. Mudge   High-performance DRAMs in workstation
                                  environments . . . . . . . . . . . . . . 1133--1153
                 V. Delaluz and   
                M. Kandemir and   
           N. Vijaykrishnan and   
         A. Sivasubramaniam and   
                    M. J. Irwin   Hardware and software techniques for
                                  controlling DRAM power modes . . . . . . 1154--1173
                K. M. Lepak and   
                 G. B. Bell and   
                  M. H. Lipasti   Silent stores and store value locality   1174--1190
                    Rui Min and   
                      Yiming Hu   Improving performance of large
                                  physically indexed caches by decoupling
                                  memory addresses from cache addresses    1191--1201
                Wei-Fen Lin and   
            S. K. Reinhardt and   
                      D. Burger   Designing a modern memory hierarchy with
                                  hardware prefetching . . . . . . . . . . 1202--1218
                   B. Abali and   
               Xiaowei Shen and   
                  H. Franke and   
                 D. E. Poff and   
                    T. B. Smith   Hardware compressed main memory:
                                  operating system support and performance
                                  evaluation . . . . . . . . . . . . . . . 1219--1233
                   R. Barua and   
                     W. Lee and   
            S. Arnarasinghe and   
                     A. Agarwal   Compiler support for scalable and
                                  efficient memory systems . . . . . . . . 1234--1247
                Yan Solihin and   
                 Jaejin Lee and   
                   J. Torrellas   Automatic code mapping on an intelligent
                                  memory architecture  . . . . . . . . . . 1248--1266
               D. S. Phatak and   
                    T. Goff and   
                       I. Koren   Constant-time addition and simultaneous
                                  format conversion based on redundant
                                  binary representations . . . . . . . . . 1267--1278
                    A. Cuyt and   
                    R. B. Lenin   Multivariate rational approximants for
                                  multiclass closed queuing networks . . . 1279--1288
                    J. Jain and   
                 I. Wegener and   
                      M. Fujita   A note on complexity of OBDD composition
                                  and efficiency of partitioned-OBDDs over
                                  OBDDs  . . . . . . . . . . . . . . . . . 1289--1290
                Mao-Hsu Yen and   
               Sao-Jie Chen and   
                      S. H. Lan   A three-stage one-sided rearrangeable
                                  polygonal switching network  . . . . . . 1291--1294

IEEE Transactions on Computers
Volume 50, Number 12, December, 2001

                  Y. A. Liu and   
                       G. Gomez   Automatic accurate cost-bound analysis
                                  for high-level languages . . . . . . . . 1295--1309
                 Minsoo Ryu and   
              Jungkeun Park and   
                  Seongsoo Hong   Timing constraint remapping to achieve
                                  time equi-continuity in distributed
                                  real-time systems  . . . . . . . . . . . 1310--1320
                M. Kandemir and   
               J. Ramanujam and   
               A. Choudhary and   
                    P. Banerjee   A layout-conscious iteration space
                                  transformation technique . . . . . . . . 1321--1335
                    I. Mura and   
                  A. Bondavalli   Markov regenerative stochastic Petri
                                  nets to model and evaluate phased
                                  mission systems dependability  . . . . . 1337--1351
                Donghee Lee and   
               Jongmoo Choi and   
               Jong-Hun Kim and   
                  S. H. Noh and   
              Sang Lyul Min and   
                 Yookun Cho and   
                 Chong Sang Kim   LRFU: a spectrum of policies that
                                  subsumes the least recently used and
                                  least frequently used policies . . . . . 1352--1361
                J. Gonzalez and   
                    A. Gonzalez   Control-flow speculation through value
                                  prediction . . . . . . . . . . . . . . . 1362--1376
                      Anonymous   Author Index . . . . . . . . . . . . . . 1377--1380
                      Anonymous   Subject Index  . . . . . . . . . . . . . 1380--1388


IEEE Transactions on Computers
Volume 51, Number 1, January, 2002

                      Anonymous   Editor's Note  . . . . . . . . . . . . . 1--2
              L. M. Kaufman and   
              B. W. Johnson and   
                    J. B. Dugan   Coverage estimation using statistics of
                                  the extremes for when testing reveals no
                                  failures . . . . . . . . . . . . . . . . 3--12
                   Wei Chen and   
                   S. Toueg and   
                 M. K. Aguilera   On the quality of service of failure
                                  detectors  . . . . . . . . . . . . . . . 13--32
              Cheng-Nan Lai and   
              Gen-Huey Chen and   
                   Dyi-Rong Duh   Constructing one-to-many disjoint paths
                                  in folded hypercubes . . . . . . . . . . 33--45
                  B. S. Yoo and   
                      C. R. Das   A fast and efficient processor
                                  allocation scheme for mesh-connected
                                  multicomputers . . . . . . . . . . . . . 46--60
                  Farn Wang and   
                 Pao-Ann Hsiung   Efficient and user-friendly verification 61--83
                   A. A. Hiasat   High-speed and reduced-area modular
                                  adder structures for RNS . . . . . . . . 84--89
              Chang Han Kim and   
                  Sangho Oh and   
                     Jongin Lim   A new hardware architecture for
                                  operations in $\mathrm{GF}(2^n)$ . . . . 90--92
               Hongbing Fan and   
                Yu-Liang Wu and   
                  Yao-Wen Chang   Comment on ``Generic universal switch
                                  blocks'' . . . . . . . . . . . . . . . . 93--95

IEEE Transactions on Computers
Volume 51, Number 2, February, 2002

                 D. Avresky and   
              B. W. Johnson and   
                    F. Lombardi   Guest Editors' introduction  . . . . . . 97--99
             D. Oppenheimer and   
                   A. Brown and   
                    J. Beck and   
                 D. Hettena and   
                  J. Kuroda and   
                N. Treuhaft and   
            D. A. Patterson and   
                      K. Yelick   ROC-1: hardware support for
                                  recovery-oriented computing  . . . . . . 100--107
               R. A. Maxion and   
                   K. M. C. Tan   Anomaly detection in embedded systems    108--120
                  A. T. Tai and   
                  K. S. Tso and   
                 L. Alkalai and   
                 S. N. Chau and   
                  W. H. Sanders   Low-cost error containment and recovery
                                  for onboard guarded software upgrading
                                  and beyond . . . . . . . . . . . . . . . 121--137
                   J. Arlat and   
                J.-C. Fabre and   
                   M. Rodriguez   Dependability of COTS microkernel-based
                                  systems  . . . . . . . . . . . . . . . . 138--163
                      J. Xu and   
                 B. Randell and   
              A. Romanovsky and   
               R. J. Stroud and   
                A. F. Zorzo and   
                  E. Canver and   
                   F. von Henke   Rigorous development of an embedded
                                  fault-tolerant system based on
                                  coordinated atomic actions . . . . . . . 164--179
                      N. Oh and   
                   S. Mitra and   
                E. J. McCluskey   ED$^4$I: error detection by diverse data
                                  and duplicated instructions  . . . . . . 180--199
                F. Ferrandi and   
                   F. Fummi and   
                      D. Sciuto   Test generation and testability
                                  alternatives exploration of critical
                                  algorithms for embedded applications . . 200--215
                     D. Lee and   
                  M. Yannakakis   Closed partition lattice and machine
                                  decomposition  . . . . . . . . . . . . . 216--228
                 S. J. Piestrak   Design method of a class of embedded
                                  combinational self-testing checkers for
                                  two-rail codes . . . . . . . . . . . . . 229--234
                  A. Steininger   Identifying efficient combinations of
                                  error detection mechanisms based on
                                  results of fault injection experiments   235--239

IEEE Transactions on Computers
Volume 51, Number 3, March, 2002

                  Jien-Chung Lo   Analysis of a BICS-only concurrent error
                                  detection method . . . . . . . . . . . . 241--253
                 J. A. Carrasco   Computationally efficient and
                                  numerically stable reliability bounds
                                  for repairable fault-tolerant systems    254--268
                V. Kanitkar and   
                       A. Delis   Real-time processing in client-server
                                  databases  . . . . . . . . . . . . . . . 269--288
             G. C. Buttazzo and   
                  G. Lipari and   
                 M. Caccamo and   
                       L. Abeni   Elastic scheduling for flexible workload
                                  management . . . . . . . . . . . . . . . 289--302
                   A. Cohen and   
                       R. Cohen   A dynamic approach for efficient TCP
                                  buffer allocation  . . . . . . . . . . . 303--312
                A. Moshovos and   
                     G. S. Sohi   Reducing memory latency via
                                  read-after-read memory dependence
                                  prediction . . . . . . . . . . . . . . . 313--326
              Chun-Yuan Lin and   
              Jen-Shiuh Liu and   
                Yeh-Ching Chung   Efficient representation scheme for
                                  multidimensional array operations  . . . 327--345
                    M. Elia and   
                       M. Leone   On the inherent space complexity of fast
                                  parallel multipliers for
                                  $\mathrm{GF}(2^m)$ . . . . . . . . . . . 346--351

IEEE Transactions on Computers
Volume 51, Number 4, April, 2002

               L. Golubchik and   
                   J. C. S. Lui   Bounding of performance measures for
                                  threshold-based queuing systems: theory
                                  and application to dynamic resource
                                  management in video-on-demand servers    353--372
                 Wen-Guey Tzeng   A secure fault-tolerant conference-key
                                  agreement protocol . . . . . . . . . . . 373--379
            V. Krishnaswamy and   
                 G. Hasteer and   
                    P. Banerjee   Automatic parallelization of compiled
                                  event driven VHDL simulation . . . . . . 380--394
                  M. Hurfin and   
              A. Mostefaoui and   
                      M. Raynal   A versatile family of consensus
                                  protocols based on Chandra--Toueg's
                                  unreliable failure detectors . . . . . . 395--408
                I. Pomeranz and   
                    S. M. Reddy   Built-in test sequence generation for
                                  synchronous sequential circuits based on
                                  loading and expansion of input sequences
                                  using single and multiple fault
                                  detection times  . . . . . . . . . . . . 409--419
                 Jinwoo Suh and   
                 V. K. Prasanna   An efficient algorithm for out-of-core
                                  matrix transposition . . . . . . . . . . 420--438
                 H. Cancela and   
                 M. E. Urquhart   Adapting RVR simulation techniques for
                                  residual connectedness network
                                  reliability models . . . . . . . . . . . 439--443
               Chan-Ik Park and   
                 Tae-Young Choe   An optimal scheduling algorithm based on
                                  task duplication . . . . . . . . . . . . 444--448

IEEE Transactions on Computers
Volume 51, Number 5, May, 2002

                 V. Iyengar and   
                 K. Chakrabarty   Test bus sizing for system-on-a-chip . . 449--459
                S. Hamdioui and   
              A. J. van de Goor   Efficient tests for realistic faults in
                                  dual-port SRAMs  . . . . . . . . . . . . 460--473
               Shin-ichi Minato   Streaming BDD manipulation . . . . . . . 474--485
            T. J. Yamaguchi and   
                Dong Sam Ha and   
                  M. Ishida and   
                        T. Ohmi   A method for compressing test data based
                                  on Burrows--Wheeler transformation . . . 486--497
                   S. Mitra and   
               N. R. Saxena and   
                E. J. McCluskey   A design diversity metric and analysis
                                  of redundant systems . . . . . . . . . . 498--510
         A. Reyhani-Masoleh and   
                    M. A. Hasan   A new construction of Massey--Omura
                                  parallel multiplier over
                                  $\mathrm{GF}(2^m)$ . . . . . . . . . . . 511--520
                     Huapeng Wu   Montgomery multiplier and squarer for a
                                  class of finite fields . . . . . . . . . 521--529
                Jianer Chen and   
                Guojun Wang and   
                  Songqiao Chen   Locally subcube-connected hypercube
                                  networks: theoretical analysis and
                                  experimental results . . . . . . . . . . 530--540
            T. S. Messerges and   
              E. A. Dabbish and   
                    R. H. Sloan   Examining smart-card security under the
                                  threat of power analysis attacks . . . . 541--552
                       Li Zhang   Fault-tolerant meshes with small degree  553--560
                   Wei Chen and   
                  Sam Toueg and   
                 M. K. Aguilera   On the quality of service of failure
                                  detectors  . . . . . . . . . . . . . . . 561--580
              Chor Ping Low and   
                    Xueyan Song   On finding feasible solutions for the
                                  delay constrained group multicast
                                  routing problem  . . . . . . . . . . . . 581--588
                    D. Gollmann   Equally spaced polynomials, dual bases,
                                  and multiplication in $F(2^n)$ . . . . . 588--591

IEEE Transactions on Computers
Volume 51, Number 6, June, 2002

                   M. Conti and   
                   M. Kumar and   
                  S. K. Das and   
                  B. A. Shirazi   Quality of service issues in Internet
                                  Web services . . . . . . . . . . . . . . 593--594
                Xueyan Tang and   
                  S. T. Chanson   Coordinated en-route Web caching . . . . 595--607
                    Guohong Cao   Proactive power-aware cache management
                                  for mobile computing systems . . . . . . 608--621
             J. Kangasharju and   
                F. Hartanto and   
               M. Reisslein and   
                     K. W. Ross   Distributing layered encoded video
                                  through caches . . . . . . . . . . . . . 622--636
                  G. Pierre and   
               M. van Steen and   
                A. S. Tanenbaum   Dynamically selecting optimal
                                  distribution strategies for Web
                                  documents  . . . . . . . . . . . . . . . 637--651
                   M. Bhide and   
                P. Deolasee and   
                  A. Katkar and   
              A. Panchbudhe and   
             K. Ramamritham and   
                      P. Shenoy   Adaptive push-pull: disseminating
                                  dynamic Web data . . . . . . . . . . . . 652--668
              L. Cherkasova and   
                       P. Phaal   Session-based admission control: a
                                  mechanism for peak load management of
                                  commercial Web sites . . . . . . . . . . 669--685
                     Nan Ni and   
                   L. N. Bhuyan   Fair scheduling in Internet routers  . . 686--701
                  Yijie Han and   
                     Yi Pan and   
                      Hong Shen   Sublogarithmic deterministic selection
                                  on arrays with a reconfigurable optical
                                  bus  . . . . . . . . . . . . . . . . . . 702--707
                Tei-Wei Kuo and   
               Wang-Ru Yang and   
                   Kwei-Jay Lin   A class of rate-based real-time
                                  scheduling algorithms  . . . . . . . . . 708--720
                N. Nicolici and   
               B. M. Al-Hashimi   Multiple scan chains for power
                                  minimization during test application in
                                  sequential circuits  . . . . . . . . . . 721--734
                 S. J. Piestrak   Comments on ``Novel totally
                                  self-checking Berger checker designs
                                  based on generalized Berger code
                                  partitioning'' . . . . . . . . . . . . . 735--736

IEEE Transactions on Computers
Volume 51, Number 7, July, 2002

                  J.-L. Gaudiot   Editor's note  . . . . . . . . . . . . . 737--739
                      C. Alippi   Randomized algorithms: a system-level,
                                  poly-time analysis of robust computation 740--749
                     Huapeng Wu   Bit-parallel finite field multiplier and
                                  squarer using polynomial basis . . . . . 750--758
               M. Burtscher and   
                     B. G. Zorn   Hybrid load-value predictors . . . . . . 759--774
            Hsien-Ming Tsai and   
                    Yi-Bing Lin   Modeling wireless local loop with
                                  general call holding times and finite
                                  number of subscribers  . . . . . . . . . 775--786
               F. J. Monaco and   
                     A. Gonzaga   Remote device command and resource
                                  sharing over the Internet: a new
                                  approach based on a distributed layered
                                  architecture . . . . . . . . . . . . . . 787--792
               Jongmoo Choi and   
                  S. H. Noh and   
              Sang Lyul Min and   
                Eun-Yong Ha and   
                     Yookun Cho   Design, implementation, and performance
                                  evaluation of a detection-based adaptive
                                  block replacement scheme . . . . . . . . 793--800
              S. Hellebrand and   
           H.-J. Wunderlich and   
              A. A. Ivaniuk and   
              Y. V. Klimets and   
                 V. N. Yarmolik   Efficient online and offline testing of
                                  embedded DRAMs . . . . . . . . . . . . . 801--809
                      N. Ye and   
                S. M. Emran and   
                    Q. Chen and   
                     S. Vilbert   Multivariate statistical analysis of
                                  audit trails for host-based intrusion
                                  detection  . . . . . . . . . . . . . . . 810--820
               V. C. S. Lee and   
                Kwok-wa Lam and   
                Sheung-Lun Hung   Concurrency control for mixed
                                  transactions in real-time databases  . . 821--834
                 M. Caccamo and   
                G. Buttazzo and   
                        Lui Sha   Handling execution overruns in hard
                                  real-time control systems  . . . . . . . 835--849
                  A. Caruso and   
                  S. Chessa and   
               P. Maestrini and   
                       P. Santi   Evaluation of a diagnosis algorithm for
                                  regular structures . . . . . . . . . . . 850--865
                I. Pomeranz and   
                    S. M. Reddy   Enumeration of test sequences in
                                  increasing chronological order to
                                  improve the levels of compaction
                                  achieved by vector omission  . . . . . . 866--872
              Yu-Chee Tseng and   
               Hsiang-Kuang Pan   Data hiding in $2$-color images  . . . . 873--878

IEEE Transactions on Computers
Volume 51, Number 8, August, 2002

               E. D. Jensen and   
                   B. Ravindran   Guest editors' introduction to special
                                  section on asynchronous real-time
                                  distributed systems  . . . . . . . . . . 881--882
                  S. Mishra and   
                  C. Fetzer and   
                    F. Cristian   The timewheel group communication system 883--899
                   Yun Wang and   
                E. Anceaume and   
              F. Brasileiro and   
                   F. Greve and   
                      M. Hurfin   Solving the group priority inversion
                                  problem in a timed asynchronous system   900--915
               P. Verissimo and   
                    A. Casimiro   The timely computing base model and
                                  architecture . . . . . . . . . . . . . . 916--930
              J.-F. Hermant and   
                     G. Le Lann   Fast asynchronous uniform consensus in
                                  real-time distributed systems  . . . . . 931--944
                  T. Hegazy and   
                   B. Ravindran   Using application benefit for proactive
                                  resource allocation in asynchronous
                                  real-time distributed systems  . . . . . 945--962
              B. M. Maziarz and   
                     V. K. Jain   Automatic reconfiguration and yield of
                                  the TESH multicomputer network . . . . . 963--972
                E. Al-Daoud and   
                  R. Mahmod and   
                 M. Rushdan and   
                    A. Kilicman   A new addition formula for elliptic
                                  curves over $\mathrm{GF}(2^n)$ . . . . . 972--975

IEEE Transactions on Computers
Volume 51, Number 9, September, 2002

                 Suhyun Kim and   
              Soo-Mook Moon and   
                Jinpyo Park and   
                    K. Ebcioglu   Unroll-based copy elimination for
                                  enhanced pipeline scheduling . . . . . . 977--994
                  Yuanyuan Yang   A new conference network for group
                                  communication  . . . . . . . . . . . . . 995--1010
                 L. Lenzini and   
                E. Mingozzi and   
                        G. Stea   A unifying service discipline for
                                  providing rate-based guaranteed and fair
                                  queuing services based on the Timed
                                  Token protocol . . . . . . . . . . . . . 1011--1025
                 E. Jovanov and   
             V. Milutinovic and   
                   A. R. Hurson   Acceleration of nonnumeric operations
                                  using hardware support for the Ordered
                                  Table Hashing algorithms . . . . . . . . 1026--1040
                Linguo Gong and   
                Xian-He Sun and   
                   E. F. Watson   Performance modeling and prediction of
                                  nondedicated network computing . . . . . 1041--1055
                   Jun Wang and   
                    Rui Min and   
                 Yingwu Zhu and   
                      Yiming Hu   UCFS --- a novel User-space, high
                                  performance, Customized File System for
                                  Web proxy servers  . . . . . . . . . . . 1056--1073
             Sang-Jeong Lee and   
                  Pen-Chung Yew   On augmenting trace cache for
                                  high-bandwidth value prediction  . . . . 1074--1088
                     Jun Xu and   
                     M. Singhal   Cost-effective flow table designs for
                                  high-speed routers: architecture and
                                  performance evaluation . . . . . . . . . 1089--1099
                   Z. Zilic and   
                 Z. G. Vranesic   A deterministic multivariate
                                  interpolation algorithm for small finite
                                  fields . . . . . . . . . . . . . . . . . 1100--1105
                    K. Paul and   
            D. R. Choudhury and   
                P. P. Chaudhuri   Theory of Extended Linear Machines . . . 1106--1110
              R. M. Hierons and   
                        H. Ural   Reduced length checking sequences  . . . 1111--1117
               Guoliang Xue and   
                K. Thulasiraman   Computing the shortest network under a
                                  fixed topology . . . . . . . . . . . . . 1117--1120

IEEE Transactions on Computers
Volume 51, Number 10, October, 2002

              P. K. Srimani and   
             Wang-Chien Lee and   
                 S. K. S. Gupta   Guest editorial: special section on data
                                  management systems and mobile computing  1121--1123
               S. Prabhakar and   
                   Yuni Xia and   
          D. V. Kalashnikov and   
                 W. G. Aref and   
                S. E. Hambrusch   Query indexing and velocity constrained
                                  indexing: scalable techniques for
                                  continuous queries on moving objects . . 1124--1140
               Baihua Zheng and   
               Jianliang Xu and   
                      D. L. Lee   Cache invalidation and replacement
                                  strategies for location-dependent data
                                  in mobile environments . . . . . . . . . 1141--1153
                Yi-Bing Lin and   
             Hsu-Yung Cheng and   
             Ya-Hsing Cheng and   
                     P. Agrawal   Implementing automatic location update
                                  for follow-me database using VoIP and
                                  Bluetooth technologies . . . . . . . . . 1154--1168
                   Yuguang Fang   General modeling and performance
                                  analysis for location management in
                                  wireless mobile networks . . . . . . . . 1169--1181
             Chang-Hung Lee and   
                 Ming-Syan Chen   Processing distributed mobile queries
                                  with interleaved remote mobile joins . . 1182--1195
               V. C. S. Lee and   
                Kwok-Wa Lam and   
                  S. H. Son and   
                  E. Y. M. Chan   On transaction processing with partial
                                  validation and timestamp ordering in
                                  mobile broadcast environments  . . . . . 1196--1211
                   V. Kumar and   
                  N. Prabhu and   
               M. H. Dunham and   
                   A. Y. Seydim   TCOT --- a timeout-based mobile
                                  transaction commitment protocol  . . . . 1212--1218
         C. Pedregal-Martin and   
                 K. Ramamritham   Support for recovery in mobile systems   1219--1224
                 E. Pitoura and   
              P. K. Chrysanthis   Multiversion data broadcast  . . . . . . 1224--1230
                Wai Gen Yee and   
              S. B. Navathe and   
              E. Omiecinski and   
                    C. Jermaine   Efficient data allocation over multiple
                                  channels at broadcast servers  . . . . . 1231--1236
               Guanling Lee and   
               Shou-Chih Lo and   
                  A. L. P. Chen   Data allocation on wireless broadcast
                                  channels for efficient query processing  1237--1252
               K. C. K. Lee and   
              Hong Va Leong and   
                          A. Si   Semantic data broadcast for a mobile
                                  environment based on dynamic and
                                  adaptive chunking  . . . . . . . . . . . 1253--1268
                   W. Tembe and   
                       S. Pande   Loop restructuring for data I/O
                                  minimization on limited on-chip memory
                                  embedded processors  . . . . . . . . . . 1269--1280

IEEE Transactions on Computers
Volume 51, Number 11, November, 2002

                I. Pomeranz and   
                    S. M. Reddy   A storage-based built-in test pattern
                                  generation method for scan circuits
                                  based on partitioning and reduction of a
                                  precomputed test set . . . . . . . . . . 1282--1293
                    A. Saed and   
                  M. Ahmadi and   
                  G. A. Jullien   A number system with continuous valued
                                  digits and modulo arithmetic . . . . . . 1294--1305
                 Huapeng Wu and   
                M. A. Hasan and   
                I. F. Blake and   
                    Shuhong Gao   Finite field multiplier using redundant
                                  representation . . . . . . . . . . . . . 1306--1316
             N. Slingerland and   
                    A. J. Smith   Measuring the performance of multimedia
                                  instruction sets . . . . . . . . . . . . 1317--1332
              M. Kallahalla and   
                   P. J. Varman   PC-OPT: optimal offline prefetching and
                                  caching for parallel I/O systems . . . . 1333--1344
            Eui-Young Chung and   
                  L. Benini and   
                A. Bogliolo and   
             Yung-Hsiang Lu and   
                  G. De Micheli   Dynamic power management for
                                  nonstationary service requests . . . . . 1345--1361
               Sijing Zhang and   
                   A. Burns and   
                Tee-Hiang Cheng   Cycle-time properties of the timed token
                                  medium access control protocol . . . . . 1362--1367
             Xiangping Chen and   
                   P. Mohapatra   Performance evaluation of service
                                  differentiating Internet servers . . . . 1368--1375

IEEE Transactions on Computers
Volume 51, Number 12, December, 2002

       J. A. Piñeiro and   
                 J. D. Bruguera   High-Speed Double Precision Computation
                                  of Reciprocal, Division, Square Root,
                                  and Inverse Square Root  . . . . . . . . 1377--1388
               H. T. Vergos and   
              C. Efstathiou and   
                     D. Nikolos   Diminished-one modulo $2^n + 1$ adder
                                  design . . . . . . . . . . . . . . . . . 1389--1399
             Yieh-Ran Haung and   
                    Jan-Ming Ho   Distributed call admission control for a
                                  heterogeneous PCS network  . . . . . . . 1400--1409
                Yui-Wah Lee and   
            Kwong-Sak Leung and   
              M. Satyanarayanan   Operation shipping for mobile file
                                  systems  . . . . . . . . . . . . . . . . 1410--1422
               P. Cremonesi and   
           P. J. Schweitzer and   
                     G. Serazzi   A unifying framework for the approximate
                                  solution of closed multiclass queuing
                                  networks . . . . . . . . . . . . . . . . 1423--1434
             E. A. Schweitz and   
                  D. P. Agrawal   Parallelization domain oriented
                                  multilevel graph partitioner . . . . . . 1435--1441
              Ching-Min Lin and   
               Ge-Ming Chiu and   
                 Cheng-Hong Cho   A new quorum-based scheme for managing
                                  replicated data in distributed systems   1442--1447
             K. Chakrabarty and   
              S. S. Iyengar and   
                 Hairong Qi and   
                   Eungchun Cho   Grid coverage for surveillance and
                                  target location in distributed sensor
                                  networks . . . . . . . . . . . . . . . . 1448--1453
                 N. Sklavos and   
                 O. Koufopavlou   Architectures and VLSI implementations
                                  of the AES-Proposal Rijndael . . . . . . 1454--1459
              W. Geiselmann and   
            J. Muller-Quade and   
                  R. Steinwandt   On ``A new representation of elements of
                                  finite fields $\mathrm{GF}(2^m)$
                                  yielding small complexity arithmetic
                                  circuits'' . . . . . . . . . . . . . . . 1460--1461
                 Wen Guey Tzeng   Corrections to ``A secure fault-tolerant
                                  conference-key agreement protocol''  . . 1462--1462
                      Anonymous   Author Index . . . . . . . . . . . . . . 1463--1466
                      Anonymous   Subject Index  . . . . . . . . . . . . . 1466--1472


IEEE Transactions on Computers
Volume 52, Number 1, January, 2003

            R. Govindarajan and   
                Hongbo Yang and   
               J. N. Amaral and   
              Chihong Zhang and   
                      G. R. Gao   Minimum register instruction sequencing
                                  to reduce register spills in
                                  out-of-order issue superscalar
                                  architectures  . . . . . . . . . . . . . 4--20
               Hongbing Fan and   
                 Jiping Liu and   
                    Yu-Liang Wu   General models and a reduction design
                                  technique for FPGA switch box designs    21--30
                Yansong Ren and   
               D. E. Bakken and   
                T. Courtney and   
                  M. Cukier and   
                 D. A. Karr and   
                   P. Rubel and   
                  C. Sabnis and   
              W. H. Sanders and   
              R. E. Schantz and   
                        M. Seri   AQuA: an adaptive architecture that
                                  provides dependable distributed objects  31--50
                 Jin-Ho Kim and   
              Saewoong Bahk and   
                     Hyogon Kim   Performance impact of coarse timer
                                  granularities on QoS guarantees in
                                  Unix-based systems . . . . . . . . . . . 51--58
           N. Vijaykrishnan and   
                M. Kandemir and   
                M. J. Irwin and   
               Hyun Suk Kim and   
                      Wu Ye and   
                      D. Duarte   Evaluating integrated hardware-software
                                  optimizations using a unified energy
                                  estimation framework . . . . . . . . . . 59--76
                     H. M. Heys   Analysis of the statistical cipher
                                  feedback mode of block ciphers . . . . . 77--92
                      Anonymous   2002 reviewers list  . . . . . . . . . . 93--96

IEEE Transactions on Computers
Volume 52, Number 2, February, 2003

            S. J. Upadhyaya and   
                  A. Bondavalli   Guest editorial: special issue on
                                  reliable distributed systems . . . . . . 97--98
                      C. Fetzer   Perfect failure detection in timed
                                  asynchronous systems . . . . . . . . . . 99--112
               N. Kandasamy and   
                J. P. Hayes and   
                   B. T. Murray   Transparent recovery from intermittent
                                  faults in time-triggered distributed
                                  systems  . . . . . . . . . . . . . . . . 113--125
               Kuo-Feng Ssu and   
                W. K. Fuchs and   
                     H. C. Jiau   Process recovery in heterogeneous
                                  systems  . . . . . . . . . . . . . . . . 126--138
               A. J. Ganesh and   
            A.-M. Kermarrec and   
                   L. Massoulie   Peer-to-peer membership management for
                                  gossip-based protocols . . . . . . . . . 139--149
                 J. Pereira and   
               L. Rodrigues and   
                    R. Oliveira   Semantically reliable multicast:
                                  definition, implementation, and
                                  performance evaluation . . . . . . . . . 150--165
                    E. Nett and   
                    S. Schemmer   Reliable real-time communication in
                                  cooperative mobile applications  . . . . 166--180
             M. A. Hiltunen and   
          R. D. Schlichting and   
                   C. A. Ugarte   Building survivable services using
                                  redundancy and adaptation  . . . . . . . 181--194
                     Jun Xu and   
                    Wooyong Lee   Sustaining availability of Web services
                                  under distributed denial of service
                                  attacks  . . . . . . . . . . . . . . . . 195--208
                 S. Pleisch and   
                     A. Schiper   Fault-tolerant mobile agent execution    209--222
                   M. Rabah and   
                      K. Kanoun   Performability evaluation of
                                  multipurpose multiprocessor systems: the
                                  ``separation of concerns'' approach  . . 223--236
                 J. C. Ruiz and   
            M.-O. Killijian and   
                J.-C. Fabre and   
               P. Thvenod-Fosse   Reflective fault-tolerant systems: from
                                  experience to challenges . . . . . . . . 237--254
                       Lu Zhang   Comments on ``A fast and efficient
                                  processor allocation scheme for
                                  mesh-connected multicomputers''  . . . . 255--256

IEEE Transactions on Computers
Volume 52, Number 3, March, 2003

                 V. K. Prasanna   Editor's note  . . . . . . . . . . . . . 257--259
                    S. Sair and   
                T. Sherwood and   
                      B. Calder   A decoupled predictor-directed stream
                                  prefetching architecture . . . . . . . . 260--276
               Chao-ying Fu and   
               J. T. Bodine and   
                    T. M. Conte   Modeling value speculation: an optimal
                                  edge selection problem . . . . . . . . . 277--292
                  Z. Al-Ars and   
              A. J. van de Goor   Static and dynamic behavior of memory
                                  cell array spot defects in embedded
                                  DRAMs  . . . . . . . . . . . . . . . . . 293--309
                     Dajin Wang   A rectilinear-monotone polygonal fault
                                  block model for fault-tolerant minimal
                                  routing in mesh  . . . . . . . . . . . . 310--320
             B. B. Fraguela and   
                  R. Doallo and   
                   E. L. Zapata   Probabilistic miss equations: evaluating
                                  memory hierarchy performance . . . . . . 321--336
                  S. Lauzac and   
                  R. Melhem and   
                       D. Mosse   An improved rate-monotonic admission
                                  control and its applications . . . . . . 337--350
                  Deji Chen and   
                  A. K. Mok and   
                    Tei-Wei Kuo   Utilization bound revisited  . . . . . . 351--361
             Ching-Chih Han and   
                 K. G. Shin and   
                        Jian Wu   A fault-tolerant scheduling algorithm
                                  for real-time periodic tasks with
                                  possible software faults . . . . . . . . 362--372
                    Ben Kao and   
                Kam-Yiu Lam and   
                B. Adelberg and   
                   R. Cheng and   
                         T. Lee   Maintaining temporal consistency of
                                  discrete objects in soft real-time
                                  database systems . . . . . . . . . . . . 373--389
                S. O. Memik and   
          A. K. Katsaggelos and   
                 M. Sarrafzadeh   Analysis and FPGA implementation of
                                  image restoration under resource
                                  constraints  . . . . . . . . . . . . . . 390--399

IEEE Transactions on Computers
Volume 52, Number 4, April, 2003

                  C. K. Koc and   
                        C. Paar   Guest editors' introduction to the
                                  special section on cryptographic
                                  hardware and embedded systems  . . . . . 401--402
                   M. Bucci and   
                 L. Germani and   
                   R. Luzzi and   
              A. Trifiletti and   
                 M. Varanonuovo   A high-speed oscillator-based truly
                                  random number source for cryptographic
                                  applications on a smart card IC  . . . . 403--409
                  P. Sarkar and   
                      S. Maitra   Efficient implementation of
                                  cryptographically useful ``large''
                                  Boolean functions  . . . . . . . . . . . 410--417
                   R. Katti and   
                     J. Brennan   Low complexity multiplication in a
                                  finite field using ring representation   418--427
         A. Reyhani-Masoleh and   
                    M. A. Hasan   Efficient multiplication beyond optimal
                                  normal bases . . . . . . . . . . . . . . 428--439
                C. O'Rourke and   
                       B. Sunar   Achieving NTRU with Montgomery
                                  multiplication . . . . . . . . . . . . . 440--448
                   A. Satoh and   
                      K. Takano   A scalable dual-field elliptic curve
                                  cryptographic processor  . . . . . . . . 449--460
              Sung-Ming Yen and   
               Seungjoo Kim and   
                Seongan Lim and   
                  Sang-Jae Moon   RSA speedup with Chinese Remainder
                                  Theorem immune against hardware fault
                                  cryptanalysis  . . . . . . . . . . . . . 461--472
                 G. Rouvroy and   
            F.-X. Standaert and   
           J.-J. Quisquater and   
                    J.-D. Legat   Efficient uses of FPGAs for
                                  implementations of DES and its
                                  experimental linear cryptanalysis  . . . 473--482
                 S. Mangard and   
                  M. Aigner and   
                   S. Dominikus   A highly regular and scalable AES
                                  hardware architecture  . . . . . . . . . 483--491
                 G. Bertoni and   
             L. Breveglieri and   
                   I. Koren and   
                 P. Maistri and   
                       V. Piuri   Error analysis and detection procedures
                                  for a hardware implementation of the
                                  advanced encryption standard . . . . . . 492--505
                Tei-Wei Kuo and   
              Yuan-Ting Kao and   
                    Chin-Fu Kuo   Two-version based concurrency control
                                  and recovery in real-time client/server
                                  databases  . . . . . . . . . . . . . . . 506--524
              L. E. LaForge and   
               K. F. Korver and   
                 M. Sami Fadali   What designers of bus and network
                                  architectures should know about
                                  hypercubes . . . . . . . . . . . . . . . 525--544

IEEE Transactions on Computers
Volume 52, Number 5, May, 2003

              Yu-Chee Tseng and   
                 Sze-Yao Ni and   
                     En-Yu Shih   Adaptive approaches to relieving
                                  broadcast storms in a wireless multihop
                                  mobile ad hoc network  . . . . . . . . . 545--557
              L. G. Tallini and   
                        B. Bose   Transmission time analysis for the
                                  parallel asynchronous communication
                                  scheme . . . . . . . . . . . . . . . . . 558--571
                  R. Conway and   
                      J. Nelson   New CRT-based RNS converter using
                                  restricted moduli set  . . . . . . . . . 572--578
                  M. Turmon and   
                  R. Granat and   
                 D. S. Katz and   
                      J. Z. Lou   Tests and tolerances for
                                  high-performance software-implemented
                                  fault detection  . . . . . . . . . . . . 579--591
            M. G. Karpovsky and   
            R. S. Stankovic and   
                   J. T. Astola   Reduction of sizes of decision diagrams
                                  by autocorrelation functions . . . . . . 592--606
              Jung-Hoon Lee and   
            Seh-woong Jeong and   
               Shin-Dug Kim and   
                    C. C. Weems   An intelligent cache system with
                                  hardware prefetching for high
                                  performance  . . . . . . . . . . . . . . 607--616
               L. N. Bhuyan and   
                     Hujun Wang   Switch MSHR: a technique to reduce
                                  remote read memory access time in
                                  CC-NUMA multiprocessors  . . . . . . . . 617--632
                    A. Cuyt and   
                R. B. Lenin and   
                 G. Willems and   
                 C. Blondia and   
                   P. Rousseeuw   Computing packet loss probabilities in
                                  multiplexer models using rational
                                  approximation  . . . . . . . . . . . . . 633--644
               Moonsoo Kang and   
                  Chansu Yu and   
              Hee Yong Youn and   
                    Ben Lee and   
                  Myungchul Kim   Isomorphic strategy for processor
                                  allocation in $k$-ary $n$-cube systems   645--657
                Tei-Wei Kuo and   
                      A. K. Mok   Schedulability and performance analysis
                                  of the similarity stack protocol . . . . 658--669
           Ming-Chung Liang and   
                Tei-Wei Kuo and   
                   LihChyun Shu   A quantification of aborting effect for
                                  real-time data accesses  . . . . . . . . 670--675
                      P. K. Jha   A counterexample to Tang and Padubidri's
                                  claim about the bisection width of a
                                  diagonal mesh  . . . . . . . . . . . . . 676--677
           T. F. Abdelzaher and   
                 K. G. Shin and   
                      N. Bhatti   User-level QoS-adaptive resource
                                  management in server end-systems . . . . 678--685
                   Yuguang Fang   Thinning schemes for call admission
                                  control in wireless networks . . . . . . 685--688
                    F. Wolz and   
                       R. Kolla   Disproving the perfect-rate property of
                                  data-flow graphs unfolded by the least
                                  common multiple of the number of loop
                                  register . . . . . . . . . . . . . . . . 688--688

IEEE Transactions on Computers
Volume 52, Number 6, June, 2003

                  Y.-B. Lin and   
                    Y.-C. Tseng   Guest editorial: special section on
                                  wireless Internet  . . . . . . . . . . . 689--689
                   B. Emako and   
               R. H. Glitho and   
                      S. Pierre   A mobile agent-based advanced service
                                  architecture for wireless Internet
                                  telephony: design, implementation, and
                                  evaluation . . . . . . . . . . . . . . . 690--705
                  Y. J. Lee and   
                 I. F. Akyildiz   A new scheme for reducing link and
                                  signaling costs in mobile IP . . . . . . 706--712
             P. K. McKinley and   
          U. I. Padmanabhan and   
                   N. Ancha and   
                  S. M. Sadjadi   Composable proxy services to support
                                  collaboration on the mobile Internet . . 713--726
               V. A. Chitre and   
                   J. N. Daigle   Performance of IP-based services over
                                  GPRS . . . . . . . . . . . . . . . . . . 727--741
                  S. K. Das and   
                     E. Lee and   
                    K. Basu and   
                      S. K. Sen   Performance optimization of VoIP calls
                                  over wireless links using H.323 protocol 742--752
              Xiang-Yang Li and   
               Peng-Jun Wan and   
                     O. Frieder   Coverage in wireless ad hoc sensor
                                  networks . . . . . . . . . . . . . . . . 753--763
               Shou-Chih Lo and   
               Guanling Lee and   
                 Wen-Tsuen Chen   An efficient multipolling mechanism for
                                  IEEE 802.11 wireless LANs  . . . . . . . 764--778
                C. Petrioli and   
                 S. Basagni and   
                    M. Chlamtac   Configuring BlueStars: multihop
                                  scatternet formation for Bluetooth
                                  networks . . . . . . . . . . . . . . . . 779--790
                   Yuguang Fang   Movement-based mobility management and
                                  trade off analysis for wireless mobile
                                  networks . . . . . . . . . . . . . . . . 791--803
              Yu-Kwong Kwok and   
                   V. K. N. Lau   System modeling and performance
                                  evaluation of rate allocation schemes
                                  for packet data services in wideband
                                  CDMA systems . . . . . . . . . . . . . . 804--814
               F. Schmiedle and   
               R. Drechsler and   
                      B. Becker   Exact routing with search space
                                  reduction  . . . . . . . . . . . . . . . 815--825
             Hung-Ying Tyan and   
                  J. C. Hou and   
                       Bin Wang   Many-to-many multicast routing with
                                  temporal quality of service guarantees   826--832

IEEE Transactions on Computers
Volume 52, Number 7, July, 2003

                 V. K. Prasanna   Editor's note  . . . . . . . . . . . . . 833--834
                G. Umanesan and   
                    E. Fujiwara   A class of random multiple bits in a
                                  byte error correcting and single byte
                                  error detecting $({S}_t b / {EC} - {S}_b
                                  {ED})$ codes . . . . . . . . . . . . . . 835--847
              W. Geiselmann and   
                  R. Steinwandt   A redundant representation of
                                  $\mathrm{GF}(q^n)$ for designing
                                  arithmetic circuits  . . . . . . . . . . 848--853
               R. Duggirala and   
                   R. Gupta and   
               Qing-An Zeng and   
                  D. P. Agrawal   Notice of Violation of IEEE Publication
                                  Principles ``Performance enhancements of
                                  ad hoc networks with localized route
                                  repair'' . . . . . . . . . . . . . . . . 854--861
               M. Chaudhuri and   
                M. Heinrich and   
                    C. Holt and   
                J. P. Singh and   
                E. Rothberg and   
                    J. Hennessy   Latency, occupancy, and bandwidth in DSM
                                  multiprocessors: a performance
                                  evaluation . . . . . . . . . . . . . . . 862--880
                     J. Liu and   
                    F. Chow and   
                    T. Kong and   
                         R. Roy   Variable instruction set architecture
                                  and its compiler support . . . . . . . . 881--895
               H. T. Vergos and   
                 D. Nikolos and   
                  M. Bellos and   
                  C. Efstathiou   Deterministic BIST for RNS adders  . . . 896--906
              S.-H. G. Chan and   
                   F. A. Tobagi   Modeling and dimensioning hierarchical
                                  storage systems for low-delay video
                                  services . . . . . . . . . . . . . . . . 907--919
             Sheng-Uei Guan and   
                        Wei Liu   Self-modifiable color Petri nets for
                                  modeling user manipulation and network
                                  event handling . . . . . . . . . . . . . 920--932
                    E. Bini and   
             G. C. Buttazzo and   
                 G. M. Buttazzo   Rate monotonic analysis: the hyperbolic
                                  bound  . . . . . . . . . . . . . . . . . 933--942
              U. Cetintemel and   
              P. J. Keleher and   
           B. Bhattacharjee and   
                 M. J. Franklin   Deno: a decentralized, peer-to-peer
                                  object-replication system for weakly
                                  connected environments . . . . . . . . . 943--959
                    D. Keen and   
                   M. Oskin and   
                 J. Hensley and   
                    F. T. Chong   Cache coherence in intelligent memory
                                  systems  . . . . . . . . . . . . . . . . 960--966
               S. K. Baruah and   
                    J. Goossens   Rate-monotonic scheduling on uniform
                                  multiprocessors  . . . . . . . . . . . . 966--970
                   T. Araki and   
                     Y. Shibata   $(t, k)$-diagnosable system: a
                                  generalization of the PMC models . . . . 971--975
                B. J. Falkowski   A comment on ``Generalized Reed--Muller
                                  forms as a tool to detect symmetries''   975--976

IEEE Transactions on Computers
Volume 52, Number 8, August, 2003

                   A. Smailagic   Wearable computers: a new paradigm in
                                  computer systems and their applications  977--978
               T. L. Martin and   
                D. P. Siewiorek   Nonideal battery properties and their
                                  impact on software design for wearable
                                  computers  . . . . . . . . . . . . . . . 979--984
                  L. Benini and   
                   D. Bruni and   
                    A. Mach and   
                   E. Macii and   
                     M. Poncino   Discharge current steering for battery
                                  lifetime optimization  . . . . . . . . . 985--995
      P. S. Stanley-Marbell and   
              D. Marculescu and   
              R. Marculescu and   
                   P. K. Khosla   Modeling, analysis, and self-management
                                  of electronic textiles . . . . . . . . . 996--1010
                      B. Rhodes   Using physical context for just-in-time
                                  information retrieval  . . . . . . . . . 1011--1014
                   D. Talla and   
                 L. K. John and   
                      D. Burger   Bottlenecks in multimedia processing
                                  with SIMD style extensions and
                                  architectural enhancements . . . . . . . 1015--1031
                 Jian Huang and   
                     D. J. Lija   Balancing reuse opportunities and
                                  performance gains with subblock value
                                  reuse  . . . . . . . . . . . . . . . . . 1032--1050
                 R. Beraldi and   
                     R. Baldoni   A caching scheme for routing in mobile
                                  ad hoc networks and its application to
                                  ZRP  . . . . . . . . . . . . . . . . . . 1051--1062
                 Dong Xiang and   
                      Yi Xu and   
                    H. Fujiwara   Nonscan design for testability for
                                  synchronous sequential circuits based on
                                  conflict resolution  . . . . . . . . . . 1063--1075
                 A. Chandra and   
                 K. Chakrabarty   Test data compression and test resource
                                  partitioning for system-on-a-chip using
                                  frequency-directed run-length (FDR)
                                  codes  . . . . . . . . . . . . . . . . . 1076--1088

IEEE Transactions on Computers
Volume 52, Number 9, September, 2003

                  A. Mishra and   
                    P. Banerjee   An algorithm-based error detection
                                  scheme for the multigrid method  . . . . 1089--1099
          Tomás Lang and   
                Elisardo Antelo   Radix-$4$ Reciprocal Square-root and Its
                                  Combination with Division and Square
                                  Root . . . . . . . . . . . . . . . . . . 1100--1114
                   J. Arlat and   
                 Y. Crouzet and   
                J. Karlsson and   
               P. Folkesson and   
                   E. Fuchs and   
                    G. H. Leber   Comparison of physical and
                                  software-implemented fault injection
                                  techniques . . . . . . . . . . . . . . . 1115--1133
                   J. Flich and   
                   P. Lopez and   
            M. P. Malumbres and   
                   J. Duato and   
                     T. Rokicki   Applying in-transit buffers to boost the
                                  performance of networks with source
                                  routing  . . . . . . . . . . . . . . . . 1134--1153
                         Jie Wu   A fault-tolerant and deadlock-free
                                  routing protocol in $2$D meshes based on
                                  odd-even turn model  . . . . . . . . . . 1154--1169
                     P. Sanders   Asynchronous scheduling of redundant
                                  disk arrays  . . . . . . . . . . . . . . 1170--1184
                  S. Baruah and   
                    S. Funk and   
                    J. Goossens   Robustness results concerning EDF
                                  scheduling upon uniform multiprocessors  1185--1195
                 W. Gunther and   
                   R. Drechsler   Efficient minimization and manipulation
                                  of linearly transformed binary decision
                                  diagrams . . . . . . . . . . . . . . . . 1196--1209
                   J. Aerts and   
                   J. Korst and   
                F. Spieksma and   
                W. Verhaegh and   
                   G. Woeginger   Random redundant storage in disk arrays:
                                  complexity of retrieval problems . . . . 1210--1214
                A. F. Tenca and   
                      C. K. Koc   A scalable architecture for modular
                                  multiplication based on Montgomery's
                                  algorithm  . . . . . . . . . . . . . . . 1215--1221
                 K. H. Abed and   
                   R. E. Siferd   VLSI implementation of a low-power
                                  antilogarithmic converter  . . . . . . . 1221--1228
             Jong-Hoon Youn and   
                        B. Bose   Efficient encoding and decoding schemes
                                  for balanced codes . . . . . . . . . . . 1229--1232

IEEE Transactions on Computers
Volume 52, Number 10, October, 2003

              Wen-Chang Yeh and   
                  Chein-Wei Jen   Generalized earliest-first fast addition
                                  algorithm  . . . . . . . . . . . . . . . 1233--1242
         R. Balasubramonian and   
             D. H. Albonesi and   
          A. Buyuktosunoglu and   
                   S. Dwarkadas   A dynamically tunable memory hierarchy   1243--1258
                Wen-Yi Feng and   
                F. J. Meyer and   
                    F. Lombardi   Adaptive algorithms for maximal
                                  diagnosis of wiring interconnects  . . . 1259--1270
                  M. M. Bae and   
                        B. Bose   Edge disjoint Hamiltonian cycles in
                                  $k$-ary $n$-cubes and hypercubes . . . . 1271--1284
                 D. B. Shaw and   
              D. Al-Khalili and   
                    C. N. Rozon   IC bridge fault modeling for IP blocks
                                  using neural network-based VHDL
                                  saboteurs  . . . . . . . . . . . . . . . 1285--1297
                     Jie Wu and   
                    Fei Dai and   
                 Xiaola Lin and   
               Jiannong Cao and   
                     Weijia Jia   An extended fault-tolerant link-state
                                  routing protocol in the Internet . . . . 1298--1311
              G. Campobello and   
                  G. Patane and   
                       M. Russo   Parallel CRC realization . . . . . . . . 1312--1319
          A. J. van de Goor and   
                 I. B. S. Tlili   A systematic method for modifying march
                                  tests for bit-oriented memories into
                                  tests for word-oriented memories . . . . 1320--1331
              G. de A. Lima and   
                       A. Burns   An optimal fixed-priority assignment
                                  algorithm for supporting fault-tolerant
                                  hard real-time systems . . . . . . . . . 1332--1346
           P. Mejia-Alvarez and   
                  R. Melhem and   
                   D. Mosse and   
                       H. Aydin   An incremental server for scheduling
                                  overloaded real-time systems . . . . . . 1347--1361
               J. M. P. Cardoso   On combining temporal partitioning and
                                  sharing of functional units in
                                  compilation for reconfigurable
                                  architectures  . . . . . . . . . . . . . 1362--1375

IEEE Transactions on Computers
Volume 52, Number 11, November, 2003

         A. Reyhani-Masoleh and   
                    M. A. Hasan   Fast normal basis multiplication using
                                  general purpose processors . . . . . . . 1379--1390
                   B. Sunar and   
                   E. Savas and   
                      C. K. Koc   Constructing composite field
                                  representations for efficient conversion 1391--1398
              C. Efstathiou and   
               H. T. Vergos and   
                     D. Nikolos   Modulo $2^n \pm 1$ adder design using
                                  select-prefix blocks . . . . . . . . . . 1399--1406
                W. Michiels and   
                   J. Korst and   
                       J. Aerts   On the guaranteed throughput of
                                  multizone disks  . . . . . . . . . . . . 1407--1420
                 K. H. Abed and   
                   R. E. Siferd   CMOS VLSI implementation of a low-power
                                  logarithmic converter  . . . . . . . . . 1421--1433
                  G. R. Redinbo   Failure-detecting arithmetic
                                  convolutional codes and an iterative
                                  correcting strategy  . . . . . . . . . . 1434--1442
                B. A. Izadi and   
                     F. Ozguner   Enhanced cluster $k$-ary $n$-cube, a
                                  fault-tolerant multiprocessor  . . . . . 1443--1453
                  K. Baynes and   
                 C. Collins and   
                E. Fiterman and   
              Brinda Ganesh and   
                  P. Kohout and   
                    C. Smit and   
                   T. Zhang and   
                       B. Jacob   The performance and energy consumption
                                  of embedded real-time operating systems  1454--1469
                F. J. Meyer and   
                        N. Park   Predicting defect-tolerant yield in the
                                  embedded core context  . . . . . . . . . 1470--1479
           I. Bayraktaroglu and   
                   A. Orailoglu   Concurrent application of compaction and
                                  compression for test time and data
                                  volume reduction in scan designs . . . . 1480--1489
                S. R. Naidu and   
                  Vijay Chandru   On synthesis of easily testable $(k, K)$
                                  circuits . . . . . . . . . . . . . . . . 1490--1494
                   S. Weiss and   
                       S. Beren   Class-based decompressor design for
                                  compressed instruction memory in
                                  embedded processors  . . . . . . . . . . 1495--1500
                 W.-C. Park and   
                  K.-W. Lee and   
                  I.-S. Kim and   
                  T.-D. Han and   
                     S.-B. Yang   An effective pixel rasterization
                                  pipeline architecture for $3$D rendering
                                  processors . . . . . . . . . . . . . . . 1501--1508
                     B. Parhami   Tight upper bounds on the minimum
                                  precision required of the divisor and
                                  the partial remainder in high-radix
                                  division . . . . . . . . . . . . . . . . 1509--1514
                     Z. Yan and   
                  D. V. Sarwate   New systolic architectures for inversion
                                  and division in $\mathrm{GF}(2^m)$ . . . 1514--1519

IEEE Transactions on Computers
Volume 52, Number 12, December, 2003

                     Y. Gao and   
                  J. C. Hou and   
                    Sanjoy Paul   RACCOOM: a rate-based congestion control
                                  approach for multicast . . . . . . . . . 1521--1534
     F. Rodriguez-Henriquez and   
        Ç. K. Koç   Parallel multipliers based on special
                                  irreducible pentanomials . . . . . . . . 1535--1542
        Mitrajit Chatterjee and   
                  D. K. Pradhan   A BIST pattern generator design for
                                  near-perfect fault coverage  . . . . . . 1543--1558
                   Jun Wang and   
                      Yiming Hu   A novel reordering write buffer to
                                  improve write performance of
                                  log-structured file systems  . . . . . . 1559--1572
                 O. Ercetin and   
                   L. Tassiulas   Market-based resource allocation for
                                  content delivery in the Internet . . . . 1573--1585
              C. M. Krishna and   
                      Y.-H. Lee   Voltage-clock-scaling adaptive
                                  scheduling techniques for low power in
                                  hard real-time systems . . . . . . . . . 1586--1593
                L. M. Pinho and   
                     F. Vasques   Reliable real-time communication in CAN
                                  networks . . . . . . . . . . . . . . . . 1594--1607
                    X. Zang and   
                    D. Wang and   
                     H. Sun and   
                  K. S. Trivedi   A BDD-based algorithm for analysis of
                                  multistate systems with multistate
                                  components . . . . . . . . . . . . . . . 1608--1618
             Vikram Iyengar and   
     Krishnendu Chakrabarty and   
               E. J. Marinissen   Test access mechanism optimization, test
                                  scheduling, and tester data volume
                                  reduction for system-on-chip . . . . . . 1619--1632
                     D. Kagaris   Multiple-seed TPG structures . . . . . . 1633--1639
              Chun-Yuan Lin and   
            Yeh-Ching Chung and   
                  Jen-Shiuh Liu   Efficient data compression methods for
                                  multidimensional sparse array operations
                                  based on the EKMR scheme . . . . . . . . 1640--1646
         B. B. Bhattacharya and   
                A. Dmitriev and   
                      M. Gossel   Zero-aliasing space compaction of test
                                  responses using a single periodic output 1646--1651


IEEE Transactions on Computers
Volume 53, Number 1, January, 2004

               V. De La Luz and   
                    M. Kandemir   Array regrouping and its use in
                                  compiling data-intensive, embedded
                                  applications . . . . . . . . . . . . . . 1--19
                      Z. Xu and   
                  S. Sohoni and   
                     R. Min and   
                          Y. Hu   An analysis of cache performance of
                                  multimedia applications  . . . . . . . . 20--38
              Hong-Chun Hsu and   
              Tseng-Kuei Li and   
               J. J. M. Tan and   
                  Lih-Hsing Hsu   Fault hamiltonicity and fault
                                  Hamiltonian connectivity of the
                                  arrangement graphs . . . . . . . . . . . 39--53
            Yung-Ruei Chang and   
                S. V. Amari and   
                     Sy-Yen Kuo   Computing system failure frequencies and
                                  reliability importance measures using
                                  OBDD . . . . . . . . . . . . . . . . . . 54--68
              T. Srikanthan and   
                  S. K. Lam and   
                   Mishra Suman   Area-time efficient sign detection
                                  technique for binary signed-digit number
                                  system . . . . . . . . . . . . . . . . . 69--72
                  M. Brehob and   
                  S. Wagner and   
                   E. Torng and   
                      R. Enbody   Optimal replacement is NP-hard for
                                  nonstandard caches . . . . . . . . . . . 73--76
               Yin-Fu Huang and   
                Jiing-Maw Huang   Disk scheduling on multimedia storage
                                  servers  . . . . . . . . . . . . . . . . 77--82
                I. Pomeranz and   
               Sandip Kundu and   
                    S. M. Reddy   Masking of unknown output values during
                                  output response compression by using
                                  comparison units . . . . . . . . . . . . 83--89
                   P. Santi and   
                      S. Chessa   Reducing the number of sequential
                                  diagnosis iterations in hypercubes . . . 89--92
                      Anonymous   2003 reviewers list  . . . . . . . . . . 93--96

IEEE Transactions on Computers
Volume 53, Number 2, February, 2004

               P.-M. Seidel and   
                        G. Even   Delay-optimized implementation of IEEE
                                  floating-point addition  . . . . . . . . 97--113
               P. Marcuello and   
                A. Gonzalez and   
                     J. Tubella   Thread partitioning and value prediction
                                  for exploiting speculative thread-level
                                  parallelism  . . . . . . . . . . . . . . 114--125
            Viji Srinivasan and   
             E. S. Davidson and   
                    G. S. Tyson   A prefetch taxonomy  . . . . . . . . . . 126--140
             B. R. Childers and   
                 J. W. Davidson   Custom wide counterflow pipelines for
                                  high-performance embedded applications   141--158
                  H. Kaneko and   
                    E. Fujiwara   A class of $M$-ary asymmetric symbol
                                  error correcting codes for data entry
                                  devices  . . . . . . . . . . . . . . . . 159--167
                  D. Parikh and   
                 K. Skadron and   
                   Y. Zhang and   
                        M. Stan   Power-aware branch prediction:
                                  characterization and design  . . . . . . 168--186
                  C.-G. Lee and   
                     L. Sha and   
                  Avinash Peddi   Enhanced utilization bounds for QoS
                                  management . . . . . . . . . . . . . . . 187--200
            Binoy Ravindran and   
                          P. Li   DPR, LPR: proactive resource allocation
                                  algorithms for asynchronous real-time
                                  distributed systems  . . . . . . . . . . 201--216
                  R. Melhem and   
                   D. Mosse and   
                    E. Elnozahy   The interplay of power management and
                                  fault recovery in real-time systems  . . 217--231
                 Wen-Guey Tzeng   Efficient $1$-out-of-$n$ oblivious
                                  transfer schemes with universally usable
                                  parameters . . . . . . . . . . . . . . . 232--240

IEEE Transactions on Computers
Volume 53, Number 3, March, 2004

          B. Krishnamachari and   
                     S. Iyengar   Distributed Bayesian algorithms for
                                  fault-tolerant event region detection in
                                  wireless sensor networks . . . . . . . . 241--250
                      D. Harris   An exponentiation unit for an OpenGL
                                  lighting engine  . . . . . . . . . . . . 251--258
               Huan-Yun Wei and   
           Shih-Chiang Tsao and   
                   Ying-Dar Lin   Assessing and improving TCP rate shaping
                                  over edge gateways . . . . . . . . . . . 259--275
                 Dong Xiang and   
                    J. H. Patel   Partial scan design based on circuit
                                  state information and functional
                                  analysis . . . . . . . . . . . . . . . . 276--287
                     D. Kim and   
               M. Chaudhuri and   
                M. Heinrich and   
                     E. Speight   Architectural support for uniprocessor
                                  and multiprocessor active memory systems 288--307
                   Y. Jiang and   
                      J. Li and   
                   S. Nishimura   A general stochastic model for dynamic
                                  locking in database systems  . . . . . . 308--319
               T. Clouqueur and   
               K. K. Saluja and   
                  P. Ramanathan   Fault tolerance in collaborative sensor
                                  networks for target detection  . . . . . 320--333
           T. F. Abdelzaher and   
               Vivek Sharma and   
                          C. Lu   A utilization bound for aperiodic tasks
                                  and priority driven scheduling . . . . . 334--350
                   S. Sahni and   
                      K. S. Kim   An $O(\log n)$ dynamic router-table
                                  design . . . . . . . . . . . . . . . . . 351--363
        V. Phipatanasuphorn and   
        Parameswaran Ramanathan   Vulnerability of sensor networks to
                                  unauthorized traversal and monitoring    364--369
              C. Efstathiou and   
               H. T. Vergos and   
                     D. Nikolos   Modified Booth modulo $2^n - 1$
                                  multipliers  . . . . . . . . . . . . . . 370--374
             Chien-Hsing Wu and   
              Chien-Ming Wu and   
             Ming-Der Shieh and   
                Yin-Tsung Hwang   High-speed, low-complexity systolic
                                  designs of novel iterative division
                                  algorithms in $\mathrm{GF}(2^m)$ . . . . 375--380
                    X. Teng and   
                        H. Pham   Software cost model for quantifying the
                                  gain with considerations of random field
                                  environments . . . . . . . . . . . . . . 380--384

IEEE Transactions on Computers
Volume 53, Number 4, April, 2004

             V. K. Prasanna and   
                    F. Lombardi   Editor's note  . . . . . . . . . . . . . 385--385
                   Pei-Yin Chen   VLSI implementation for one-dimensional
                                  multilevel lifting-based wavelet
                                  transform  . . . . . . . . . . . . . . . 386--398
           J. J. Koppanalil and   
                   E. Rotenberg   A simple mechanism for detecting
                                  ineffectual instructions in slipstream
                                  processors . . . . . . . . . . . . . . . 399--413
                    Y. Yang and   
                        J. Wang   A fault-tolerant rearrangeable
                                  permutation network  . . . . . . . . . . 414--426
                   C.-T. Ho and   
                  L. Stockmeyer   A new approach to fault-tolerant
                                  wormhole routing for mesh-connected
                                  parallel computers . . . . . . . . . . . 427--438
                  Jong Won Park   Multiaccess memory system for attached
                                  SIMD computer  . . . . . . . . . . . . . 439--452
               R. Guerraoui and   
                      M. Raynal   The information structure of indulgent
                                  consensus  . . . . . . . . . . . . . . . 453--466
                  L. Benini and   
              F. Menichelli and   
                    M. Olivieri   A class of code compression schemes for
                                  reducing power consumption in embedded
                                  microprocessor systems . . . . . . . . . 467--482
           M. Franceschetti and   
                    M. Cook and   
                       J. Bruck   A geometric theorem for network design   483--489
            Jong-Chul Jeong and   
              Woo-Chan Park and   
                Woong Jeong and   
               Tack-Don Han and   
                   Moon-Key Lee   A cost-effective pipelined divider with
                                  a small lookup table . . . . . . . . . . 489--495
              C. M. Krishna and   
                  Yann-Hang Lee   Addendum to ``Voltage-clock-scaling
                                  adaptive scheduling techniques for low
                                  power in hard real-time systems''  . . . 497--497
                      Anonymous   TC: Information for Authors  . . . . . . 498--498
                      Anonymous   IEEE Computer Society Information  . . . 499--499

IEEE Transactions on Computers
Volume 53, Number 5, May, 2004

                  P. Felber and   
                  P. Narasimhan   Experiences, strategies, and challenges
                                  in building fault-tolerant CORBA systems 497--511
                  M. Hiller and   
                  A. Jhumka and   
                    Neeraj Suri   EPIC: profiling the propagation and
                                  effect of data errors in software  . . . 512--530
                   C. Metra and   
      S. Di Francescantonio and   
                      T. M. Mak   Implications of clock distribution
                                  faults and issues with screening them
                                  during manufacturing testing . . . . . . 531--546
                     J. Xue and   
                        X. Vera   Efficient and accurate analytical
                                  modeling of whole-program data cache
                                  behavior . . . . . . . . . . . . . . . . 547--566
                   M. Xiong and   
                 K. Ramamritham   Deriving deadlines and periods for
                                  real-time update transactions  . . . . . 567--583
                   H. Aydin and   
                  R. Melhem and   
                   D. Mosse and   
               P. Mejia-Alvarez   Power-aware scheduling for periodic
                                  real-time tasks  . . . . . . . . . . . . 584--600
                     G. Min and   
                 M. Ould-Khaoua   A performance model for
                                  wormhole-switched interconnection
                                  networks under self-similar traffic  . . 601--613
                A. Y. Duale and   
                     M. U. Uyar   A method enabling feasible conformance
                                  test sequence generation for EFSM models 614--627
                 K. Radecka and   
                       Z. Zilic   Design verification by test vectors and
                                  arithmetic transform universal test set  628--640
                      Anonymous   TC: Information for Authors  . . . . . . 641--641
                      Anonymous   IEEE Computer Society Information  . . . 642--642

IEEE Transactions on Computers
Volume 53, Number 6, June, 2004

                     Y. G. Saab   An effective multilevel algorithm for
                                  bisecting graphs and hypergraphs . . . . 641--652
                   G. Kucuk and   
            D. V. Ponomarev and   
                   O. Ergin and   
                       K. Ghose   Complexity-effective reorder buffer
                                  designs for superscalar processors . . . 653--665
                B. Phillips and   
                     N. Burgess   Minimal weight digit set conversions . . 666--677
                       R.-C. Li   Near optimality of Chebyshev
                                  interpolation for elementary function
                                  computations . . . . . . . . . . . . . . 678--687
                  G.-J. Nam and   
                   F. Aloul and   
             K. A. Sakallah and   
                 R. A. Rutenbar   A comparative study of two Boolean
                                  formulations of FPGA detailed routing
                                  constraints  . . . . . . . . . . . . . . 688--696
               D. Ponomarev and   
                   G. Kucuk and   
                   O. Ergin and   
                       K. Ghose   Isolating short-lived operands for
                                  energy reduction . . . . . . . . . . . . 697--709
                     B. Liu and   
                F. Lombardi and   
                    N. Park and   
                        M. Choi   Testing layered interconnection networks 710--722
                     Y. Luo and   
                     L. K. John   Locality-based online trace compression  723--731
                     X. Qiu and   
                      M. Dubois   Tolerating late memory traps in
                                  dynamically scheduled processors . . . . 732--743
                    R. West and   
                   Y. Zhang and   
                  K. Schwan and   
                 C. Poellabauer   Dynamic window-constrained scheduling of
                                  real-time streams in media servers . . . 744--759
        B. Chevallier-Mames and   
                    M. Ciet and   
                        M. Joye   Low-cost solutions for preventing simple
                                  side-channel analysis: side-channel
                                  atomicity  . . . . . . . . . . . . . . . 760--768
               J.-C. Bajard and   
                      L. Imbert   A full RNS implementation of RSA . . . . 769--774
                     C. Liu and   
         Krishnendu Chakrabarty   Compact dictionaries for fault diagnosis
                                  in scan-BIST . . . . . . . . . . . . . . 775--780
                   S. K. Baruah   Optimal utilization bounds for the
                                  fixed-priority scheduling of periodic
                                  task systems on identical
                                  multiprocessors  . . . . . . . . . . . . 781--784

IEEE Transactions on Computers
Volume 53, Number 7, July, 2004

                  S. Sarkar and   
                   L. Tassiulas   Fair bandwidth allocation for
                                  multicasting in networks with discrete
                                  feasible set . . . . . . . . . . . . . . 785--797
                A. Yakovlev and   
                  S. Furber and   
                   R. Krenz and   
                     A. Bystrov   Design and analysis of a self-timed
                                  duplex communication system  . . . . . . 798--814
                  M. Larrea and   
               A. Fernandez and   
                     S. Arevalo   On the implementation of unreliable
                                  failure detectors in partially
                                  synchronous systems  . . . . . . . . . . 815--828
              Nak-Woong Eum and   
                Taewhan Kim and   
                Chong-Min Kyung   CeRA: a router for symmetrical FPGAs
                                  based on exact routing density
                                  evaluation . . . . . . . . . . . . . . . 829--842
                 Zhao Zhang and   
                Zhichun Zhu and   
                 Xiaodong Zhang   Design and optimization of large size
                                  and low overhead off-chip caches . . . . 843--855
                J. R. Lorch and   
                    A. J. Smith   PACE: a new approach to dynamic voltage
                                  scaling  . . . . . . . . . . . . . . . . 856--869
                 J. P. Grossman   Analytically modeling a fault-tolerant
                                  messaging protocol . . . . . . . . . . . 870--878
                 L. Lenzini and   
                E. Mingozzi and   
                        G. Stea   Design and performance analysis of the
                                  generalized timed token service
                                  discipline . . . . . . . . . . . . . . . 879--891
            D. V. Ponomarev and   
                   G. Kucuk and   
                   O. Ergin and   
                       K. Ghose   Energy efficient comparators for
                                  superscalar datapaths  . . . . . . . . . 892--904
                     Y. Kim and   
                  A. Perrig and   
                      G. Tsudik   Group key agreement efficient in
                                  communication  . . . . . . . . . . . . . 905--921
                Jehn-Ruey Jiang   On the nondomination of cohorts coteries 922--923
                      A. Seznec   Concurrent support of multiple page
                                  sizes on a skewed associative TLB  . . . 924--927
                      Anonymous   Notice of Violation of IEEE publication
                                  Principles in ``Performance Enhancement
                                  of Ad Hoc Networks with Localized Route
                                  Repair'' . . . . . . . . . . . . . . . . 928--928

IEEE Transactions on Computers
Volume 53, Number 8, August, 2004

                    Q. Zhao and   
                    D. J. Lilja   Static classification of value
                                  predictability using compiler hints  . . 929--944
         A. Reyhani-Masoleh and   
                    M. A. Hasan   Low complexity bit parallel
                                  architectures for polynomial basis
                                  multiplication over ${\rm GF}(2^m)$  . . 945--959
                 A. Gentile and   
                    D. S. Wills   Portable video supercomputing  . . . . . 960--973
                   T. Heath and   
                E. Pinheiro and   
                     J. Hom and   
                  U. Kremer and   
                   R. Bianchini   Code transformations for
                                  energy-efficient device management . . . 974--987
                    T. Lang and   
                 J. D. Bruguera   Floating-point multiply-add-fused with
                                  reduced latency  . . . . . . . . . . . . 988--1003
                  V. Zyuban and   
                  D. Brooks and   
            Viji Srinivasan and   
                M. Gschwind and   
                Pradip Bose and   
             P. N. Strenski and   
                     P. G. Emma   Integrated analysis of power and
                                  performance for pipelined
                                  microprocessors  . . . . . . . . . . . . 1004--1016
                 U. Anliker and   
                  J. Beutel and   
                    M. Dyer and   
                  R. Enzler and   
                P. Lukowicz and   
                  L. Thiele and   
                     G. Troster   A systematic approach to the design of
                                  distributed wearable systems . . . . . . 1017--1033
                     J. Lee and   
                   F. Peper and   
                  S. Adachi and   
                      K. Morita   Universal delay-insensitive circuits
                                  with bidirectional and buffering lines   1034--1046
                    K. Fong and   
               D. Hankerson and   
                   J. Lopez and   
                     A. Menezes   Field inversion and point halving
                                  revisited  . . . . . . . . . . . . . . . 1047--1059
               J. J. C. H. Ryan   Information security tools and
                                  practices: what works? . . . . . . . . . 1060--1063
               Pao-Lien Lai and   
               J. J. M. Tan and   
          Chang-Hsiung Tsai and   
                  Lih-Hsing Hsu   The diagnosability of the matching
                                  composition network under the comparison
                                  diagnosis model  . . . . . . . . . . . . 1064--1069
              N. Brisebarre and   
               J.-M. Muller and   
            Saurabh Kumar Raina   Accelerating correctly rounded
                                  floating-point division when the divisor
                                  is known in advance  . . . . . . . . . . 1069--1072

IEEE Transactions on Computers
Volume 53, Number 9, September, 2004

              Yonghong Song and   
                    Rong Xu and   
                 Cheng Wang and   
                     Zhiyuan Li   Improving data locality by array
                                  contraction  . . . . . . . . . . . . . . 1073--1084
       J. A. Piñeiro and   
            M. D. Ercegovac and   
                 J. D. Bruguera   Algorithm and Architecture for
                                  Logarithm, Exponential and Powering
                                  Computation  . . . . . . . . . . . . . . 1085--1096
                       B. Sunar   A generalized method for constructing
                                  subquadratic complexity
                                  $\mathrm{GF}(2^k)$ multipliers . . . . . 1097--1105
                 J. A. Carrasco   Transient analysis of some rewarded
                                  Markov models using randomization with
                                  quasistationarity detection  . . . . . . 1106--1120
                I. Pomeranz and   
                    S. M. Reddy   On maximizing the fault coverage for a
                                  given test length limit in a synchronous
                                  sequential circuit . . . . . . . . . . . 1121--1133
              D. Niggemeyer and   
                  E. M. Rudnick   Automatic generation of diagnostic
                                  memory tests based on fault
                                  decomposition and output tracing . . . . 1134--1146
                 M. Llorens and   
                      J. Oliver   Structural and dynamic changes in
                                  concurrent systems: reconfigurable Petri
                                  nets . . . . . . . . . . . . . . . . . . 1147--1158
                    Peng Li and   
                   B. Ravindran   Fast, best-effort real-time scheduling
                                  algorithms . . . . . . . . . . . . . . . 1159--1175
                A. L. Rosenberg   On scheduling mesh-structured
                                  computations for Internet-based
                                  computing  . . . . . . . . . . . . . . . 1176--1186
                V. V. Phoha and   
               A. U. Nadgar and   
                     A. Ray and   
                       S. Phoha   Supervisory control of software systems  1187--1199
                   P. Varma and   
               B. S. Panwar and   
                K. N. Ramganesh   Cutting metastability using aperture
                                  transformation . . . . . . . . . . . . . 1200--1204
             L. Macchiarulo and   
               Shih-Min Shu and   
              M. Marek-Sadowska   Pipelining sequential circuits with wave
                                  steering . . . . . . . . . . . . . . . . 1205--1210
              C. Efstathiou and   
               H. T. Vergos and   
                     D. Nikolos   Fast parallel-prefix modulo $2^n + 1$
                                  adders . . . . . . . . . . . . . . . . . 1211--1216

IEEE Transactions on Computers
Volume 53, Number 10, October, 2004

                  Haibin Lu and   
                   Sartaj Sahni   $O(\log n)$ dynamic router-tables for
                                  prefixes and ranges  . . . . . . . . . . 1217--1230
                  S. Baktir and   
                       B. Sunar   Optimal tower fields . . . . . . . . . . 1231--1243
                 T. Monreal and   
                  V. Vinals and   
                J. Gonzalez and   
                A. Gonzalez and   
                      M. Valero   Late allocation and early release of
                                  physical registers . . . . . . . . . . . 1244--1259
                K. Chanchio and   
                      X.-H. Sun   Communication state transfer for the
                                  mobility of concurrent heterogeneous
                                  computing  . . . . . . . . . . . . . . . 1260--1273
            Rama Sangireddy and   
                     H. Kim and   
                   A. K. Somani   Low-power high-performance
                                  reconfigurable computing cache
                                  architectures  . . . . . . . . . . . . . 1274--1290
              G. R. Redinbo and   
                      C. Nguyen   Concurrent error detection in wavelet
                                  lifting transforms . . . . . . . . . . . 1291--1302
                 T. Okumura and   
                       D. Mosse   Virtualizing network I/O on end-host
                                  operating system: operating system
                                  support for network control and resource
                                  protection . . . . . . . . . . . . . . . 1303--1316
                Shiuh-Jeng Wang   Anonymous wireless authentication on a
                                  portable cellular mobile system  . . . . 1317--1329
                  R. M. Hierons   Testing from a nondeterministic finite
                                  state machine using adaptive state
                                  counting . . . . . . . . . . . . . . . . 1330--1342
                      J. Wu and   
                         F. Dai   A generic distributed broadcast scheme
                                  in ad hoc wireless networks  . . . . . . 1343--1354
                G. Anastasi and   
                 A. Bartoli and   
                    G. Giannini   On causal broadcasting with positive
                                  acknowledgments and bounded-length
                                  counters . . . . . . . . . . . . . . . . 1355--1358
                     R. Baldoni   Response to Comment on ``A Positive
                                  Acknowledgment Protocol for Causal
                                  Broadcasting'' . . . . . . . . . . . . . 1358--1358
                      Anonymous   Call for Papers for Special Issue on
                                  Design and Test of Systems-on-a Chip . . 1359--1359
                      Anonymous   Call for Papers for Special Issue on
                                  Simulation-Based Design Validation . . . 1360--1360

IEEE Transactions on Computers
Volume 53, Number 11, November, 2004

            P. Y. K. Cheung and   
       G. A. Constantinides and   
                 J. T. de Sousa   Guest Editors' Introduction: Field
                                  Programmable Logic and Applications  . . 1361--1362
             S. Vassiliadis and   
                    S. Wong and   
              G. Gaydadjiev and   
                 K. Bertels and   
                G. Kuzmanov and   
                 E. M. Panainte   The MOLEN polymorphic processor  . . . . 1363--1375
                  J. Teifel and   
                     R. Manohar   An asynchronous dataflow FPGA
                                  architecture . . . . . . . . . . . . . . 1376--1392
                 C. Steiger and   
                  H. Walder and   
                    M. Platzner   Operating systems for reconfigurable
                                  embedded platforms: online scheduling of
                                  real-time tasks  . . . . . . . . . . . . 1393--1407
                  H. Styles and   
                         W. Luk   Exploiting program branch probabilities
                                  in hardware compilation  . . . . . . . . 1408--1419
              Joonseok Park and   
                P. C. Diniz and   
            K. R. Shesha Shayee   Performance and area modeling of
                                  complete FPGA designs in the presence of
                                  loop transformations . . . . . . . . . . 1420--1435
                 C. Ebeling and   
                  C. Fisher and   
               Guanbin Xing and   
               Manyuan Shen and   
                        Hui Liu   Implementing an OFDM receiver on the
                                  RaPiD reconfigurable architecture  . . . 1436--1448
               I. Skliarova and   
            A. de Brito Ferrari   Reconfigurable hardware SAT solvers: a
                                  survey of systems  . . . . . . . . . . . 1449--1461
                    E. Bini and   
                 G. C. Buttazzo   Schedulability analysis of periodic
                                  fixed priority systems . . . . . . . . . 1462--1473
                    D. Page and   
                    N. P. Smart   Parallel cryptographic arithmetic using
                                  a redundant Montgomery representation    1474--1482
                   S. Mitra and   
               N. R. Saxena and   
                E. J. McCluskey   Efficient design diversity estimation
                                  for combinational circuits . . . . . . . 1483--1492
                       Feng Bao   Cryptanalysis of a partially known
                                  cellular automata cryptosystem . . . . . 1493--1497
                I. Pomeranz and   
                    S. M. Reddy   A measure of quality for $n$-detection
                                  test sets  . . . . . . . . . . . . . . . 1497--1503
                      Anonymous   Call for Papers for Special Section on
                                  Fault Diagnosis and Tolerance in
                                  Cryptography . . . . . . . . . . . . . . 1504--1504

IEEE Transactions on Computers
Volume 53, Number 12, December, 2004

                 V. K. Prasanna   Editor's Note  . . . . . . . . . . . . . 1505--1507
                M. Meribout and   
                    M. Motomura   A-combined approach to high-level
                                  synthesis for dynamically reconfigurable
                                  systems  . . . . . . . . . . . . . . . . 1508--1522
                  D.-U. Lee and   
                     W. Luk and   
           J. D. Villasenor and   
                P. Y. K. Cheung   A Gaussian noise generator for
                                  hardware-based simulations . . . . . . . 1523--1534
           H. P. Dharmasena and   
                R. Vaidyanathan   Lower bounds on the loading of multiple
                                  bus networks for binary tree algorithms  1535--1546
              Yuanyuan Yang and   
                  Jianchao Wang   Designing WDM optical interconnects with
                                  full connectivity by using limited
                                  wavelength conversion  . . . . . . . . . 1547--1556
                  A. Messer and   
                P. Bernadat and   
                      G. Fu and   
                    D. Chen and   
            Z. Dimitrijevic and   
                     D. Lie and   
              D. D. Mannaru and   
                   A. Riska and   
                   D. Milojicic   Susceptibility of commodity systems and
                                  software to memory soft errors . . . . . 1557--1568
                I. Pomeranz and   
                    S. M. Reddy   Static test compaction for full-scan
                                  circuits based on combinational test
                                  sets and nonscan input sequences and a
                                  lower bound on the number of tests . . . 1569--1581
           Chien-Ping Chang and   
               Pao-Lien Lai and   
       Jimmy Jiann-Mean Tan and   
                  Lih-Hsing Hsu   Diagnosability of $t$-connected networks
                                  and product networks under the
                                  comparison diagnosis model . . . . . . . 1582--1590
                  G. Lipari and   
                G. Lamastra and   
                       L. Abeni   Task synchronization in
                                  reservation-based real-time systems  . . 1591--1601
                    Z. Wang and   
                     H. Che and   
                Mohan Kumar and   
                      S. K. Das   CoPTUA: Consistent Policy Table Update
                                  Algorithm for TCAM without locking . . . 1602--1614
                  Haibin Lu and   
                       S. Sahni   Enhanced interval trees for dynamic IP
                                  router-tables  . . . . . . . . . . . . . 1615--1628
                M. X. Cheng and   
                  M. Cardei and   
                 Jinhua Sun and   
             Xiaochun Cheng and   
               Lusheng Wang and   
                Yingfeng Xu and   
                    Ding-Zhu Du   Topology control of ad hoc wireless
                                  networks for energy efficiency . . . . . 1629--1635
                      Anonymous   Annual Index . . . . . . . . . . . . . . 1636--1648


IEEE Transactions on Computers
Volume 54, Number 1, January, 2005

                   G. D. Nguyen   Error-detection codes: algorithms and
                                  fast implementation  . . . . . . . . . . 1--11
              M. E. Kaihara and   
                      N. Takagi   A hardware algorithm for modular
                                  multiplication/division  . . . . . . . . 12--21 54
                 A. Ramirez and   
          J. L. Larriba-Pey and   
                      M. Valero   Software Trace Cache . . . . . . . . . . 22--35
               H. Sabbineni and   
                 K. Chakrabarty   Location-aided flooding: an
                                  energy-efficient data dissemination
                                  protocol for wireless-sensor networks    36--46
                Tei-Wei Kuo and   
            Yung-Sheng Chao and   
                Chin-Fu Kuo and   
                    Cheng Chang   Real-time dwell scheduling of
                                  component-oriented phased array radars   47--60
           I. Bayraktaroglu and   
                   A. Orailoglu   The construction of optimal
                                  deterministic partitionings in
                                  scan-based BIST fault diagnosis:
                                  mathematical foundations and
                                  cost-effective implementations . . . . . 61--75
                C. Kulkarni and   
                    C. Ghez and   
                 M. Miranda and   
                F. Catthoor and   
                      H. De Man   Cache conscious data layout organization
                                  for conflict miss reduction in embedded
                                  multimedia applications  . . . . . . . . 76--81
              P. G. Sassone and   
                    D. S. Wills   Scaling up the Atlas chip-multiprocessor 82--87
                G. Umanesan and   
                    E. Fujiwara   Parallel decoding cyclic burst error
                                  correcting codes . . . . . . . . . . . . 87--92
                      Anonymous   Reviewers List . . . . . . . . . . . . . 93--96

IEEE Transactions on Computers
Volume 54, Number 2, February, 2005

             V. K. Prasanna and   
                    F. Lombardi   Editor's Note  . . . . . . . . . . . . . 97--97
         A. Reyhani-Masoleh and   
                    M. A. Hasan   Low complexity word-level sequential
                                  normal basis multipliers . . . . . . . . 98--110
               P.-M. Seidel and   
             L. D. McFearin and   
                   D. W. Matula   Secondary radix recodings for higher
                                  radix multipliers  . . . . . . . . . . . 111--123
                    X. Ruan and   
                    R. S. Katti   Left-to-right optimal signed-binary
                                  representation of a pair of integers . . 124--131
                      A. K. Uht   Uniprocessor performance enhancement
                                  through adaptive clock frequency control 132--140
                   J. Burns and   
                  J.-L. Gaudiot   Area and system clock effects on SMT/CMP
                                  throughput . . . . . . . . . . . . . . . 141--152
                   M. Omana and   
                   D. Rossi and   
                       C. Metra   Low cost and high speed embedded
                                  two-rail code checker  . . . . . . . . . 153--164
               Pao-Lien Lai and   
               J. J. M. Tan and   
           Chien-Ping Chang and   
                  Lih-Hsing Hsu   Conditional diagnosability measures for
                                  large multiprocessor systems . . . . . . 165--175
                 Jianxi Fan and   
                     Xiaola Lin   The $t / k$-diagnosability of the BC
                                  graphs . . . . . . . . . . . . . . . . . 176--184
               P. D'Alberto and   
                 A. Nicolau and   
              A. Veidenbaum and   
                   Rajesh Gupta   Line size adaptivity analysis of
                                  parameterized loop nests for direct
                                  mapped data cache  . . . . . . . . . . . 185--197
                 M. Caccamo and   
             G. C. Buttazzo and   
                   D. C. Thomas   Efficient reclaiming in
                                  reservation-based real-time systems with
                                  variable execution times . . . . . . . . 198--213
                          H. Lu   A novel high-order tree for secure
                                  multicast key management . . . . . . . . 214--224
         G. Dimitrakopoulos and   
                     D. Nikolos   High-speed parallel-prefix VLSI Ling
                                  adders . . . . . . . . . . . . . . . . . 225--231
                  L. G. Tallini   Bounds on the capacity of the
                                  unidirectional channels  . . . . . . . . 232--235
                M. Teslenko and   
              A. Martinelli and   
                     E. Dubrova   Bound-set preserving ROBDD variable
                                  orderings may not be optimum . . . . . . 236--237
                 Hyogon Kim and   
                 Jin-Ho Kim and   
                 Inhye Kang and   
                  Saewoong Bahk   Preventing session table explosion in
                                  packet inspection computers  . . . . . . 238--240

IEEE Transactions on Computers
Volume 54, Number 3, March, 2005

         Michael J. Schulte and   
             Jean-Claude Bajard   Guest Editors' Introduction: Special
                                  Issue on Computer Arithmetic . . . . . . 241--242
             Sorin Cotofana and   
             Casper Lageweg and   
           Stamatis Vassiliadis   Addition Related Arithmetic Operations
                                  via Controlled Transport of Charge . . . 243--256
          Roberto Muscedere and   
            Vassil Dimitrov and   
          Graham A. Jullien and   
              William C. Miller   Efficient Techniques for
                                  Binary-to-Multidigit Multidimensional
                                  Logarithmic Number System Conversion
                                  Using Range-Addressable Look-Up Tables   257--271
               Zhijun Huang and   
           Milo\vs D. Ercegovac   High-Performance Low-Power Left-to-Right
                                  Array Multiplier Design  . . . . . . . . 272--283
              Albert Danysh and   
                    Dimitri Tan   Architecture and Implementation of a
                                  Vector/SIMD Multiply-Accumulate Unit . . 284--293
                 Peter Kornerup   Digit Selection for SRT Division and
                                  Square Root  . . . . . . . . . . . . . . 294--303
Jose-Alejandro Piñeiro and   
          Stuart F. Oberman and   
         Jean-Michel Muller and   
             Javier D. Bruguera   High-Speed Function Approximation Using
                                  a Minimax Quadratic Interpolator . . . . 304--318
        Florent de Dinechin and   
               Arnaud Tisserand   Multipartite Table Methods . . . . . . . 319--330
         Nicolas Brisebarre and   
               David Defour and   
             Peter Kornerup and   
         Jean-Michel Muller and   
                 Nathalie Revol   A New Range-Reduction Algorithm  . . . . 331--339
       Damien Stehlé and   
          Vincent Lef\`evre and   
                Paul Zimmermann   Searching Worst Cases of a One-Variable
                                  Function Using Lattice Reduction . . . . 340--346
          Tomás Lang and   
                Elisardo Antelo   High-Throughput CORDIC-Based Geometry
                                  Operations for $3$D Computer Graphics    347--361
            Peter L. Montgomery   Five, Six, and Seven-Term Karatsuba-Like
                                  Formulae . . . . . . . . . . . . . . . . 362--369
          Amir K. Daneshbeh and   
                 M. Anwar Hasan   A Class of Unidirectional Bit Serial
                                  Systolic Architectures for
                                  Multiplicative Inversion and Division
                                  over $\mathrm{GF}(2^m)$  . . . . . . . . 370--380
                      Anonymous   Call For Papers  . . . . . . . . . . . . 381--381

IEEE Transactions on Computers
Volume 54, Number 4, April, 2005

                   D. Baron and   
                     Y. Bresler   Antisequential suffix sorting for
                                  BWT-based data compression . . . . . . . 385--397
         S. V. Anastasiadis and   
                  P. Varman and   
               J. S. Vitter and   
                          Ke Yi   Optimal lexicographic shaping of
                                  aggregate streaming data . . . . . . . . 398--408
                     Z. Ren and   
                B. H. Krogh and   
                  R. Marculescu   Hierarchical adaptive dynamic power
                                  management . . . . . . . . . . . . . . . 409--420
                 M. Volkmer and   
                     S. Wallner   Tree parity machine rekeying
                                  architectures  . . . . . . . . . . . . . 421--427
            A. L. Rosenberg and   
                   M. Yurkewych   Guidelines for scheduling some common
                                  computation-dags for Internet-based
                                  computing  . . . . . . . . . . . . . . . 428--438
                   Jiwu Shu and   
                  Bigang Li and   
                   Weimin Zheng   Design and implementation of an SAN
                                  system based on the fiber channel
                                  protocol . . . . . . . . . . . . . . . . 439--448
                 D. Sokolov and   
                  J. Murphy and   
                 A. Bystrov and   
                    A. Yakovlev   Design and analysis of dual-rail
                                  circuits for security applications . . . 449--460
                N. Kranitis and   
               A. Paschalis and   
              D. Gizopoulos and   
                    G. Xenoulis   Software-based self-testing of embedded
                                  processors . . . . . . . . . . . . . . . 461--475
                   I. Voyiatzis   Test vector embedding into
                                  accumulator-generated sequences: a
                                  linear-time solution . . . . . . . . . . 476--484
                Haining Fan and   
                       Yiqi Dai   Fast bit-parallel $\mathrm{GF}(2^n)$
                                  multiplier for all trinomials  . . . . . 485--490
              C. Efstathiou and   
               H. T. Vergos and   
         G. Dimitrakopoulos and   
                     D. Nikolos   Efficient diminished-$1$ modulo $2^n +
                                  1$ multipliers . . . . . . . . . . . . . 491--496

IEEE Transactions on Computers
Volume 54, Number 5, May, 2005

                    J. Abel and   
                      W. Teahan   Universal text preprocessing for data
                                  compression  . . . . . . . . . . . . . . 497--507
                  J. A. Barnett   Dynamic task-level voltage scheduling
                                  optimizations  . . . . . . . . . . . . . 508--520
            V. C. Ravikumar and   
            R. N. Mahapatra and   
           Laxmi Narayan Bhuyan   EaseCAM: an energy and storage efficient
                                  TCAM-based router architecture for IP
                                  lookup . . . . . . . . . . . . . . . . . 521--533
                Rajgopal Kannan   The KR---Benes network: a
                                  control-optimal rearrangeable
                                  permutation network  . . . . . . . . . . 534--544
                  Haibin Lu and   
                  K. S. Kim and   
                       S. Sahni   Prefix and interval-partitioned dynamic
                                  IP router-tables . . . . . . . . . . . . 545--557
               E. Ardizzoni and   
             A. A. Bertossi and   
              M. C. Pinotti and   
              S. Ramaprasad and   
                   R. Rizzi and   
             M. V. S. Shashanka   Optimal skewed data allocation on
                                  multiple channels with flat broadcast
                                  per channel  . . . . . . . . . . . . . . 558--572
               M. Kharbutli and   
                 Y. Solihin and   
                     Jaejin Lee   Eliminating conflict misses using prime
                                  number-based cache indexing  . . . . . . 573--586
                     Q. Zhu and   
                        Y. Zhou   Power-aware storage cache management . . 587--602
                 D. Avresky and   
                     N. Natchev   Dynamic reconfiguration in computer
                                  clusters with irregular topologies in
                                  the presence of multiple node and link
                                  failures . . . . . . . . . . . . . . . . 603--615
                    J. Yang and   
                   Q. Jiang and   
              D. Manivannan and   
                 Mukesh Singhal   A fault-tolerant distributed channel
                                  allocation scheme for cellular networks  616--629
                   Jun Yang and   
                    Lan Gao and   
                   Youtao Zhang   Improving memory encryption performance
                                  in secure processors . . . . . . . . . . 630--640

IEEE Transactions on Computers
Volume 54, Number 6, June, 2005

                       T. Mudge   Introduction to the Special Section on
                                  Energy Efficient Computing . . . . . . . 641--641
                M. Hariyama and   
                  T. Aoyama and   
                    M. Kameyama   Genetic approach to minimizing energy
                                  consumption of VLSI processors using
                                  multiple supply voltages . . . . . . . . 642--650
                 Suhwan Kim and   
              C. H. Ziesler and   
            M. C. Papaefthymiou   Charge-recovery computing on silicon . . 651--659
                  E. J. Kim and   
                 G. M. Link and   
                  K. H. Yum and   
           N. Vijaykrishnan and   
                M. Kandemir and   
                M. J. Irwin and   
                      C. R. Das   A holistic approach to designing
                                  energy-efficient cluster interconnects   660--671
                M. Jayapala and   
                   F. Barat and   
               T. Vander Aa and   
                F. Catthoor and   
               H. Corporaal and   
                   G. Deconinck   Clustered loop buffer organization for
                                  low energy VLIW embedded processors  . . 672--683
                B. H. Meyer and   
               J. J. Pieper and   
                 J. M. Paul and   
               J. E. Nelson and   
               S. M. Pieper and   
                     A. G. Rowe   Power-performance simulation and design
                                  strategies for single-chip heterogeneous
                                  multiprocessors  . . . . . . . . . . . . 684--697
                A. C. Cheng and   
                    G. S. Tyson   An energy efficient instruction set
                                  synthesis framework for low power
                                  embedded system designs  . . . . . . . . 698--713
                    S. Yang and   
                    W. Wolf and   
               N. Vijaykrishnan   Power and performance analysis of motion
                                  estimation based on hardware and
                                  software realizations  . . . . . . . . . 714--726
              B. H. Calhoun and   
                 D. C. Daly and   
               Naveen Verma and   
         D. F. Finchelstein and   
            D. D. Wentzloff and   
                    A. Wang and   
             Seong-Hwan Cho and   
             A. P. Chandrakasan   Design considerations for ultra-low
                                  energy wireless microsensor nodes  . . . 727--740
                J. H. Tseng and   
                    K. Asanovic   A speculative control scheme for an
                                  energy-efficient banked register file    741--751
              Swarup Bhunia and   
              Animesh Datta and   
          Nilanjan Banerjee and   
                    Kaushik Roy   GAARP: a power-aware GALS architecture
                                  for real-time algorithm-specific tasks   752--766
                   B. Gedik and   
                         L. Liu   A scalable peer-to-peer architecture for
                                  distributed information monitoring
                                  applications . . . . . . . . . . . . . . 767--782
                      Anonymous   Correction to ``Efficient Reclaiming in
                                  Reservation-Based Real-Time Systems with
                                  Variable Execution Times'' . . . . . . . 783--783
                      Anonymous   Call for Papers for Special Issue on
                                  Nano Systems and Computing . . . . . . . 784--784

IEEE Transactions on Computers
Volume 54, Number 7, July, 2005

                 V. K. Prasanna   Editor's Note  . . . . . . . . . . . . . 785--787
                R. B. Reese and   
             M. A. Thornton and   
                      C. Traver   A coarse-grain phased logic CPU  . . . . 788--799
          H. Vandierendonck and   
                K. De Bosschere   XOR-based hash functions . . . . . . . . 800--812
                      H. Lu and   
                   Sartaj Sahni   A B-tree dynamic router-table design . . 813--824
              E. M. Schwarz and   
              M. Schmookler and   
                    S. D. Trong   FPU implementations with denormalized
                                  numbers  . . . . . . . . . . . . . . . . 825--836
                  E. Antelo and   
                    T. Lang and   
               P. Montuschi and   
                  A. Nannarelli   Digit-recurrence dividers with reduced
                                  logical depth  . . . . . . . . . . . . . 837--851
                 R. Granger and   
                    D. Page and   
                        M. Stam   Hardware and software normal basis
                                  arithmetic for pairing-based
                                  cryptography in characteristic three . . 852--860
               T. Wollinger and   
                   J. Pelzl and   
                        C. Paar   Cantor versus Harley: optimization and
                                  analysis of explicit formulae for
                                  hyperelliptic curve cryptosystems  . . . 861--872
                     X. Sun and   
                     Y. Q. Zhao   An on-chip IP address lookup algorithm   873--885
            Sanghamitra Roy and   
                 Prith Banerjee   An algorithm for trading off
                                  quantization error with hardware
                                  resources for MATLAB-based FPGA design   886--896
                    H. Zhou and   
                    T. M. Conte   Enhancing memory-level parallelism via
                                  recovery-free value prediction . . . . . 897--912
                  A. Seznec and   
                      R. Espasa   Conflict-free accesses to strided
                                  vectors on a banked cache  . . . . . . . 913--916
                  B. K. Lee and   
                     L. K. John   Implications of executing compression
                                  and encryption applications on general
                                  purpose processors . . . . . . . . . . . 917--922
                 C. Alvarez and   
                  J. Corbal and   
                      M. Valero   Fuzzy Memoization for Floating-Point
                                  Multimedia Applications  . . . . . . . . 922--927
                      Anonymous   Call for Papers for Special Issue on
                                  Nano Systems and Computing . . . . . . . 928--928

IEEE Transactions on Computers
Volume 54, Number 8, August, 2005

                     T. Tao and   
                 Amar Mukherjee   Pattern matching in LZW compressed files 929--938
                   S. Jiang and   
                       X. Zhang   Making LRU friendly to weak locality
                                  workloads: a novel replacement algorithm
                                  to improve buffer cache performance  . . 939--952
               R. D. Kenney and   
                  M. J. Schulte   High-Speed Multioperand Decimal Adders   953--963
                     J. Wei and   
                    X. Zhou and   
                       C.-Z. Xu   Robust processing rate allocation for
                                  proportional slowdown differentiation on
                                  Internet servers . . . . . . . . . . . . 964--977
                     Yi Zou and   
                 K. Chakrabarty   A distributed coverage- and
                                  connectivity-centric technique for
                                  selecting active nodes in wireless
                                  sensor networks  . . . . . . . . . . . . 978--991
                       B. Sunar   An efficient basis conversion algorithm
                                  for composite fields with given
                                  representations  . . . . . . . . . . . . 992--997
            R. A. Ravindran and   
               R. M. Senger and   
              E. D. Marsman and   
               G. S. Dasika and   
              M. R. Guthaus and   
               S. A. Mahlke and   
                    R. B. Brown   Partitioning variables across register
                                  windows to reduce spill code in a
                                  low-power processor  . . . . . . . . . . 998--1012
                 A. Durresi and   
            V. K. Paruchuri and   
              S. S. Iyengar and   
                      R. Kannan   Optimized broadcast protocol for sensor
                                  networks . . . . . . . . . . . . . . . . 1013--1024
        Partha Pratim Pande and   
                   C. Grecu and   
                   M. Jones and   
                  A. Ivanov and   
                       R. Saleh   Performance evaluation and design
                                  trade-offs for network-on-chip
                                  interconnect architectures . . . . . . . 1025--1040

IEEE Transactions on Computers
Volume 54, Number 9, September, 2005

               J. T. Butler and   
                   T. Sasao and   
                    M. Matsuura   Average path length of binary decision
                                  diagrams . . . . . . . . . . . . . . . . 1041--1053
                       S. Bique   New characterizations of $2$D discrete
                                  cosine transform . . . . . . . . . . . . 1054--1060
              Chiou-Yng Lee and   
          Jenn-Shyong Horng and   
                I-Chang Jou and   
                    Erl-Huei Lu   Low-complexity bit-parallel systolic
                                  Montgomery multipliers for special
                                  classes of $\mathrm{GF}(2^m)$  . . . . . 1061--1070
                 G.-L. Feng and   
                 R. H. Deng and   
                     F. Bao and   
                     J.-C. Shen   New efficient MDS array codes for RAID.
                                  Part I. Reed--Solomon-like codes for
                                  tolerating three disk failures . . . . . 1071--1080
                    J. Park and   
                       S. Sahni   Maximum lifetime broadcasting in
                                  wireless networks  . . . . . . . . . . . 1081--1090
                    L. Xiao and   
                 Yunhao Liu and   
                       L. M. Ni   Improving unstructured peer-to-peer
                                  systems by adaptive connection
                                  establishment  . . . . . . . . . . . . . 1091--1103
                A. Ermedahl and   
                F. Stappert and   
                     J. Engblom   Clustered worst-case execution-time
                                  calculation  . . . . . . . . . . . . . . 1104--1122
                    K. V. Palem   Energy aware computing through
                                  probabilistic switching: a study of
                                  limits . . . . . . . . . . . . . . . . . 1123--1137
                 Haisang Wu and   
               B. Ravindran and   
               E. D. Jensen and   
                        Peng Li   Time/utility function decomposition
                                  techniques for utility accrual
                                  scheduling algorithms in real-time
                                  distributed systems  . . . . . . . . . . 1138--1153
                A. Petrenko and   
                 N. Yevtushenko   Testing from partial deterministic FSM
                                  specifications . . . . . . . . . . . . . 1154--1165
              H. Hashempour and   
                    F. Lombardi   Application of arithmetic coding to
                                  compression of VLSI test data  . . . . . 1166--1177
                  J. Satran and   
               D. Sheinwald and   
                     I. Shimony   Out of order incremental CRC computation 1178--1181
              Qingchun Chen and   
                Kam-Yiu Lam and   
                    Pingzhi Fan   Comments on ``Distributed Bayesian
                                  algorithms for fault-tolerant event
                                  region detection in wireless sensor
                                  networks'' . . . . . . . . . . . . . . . 1182--1183
                      Anonymous   Call for Papers for Special Issue on
                                  Nano Systems and Computing . . . . . . . 1184--1184

IEEE Transactions on Computers
Volume 54, Number 10, October, 2005

             Wen-mei W. Hwu and   
                    K. V. Palem   Guest Editors' Introduction  . . . . . . 1185--1187
                B. J. Welch and   
             S. O. Kanaujia and   
               A. Seetharam and   
              D. Thirumalai and   
                     A. G. Dean   Supporting demanding hard-real-time
                                  systems with STI . . . . . . . . . . . . 1188--1202
             A. Gordon-Ross and   
                       F. Vahid   Frequent loop detection using efficient
                                  nonintrusive on-chip hardware  . . . . . 1203--1215
                  P. Biswas and   
                     N. D. Dutt   Code size reduction in
                                  heterogeneous-connectivity-based DSPs
                                  using instruction set extensions . . . . 1216--1226
                  E. Gibert and   
                 J. Sanchez and   
                    A. Gonzalez   Distributed data cache designs for
                                  clustered VLIW processors  . . . . . . . 1227--1241
                   A. Darte and   
               R. Schreiber and   
                     G. Villard   Lattice-based memory allocation  . . . . 1242--1257
                N. T. Clark and   
                   H. Zhong and   
                   S. A. Mahlke   Automated custom instruction generation
                                  for domain-specific processor
                                  acceleration . . . . . . . . . . . . . . 1258--1270
                 N. Boullis and   
                   A. Tisserand   Some optimizations of hardware
                                  multiplication by constant matrices  . . 1271--1282
                     D. Pan and   
                        Y. Yang   FIFO-based multicast scheduling
                                  algorithm for virtual output queued
                                  packet switches  . . . . . . . . . . . . 1283--1297
                 Yung-Yuan Chen   Concurrent detection of control flow
                                  errors by hybrid signature monitoring    1298--1313
            Z. Dimitrijevic and   
              R. Rangaswami and   
                    E. Y. Chang   Systems support for preemptive disk
                                  scheduling . . . . . . . . . . . . . . . 1314--1326

IEEE Transactions on Computers
Volume 54, Number 11, November, 2005

               M. Burtscher and   
                 I. Ganusov and   
              S. J. Jackson and   
                      J. Ke and   
          P. Ratanaworabhan and   
                      N. B. Sam   The VPC trace-compression algorithms . . 1329--1344
          J. L. Nunez-Yanez and   
               V. A. Chouliaras   A configurable statistical lossless
                                  compression core based on variable order
                                  Markov modeling and arithmetic coding    1345--1359
                   J. J. Yi and   
                D. J. Lilja and   
                  D. M. Hawkins   Improving computer architecture
                                  simulation methodology by adding
                                  statistical rigor  . . . . . . . . . . . 1360--1373
                 F. Arnault and   
                   T. P. Berger   Design and properties of a new
                                  pseudorandom generator based on a
                                  filtered FCSR automaton  . . . . . . . . 1374--1383
            Sudipta Rakshit and   
                     R. K. Guha   Fair bandwidth sharing in distributed
                                  systems: a game-theoretic approach . . . 1384--1393
                     H. Kim and   
                  S. Rixner and   
                      V. S. Pai   Network interface data caching . . . . . 1394--1408
                       A. Datta   A fault-tolerant protocol for
                                  energy-efficient permutation routing in
                                  wireless networks  . . . . . . . . . . . 1409--1421
                   C. Huang and   
                  T. Abdelzaher   Bounded-latency content distribution
                                  feasibility and evaluation . . . . . . . 1422--1437
                 P. Chandra and   
             A. D. Kshemkalyani   Causality-based predicate detection
                                  across space and time  . . . . . . . . . 1438--1453
              M. Khabbazian and   
             T. A. Gulliver and   
                 V. K. Bhargava   A new minimal average weight
                                  representation for left-to-right point
                                  multiplication methods . . . . . . . . . 1454--1459
                Kanghee Kim and   
                 J. L. Diaz and   
                L. L. Bello and   
                J. M. Lopez and   
              Chang-Gun Lee and   
                  Sang Lyul Min   An exact stochastic analysis of
                                  priority-driven periodic real-time
                                  systems and its approximations . . . . . 1460--1466
                    J. C.-M. Li   Diagnosis of multiple hold-time and
                                  setup-time faults in scan chains . . . . 1467--1472

IEEE Transactions on Computers
Volume 54, Number 12, December, 2005

                 G.-L. Feng and   
                 R. H. Deng and   
                     F. Bao and   
                     J.-C. Shen   New efficient MDS array codes for RAID.
                                  Part II. Rabin-like codes for tolerating
                                  multiple ($>= 4$) disk failures . . . . . 1473--1483
                 J.-P. Kaps and   
                  K. Yuksel and   
                       B. Sunar   Energy scalable universal hashing  . . . 1484--1495
                A. Aggarwal and   
                    M. Franklin   Instruction replication for reducing
                                  delays due to inter-PE communication
                                  latency  . . . . . . . . . . . . . . . . 1496--1507
                       E. Savas   A carry-free architecture for Montgomery
                                  inversion  . . . . . . . . . . . . . . . 1508--1519
                Dong-U. Lee and   
         Altaf Abdul Gaffar and   
               Oskar Mencer and   
                      Wayne Luk   Optimizing hardware function evaluation  1520--1531
                M. W. Heath and   
             W. P. Burleson and   
                   I. G. Harris   Synchro-tokens: a deterministic GALS
                                  methodology for chip-level debug and
                                  test . . . . . . . . . . . . . . . . . . 1532--1546
                       W. Zhang   Replication cache: a small fully
                                  associative cache to improve data cache
                                  reliability  . . . . . . . . . . . . . . 1547--1555
                   O. Mutlu and   
                     H. Kim and   
            D. N. Armstrong and   
                     Y. N. Patt   An analysis of the performance impact of
                                  wrong-path memory references on
                                  out-of-order and runahead execution
                                  processors . . . . . . . . . . . . . . . 1556--1571
                    M. A. Palis   The granularity metric for fine-grain
                                  real-time scheduling . . . . . . . . . . 1572--1583
              M. Chatterjee and   
              G. D. Mandyam and   
                      S. K. Das   Joint reliability of medium access
                                  control and radio link protocol in $3$G
                                  CDMA systems . . . . . . . . . . . . . . 1584--1597
                    J. Chin and   
                     M. Nourani   FITS: an integrated ILP-based test
                                  scheduling environment . . . . . . . . . 1598--1613
              C. N. Hadjicostis   Aliasing probability calculations for
                                  arbitrary compaction under independently
                                  selected random test vectors . . . . . . 1614--1627
             Ku-Young Chang and   
                 Dowon Hong and   
                  Hyun-Sook Cho   Low complexity bit-parallel multiplier
                                  for ${\rm GF}(2^m)$ defined by all-one
                                  polynomials using redundant
                                  representation . . . . . . . . . . . . . 1628--1630
                      Anonymous   2005 Annual Index  . . . . . . . . . . . 1631--1648


IEEE Transactions on Computers
Volume 55, Number 1, January, 2006

             V. K. Prasanna and   
                    F. Lombardi   Editors' Note  . . . . . . . . . . . . . 1--1
                      B. Wu and   
             A. D. Kshemkalyani   Objective-optimal algorithms for
                                  long-term Web prefetching  . . . . . . . 2--17
               R. D. Barnes and   
                 J. W. Sias and   
              E. M. Nystrom and   
                S. J. Patel and   
                 J. Navarro and   
                      W. W. Hwu   Beating in-order stalls with
                                  ``flea-flicker'' two-pass pipelining . . 18--33
             A. Reyhani-Masoleh   Efficient algorithms and architectures
                                  for field multiplication using Gaussian
                                  normal bases . . . . . . . . . . . . . . 34--47
           K. Schmidt-Samoa and   
                   O. Semay and   
                      T. Takagi   Analysis of fractional window recoding
                                  methods and their application to
                                  elliptic curve cryptosystems . . . . . . 48--57
                     X. Luo and   
                    M. Dong and   
                       Y. Huang   On distributed fault-tolerant detection
                                  in wireless sensor networks  . . . . . . 58--70
                   Z. Zhang and   
                        Y. Yang   Optimal scheduling in buffered WDM
                                  interconnects with limited range
                                  wavelength conversion capability . . . . 71--82
               G. Mrugalski and   
               M. Mukherjee and   
                  J. Rajski and   
                      J. Tyszer   High performance dense ring generators   83--87
             Guey-Yun Chang and   
              Gen-Huey Chen and   
                    G. J. Chang   $(t; k)$-Diagnosis for matching
                                  composition networks . . . . . . . . . . 88--92
                      Anonymous   2005 Reviewers List  . . . . . . . . . . 93--96

IEEE Transactions on Computers
Volume 55, Number 2, February, 2006

              Jien-Chung Lo and   
                   C. Metra and   
                    F. Lombardi   Guest Editors' Introduction: Special
                                  Section on Design and Test of
                                  Systems-on-Chip (SoC)  . . . . . . . . . 97--98
             A. D. Pimentel and   
                   C. Erbas and   
                     S. Polstra   A systematic approach to exploring
                                  embedded system architectures at
                                  multiple abstraction levels  . . . . . . 99--112
          T. Phatrapornnant and   
                     M. J. Pont   Reducing jitter in embedded systems
                                  employing a time-triggered software
                                  architecture and dynamic voltage scaling 113--124
           Moo-Kyoung Chung and   
                Chong-Min Kyung   Enhancing performance of HW/SW
                                  cosimulation and coemulation by reducing
                                  communication overhead . . . . . . . . . 125--136
                 D. Kagaris and   
               S. Tragoudas and   
                   S. Kuriakose   InTeRail: a test architecture for
                                  core-based SOCs  . . . . . . . . . . . . 137--149
                    X. Chen and   
                    M. S. Hsiao   Testing embedded sequential cores in
                                  parallel using spectrum-based BIST . . . 150--162
                   S. Mitra and   
                      K. S. Kim   XPAND: an efficient test stimulus
                                  compression technique  . . . . . . . . . 163--173
           A. B. T. Hopkins and   
           K. D. McDonald-Maier   Debug support strategy for
                                  systems-on-chips with multiple processor
                                  cores  . . . . . . . . . . . . . . . . . 174--184
                P. Bernardi and   
           L. M. V. Bolzani and   
              M. Rebaudengo and   
               M. S. Reorda and   
               F. L. Vargas and   
                    M. Violante   A new hybrid fault detection technique
                                  for systems-on-a-chip  . . . . . . . . . 185--198
               D. Ponomarev and   
                   G. Kucuk and   
                       K. Ghose   Dynamic resizing of superscalar datapath
                                  components for energy efficiency . . . . 199--213
                     Qun Li and   
                         D. Rus   Global clock synchronization in sensor
                                  networks . . . . . . . . . . . . . . . . 214--226
                 E. Larsson and   
                        Z. Peng   Power-aware test planning in the early
                                  system-on-chip design exploration
                                  process  . . . . . . . . . . . . . . . . 227--239

IEEE Transactions on Computers
Volume 55, Number 3, March, 2006

                 V. K. Prasanna   Editor's Note  . . . . . . . . . . . . . 241--242
                  W. Jigang and   
                  T. Srikanthan   Reconfiguration algorithms for power
                                  efficient VLSI subarrays with four-port
                                  switches . . . . . . . . . . . . . . . . 243--253
                J. Villalba and   
                    T. Lang and   
                 M. A. Gonzalez   Double-residue modular range reduction
                                  for floating-point hardware
                                  implementations  . . . . . . . . . . . . 254--267
                   J. J. Yi and   
                    D. J. Lilja   Simulation of computer architectures:
                                  simulators, benchmarks, methodologies,
                                  and recommendations  . . . . . . . . . . 268--280
               J. L. Aragon and   
                J. Gonzalez and   
                    A. Gonzalez   Control speculation for energy-efficient
                                  next-generation superscalar processors   281--291
              S. E. Paynter and   
               N. Henderson and   
                J. M. Armstrong   Metastability in asynchronous wait-free
                                  protocols  . . . . . . . . . . . . . . . 292--303
                M. Amirijoo and   
                 J. Hansson and   
                      S. H. Son   Specification and management of QoS in
                                  real-time databases supporting imprecise
                                  computations . . . . . . . . . . . . . . 304--319
                     D. Liu and   
                   X. S. Hu and   
               M. D. Lemmon and   
                        Q. Ling   Firm real-time system scheduling based
                                  on a novel QoS constraint  . . . . . . . 320--333
                      J. Wu and   
                    Wei Lou and   
                         F. Dai   Extended multipoint relays to determine
                                  connected dominating sets in MANETs  . . 334--347
                     M. Favalli   Diversity analysis in the presence of
                                  delay faults affecting duplex systems    348--352

IEEE Transactions on Computers
Volume 55, Number 4, April, 2006

                   J. Jeong and   
                      M. Dubois   Cache replacement algorithms with
                                  nonuniform miss costs  . . . . . . . . . 353--365
                  A. Hodjat and   
                 I. Verbauwhede   Area-throughput trade-offs for fully
                                  pipelined 30 to 70 Gbits/s AES
                                  processors . . . . . . . . . . . . . . . 366--372
                     H. Fan and   
                Yu-Liang Wu and   
            R. C. C. Cheung and   
                         J. Liu   Decomposition design theory and
                                  methodology for arbitrary-shaped switch
                                  boxes  . . . . . . . . . . . . . . . . . 373--384
                   S. Dolev and   
                    Y. A. Haviv   Self-stabilizing microprocessor:
                                  analyzing and overcoming soft errors . . 385--399
                M. E. Gomez and   
           N. A. Nordbotten and   
                   J. Flich and   
                   P. Lopez and   
                  A. Robles and   
                   J. Duato and   
                   T. Skeie and   
                       O. Lysne   A routing methodology for achieving
                                  fault tolerance in direct networks . . . 400--415
                  M. H. Karaata   Self-stabilizing clustering of tree
                                  networks . . . . . . . . . . . . . . . . 416--427
      Karthik Channakeshava and   
            Binoy Ravindran and   
                   E. D. Jensen   Utility accrual channel establishment in
                                  multihop networks  . . . . . . . . . . . 428--442
                  Zili Shao and   
                     C. Xue and   
                   Q. Zhuge and   
                     M. Qiu and   
                   Bin Xiao and   
                   E. H.-M. Sha   Security protection and checking for
                                  embedded system integration against
                                  buffer overflow attacks via
                                  hardware/software  . . . . . . . . . . . 443--453
                      P. Li and   
                      H. Wu and   
            Binoy Ravindran and   
                   E. D. Jensen   A utility accrual scheduling algorithm
                                  for real-time activities with mutual
                                  exclusion resource constraints . . . . . 454--469
                   Qiang Xu and   
                    N. Nicolici   DFT infrastructure for broadside
                                  two-pattern test of core-based SOCs  . . 470--485
               J. Blazewicz and   
             M. Y. Kovalyov and   
               M. Machowiak and   
                D. Trystram and   
                     J. Weglarz   Preemptable malleable task scheduling
                                  problem  . . . . . . . . . . . . . . . . 486--490
                I. Pomeranz and   
                    S. M. Reddy   On generating tests that avoid the
                                  detection of redundant faults in
                                  synchronous sequential circuits with
                                  full scan  . . . . . . . . . . . . . . . 491--495

IEEE Transactions on Computers
Volume 55, Number 5, May, 2006

  Mahadevan Gomathisankaran and   
                       A. Tyagi   Architecture support for $3$D
                                  obfuscation  . . . . . . . . . . . . . . 497--507
              C. Brandolese and   
              W. Fornaciari and   
                 L. Pomante and   
                  F. Salice and   
                      D. Sciuto   Affinity-driven system design
                                  exploration for heterogeneous
                                  multiprocessor SoC . . . . . . . . . . . 508--519
                J. L. Imana and   
              J. M. Sanchez and   
                      F. Tirado   Bit-parallel finite field multipliers
                                  for irreducible trinomials . . . . . . . 520--533
           G. C. Cardarilli and   
                  M. Ottavi and   
              S. Pontarelli and   
                      M. Re and   
                     A. Salsano   Fault localization, error correction,
                                  and graceful degradation in radix 2
                                  signed digit-based adders  . . . . . . . 534--540
                P. Kornerup and   
                   J.-M. Muller   Leading guard digits in finite precision
                                  redundant representations  . . . . . . . 541--548
                F. A. Aloul and   
             K. A. Sakallah and   
                   I. L. Markov   Efficient symmetry breaking for Boolean
                                  satisfiability . . . . . . . . . . . . . 549--558
                  A. Jaleel and   
                       B. Jacob   In-line interrupt handling and lock-up
                                  free translation lookaside buffers
                                  (TLBs) . . . . . . . . . . . . . . . . . 559--574
               Swapan Kumar Ray   Large-capacity high-throughput low-cost
                                  pipelined CAM using pipelined CTAM . . . 575--587
            J. Garcia-Vidal and   
                   M. March and   
                   L. Cerda and   
                  J. Corbal and   
                      M. Valero   A DRAM/SRAM memory scheme for fast
                                  packet buffers . . . . . . . . . . . . . 588--602
             Meongchul Song and   
                       S. Sahni   Approximation algorithms for
                                  multiconstrained quality-of-service
                                  routing  . . . . . . . . . . . . . . . . 603--617
              R. M. Hierons and   
                        H. Ural   Optimizing the length of checking
                                  sequences  . . . . . . . . . . . . . . . 618--629
                A. F. Tenca and   
                    S. Park and   
                 L. A. Tawalbeh   Carry-save representation is
                                  shift-unsafe: the problem and its
                                  solution . . . . . . . . . . . . . . . . 630--635
                 N. A. S. Alwan   A fully pipelined systolic array for
                                  sinusoidal sequence generation . . . . . 636--639

IEEE Transactions on Computers
Volume 55, Number 6, June, 2006

                  C. Gniady and   
                 A. R. Butt and   
                   Y. C. Hu and   
                 Yung-Hsiang Lu   Program counter-based prediction
                                  techniques for dynamic power management  641--658
                  D.-U. Lee and   
           J. D. Villasenor and   
                     W. Luk and   
                 P. H. W. Leong   A hardware Gaussian noise generator
                                  using the Box--Muller method and its
                                  error analysis . . . . . . . . . . . . . 659--671
                Rama Sangireddy   Reducing rename logic complexity for
                                  high-speed and low-power front-end
                                  architectures  . . . . . . . . . . . . . 672--685
                   S. Misra and   
                   B. J. Oommen   An efficient dynamic algorithm for
                                  maintaining all-pairs shortest paths in
                                  stochastic networks  . . . . . . . . . . 686--702
                    S. Song and   
                  Kai Hwang and   
                  Yu-Kwong Kwok   Risk-resilient heuristics and genetic
                                  algorithms for security-assured grid job
                                  scheduling . . . . . . . . . . . . . . . 703--719
               Chih-Hsu Yen and   
                    Bing-Fei Wu   Simple error detection methods for
                                  hardware implementation of Advanced
                                  Encryption Standard  . . . . . . . . . . 720--731
                L. Sterpone and   
                    M. Violante   A new reliability-oriented place and
                                  route algorithm for SRAM-based FPGAs . . 732--744
              Jung-Chun Kao and   
                  R. Marculescu   On optimization of e-textile systems
                                  using redundancy and energy-aware
                                  routing  . . . . . . . . . . . . . . . . 745--756
                G. Malewicz and   
            A. L. Rosenberg and   
                   M. Yurkewych   Toward a theory for scheduling dags in
                                  Internet-based computing . . . . . . . . 757--768
                 Ajay Joshi and   
         Aashish Phansalkar and   
                L. Eeckhout and   
                     L. K. John   Measuring benchmark similarity using
                                  inherent program characteristics . . . . 769--782
                 M. Zachariasen   Comment on ``Computing the shortest
                                  network under a fixed topology'' . . . . 783--784

IEEE Transactions on Computers
Volume 55, Number 7, July, 2006

              F. J. Cazorla and   
       P. M. W. Knijnenburg and   
             R. Sakellariou and   
               E. Fernandez and   
                 A. Ramirez and   
                      M. Valero   Predictable performance in SMT
                                  processors: synergy between the OS and
                                  SMTs . . . . . . . . . . . . . . . . . . 785--799
                  N. Pettis and   
                     L. Cai and   
                 Yung-Hsiang Lu   Statistically optimal dynamic power
                                  management for streaming data  . . . . . 800--814
                    Y. Xiao and   
   Krishnaiyan Thulasiraman and   
                         G. Xue   QoS routing in communication networks:
                                  approximation algorithms based on the
                                  primal simplex method of linear
                                  programming  . . . . . . . . . . . . . . 815--829
                  S. Andrei and   
                 W. N. Chin and   
             A. M. K. Cheng and   
                        M. Lupu   Automatic debugging of real-time systems
                                  based on incremental satisfiability
                                  counting . . . . . . . . . . . . . . . . 830--842
                   T. Izumi and   
                    T. Masuzawa   Condition adaptation in synchronous
                                  consensus  . . . . . . . . . . . . . . . 843--853
             Sun-Yuan Hsieh and   
                  Nai-Wen Chang   Hamiltonian path embedding and
                                  pancyclicity on the Möbius cube with
                                  faulty nodes and faulty edges  . . . . . 854--863
                     T. Xie and   
                         X. Qin   Scheduling security-critical real-time
                                  applications on clusters . . . . . . . . 864--879
                   H. Inoue and   
              D. Stefanovic and   
                     S. Forrest   On the prediction of Java object
                                  lifetimes  . . . . . . . . . . . . . . . 880--892
             Samrat Ganguly and   
          Mainak Chatterjee and   
                    R. Izmailov   Non-real-time content scheduling
                                  algorithms for wireless data networks    893--905
               Seung-Ho Lim and   
                    Kyu-Ho Park   An efficient NAND flash file system for
                                  flash memory storage . . . . . . . . . . 906--912
                  M. Cadoli and   
               F. M. Donini and   
              P. Liberatore and   
                     M. Schaerf   $k$-approximating circuits . . . . . . . 913--917
              Sanjoy Baruah and   
                      N. Fisher   The partitioned multiprocessor
                                  scheduling of deadline-constrained
                                  sporadic task systems  . . . . . . . . . 918--923
            Ching-Nung Yang and   
                  Dong-Jing Lee   Some new efficient second-order
                                  spectral- codes with small lookup tables 924--927
                      Anonymous   Call for Papers for Special Issue on
                                  Emergent Systems, Algorithms, and
                                  Architectures for Speech-Based
                                  Human-Machine Interaction  . . . . . . . 928--928

IEEE Transactions on Computers
Volume 55, Number 8, August, 2006

                R. Mascella and   
                  L. G. Tallini   Efficient $m$-ary balanced codes which
                                  are invariant under symbol permutation   929--946
                  Kai Zheng and   
                     H. Che and   
                Zhijun Wang and   
                    Bin Liu and   
                      Xin Zhang   DPPC-RE: TCAM-based distributed parallel
                                  packet classification with range
                                  encoding . . . . . . . . . . . . . . . . 947--961
              L. Schaelicke and   
                    A. L. Davis   Design trade-offs for user-level I/O
                                  architectures  . . . . . . . . . . . . . 962--973
                   R. Dahab and   
               D. Hankerson and   
                      F. Hu and   
                    M. Long and   
                   J. Lopez and   
                     A. Menezes   Software multiplication using Gaussian
                                  normal bases . . . . . . . . . . . . . . 974--984
             J. Y.-T. Leung and   
                        H. Zhao   Minimizing sum of completion times and
                                  makespan in master-slave systems . . . . 985--999
                   P. M. Mishra   Pipelined computation of scalar
                                  multiplication in elliptic curve
                                  cryptosystems (extended version) . . . . 1000--1010
                N. Hanchate and   
                 N. Ranganathan   Simultaneous interconnect delay and
                                  crosstalk noise optimization through
                                  gate sizing using game theory  . . . . . 1011--1023
              Moon-Hee Choi and   
              Woo-Chan Park and   
             F. Neelamkavil and   
               Tack-Don Han and   
                   Shin-Dug Kim   An effective visibility culling method
                                  based on cache block . . . . . . . . . . 1024--1032
               P. K. Biswas and   
                       S. Phoha   Self-organizing sensor networks for
                                  integrated target surveillance . . . . . 1033--1047
                    J. Park and   
                       S. Sahni   An online heuristic for maximum lifetime
                                  routing in wireless sensor networks  . . 1048--1056
                      Yi Ma and   
              Hongliang Gao and   
                   Huiyang Zhou   Using indexing functions to reduce
                                  conflict aliasing in branch prediction
                                  tables . . . . . . . . . . . . . . . . . 1057--1061
                     M. Gok and   
              M. J. Schulte and   
                   M. G. Arnold   Integer multipliers with overflow
                                  detection  . . . . . . . . . . . . . . . 1062--1066
                S. Dautovic and   
                       L. Novak   A comment on ``Boolean functions
                                  classification via fixed polarity
                                  Reed--Muller form''  . . . . . . . . . . 1067--1069
                      Anonymous   Call for papers --- Special issue on
                                  Emergent Systems, Algorithms, and
                                  Architectures for Speech-Based
                                  Human-Machine Interaction  . . . . . . . 1070--1070
                      Anonymous   IEEE Computer Society Celebrates two
                                  60-year anniversaries  . . . . . . . . . 1071--1071
                      Anonymous   Join the IEEE Computer Society --- Now
                                  with 800 Course Modules for Distance
                                  Learning!  . . . . . . . . . . . . . . . 1072--1072

IEEE Transactions on Computers
Volume 55, Number 9, September, 2006

             L. Breveglieri and   
                       I. Koren   Guest Editors' Introduction: Special
                                  Section on Fault Diagnosis and Tolerance
                                  in Cryptography  . . . . . . . . . . . . 1073--1074
                    D. Page and   
                 F. Vercauteren   A Fault Attack on Pairing-Based
                                  Cryptography . . . . . . . . . . . . . . 1075--1080
                     F. Hao and   
                R. Anderson and   
                     J. Daugman   Combining Crypto with Biometrics
                                  Effectively  . . . . . . . . . . . . . . 1081--1088
         A. Reyhani-Masoleh and   
                    M. A. Hasan   Fault Detection Architectures for Field
                                  Multiplication Using Polynomial Bases    1089--1103
                  Y. Monnet and   
                M. Renaudin and   
                    R. Leveugle   Designing Resistant Circuits against
                                  Malicious Faults Injection Using
                                  Asynchronous Logic . . . . . . . . . . . 1104--1115
                      C. Giraud   An RSA Implementation Resistant to Fault
                                  Attacks and to Simple Power Analysis . . 1116--1120
               Arnab Sarkar and   
          P. P. Chakrabarti and   
                   Rajeev Kumar   Frame-Based Proportional Round-Robin . . 1121--1129
                    J. Wang and   
                    M. Yang and   
                    B. Yang and   
                    S. Q. Zheng   Dual-Homing Based Scalable Partia
                                  Multicast Protection . . . . . . . . . . 1130--1141
                  S.-W. Lee and   
                  J.-L. Gaudiot   Throttling-Based Resource Management in
                                  High Performance Multithreaded
                                  Architectures  . . . . . . . . . . . . . 1142--1152
                   O. Ergin and   
                  D. Balkan and   
               D. Ponomarev and   
                       K. Ghose   Early Register Deallocation Mechanisms
                                  Using Checkpointed Register Files  . . . 1153--1166
               J.-C. Bajard and   
                  L. Imbert and   
                       C. Negre   Arithmetic Operations in Finite Fields
                                  of Medium Prime Characteristic Using the
                                  Lagrange Representation  . . . . . . . . 1167--1177
                    Y. Ling and   
                    S. Chen and   
                C.-Y. J. Chiang   On Optimal Deadlock Detection Scheduling 1178--1187
              M. Ciesielski and   
              Priyank Kalla and   
                       S. Askar   Taylor Expansion Diagrams: a Canonical
                                  Representation for Verification of Data
                                  Flow Designs . . . . . . . . . . . . . . 1188--1201
                     H. Fan and   
                    M. A. Hasan   Relationship between $\mathrm{GF}(2^m)$
                                  Montgomery and Shifted Polynomial Basis
                                  Multiplication Algorithms  . . . . . . . 1202--1206
                   Rui Deng and   
                     Yujie Zhou   Improvement to Montgomery Modular
                                  Inverse Algorithm  . . . . . . . . . . . 1207--1210
                Sun-Mi Park and   
             Ku-Young Chang and   
                     Dowon Hong   Efficient Bit-Parallel Multiplier for
                                  Irreducible Pentanomials Using a Shifted
                                  Polynomial Basis . . . . . . . . . . . . 1211--1215
                      Anonymous   Call for papers --- Special issue on
                                  Emergent Systems, Algorithms, and
                                  Architectures for Speech-Based
                                  Human-Machine Interaction  . . . . . . . 1216--1216

IEEE Transactions on Computers
Volume 55, Number 10, October, 2006

                    J. D. Golic   New Methods for Digital Generation and
                                  Postprocessing of Random Data  . . . . . 1217--1229
                   N. Joshi and   
            J. Sundararajan and   
                      K. Wu and   
                    Bo Yang and   
                       R. Karri   Tamper Proofing by Design Using
                                  Generalized Involution-Based Concurrent
                                  Error Detection for Involutional
                                  Substitution Permutation and Feistel
                                  Networks . . . . . . . . . . . . . . . . 1230--1239
               S. Rajagopal and   
                J. R. Cavallaro   Truncated Online Arithmetic with
                                  Applications to Communication Systems    1240--1252
                 J.-Y. Kang and   
                  J.-L. Gaudiot   A Simple High-Speed Multiplier Design    1253--1258
                 K. Frikken and   
                 M. Atallah and   
                          J. Li   Attribute-Based Access Control with
                                  Hidden Policies and Hidden Credentials   1259--1270
             H. Ozdoganoglu and   
           T. N. Vijaykumar and   
              C. E. Brodley and   
             B. A. Kuperman and   
                      A. Jalote   SmashGuard: a Hardware Solution to
                                  Prevent Security Attacks on the Function
                                  Return Address . . . . . . . . . . . . . 1271--1285
                   Hong Luo and   
                     J. Luo and   
                     Y. Liu and   
                      S. K. Das   Adaptive Data Fusion for Energy
                                  Efficient Routing in Wireless Sensor
                                  Networks . . . . . . . . . . . . . . . . 1286--1299
                    X. Ruan and   
                    R. S. Katti   A New Source Coding Scheme with Small
                                  Expected Length and Its Application to
                                  Simple Data Encryption . . . . . . . . . 1300--1305
              Sandeep Kumar and   
               T. Wollinger and   
                        C. Paar   Optimum Digit Serial $\mathrm{GF}(2^m)$
                                  Multipliers for Curve-Based Cryptography 1306--1311
                      Anonymous   Join the IEEE Computer Society!  . . . . 1312--1312

IEEE Transactions on Computers
Volume 55, Number 11, November, 2006

                   I. G. Harris   Guest Editor's Introduction to the
                                  Special Section on Simulation-Based
                                  Design Validation  . . . . . . . . . . . 1313--1314
                   D. Babic and   
                 J. Bingham and   
                       A. J. Hu   B-Cubing: New Possibilities for
                                  Efficient SAT-Solving  . . . . . . . . . 1315--1324
                 Qingwei Wu and   
                    M. S. Hsiao   A New Simulation-Based Property Checking
                                  Algorithm Based on Partitioned
                                  Alternative Search Space Traversal . . . 1325--1334
               C. H.-P. Wen and   
                  Li-C Wang and   
               Kwang-Ting Cheng   Simulation-Based Functional Test
                                  Generation for Embedded Processors . . . 1335--1343
                    S. Fine and   
                  A. Freund and   
                  I. Jaeger and   
                 Y. Mansour and   
                   Y. Naveh and   
                         A. Ziv   Harnessing Machine Learning to Improve
                                  the Success Rate of Stimuli Generation   1344--1355
              Chia-Chih Yen and   
                  Jing-Yang Jou   An Optimum Algorithm for Compacting
                                  Error Traces for Efficient Design Error
                                  Debugging  . . . . . . . . . . . . . . . 1356--1366
                 H. Azatchi and   
                L. Fournier and   
                  E. Marcus and   
                      S. Ur and   
                     A. Ziv and   
                       K. Zohar   Advanced Analysis Techniques for
                                  Cross-Product Coverage . . . . . . . . . 1367--1379
               P. Schaumont and   
                   D. Hwang and   
              Shenglin Yang and   
                 I. Verbauwhede   Multilevel Design Validation in a Secure
                                  Embedded System  . . . . . . . . . . . . 1380--1390
                  S. Suhaib and   
             D. Mathaikutty and   
                  D. Berner and   
                      S. Shukla   Validating Families of Latency
                                  Insensitive Protocols  . . . . . . . . . 1391--1401
              R. C.-W. Phan and   
                  M. U. Siddiqi   A Framework for Describing Block Cipher
                                  Cryptanalysis  . . . . . . . . . . . . . 1402--1409
                  Zeng Zeng and   
                  B. Veeravalli   Design and Performance Evaluation of
                                  Queue-and-Rate-Adjustment Dynamic Load
                                  Balancing Policies for Distributed
                                  Networks . . . . . . . . . . . . . . . . 1410--1422
             P. Oikonomakos and   
                   M. Zwolinski   On the Design of Self-Checking
                                  Controllers with Datapath Interactions   1423--1434
          Shiann-Tsong Sheu and   
                  Yue-Ru Chuang   A Pipeline-Based Genetic Algorithm
                                  Accelerator for Time-Critical Processes
                                  in Real-Time Systems . . . . . . . . . . 1435--1448
                G. Xenoulis and   
                M. Psarakis and   
              D. Gizopoulos and   
                   A. Paschalis   Testability Analysis and Scalable Test
                                  Generation for High-Speed Floating-Point
                                  Units  . . . . . . . . . . . . . . . . . 1449--1457
                  J. Sarkar and   
                S. Sengupta and   
              M. Chatterjee and   
                     S. Ganguly   Differential FEC and ARQ for Radio Link
                                  Protocols  . . . . . . . . . . . . . . . 1458--1472
                  D. Niyato and   
                     E. Hossain   A Queuing-Theoretic and
                                  Optimization-Based Model for Radio
                                  Resource Management in IEEE 802.16
                                  Broadband Wireless Networks  . . . . . . 1473--1488

IEEE Transactions on Computers
Volume 55, Number 12, December, 2006

                 V. K. Prasanna   Introducing the New Editor-in-Chief of
                                  the IEEE Transactions on Computers . . . 1489--1490
                   O. Mutlu and   
                Hyesoon Kim and   
                     Y. N. Patt   Address-Value Delta (AVD) Prediction: a
                                  Hardware Technique for Efficiently
                                  Parallelizing Dependent Cache Misses . . 1491--1508
                C. Scordino and   
                      G. Lipari   A Resource Reservation Algorithm for
                                  Power-Aware Scheduling of Periodic and
                                  Aperiodic Real-Time Tasks  . . . . . . . 1509--1522
              V. Mahalingam and   
                 N. Ranganathan   Improving Accuracy in Mitchell's
                                  Logarithmic Multiplication Using Operand
                                  Decomposition  . . . . . . . . . . . . . 1523--1535
             Jung Hee Cheon and   
                  Dong Hoon Lee   Use of Sparse and/or Complex Exponents
                                  in Batch Verification of Exponentiations 1536--1542
                Jianbin Wei and   
                 Cheng-Zhong Xu   eQoS: Provisioning of Client-Perceived
                                  End-to-End QoS Guarantees in Web Servers 1543--1556
             Alessandro Mei and   
                       R. Rizzi   Online Permutation Routing in
                                  Partitioned Optical Passive Star
                                  Networks . . . . . . . . . . . . . . . . 1557--1571
            E. Frachtenberg and   
                 F. Petrini and   
               J. Fernandez and   
                       S. Pakin   STORM: Scalable Resource Management for
                                  Large-Scale Parallel Computers . . . . . 1572--1587
               R. Jejurikar and   
                       R. Gupta   Optimized Slowdown in Real-Time Task
                                  Systems  . . . . . . . . . . . . . . . . 1588--1598
             Chang-Gung Lee and   
               Phil-Su Kang and   
             Chi-Sheng Shih and   
                        Lui Sha   Schedulability Envelope for Real-Time
                                  Radar Dwell Scheduling . . . . . . . . . 1599--1613
                Yeim-Kuan Chang   A $2$-Level TCAM Architecture for Ranges 1614--1629
                S. Hamdioui and   
                  Z. Al-Ars and   
              A. J. van de Goor   Opens and Delay Faults in CMOS RAM
                                  Address Decoders . . . . . . . . . . . . 1630--1639
               A. Thomasian and   
                       M. Blaum   Mirrored Disk Organization Reliability
                                  Analysis . . . . . . . . . . . . . . . . 1640--1644
               Baoxing Chen and   
                Wenjun Xiao and   
                     B. Parhami   Internode Distance and Optimal Routing
                                  in a Class of Alternating Group Networks 1645--1648
                      Anonymous   Annual Index . . . . . . . . . . . . . . tc06--tc06


IEEE Transactions on Computers
Volume 56, Number 1, January, 2007

                      Anonymous   Message from the New Editor-in-Chief . . 1--1
                     Tao Li and   
                 L. K. John and   
         A. Sivasubramaniam and   
           N. Vijaykrishnan and   
                       J. Rubio   OS-Aware Branch Prediction: Improving
                                  Microprocessor Control Flow Prediction
                                  for Operating Systems  . . . . . . . . . 2--17
            Xiaotong Zhuang and   
              Hsien-Hsin S. Lee   Reducing Cache Pollution via Dynamic
                                  Data Prefetch Filtering  . . . . . . . . 18--31
                Kun Suk Kim and   
                       S. Sahni   Efficient Construction of Pipelined
                                  Multibit-Trie Router-Tables  . . . . . . 32--43
              Jaewook Chung and   
                 M. Anwar Hasan   Low-Weight Polynomial Form Integers for
                                  Efficient Modular Multiplication . . . . 44--57
         M. J. Akhbarizadeh and   
                 M. Nourani and   
               R. Panigrahy and   
                      S. Sharma   A TCAM-Based Parallel Architecture for
                                  High-Speed Packet Forwarding . . . . . . 58--72
             Guey-Yun Chang and   
              Gen-Huey Chen and   
                    G. J. Chang   $(t, k)$-Diagnosis for Matching
                                  Composition Networks under the MM* Model 73--79
               Jiannong Cao and   
                Guojun Wang and   
                  K. C. C. Chan   A Fault-Tolerant Group Communication
                                  Protocol in Large Scale and Highly
                                  Dynamic Mobile Next-Generation Networks  80--94
                 Song Jiang and   
                   K. Davis and   
                 Xiaodong Zhang   Coordinated Multilevel Buffer Cache
                                  Management with Consistent Access
                                  Locality Quantification  . . . . . . . . 95--108
                   B. Sunar and   
               W. J. Martin and   
                  D. R. Stinson   A Provably Secure True Random Number
                                  Generator with Built-In Tolerance to
                                  Active Attacks . . . . . . . . . . . . . 109--119
                  A. Sehgal and   
                 K. Chakrabarty   Optimization of Dual-Speed TAM
                                  Architectures for Efficient Modular
                                  Testing of SOCs  . . . . . . . . . . . . 120--133
                E. L. Lloyd and   
                   Guoliang Xue   Relay Node Placement in Wireless Sensor
                                  Networks . . . . . . . . . . . . . . . . 134--138
                      Anonymous   2006 Reviewers List  . . . . . . . . . . 139--143
                      Anonymous   Call for Papers for Special Issue on
                                  Computer Arithmetic  . . . . . . . . . . 144--144

IEEE Transactions on Computers
Volume 56, Number 2, February, 2007

                   A. Dehon and   
                 C. S. Lent and   
                    F. Lombardi   Introduction to the Special Section on
                                  Nano Systems and Computing . . . . . . . 145--146
         Ravi K. Venkatesan and   
         Ahmed S. Al-Zawawi and   
   Krishnan Sivasubramanian and   
                 Eric Rotenberg   ZettaRAM: a Power-Scalable DRAM
                                  Alternative through Charge-Voltage
                                  Decoupling . . . . . . . . . . . . . . . 147--160
               Love Kothari and   
             Nicholas P. Carter   Architecture of a Self-Checkpointing
                                  Microprocessor that Incorporates
                                  Nanomagnetic Devices . . . . . . . . . . 161--173
           Saket Srivastava and   
                Sanjukta Bhanja   Hierarchical Probabilistic Macromodeling
                                  for QCA Circuits . . . . . . . . . . . . 174--190
 Omar Paranaiba Vilela Neto and   
   Marco Aurelio C. Pacheco and   
         Carlos R. Hall Barbosa   Neural Network Simulation and
                                  Evolutionary Synthesis of QCA Circuits   191--201
               Zeljko Zilic and   
              Katarzyna Radecka   Scaling and Better Approximating Quantum
                                  Fourier Transform by Higher Radices  . . 202--207
          Joseph J. Sharkey and   
            Dmitry V. Ponomarev   Exploiting Operand Availability for
                                  Efficient Simultaneous Multithreading    208--223
                Haining Fan and   
                 M. Anwar Hasan   A New Approach to Subquadratic Space
                                  Complexity Parallel Multipliers for
                                  Extended Binary Fields . . . . . . . . . 224--233
              Wu-Chuan Yang and   
                 D. J. Guan and   
                  Chi Sung Laih   Fast Multicomputation with Asynchronous
                                  Strategy . . . . . . . . . . . . . . . . 234--242
                  Han Liang and   
              Piyush Mishra and   
                      Kaijie Wu   Error Correction On-Demand: a Low Power
                                  Register Transfer Level Concurrent Error
                                  Correction Technique . . . . . . . . . . 243--252
           Giorgio Buttazzo and   
              Manel Velasco and   
                      Pau Marti   Quality-of-Control Management in
                                  Overloaded Real-Time Systems . . . . . . 253--266
               Juan Piernas and   
                Toni Cortes and   
                 Jose M. Garcia   The Design of New Journaling File
                                  Systems: The DualFS Case . . . . . . . . 267--281
                  Gang Chen and   
               Guoqiang Bai and   
                    Hongyi Chen   A New Systolic Architecture for Modular
                                  Division . . . . . . . . . . . . . . . . 282--286
                      Anonymous   Call for Papers for Special Section on
                                  Computer Arithmetic  . . . . . . . . . . 287--287
                      Anonymous   IEEE Computer Society Digital Library    288--288

IEEE Transactions on Computers
Volume 56, Number 3, March, 2007

                J. D. Bakos and   
            D. M. Chiarulli and   
                  S. P. Levitan   Lightweight Error Correction Coding for
                                  System-Level Interconnects . . . . . . . 289--304
              M. Khabbazian and   
             T. A. Gulliver and   
                 V. K. Bhargava   Double Point Compression with
                                  Applications to Speeding Up Random Point
                                  Multiplication . . . . . . . . . . . . . 305--313
              K. W. Cameron and   
                      R. Ge and   
                      X.-H. Sun   $\log_n{\rm P}$ and $log_3{\rm P}$:
                                  Accurate Analytical Models of
                                  Point-to-Point Communication in
                                  Distributed Systems  . . . . . . . . . . 314--327
                   Y. Zhong and   
              S. G. Dropsho and   
                    X. Shen and   
                  A. Studer and   
                        C. Ding   Miss Rate Prediction Across Program
                                  Inputs and Cache Configurations  . . . . 328--343
                  F. Harada and   
                   T. Ushio and   
                    Y. Nakamoto   Adaptive Resource Allocation Control for
                                  Fair QoS Management  . . . . . . . . . . 344--357
                   X. Zhong and   
                       C.-Z. Xu   Energy-Aware Modeling and Scheduling for
                                  Dynamic Voltage Scaling with Statistical
                                  Real-Time Guarantee  . . . . . . . . . . 358--372
             Hyeonjoong Cho and   
               B. Ravindran and   
                   E. D. Jensen   Space-Optimal, Wait-Free Real-Time
                                  Synchronization  . . . . . . . . . . . . 373--384
                   U. Balli and   
                      H. Wu and   
               B. Ravindran and   
             J. S. Anderson and   
                   E. D. Jensen   Utility Accrual Real-Time Scheduling
                                  under Variable Cost Functions  . . . . . 385--401
          James Chien-Mo Li and   
               Hung-Mao Lin and   
                  Fang-Min Wang   Column Parity Row Selection (CPRS) BIST
                                  Diagnosis Technique: Modeling and
                                  Analysis . . . . . . . . . . . . . . . . 402--414
                   C. Metra and   
                   D. Rossi and   
                      T. M. Mak   Won't On-Chip Clock Calibration
                                  Guarantee Performance Boost and Product
                                  Quality? . . . . . . . . . . . . . . . . 415--428
                 K. W. Tang and   
                      R. Kamoua   An Upper Bound for the Bisection Width
                                  of a Diagonal Mesh . . . . . . . . . . . 429--431
                      Anonymous   Call for Papers for Special Section on
                                  Networks-on-Chips: Modeling, Analysis
                                  and Optimization . . . . . . . . . . . . 432--432

IEEE Transactions on Computers
Volume 56, Number 4, April, 2007

                 M. Anantha and   
                    B. Bose and   
                  L. G. Tallini   ARQ Protocols and Unidirectional Codes   433--443
                 T. Horvath and   
              T. Abdelzaher and   
                 K. Skadron and   
                        Xue Liu   Dynamic Voltage Scaling in Multitier Web
                                  Servers with End-to-End Delay Control    444--458
              Sang Seok Lim and   
                    Kyu Ho Park   TPF: TCP Plugged File System for
                                  Efficient Data Delivery over TCP . . . . 459--473
                 F. Z. Wang and   
                      S. Wu and   
                  N. Helian and   
               M. A. Parker and   
                     Y. Guo and   
                    Y. Deng and   
                    V. R. Khare   Grid-Oriented Storage: a Single-Image,
                                  Cross-Domain, High-Bandwidth
                                  Architecture . . . . . . . . . . . . . . 474--487
                     M. Lee and   
               Euiseong Seo and   
                Joonwon Lee and   
                    Jin-soo Kim   PABC: Power-Aware Buffer Cache
                                  Management for Low Power Consumption . . 488--501
                      R. Melhem   Low Diameter Interconnections for
                                  Routing in High-Performance Parallel
                                  Systems  . . . . . . . . . . . . . . . . 502--510
                     A. Sen and   
                     V. K. Garg   Formal Verification of Simulation Traces
                                  Using Computation Slicing  . . . . . . . 511--527
                  A. Fedeli and   
                   F. Fummi and   
                  G. Pravadelli   Properties Incompleteness Evaluation by
                                  Functional Verification  . . . . . . . . 528--544
                Xiaoyu Ruan and   
                    R. S. Katti   Data-Independent Pattern Run-Length
                                  Compression for Testing Embedded Cores
                                  in SoCs  . . . . . . . . . . . . . . . . 545--556
                 Dong Xiang and   
                  Kaiwei Li and   
               Jiaguang Sun and   
                    H. Fujiwara   Reconfigured Scan Forest for Test
                                  Application Cost, Test Data Volume, and
                                  Test Power Reduction . . . . . . . . . . 557--562
                  H. Fujita and   
                    K. Sakaniwa   Modified Low-Density MDS Array Codes for
                                  Tolerating Double Disk Failures in Disk
                                  Arrays . . . . . . . . . . . . . . . . . 563--566
                  D.-U. Lee and   
               J. D. Villasenor   A Bit-Width Optimization Methodology for
                                  Polynomial-Based Function Evaluation . . 567--571
                R. A. Patel and   
                M. Benaissa and   
                   S. Boussakta   Fast Modulo $2^n - (2^{n - 2} + 1)$
                                  Addition: a New Class of Adder for RNS   572--576

IEEE Transactions on Computers
Volume 56, Number 5, May, 2007

                   U. Gupta and   
                 N. Ranganathan   Multievent Crisis Management Using
                                  Noncooperative Multistep Games . . . . . 577--589
                W. H. D. Ng and   
                 M. Howarth and   
                     Z. Sun and   
                 H. Cruickshank   Dynamic Balanced Key Tree Management for
                                  Secure Multicast Communications  . . . . 590--605
                 F. Poletti and   
                A. Poggiali and   
                D. Bertozzi and   
                  L. Benini and   
                 P. Marchal and   
                   M. Loghi and   
                     M. Poncino   Energy-Efficient Multiprocessor
                                  Systems-on-Chip for Embedded Computing:
                                  Exploring Programming Models and Their
                                  Architectural Support  . . . . . . . . . 606--621
                     S. Kyo and   
                 S. Okazaki and   
                        T. Arai   An Integrated Memory Array Processor for
                                  Embedded Image Recognition Systems . . . 622--634
             L. Breveglieri and   
                   I. Koren and   
                     P. Maistri   An Operation-Centered Approach to Fault
                                  Detection in Symmetric Cryptography
                                  Ciphers  . . . . . . . . . . . . . . . . 635--649
                     Z. Pan and   
                   M. A. Breuer   Estimating Error Rate in Defective Logic
                                  Using Signature Analysis . . . . . . . . 650--661
                 K. Compton and   
                       S. Hauck   Automatic Design of Area-Efficient
                                  Configurable ASIC Cores  . . . . . . . . 662--672
               A. Ahmadinia and   
                   C. Bobda and   
               S. P. Fekete and   
                   J. Teich and   
             J. C. van der Veen   Optimal Free-Space Management and
                                  Routing-Conscious Dynamic Placement for
                                  Reconfigurable Devices . . . . . . . . . 673--680
                  Y.-H. Dai and   
                     Y. Pan and   
                         X. Zou   A Hierarchical Modeling and Analysis for
                                  Grid Service Reliability . . . . . . . . 681--691
             Pao-Ann Hsiung and   
               Yean-Ru Chen and   
                   Yen-Hung Lin   Model Checking Safety-Critical Systems
                                  Using Safecharts . . . . . . . . . . . . 692--705
                        S. Imre   Quantum Existence Testing and Its
                                  Application for Finding Extreme Values
                                  in Unsorted Databases  . . . . . . . . . 706--710
               Wei-Chieh Ke and   
              Bing-Hong Liu and   
                  Ming-Jer Tsai   Constructing a Wireless Sensor Network
                                  to Fully Cover Critical Grids by
                                  Deploying Minimum Sensors on Grid Points
                                  Is NP-Complete . . . . . . . . . . . . . 710--715
                Haining Fan and   
                       A. Hasan   Comments on ``Five, Six, and Seven-Term
                                  Karatsuba-Like Formulae''  . . . . . . . 716--717
                    R. West and   
                       Y. Zhang   Comments on ``Dynamic Window-Constrained
                                  Scheduling of Real-Time Streams in Media
                                  Servers''  . . . . . . . . . . . . . . . 718--719
                      Anonymous   Call for Papers for Special Section on
                                  Programming Models and Architectures for
                                  Embedded Systems . . . . . . . . . . . . 720--720

IEEE Transactions on Computers
Volume 56, Number 6, June, 2007

              Fabrizio Lombardi   Editor's Note  . . . . . . . . . . . . . 721--726
                 Tomas Lang and   
             Alberto Nannarelli   A Radix-10 Digit-Recurrence Division
                                  Unit: Algorithm and Architecture . . . . 727--739
                    Li Zhao and   
               L. N. Bhuyan and   
                    R. Iyer and   
                S. Makineni and   
                      D. Newell   Hardware Support for Accelerating Data
                                  Movement in Server Platform  . . . . . . 740--753
              Kwangjin Park and   
                 Hyunseung Choo   Energy-Efficient Data Dissemination
                                  Schemes for Nearest Neighbor Query
                                  Processing . . . . . . . . . . . . . . . 754--768
            Yeim-Kuan Chang and   
                 Yung-Chieh Lin   Dynamic Segment Trees for Ranges and
                                  Prefixes . . . . . . . . . . . . . . . . 769--784
             S. Almukhaizim and   
                      Y. Makris   Concurrent Error Detection Methods for
                                  Asynchronous Burst-Mode Machines . . . . 785--798
               A. Thomasian and   
                      G. Fu and   
                         C. Han   Performance of Two-Disk Failure-Tolerant
                                  Disk Arrays  . . . . . . . . . . . . . . 799--814
                  Y. C. Lee and   
                   A. Y. Zomaya   Practical Scheduling of Bag-of-Tasks
                                  Applications on Grids with Dynamic
                                  Resilience . . . . . . . . . . . . . . . 815--825
                   T. Sasao and   
                S. Nagayama and   
                   J. T. Butler   Numerical Function Generators Using LUT
                                  Cascades . . . . . . . . . . . . . . . . 826--838
               D. R. Llanos and   
                   D. Orden and   
                       B. Palop   New Scheduling Strategies for Randomized
                                  Incremental Algorithms in the Context of
                                  Speculative Parallelization  . . . . . . 839--852
                 L. Allulli and   
                 R. Baldoni and   
                   L. Laura and   
             S. T. Piergiovanni   On the Complexity of Removing Z-Cycles
                                  from a Checkpoints and Communication
                                  Pattern  . . . . . . . . . . . . . . . . 853--858
                     G. Xue and   
                    S. K. Makki   Multiconstrained QoS Routing: a Norm
                                  Approach . . . . . . . . . . . . . . . . 859--863
                      Anonymous   Call for Papers for the Special Secion
                                  on Programming Models and Achitectures
                                  for Embedded Systems . . . . . . . . . . 864--864

IEEE Transactions on Computers
Volume 56, Number 7, July, 2007

                R. Friedman and   
              A. Mostefaoui and   
                S. Rajsbaum and   
                      M. Raynal   Asynchronous Agreement and Its Relation
                                  with Error-Correcting Codes  . . . . . . 865--875
                    B. Bose and   
                 S. Elmougy and   
                  L. G. Tallini   Systematic $t$-Unidirectional
                                  Error-Detecting Codes over $Z_m$ . . . . 876--880
              M. H. Karaata and   
                    M. G. Gouda   A Stabilizing Deactivation/Reactivation
                                  Protocol . . . . . . . . . . . . . . . . 881--888
                 A. R. Butt and   
                  C. Gniady and   
                       Y. C. Hu   The Performance Impact of Kernel
                                  Prefetching on Buffer Cache Replacement
                                  Algorithms . . . . . . . . . . . . . . . 889--908
                A. H. Namin and   
                 Huapeng Wu and   
                      M. Ahmadi   Comb Architectures for Finite Field
                                  Multiplication in ${\em F}(2^m)$ . . . . 909--916
                  A. Caruso and   
                      S. Chessa   Worst-Case Diagnosis Completeness in
                                  Regular Graphs under the PMC Model . . . 917--924
                  Y.-S. Dai and   
                 G. Levitin and   
                  K. S. Trivedi   Performance and Reliability of
                                  Tree-Structured Grid Services
                                  Considering Data Dependence and Failure
                                  Correlation  . . . . . . . . . . . . . . 925--936
               R. C. Murphy and   
                    P. M. Kogge   On the Memory Access Patterns of
                                  Supercomputer Applications: Benchmark
                                  Selection and Its Implications . . . . . 937--945
                    Ming Ma and   
                  Yuanyuan Yang   Adaptive Triangular Deployment Algorithm
                                  for Unattended Mobile Sensor Networks    946--958
               B. J. Oommen and   
                   S. Misra and   
                   O.-C. Granmo   Routing Bandwidth-Guaranteed Paths in
                                  MPLS Traffic Engineering: a Multiple
                                  Race Track Learning Approach . . . . . . 959--976
               Chan-gun Lee and   
                  A. K. Mok and   
                      P. Konana   Monitoring of Timing Constraints with
                                  Confidence Threshold Requirements  . . . 977--991
              P. Leadbitter and   
                    D. Page and   
                    N. P. Smart   Nondeterministic Multithreading  . . . . 992--998
                 Jia Jingxi and   
              B. Veeravalli and   
                       D. Ghose   Adaptive Load Distribution Strategies
                                  for Divisible Load Processing on
                                  Resource Unaware Multilevel Tree
                                  Networks . . . . . . . . . . . . . . . . 999--1005
                Yu-Chen Kuo and   
                   Teng-Yi Chiu   Comments on ``On the Nondomination of
                                  Cohorts Coteries'' . . . . . . . . . . . 1006--1007
                      Anonymous   Call for Papers: Special-Purpose
                                  Hardware for Cryptography and
                                  Cryptanalysis  . . . . . . . . . . . . . 1008--1008

IEEE Transactions on Computers
Volume 56, Number 8, August, 2007

              Jung-Chun Kao and   
                Radu Marculescu   Minimizing Eavesdropping Risk by
                                  Transmission Power Control in Multihop
                                  Wireless Networks  . . . . . . . . . . . 1009--1023
               F. J. Alfaro and   
              J. L. Sanchez and   
                 M. Menduia and   
                       J. Duato   A Formal Model to Manage the InfiniBand
                                  Arbitration Tables Providing QoS . . . . 1024--1039
             Sung Hoon Baek and   
                    Kyu Ho Park   Matrix-Stripe-Cache-Based Contiguity
                                  Transform for Fragmented Writes in
                                  RAID-5 . . . . . . . . . . . . . . . . . 1040--1054
                 Weigang Wu and   
               Jiannong Cao and   
                   Jin Yang and   
                      M. Raynal   Design and Performance Evaluation of
                                  Efficient Consensus Protocols for Mobile
                                  Ad Hoc Networks  . . . . . . . . . . . . 1055--1070
                 F. Sabrina and   
              S. S. Kanhere and   
                      S. K. Jha   Design, Analysis and Implementation of a
                                  Novel Multiple Resource Scheduler  . . . 1071--1086
                   P. Ghosh and   
                    K. Basu and   
                      S. K. Das   A Novel Photonic Container Switched
                                  Architecture and Scheduler to Design the
                                  Core Transport Network . . . . . . . . . 1087--1104
             Cheng-Yeh Wang and   
               Chin-Bin Kuo and   
                  Jing-Yang Jou   Hybrid Wordlength Optimization Methods
                                  of Pipelined FFT Processors  . . . . . . 1105--1118
                A. M. Jabir and   
                  D. K. Pradhan   A Graph-Based Unified Technique for
                                  Computing and Representing Coefficients
                                  over Finite Fields . . . . . . . . . . . 1119--1132
                A. M. Jabir and   
              D. K. Pradhan and   
                A. K. Singh and   
               T. L. Rajaprabhu   A Technique for Representing Multiple
                                  Output Binary Functions with
                                  Applications to Verification and
                                  Simulation . . . . . . . . . . . . . . . 1133--1145
             X. Kavousianos and   
              E. Kalligeros and   
                     D. Nikolos   Optimal Selective Huffman Coding for
                                  Test-Data Compression  . . . . . . . . . 1146--1152

IEEE Transactions on Computers
Volume 56, Number 9, September, 2007

   Rodrigo Capobianco Guido and   
                    Li Deng and   
                   Shoji Makino   Guest Editors' Introduction: Special
                                  Section on Emergent Systems, Algorithms
                                  and Architectures for Speech-Based
                                  Human-Machine Interaction  . . . . . . . 1153--1155
                   J. Odell and   
                    K. Mukerjee   Architecture, User Interface, and
                                  Enabling Technology in Windows Vista's
                                  Speech Systems . . . . . . . . . . . . . 1156--1168
                M.-l. Faraj and   
                       J. Bigun   Synergy of Lip-Motion and Acoustic
                                  Features in Biometric Speech and Speaker
                                  Recognition  . . . . . . . . . . . . . . 1169--1175
                    R. K. Moore   PRESENCE: a Human-Inspired Architecture
                                  for Speech-Based Human-Machine
                                  Interaction  . . . . . . . . . . . . . . 1176--1188
            Shi-Xiong Zhang and   
                Man-Wai Mak and   
                     H. M. Meng   Speaker Verification via High-Level
                                  Feature Based Phonetic-Class
                                  Pronunciation Modeling . . . . . . . . . 1189--1198
                   S. Sakti and   
                  K. Markov and   
                    S. Nakamura   Incorporating Knowledge Sources Into a
                                  Statistical Acoustic Model for Spoken
                                  Language Communication Systems . . . . . 1199--1211
       José M. Pardo and   
             Xavier Anguera and   
                  Chuck Wooters   Speaker Diarization For
                                  Multiple-Distant-Microphone Meetings
                                  Using Several Sources of Information . . 1212--1224
            Chien-Lin Huang and   
                 Chung-Hsien Wu   Generation of Phonetic Units for
                                  Mixed-Language Speech Recognition Based
                                  on Acoustic and Contextual Analysis  . . 1225--1233
              Chi-Chun Hsia and   
             Chung-Hsien Wu and   
                     Jian-Qi Wu   Conversion Function Clustering and
                                  Selection Using Linguistic and Spectral
                                  Information for Emotional Voice
                                  Conversion . . . . . . . . . . . . . . . 1245--1254
                   M. Omana and   
                   D. Rossi and   
                       C. Metra   Latch Susceptibility to Transient Faults
                                  and New Hardening Approach . . . . . . . 1255--1268
                K. Sakiyama and   
                  L. Batina and   
                 B. Preneel and   
                 I. Verbauwhede   Multicore Curve-Based Cryptoprocessor
                                  with Reconfigurable Modular Arithmetic
                                  Logic Units over $\mathrm{GF}(2^n)$  . . 1269--1282
                     M. Cluzeau   Reconstruction of a Linear Scrambler . . 1283--1291
                    Y. Oren and   
                      A. Shamir   Remote Password Extraction from RFID
                                  Tags . . . . . . . . . . . . . . . . . . 1292--1296

IEEE Transactions on Computers
Volume 56, Number 10, October, 2007

                 M. Anantha and   
                    B. Bose and   
                 B. F. AlBdaiwi   Mixed-Radix Gray Codes in Lee Metric . . 1297--1307
                J. P. David and   
                  K. Kalach and   
                     N. Tittley   Hardware Complexity of Modular
                                  Multiplication and Exponentiation  . . . 1308--1319
                    Luigi Dadda   Multioperand Parallel Decimal Adder: a
                                  Mixed Binary and BCD Approach  . . . . . 1320--1328
                     S. Pal and   
                S. R. Kundu and   
              M. Chatterjee and   
                      S. K. Das   Combinatorial Reverse Auction based
                                  Scheduling in Multi-Rate Wireless
                                  Systems  . . . . . . . . . . . . . . . . 1329--1341
                  L. Desmet and   
               P. Verbaeten and   
                  W. Joosen and   
                    F. Piessens   Enlarging Instruction Streams  . . . . . 1342--1357
                 Haisang Wu and   
               B. Ravindran and   
                   E. D. Jensen   Utility Accrual Real-Time Scheduling
                                  Under the Unimodal Arbitrary Arrival
                                  Model with Energy Bounds . . . . . . . . 1358--1371
                       H. Aydin   Exact Fault-Sensitive Feasibility
                                  Analysis of Real-Time Tasks  . . . . . . 1372--1386
                  Wu Jigang and   
              T. Srikanthan and   
                  Xiaodong Wang   Integrated Row and Column Rerouting for
                                  Reconfiguration of VLSI Arrays with
                                  Four-Port Switches . . . . . . . . . . . 1387--1400
               S. Vasudevan and   
               V. Viswanath and   
              R. W. Sumners and   
                  J. A. Abraham   Automatic Verification of Arithmetic
                                  Circuits in RTL Using Stepwise
                                  Refinement of Term Rewriting Systems . . 1401--1414
                F. A. Aloul and   
                  A. Ramani and   
             K. A. Sakallah and   
                   I. L. Markov   Solution and Optimization of Systems of
                                  Pseudo-Boolean Constraints . . . . . . . 1415--1424
                   Peng Liu and   
                     Jie Li and   
                 S. Jajodia and   
                      P. Ammann   Can-Follow Concurrency Control . . . . . 1425--1430
                    R. Leveugle   Early Analysis of Fault-based Attack
                                  Effects in Secure Circuits . . . . . . . 1431--1434
                Haining Fan and   
                 M. Anwar Hasan   Subquadratic Computational Complexity
                                  Schemes for Extended Binary Field
                                  Multiplication Using Optimal Normal
                                  Bases  . . . . . . . . . . . . . . . . . 1435--1437
                      Anonymous   Call for Papers for Special Section on
                                  Chips and Architectures for Emerging
                                  Technologies and Applications  . . . . . 1438--1438
                      Anonymous   Call for Papers for Special Section on
                                  Special-Purpose Hardware for
                                  Cryptography and Cryptanalysis . . . . . 1439--1439
                      Anonymous   180,000 Computing Articles in the IEEE
                                  Computer Society Digital Library . . . . 1440--1440

IEEE Transactions on Computers
Volume 56, Number 11, November, 2007

            N. AbouGhazaleh and   
             B. R. Childers and   
                   D. Mosse and   
                   R. G. Melhem   Near-Memory Caching for Improved Energy
                                  Consumption  . . . . . . . . . . . . . . 1441--1455
                  R. K. Lam and   
              Dah-Ming Chiu and   
                   J. C. S. Lui   On the Access Pricing and Network
                                  Scaling Issues of Wireless Mesh Networks 1456--1469
                   N. Petra and   
                 D. De Caro and   
               A. G. M. Strollo   A Novel Architecture for Galois Fields
                                  ${\rm GF}(2^m)$ Multipliers Based on
                                  Mastrovito Scheme  . . . . . . . . . . . 1470--1483
                R. A. Patel and   
                   S. Boussakta   Fast Parallel-Prefix Architectures for
                                  Modulo $2^n - 1$ Addition with a Single
                                  Representation of Zero . . . . . . . . . 1484--1492
                S.-A.-A. Touati   On Periodic Register Need in Software
                                  Pipelining . . . . . . . . . . . . . . . 1493--1504
            S. Fischmeister and   
                O. Sokolsky and   
                      Insup Lee   A Verifiable Language for Programming
                                  Real-Time Communication Schedules  . . . 1505--1519
                   A. Joshi and   
                    Yue Luo and   
                     L. K. John   Applying Statistical Sampling for Fast
                                  and Efficient Simulation of Commercial
                                  Workloads  . . . . . . . . . . . . . . . 1520--1533
              Chung-Ho Chen and   
                   Kuo-Su Hsiao   Scalable Dynamic Instruction Scheduler
                                  through Wake-Up Spatial Locality . . . . 1534--1548
                   J. J. Yi and   
                  R. Sendag and   
                D. J. Lilja and   
                  D. M. Hawkins   Speed versus Accuracy Trade-Offs in
                                  Microarchitectural Simulations . . . . . 1549--1563
                    Ge Nong and   
                      Sen Zhang   Efficient Algorithms for the Inverse
                                  Sort Transform . . . . . . . . . . . . . 1564--1574
               Pi-Rong Sheu and   
                  Shan-Tai Chen   On the Hardness of Approximating the
                                  Multicast Delay Variation Problem  . . . 1575--1577
             A. D. Kshemkalyani   Temporal Predicate Detection Using
                                  Synchronized Clocks  . . . . . . . . . . 1578--1584

IEEE Transactions on Computers
Volume 56, Number 12, December, 2007

               E. Touloupis and   
                J. A. Flint and   
           V. A. Chouliaras and   
                     D. D. Ward   Study of the Effects of SEU-Induced
                                  Faults on a Pipeline Protected
                                  Microprocessor . . . . . . . . . . . . . 1585--1596
                   Hui Chen and   
                      Yang Xiao   On-Bound Selection Cache Replacement
                                  Policy for Wireless Data Access  . . . . 1597--1611
               Xiaofan Yang and   
                  Yuan Yan Tang   Efficient Fault Identification of
                                  Diagnosable Systems under the Comparison
                                  Model  . . . . . . . . . . . . . . . . . 1612--1618
                 Dong Xiang and   
              Mingjing Chen and   
                    H. Fujiwara   Using Weighted Scan Enable Signals to
                                  Improve Test Effectiveness of Scan-Based
                                  BIST . . . . . . . . . . . . . . . . . . 1619--1628
                  P. Calyam and   
              Chang-Gun Lee and   
                   E. Ekici and   
                 M. Haffner and   
                       N. Howes   Orchestration of Network-Wide Active
                                  Measurements for Supporting Distributed
                                  Computing Applications . . . . . . . . . 1629--1642
               R. Van Meter and   
                  K. Nemoto and   
                    W. J. Munro   Communication Links for Distributed
                                  Quantum Computation  . . . . . . . . . . 1643--1653
             Guangyan Zhang and   
                   Jiwu Shu and   
                    Wei Xue and   
                   Weimin Zheng   Design and Implementation of an
                                  Out-of-Band Virtualization System for
                                  Large SANs . . . . . . . . . . . . . . . 1654--1665
              R. Pellizzoni and   
                     M. Caccamo   Real-Time Management of Hardware and
                                  Software Tasks for FPGA-based Embedded
                                  Systems  . . . . . . . . . . . . . . . . 1666--1680
                Xiaochun Xu and   
                       S. Sahni   Approximation Algorithms for Sensor
                                  Deployment . . . . . . . . . . . . . . . 1681--1695
               P. Montuschi and   
             J. D. Bruguera and   
               L. Ciminiera and   
                   J.-A. Pieiro   A Digit-by-Digit Algorithm for $m$th
                                  Root Extraction  . . . . . . . . . . . . 1696--1706
               P. Chardaire and   
                  M. Barake and   
                  G. P. McKeown   A PROBE-Based Heuristic for Graph
                                  Partitioning . . . . . . . . . . . . . . 1707--1720
           G. C. Cardarilli and   
              S. Pontarelli and   
                      M. Re and   
                     A. Salsano   Analysis of Errors and Erasures in
                                  Parity Sharing RS Codecs . . . . . . . . 1721--1726
                      Anonymous   Join the IEEE Computer Society . . . . . 1727--1727
                      Anonymous   IEEE Computer Society Digital Library    1728--1728


IEEE Transactions on Computers
Volume 57, Number 1, January, 2008

              Fabrizio Lombardi   State of the Journal . . . . . . . . . . 1--6
             Sung Woo Chung and   
                     K. Skadron   On-Demand Solution to Minimize I-Cache
                                  Leakage Energy with Maintaining
                                  Performance  . . . . . . . . . . . . . . 7--24
                 Yifeng Zhu and   
                     Hong Jiang   RACE: a Robust Adaptive Caching Strategy
                                  for Buffer Cache . . . . . . . . . . . . 25--40
               D. Genbrugge and   
                    L. Eeckhout   Memory Data Flow Modeling in Statistical
                                  Simulation for the Efficient Exploration
                                  of Microprocessor Design Spaces  . . . . 41--54
                   Qishi Wu and   
                 Jinzhu Gao and   
                Mengxia Zhu and   
               N. S. V. Rao and   
                 Jian Huang and   
                  S. S. Iyengar   Self-Adaptive Configuration of
                                  Visualization Pipeline Over Wide-Area
                                  Networks . . . . . . . . . . . . . . . . 55--68
                 Z. Chishti and   
               T. N. Vijaykumar   Optimal Power/Performance Pipeline Depth
                                  for SMT in Scaled Technologies . . . . . 69--81
                  D. Balkan and   
                 J. Sharkey and   
               D. Ponomarev and   
                       K. Ghose   Predicting and Exploiting Transient
                                  Values for Reducing Register File
                                  Pressure and Energy Consumption  . . . . 82--95
               P. Balbastre and   
                  I. Ripoll and   
                      A. Crespo   Minimum Deadline Calculation for
                                  Periodic Real-Time Tasks in Dynamic
                                  Priority Systems . . . . . . . . . . . . 96--109
                Sieteng Soh and   
                L. Hiryanto and   
                         S. Rai   Efficient Prefix Updates for IP Router
                                  Using Lexicographic Ordering and
                                  Updatable Address Set  . . . . . . . . . 110--125
                 G. Gaubatz and   
                   E. Savas and   
                       B. Sunar   Sequential Circuit Design for Embedded
                                  Cryptographic Applications Resilient to
                                  Adversarial Faults . . . . . . . . . . . 126--138
                      Anonymous   Reviewers List . . . . . . . . . . . . . 139--144
                      Anonymous   Annual Index . . . . . . . . . . . . . . ??

IEEE Transactions on Computers
Volume 57, Number 2, February, 2008

                S. Sengupta and   
              M. Chatterjee and   
                     S. Ganguly   Improving Quality of VoIP Streams over
                                  WiMax  . . . . . . . . . . . . . . . . . 145--156
              M. E. Kaihara and   
                      N. Takagi   Bipartite Modular Multiplication Method  157--164
              N. Brisebarre and   
                   J.-M. Muller   Correctly Rounded Multiplication by
                                  Arbitrary Precision Constants  . . . . . 165--174
                 E. Rachlin and   
                   J. E. Savage   Analysis of Mask-Based Nanowire Decoders 175--187
                   Xiao Qin and   
                        Tao Xie   An Availability-Aware Task Scheduling
                                  Strategy for Heterogeneous Systems . . . 188--199
               N. Kavvadias and   
                  S. Nikolaidis   Elimination of Overhead Operations in
                                  Complex Loop Structures for Embedded
                                  Microprocessors  . . . . . . . . . . . . 200--214
                 S. Acharya and   
                R. N. Mahapatra   A Dynamic Slack Management Technique for
                                  Real-Time Distributed Embedded Systems   215--230
             Zhenghao Zhang and   
                    Ming Ma and   
                  Yuanyuan Yang   Energy-Efficient Multihop Polling in
                                  Clusters of Two-Layered Heterogeneous
                                  Sensor Networks  . . . . . . . . . . . . 231--245
              Liqiang Zhang and   
                Qiang Cheng and   
                Yingge Wang and   
                    S. Zeadally   A Novel Distributed Sensor Positioning
                                  System Using the Dual of Target Tracking 246--260
                Hung-Ta Pai and   
                      Y. S. Han   Power-Efficient Direct-Voting Assurance
                                  for Data Fusion in Wireless Sensor
                                  Networks . . . . . . . . . . . . . . . . 261--273
                 M. U. Uyar and   
                S. S. Batth and   
                    Yu Wang and   
                    M. A. Fecko   Algorithms for Modeling a Class of
                                  Single Timing Faults in Communication
                                  Protocols  . . . . . . . . . . . . . . . 274--288

IEEE Transactions on Computers
Volume 57, Number 3, March, 2008

              Patrick Longa and   
                       Ali Miri   Fast and Flexible Elliptic Curve Point
                                  Arithmetic over Prime Fields . . . . . . 289--302
                 M. Nourani and   
             M. Tehranipoor and   
                       N. Ahmed   Low-Transition Test Pattern Generation
                                  for BIST-Based Applications  . . . . . . 303--315
      Mohammad Hosseinabady and   
            Shervin Sharifi and   
          Fabrizio Lombardi and   
            Zainalabedin Navabi   A Selective Trigger Scan Architecture
                                  for VLSI Testing . . . . . . . . . . . . 316--328
                    Tao Xie and   
                       Xiao Qin   An Energy-Delay Tunable Task Allocation
                                  Strategy for Collaborative Applications
                                  in Networked Embedded Systems  . . . . . 329--343
          S. Gopalakrishnan and   
                 M. Caccamo and   
                        Lui Sha   Sharp Thresholds for Scheduling
                                  Recurring Tasks with Distance
                                  Constraints  . . . . . . . . . . . . . . 344--358
                   Jun Wang and   
                 Huijun Zhu and   
                        Dong Li   eRAID: Conserving Energy in Conventional
                                  Disk-Based RAID System . . . . . . . . . 359--374
              Jung-Yup Kang and   
                   S. Gupta and   
                  J.-L. Gaudiot   An Efficient Data-Distribution Mechanism
                                  in a Processor-In-Memory (PIM)
                                  Architecture Applied to Motion
                                  Estimation . . . . . . . . . . . . . . . 375--388
                 T. M. Taha and   
                 D. Scott Wills   An Instruction Throughput Model of
                                  Superscalar Processors . . . . . . . . . 389--403
                  E. Antelo and   
                J. Villalba and   
                   E. L. Zapata   A Low-Latency Pipelined $2$D and $3$D
                                  CORDIC Processors  . . . . . . . . . . . 404--417
                     Yue Yu and   
              Shangping Ren and   
                  Ophir Frieder   Interval-Based Timing Constraints Their
                                  Satisfactions and Applications . . . . . 418--432

IEEE Transactions on Computers
Volume 57, Number 4, April, 2008

               M. Kharbutli and   
                    Yan Solihin   Counter-Based Cache Replacement and
                                  Bypassing Algorithms . . . . . . . . . . 433--447
               C. Gunaratne and   
             K. Christensen and   
                 B. Nordman and   
                        S. Suen   Reducing the Energy Consumption of
                                  Ethernet with Adaptive Link Rate (ALR)   448--461
               Sylvie Boldo and   
            Guillaume Melquiond   Emulation of a FMA and Correctly Rounded
                                  Sums: Proved Algorithms Using Rounding
                                  to Odd . . . . . . . . . . . . . . . . . 462--471
     F. Rodriguez-Henriquez and   
            G. Morales-Luna and   
                       J. Lopez   Low-Complexity Bit-Parallel Square Root
                                  Computation over $\mathrm{GF}(2^{m})$
                                  for All Trinomials . . . . . . . . . . . 472--480
               C. Vuillaume and   
                   K. Okeya and   
                      T. Takagi   Short-Memory Scalar Multiplication for
                                  Koblitz Curves . . . . . . . . . . . . . 481--489
             Byeong-Gyu Nam and   
                Hyejung Kim and   
                    Hoi-Jun Yoo   Power and Area-Efficient Unified
                                  Computation of Vector and Elementary
                                  Functions for Handheld $3$D Graphics
                                  Systems  . . . . . . . . . . . . . . . . 490--504
                   B. Halak and   
                 A. V. Yakovlev   Fault-Tolerant Techniques to Minimize
                                  the Impact of Crosstalk on Phase Encoded
                                  Communication Channels . . . . . . . . . 505--519
                       O. Keren   Reduction of Average Path Length in
                                  Binary Decision Diagrams by Spectral
                                  Methods  . . . . . . . . . . . . . . . . 520--531
              J. N. Coleman and   
              C. I. Softley and   
                  J. Kadlec and   
                R. Matousek and   
                   M. Tichy and   
                    Z. Pohl and   
                A. Hermanek and   
                 N. F. Benschop   The European Logarithmic Microprocessor  532--546
             S. Rajasekaran and   
                         S. Sen   Optimal and Practical Algorithms for
                                  Sorting on the PDM . . . . . . . . . . . 547--561
              J.-A. Pineiro and   
             J. D. Bruguera and   
                F. Lamberti and   
                   P. Montuschi   A Radix-2 Digit-by-Digit Architecture
                                  for Cube Root  . . . . . . . . . . . . . 562--566
                   R. Raman and   
                     D. S. Wise   Converting to and from Dilated Integers  567--573
            Yeim-Kuan Chang and   
                 Cheng-Chien Su   Comments on ``A TCAM-Based Parallel
                                  Architecture for High-Speed Packet
                                  Forwarding'' . . . . . . . . . . . . . . 574--576

IEEE Transactions on Computers
Volume 57, Number 5, May, 2008

                   I. Voyiatzis   An ALU-Based BIST Scheme for
                                  Word-Organized RAMs  . . . . . . . . . . 577--590
                Wencheng Lu and   
                       S. Sahni   Packet Classification Using
                                  Space-Efficient Pipelined Multibit Tries 591--605
             V. Vankamamidi and   
                  M. Ottavi and   
                    F. Lombardi   A Serial Memory by Quantum-Dot Cellular
                                  Automata (QCA) . . . . . . . . . . . . . 606--618
                 Ming Zhong and   
                   Kai Shen and   
                    J. Seiferas   The Convergence-Guaranteed Random Walk
                                  and Its Applications in Peer-to-Peer
                                  Networks . . . . . . . . . . . . . . . . 619--633
             Cheng-Han Tsai and   
               Tai-Yi Huang and   
               E. T.-H. Chu and   
              Chun-Hang Wei and   
                    Yu-Che Tsai   An Efficient Real-Time Disk-Scheduling
                                  Framework with Adaptive Quality
                                  Guarantee  . . . . . . . . . . . . . . . 634--647
                Wan-Chen Lu and   
               Kwei-Jay Lin and   
               Hsin-Wen Wei and   
                  Wei-Kuan Shih   Efficient Exact Test for Rate-Monotonic
                                  Schedulability Using Large
                                  Period-Dependent Initial Values  . . . . 648--659
                   C. Busch and   
           M. Magdon-lsmail and   
                        Jing Xi   Optimal Oblivious Path Selection on the
                                  Mesh . . . . . . . . . . . . . . . . . . 660--671
               S. Bartolini and   
                I. Branovic and   
                  R. Giorgi and   
                  E. Martinelli   Effects of Instruction-Set Extensions on
                                  an Embedded Processor: a Case Study on
                                  Elliptic Curve Cryptography over
                                  $\mathrm{GF}(2^m)$ . . . . . . . . . . . 672--685
                 Dong-U Lee and   
            R. C. C. Cheung and   
                     W. Luk and   
               J. D. Villasenor   Hardware Implementation Trade-Offs of
                                  Polynomial Approximations and
                                  Interpolations . . . . . . . . . . . . . 686--701
                     Jie Wu and   
                    Fei Dai and   
                    Shuhui Yang   Iterative Local Solutions for Connected
                                  Dominating Set in Ad Hoc Wireless
                                  Networks . . . . . . . . . . . . . . . . 702--715
                A. H. Namin and   
                 Huapeng Wu and   
                      M. Ahmadi   A New Finite-Field Multiplier Using
                                  Redundant Representation . . . . . . . . 716--720

IEEE Transactions on Computers
Volume 57, Number 6, June, 2008

             Sun-Yuan Hsieh and   
                    Yu-Shu Chen   Strongly Diagnosable Product Networks
                                  Under the Comparison Diagnosis Model . . 721--732
                   Jun Wang and   
                 Xiaoyu Yao and   
                     Huijun Zhu   Exploiting In-Memory and On-Disk
                                  Redundancy to Conserve Energy in Storage
                                  Systems  . . . . . . . . . . . . . . . . 733--747
                        Tao Xie   SEA: a Striping-Based Energy-Aware
                                  Strategy for Data Placement in
                                  RAID-Structured Storage Systems  . . . . 748--761
                   O. Lysne and   
            J. M. Montanana and   
                   J. Flich and   
                   J. Duato and   
             T. M. Pinkston and   
                       T. Skeie   An Efficient and Deadlock-Free Network
                                  Reconfiguration Protocol . . . . . . . . 762--779
                  G. Casale and   
                   R. Muntz and   
                     G. Serazzi   Geometric Bounds: a Noniterative
                                  Analysis Technique for Closed Queueing
                                  Networks . . . . . . . . . . . . . . . . 780--794
              Min-Young Nam and   
              Z. Al-Sabbagh and   
               Jung-Eun Kim and   
                Man-Ki Yoon and   
              Chang-Gun Lee and   
                    Eun Yong Ha   A Real-Time Ubiquitous System for
                                  Assisted Living: Combined Scheduling of
                                  Sensing and Communication for Real-Time
                                  Tracking . . . . . . . . . . . . . . . . 795--808
             Giuseppe Ascia and   
           Vincenzo Catania and   
            Maurizio Palesi and   
                   Davide Patti   Implementation and Analysis of a New
                                  Selection Strategy for Adaptive Routing
                                  in Networks-on-Chip  . . . . . . . . . . 809--820
              Ki-Woong Park and   
              Sang Seok Lim and   
                    Kyu Ho Park   Computationally Efficient PKI-Based
                                  Single Sign-On Protocol, PKASSO for
                                  Mobile Devices . . . . . . . . . . . . . 821--834
               M. G. Merayo and   
                   M. Nunez and   
                   I. Rodriguez   Extending EFSMs to Specify and Test
                                  Timed Systems with Action Durations and
                                  Time-Outs  . . . . . . . . . . . . . . . 835--848
              Bing-Hong Liu and   
               Wei-Chieh Ke and   
            Chin-Hsien Tsai and   
                  Ming-Jer Tsai   Constructing a Message-Pruning Tree with
                                  Minimum Cost for Tracking Moving Objects
                                  in Wireless Sensor Networks Is
                                  NP-Complete and an Enhanced Data
                                  Aggregation Structure  . . . . . . . . . 849--863
              Jong-Seok Kim and   
                  Hyeong-Ok Lee   Comments on ``A Study of Odd Graphs as
                                  Fault-Tolerant Interconnection
                                  Networks'' . . . . . . . . . . . . . . . 864--864

IEEE Transactions on Computers
Volume 57, Number 7, July, 2008

                 M. Beltran and   
                  A. Guzman and   
                   J. L. Bosque   A New CPU Availability Prediction Model
                                  for Time-Shared Systems  . . . . . . . . 865--875
                Ching-Nung Yang   Efficient Encoding Algorithm for
                                  Second-Order Spectral-Null Codes Using
                                  Cyclic Bit Shift . . . . . . . . . . . . 876--888
                Cheng Huang and   
                       Lihao Xu   STAR : An Efficient Coding Scheme for
                                  Correcting Triple Storage Node Failures  889--901
                    Hao Che and   
                Zhijun Wang and   
                  Kai Zheng and   
                        Bin Liu   DRES: Dynamic Range Encoding Scheme for
                                  TCAM Coprocessors  . . . . . . . . . . . 902--915
               M. Thuresson and   
               L. Spracklen and   
                   P. Stenstrom   Memory-Link Compression Schemes: a Value
                                  Locality Perspective . . . . . . . . . . 916--927
                A. Martinez and   
          G. Apostolopoulos and   
               F. J. Alfaro and   
              J. L. Sanchez and   
                       J. Duato   Efficient Deadline-Based QoS Algorithms
                                  for High-Performance Networks  . . . . . 928--939
                    P. Ndai and   
                  S. Bhunia and   
                 A. Agarwal and   
                         K. Roy   Within-Die Variation-Aware Scheduling in
                                  Superscalar Processors for Improved
                                  Throughput . . . . . . . . . . . . . . . 940--951
                 Ming Xiong and   
                   Song Han and   
                Kam-Yiu Lam and   
                      Deji Chen   Deferrable Scheduling for Maintaining
                                  Real-Time Data Freshness: Algorithms,
                                  Analysis, and Results  . . . . . . . . . 952--964
                  S. C. Lee and   
                     L. R. Hook   Logic and Computer Design in Nanospace   965--977
             Seongmoon Wang and   
         K. J. Balakrishnan and   
                    Wenlong Wei   X-Block: An Efficient LFSR
                                  Reseeding-Based Method to Block Unknowns
                                  for Temporal Compactors  . . . . . . . . 978--989
               A. M. Masuda and   
                   L. Moura and   
                 D. Panario and   
                     D. Thomson   Low Complexity Normal Elements over
                                  Finite Fields of Characteristic Two  . . 990--1001
                   Chul Lee and   
             Sung Hoon Baek and   
                    Kyu Ho Park   A Hybrid Flash File System Based on NOR
                                  and NAND Flash Memories for Embedded
                                  Devices  . . . . . . . . . . . . . . . . 1002--1008

IEEE Transactions on Computers
Volume 57, Number 8, August, 2008

              Fabrizio Lombardi   Editor-in-Chief's Note . . . . . . . . . 1009--1011
               I. Voyiatzis and   
               A. Paschalis and   
              D. Gizopoulos and   
                C. Halatsis and   
                F. S. Makri and   
                 M. Hatzimihail   An Input Vector Monitoring Concurrent
                                  BIST Architecture Based on a Precomputed
                                  Test Set . . . . . . . . . . . . . . . . 1012--1022
                     Huapeng Wu   Bit-Parallel Polynomial Basis Multiplier
                                  for New Classes of Finite Fields . . . . 1023--1031
                S. Matakias and   
              Y. Tsiatouhas and   
              T. Haniotakis and   
                  A. Arapoyanni   A Current Mode, Parallel, Two-Rail Code
                                  Checker  . . . . . . . . . . . . . . . . 1032--1045
                C. Martinez and   
                 R. Beivide and   
                E. Stafford and   
                  M. Moreto and   
                E. M. Gabidulin   Modeling Toroidal Networks with the
                                  Gaussian Integers  . . . . . . . . . . . 1046--1056
                  Ling Zhuo and   
                 V. K. Prasanna   High-Performance Designs for Linear
                                  Algebra Operations on Reconfigurable
                                  Hardware . . . . . . . . . . . . . . . . 1057--1071
              M. Khabbazian and   
                 V. K. Bhargava   Localized Broadcasting with Guaranteed
                                  Delivery and Bounded Transmission
                                  Redundancy . . . . . . . . . . . . . . . 1072--1086
                    V. Daza and   
                 J. Herranz and   
                        G. Saez   On the Computational Security of a
                                  Distributed Key Distribution Scheme  . . 1087--1097
                J. Mirkovic and   
                  P. Reiher and   
            C. Papadopoulos and   
                 A. Hussain and   
                 M. Shepard and   
                    M. Berg and   
                        R. Jung   Testing a Collaborative DDoS Defense in
                                  a Red Team/Blue Team Exercise  . . . . . 1098--1112
             K. Baumgartner and   
                     S. Ferrari   A Geometric Transversal Approach to
                                  Analyzing Track Coverage in Sensor
                                  Networks . . . . . . . . . . . . . . . . 1113--1128
             Jeonghwan Choi and   
               Youngjae Kim and   
         A. Sivasubramaniam and   
                 J. Srebric and   
                  Qian Wang and   
                    Joonwon Lee   A CFD-Based Tool for Studying
                                  Temperature in Rack-Mounted Servers  . . 1129--1142
                  Xian Wang and   
                Pingzhi Fan and   
                         Yi Pan   A More Realistic Thinning Scheme for
                                  Call Admission Control in Multimedia
                                  Wireless Networks  . . . . . . . . . . . 1143--1147
            M. G. B. Sumanasena   A Scale Factor Correction Scheme for the
                                  CORDIC Algorithm . . . . . . . . . . . . 1148--1152

IEEE Transactions on Computers
Volume 57, Number 9, September, 2008

                Radu Marculescu   Introduction to the Special Section on
                                  Networks-on-Chip . . . . . . . . . . . . 1153--1155
                Shu-Yen Lin and   
          Chun-Hsiang Huang and   
              Chih-Hao Chao and   
           Keng-Hsien Huang and   
                      An-Yeu Wu   Traffic-Balanced Routing Algorithm for
                                  Irregular Mesh-Based On-Chip Networks    1156--1168
                 A. K. Kodi and   
                 A. Sarathy and   
                       A. Louri   Adaptive Channel Buffers in On-Chip
                                  Interconnection Networks- A Power and
                                  Performance Analysis . . . . . . . . . . 1169--1181
                   A. Leroy and   
               D. Milojevic and   
                 D. Verkest and   
                  F. Robert and   
                    F. Catthoor   Concepts and Implementation of Spatial
                                  Division Multiplexing for Guaranteed
                                  Throughput in Networks-on-Chip . . . . . 1182--1195
                 F. Vitullo and   
           N. E. L'Insalata and   
                   E. Petri and   
                S. Saponara and   
                 L. Fanucci and   
                  M. Casula and   
               R. Locatelli and   
                     M. Coppola   Low-Complexity Link Microarchitecture
                                  for Mesochronous Communication in
                                  Networks-on-Chip . . . . . . . . . . . . 1196--1201
                    E. Cota and   
          F. L. Kastensmidt and   
                  M. Cassel and   
                   M. Herve and   
                 P. Almeida and   
               P. Meirelles and   
                   A. Amory and   
                 M. Lubaszewski   A High-Fault-Coverage Approach for the
                                  Test of Data, Control and Handshake
                                  Interconnects in Mesh Networks-on-Chip   1202--1215
                  L. Fiorin and   
                 G. Palermo and   
                 S. Lukovic and   
                V. Catalano and   
                     C. Silvano   Secure Memory Accesses on
                                  Networks-on-Chip . . . . . . . . . . . . 1216--1229
                   Dan Zhao and   
                        Yi Wang   SD-MAC: Design and Synthesis of a
                                  Hardware-Efficient Collision-Free
                                  QoS-Aware MAC Protocol for Wireless
                                  Network-on-Chip  . . . . . . . . . . . . 1230--1245
                 A. Shacham and   
                 K. Bergman and   
                  L. P. Carloni   Photonic Networks-on-Chip for Future
                                  Generations of Chip Multiprocessors  . . 1246--1260
                R. I. Davis and   
                   A. Zabos and   
                       A. Burns   Efficient Exact Schedulability Tests for
                                  Fixed Priority Real-Time Systems . . . . 1261--1276
                  Wei Huang and   
        K. Sankaranarayanan and   
                 K. Skadron and   
              R. J. Ribando and   
                     M. R. Stan   Accurate, Pre-RTL Temperature-Aware
                                  Design Using a Parameterized, Geometric
                                  Thermal Model  . . . . . . . . . . . . . 1277--1288
                 H. Rahaman and   
                  J. Mathew and   
              D. K. Pradhan and   
                    A. M. Jabir   Derivation of Reduced Test Vectors for
                                  Bit-Parallel Multipliers over
                                  $\mathrm{GF}(2^m)$ . . . . . . . . . . . 1289--1294
                      Anonymous   Silver Bullet Security Podcast Series    1295--1295
                      Anonymous   Build Your Career in Computing . . . . . 1296--1296

IEEE Transactions on Computers
Volume 57, Number 10, October, 2008

          Sandeep K. Shukla and   
             Jean-Pierre Talpin   Guest Editors' Introduction to the
                                  Special Section on Programming
                                  Architectures for Embedded Systems . . . 1297--1299
                S. Tripakis and   
                 C. Pinello and   
              A. Benveniste and   
     A. Sangiovanni-Vincent and   
                   P. Caspi and   
                   M. Di Natale   Implementing Synchronous Models on
                                  Loosely Time Triggered Architectures . . 1300--1314
                 S. Bliudze and   
                     J. Sifakis   The Algebra of Connectors-Structuring
                                  Interaction in BIP . . . . . . . . . . . 1315--1330
                  S. Stuijk and   
                  M. Geilen and   
                      T. Basten   Throughput-Buffering Trade-Off
                                  Exploration for Cyclo-Static and
                                  Synchronous Dataflow Graphs  . . . . . . 1331--1345
                  L. Pierre and   
                       L. Ferro   A Tractable and Fast Method for
                                  Monitoring SystemC TLM Specifications    1346--1356
                 S. K. Wood and   
             D. H. Akehurst and   
                 O. Uzenkov and   
           W. G. J. Howells and   
           K. D. McDonald-Maier   A Model-Driven Development Approach to
                                  Mapping UML State Diagrams to
                                  Synthesizable VHDL . . . . . . . . . . . 1357--1371
                  P. Pujara and   
                    A. Aggarwal   Cache Noise Prediction . . . . . . . . . 1372--1386
                    Tao Xie and   
                       Hui Wang   MICRO: a Multilevel Caching-Based
                                  Reconstruction Optimization for Mobile
                                  Storage Systems  . . . . . . . . . . . . 1386--1398
               V. Marojevic and   
             X. R. Balleste and   
                     A. Gelonch   A Computing Resource Management
                                  Framework for Software-Defined Radios    1399--1412
                 R. Subrata and   
               A. Y. Zomaya and   
                   B. Landfeldt   A Cooperative Game Framework for QoS
                                  Guided Job Allocation Schemes in Grids   1413--1422
               H. M. Ammari and   
                      S. K. Das   Integrated Coverage and Connectivity in
                                  Wireless Sensor Networks: a
                                  Two-Dimensional Percolation Problem  . . 1423--1434
                   O. Arazi and   
                     Hairong Qi   On Calculating Multiplicative Inverses
                                  Modulo $2^{m}$ . . . . . . . . . . . . . 1435--1438
                      Anonymous   Build Your Career  . . . . . . . . . . . 1439--1439
                      Anonymous   Silver Bullet Security Podcast series    1440--1440

IEEE Transactions on Computers
Volume 57, Number 11, November, 2008

          Rainer Steinwandt and   
           Willi Geiselmann and   
   Çetin Kaya Koç   Guest Editors' Introduction to the
                                  Special Section on Special-Purpose
                                  Hardware for Cryptography and
                                  Cryptanalysis  . . . . . . . . . . . . . 1441--1442
                  B. Ansari and   
                    M. A. Hasan   High-Performance Architecture of
                                  Elliptic Curve Scalar Multiplication . . 1443--1453
              J.-L. Beuchat and   
              N. Brisebarre and   
                  J. Detrey and   
                 E. Okamoto and   
                 M. Shirase and   
                      T. Takagi   Algorithms and Arithmetic Operators for
                                  Computing the $\eta T$ Pairing in
                                  Characteristic Three . . . . . . . . . . 1454--1468
             V. S. Dimitrov and   
             K. U. Jarvinen and   
             M. J. Jacobson and   
                    W. Chan and   
                     Zhun Huang   Provably Sublinear Point Multiplication
                                  on Koblitz Curves and Its Hardware
                                  Implementation . . . . . . . . . . . . . 1469--1481
                 S. Guilley and   
                 L. Sauvage and   
               P. Hoogvorst and   
                 R. Pacalet and   
              G. M. Bertoni and   
                   S. Chaudhuri   Security Evaluation of WDDL and SecLib
                                  Countermeasures against Power Attacks    1482--1497
                 T. Guneysu and   
                  T. Kasper and   
                 M. Novotny and   
                    C. Paar and   
                        A. Rupp   Cryptanalysis with COPACOBANA  . . . . . 1498--1513
                Yong Ki Lee and   
                K. Sakiyama and   
                  L. Batina and   
                 I. Verbauwhede   Elliptic-Curve-Based Security Processor
                                  for RFID . . . . . . . . . . . . . . . . 1514--1527
                 P. Maistri and   
                    R. Leveugle   Double-Data-Rate Computation as a
                                  Countermeasure against Fault Analysis    1528--1539
                 R. Muresan and   
                     S. Gregori   Protection Circuit against Differential
                                  Power Analysis Attacks for Smart Cards   1540--1549
             M. E. Kounavis and   
                    F. L. Berry   Novel Table Lookup-Based Algorithms for
                                  High-Performance CRC Generation  . . . . 1550--1560
                    P. D. Fiore   Efficient Approximate Wordlength
                                  Optimization . . . . . . . . . . . . . . 1561--1570
              Jen-Wei Hsieh and   
                Yi-Lin Tsai and   
                Tei-Wei Kuo and   
                   Tzao-Lin Lee   Configurable Flash-Memory Management:
                                  Performance versus Overheads . . . . . . 1571--1583
                      Anonymous   Build Your Career in Computing . . . . . 1584--1584

IEEE Transactions on Computers
Volume 57, Number 12, December, 2008

               Xiaogang Qiu and   
                      M. Dubois   The Synonym Lookaside Buffer: a Solution
                                  to the Synonym Problem in Virtual Caches 1585--1599
              J.-L. Beuchat and   
                   J.-M. Muller   Automatic Generation of Modular
                                  Multipliers for FPGA Applications  . . . 1600--1613
                Junqing Sun and   
             G. D. Peterson and   
                O. O. Storaasli   High-Performance Mixed-Precision Linear
                                  Solver for FPGAs . . . . . . . . . . . . 1614--1623
               Shaoqiang Bi and   
                    W. J. Gross   The Mixed-Radix Chinese Remainder
                                  Theorem and Its Applications to Residue
                                  Comparison . . . . . . . . . . . . . . . 1624--1632
                   N. Homma and   
                    T. Aoki and   
                     T. Higuchi   A Systematic Approach for Designing
                                  Redundant Arithmetic Adders Based on
                                  Counter Tree Diagrams  . . . . . . . . . 1633--1646
                Zhiling Lan and   
                       Yawei Li   Adaptive Fault Management of Parallel
                                  Applications for High-Performance
                                  Computing  . . . . . . . . . . . . . . . 1647--1660
                  Ling Zhuo and   
                 V. K. Prasanna   Scalable Hybrid Designs for Linear
                                  Algebra on Reconfigurable Computing
                                  Systems  . . . . . . . . . . . . . . . . 1661--1675
                  V. Puente and   
             J. A. Gregorio and   
                 F. Vallejo and   
                     R. Beivide   Immunet: Dependable Routing for
                                  Interconnection Networks with Arbitrary
                                  Topology . . . . . . . . . . . . . . . . 1676--1689
                Jingnan Yao and   
                  Jiani Guo and   
                   L. N. Bhuyan   Ordered Round-Robin: An Efficient
                                  Sequence Preserving Packet Scheduler . . 1690--1703
                   A. Benso and   
                   A. Bosio and   
                S. Di Carlo and   
               G. Di Natale and   
                    P. Prinetto   March Test Generation Revealed . . . . . 1704--1713
                Jongsun Kim and   
               Bo-Cheng Lai and   
             M.-C. F. Chang and   
                 I. Verbauwhede   A Cost-Effective Latency-Aware Memory
                                  Bus for Symmetric Multiprocessor Systems 1714--1719
             Sun-Yuan Hsieh and   
                    Yu-Shu Chen   Strongly Diagnosable Systems under the
                                  Comparison Diagnosis Model . . . . . . . 1720--1725
                Wenjun Xiao and   
                Wenhong Wei and   
               Weidong Chen and   
                 Mingxin He and   
                     B. Parhami   Comments on ``Low Diameter
                                  Interconnections for Routing in
                                  High-Performance Parallel Systems,''
                                  with Connections and Extensions to Arc
                                  Coloring of Coset Graphs . . . . . . . . 1726--1728


IEEE Transactions on Computers
Volume 58, Number 1, January, 2009

              Fabrizio Lombardi   State of the Journal . . . . . . . . . . 1--4
               M. Faezipour and   
                     M. Nourani   Wire-Speed TCAM-Based Architectures for
                                  Multimatch Packet Classification . . . . 5--17
               M. Burtscher and   
              P. Ratanaworabhan   FPC: a High-Speed Compressor for
                                  Double-Precision Floating-Point Data . . 18--31
                B. S. Feero and   
                    P. P. Pande   Networks-on-Chip in a Three-Dimensional
                                  Environment: a Performance Evaluation    32--45
                 Dong-U Lee and   
               J. D. Villasenor   Optimized Custom Precision Function
                                  Evaluation for Embedded Processors . . . 46--59
             Yeow Meng Chee and   
                  A. C. H. Ling   Limit on the Addressability of
                                  Fault-Tolerant Nanowire Decoders . . . . 60--68
                  S. Sankar and   
                  Yan Zhang and   
              S. Gurumurthi and   
                     M. R. Stan   Sensitivity-Based Optimization of Disk
                                  Architecture . . . . . . . . . . . . . . 69--81
                  Lipo Wang and   
                    Wen Liu and   
                   Haixiang Shi   Delay-Constrained Multicast Routing
                                  Using the Noisy Chaotic Neural Networks  82--89
                   P. Marti and   
                 Caixue Lin and   
               S. A. Brandt and   
                 M. Velasco and   
                  J. M. Fuertes   Draco: Efficient Resource Management for
                                  Resource-Constrained Control Tasks . . . 90--105
                S. Nagayama and   
                       T. Sasao   Complexities of Graph-Based
                                  Representations for Elementary Functions 106--119
         J. Iguchi-Cartigny and   
                 P. M. Ruiz and   
             D. Simplot-Ryl and   
             I. Stojmenovic and   
                     C. M. Yago   Localized Minimum-Energy Broadcasting
                                  for Wireless Multihop Networks with
                                  Directional Antennas . . . . . . . . . . 120--131
                 D. Nikolos and   
                 D. Kagaris and   
               S. Sudireddy and   
                     S. Gidaros   An Improved Search Method for
                                  Accumulator-Based Test Set Embedding . . 132--138
                      Anonymous   2008 TC Reviewers List . . . . . . . . . 139--144

IEEE Transactions on Computers
Volume 58, Number 2, February, 2009

             Peter Kornerup and   
            Paolo Montuschi and   
         Jean-Michel Muller and   
                   Eric Schwarz   Guest Editors' Introduction: Special
                                  Section on Computer Arithmetic . . . . . 145--147
                  M. Cornea and   
                J. Harrison and   
                C. Anderson and   
                    P. Tang and   
               E. Schneider and   
                     E. Gvozdev   A Software Implementation of the IEEE
                                  754R Decimal Floating-Point Arithmetic
                                  Using the Binary Encoding Format . . . . 148--162
              A. Fit-Florea and   
                      L. Li and   
             M. A. Thornton and   
                   D. W. Matula   A Discrete Logarithm Number System for
                                  Integer Arithmetic Modulo $2^k$:
                                  Algorithms and Lookup Structures . . . . 163--174
                     D. Tan and   
              C. E. Lemonds and   
             Michael J. Schulte   Low-Power Multiple-Precision Iterative
                                  Floating-Point Multiplier with SIMD
                                  Support  . . . . . . . . . . . . . . . . 175--187
               Dong-Guk Han and   
                 Dooho Choi and   
                      Howon Kim   Improved Computation of Square Roots in
                                  Specific Finite Fields . . . . . . . . . 188--196
               C. Q. Lauter and   
                     V. Lefevre   An Efficient Rounding Boundary Test for
                                  pow(x, y) in Double Precision  . . . . . 197--207
          K. Papadantonakis and   
                   N. Kapre and   
                    S. Chan and   
                       A. DeHon   Pipelining Saturated Accumulation  . . . 208--219
                   Sylvie Boldo   Kahan's Algorithm for a Correct
                                  Discriminant Computation at Last
                                  Formally Proven  . . . . . . . . . . . . 220--225
                  M. Daumas and   
                  D. Lester and   
                        C. Muoz   Verified Real Number Calculations: a
                                  Library for Interval Arithmetic  . . . . 226--237
                Chuan-Ching Sue   An Enhanced Universal $N \times N$ Fully
                                  Nonblocking Quantum Switch . . . . . . . 238--250
          Chieh-Feng Chiang and   
                   J. J. M. Tan   Using Node Diagnosability to Determine
                                  t-Diagnosability under the Comparison
                                  Diagnosis Model  . . . . . . . . . . . . 251--259
                   Deng Pan and   
                  Yuanyuan Yang   Localized Independent Packet Scheduling
                                  for Buffered Crossbar Switches . . . . . 260--274
             S. C. Krishnan and   
               R. Panigrahy and   
               S. Parthasarathy   Error-Correcting Codes for Ternary
                                  Content Addressable Memories . . . . . . 275--279
                    E. Bini and   
      Thi Huyen Chau Nguyen and   
                 P. Richard and   
                   S. K. Baruah   A Response-Time Bound in Fixed-Priority
                                  Scheduling with Arbitrary Deadlines  . . 279--286
              R. M. Hierons and   
                        H. Ural   Correction to ``Reduced Length Checking
                                  Sequences'' [Sep 02 93--99]  . . . . . . 287--287
                      Anonymous   Silver Bullet Security Podcast series    288--288

IEEE Transactions on Computers
Volume 58, Number 3, March, 2009

              J. G. Elerath and   
                       M. Pecht   A Highly Accurate Method for Assessing
                                  Reliability of Redundant Arrays of
                                  Inexpensive Disks (RAID) . . . . . . . . 289--299
                    Soontae Kim   Reducing Area Overhead for
                                  Error-Protecting Large L2/L3 Caches  . . 300--310
                P. Raghavan and   
              A. Lambrechts and   
                M. Jayapala and   
                F. Catthoor and   
                     D. Verkest   Distributed Loop Controller for
                                  Multithreading in Unithreaded ILP
                                  Architectures  . . . . . . . . . . . . . 311--321
             Liang-Kai Wang and   
         Michael J. Schulte and   
             J. D. Thompson and   
                      N. Jairam   Hardware Designs for Decimal
                                  Floating-Point Addition and Related
                                  Operations . . . . . . . . . . . . . . . 322--335
            M. E. Tolentino and   
                  J. Turner and   
                  K. W. Cameron   Memory MISER: Improving Main Memory
                                  Energy Efficiency in Servers . . . . . . 336--350
                  A. Gourgy and   
                T. H. Szymanski   Cooperative Token-Ring Scheduling For
                                  Input-Queued Switches  . . . . . . . . . 351--364
                   Xin Yuan and   
                   Zhenhai Duan   Fair Round-Robin: a Low Complexity
                                  Packet Schduler with Proportional and
                                  Worst-Case Fairness  . . . . . . . . . . 365--379
                  Qin Zheng and   
              B. Veeravalli and   
                Chen-Khong Tham   On the Design of Fault-Tolerant
                                  Scheduling Strategies Using
                                  Primary-Backup Approach for
                                  Computational Grids with Low Replication
                                  Costs  . . . . . . . . . . . . . . . . . 380--393
                   Feng Shi and   
                      Y. Makris   Enhancing Simulation Accuracy through
                                  Advanced Hazard Detection in
                                  Asynchronous Circuits  . . . . . . . . . 394--408
                    S. Goel and   
           E. J. Marinissen and   
                  A. Sehgal and   
                 K. Chakrabarty   Testing of SoCs with Hierarchical Cores:
                                  Common Fallacies, Test Access
                                  Optimization, and Test Scheduling  . . . 409--423
               L. J. Stocco and   
                     G. Schrack   On Spatial Orders and Location Codes . . 424--432

IEEE Transactions on Computers
Volume 58, Number 4, April, 2009

                   Jun Wang and   
                 Xiaoyu Yao and   
                C. Mitchell and   
                        Peng Gu   A New Hierarchical Data Cache
                                  Architecture for iSCSI Storage Server    433--447
              O. J. Santana and   
                  A. Falcon and   
                 A. Ramirez and   
                      M. Valero   DIA: a Complexity-Effective Decoding
                                  Architecture . . . . . . . . . . . . . . 448--462
                Yeim-Kuan Chang   Efficient Multidimensional Packet
                                  Classification with Fast Updates . . . . 463--479
                 T. Chantem and   
           Xiaobo Sharon Hu and   
                   M. D. Lemmon   Generalized Elastic Scheduling for
                                  Real-Time Tasks  . . . . . . . . . . . . 480--495
                  F. Castro and   
                    R. Noor and   
                    A. Garg and   
                  D. Chaver and   
                M. C. Huang and   
                   L. Piuel and   
                  M. Prieto and   
                      F. Tirado   Replacing Associative Load Queues: a
                                  Timing-Centric Approach  . . . . . . . . 496--511
                 D. Baneres and   
              J. Cortadella and   
                 M. Kishinevsky   A Recursive Paradigm to Solve Boolean
                                  Relations  . . . . . . . . . . . . . . . 512--527
             Jung-Heum Park and   
               Hee-Chul Kim and   
                Hyeong-Seok Lim   Many-to-Many Disjoint Path Covers in the
                                  Presence of Faulty Elements  . . . . . . 528--540
              E. P. F. Chan and   
                      Yaya Yang   Shortest Path Tree Computation in
                                  Dynamic Graphs . . . . . . . . . . . . . 541--557
                     Hui Li and   
                    Ming Li and   
                 B. Prabhakaran   On Supporting High-Quality $3$D Geometry
                                  Multicasting over IEEE 802.11 Wireless
                                  Networks . . . . . . . . . . . . . . . . 558--571
                    M. Cenk and   
                     F. Ozbudak   Improved Polynomial Multiplication
                                  Formulas over ${\rm IF}_2$ Using Chinese
                                  Remainder Theorem  . . . . . . . . . . . 572--576

IEEE Transactions on Computers
Volume 58, Number 5, May, 2009

              Pai-Han Huang and   
                   M. Desai and   
                Xiaofan Qiu and   
              B. Krishnamachari   On the Multihop Performance of
                                  Synchronization Mechanisms in High
                                  Propagation Delay Networks . . . . . . . 577--590
                 L. Mamatas and   
                 V. Tsaoussidis   Differentiating Services with
                                  Noncongestive Queuing (NCQ)  . . . . . . 591--604
                  Hong Shen and   
                     Shihong Xu   Coordinated En-Route Web Caching in
                                  Multiserver Networks . . . . . . . . . . 605--619
                 Dong Xiang and   
                Yueli Zhang and   
                         Yi Pan   Practical Deadlock-Free Fault-Tolerant
                                  Routing in Meshes Based on the Planar
                                  Network Fault Model  . . . . . . . . . . 620--633
                Kanghee Kim and   
                  Chang-Gun Lee   A Safe Stochastic Analysis with Relaxed
                                  Limitations on the Periodic Task Model   634--647
                Jupyung Lee and   
                    Kyu Ho Park   Prediction-Based Micro-Scheduler: Toward
                                  Responsive Scheduling of General-Purpose
                                  Operating Systems  . . . . . . . . . . . 648--661
                  N. Hopper and   
                 L. von Ahn and   
                    J. Langford   Provably Secure Steganography  . . . . . 662--676
    H. A. B. F. de Oliveira and   
               A. Boukerche and   
             E. F. Nakamura and   
              A. A. F. Loureiro   An Efficient Directed Localization
                                  Recursion Protocol for Wireless Sensor
                                  Networks . . . . . . . . . . . . . . . . 677--691
               Tai-Lin Chin and   
              P. Ramanathan and   
                   K. K. Saluja   Modeling Detection Latency with
                                  Collaborative Mobile Sensing
                                  Architecture . . . . . . . . . . . . . . 692--705
             Zhenghao Zhang and   
              Yuanyuan Yang and   
                      Miao Zhao   Enhancing Downlink Performance in
                                  Wireless Networks by Simultaneous
                                  Multiple Packet Transmission . . . . . . 706--718
                      Anonymous   Call-for-Papers on Computer Arithmetic   719--719
                      Anonymous   Build your Career  . . . . . . . . . . . 720--720

IEEE Transactions on Computers
Volume 58, Number 6, June, 2009

                     H. Cho and   
             E. E. Swartzlander   Adder and Multiplier Design in
                                  Quantum-Dot Cellular Automata  . . . . . 721--727
             Mingsheng Ying and   
                      Yuan Feng   An Algebraic Language for Distributed
                                  Quantum Computing  . . . . . . . . . . . 728--743
               Sooyong Kang and   
               Sungmin Park and   
               Hoyoung Jung and   
                 Hyoki Shim and   
                    Jaehyuk Cha   Performance Trade-Offs in Using NVRAM
                                  Write Buffer for Flash Memory-Based
                                  Storage Devices  . . . . . . . . . . . . 744--758
               Shaoshan Liu and   
                  J.-L. Gaudiot   Potential Impact of Value Prediction on
                                  Communication in Many-Core Architectures 759--769
                   A. Aleta and   
               J. M. Codina and   
                 J. Sanchez and   
                A. Gonzalez and   
                       D. Kaeli   AGAMOS: a Graph-Based Approach to Modulo
                                  Scheduling for Clustered
                                  Microarchitectures . . . . . . . . . . . 770--783
              Yingxin Jiang and   
                    A. Striegel   An Exploration of the Effects of State
                                  Granularity through $(m, k)$ Real-Time
                                  Streams  . . . . . . . . . . . . . . . . 784--798
                  E. Prouff and   
                  M. Rivain and   
                       R. Bevan   Statistical Analysis of Second Order
                                  Differential Power Analysis  . . . . . . 799--811
              K. K. Rachuri and   
                      C. Murthy   Energy Efficient and Scalable Search in
                                  Dense Wireless Sensor Networks . . . . . 812--826
             You-Chiun Wang and   
               Yao-Yu Hsieh and   
                  Yu-Chee Tseng   Multiresolution Spatial and Temporal
                                  Coding in a Wireless Sensor Network for
                                  Long-Term Monitoring Applications  . . . 827--838
                     A. Mei and   
                       J. Stefa   Routing in Outer Space: Fair Traffic
                                  Load in Multihop Wireless Networks . . . 839--850
                C. W. Chiou and   
                C.-C. Chang and   
                  C.-Y. Lee and   
                  T.-W. Hou and   
                      J.-M. Lin   Concurrent Error Detection and
                                  Correction in Gaussian Normal Basis
                                  Multiplier over ${\em GF}(2^m)$  . . . . 851--857
                   F. Kocan and   
                     Lun Li and   
                     D. G. Saab   Exact Path Delay Fault Coverage
                                  Calculation of Partitioned Circuits  . . 858--864

IEEE Transactions on Computers
Volume 58, Number 7, July, 2009

                  M. Mutyam and   
                  Feng Wang and   
                R. Krishnan and   
               V. Narayanan and   
                M. Kandemir and   
                   Yuan Xie and   
                    M. J. Irwin   Process-Variation-Aware Adaptive Cache
                                  Architecture and Management  . . . . . . 865--877
                  Junho Cho and   
                   Wonyong Sung   Efficient Software-Based Encoding and
                                  Decoding of BCH Codes  . . . . . . . . . 878--889
               Donghyun Kim and   
                    Lee-Sup Kim   A Floating-Point Unit for $4$D Vector
                                  Inner Product with Reduced Latency . . . 890--901
               Mark A. Erle and   
          Brian J. Hickmann and   
             Michael J. Schulte   Decimal Floating-Point Multiplication    902--916
                   A. Satoh and   
                T. Sugawara and   
                        T. Aoki   High-Performance Hardware Architectures
                                  for Galois Counter Mode  . . . . . . . . 917--930
                   H. K. Kapoor   A Process Algebraic View of
                                  Latency-Insensitive Systems  . . . . . . 931--944
                  N. Pettis and   
                 Yung-Hsiang Lu   A Homogeneous Architecture for Power
                                  Policy Integration in Operating Systems  945--955
                 Jianyu Lou and   
                   Xiaojun Shen   Frame-Based Packet-Mode Scheduling for
                                  Input-Queued Switches  . . . . . . . . . 956--969
               Xiaosong Lou and   
                      Kai Hwang   Collusive Piracy Prevention in P2P
                                  Content Delivery Networks  . . . . . . . 970--983
                 Tsern-Huei Lee   Hardware Architecture for
                                  High-Performance Regular Expression
                                  Matching . . . . . . . . . . . . . . . . 984--993
                  Stef Graillat   Accurate Floating-Point Product and
                                  Exponentiation . . . . . . . . . . . . . 994--1000
                     A. Cilardo   Efficient Bit-Parallel
                                  $\mathrm{GF}(2^m)$ Multiplier for a
                                  Large Class of Irreducible Pentanomials  1001--1008

IEEE Transactions on Computers
Volume 58, Number 8, August, 2009

                   K. Rajan and   
                R. Govindarajan   A Novel Cache Architecture and Placement
                                  Framework for Packet Forwarding Engines  1009--1025
                 N. Elarief and   
                        B. Bose   Diversity Combining ARQ over the $m(\geq
                                  2)$-ary Unidirectional Channel . . . . . 1026--1034
                Y. Hilewitz and   
                      R. B. Lee   A New Basis for Shifters in
                                  General-Purpose Processors for Existing
                                  and Advanced Bit Manipulations . . . . . 1035--1048
               D. C. Suresh and   
                 B. Agrawal and   
                   Jun Yang and   
                   W. A. Najjar   Tunable and Energy Efficient Bus
                                  Encoding Techniques  . . . . . . . . . . 1049--1062
          K. Constantinides and   
                   O. Mutlu and   
                  T. Austin and   
                    V. Bertacco   A Flexible Software-Based Framework for
                                  Online Detection of Hardware Defects . . 1063--1079
              A. N. Bessani and   
                 M. Correia and   
          J. da Silva Fraga and   
                 Lau Cheuk Lung   An Efficient Byzantine-Resilient Tuple
                                  Space  . . . . . . . . . . . . . . . . . 1080--1094
               Xiaorui Wang and   
              Yingming Chen and   
                Chenyang Lu and   
               X. D. Koutsoukos   Towards Controllable Distributed
                                  Real-Time Systems with Feasible
                                  Utilization Control  . . . . . . . . . . 1095--1110
                S. Govindan and   
             Jeonghwan Choi and   
                 A. R. Nath and   
                     A. Das and   
               B. Urgaonkar and   
             A. Sivasubramaniam   Xen and Co.: Communication-Aware CPU
                                  Management in Consolidated Xen-Based
                                  Hosting Platforms  . . . . . . . . . . . 1111--1125
                C. K. Anand and   
                        W. Kahl   An Optimized Cell BE Special Function
                                  Library Generated by Coconut . . . . . . 1126--1138
                   S. Boldo and   
                  M. Daumas and   
                    Ren-Cang Li   Formally Verified Argument Reduction
                                  with a Fused Multiply-Add  . . . . . . . 1139--1145
             Sung Hoon Baek and   
                    Kyu Ho Park   Striping-Aware Sequential Prefetching
                                  for Independency and Parallelism in Disk
                                  Arrays with Concurrent Accesses  . . . . 1146--1152

IEEE Transactions on Computers
Volume 58, Number 9, September, 2009

                Hyesoon Kim and   
                 J. A. Joao and   
                   O. Mutlu and   
              Chang Joo Lee and   
                 Y. N. Patt and   
                        R. Cohn   Virtual Program Counter (VPC)
                                  Prediction: Very Low Cost Indirect
                                  Branch Prediction Using Conditional
                                  Branch Prediction Hardware . . . . . . . 1153--1170
                 Shuai Wang and   
                     Jie Hu and   
                  S. G. Ziavras   On the Characterization and Optimization
                                  of On-Chip Cache Reliability against
                                  Soft Errors  . . . . . . . . . . . . . . 1171--1184
          M. P. Michaelides and   
               C. G. Panayiotou   SNAP: Fault Tolerant Event Location
                                  Estimation in Sensor Networks Using
                                  Binary Data  . . . . . . . . . . . . . . 1185--1197
              D. E. Holcomb and   
             W. P. Burleson and   
                          K. Fu   Power-Up SRAM State as an Identifying
                                  Fingerprint and Source of True Random
                                  Numbers  . . . . . . . . . . . . . . . . 1198--1210
                    Hai Lin and   
                      Yunsi Fei   Orchestrating Horizontal Parallelism and
                                  Vertical Instruction Packing of Programs
                                  to Improve System Overall Efficiency . . 1211--1220
                  Chang Shu and   
               Soonhak Kwon and   
                         K. Gaj   Reconfigurable Computing Approach for
                                  Tate Pairing Cryptosystems over Binary
                                  Fields . . . . . . . . . . . . . . . . . 1221--1237
                 S. M. Iyer and   
             M. K. Nakayama and   
             A. V. Gerbessiotis   A Markovian Dependability Model with
                                  Cascading Failures . . . . . . . . . . . 1238--1249
            Fengxiang Zhang and   
                       A. Burns   Schedulability Analysis for Real-Time
                                  Systems with EDF Scheduling  . . . . . . 1250--1258
                  Yanli Cai and   
                    Wei Lou and   
                  Minglu Li and   
                  Xiang-Yang Li   Energy Efficient Target-Oriented
                                  Scheduling in Directional Sensor
                                  Networks . . . . . . . . . . . . . . . . 1259--1274
                      Xu Li and   
                 N. Santoro and   
                 I. Stojmenovic   Localized Distance-Sensitive Service
                                  Discovery in Wireless Sensor and Actor
                                  Networks . . . . . . . . . . . . . . . . 1275--1288
              B. Stephenson and   
                      B. Sikdar   A Quasi-Species Model for the
                                  Propagation and Containment of
                                  Polymorphic Worms  . . . . . . . . . . . 1289--1296

IEEE Transactions on Computers
Volume 58, Number 10, October, 2009

                Hongbin Sun and   
              Nanning Zheng and   
                     Tong Zhang   Leveraging Access Locality for the
                                  Efficient Use of Multibit
                                  Error-Correcting Codes in L2 Cache . . . 1297--1306
                  E. Torres and   
                  P. Ibanez and   
           V. Vinals-Yufera and   
                 J. M. Llaberia   Store Buffer Design for Multibanked Data
                                  Caches . . . . . . . . . . . . . . . . . 1307--1320
                   G. D. Nguyen   Fast CRCs  . . . . . . . . . . . . . . . 1321--1331
                  A. Hariri and   
             A. Reyhani-Masoleh   Bit-Serial and Bit-Parallel Montgomery
                                  Multiplication and Squaring over
                                  $\mathrm{GF}(2^m)$ . . . . . . . . . . . 1332--1345
                 Lan-Da Van and   
                     Jin-Hao Tu   Power-Efficient Pipelined Reconfigurable
                                  Fixed-Width Baugh--Wooley Multipliers    1346--1355
                  Rubao Lee and   
                      Zhiwei Xu   Exploiting Stream Request Locality to
                                  Improve Query Throughput of a Data
                                  Integration System . . . . . . . . . . . 1356--1368
              K. Puttaswamy and   
                      G. H. Loh   $3$D-Integrated SRAM Components for
                                  High-Performance Microprocessors . . . . 1369--1381
                   H. Aydin and   
                      Dakai Zhu   Reliability-Aware Energy Management for
                                  Periodic Real-Time Tasks . . . . . . . . 1382--1397
                   M. Taher and   
                  T. El-Ghazawi   Virtual Configuration Management: a
                                  Technique for Partial Runtime
                                  Reconfiguration  . . . . . . . . . . . . 1398--1410
               D. Hankerson and   
                K. Karabina and   
                     A. Menezes   Analyzing the Galbraith--Lin--Scott
                                  Point Multiplication Method for Elliptic
                                  Curves over Binary Fields  . . . . . . . 1411--1420
                 A. Shoufan and   
                     S. A. Huss   High-Performance Rekeying Processor
                                  Architecture for Group Key Management    1421--1434
                    P. Kornerup   Correcting the Normalization Shift of
                                  Redundant Binary Representations . . . . 1435--1439

IEEE Transactions on Computers
Volume 58, Number 11, November, 2009

              D. R. Avresky and   
              Harald Prokop and   
                Dinesh C. Verma   Guest Editors' Introduction: Special
                                  Section on Autonomic Network Computing   1441--1443
                 V. Gramoli and   
               Y. Vigfusson and   
                  K. Birman and   
            A.-M. Kermarrec and   
                 R. van Renesse   Slicing Distributed Systems  . . . . . . 1444--1455
              P. G. Bridges and   
             M. A. Hiltunen and   
              R. D. Schlichting   Cholla: a Framework for Composing and
                                  Coordinating Adaptations in Networked
                                  Systems  . . . . . . . . . . . . . . . . 1456--1469
               S. Deshpande and   
                 M. Thottan and   
                 Tin Kam Ho and   
                      B. Sikdar   An Online Mechanism for BGP Instability
                                  Detection and Analysis . . . . . . . . . 1470--1484
               N. Shankaran and   
            J. S. Kinnebrew and   
           X. D. Koutsoukas and   
                Chenyang Lu and   
              D. C. Schmidt and   
                      G. Biswas   An Integrated Planning and Adaptive
                                  Resource Management Architecture for
                                  Distributed Real-Time Embedded Systems   1485--1499
               R. Di Pietro and   
              L. V. Mancini and   
                C. Soriente and   
               A. Spognardi and   
                      G. Tsudik   Data Security in Unattended Wireless
                                  Sensor Networks  . . . . . . . . . . . . 1500--1511
               Zizhong Chen and   
                    J. Dongarra   Highly Scalable Self-Healing Algorithms
                                  for High Performance Scientific
                                  Computing  . . . . . . . . . . . . . . . 1512--1524
                L. M. Silva and   
                  J. Alonso and   
                      J. Torres   Using Virtualization to Improve Software
                                  Rejuvenation . . . . . . . . . . . . . . 1525--1538
               G. Jaberipur and   
                     A. Kaivani   Improving the Speed of Parallel Decimal
                                  Multiplication . . . . . . . . . . . . . 1539--1552
           S. Bayat-Sarmadi and   
                    M. A. Hasan   Concurrent Error Detection in
                                  Finite-Field Arithmetic Operations Using
                                  Pipelined and Systolic Architectures . . 1553--1567
                      L. Mhamdi   PBC: a Partially Buffered Crossbar
                                  Packet Switch  . . . . . . . . . . . . . 1568--1581
                      Anonymous   IEEE Computer Society Computing Now  . . 1582--1582
                      Anonymous   CSDA Certification . . . . . . . . . . . 1583--1583
                      Anonymous   IEEE and IEEE Computer Society 2010
                                  Student Member Package . . . . . . . . . 1584--1584

IEEE Transactions on Computers
Volume 58, Number 12, December, 2009

                     Yu Hua and   
                   Bin Xiao and   
                  Jianping Wang   BR-Tree: a Scalable Prototype for
                                  Supporting Multiple Queries of
                                  Multidimensional Data  . . . . . . . . . 1585--1598
             Li Hsien Yoong and   
                 P. S. Roop and   
                 V. Vyatkin and   
                      Z. Salcic   A Synchronous Approach for IEC 61499
                                  Function Block Implementation  . . . . . 1599--1614
                Weijun Xiao and   
                  Qing Yang and   
                    Jin Ren and   
             Changsheng Xie and   
                    Huaiyang Li   Design and Analysis of Block-Level
                                  Snapshots for Data Protection and
                                  Recovery . . . . . . . . . . . . . . . . 1615--1625
                S. P. Marti and   
               J. S. Borras and   
            P. L. Rodriguez and   
                 R. U. Tena and   
                    J. D. Marin   A Complexity-Effective Out-of-Order
                                  Retirement Microarchitecture . . . . . . 1626--1639
                  S. Andrei and   
                 A. M. K. Cheng   Efficient Verification and Optimization
                                  of Real-Time Logic-Specified Systems . . 1640--1653
               Jung Sub Kim and   
               Lanping Deng and   
             P. Mangalagiri and   
                   K. Irick and   
                   K. Sobti and   
                M. Kandemir and   
               V. Narayanan and   
             C. Chakrabarti and   
               N. Pitsianis and   
                    Xiaobai Sun   An Automated Framework for Accelerating
                                  Numerical Algorithms on Reconfigurable
                                  Platforms Using
                                  Algorithmic/Architectural Optimization   1654--1667
               D. Genbrugge and   
                    L. Eeckhout   Chip Multiprocessor Design Space
                                  Exploration through Statistical
                                  Simulation . . . . . . . . . . . . . . . 1668--1681
             A. Apostolakis and   
              D. Gizopoulos and   
                M. Psarakis and   
                   A. Paschalis   Software-Based Self-Testing of Symmetric
                                  Shared-Memory Multiprocessors  . . . . . 1682--1694
                Wencheng Lu and   
                       S. Sahni   Efficient $2$D Multibit Tries for Packet
                                  Classification . . . . . . . . . . . . . 1695--1709
                D. Jankovic and   
            R. S. Stankovic and   
                      C. Moraga   Optimization of Polynomial Expressions
                                  by Using the Extended Dual Polarity  . . 1710--1725
                    Rong Ji and   
              Zhiqiang Ling and   
               Xianjun Zeng and   
                Bingcai Sui and   
                 Liang Chen and   
              Junfeng Zhang and   
               Yingjie Feng and   
                       Gang Luo   Comments on ``Leading-One Prediction
                                  with Concurrent Position Correction''    1726--1727
                      Anonymous   Call for Papers: Dependable Computer
                                  Architecture . . . . . . . . . . . . . . 1728--1728


IEEE Transactions on Computers
Volume 61, Number 4, April, 2012

                    Mun-Kyu Lee   Comments on ``Provably Sublinear Point
                                  Multiplication on Koblitz Curves and Its
                                  Hardware Implementation''  . . . . . . . 591--592


IEEE Transactions on Computers
Volume 62, Number 1, January, 2013

                 Pranava K. Jha   Comments on ``Multiple-Radix Gray Codes
                                  in Lee Metric''  . . . . . . . . . . . . 200