Table of contents for issues of ACM Journal on Emerging Technologies in Computing Systems (JETC)

Last update: Tue Aug 27 11:02:42 MDT 2024                Valid HTML 3.2!

Volume 1, Number 1, April, 2005
Volume 1, Number 2, 2005
Volume 1, Number 3, October, 2005
Volume 2, Number 1, January, 2006
Volume 2, Number 2, April, 2006
Volume 2, Number 3, July, 2006
Volume 2, Number 4, October, 2006
Volume 3, Number 1, April, 2007
Volume 3, Number 2, July, 2007
Volume 3, Number 3, November, 2007
Volume 3, Number 4, January, 2008
Volume 4, Number 1, March, 2008
Volume 4, Number 2, April, 2008
Volume 4, Number 3, August, 2008
Volume 4, Number 4, October, 2008
Volume 5, Number 1, January, 2009
Volume 5, Number 2, July, 2009
Volume 5, Number 3, August, 2009
Volume 5, Number 4, November, 2009
Volume 6, Number 1, March, 2010
Volume 6, Number 2, June, 2010
Volume 6, Number 3, August, 2010
Volume 6, Number 4, December, 2010
Volume 7, Number 1, January, 2011
Volume 7, Number 2, June, 2011
Volume 7, Number 3, August, 2011
Volume 7, Number 4, December, 2011
Volume 8, Number 1, February, 2012
Volume 8, Number 2, June, 2012
Volume 8, Number 3, August, 2012
Volume 8, Number 4, October, 2012
Volume 9, Number 1, February, 2013
Volume 9, Number 2, May, 2013
Volume 9, Number 3, September, 2013
Volume 9, Number 4, November, 2013
Volume 10, Number 1, January, 2014
Volume 10, Number 2, February, 2014
Volume 10, Number 3, April, 2014
Volume 11, Number 1, September, 2014
Volume 11, Number 2, November, 2014
Volume 11, Number 3, December, 2014
Volume 11, Number 4, April, 2015
Volume 12, Number 1, July, 2015
Volume 12, Number 2, August, 2015
Volume 12, Number 3, September, 2015
Volume 12, Number 4, July, 2016
Volume 13, Number 1, December, 2016
Volume 13, Number 2, March, 2017
Volume 13, Number 3, May, 2017
Volume 13, Number 4, August, 2017
Volume 14, Number 1, March, 2018
Volume 14, Number 2, July, 2018
Volume 14, Number 3, October, 2018
Volume 14, Number 4, December, 2018
Volume 15, Number 1, February, 2019
Volume 15, Number 2, June, 2019
Volume 15, Number 3, June, 2019
Volume 15, Number 4, December, 2019
Volume 16, Number 1, February, 2020
Volume 16, Number 2, April, 2020
Volume 16, Number 3, July, 2020
Volume 16, Number 4, October, 2020
Volume 17, Number 1, January, 2021
Volume 17, Number 2, April, 2021
Volume 17, Number 3, July, 2021
Volume 17, Number 4, July, 2021
Volume 18, Number 1, January, 2022
Volume 18, Number 2, April, 2022
Volume 18, Number 3, July, 2022
Volume 18, Number 4, October, 2022
Volume 19, Number 1, January, 2023
Volume 19, Number 2, April, 2023
Volume 19, Number 3, July, 2023
Volume 19, Number 4, October, 2023
Volume 20, Number 1, January, 2024
Volume 20, Number 2, April, 2024
Volume 20, Number 3, July, 2024


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 1, Number 1, April, 2005

            Mary Jane Irwin and   
        Vijaykrishnan Narayanan   Editorial  . . . . . . . . . . . . . . . 1--6
               Siva G. Narendra   Challenges and design choices in
                                  nanoscale CMOS . . . . . . . . . . . . . 7--49
               Sung Kyu Lim and   
     Ramprasad Ravichandran and   
                   Mike Niemier   Partitioning and placement for buildable
                                  QCA circuits . . . . . . . . . . . . . . 50--72

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 1, Number 2, 2005

            Benjamin Gojman and   
               Eric Rachlin and   
                 John E. Savage   Evaluation of design strategies for
                                  stochastically assembled nanoarray
                                  memories . . . . . . . . . . . . . . . . 73--108
             André Dehon   Nanowire-based programmable
                                  architectures  . . . . . . . . . . . . . 109--162

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 1, Number 3, October, 2005

                   J. Huang and   
              M. Momenzadeh and   
                 L. Schiano and   
                  M. Ottavi and   
                    F. Lombardi   Tile-based QCA design using
                                  majority-like logic primitives . . . . . 163--185
     Krishnendu Chakrabarty and   
                       Jun Zeng   Design automation for
                                  microfluidics-based biochips . . . . . . 186--223


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 2, Number 1, January, 2006

       Jaidev P. Patwardhan and   
                Chris Dwyer and   
            Alvin R. Lebeck and   
                Daniel J. Sorin   NANA: a nano-scale active network
                                  architecture . . . . . . . . . . . . . . 1--30
           Rodney Van Meter and   
                     Mark Oskin   Architectural implications of quantum
                                  computing technologies . . . . . . . . . 31--63

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 2, Number 2, April, 2006

                   Yuan Xie and   
             Gabriel H. Loh and   
                Bryan Black and   
                Kerry Bernstein   Design space exploration for $3$D
                                  architectures  . . . . . . . . . . . . . 65--103
                     Fei Su and   
         Krishnendu Chakrabarty   Yield enhancement of reconfigurable
                                  microfluidics-based biochips using
                                  interstitial redundancy  . . . . . . . . 104--128
             John E. Savage and   
               Eric Rachlin and   
         André DeHon and   
          Charles M. Lieber and   
                         Yue Wu   Radial addressing of nanowires . . . . . 129--154

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 2, Number 3, July, 2006

              Yehia Massoud and   
               Arthur Nieuwoudt   Modeling and design challenges and
                                  solutions for carbon nanotube-based
                                  interconnect in future high performance
                                  integrated circuits  . . . . . . . . . . 155--196
               Mehdi B. Tahoori   Application-independent defect tolerance
                                  of reconfigurable nanoarchitectures  . . 197--218
               Kushal Datta and   
          Arindam Mukherjee and   
                 Arun Ravindran   Automated design flow for diode-based
                                  nanofabrics  . . . . . . . . . . . . . . 219--241

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 2, Number 4, October, 2006

               Marco Ottavi and   
               Luca Schiano and   
          Fabrizio Lombardi and   
                 Douglas Tougaw   HDLQ: A HDL environment for QCA design   243--261
              Daniel Davids and   
           Siddhartha Datta and   
          Arindam Mukherjee and   
               Bharat Joshi and   
                 Arun Ravindran   Multiple fault diagnosis in digital
                                  microfluidic biochips  . . . . . . . . . 262--276
           Aditya K. Prasad and   
            Vivek V. Shende and   
             Igor L. Markov and   
              John P. Hayes and   
                 Ketan N. Patel   Data structures and algorithms for
                                  simplifying reversible circuits  . . . . 277--293


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 3, Number 1, April, 2007

                   Wei Zhao and   
                         Yu Cao   Predictive technology model for
                                  nano-CMOS design exploration . . . . . . 1:1--1:??
           Gabriel Schulhof and   
               Konrad Walus and   
              Graham A. Jullien   Simulation of random cell displacements
                                  in QCA . . . . . . . . . . . . . . . . . 2:1--2:??
            Garrett S. Rose and   
                 Yuxing Yao and   
              James M. Tour and   
               Adam C. Cabe and   
      Nadine Gergel-Hackett and   
          Nabanita Majumdar and   
               John C. Bean and   
          Lloyd R. Harriott and   
                 Mircea R. Stan   Designing CMOS/molecular memories while
                                  considering device parameter variations  3:1--3:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 3, Number 2, July, 2007

                 Sally A. McKee   Editorial to special issue on reliable
                                  computing  . . . . . . . . . . . . . . . 4:1--4:??
   Mary M. Eshaghian-Wilner and   
                Alex Khitun and   
                Shiva Navab and   
                   Kang L. Wang   The spin-wave nanoscale reconfigurable
                                  mesh and the labeling problem  . . . . . 5:1--5:??
              Lucian Prodan and   
              Mihai Udrescu and   
               Oana Boncalo and   
                Mircea Vladutiu   Design for dependability in emerging
                                  technologies . . . . . . . . . . . . . . 6:1--6:??
            Andy M. Tyrrell and   
            Andrew J. Greensted   Evolving dependability . . . . . . . . . 7:1--7:??
        Luká\vs Sekanina   Evolutionary functional recovery in
                                  virtual reconfigurable circuits  . . . . 8:1--8:??
          Gianluca Tempesti and   
               Daniel Mange and   
         Pierre-Andre Mudry and   
          Joël Rossier and   
                 Andre Stauffer   Self-replicating hardware for
                                  reliability: The Embryonics Project  . . 9:1--9:??
          Jaidev Patwardhan and   
                Chris Dwyer and   
                Alvin R. Lebeck   A self-organizing defect tolerant SIMD
                                  architecture . . . . . . . . . . . . . . 10:1--10:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 3, Number 3, November, 2007

     Krishnendu Chakrabarty and   
              Sachin Sapatnekar   Editorial to special issue DAC 2006  . . 11:1--11:??
              Bipul C. Paul and   
             Shinobu Fujita and   
             Masaki Okajima and   
                     Thomas Lee   Prospect of ballistic CNFET in high
                                  performance applications: Modeling and
                                  analysis . . . . . . . . . . . . . . . . 12:1--12:??
              Ping-Hung Yuh and   
              Chia-Lin Yang and   
                  Yao-Wen Chang   Placement of defect-tolerant digital
                                  microfluidic biochips using the $T$-tree
                                  formulation  . . . . . . . . . . . . . . 13:1--13:??
                     Tao Xu and   
           William L. Hwang and   
                     Fei Su and   
         Krishnendu Chakrabarty   Automated design of pin-constrained
                                  digital microfluidic biochips under
                                  droplet-interference constraints . . . . 14:1--14:??
             Reza M. P. Rad and   
           Mohammad Tehranipoor   Evaluating area and performance of
                                  hybrid FPGAs with nanoscale clusters and
                                  CMOS routing . . . . . . . . . . . . . . 15:1--15:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 3, Number 4, January, 2008

                     Fei Su and   
         Krishnendu Chakrabarty   High-level synthesis of digital
                                  microfluidic biochips  . . . . . . . . . 1:1--1:??
           Rodney Van Meter and   
                W. J. Munro and   
                 Kae Nemoto and   
                  Kohei M. Itoh   Arithmetic on a distributed-memory
                                  quantum multicomputer  . . . . . . . . . 2:1--2:??
                 Xiaojun Ma and   
                 Jing Huang and   
              Fabrizio Lombardi   A model for computing and energy
                                  dissipation of molecular QCA devices and
                                  circuits . . . . . . . . . . . . . . . . 3:1--3:??
             Min-Lun Chuang and   
                  Chun-Yao Wang   Synthesis of reversible sequential
                                  elements . . . . . . . . . . . . . . . . 4:1--4:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 4, Number 1, March, 2008

          Tzvetan S. Metodi and   
          Darshan D. Thaker and   
            Andrew W. Cross and   
            Isaac L. Chuang and   
              Frederic T. Chong   High-level interconnect model for the
                                  quantum logic array architecture . . . . 1:1--1:??
               James Donald and   
                   Niraj K. Jha   Reversible logic synthesis with Fredkin
                                  and Peres gates  . . . . . . . . . . . . 2:1--2:??
          Carlotta Guiducci and   
              Christine Nardini   High parallelism, portability, and broad
                                  accessibility: Technologies for genomics 3:1--3:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 4, Number 2, April, 2008

        Vijaykrishnan Narayanan   Editorial  . . . . . . . . . . . . . . . 4:1--4:??
              R. Iris Bahar and   
         Krishnendu Chakrabarty   Introduction to joint ACM JETC/TODAES
                                  special issue on new, emerging, and
                                  specialized technologies . . . . . . . . 5:1--5:??
             Shih-Hsien Kuo and   
                Bruce Tidor and   
                    Jacob White   A meshless, spectrally accurate,
                                  integral equation solver for molecular
                                  surface electrostatics . . . . . . . . . 6:1--6:??
                   Jie Deng and   
                 Albert Lin and   
              Gordon C. Wan and   
              H.-S. Philip Wong   Carbon nanotube transistor compact model
                                  for circuit design and performance
                                  optimization . . . . . . . . . . . . . . 7:1--7:??
              Josep Carmona and   
           Jordi Cortadella and   
             Yousuke Takada and   
                Ferdinand Peper   Formal methods for the analysis and
                                  synthesis of nanometer-scale cellular
                                  arrays . . . . . . . . . . . . . . . . . 8:1--8:??
            Michael Crocker and   
            Michael Niemier and   
               X. Sharon Hu and   
                Marya Lieberman   Molecular QCA design with chemically
                                  reasonable constraints . . . . . . . . . 9:1--9:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 4, Number 3, August, 2008

            Alvin R. Lebeck and   
         Krishnendu Chakrabarty   Introduction to DAC 2007 special section 10:1--10:??
                     Tao Xu and   
         Krishnendu Chakrabarty   Integrated droplet routing and defect
                                  tolerance in the synthesis of digital
                                  microfluidic biochips  . . . . . . . . . 11:1--11:??
          Tsung-Ching Huang and   
     Kwang-Ting (Tim) Cheng and   
            Huai-Yuan Tseng and   
                 Chen-Pang Kung   Reliability analysis for flexible
                                  electronics: Case study of integrated
                                  a-Si:H TFT scan driver . . . . . . . . . 12:1--12:??
                    Jing Li and   
              Aditya Bansal and   
               Swarop Ghosh and   
                    Kaushik Roy   An alternate design paradigm for
                                  low-power, low-cost, testable hybrid
                                  systems using scaled LTPS TFTs . . . . . 13:1--13:??
                   Reza Rad and   
           Mohammad Tehranipoor   SCT: a novel approach for testing and
                                  configuring nanoscale devices  . . . . . 14:1--14:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 4, Number 4, October, 2008

                   Yuan Xie and   
                 Jason Cong and   
                   Paul Franzon   Editorial: Special issue on $3$D
                                  integrated circuits and
                                  microarchitectures . . . . . . . . . . . 15:1--15:??
                 Taeho Kgil and   
                  Ali Saidi and   
             Nathan Binkert and   
            Steve Reinhardt and   
         Krisztian Flautner and   
                   Trevor Mudge   PicoServer: Using $3$D stacking
                                  technology to build energy efficient
                                  servers  . . . . . . . . . . . . . . . . 16:1--16:??
                  Yuchun Ma and   
              Yongxiang Liu and   
                Eren Kursun and   
              Glenn Reinman and   
                     Jason Cong   Investigating the effects of fine-grain
                                  three-dimensional integration on
                                  microarchitecture design . . . . . . . . 17:1--17:??
                  Yong Zhan and   
           Sachin S. Sapatnekar   Automated module assignment in
                                  stacked-Vdd designs for high-efficiency
                                  power delivery . . . . . . . . . . . . . 18:1--18:??
               Cesare Ferri and   
               Sherief Reda and   
                  R. Iris Bahar   Parametric yield management for $3$D
                                  ICs: Models and strategies for
                                  improvement  . . . . . . . . . . . . . . 19:1--19:??
           Nobuaki Miyakawa and   
             Eiri Hashimoto and   
          Takanori Maebashi and   
            Natsuo Nakamura and   
               Yutaka Sacho and   
           Shigeto Nakayama and   
                Shinjiro Toyoda   Multilayer stacking technology using
                                  wafer-to-wafer stacked method  . . . . . 20:1--20:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 5, Number 1, January, 2009

                 Sandeep Shukla   Guest editorial: IEEE/ACM Symposium on
                                  Nanoscale Architectures (NANOARCH07) . . 1:1--1:??
                  Shuo Wang and   
                   Lei Wang and   
                    Faquir Jain   Towards achieving reliable and
                                  high-performance nanocomputing via
                                  dynamic redundancy allocation  . . . . . 2:1--2:??
                 Z. F. Wang and   
              Huaixiu Zheng and   
                  Q. W. Shi and   
                       Jie Chen   Emerging nanodevice paradigm:
                                  Graphene-based electronics for nanoscale
                                  computing  . . . . . . . . . . . . . . . 3:1--3:??
               Baris Taskin and   
                  Andy Chiu and   
           Jonathan Salkind and   
                Daniel Venutolo   A shift-register-based QCA memory
                                  architecture . . . . . . . . . . . . . . 4:1--4:??
                 Dennis Huo and   
                 Qiaoyan Yu and   
              David Wolpert and   
                    Paul Ampadu   A simulator for ballistic nanostructures
                                  in a $2$-D electron gas  . . . . . . . . 5:1--5:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 5, Number 2, July, 2009

                  R. Iris Bahar   Introduction to special section: Best of
                                  NANOARCH 2008  . . . . . . . . . . . . . 6:1--6:??
             Prateek Mishra and   
             Anish Muttreja and   
                   Niraj K. Jha   Low-power FinFET circuit synthesis using
                                  multiple supply and threshold voltages   7:1--7:??
            Michael Crocker and   
               X. Sharon Hu and   
                Michael Niemier   Defects and faults in QCA-based PLAs . . 8:1--8:??
                 Xiaoxia Wu and   
           Paul Falkenstern and   
     Krishnendu Chakrabarty and   
                       Yuan Xie   Scan-chain design and optimization for
                                  three-dimensional integrated circuits    9:1--9:??
           Siddhartha Datta and   
               Bharat Joshi and   
             Arun Ravindran and   
              Arindam Mukherjee   Efficient parallel testing and diagnosis
                                  of digital microfluidic biochips . . . . 10:1--10:??
               Mehdi B. Tahoori   Low-overhead defect tolerance in
                                  crossbar nanoarchitectures . . . . . . . 11:1--11:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 5, Number 3, August, 2009

   Rajat Subhra Chakraborty and   
                  Swarup Bhunia   A study of asynchronous design
                                  methodology for robust CMOS-nano hybrid
                                  system design  . . . . . . . . . . . . . 12:1--12:??
                  Wei Zhang and   
               Niraj K. Jha and   
                       Li Shang   A hybrid Nano/CMOS dynamically
                                  reconfigurable system --- Part II:
                                  Design optimization flow . . . . . . . . 13:1--13:??
         Muzaffer O. Simsir and   
            Srihari Cadambi and   
        Franjo Ivanv\vci\'c and   
           Martin Roetteler and   
                   Niraj K. Jha   A hybrid nano-CMOS architecture for
                                  defect and fault tolerance . . . . . . . 14:1--14:??
                  Shuo Wang and   
                Jianwei Dai and   
          El-Sayed Hasaneen and   
                   Lei Wang and   
                    Faquir Jain   Utilizing quantum dot transistors with
                                  programmable threshold voltages for
                                  low-power mobile computing . . . . . . . 15:1--15:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 5, Number 4, November, 2009

                  Wei Zhang and   
               Niraj K. Jha and   
                       Li Shang   A hybrid nano/CMOS dynamically
                                  reconfigurable system --- Part I:
                                  Architecture . . . . . . . . . . . . . . 16:1--16:??
                  Wei Zhang and   
               Niraj K. Jha and   
                       Li Shang   Design space exploration and data memory
                                  architecture design for a hybrid
                                  nano/CMOS dynamically reconfigurable
                                  architecture . . . . . . . . . . . . . . 17:1--17:??
                Weiguo Tang and   
                   Lei Wang and   
              Fabrizio Lombardi   A defect/error-tolerant nanosystem
                                  architecture for DSP . . . . . . . . . . 18:1--18:??
          Timothy J. Dysart and   
                 Peter M. Kogge   Organizing wires for reliability in
                                  magnetic QCA . . . . . . . . . . . . . . 19:1--19:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 6, Number 1, March, 2010

         Krishnendu Chakrabarty   Editorial  . . . . . . . . . . . . . . . 1:1--1:??
                Chun-Yi Lee and   
                   Niraj K. Jha   FinFET-based power simulator for
                                  interconnection networks . . . . . . . . 2:1--2:??
                   Yang Liu and   
                Chris Dwyer and   
                Alvin R. Lebeck   Routing in self-organizing nano-scale
                                  irregular networks . . . . . . . . . . . 3:1--3:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 6, Number 2, June, 2010

               Taskin Kocak and   
                 Dhiraj Pradhan   Introduction to design techniques for
                                  energy harvesting  . . . . . . . . . . . 4:1--4:??
               Justin Wenck and   
              Jamie Collier and   
               Jeff Siebert and   
          Rajeevan Amirtharajah   Scaling self-timed systems powered by
                                  mechanical vibration energy harvesting   5:1--5:??
                 W. S. Wang and   
               T. O'Donnell and   
                    N. Wang and   
                   M. Hayes and   
                 B. O'Flynn and   
                   C. O'Mathuna   Design considerations of sub-mW indoor
                                  light energy harvesting for wireless
                                  sensor systems . . . . . . . . . . . . . 6:1--6:??
              Clemens Moser and   
              Jian-Jia Chen and   
                  Lothar Thiele   An energy management framework for
                                  energy harvesting embedded systems . . . 7:1--7:??
          Saraju P. Mohanty and   
              Dhiraj K. Pradhan   ULS: a dual-$ V_{th} $ /high-$ \kappa $
                                  nano-CMOS universal level shifter for
                                  system-level power management  . . . . . 8:1--8:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 6, Number 3, August, 2010

                Jianwei Dai and   
                   Lei Wang and   
              Fabrizio Lombardi   An information-theoretic analysis of
                                  quantum-dot cellular automata for defect
                                  tolerance  . . . . . . . . . . . . . . . 9:1--9:??
                  Wei Zhang and   
               Niraj K. Jha and   
                       Li Shang   Low-power $3$D nano/CMOS hybrid
                                  dynamically reconfigurable architecture  10:1--10:??
                  Yang Zhao and   
                     Tao Xu and   
         Krishnendu Chakrabarty   Integrated control-path design and error
                                  recovery in the synthesis of digital
                                  microfluidic lab-on-chip . . . . . . . . 11:1--11:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 6, Number 4, December, 2010

               Ajay N. Bhoj and   
                   Niraj K. Jha   Gated-diode FinFET DRAMs: Device and
                                  circuit design-considerations  . . . . . 12:1--12:??
               Mehdi Saeedi and   
       Morteza Saheb Zamani and   
              Mehdi Sedighi and   
                 Zahra Sasanian   Reversible circuit synthesis using a
                                  cycle-based approach . . . . . . . . . . 13:1--13:??
         Himanshu Thapliyal and   
          Nagarajan Ranganathan   Design of reversible sequential circuits
                                  optimizing quantum cost, delay, and
                                  garbage outputs  . . . . . . . . . . . . 14:1--14:??
               Montek Singh and   
               Steven M. Nowick   Call for Papers: Deadline: March 15,
                                  2011 . . . . . . . . . . . . . . . . . . 15:1--15:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 7, Number 1, January, 2011

                 Shamik Das and   
                Garrett S. Rose   Introduction to Special Issue:
                                  Highlights of NANOARCH'09  . . . . . . . 1:1--1:??
              Aaron Dingler and   
         Michael T. Niemier and   
           Xiaobo Sharon Hu and   
                      Evan Lent   Performance and Energy Impact of Locally
                                  Controlled NML Circuits  . . . . . . . . 2:1--2:??
           P.-E. Gaillardon and   
                F. Clermidy and   
                I. O'Connor and   
                     J. Liu and   
                  M. Amadou and   
                   G. Nicolescu   Matrix Nanodevice-Based Logic
                                  Architectures and Associated Functional
                                  Mapping Method . . . . . . . . . . . . . 3:1--3:??
            Nor Zaidi Haron and   
                  Said Hamdioui   Redundant Residue Number System Code for
                                  Fault-Tolerant Hybrid Memories . . . . . 4:1--4:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 7, Number 2, June, 2011

                   Li Shang and   
                     Qianfan Xu   Introduction to nanophotonic
                                  communication technology integration . . 5:1--5:??
          Raymond G. Beausoleil   Large-scale integrated photonics for
                                  high-performance interconnects . . . . . 6:1--6:??
         Aleksandr Biberman and   
               Kyle Preston and   
             Gilbert Hendry and   
Nicolás Sherwood-Droz and   
               Johnnie Chan and   
              Jacob S. Levy and   
              Michal Lipson and   
                  Keren Bergman   Photonic network-on-chip architectures
                                  using multilayer deposited silicon
                                  materials for high-performance chip
                                  multiprocessors  . . . . . . . . . . . . 7:1--7:??
                   Zheng Li and   
           Moustafa Mohamed and   
                    Xi Chen and   
                Hongyu Zhou and   
             Alan Mickelson and   
                   Li Shang and   
            Manish Vachharajani   Iris: a hybrid nanophotonic network
                                  design for high-performance and
                                  low-power on-chip communication  . . . . 8:1--8:??
         Mark J. Cianchetti and   
              David H. Albonesi   A low-latency, high-throughput on-chip
                                  optical router architecture for future
                                  chip multiprocessors . . . . . . . . . . 9:1--9:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 7, Number 3, August, 2011

                 Meng Zhang and   
                   Niraj K. Jha   FinFET-Based Power Management for
                                  Improved DPA Resistance with Low
                                  Overhead . . . . . . . . . . . . . . . . 10:1--10:??
             Byung-Soo Choi and   
               Rodney Van Meter   On the Effect of Quantum Interaction
                                  Distance on Quantum Addition Circuits    11:1--11:17
           Sezer Gören and   
           H. Fatih Ugurdag and   
                     Okan Palaz   Defect-Aware Nanocrossbar Logic Mapping
                                  through Matrix Canonization Using
                                  Two-Dimensional Radix Sort . . . . . . . 12:1--12:??
         Rajeswari Devadoss and   
                 Kolin Paul and   
                M. Balakrishnan   p-QCA: a Tiled Programmable Fabric
                                  Architecture Using Molecular Quantum-Dot
                                  Cellular Automata  . . . . . . . . . . . 13:1--13:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 7, Number 4, December, 2011

               Montek Singh and   
               Steven M. Nowick   Introduction to Special Issue:
                                  Asynchrony in System Design  . . . . . . 14:1--14:??
                Marco Vacca and   
       Mariagrazia Graziano and   
               Maurizio Zamboni   Asynchronous Solutions for Nanomagnetic
                                  Logic Circuits . . . . . . . . . . . . . 15:1--15:??
                Xuefu Zhang and   
               Delong Shang and   
                    Fei Xia and   
                  Alex Yakovlev   A Novel Power Delivery Method for
                                  Asynchronous Loads in Energy Harvesting
                                  Systems  . . . . . . . . . . . . . . . . 16:1--16:??
              Luis A. Plana and   
                David Clark and   
             Simon Davidson and   
               Steve Furber and   
                Jim Garside and   
           Eustace Painkras and   
             Jeffrey Pepper and   
               Steve Temple and   
                John Bainbridge   SpiNNaker: Design and Implementation of
                                  a GALS Multicore System-on-Chip  . . . . 17:1--17:??
          Marc Galceran-Oms and   
         Alexander Gotmanov and   
           Jordi Cortadella and   
               Mike Kishinevsky   Microarchitectural Transformations Using
                                  Elasticity . . . . . . . . . . . . . . . 18:1--18:??
          Basit Riaz Sheikh and   
                  Rajit Manohar   Energy-Efficient Pipeline Templates for
                                  High-Performance Asynchronous Circuits   19:1--19:??
          Philippe Matherat and   
            Marc-Thierry Jaekel   Relativistic Causality and Clockless
                                  Circuits . . . . . . . . . . . . . . . . 20:1--20:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 8, Number 1, February, 2012

            Michael Crocker and   
            Michael Niemier and   
                   X. Sharon Hu   A Reconfigurable PLA Architecture for
                                  Nanomagnet Logic . . . . . . . . . . . . 1:1--1:??
           Michael B. Henry and   
               Leyla Nazhandali   From Transistors to NEMS: Highly
                                  Efficient Power-Gating of CMOS Circuits  2:1--2:??
          Jeremy R. Tolbert and   
              Pratik Kabali and   
            Simeranjit Brar and   
            Saibal Mukhopadhyay   Modeling and Designing for Accuracy and
                                  Energy Efficiency in Wireless
                                  Electroencephalography Systems . . . . . 3:1--3:??
              Makoto Naruse and   
            Ferdinand Peper and   
            Kouichi Akahane and   
          Naokatsu Yamamoto and   
            Tadashi Kawazoe and   
                 Naoya Tate and   
                 Motoichi Ohtsu   Skew Dependence of Nanophotonic Devices
                                  Based on Optical Near-Field Interactions 4:1--4:??
                  Yaoyao Ye and   
                   Jiang Xu and   
                 Xiaowen Wu and   
                  Wei Zhang and   
                Weichen Liu and   
                  Mahdi Nikdast   A Torus-Based Hierarchical
                                  Optical-Electronic Network-on-Chip for
                                  Multiprocessor System-on-Chip  . . . . . 5:1--5:??
                   H. Manem and   
               J. Rajendran and   
                     G. S. Rose   Design Considerations for Multilevel
                                  CMOS\slash Nano Memristive Memory  . . . 6:1--6:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 8, Number 2, June, 2012

              Swarup Bhunia and   
                Darrin J. Young   Introduction to Special Issue on
                                  Implantable Electronics  . . . . . . . . 7:1--7:??
                      Wen H. Ko   Early History and Challenges of
                                  Implantable Electronics  . . . . . . . . 8:1--8:??
     Muhammad Tariqus Salam and   
              Mohamad Sawan and   
               Dang Khoa Nguyen   Implantable Closed-Loop Epilepsy
                                  Prosthesis: Modeling, Implementation and
                                  Validation . . . . . . . . . . . . . . . 9:1--9:??
             Mrigank Sharad and   
            Sumeet K. Gupta and   
        Shriram Raghunathan and   
          Pedro P. Irazoqui and   
                    Kaushik Roy   Low-Power Architecture for Epileptic
                                  Seizure Detection Based on Reduced
                                  Complexity DWT . . . . . . . . . . . . . 10:1--10:??
        Steve J. A. Majerus and   
        Steven L. Garverick and   
          Michael A. Suster and   
            Paul C. Fletter and   
              Margot S. Damaser   Wireless, Ultra-Low-Power Implantable
                                  Sensor for Chronic Bladder Pressure
                                  Monitoring . . . . . . . . . . . . . . . 11:1--11:??
               Yu-Jie Huang and   
             Hsin-Hung Liao and   
               Pen-Li Huang and   
                   Tao Wang and   
               Yao-Joe Yang and   
              Yao-Hong Wang and   
                    Shey-Shi Lu   An Implantable Release-on-Demand CMOS
                                  Drug Delivery SoC Using Electrothermal
                                  Activation Technique . . . . . . . . . . 12:1--12:??
                 Zhenyu Sun and   
                 Xiang Chen and   
               Yaojun Zhang and   
                     Hai Li and   
                     Yiran Chen   Nonvolatile Memories as the Data Storage
                                  System for Implantable ECG Recorder  . . 13:1--13:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 8, Number 3, August, 2012

              Saraju P. Mohanty   Special section on new circuit and
                                  architecture-level solutions for
                                  multidiscipline systems  . . . . . . . . 14:1--14:??
           Ashok Srivastava and   
                     Yao Xu and   
                   Yang Liu and   
          Ashwani K. Sharma and   
                  Clay Mayberry   CMOS LC voltage controlled oscillator
                                  design using multiwalled and
                                  single-walled carbon nanotube wire
                                  inductors  . . . . . . . . . . . . . . . 15:1--15:??
    Venkataraman Mahalingam and   
      Nagarajan Ranganathan and   
            Ransford Hyman, Jr.   Dynamic clock stretching for variation
                                  compensation in VLSI circuit design  . . 16:1--16:??
                  Sudip Roy and   
              Debasis Mitra and   
    Bhargab B. Bhattacharya and   
         Krishnendu Chakrabarty   Congestion-aware layout design for
                                  high-throughput digital microfluidic
                                  biochips . . . . . . . . . . . . . . . . 17:1--17:??
         Narayanan Komerath and   
                   Aravinda Kar   Retail beamed power using millimeter
                                  waves: Survey  . . . . . . . . . . . . . 18:1--18:??
    Ashok Kumar Palaniswamy and   
               Spyros Tragoudas   An efficient heuristic to identify
                                  threshold logic functions  . . . . . . . 19:1--19:??
                      Hu Xu and   
        Vasilis F. Pavlidis and   
            Giovanni De Micheli   Effect of process variations in $3$D
                                  global clock distribution networks . . . 20:1--20:??
                Eren Kursun and   
                Jamil Wakil and   
               Mukta Farooq and   
                  Robert Hannon   Spatial and temporal thermal
                                  characterization of stacked multicore
                                  architectures  . . . . . . . . . . . . . 21:1--21:??
                    Bao Liu and   
                Xuemei Chen and   
                  Fiona Teshome   Resilient and adaptive performance logic 22:1--22:??
                Kevin Chang and   
                  Sujay Deb and   
              Amlan Ganguly and   
                  Xinmin Yu and   
           Suman Prasad Sah and   
        Partha Pratim Pande and   
            Benjamin Belzer and   
                  Deukhyoun Heo   Performance evaluation and design
                                  trade-offs for wireless network-on-chip
                                  architectures  . . . . . . . . . . . . . 23:1--23:??
             Byung-Soo Choi and   
               Rodney Van Meter   A $ \Theta (\sqrt n) $-depth quantum
                                  adder on the $2$D NTC quantum computer
                                  architecture . . . . . . . . . . . . . . 24:1--24:??
                Jiale Huang and   
                 Minhao Zhu and   
               Shengqi Yang and   
               Pallav Gupta and   
                  Wei Zhang and   
            Steven M. Rubin and   
      Gilda Garretón and   
                         Jin He   A physical design tool for carbon
                                  nanotube field-effect transistor
                                  circuits . . . . . . . . . . . . . . . . 25:1--25:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 8, Number 4, October, 2012

        Partha Pratim Pande and   
                  Amlan Ganguly   Introduction to the special issue on
                                  sustainable and green computing systems  26:1--26:??
        Prithviraj Banerjee and   
          Chandrakant Patel and   
                Cullen Bash and   
                  Amip Shah and   
                  Martin Arlitt   Towards a net-zero data center . . . . . 27:1--27:??
             Siddharth Garg and   
           Diana Marculescu and   
                Radu Marculescu   Technology-driven limits on runtime
                                  power management algorithms for
                                  multiprocessor systems-on-chip . . . . . 28:1--28:??
            Giacomo Ghidini and   
                   Sajal K. Das   Energy-efficient Markov chain-based duty
                                  cycling schemes for greener wireless
                                  sensor networks  . . . . . . . . . . . . 29:1--29:??
             Landon H. Sego and   
Andrés Márquez and   
              Andrew Rawson and   
                Tahir Cader and   
                  Kevin Fox and   
  William I. Gustafson, Jr. and   
           Christopher J. Mundy   Implementing the data center energy
                                  productivity metric  . . . . . . . . . . 30:1--30:??
     Vlasia Anagnostopoulou and   
              Susmit Biswas and   
            Heba Saadeldeen and   
                Alan Savage and   
          Ricardo Bianchini and   
                   Tao Yang and   
             Diana Franklin and   
              Frederic T. Chong   Barely alive memory servers: Keeping
                                  data active in a low-power state . . . . 31:1--31:??
         Hafiz Fahad Sheikh and   
               Hengxing Tan and   
               Ishfaq Ahmad and   
               Sanjay Ranka and   
                 Phanisekhar Bv   Energy- and performance-aware scheduling
                                  of tasks on parallel and distributed
                                  systems  . . . . . . . . . . . . . . . . 32:1--32:??
               Krishna Kant and   
         Muthukumar Murugan and   
                 David H. C. Du   Enhancing data center sustainability
                                  through energy-adaptive computing  . . . 33:1--33:??
               Zahra Abbasi and   
           Tridib Mukherjee and   
     Georgios Varsamopoulos and   
            Sandeep K. S. Gupta   DAHM: a green and dynamic Web
                                  application hosting manager across
                                  geographically distributed data centers  34:1--34:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 9, Number 1, February, 2013

              S. Srinivasan and   
                V. Kamakoti and   
                A. Bhattacharya   A Novel Algorithm for Fast Synthesis of
                                  DNA Probes on Microarrays  . . . . . . . 1:1--1:??
               Elena Maftei and   
                   Paul Pop and   
                     Jan Madsen   Module-Based Synthesis of Digital
                                  Microfluidic Biochips with Droplet-Aware
                                  Operation Execution  . . . . . . . . . . 2:1--2:??
            Ferdinand Peper and   
                    Jia Lee and   
              Josep Carmona and   
           Jordi Cortadella and   
                 Kenichi Morita   Brownian Circuits: Fundamentals  . . . . 3:1--3:??
             Behnam Ghavami and   
                Mohsen Raji and   
             Hossein Pedram and   
               Mehdi B. Tahoori   Design and Analysis of a Robust Carbon
                                  Nanotube-Based Asynchronous Primitive
                                  Circuit  . . . . . . . . . . . . . . . . 4:1--4:??
             Yung-Chih Chen and   
          Soumya Eachempati and   
              Chun-Yao Wang and   
                Suman Datta and   
                   Yuan Xie and   
        Vijaykrishnan Narayanan   A Synthesis Algorithm for Reconfigurable
                                  Single-Electron Transistor Arrays  . . . 5:1--5:??
               Aoxiang Tang and   
                   Niraj K. Jha   Thermal Characterization of Test
                                  Techniques for FinFET and $3$D
                                  Integrated Circuits  . . . . . . . . . . 6:1--6:??
                  Shuo Wang and   
                Jianwei Dai and   
                       Lei Wang   Hybrid Redundancy for Defect Tolerance
                                  in Molecular Crossbar Memory . . . . . . 7:1--7:??
          Pritish Narayanan and   
       Michael Leuchtenburg and   
                 Jorge Kina and   
               Prachi Joshi and   
       Pavan Panchapakeshan and   
                Chi On Chui and   
               C. Andras Moritz   Variability in Nanoscale Fabrics:
                                  Bottom-up Integrated Analysis and
                                  Mitigation . . . . . . . . . . . . . . . 8:1--8:??
                Jiale Liang and   
                Stanley Yeh and   
              S. Simon Wong and   
              H.-S. Philip Wong   Effect of Wordline/Bitline Scaling on
                                  the Performance, Energy Consumption, and
                                  Reliability of Cross-Point Memory Array  9:1--9:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 9, Number 2, May, 2013

              Bipul C. Paul and   
            Arijit Raychowdhury   Introduction to the special issue on
                                  memory technologies  . . . . . . . . . . 10:1--10:??
             J. Joshua Yang and   
            R. Stanley Williams   Memristive devices in computing system:
                                  Promises and challenges  . . . . . . . . 11:1--11:??
           Bryan L. Jackson and   
            Bipin Rajendran and   
         Gregory S. Corrado and   
         Matthew Breitwisch and   
           Geoffrey W. Burr and   
                Roger Cheek and   
     Kailash Gopalakrishnan and   
               Simone Raoux and   
         Charles T. Rettner and   
             Alvaro Padilla and   
            Alex G. Schrott and   
            Rohit S. Shenoy and   
       Bülent N. Kurdi and   
               Chung H. Lam and   
            Dharmendra S. Modha   Nanoscale electronic synapses using
                                  phase change devices . . . . . . . . . . 12:1--12:??
             Dmytro Apalkov and   
        Alexey Khvalkovskiy and   
               Steven Watts and   
           Vladimir Nikitin and   
                 Xueti Tang and   
              Daniel Lottis and   
                Kiseok Moon and   
                   Xiao Luo and   
                Eugene Chen and   
                 Adrian Ong and   
   Alexander Driskill-Smith and   
                Mohamad Krounbi   Spin-transfer torque magnetic random
                                  access memory (STT-MRAM) . . . . . . . . 13:1--13:??
        Niladri N. Mojumder and   
               Xuanyao Fong and   
          Charles Augustine and   
            Sumeet K. Gupta and   
          Sri Harsha Choday and   
                    Kaushik Roy   Dual pillar spin-transfer torque MRAMs
                                  for low power applications . . . . . . . 14:1--14:??
           Subho Chatterjee and   
          Sayeef Salahuddin and   
               Satish Kumar and   
            Saibal Mukhopadhyay   Electrothermal analysis of
                                  spin-transfer-torque random access
                                  memory arrays  . . . . . . . . . . . . . 15:1--15:??
                 Yiran Chen and   
              Weng-Fai Wong and   
                     Hai Li and   
              Cheng-Kok Koh and   
               Yaojun Zhang and   
                      Wujie Wen   On-chip caches built on multilevel
                                  spin-transfer torque RAM cells and its
                                  optimizations  . . . . . . . . . . . . . 16:1--16:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 9, Number 3, September, 2013

         Himanshu Thapliyal and   
          Nagarajan Ranganathan   Design of efficient reversible
                                  logic-based binary and BCD adder
                                  circuits . . . . . . . . . . . . . . . . 17:1--17:??
              Woo Hyung Lee and   
                Pinaki Mazumder   Color image processing with multi-peak
                                  resonant tunneling diodes  . . . . . . . 18:1--18:??
          Shashikanth Bobba and   
       Ashutosh Chakraborty and   
             Olivier Thomas and   
             Perrine Batude and   
            Giovanni de Micheli   Cell transformations and physical design
                                  techniques for $3$D monolithic
                                  integrated circuits  . . . . . . . . . . 19:1--19:??
               Aoxiang Tang and   
                   Niraj K. Jha   Design space exploration of FinFET cache 20:1--20:??
              Masoud Zamani and   
             Hanieh Mirzaei and   
               Mehdi B. Tahoori   ILP formulations for
                                  variation/defect-tolerant logic mapping
                                  on crossbar nano-architectures . . . . . 21:1--21:??
                Guangyu Sun and   
                Eren Kursun and   
             Jude A. Rivers and   
                       Yuan Xie   Exploring the vulnerability of CMPs to
                                  soft errors with $3$D stacked
                                  nonvolatile memory . . . . . . . . . . . 22:1--22:??
               Shengqi Yang and   
               Wenping Wang and   
                 Mark Hagan and   
                  Wei Zhang and   
               Pallav Gupta and   
                         Yu Cao   NBTI-aware circuit node criticality
                                  computation  . . . . . . . . . . . . . . 23:1--23:??
                Paul Wettin and   
       Anuroop Vidapalapati and   
               Amlan Gangul and   
            Partha Pratim Pande   Complex network-enabled robust wireless
                                  network-on-chip architectures  . . . . . 24:1--24:??
               Xuehui Zhang and   
          Andrew Ferraiuolo and   
           Mohammad Tehranipoor   Detection of Trojans using a combined
                                  ring oscillator network and off-chip
                                  transient power analysis . . . . . . . . 25:1--25:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 9, Number 4, November, 2013

              Carlotta Guiducci   Introduction to Special Issue on
                                  Bioinformatics . . . . . . . . . . . . . 26:1--26:??
           Damiano Piovesan and   
           Giuseppe Profiti and   
        Pier Luigi Martelli and   
            Piero Fariselli and   
                   Rita Casadio   Extended and Robust Protein Sequence
                                  Annotation over Conservative
                                  Nonhierarchical Clusters: The Case Study
                                  of the ABC Transporters  . . . . . . . . 27:1--27:??
            Francesco Abate and   
           Andrea Acquaviva and   
              Elisa Ficarra and   
                   Enrico Macii   Integration of Literature with
                                  Heterogeneous Information for Genes
                                  Correlation Scoring  . . . . . . . . . . 28:1--28:??
       Mariagrazia Graziano and   
             Stefano Frache and   
               Maurizio Zamboni   A Hardware Viewpoint on Biosequence
                                  Analysis: What's Next? . . . . . . . . . 29:1--29:??
                 Lyn Venken and   
           Kathleen Marchal and   
               Jos Vanderleyden   Synthetic Biology and Microdevices: a
                                  Powerful Combination . . . . . . . . . . 30:1--30:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 10, Number 1, January, 2014

                        Editors   Introduction to special issue on
                                  reliability and device degradation in
                                  emerging technologies  . . . . . . . . . 1:1--1:??
 Haldun Küflüoglu and   
           Cathy Chancellor and   
                   Min Chen and   
               Claude Cirba and   
                    Vijay Reddy   Recovery modeling of negative bias
                                  temperature instability (NBTI) for
                                  SPICE-compatible circuit aging
                                  simulators . . . . . . . . . . . . . . . 2:1--2:??
              Senthil Arasu and   
            Mehrdad Nourani and   
                Vijay Reddy and   
        John M. Carulli Jr. and   
              Gautam Kapila and   
                       Min Chen   Reliability improvement of logic and
                                  clock paths in power-efficient designs   3:1--3:??
                    Jin Sun and   
              Roman Lysecky and   
            Karthik Shankar and   
               Avinash Kodi and   
                Ahmed Louri and   
                   Janet Roveda   Workload assignment considering NBTI
                                  degradation in multicore systems . . . . 4:1--4:??
              Djaafar Chabi and   
            Damien Querlioz and   
              Weisheng Zhao and   
          Jacques-Olivier Klein   Robust learning approach for
                                  neuro-inspired nanoscale crossbar
                                  architecture . . . . . . . . . . . . . . 5:1--5:??
             Stefano Frache and   
       Mariagrazia Graziano and   
               Maurizio Zamboni   Nanoarray architectures multilevel
                                  simulation . . . . . . . . . . . . . . . 6:1--6:??
           Alberto Avritzer and   
                   Tadashi Dohi   Introduction to special issue on WoSAR
                                  2011 . . . . . . . . . . . . . . . . . . 7:1--7:??
          Domenico Cotroneo and   
            Roberto Natella and   
       Roberto Pietrantuono and   
                  Stefano Russo   A survey of software aging and
                                  rejuvenation studies . . . . . . . . . . 8:1--8:??
                  Jing Zhao and   
                Yuliang Jin and   
          Kishor S. Trivedi and   
        Rivalino Matias Jr. and   
                    Yanbin Wang   Software rejuvenation scheduling using
                                  accelerated life testing . . . . . . . . 9:1--9:??
              Fumio Machida and   
           Victor F. Nicola and   
              Kishor S. Trivedi   Job completion time on a virtualized
                                  server with software rejuvenation  . . . 10:1--10:??
                Jean Araujo and   
               Rubens Matos and   
                Vandi Alves and   
               Paulo Maciel and   
         F. Vieira de Souza and   
        Rivalino Matias Jr. and   
              Kishor S. Trivedi   Software aging in the Eucalyptus cloud
                                  computing infrastructure:
                                  Characterization and rejuvenation  . . . 11:1--11:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 10, Number 2, February, 2014

                Jifeng Chen and   
                  Shuo Wang and   
           Mohammad Tehranipoor   Critical-reliability path identification
                                  and delay analysis . . . . . . . . . . . 12:1--12:??
             Michael Gladshtein   Delay-based processing-in-wire for
                                  design of QCA serial decimal arithmetic
                                  units  . . . . . . . . . . . . . . . . . 13:1--13:??
              Chia-Chun Lin and   
                   Niraj K. Jha   RMDDS: Reed--Muller decision diagram
                                  synthesis of reversible logic circuits   14:1--14:??
                Weichen Liu and   
                  Xuan Wang and   
                   Jiang Xu and   
                  Wei Zhang and   
                  Yaoyao Ye and   
                 Xiaowen Wu and   
              Mahdi Nikdast and   
                    Zhehui Wang   On-chip sensor networks for soft-error
                                  tolerant real-time multiprocessor
                                  systems-on-chip  . . . . . . . . . . . . 15:1--15:??
                Jaeyoon Kim and   
                  Sandip Tiwari   Inexact computing using probabilistic
                                  circuits: Ultra low-power digital
                                  processing . . . . . . . . . . . . . . . 16:1--16:??
                Luke Pierce and   
               Spyros Tragoudas   Nanopipelined threshold network
                                  synthesis  . . . . . . . . . . . . . . . 17:1--17:??
                 Dong Xiang and   
                      Kele Shen   A thermal-driven test application scheme
                                  for pre-bond and post-bond scan testing
                                  of three-dimensional ICs . . . . . . . . 18:1--18:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 10, Number 3, April, 2014

                Mehdi Kamal and   
           Ali Afzali-Kusha and   
               Saeed Safari and   
                 Massoud Pedram   Impact of Process Variations on Speedup
                                  and Maximum Achievable Frequency of
                                  Extensible Processors  . . . . . . . . . 19:1--19:??
                Haera Chung and   
          Christof Teuscher and   
                   Partha Pande   Design and Evaluation of
                                  Technology-Agnostic Heterogeneous
                                  Networks-on-Chip . . . . . . . . . . . . 20:1--20:??
    Ashok Kumar Palaniswamy and   
               Spyros Tragoudas   Improved Threshold Logic Synthesis Using
                                  Implicant-Implicit Algorithms  . . . . . 21:1--21:??
                Fu-Wei Chen and   
                 Tingting Hwang   Clock-Tree Synthesis with Methodology of
                                  Reuse in $3$D-IC . . . . . . . . . . . . 22:1--22:??
                 Wulong Liu and   
                    Yu Wang and   
                  Yuchun Ma and   
                   Yuan Xie and   
                  Huazhong Yang   On-Chip Hybrid Power Supply System for
                                  Wireless Sensor Nodes  . . . . . . . . . 23:1--23:??
             Daniel Grissom and   
         Christopher Curtis and   
                   Philip Brisk   Interpreting Assays with Control Flow on
                                  Digital Microfluidic Biochips  . . . . . 24:1--24:??
                    Bo Yuan and   
                         Bin Li   A Fast Extraction Algorithm for
                                  Defect-Free Subcrossbar in
                                  Nanoelectronic Crossbar  . . . . . . . . 25:1--25:??
     Sourindra M. Chaudhuri and   
                   Niraj K. Jha   $3$D vs. $2$D Device Simulation of
                                  FinFET Logic Gates under PVT Variations  26:1--26:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 11, Number 1, September, 2014

                Jiun-Li Lin and   
                 Po-Hsun Wu and   
                    Tsung-Yi Ho   Placement optimization of flexible TFT
                                  circuits with mechanical strain and
                                  temperature consideration  . . . . . . . 1:1--1:??
                  Sudip Roy and   
    Bhargab B. Bhattacharya and   
         Sarmishtha Ghoshal and   
         Krishnendu Chakrabarty   Theory and analysis of generalized
                                  mixing and dilution of biochemical
                                  fluids using digital microfluidic
                                  biochips . . . . . . . . . . . . . . . . 2:1--2:??
               Xianmin Chen and   
                   Niraj K. Jha   Ultra-low-leakage chip multiprocessor
                                  design with hybrid FinFET logic styles   3:1--3:??
               Ing-Chao Lin and   
              Shun-Ming Syu and   
                    Tsung-Yi Ho   NBTI tolerance and leakage reduction
                                  using gate sizing  . . . . . . . . . . . 4:1--4:??
                   Jing Xie and   
                    Yang Du and   
                       Yuan Xie   Testable cross-power domain interface
                                  (CPDI) circuit design in monolithic $3$D
                                  technology . . . . . . . . . . . . . . . 5:1--5:??
               Renu Kumawat and   
              Vineet Sahula and   
                  Manoj S. Gaur   Probabilistic modeling and analysis of
                                  molecular memory . . . . . . . . . . . . 6:1--6:??
              Chia-Chun Lin and   
          Amlan Chakrabarti and   
                   Niraj K. Jha   QLib: Quantum module library . . . . . . 7:1--7:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 11, Number 2, November, 2014

               Robert Wille and   
             Rolf Drechsler and   
               Mehdi B. Tahoori   Introduction to the Special Issue on
                                  Reversible Computation . . . . . . . . . 8:1--8:??
              Alexis De Vos and   
          Stijn De Baerdemacker   Matrix Calculus for Classical and
                                  Quantum Circuits . . . . . . . . . . . . 9:1--9:??
      Ismo K. Hänninen and   
              Craig S. Lent and   
              Gregory L. Snider   Quantifying Irreversible Information
                                  Loss in Digital Circuits . . . . . . . . 10:1--10:??
              Alexis De Vos and   
   Stéphane Burignat and   
          Robert Glück and   
Torben Ægidius Mogensen and   
        Holger Bock Axelsen and   
   Michael Kirkedal Thomsen and   
              Eva Rotenberg and   
                Tetsuo Yokoyama   Designing Garbage-Free Reversible
                                  Implementations of the Integer Cosine
                                  Transform  . . . . . . . . . . . . . . . 11:1--11:??
  Torben Ægidius Mogensen   Garbage-Free Reversible Multipliers for
                                  Arbitrary Constants  . . . . . . . . . . 12:1--12:??
           Trung Duc Nguyen and   
               Rodney Van Meter   A Resource-Efficient Design for a
                                  Reversible Floating Point Adder in
                                  Quantum Computing  . . . . . . . . . . . 13:1--13:??
            Alireza Shafaei and   
               Mehdi Saeedi and   
                 Massoud Pedram   Cofactor Sharing for Reversible Logic
                                  Synthesis  . . . . . . . . . . . . . . . 14:1--14:??
             Kamalika Datta and   
               Gaurav Rathi and   
          Indranil Sengupta and   
                Hafizur Rahaman   An Improved Reversible Circuit Synthesis
                                  Approach using Clustering of ESOP Cubes  15:1--15:??
      Umamaheswara Rao Tida and   
                 Cheng Zhuo and   
                       Yiyu Shi   Novel Through-Silicon-Via Inductor-Based
                                  On-Chip DC--DC Converter Designs in $3$D
                                  ICs  . . . . . . . . . . . . . . . . . . 16:1--16:??
               Jacob Murray and   
                   Ryan Kim and   
                Paul Wettin and   
        Partha Pratim Pande and   
                Behrooz Shirazi   Performance Evaluation of
                                  Congestion-Aware Routing with DVFS on a
                                  Millimeter-Wave Small-World Wireless NoC 17:1--17:??
   Pragyan (Sheela) Mohanty and   
               Spyros Tragoudas   Scalable Offline Searches in DNA
                                  Sequences  . . . . . . . . . . . . . . . 18:1--18:??
     Sourindra M. Chaudhuri and   
             Prateek Mishra and   
                   Niraj K. Jha   Accurate Leakage/Delay Estimation for
                                  FinFET Standard Cells under PVT
                                  Variations using the Response Surface
                                  Methodology  . . . . . . . . . . . . . . 19:1--19:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 11, Number 3, December, 2014

             Chris J. Myers and   
              Herbert Sauro and   
                     Anil Wipat   Introduction to the Special Issue on
                                  Computational Synthetic Biology  . . . . 20:1--20:??
                  Tara L. Deans   Parallel Networks: Synthetic Biology and
                                  Artificial Intelligence  . . . . . . . . 21:1--21:??
             Goksel Misirli and   
          Jennifer Hallinan and   
                     Anil Wipat   Composable Modular Models for Synthetic
                                  Biology  . . . . . . . . . . . . . . . . 22:1--22:??
              Curtis Madsen and   
                 Zhen Zhang and   
           Nicholas Roehner and   
             Chris Winstead and   
                    Chris Myers   Stochastic Model Checking of Genetic
                                  Circuits . . . . . . . . . . . . . . . . 23:1--23:??
          Harold Fellermann and   
                Maik Hadorn and   
    Rudolf M. Füchslin and   
              Natalio Krasnogor   Formalizing Modularization and Data
                                  Hiding in Synthetic Biology  . . . . . . 24:1--24:??
           Ernst Oberortner and   
             Swapnil Bhatia and   
              Erik Lindgren and   
               Douglas Densmore   A Rule-Based Design Specification
                                  Language for Synthetic Biology . . . . . 25:1--25:??
               Haiyao Huang and   
               Douglas Densmore   Fluigi: Microfluidic Device Synthesis
                                  for Synthetic Biology  . . . . . . . . . 26:1--26:??
        Fatima Zohra Hadjam and   
                 Claudio Moraga   RIMEP2: Evolutionary Design of
                                  Reversible Digital Circuits  . . . . . . 27:1--27:??
        Mahboobeh Houshmand and   
       Morteza Saheb Zamani and   
              Mehdi Sedighi and   
                 Mona Arabzadeh   Decomposition of Diagonal Hermitian
                                  Quantum Gates Using Multiple-Controlled
                                  Pauli Z Gates  . . . . . . . . . . . . . 28:1--28:??
                Zhiqiang Li and   
                 Hanwu Chen and   
                Xiaoyu Song and   
                Marek Perkowski   A Synthesis Algorithm for $4$-Bit
                                  Reversible Logic Circuits with Minimum
                                  Quantum Cost . . . . . . . . . . . . . . 29:1--29:??
                Bibhash Sen and   
              Manojit Dutta and   
                 Samik Some and   
               Biplab K. Sikdar   Realizing Reversible Computing in QCA
                                  Framework Resulting in Efficient Design
                                  of Testable ALU  . . . . . . . . . . . . 30:1--30:??
          Md. Mazder Rahman and   
           Gerhard W. Dueck and   
               Joseph D. Horton   An Algorithm for Quantum Template
                                  Matching . . . . . . . . . . . . . . . . 31:1--31:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 11, Number 4, April, 2015

            Dan Hammerstrom and   
        Vijaykrishnan Narayanan   Introduction to Special Issue on
                                  Neuromorphic Computing . . . . . . . . . 32:1--32:??
          Laurent Rodriguez and   
         Beno\^\it Miramond and   
               Bertrand Granado   Toward a Sparse Self-Organizing Map for
                                  Neuromorphic Architectures . . . . . . . 33:1--33:??
              Djaafar Chabi and   
              Weisheng Zhao and   
            Damien Querlioz and   
          Jacques-Olivier Klein   On-Chip Universal Supervised Learning
                                  Methods for Neuro-Inspired Block of
                                  Memristive Nanodevices . . . . . . . . . 34:1--34:??
            Philippe Coussy and   
             Cyrille Chavet and   
         Hugues Nono Wouafo and   
           Laura Conde-Canencia   Fully Binary Neural Network Model and
                                  Optimized Hardware Architectures for
                                  Associative Memories . . . . . . . . . . 35:1--35:??
        Jeffrey L. Krichmar and   
            Philippe Coussy and   
                     Nikil Dutt   Large-Scale Spiking Neural Networks
                                  using Neuromorphic Hardware Compatible
                                  Models . . . . . . . . . . . . . . . . . 36:1--36:??
Beno\^\it Chappet De Vangel and   
       Cesar Torres-huitzil and   
                  Bernard Girau   Randomly Spiking Dynamic Neural Fields   37:1--37:??
                Yongtae Kim and   
                 Yong Zhang and   
                        Peng Li   A Reconfigurable Digital Neuromorphic
                                  Processor with Memristive Synaptic
                                  Crossbar for Cognitive Computing . . . . 38:1--38:??
         Masoud Daneshtalab and   
           Farhad Mehdipour and   
                   Zhiyi Yu and   
                 Hannu Tenhunen   Special Issue on Emerging Many-Core
                                  Systems for Exascale Computing . . . . . 39:1--39:??
        Syed M. A. H. Jafri and   
                 Ozan Ozbag and   
             Nasim Farahini and   
                 Kolin Paul and   
               Ahmed Hemani and   
               Juha Plosila and   
                 Hannu Tenhunen   Architecture and Implementation of
                                  Dynamic Parallelism, Voltage and
                                  Frequency Scaling (PVFS) on CGRAs  . . . 40:1--40:??
            Oluleye Olorode and   
                Mehrdad Nourani   Improving Performance in Sub-Block
                                  Caches with Optimized Replacement
                                  Policies . . . . . . . . . . . . . . . . 41:1--41:??
                 Zhongqi Li and   
           Nilanjan Goswami and   
                         Tao Li   iConn: a Communication Infrastructure
                                  for Heterogeneous Computing
                                  Architectures  . . . . . . . . . . . . . 42:1--42:??
         Misagh Khayambashi and   
          Pooria M. Yaghini and   
              Ashkan Eghbal and   
              Nader Bagherzadeh   Analytical Reliability Analysis of $3$D
                                  NoC under TSV Failure  . . . . . . . . . 43:1--43:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 12, Number 1, July, 2015

                   Jun Pang and   
          Christopher Dwyer and   
                Alvin R. Lebeck   mNoC: Large Nanophotonic Network-on-Chip
                                  Crossbars with Molecular Scale Devices   1:1--1:??
           Nahid M. Hossain and   
             Masud H. Chowdhury   Multilayer Graphene Nanoribbon and
                                  Carbon Nanotube Based Floating Gate
                                  Transistor for Nonvolatile Flash Memory  2:1--2:??
           Amirali Ghofrani and   
Miguel-Angel Lastras-Montaño and   
             Siddharth Gaba and   
             Melika Payvand and   
                     Wei Lu and   
           Luke Theogarajan and   
               Kwang-Ting Cheng   A Low-Power Variation-Aware Adaptive
                                  Write Scheme for Access-Transistor-Free
                                  Memristive Memory  . . . . . . . . . . . 3:1--3:??
     Rangharajan Venkatesan and   
             Mrigank Sharad and   
                Kaushik Roy and   
              Anand Raghunathan   Energy-Efficient All-Spin Cache
                                  Hierarchy Using Shift-Based Writes and
                                  Multilevel Storage . . . . . . . . . . . 4:1--4:??
                Kyu Ho Park and   
               Woomin Hwang and   
              Hyunchul Seok and   
                Chulmin Kim and   
              Dong-jae Shin and   
               Dong Jin Kim and   
              Min Kyu Maeng and   
                  Seong Min Kim   MN-MATE: Elastic Resource Management of
                                  Manycores and a Hybrid Memory Hierarchy
                                  for a Cloud Node . . . . . . . . . . . . 5:1--5:??
                   Jue Wang and   
                       Yuan Xie   A Write-Aware STTRAM-Based Register File
                                  Architecture for GPGPU . . . . . . . . . 6:1--6:??
                Aldo Romani and   
             Matteo Filippi and   
               Michele Dini and   
                 Marco Tartagni   A Sub-$ \mu $ A Stand-By Current
                                  Synchronous Electric Charge Extractor
                                  for Piezoelectric Energy Harvesting  . . 7:1--7:??
       Hrishikesh Jayakumar and   
                 Arnab Raha and   
                Woo Suk Lee and   
              Vijay Raghunathan   QuickRecall: a HW/SW Approach for
                                  Computing across Power Cycles in
                                  Transiently Powered Computers  . . . . . 8:1--8:??
            Chia-Hung Chien and   
           Rodney Van Meter and   
                     Sy-Yen Kuo   Fault-Tolerant Operations for Universal
                                  Blind Quantum Computation  . . . . . . . 9:1--9:??
                Ching-Hwa Cheng   SCKVdd: a Scalable Clock-Controlled
                                  Self-Stabilized Voltage Technique for
                                  Low Power CMOS Digital Circuits  . . . . 10:1--10:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 12, Number 2, August, 2015

          Aida Todri-Sanial and   
                Sanjukta Bhanja   Guest Editorial: Special Issue on
                                  Advances in Design of Ultra-Low Power
                                  Circuits and Systems in Emerging
                                  Technologies . . . . . . . . . . . . . . 11:1--11:??
 Pierre-Emmanuel Gaillardon and   
               Edith Beigne and   
             Suzanne Lesecq and   
            Giovanni De Micheli   A Survey on Low-Power Techniques with
                                  Emerging Technologies: From Devices to
                                  Systems  . . . . . . . . . . . . . . . . 12:1--12:??
                  Can Sitik and   
                Emre Salman and   
              Leo Filippini and   
              Sung Jun Yoon and   
                   Baris Taskin   FinFET-Based Low-Swing Clocking  . . . . 13:1--13:??
            Tiansheng Zhang and   
                   Jie Meng and   
                 Ayse K. Coskun   Dynamic Cache Pooling in $3$D Multicore
                                  Processors . . . . . . . . . . . . . . . 14:1--14:??
          Santosh Khasanvis and   
          K. M. Masum Habib and   
          Mostafizur Rahman and   
                 Roger Lake and   
            Csaba Andras Moritz   Low-Power Heterogeneous Graphene
                                  Nanoribbon-CMOS Multistate Volatile
                                  Memory Circuit . . . . . . . . . . . . . 15:1--15:??
                  Wang Kang and   
                  Yue Zhang and   
               Zhaohao Wang and   
      Jacques-Olivier Klein and   
            Claude Chappert and   
   Dafiné Ravelosona and   
                 Gefei Wang and   
             Youguang Zhang and   
                  Weisheng Zhao   Spintronics: Emerging Ultra-Low-Power
                                  Circuits and Systems beyond MOS
                                  Technology . . . . . . . . . . . . . . . 16:1--16:??
     Mostafa Rahimi Azghadi and   
               Saber Moradi and   
         Daniel B. Fasnacht and   
         Mehmet Sirin Ozdas and   
               Giacomo Indiveri   Programmable Spike-Timing-Dependent
                                  Plasticity Learning Circuits in
                                  Neuromorphic VLSI Architectures  . . . . 17:1--17:??
       Mariagrazia Graziano and   
           Azzurra Pulimeno and   
                 Ruiyu Wang and   
                  Xiang Wei and   
           Massimo Ruo Roch and   
             Gianluca Piccinini   Process Variability and Electrostatic
                                  Analysis of Molecular QCA  . . . . . . . 18:1--18:??
              Trong Nhan Le and   
           Alain Pegatoquet and   
             Olivier Berder and   
           Olivier Sentieys and   
                   Arnaud Carer   Energy-Neutral Design Framework for
                                  Supercapacitor-Based Autonomous Wireless
                                  Sensor Networks  . . . . . . . . . . . . 19:1--19:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 12, Number 3, September, 2015

                   Yiyu Shi and   
                   Takashi Sato   Introduction to: Special Issue on
                                  Cross-Layer System Design  . . . . . . . 20:1--20:??
                Vivek K. De and   
            Andrew B. Kahng and   
               Tanay Karnik and   
                    Bao Liu and   
               Milad Maleki and   
                        Lu Wang   Application-Specific Cross-Layer
                                  Optimization Based on Predictive
                                  Variable-Latency VLSI Design . . . . . . 21:1--21:??
              Milan Patnaik and   
       Chidhambaranathan R. and   
                Chirag Garg and   
                  Arnab Roy and   
           V. R. Devanathan and   
       Shankar Balachandran and   
                    V. Kamakoti   ProWATCh: a Proactive Cross-Layer
                                  Workload-Aware Temperature Management
                                  Framework for Low-Power Chip
                                  Multi-Processors . . . . . . . . . . . . 22:1--22:??
              Chenyuan Zhao and   
          Bryant T. Wysocki and   
                 Yifang Liu and   
             Clare D. Thiem and   
         Nathan R. McDonald and   
                        Yang Yi   Spike-Time-Dependent Encoding for
                                  Neuromorphic Processors  . . . . . . . . 23:1--23:??
               Martin Barke and   
               Ulf Schlichtmann   A Cross-Layer Approach to Measure the
                                  Robustness of Integrated Circuits  . . . 24:1--24:??
                 Cheng Zhuo and   
                  Houle Gan and   
               Wei-Kai Shih and   
            Alaeddin A. Aydiner   A Cross-Layer Approach for Early-Stage
                                  Power Grid Design and Optimization . . . 25:1--25:??
                  Jinho Lee and   
               Kyungsu Kang and   
                   Kiyoung Choi   REDELF: an Energy-Efficient
                                  Deadlock-Free Routing for $3$D NoCs with
                                  Partial Vertical Connections . . . . . . 26:1--26:??
                Davide Zoni and   
             William Fornaciari   Modeling DVFS and Power-Gating Actuators
                                  for Cycle-Accurate NoC-Based Simulators  27:1--27:??
               Xianmin Chen and   
                   Niraj K. Jha   gem5-PVT: a Framework for FinFET System
                                  Simulation under PVT Variations  . . . . 28:1--28:??
           Tayebeh Bahreini and   
            Naser Mohammadzadeh   An MINLP Model for Scheduling and
                                  Placement of Quantum Circuits with a
                                  Heuristic Solution Approach  . . . . . . 29:1--29:??
          Mostafizur Rahman and   
          Santosh Khasanvis and   
            Csaba Andras Moritz   Nanowire Volatile RAM as an Alternative
                                  to SRAM  . . . . . . . . . . . . . . . . 30:1--30:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 12, Number 4, July, 2016

       Hoda Aghaei Khouzani and   
                   Yuan Xue and   
                   Chengmo Yang   Fully Exploiting PCM Write Capacity
                                  Within Near Zero Cost Through
                                  Segment-Based Page Allocation  . . . . . 31:1--31:??
           Christophe Layer and   
             Laurent Becker and   
                Kotb Jabeur and   
           Sylvain Claireux and   
              Bernard Dieny and   
           Guillaume Prenat and   
         Gregory Di Pendina and   
              Stephane Gros and   
               Pierre Paoli and   
          Virgile Javerliac and   
    Fabrice Bernard-Granger and   
                  Loic Decloedt   Reducing System Power Consumption Using
                                  Check-Pointing on Nonvolatile Embedded
                                  Magnetic Random Access Memories  . . . . 32:1--32:??
                Chengwen Wu and   
             Guangyan Zhang and   
                       Keqin Li   Rethinking Computer Architectures and
                                  Software Systems for Phase-Change Memory 33:1--33:40
                Arighna Deb and   
              Debesh K. Das and   
            Hafizur Rahaman and   
               Robert Wille and   
             Rolf Drechsler and   
        Bhargab B. Bhattacharya   Reversible Synthesis of Symmetric
                                  Functions with a Simple Regular
                                  Structure and Easy Testability . . . . . 34:1--34:??
                  Qian Wang and   
                Yongtae Kim and   
                        Peng Li   Neuromorphic Processors with Memristive
                                  Synapses: Synaptic Interface and
                                  Architectural Exploration  . . . . . . . 35:1--35:??
              Kalyan Biswas and   
            Angsuman Sarkar and   
           Chandan Kumar Sarkar   Impact of Fin Width Scaling on RF/Analog
                                  Performance of Junctionless
                                  Accumulation-Mode Bulk FinFET  . . . . . 36:1--36:??
               Yi-Hang Chen and   
               Jian-Yu Chen and   
                Juinn-Dar Huang   Area Minimization Synthesis for
                                  Reconfigurable Single-Electron
                                  Transistor Arrays with Fabrication
                                  Constraints  . . . . . . . . . . . . . . 37:1--37:??
              Moon Seok Kim and   
       William Cane-Wissing and   
                 Xueqing Li and   
               Jack Sampson and   
                Suman Datta and   
         Sumeet Kumar Gupta and   
        Vijaykrishnan Narayanan   Comparative Area and Parasitics Analysis
                                  in FinFET and Heterojunction Vertical
                                  TFET Standard Cells  . . . . . . . . . . 38:1--38:??
             Muhammad Ahsan and   
           Rodney Van Meter and   
                   Jungsang Kim   Designing a Million-Qubit Quantum
                                  Computer Using a Resource Performance
                                  Simulator  . . . . . . . . . . . . . . . 39:1--39:??
             Mona Arabzadeh and   
        Mahboobeh Houshmand and   
              Mehdi Sedighi and   
           Morteza Saheb Zamani   Quantum-Logic Synthesis of Hermitian
                                  Gates  . . . . . . . . . . . . . . . . . 40:1--40:??
             Mathias Soeken and   
               Robert Wille and   
            Oliver Keszocze and   
          D. Michael Miller and   
                 Rolf Drechsler   Embedding of Large Boolean Functions for
                                  Reversible Logic . . . . . . . . . . . . 41:1--41:??
               Aoxiang Tang and   
                    Xun Gao and   
              Lung-Yen Chen and   
                   Niraj K. Jha   Delay/Power Modeling and Optimization of
                                  FinFET Circuit Modules under PVT
                                  Variations: Observing the Trends between
                                  the 22nm and 14nm Technology Nodes . . . 42:1--42:??
     Sourindra M. Chaudhuri and   
                   Niraj K. Jha   Ultra-Low-Leakage and High-Performance
                                  Logic Circuit Design Using
                                  Multiparameter Asymmetric FinFETs  . . . 43:1--43:??
         Anja Von Beuningen and   
                Luca Ramini and   
            Davide Bertozzi and   
               Ulf Schlichtmann   PROTON+: a Placement and Routing Tool
                                  for $3$D Optical Networks-on-Chip with a
                                  Single Optical Layer . . . . . . . . . . 44:1--44:??
             Abbas Dehghani and   
                 Kamal Jamshidi   A Novel Approach to Optimize
                                  Fault-Tolerant Hybrid Wireless
                                  Network-on-Chip Architectures  . . . . . 45:1--45:??
                  Sparsh Mittal   A Survey of Architectural Techniques for
                                  Near-Threshold Computing . . . . . . . . 46:1--46:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 13, Number 1, December, 2016

            Ozgur Sinanoglu and   
                   Ramesh Karri   Guest Editorial Special Issue on Secure
                                  and Trustworthy Computing  . . . . . . . 1:1--1:??
                 Jayita Das and   
                Kevin Scott and   
                Sanjukta Bhanja   MRAM PUF: Using Geometric and Resistive
                                  Variations in MRAM Cells . . . . . . . . 2:1--2:??
                      Yu Bi and   
               Kaveh Shamsi and   
           Jiann-Shiun Yuan and   
 Pierre-Emmanuel Gaillardon and   
        Giovanni De Micheli and   
                Xunzhao Yin and   
               X. Sharon Hu and   
            Michael Niemier and   
                       Yier Jin   Emerging Technology-Based Design of
                                  Primitives for Hardware Security . . . . 3:1--3:??
            Anirudh Iyengar and   
              Swaroop Ghosh and   
            Kenneth Ramclam and   
               Jae-Won Jang and   
                  Cheng-Wei Lin   Spintronic PUFs for Security, Trust, and
                                  Authentication . . . . . . . . . . . . . 4:1--4:??
       Elena Ioana Vatajelu and   
          Giorgio Di Natale and   
          Mario Barbareschi and   
              Lionel Torres and   
               Marco Indaco and   
                 Paolo Prinetto   STT--MRAM-Based PUF Architecture
                                  Exploiting Magnetic Tunnel Junction
                                  Fabrication-Induced Variability  . . . . 5:1--5:??
           Shahed E. Quadir and   
                Junlin Chen and   
              Domenic Forte and   
         Navid Asadizanjani and   
       Sina Shahbazmohamadi and   
                   Lei Wang and   
                John Chandy and   
               Mark Tehranipoor   A Survey on Chip to System Reverse
                                  Engineering  . . . . . . . . . . . . . . 6:1--6:??
          Stephan De Castro and   
          Jean-Max Dutertre and   
             Bruno Rouzeyre and   
          Giorgio Di Natale and   
             Marie-Lise Flottes   Frontside Versus Backside Laser
                                  Injection: a Comparative Study . . . . . 7:1--7:??
        Alessandro Barenghi and   
           Guido M. Bertoni and   
           Luca Breveglieri and   
             Gerardo Pelosi and   
         Stefano Sanfilippo and   
                Ruggero Susella   A Fault-Based Secret Key Retrieval
                                  Method for ECDSA: Analysis and
                                  Countermeasure . . . . . . . . . . . . . 8:1--8:??
                Yingjie Lao and   
              Qianying Tang and   
               Chris H. Kim and   
                Keshab K. Parhi   Beat Frequency Detector-Based High-Speed
                                  True Random Number Generators:
                                  Statistical Modeling and Analysis  . . . 9:1--9:??
              Amey Kulkarni and   
               Youngok Pino and   
             Matthew French and   
               Tinoosh Mohsenin   Real-Time Anomaly Detection Framework
                                  for Many-Core Router through
                                  Machine-Learning Techniques  . . . . . . 10:1--10:??
                Arighna Deb and   
               Robert Wille and   
       Oliver Keszöcze and   
            Stefan Hillmich and   
                 Rolf Drechsler   Gates vs. Splitters: Contradictory
                                  Optimization Objectives in the Synthesis
                                  of Optical Circuits  . . . . . . . . . . 11:1--11:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 13, Number 2, March, 2017

          Aida Todri-Sanial and   
          Saraju P. Mohanty and   
              Mariane Comte and   
                Marc Belleville   Guest Editorial: Special Issue on
                                  Nanoelectronic Circuit and System Design
                                  Methods for the Mobile Computing Era . . 12:1--12:??
         Anderson L. Sartor and   
         Arthur F. Lorenzon and   
                Luigi Carro and   
       Fernanda Kastensmidt and   
               Stephan Wong and   
             Antonio C. S. Beck   Exploiting Idle Hardware to Provide Low
                                  Overhead Fault Tolerance for VLIW
                                  Processors . . . . . . . . . . . . . . . 13:1--13:??
                   Yan Fang and   
           Victor V. Yashin and   
        Brandon B. Jennings and   
        Donald M. Chiarulli and   
              Steven P. Levitan   A Simplified Phase Model for Simulation
                                  of Oscillator-Based Computing Systems    14:1--14:??
               Ajay Singhvi and   
         Matheus T. Moreira and   
             Ramy N. Tadros and   
         Ney L. V. Calazans and   
                Peter A. Beerel   A Fine-Grain, Uniform, Energy-Efficient
                                  Delay Element for $2$-Phase Bundled-Data
                                  Circuits . . . . . . . . . . . . . . . . 15:1--15:??
Hassan Ghasemzadeh Mohammadi and   
 Pierre-Emmanuel Gaillardon and   
                 Jian Zhang and   
        Giovanni De Micheli and   
            Ernesto Sanchez and   
            Matteo Sonza Reorda   A Fault-Tolerant Ripple-Carry Adder with
                                  Controllable-Polarity Transistors  . . . 16:1--16:??
             Sophiane Senni and   
              Lionel Torres and   
          Gilles Sassatelli and   
              Abdoulaye Gamatie   Non-Volatile Processor Based on MRAM for
                                  Ultra-Low-Power IoT Devices  . . . . . . 17:1--17:??
            Joydeep Rakshit and   
            Kartik Mohanram and   
                 Runlai Wan and   
                Kai Tak Lam and   
                       Jing Guo   Monolayer Transistor SRAMs: Toward
                                  Low-Power, Denser Memory Systems . . . . 18:1--18:??
                  Xuan Wang and   
                   Jiang Xu and   
                   Zhe Wang and   
                  Haoran Li and   
                Zhehui Wang and   
                  Peng Yang and   
           Luan H. K. Duong and   
         Rafael K. V. Maeda and   
                    Zhifei Wang   Alleviate Chip Pin Constraint for
                                  Multicore Processor by On/Off-Chip Power
                                  Delivery System Codesign . . . . . . . . 19:1--19:??
               Zoha Pajouhi and   
               Xuanyao Fong and   
          Anand Raghunathan and   
                    Kaushik Roy   Yield, Area, and Energy Optimization in
                                  STT--MRAMs Using Failure-Aware ECC . . . 20:1--20:??
        Meghna G. Mankalale and   
           Sachin S. Sapatnekar   Optimized Standard Cells for All-Spin
                                  Logic  . . . . . . . . . . . . . . . . . 21:1--21:??
                  Wei Jiang and   
                  Liang Wen and   
                   Ke Jiang and   
                  Xia Zhang and   
                  Xiong Pan and   
                     Keran Zhou   System-Level Design to Detect Fault
                                  Injection Attacks on Embedded Real-Time
                                  Applications . . . . . . . . . . . . . . 22:1--22:??
               A. Arun Goud and   
     Rangharajan Venkatesan and   
          Anand Raghunathan and   
                    Kaushik Roy   Asymmetric Underlapped FinFETs for Near-
                                  and Super-Threshold Logic at Sub-10nm
                                  Technology Nodes . . . . . . . . . . . . 23:1--23:??
José L. Abellán and   
                  Chao Chen and   
                     Ajay Joshi   Electro-Photonic NoC Designs for
                                  Kilocore Systems . . . . . . . . . . . . 24:1--24:??
                   Yao Wang and   
                 Liang Rong and   
                 Haibo Wang and   
                   Guangjun Wen   One-Step Sneak-Path Free Read Scheme for
                                  Resistive Crossbar Memory  . . . . . . . 25:1--25:??
             Abdullah Guler and   
                   Niraj K. Jha   Ultra-low-leakage, Robust FinFET SRAM
                                  Design Using Multiparameter Asymmetric
                                  FinFETs  . . . . . . . . . . . . . . . . 26:1--26:??
                 Hang Zhang and   
                 Xuhao Chen and   
                  Nong Xiao and   
                   Lei Wang and   
                   Fang Liu and   
                   Wei Chen and   
                  Zhiguang Chen   Shielding STT--RAM Based Register Files
                                  on GPUs against Read Disturbance . . . . 27:1--27:??
             Arnab Kumar Biswas   Source Authentication Techniques for
                                  Network-on-Chip Router Configuration
                                  Packets  . . . . . . . . . . . . . . . . 28:1--28:??
                  Sparsh Mittal   A Survey of Techniques for Architecting
                                  Processor Components Using Domain-Wall
                                  Memory . . . . . . . . . . . . . . . . . 29:1--29:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 13, Number 3, May, 2017

                     Yu Cao and   
                     Xin Li and   
                 Taemin Kim and   
                    Suyog Gupta   Guest Editors' Introduction: Hardware
                                  and Algorithms for On-Chip Learning  . . 30:1--30:??
                  Adam Page and   
                 Ali Jafari and   
                 Colin Shea and   
               Tinoosh Mohsenin   SPARCNet: a Hardware Accelerator for
                                  Efficient Deployment of Sparse
                                  Convolutional Networks . . . . . . . . . 31:1--31:??
                Sajid Anwar and   
              Kyuyeon Hwang and   
                   Wonyong Sung   Structured Pruning of Deep Convolutional
                                  Neural Networks  . . . . . . . . . . . . 32:1--32:??
        Priyadarshini Panda and   
          Abhronil Sengupta and   
                    Kaushik Roy   Energy-Efficient and Improved Image
                                  Recognition with Conditional Deep
                                  Learning . . . . . . . . . . . . . . . . 33:1--33:??
               Robert Karam and   
               Somnath Paul and   
                Ruchir Puri and   
                  Swarup Bhunia   Memory-Centric Reconfigurable
                                  Accelerator for Classification and
                                  Machine Learning Applications  . . . . . 34:1--34:??
                    Bo Yuan and   
                Keshab K. Parhi   VLSI Architectures for the Restricted
                                  Boltzmann Machine  . . . . . . . . . . . 35:1--35:??
                  Leibin Ni and   
               Hantao Huang and   
                Zichuan Liu and   
             Rajiv V. Joshi and   
                         Hao Yu   Distributed In-Memory Computing on
                                  Binary RRAM Crossbar . . . . . . . . . . 36:1--36:??
                Cory Merkel and   
      Dhireesha Kudithipudi and   
                 Manan Suri and   
                 Bryant Wysocki   Stochastic CBRAM-Based Neuromorphic Time
                                  Series Prediction System . . . . . . . . 37:1--37:??
         Rasit O. Topaloglu and   
                   Naveen Verma   Editorial for JETC Special Issue on
                                  Alternative Computing Systems  . . . . . 38:1--38:??
             Keith A. Britt and   
               Travis S. Humble   High-Performance Computing with Quantum
                                  Processing Units . . . . . . . . . . . . 39:1--39:??
              Su-Kyung Yoon and   
             Young-Sun Youn and   
                Kihyun Park and   
                   Shin-Dug Kim   Mobile Unified Memory-Storage Structure
                                  Based on Hybrid Non-Volatile Memories    40:1--40:??
            Krishnendu Guha and   
               Debasri Saha and   
              Amlan Chakrabarti   Real-Time SoC Security against Passive
                                  Threats Using Crypsis Behavior of Geckos 41:1--41:??
                    Yin Liu and   
                Keshab K. Parhi   Computing Polynomials Using Unipolar
                                  Stochastic Logic . . . . . . . . . . . . 42:1--42:??
     Pareesa Ameneh Golnari and   
                Yavuz Yetim and   
         Margaret Martonosi and   
                Yakir Vizel and   
                   Sharad Malik   PPU: a Control Error-Tolerant Processor
                                  for Streaming Applications with Formal
                                  Guarantees . . . . . . . . . . . . . . . 43:1--43:??
            Anusha Gorantla and   
                       Deepa P.   Design of Approximate Compressors for
                                  Multiplication . . . . . . . . . . . . . 44:1--44:??
               Arvind Kumar and   
                    Zhe Wan and   
         Winfried W. Wilcke and   
            Subramanian S. Iyer   Toward Human-Scale Brain Computing Using
                                  $3$D Wafer Scale Integration . . . . . . 45:1--45:??
            Mohammed Alawad and   
                    Mingjie Lin   Sketching Computation with Stochastic
                                  Processing Engines . . . . . . . . . . . 46:1--46:??
               Armin Alaghi and   
           Wei-Ting J. Chan and   
              John P. Hayes and   
            Andrew B. Kahng and   
                      Jiajia Li   Trading Accuracy for Energy in
                                  Stochastic Circuit Design  . . . . . . . 47:1--47:??
              Soheil Salehi and   
                Deliang Fan and   
               Ronald F. Demara   Survey of STT--MRAM Cell Design
                                  Strategies: Taxonomy and Sense Amplifier
                                  Tradeoffs for Resiliency . . . . . . . . 48:1--48:??
                Songping Yu and   
                  Nong Xiao and   
               Mingzhu Deng and   
                   Fang Liu and   
                       Wei Chen   Redesign the Memory Allocator for
                                  Non-Volatile Main Memory . . . . . . . . 49:1--49:??
                    Bing Li and   
                      Yu Hu and   
                  Ying Wang and   
                    Jing Ye and   
                     Xiaowei Li   Power-Utility-Driven Write Management
                                  for MLC PCM  . . . . . . . . . . . . . . 50:1--50:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 13, Number 4, August, 2017

           Mrityunjay Ghosh and   
          Amlan Chakrabarti and   
                   Niraj K. Jha   Automated Quantum Circuit Synthesis and
                                  Cost Estimation for the Binary Welded
                                  Tree Oracle  . . . . . . . . . . . . . . 51:1--51:??
           Rekha Govindaraj and   
                  Swaroop Ghosh   Design and Analysis of STTRAM-Based
                                  Ternary Content Addressable Memory Cell  52:1--52:??
              Eldhose Peter and   
                 Anuj Arora and   
             Janibul Bashir and   
             Akriti Bagaria and   
              Smruti R. Sarangi   Optical Overlay NUCA: a High-Speed
                                  Substrate for Shared L2 Caches . . . . . 53:1--53:??
            Abhishek Koneru and   
           Sukeshwar Kannan and   
         Krishnendu Chakrabarty   Impact of Electrostatic Coupling and
                                  Wafer-Bonding Defects on Delay Testing
                                  of Monolithic $3$D Integrated Circuits   54:1--54:??
        Mahboobeh Houshmand and   
              Mehdi Sedighi and   
       Morteza Saheb Zamani and   
                Kourosh Marjoei   Quantum Circuit Synthesis Targeting to
                                  Improve One-Way Quantum Computation
                                  Pattern Cost Metrics . . . . . . . . . . 55:1--55:??
           Karthik Yogendra and   
       Chamika Liyanagedera and   
                Deliang Fan and   
                  Yong Shim and   
                    Kaushik Roy   Coupled Spin-Torque
                                  Nano-Oscillator-Based Computation: a
                                  Simulation Study . . . . . . . . . . . . 56:1--56:??
           M. Hassan Najafi and   
                    Peng Li and   
             David J. Lilja and   
               Weikang Qian and   
               Kia Bazargan and   
                    Marc Riedel   A Reconfigurable Architecture with
                                  Sequential Logic-Based Stochastic
                                  Computing  . . . . . . . . . . . . . . . 57:1--57:??
Sai Vineel Reddy Chittamuru and   
             Srinivas Desai and   
                Sudeep Pasricha   SWIFTNoC: a Reconfigurable
                                  Silicon-Photonic Network with
                                  Multicast-Enabled Channel Sharing for
                                  Multicore Architectures  . . . . . . . . 58:1--58:??
        Sandeep Kumar Samal and   
               Guoqing Chen and   
                   Sung Kyu Lim   Improving Performance under Process and
                                  Voltage Variations in Near-Threshold
                                  Computing Using $3$D ICs . . . . . . . . 59:1--59:??
              Honglan Jiang and   
                   Cong Liu and   
                  Leibo Liu and   
          Fabrizio Lombardi and   
                        Jie Han   A Review, Classification, and
                                  Comparative Evaluation of Approximate
                                  Arithmetic Circuits  . . . . . . . . . . 60:1--60:??
                     Hui Li and   
   Sébastien Le Beux and   
   Martha Johanna Sepulveda and   
                   Ian O'Connor   Energy-Efficiency Comparison of
                                  Multi-Layer Deposited Nanophotonic
                                  Crossbar Interconnects . . . . . . . . . 61:1--61:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 14, Number 1, March, 2018

                  Neel Gala and   
         Sarada Krithivasan and   
                Wei-Yu Tsai and   
                 Xueqing Li and   
    Vijaykrishnan Narayanan and   
                    V. Kamakoti   An Accuracy Tunable Non-Boolean
                                  Co-Processor Using Coupled
                                  Nano-Oscillators . . . . . . . . . . . . 1:1--1:??
               Mesbah Uddin and   
    MD. Badruddoja Majumder and   
           Karsten Beckmann and   
               Harika Manem and   
         Zahiruddin Alamgir and   
          Nathaniel C. Cady and   
                Garrett S. Rose   Design Considerations for Memristive
                                  Crossbar Physical Unclonable Functions   2:1--2:??
                      Ye Yu and   
                   Niraj K. Jha   Statistical Optimization of FinFET
                                  Processor Architectures under PVT
                                  Variations Using Dual Device-Type
                                  Assignment . . . . . . . . . . . . . . . 3:1--3:??
 Mohammad Hossein Hajkazemi and   
    Mohammad Khavari Tavana and   
           Tinoosh Mohsenin and   
                Houman Homayoun   Heterogeneous HMC + DDRx Memory
                                  Management for Performance-Temperature
                                  Tradeoffs  . . . . . . . . . . . . . . . 4:1--4:??
      Sukanta Bhattacharjee and   
              Debasis Mitra and   
        Bhargab B. Bhattacharya   Robust In-Field Testing of Digital
                                  Microfluidic Biochips  . . . . . . . . . 5:1--5:??
               Xiaokun Yang and   
                  Wujie Wen and   
                       Ming Fan   Improving AES Core Performance via an
                                  Advanced ASBUS Protocol  . . . . . . . . 6:1--6:??
             Kenneth O'neal and   
             Daniel Grissom and   
                   Philip Brisk   Resource-Constrained Scheduling for
                                  Digital Microfluidic Biochips  . . . . . 7:1--7:??
     Seyedhamidreza Motaman and   
              Swaroop Ghosh and   
               Jaydeep Kulkarni   Impact of Process Variation on
                                  Self-Reference Sensing Scheme and
                                  Adaptive Current Modulation for Robust
                                  STTRAM Sensing . . . . . . . . . . . . . 8:1--8:??
           Vincenzo Catania and   
               Andrea Mineo and   
       Salvatore Monteleone and   
            Maurizio Palesi and   
                   Davide Patti   Improving Energy Efficiency in Wireless
                                  Network-on-Chip Architectures  . . . . . 9:1--9:??
                   Bohua Li and   
                  Yukui Pei and   
                      Wujie Wen   Efficient LDPC Code Design for Combating
                                  Asymmetric Errors in STT-RAM . . . . . . 10:1--10:??
                     Yu Liu and   
              Yingyezhe Jin and   
                        Peng Li   Online Adaptation and Energy
                                  Minimization for Hardware Recurrent
                                  Spiking Neural Networks  . . . . . . . . 11:1--11:??
                Paolo Grani and   
               Sandro Bartolini   Scalable Path-Setup Scheme for
                                  All-Optical Dynamic Circuit Switched
                                  NoCs in Cache Coherent CMPs  . . . . . . 12:1--12:??
          Andre Van Rynbach and   
             Muhammad Ahsan and   
                   Jungsang Kim   A Quantum Computing Performance
                                  Simulator Based on Circuit Failure
                                  Probability and Fault Path Counting  . . 13:1--13:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 14, Number 2, July, 2018

                     Yu Cao and   
                     Xin Li and   
                Jae-Sun Seo and   
                  Ganesh Dasika   Guest Editors' Introduction: Frontiers
                                  of Hardware and Algorithms for On-chip
                                  Learning . . . . . . . . . . . . . . . . 14:1--14:??
               Hyungjun Kim and   
                  Taesu Kim and   
                Jinseok Kim and   
                   Jae-Joon Kim   Deep Neural Network Optimized to
                                  Resistive Memory with Nonlinear
                                  Current-Voltage Characteristics  . . . . 15:1--15:??
         Syed Shakib Sarwar and   
      Swagath Venkataramani and   
               Aayush Ankit and   
          Anand Raghunathan and   
                    Kaushik Roy   Energy-Efficient Neural Computing with
                                  Approximate Multipliers  . . . . . . . . 16:1--16:??
                Glenn G. Ko and   
                Rob A. Rutenbar   Real-Time and Low-Power Streaming Source
                                  Separation Using Markov Random Field . . 17:1--17:??
                  Yixing Li and   
                Zichuan Liu and   
                     Kai Xu and   
                     Hao Yu and   
                     Fengbo Ren   A GPU-Outperforming FPGA Accelerator
                                  Architecture for Binary Convolutional
                                  Neural Networks  . . . . . . . . . . . . 18:1--18:??
            Thomas E. Potok and   
          Catherine Schuman and   
               Steven Young and   
              Robert Patton and   
        Federico Spedalieri and   
                 Jeremy Liu and   
                Ke-Thia Yao and   
               Garrett Rose and   
               Gangotree Chakma   A Study of Complex Deep Learning
                                  Networks on High-Performance,
                                  Neuromorphic, and Quantum Computers  . . 19:1--19:??
                   Jiang Xu and   
            Yuichi Nakamura and   
                   Andrew Kahng   Silicon Photonics for Computing Systems  20:1--20:??
                  Zhe Zhang and   
                      Yaoyao Ye   A Learning-Based Thermal-Sensitive Power
                                  Optimization Approach for Optical NoCs   21:1--21:??
                      Yi Xu and   
                   Jun Yang and   
                    Rami Melhem   A Process-Variation-Tolerant Method for
                                  Nanophotonic On-Chip Network . . . . . . 22:1--22:??
            Edoardo Fusella and   
             Alessandro Cilardo   Reducing Power Consumption of Lasers in
                                  Photonic NoCs through
                                  Application-Specific Mapping . . . . . . 23:1--23:??
                Jiating Luo and   
             Cedric Killian and   
          Sebastien Le Beux and   
             Daniel Chillet and   
           Olivier Sentieys and   
                   Ian O'Connor   Offline Optimization of Wavelength
                                  Allocation and Laser Power in
                                  Nanophotonic Interconnects . . . . . . . 24:1--24:??
            Scott Vanwinkle and   
           Avinash Karanth Kodi   SHARP: Shared Heterogeneous Architecture
                                  with Reconfigurable Photonic
                                  Network-on-Chip  . . . . . . . . . . . . 25:1--25:??
             Tohru Ishihara and   
             Akihiko Shinya and   
                 Koji Inoue and   
               Kengo Nozaki and   
                  Masaya Notomi   An Integrated Nanophotonic Parallel
                                  Adder  . . . . . . . . . . . . . . . . . 26:1--26:??
                     Shi Xu and   
                  Zhang Luo and   
                Mingche Lai and   
              Zhengbin Pang and   
                       Renfa Li   Integrated High-Speed Optical SerDes
                                  over 100GBd Based on Optical Time
                                  Division Multiplexing  . . . . . . . . . 27:1--27:??
             Ali Alsuwaiyan and   
                Kartik Mohanram   MFNW: an MLC/TLC Flip-N-Write
                                  Architecture . . . . . . . . . . . . . . 28:1--28:??
                 Shuai Chen and   
                Junlin Chen and   
                       Lei Wang   A Chip-Level Anti-Reverse Engineering
                                  Technique  . . . . . . . . . . . . . . . 29:1--29:??
     Debjyoti Bhattacharjee and   
                Anne Siemon and   
                  Eike Linn and   
             Stephan Menzel and   
           Anupam Chattopadhyay   Kogge--Stone Adder Realization using
                                  1S1R Resistive Switching Crossbar Arrays 30:1--30:??
         Florian Neugebauer and   
                Ilia Polian and   
                  John P. Hayes   Framework for Quantifying and Managing
                                  Accuracy in Stochastic Circuit Design    31:1--31:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 14, Number 3, October, 2018

                Dongjin Lee and   
                 Sourav Das and   
               Dae Hyun Kim and   
        Janardhan Rao Doppa and   
            Partha Pratim Pande   Design Space Exploration of $3$D
                                  Network-on-Chip: a Sensitivity-based
                                  Optimization Approach  . . . . . . . . . 32:1--32:??
               Xiaotong Cui and   
              Elnaz Koopahi and   
                  Kaijie Wu and   
                   Ramesh Karri   Hardware Trojan Detection Using the
                                  Order of Path Delay  . . . . . . . . . . 33:1--33:??
               Guan-Ruei Lu and   
           Ansuman Banerjee and   
    Bhargab B. Bhattacharya and   
                Tsung-Yi Ho and   
                 Hung-Ming Chen   Reliability Hardening Mechanisms in
                                  Cyber-Physical Digital-Microfluidic
                                  Biochips . . . . . . . . . . . . . . . . 34:1--34:??
            Farhana Parveen and   
             Shaahin Angizi and   
                    Deliang Fan   IMFlexCom: Energy Efficient In-Memory
                                  Flexible Computing Using Dual-Mode
                                  SOT-MRAM . . . . . . . . . . . . . . . . 35:1--35:??
 Edgard Muñoz-Coreas and   
             Himanshu Thapliyal   T-count and Qubit Optimized Quantum
                                  Circuit Design of the Non-Restoring
                                  Square Root Algorithm  . . . . . . . . . 36:1--36:15
             Ayed Alqahtani and   
               Zongqing Ren and   
                  Jaeho Lee and   
              Nader Bagherzadeh   System-Level Analysis of $3$D ICs with
                                  Thermal TSVs . . . . . . . . . . . . . . 37:1--37:??
             Nihar Athreyas and   
                Wenhao Song and   
                Blair Perot and   
               Qiangfei Xia and   
               Abbie Mathew and   
                  Jai Gupta and   
                  Dev Gupta and   
                 J. Joshua Yang   Memristor-CMOS Analog Coprocessor for
                                  Acceleration of High-Performance
                                  Computing Applications . . . . . . . . . 38:1--38:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 14, Number 4, December, 2018

                      Anonymous   Guest Editor Introduction: Neuromorphic
                                  Computing  . . . . . . . . . . . . . . . 39:1--39:??
       Kathleen E. Hamilton and   
                 Neena Imam and   
               Travis S. Humble   Sparse Hardware Embedding of Spiking
                                  Neuron Systems for Community Detection   40:1--40:??
   Venkataramesh Bontupalli and   
             Chris Yakopcic and   
              Raqibul Hasan and   
                  Tarek M. Taha   Efficient Memristor-Based Architecture
                                  for Intrusion Detection and High-Speed
                                  Packet Classification  . . . . . . . . . 41:1--41:??
            Kyungwook Chang and   
           Deepak Kadetotad and   
                     Yu Cao and   
                Jae-Sun Seo and   
                   Sung Kyu Lim   Power, Performance, and Area Benefit of
                                  Monolithic $3$D ICs for On-Chip Deep
                                  Neural Networks Targeting Speech
                                  Recognition  . . . . . . . . . . . . . . 42:1--42:??
         Abdullah M. Zyarah and   
          Dhireesha Kudithipudi   Semi-Trained Memristive Crossbar
                                  Computing Engine with In Situ Learning
                                  Accelerator  . . . . . . . . . . . . . . 43:1--43:??
  Gopalakrishnan Srinivasan and   
        Priyadarshini Panda and   
                    Kaushik Roy   STDP-based Unsupervised Feature Learning
                                  using Convolution-over-time in Spiking
                                  Neural Networks for Energy-Efficient
                                  Neuromorphic Computing . . . . . . . . . 44:1--44:??
                Kangjun Bai and   
                        Yang Yi   DFR: an Energy-efficient Analog Delay
                                  Feedback Reservoir Computing System for
                                  Brain-inspired Computing . . . . . . . . 45:1--45:??
                Lisa Loomis and   
            Nathan McDonald and   
                    Cory Merkel   An FPGA Implementation of a Time Delay
                                  Reservoir Using Stochastic Logic . . . . 46:1--46:??
              Zhongyang Liu and   
               Shaoheng Luo and   
                 Xiaowei Xu and   
                   Yiyu Shi and   
                     Cheng Zhuo   A Multi-Level-Optimization Framework for
                                  FPGA-Based Cellular Neural Network
                                  Implementation . . . . . . . . . . . . . 47:1--47:??
                 Xiaowei Xu and   
                    Qing Lu and   
              Tianchen Wang and   
                      Yu Hu and   
                  Chen Zhuo and   
                Jinglan Liu and   
                       Yiyu Shi   Efficient Hardware Implementation of
                                  Cellular Neural Networks with
                                  Incremental Quantization and Early Exit  48:1--48:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 15, Number 1, February, 2019

            Edoardo Fusella and   
              Mahdi Nikdast and   
               Ian O'Connor and   
          José Flich and   
                Sudeep Pasricha   Guest Editors' Introduction: Emerging
                                  Networks-on-Chip Designs, Technologies,
                                  and Applications . . . . . . . . . . . . 1:1--1:??
               Mourad Dridi and   
     Stéphane Rubini and   
             Mounir Lallali and   
Martha Johanna Sepúlveda Flórez and   
             Frank Singhoff and   
           Jean-Philippe Diguet   Design and Multi-Abstraction-Level
                                  Evaluation of a NoC Router for
                                  Mixed-Criticality Real-Time Systems  . . 2:1--2:??
         Mladen Slijepcevic and   
           Carles Hernandez and   
               Jaume Abella and   
           Francisco J. Cazorla   Time-Randomized Wormhole NoCs for
                                  Critical Applications  . . . . . . . . . 3:1--3:??
                Ahmed Louri and   
             Jacques Collet and   
                Avinash Karanth   Limit of Hardware Solutions for
                                  Self-Protecting Fault-Tolerant NoCs  . . 4:1--4:??
              P. Veda Bhanu and   
  Pranav Venkatesh Kulkarni and   
                      Soumya J.   Fault-Tolerant Network-on-Chip Design
                                  with Flexible Spare Core Placement . . . 5:1--5:??
              Kanchan Manna and   
         Chatla Swami Sagar and   
      Santanu Chattopadhyay and   
              Indranil Sengupta   Thermal-aware Test Scheduling Strategy
                                  for Network-on-Chip based Systems  . . . 6:1--6:??
               Sneha N. Ved and   
            Sarabjeet Singh and   
                   Joycee Mekie   PANE: Pluggable Asynchronous
                                  Network-on-Chip Simulator  . . . . . . . 7:1--7:??
             Janibul Bashir and   
              Eldhose Peter and   
              Smruti R. Sarangi   BigBus: a Scalable Optical Interconnect  8:1--8:??
                    Zhen Xu and   
                 Xuhao Chen and   
                   Jie Shen and   
                 Yang Zhang and   
                 Cheng Chen and   
                    Canqun Yang   GARDENIA: a Graph Processing Benchmark
                                  Suite for Next-Generation Accelerators   9:1--9:??
              Su-Kyung Yoon and   
             Young-Sun Youn and   
          Bernd Burgstaller and   
                   Shin-Dug Kim   Self-learnable Cluster-based Prefetching
                                  Method for DRAM-Flash Hybrid Main Memory
                                  Architecture . . . . . . . . . . . . . . 10:1--10:??
               Xiaotong Cui and   
           Jeff (Jun) Zhang and   
                  Kaijie Wu and   
             Siddharth Garg and   
                   Ramesh Karri   Split Manufacturing-Based Register
                                  Transfer-Level Obfuscation . . . . . . . 11:1--11:??
                 Bingzhe Li and   
                 Yaobin Qin and   
                    Bo Yuan and   
                 David J. Lilja   Neural Network Classifiers Using a
                                  Hardware-Based Approximate Activation
                                  Function with a Hybrid Stochastic
                                  Multiplier . . . . . . . . . . . . . . . 12:1--12:??
                  Zhou Zhao and   
           Ashok Srivastava and   
                    Lu Peng and   
                      Qing Chen   Long Short-Term Memory Network Design
                                  for Analog Computing . . . . . . . . . . 13:1--13:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 15, Number 2, June, 2019

                Jae-Sun Seo and   
                     Yu Cao and   
                     Xin Li and   
                 Paul Whatmough   Guest Editors' Introduction to the
                                  Special Section on Hardware and
                                  Algorithms for Energy-Constrained
                                  On-chip Machine Learning . . . . . . . . 14:1--14:??
                Weijia Wang and   
                       Bill Lin   Trained Biased Number Representation for
                                  ReRAM-Based Neural Network Accelerators  15:1--15:??
               Ankit Mondal and   
               Ankur Srivastava   In Situ Stochastic Training of MTJ
                                  Crossbars With Machine Learning
                                  Algorithms . . . . . . . . . . . . . . . 16:1--16:??
                Ramtin Zand and   
           Kerem Y. Camsari and   
              Supriyo Datta and   
               Ronald F. Demara   Composable Probabilistic Inference
                                  Networks Using MRAM-based Stochastic
                                  Neurons  . . . . . . . . . . . . . . . . 17:1--17:??
                 Bingzhe Li and   
           M. Hassan Najafi and   
                 David J. Lilja   Low-Cost Stochastic Hybrid Multiplier
                                  for Quantized Neural Networks  . . . . . 18:1--18:??
                 Qiuwen Lou and   
                Chenyun Pan and   
            John McGuinness and   
             Andras Horvath and   
                Azad Naeemi and   
            Michael Niemier and   
                   X. Sharon Hu   A Mixed Signal Architecture for
                                  Convolutional Neural Networks  . . . . . 19:1--19:??
           Praveen K. Pilly and   
             Nigel D. Stepp and   
              Yannis Liapis and   
            David W. Payton and   
              Narayan Srinivasa   Hypercolumn Sparsification for Low-Power
                                  Convolutional Neural Networks  . . . . . 20:1--20:??
               Mohsen Imani and   
             Ricardo Garcia and   
              Saransh Gupta and   
                  Tajana Rosing   Hardware-Software Co-design to
                                  Accelerate Neural Network Applications   21:1--21:??
            Maxence Bouvier and   
        Alexandre Valentian and   
            Thomas Mesquida and   
    François Rummens and   
              Marina Reyboz and   
             Elisa Vianello and   
                   Edith Beigne   Spiking Neural Networks Hardware
                                  Implementations and Challenges: a Survey 22:1--22:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 15, Number 3, June, 2019

        Samah Mohamed Saeed and   
           Nithin Mahendran and   
             Alwin Zulehner and   
               Robert Wille and   
                   Ramesh Karri   Identification of Synthesis Approaches
                                  for IP/IC Piracy of Reversible Circuits  23:1--23:??
         Abdullah M. Zyarah and   
          Dhireesha Kudithipudi   Neuromemrisitive Architecture of HTM
                                  with On-Device Learning and Neurogenesis 24:1--24:??
                 Qixiao Liu and   
               Zhifeng Chen and   
                      Zhibin Yu   MiC: Multi-level Characterization and
                                  Optimization of GPGPU Kernels  . . . . . 25:1--25:??
            Andreas Grimmer and   
         Medina Hamidovi\'c and   
           Werner Haselmayr and   
                   Robert Wille   Advanced Simulation of Droplet
                                  Microfluidics  . . . . . . . . . . . . . 26:1--26:??
                     Yu Liu and   
 Sai Sourabh Yenamachintala and   
                        Peng Li   Energy-efficient FPGA Spiking Neural
                                  Accelerators with Supervised and
                                  Unsupervised
                                  Spike-timing-dependent-Plasticity  . . . 27:1--27:??
                 Gaoming Du and   
                 Guanyu Liu and   
                 Zhenmin Li and   
                  Yifan Cao and   
                Duoli Zhang and   
              Yiming Ouyang and   
                Minglun Gao and   
                    Zhonghai Lu   SSS: Self-aware System-on-chip Using a
                                  Static-dynamic Hybrid Method . . . . . . 28:1--28:??
              Marcel Walter and   
               Robert Wille and   
         Daniel Große and   
          Frank Sill Torres and   
                 Rolf Drechsler   Placement and Routing for Tile-based
                                  Field-coupled Nanocomputing Circuits Is
                                  NP-complete (Research Note)  . . . . . . 29:1--29:??
                   Sumin Li and   
               Kaixin Huang and   
              Linpeng Huang and   
                    Jiashun Zhu   LiwePMS: a Lightweight Persistent Memory
                                  with Wear-aware Memory Management  . . . 30:1--30:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 15, Number 4, December, 2019

                Jae-Sun Seo and   
                     Yu Cao and   
                     Xin Li and   
                 Paul Whatmough   Guest Editors' Introduction: Hardware
                                  and Algorithms for Energy-Constrained
                                  On-Chip Machine Learning (Part 2)  . . . 31:1--31:??
             Manuel Schmuck and   
                Luca Benini and   
                   Abbas Rahimi   Hardware Optimizations of Dense Binary
                                  Hyperdimensional Computing:
                                  Rematerialization of Hypervectors,
                                  Binarized Bundling, and Combinational
                                  Associative Memory . . . . . . . . . . . 32:1--32:??
Sai Manoj Pudukotai Dinakarrao and   
                Arun Joseph and   
             Anand Haridass and   
          Muhammad Shafique and   
           Jörg Henkel and   
                Houman Homayoun   Application and
                                  Thermal-reliability-aware Reinforcement
                                  Learning Based Multi-core Power
                                  Management . . . . . . . . . . . . . . . 33:1--33:??
                  The H. Vu and   
             Yuichi Okuyama and   
         Abderazek Ben Abdallah   Comprehensive Analytic Performance
                                  Assessment and $K$-means based Multicast
                                  Routing Algorithm and Architecture for
                                  $3$D-NoC of Spiking Neurons  . . . . . . 34:1--34:??
                 Yibin Tang and   
                  Ying Wang and   
                  Huawei Li and   
                     Xiaowei Li   MV-Net: Toward Real-Time Deep Learning
                                  on Mobile GPGPU Systems  . . . . . . . . 35:1--35:??
                 Colin Shea and   
               Tinoosh Mohsenin   Heterogeneous Scheduling of Deep Neural
                                  Networks for Low-power Real-time Designs 36:1--36:??
             Michaela Blott and   
                Lisa Halder and   
              Miriam Leeser and   
                    Linda Doyle   QuTiBench: Benchmarking Neural Networks
                                  on Heterogeneous Hardware  . . . . . . . 37:1--37:??
             Pampa Howladar and   
                 Pranab Roy and   
                Hafizur Rahaman   A High-performance Homogeneous Droplet
                                  Routing Technique for MEDA-based
                                  Biochips . . . . . . . . . . . . . . . . 38:1--38:??
                    Bing Li and   
                Mengjie Mao and   
               Xiaoxiao Liu and   
                    Tao Liu and   
                  Zihao Liu and   
                  Wujie Wen and   
                 Yiran Chen and   
                 Hai (Helen) Li   Thread Batching for High-performance
                                  Energy-efficient GPU Memory Design . . . 39:1--39:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 16, Number 1, February, 2020

                   Ramesh Karri   Editorial  . . . . . . . . . . . . . . . 1:1--1:1
                  Wang Kang and   
                      Bi Wu and   
                  Xing Chen and   
                Daoqian Zhu and   
               Zhaohao Wang and   
               Xichao Zhang and   
                   Yan Zhou and   
             Youguang Zhang and   
                  Weisheng Zhao   A Comparative Cross-layer Study on
                                  Racetrack Memories: Domain Wall vs
                                  Skyrmion . . . . . . . . . . . . . . . . 2:1--2:17
           Kaitlin N. Smith and   
           Mitchell A. Thornton   Higher Dimension Quantum Entanglement
                                  Generators . . . . . . . . . . . . . . . 3:1--3:21
             Janibul Bashir and   
          Smruti Ranjan Sarangi   Predict, Share, and Recycle Your Way to
                                  Low-power Nanophotonic Networks  . . . . 4:1--4:26
           Christos Sakalis and   
        Alexandra Jimborean and   
           Stefanos Kaxiras and   
          Magnus Själander   Evaluating the Potential Applications of
                                  Quaternary Logic for Approximate
                                  Computing  . . . . . . . . . . . . . . . 5:1--5:25
               Jungmin Park and   
               Fahim Rahman and   
           Apostol Vassilev and   
              Domenic Forte and   
               Mark Tehranipoor   Leveraging Side-Channel Information for
                                  Disassembly and Security . . . . . . . . 6:1--6:21
               Ankit Mondal and   
               Ankur Srivastava   Energy-efficient Design of MTJ-based
                                  Neural Networks with Stochastic
                                  Computing  . . . . . . . . . . . . . . . 7:1--7:27
              Hokchhay Tann and   
                  Heng Zhao and   
                   Sherief Reda   A Resource-Efficient Embedded Iris
                                  Recognition System Using Fully
                                  Convolutional Networks . . . . . . . . . 8:1--8:23
                Weilong Cui and   
        Georgios Tzimpragos and   
                     Yu Tao and   
             Joseph McMahan and   
            Deeksha Dangwal and   
         Nestan Tsiskaridze and   
    George Michelogiannakis and   
         Dilip P. Vasudevan and   
               Timothy Sherwood   Language Support for Navigating
                                  Architecture Design in Closed Form . . . 9:1--9:28
            Mahzabeen Islam and   
          Shashank Adavally and   
               Marko Scrbak and   
                   Krishna Kavi   On-the-fly Page Migration and Address
                                  Reconciliation for Heterogeneous Memory
                                  Systems  . . . . . . . . . . . . . . . . 10:1--10:27
          Frank Sill Torres and   
            Philipp Niemann and   
               Robert Wille and   
                 Rolf Drechsler   Near Zero-Energy Computation Using
                                  Quantum-Dot Cellular Automata  . . . . . 11:1--11:16

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 16, Number 2, April, 2020

                Fengyu Qian and   
               Yanping Gong and   
                       Lei Wang   A Memristor-Based Compressive Sampling
                                  Encoder with Dynamic Rate Control for
                                  Low-Power Video Streaming  . . . . . . . 12:1--12:16
        Hoang Anh Du Nguyen and   
                  Jintao Yu and   
           Muath Abu Lebdeh and   
        Mottaqiallah Taouil and   
              Said Hamdioui and   
               Francky Catthoor   A Classification of Memory-Centric
                                  Computing  . . . . . . . . . . . . . . . 13:1--13:26
               Brian Crites and   
                 Karen Kong and   
                   Philip Brisk   Directed Placement for mVLSI Devices . . 14:1--14:26
                  Zhezhi He and   
                    Li Yang and   
             Shaahin Angizi and   
          Adnan Siraj Rakin and   
                    Deliang Fan   Sparse BD-Net: a Multiplication-less DNN
                                  with Sparse Binarized Depth-wise
                                  Separable Convolution  . . . . . . . . . 15:1--15:24
                   Lei Wang and   
                    Yu Deng and   
                   Rui Gong and   
                    Wei Shi and   
                     Li Luo and   
                   Yongwen Wang   CSMO--DSE: Fast and Precise
                                  Application-driven DSE Guided by
                                  Criticality and Sensitivity Analysis . . 16:1--16:22
                   Zimu Guo and   
           Sreeja Chowdhury and   
        Mark M. Tehranipoor and   
                  Domenic Forte   Permutation Network De-obfuscation: a
                                  Delay-based Attack and Countermeasure
                                  Investigation  . . . . . . . . . . . . . 17:1--17:25
        Mohammad M. A. Taha and   
              Christof Teuscher   Approximate Memristive In-Memory Hamming
                                  Distance Circuit . . . . . . . . . . . . 18:1--18:14
             Farhan Rasheed and   
         Michael Hefenbrock and   
           Rajendra Bishnoi and   
              Michael Beigl and   
     Jasmin Aghassi-Hagmann and   
               Mehdi B. Tahoori   Crossover-aware Placement and Routing
                                  for Inkjet Printed Circuits  . . . . . . 19:1--19:22
                    Bing Li and   
        Janardhan Rao Doppa and   
        Partha Pratim Pande and   
     Krishnendu Chakrabarty and   
                 Joe X. Qiu and   
                 Hai (Helen) Li   $3$D-ReG: a $3$D ReRAM-based
                                  Heterogeneous Architecture for Training
                                  Deep Neural Networks . . . . . . . . . . 20:1--20:24
             Giuseppe Ascia and   
           Vincenzo Catania and   
       Salvatore Monteleone and   
            Maurizio Palesi and   
               Davide Patti and   
                  John Jose and   
          Valerio Mario Salerno   Exploiting Data Resilience in Wireless
                                  Network-on-chip Architectures  . . . . . 21:1--21:27
           Tiffany M. Mintz and   
      Alexander J. McCaskey and   
       Eugene F. Dumitrescu and   
           Shirley V. Moore and   
               Sarah Powers and   
                Pavel Lougovski   QCOR: a Language Extension Specification
                                  for the Heterogeneous Quantum-Classical
                                  Model of Computation . . . . . . . . . . 22:1--22:17
           Karsten Beckmann and   
      Wilkie Olin-Ammentorp and   
           Gangotree Chakma and   
                Sherif Amer and   
            Garrett S. Rose and   
                Chris Hobbs and   
        Joseph Van Nostrand and   
             Martin Rodgers and   
              Nathaniel C. Cady   Towards Synaptic Behavior of Nanoscale
                                  ReRAM Devices for Neuromorphic Computing
                                  Applications . . . . . . . . . . . . . . 23:1--23:18

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 16, Number 3, July, 2020

                   Helen Li and   
                  Wei Zhang and   
              Swarup Bhunia and   
                      Wujie Wen   Introduction to the Special Issue on New
                                  Trends in Nanoelectronic Device,
                                  Circuit, and Architecture Design,Part 1  24:1--24:3
                  Fan Zhang and   
                        Miao Hu   Mitigate Parasitic Resistance in
                                  Resistive Crossbar-based Convolutional
                                  Neural Networks  . . . . . . . . . . . . 25:1--25:20
                Xinyi Zhang and   
             Clay Patterson and   
                Yongpan Liu and   
               Chengmo Yang and   
             Chun Jason Xue and   
                    Jingtong Hu   Low Overhead Online Data Flow Tracking
                                  for Intermittently Powered Non-Volatile
                                  FPGAs  . . . . . . . . . . . . . . . . . 26:1--26:20
                   Sumin Li and   
                  Linpeng Huang   LosPem: a Novel Log-Structured Framework
                                  for Persistent Memory  . . . . . . . . . 27:1--27:17
     Sagarvarma Sayyaparaju and   
          Md Musabbir Adnan and   
                Sherif Amer and   
                Garrett S. Rose   Device-aware Circuit Design for Robust
                                  Memristive Neuromorphic Systems with
                                  STDP-based Learning  . . . . . . . . . . 28:1--28:25
                Jiacheng Ni and   
                  Keren Liu and   
                      Bi Wu and   
              Weisheng Zhao and   
             Yuanqing Cheng and   
             Xiaolong Zhang and   
                      Ying Wang   Write Back Energy Optimization for
                                  STT-MRAM-based Last-level Cache with
                                  Data Pattern Characterization  . . . . . 29:1--29:18
       I. M. Delgado-Lozano and   
     E. Tena-Sánchez and   
     J. Núñez and   
                   A. J. Acosta   Projection of Dual-Rail DPA
                                  Countermeasures in Future FinFET and
                                  Emerging TFET Technologies . . . . . . . 30:1--30:16
                Subrata Das and   
           Debesh Kumar Das and   
                  Soumya Pandit   A Global Routing Method for Graphene
                                  Nanoribbons Based Circuits and
                                  Interconnects  . . . . . . . . . . . . . 31:1--31:28
                Shin Nishio and   
                   Yulu Pan and   
             Takahiko Satoh and   
             Hideharu Amano and   
               Rodney Van Meter   Extracting Success from IBM's $
                                  20$-Qubit Machines Using Error-Aware
                                  Compilation  . . . . . . . . . . . . . . 32:1--32:25
                J. Hyun Kim and   
              Young Je Moon and   
               Hyunsub Song and   
                Jay H. Park and   
                     Sam H. Noh   On Providing OS Support to Allow
                                  Transparent Use of Traditional
                                  Programming Models for Persistent Memory 33:1--33:24
            S. Dinesh Kumar and   
             Himanshu Thapliyal   Design of Adiabatic Logic-Based
                                  Energy-Efficient and Reliable PUF for
                                  IoT Devices  . . . . . . . . . . . . . . 34:1--34:18

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 16, Number 4, October, 2020

                  Wei Zhang and   
                   Helen Li and   
                  Wujie Wen and   
                  Swarup Bhunia   Guest Editorial: ACM JETC Special Issue
                                  on New Trends in Nanolectronic Device,
                                  Circuit, and Architecture Design:Part 2  35:1--35:3
              Youngseok Kim and   
                Seyoung Kim and   
              Chun-Chen Yeh and   
            Vijay Narayanan and   
                  Jungwook Choi   Hardware and Software Co-optimization
                                  for the Initialization Failure of the
                                  ReRAM-based Cross-bar Array  . . . . . . 36:1--36:19
                Xueyan Wang and   
               Jienlei Yang and   
               Yinglin Zhao and   
                Xiaotao Jia and   
                    Gang Qu and   
                  Weisheng Zhao   Hardware Security in Spin-based
                                  Computing-in-memory: Analysis, Exploits,
                                  and Mitigation Techniques  . . . . . . . 37:1--37:18
Mohammad Hossein Samavatian and   
                 Anys Bacha and   
                    Li Zhou and   
                Radu Teodorescu   RNNFast: an Accelerator for Recurrent
                                  Neural Networks Using Domain-Wall Memory 38:1--38:27
                Ziyang Kang and   
                   Lei Wang and   
                 Shasha Guo and   
                   Rui Gong and   
                 Shiming Li and   
                    Yu Deng and   
                      Weixia Xu   ASIE: an Asynchronous SNN Inference
                                  Engine for AER Events Processing . . . . 39:1--39:22
            Bertrand Cambou and   
          David Hély and   
                   Sareh Assiri   Cryptography with Analog Scheme Using
                                  Memristors . . . . . . . . . . . . . . . 40:1--40:30
           Aqeeb Iqbal Arka and   
           Srinivasan Gopal and   
        Janardhan Rao Doppa and   
              Deukhyoun Heo and   
            Partha Pratim Pande   Making a Case for Partially Connected
                                  $3$D NoC: NFIC versus TSV  . . . . . . . 41:1--41:17
               Dhwani Mehta and   
                 Hangwei Lu and   
          Olivia P. Paradis and   
       Mukhil Azhagan M. S. and   
         M. Tanjidur Rahman and   
            Yousef Iskander and   
             Praveen Chawla and   
           Damon L. Woodard and   
           Mark Tehranipoor and   
             Navid Asadizanjani   The Big Hack Explained: Detection and
                                  Prevention of PCB Supply Chain Implants  42:1--42:25
                 Nour Sayed and   
           Rajendra Bishnoi and   
               Mehdi B. Tahoori   Approximate Spintronic Memories  . . . . 43:1--43:22
 Patricia Gonzalez-Guerrero and   
             Tommy Tracy II and   
                 Xinfei Guo and   
            Rahul Sreekumar and   
            Marzieh Lenjani and   
              Kevin Skadron and   
                 Mircea R. Stan   Towards on-node Machine Learning for
                                  Ultra-low-power Sensors Using
                                  Asynchronous $ \Sigma \Delta $ Streams   44:1--44:20


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 17, Number 1, January, 2021

       Muhammad Kamran Ayub and   
    Muhammad Abdullah Hanif and   
                Osman Hasan and   
              Muhammad Shafique   PEAL: Probabilistic Error Analysis
                                  Methodology for Low-power Approximate
                                  Adders . . . . . . . . . . . . . . . . . 1:1--1:37
             Ghasem Pasandi and   
                 Massoud Pedram   Depth-bounded Graph Partitioning
                                  Algorithm and Dual Clocking Method for
                                  Realization of Superconducting SFQ
                                  Circuits . . . . . . . . . . . . . . . . 2:1--2:22
                Manaar Alam and   
                  Arnab Bag and   
         Debapriya Basu Roy and   
               Dirmanto Jap and   
               Jakub Breier and   
              Shivam Bhasin and   
           Debdeep Mukhopadhyay   Neural Network-based Inherently
                                  Fault-tolerant Hardware Cryptographic
                                  Primitives without Explicit Redundancy
                                  Checks . . . . . . . . . . . . . . . . . 3:1--3:30
             Arnab Kumar Biswas   Network-on-Chip Intellectual Property
                                  Protection Using Circular Path-based
                                  Fingerprinting . . . . . . . . . . . . . 4:1--4:22
           Nandan Kumar Jha and   
              Sparsh Mittal and   
                Binod Kumar and   
              Govardhan Mattela   DeepPeep: Exploiting Design
                                  Ramifications to Decipher the
                                  Architecture of Compact DNNs . . . . . . 5:1--5:25
                 Xinmu Wang and   
             Tamzidul Hoque and   
             Abhishek Basak and   
               Robert Karam and   
                     Wei Hu and   
                Maoyuan Qin and   
                   Dejun Mu and   
                  Swarup Bhunia   Hardware Trojan Attack in Embedded
                                  Memory . . . . . . . . . . . . . . . . . 6:1--6:28
                 Yunfeng Lu and   
                   Huaxi Gu and   
                Xiaoshan Yu and   
         Krishnendu Chakrabarty   Lotus: a New Topology for Large-scale
                                  Distributed Machine Learning . . . . . . 7:1--7:21
             Janibul Bashir and   
              Smruti R. Sarangi   GPUOPT: Power-efficient Photonic
                                  Network-on-Chip for a Scalable GPU . . . 8:1--8:26
                 Nour Sayed and   
                Longfei Mao and   
               Mehdi B. Tahoori   Dynamic Behavior Predictions for Fast
                                  and Efficient Hybrid STT-MRAM Caches . . 9:1--9:21

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 17, Number 2, April, 2021

    Michiel Van Beirendonck and   
        Jan-Pieter D'anvers and   
         Angshuman Karmakar and   
              Josep Balasch and   
             Ingrid Verbauwhede   A Side-Channel-Resistant Implementation
                                  of SABER . . . . . . . . . . . . . . . . 10:1--10:26
             Qutaiba Alasad and   
                    Jie Lin and   
           Jiann-Shuin Yuan and   
                Deliang Fan and   
                      Amro Awad   Resilient and Secure Hardware Devices
                                  Using ASL  . . . . . . . . . . . . . . . 11:1--11:26
   Anand Kumar Mukhopadhyay and   
                Atul Sharma and   
       Indrajit Chakrabarti and   
               Arindam Basu and   
                 Mrigank Sharad   Power-efficient Spike Sorting Scheme
                                  Using Analog Spiking Neural Network
                                  Classifier . . . . . . . . . . . . . . . 12:1--12:29
         Anwesha Chatterjee and   
           Shouvik Musavvir and   
              Ryan Gary Kim and   
        Janardhan Rao Doppa and   
            Partha Pratim Pande   Power Management of Monolithic $3$D
                                  Manycore Chips with Inter-tier Process
                                  Variations . . . . . . . . . . . . . . . 13:1--13:19
                Manaar Alam and   
        Sarani Bhattacharya and   
           Debdeep Mukhopadhyay   Victims Can Be Saviors: a Machine
                                  Learning--based Detection for
                                  Micro-Architectural Side-Channel Attacks 14:1--14:31
              Chia-Cheng Wu and   
               Yi-Hsiang Hu and   
              Chia-Chun Lin and   
             Yung-Chih Chen and   
            Juinn-Dar Huang and   
                  Chun-Yao Wang   Diagnosis for Reconfigurable
                                  Single-Electron Transistor Arrays with a
                                  More Generalized Defect Model  . . . . . 15:1--15:23
          Shashank Adavally and   
            Mahzabeen Islam and   
                   Krishna Kavi   Dynamically Adapting Page Migration
                                  Policies Based on Applications' Memory
                                  Access Behaviors . . . . . . . . . . . . 16:1--16:24
                   Dat Tran and   
              Christof Teuscher   Computational Capacity of Complex
                                  Memcapacitive Networks . . . . . . . . . 17:1--17:25
                 Yiran Chen and   
                  Qinru Qiu and   
                    Yingyan Lin   Introduction of Special Issue on
                                  Hardware and Algorithms for Efficient
                                  Machine Learning-Part 1  . . . . . . . . 18:1--18:2
           Morteza Hosseini and   
               Tinoosh Mohsenin   Binary Precision Neural Network Manycore
                                  Accelerator  . . . . . . . . . . . . . . 19:1--19:27
               Nathan Zhang and   
               Kevin Canini and   
                 Sean Silva and   
                     Maya Gupta   Fast Linear Interpolation  . . . . . . . 20:1--20:15
             Alexis Asseman and   
            Nicolas Antoine and   
                 Ahmet S. Ozcan   Accelerating Deep Neuroevolution on
                                  Distributed FPGAs for Reinforcement
                                  Learning Problems  . . . . . . . . . . . 21:1--21:17
                 Palash Das and   
             Hemangee K. Kapoor   CLU: a Near-Memory Accelerator
                                  Exploiting the Parallelism in
                                  Convolutional Neural Networks  . . . . . 22:1--22:25
             Mohit Khatwani and   
            Hasib-Al Rashid and   
        Hirenkumar Paneliya and   
                Mark Horton and   
         Nicholas Waytowich and   
          W. David Hairston and   
               Tinoosh Mohsenin   A Flexible Multichannel EEG Artifact
                                  Identification Processor using
                                  Depthwise-Separable Convolutional Neural
                                  Networks . . . . . . . . . . . . . . . . 23:1--23:21
                 Adi Eliahu and   
                Ronny Ronen and   
 Pierre-Emmanuel Gaillardon and   
               Shahar Kvatinsky   multiPULPly: a Multiplication Engine for
                                  Accelerating Neural Networks on
                                  Ultra-low-power Architectures  . . . . . 24:1--24:27
       Saman Biookaghazadeh and   
          Pravin Kumar Ravi and   
                      Ming Zhao   Toward Multi-FPGA Acceleration of the
                                  Neural Networks  . . . . . . . . . . . . 25:1--25:23

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 17, Number 3, July, 2021

           Sourabh Kulkarni and   
                Sachin Bhat and   
            Csaba Andras Moritz   Architecting for Artificial Intelligence
                                  with Emerging Nanotechnology . . . . . . 26:1--26:33
                 Heewoo Kim and   
            Aporva Amarnath and   
          Javad Bagherzadeh and   
              Nishil Talati and   
           Ronald G. Dreslinski   A Survey Describing Beyond Si
                                  Transistors and Exploring Their
                                  Implications for Future Processors . . . 27:1--27:44
            Advait Madhavan and   
         Matthew W. Daniels and   
                 Mark D. Stiles   Temporal State Machines: Using Temporal
                                  Memory to Stitch Time-based Graph
                                  Computations . . . . . . . . . . . . . . 28:1--28:27
              Domenic Forte and   
       Debdeep Mukhopadhyay and   
                Ilia Polian and   
                  Yunsi Fei and   
              Rosario Cammarota   Introduction to the Special Issue on
                                  Emerging Challenges and Solutions in
                                  Hardware Security  . . . . . . . . . . . 29:1--29:4
         Dominik Sisejkovic and   
            Farhad Merchant and   
         Lennart M. Reimann and   
         Harshit Srivastava and   
              Ahmed Hallawa and   
                 Rainer Leupers   Challenging the Security of Logic
                                  Locking Schemes in the Era of Deep
                                  Learning: a Neuroevolutionary Approach   30:1--30:26
                   Jun Zhou and   
                Mengquan Li and   
               Pengxing Guo and   
                    Weichen Liu   Attack Mitigation of Hardware Trojans
                                  for Thermal Sensing via Micro-ring
                                  Resonator in Optical NoCs  . . . . . . . 31:1--31:23
          Ioannis Tsiokanos and   
              Jack Miskelly and   
                Chongyan Gu and   
              Maire O'neill and   
        Georgios Karakonstantis   DTA-PUF: Dynamic Timing-aware Physical
                                  Unclonable Function for
                                  Resource-constrained Devices . . . . . . 32:1--32:24
             Tapobrata Dhar and   
          Surajit Kumar Roy and   
                   Chandan Giri   Hardware Trojan Horse Detection through
                                  Improved Switching of Dormant Nets . . . 33:1--33:22
                 Asha K. A. and   
                  Li En Hsu and   
            Abhishek Patyal and   
                 Hung-Ming Chen   Improving the Quality of FPGA RO-PUF by
                                  Principal Component Analysis (PCA) . . . 34:1--34:25
          Eros Camacho-Ruiz and   
Santiago Sánchez-Solano and   
                Piedad Brox and   
Macarena C. Martínez-Rodríguez   Timing-Optimized Hardware Implementation
                                  to Accelerate Polynomial Multiplication
                                  in the NTRU Algorithm  . . . . . . . . . 35:1--35:16
          Noor Ahmad Hazari and   
                  Ahmed Oun and   
                Mohammed Niamat   Machine Learning Vulnerability Analysis
                                  of FPGA-based Ring Oscillator PUFs and
                                  Counter Measures . . . . . . . . . . . . 36:1--36:20
                 Yuntao Liu and   
              Michael Zuzak and   
                   Yang Xie and   
       Abhishek Chakraborty and   
               Ankur Srivastava   Robust and Attack Resilient Logic
                                  Locking with a High Application-Level
                                  Impact . . . . . . . . . . . . . . . . . 37:1--37:22
                 J. Laurent and   
                 C. Deleuze and   
          F. Pebay-Peyroula and   
                    V. Beroulle   Bridging the Gap between RTL and
                                  Software Fault Injection . . . . . . . . 38:1--38:24
         M. Tanjidur Rahman and   
        Nusrat Farzana Dipu and   
               Dhwani Mehta and   
               Shahin Tajik and   
           Mark Tehranipoor and   
             Navid Asadizanjani   CONCEALING-Gate: Optical Contactless
                                  Probing Resilient Design . . . . . . . . 39:1--39:25
                 Unai Rioja and   
             Servio Paguada and   
               Lejla Batina and   
                Igor Armendariz   The Uncertainty of Side-channel
                                  Analysis: a Way to Leverage from
                                  Heuristics . . . . . . . . . . . . . . . 40:1--40:27
           Damien Robissout and   
             Lilian Bossuet and   
             Amaury Habrard and   
                 Vincent Grosso   Improving Deep Learning Networks for
                                  Profiled Side-channel Analysis Using
                                  Performance Improvement Techniques . . . 41:1--41:30
           Lauren Biernacki and   
             Mark Gallagher and   
                 Zhixing Xu and   
        Misiker Tadesse Aga and   
              Austin Harris and   
                 Shijia Wei and   
               Mohit Tiwari and   
              Baris Kasikci and   
               Sharad Malik and   
                    Todd Austin   Software-driven Security Attacks: From
                                  Vulnerability Sources to Durable
                                  Hardware Defenses  . . . . . . . . . . . 42:1--42:38
                 Nico Mexis and   
Nikolaos Athanasios Anagnostopoulos and   
                 Shuai Chen and   
                Jan Bambach and   
                 Tolga Arul and   
           Stefan Katzenbeisser   A Lightweight Architecture for
                                  Hardware-Based Security in the Emerging
                                  Era of Systems of Systems  . . . . . . . 43:1--43:25
           Shubhra Deb Paul and   
                  Swarup Bhunia   SILVerIn: Systematic Integrity
                                  Verification of Printed Circuit Board
                                  Using JTAG Infrastructure  . . . . . . . 44:1--44:28

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 17, Number 4, July, 2021

                 Yiran Chen and   
                  Qinru Qiu and   
                    Yingyan Lin   Introduction to the Special Issue on
                                  Hardware and Algorithms for Efficient
                                  Machine Learning --- Part 2  . . . . . . 45:1--45:2
             Urmish Thakker and   
               Igor Fedorov and   
                   Chu Zhou and   
               Dibakar Gope and   
            Matthew Mattina and   
              Ganesh Dasika and   
                      Jesse Beu   Compressing RNNs to Kilobyte Budget for
                                  IoT Devices Using Kronecker Products . . 46:1--46:18
              Victor M. Gan and   
                Yibin Liang and   
                 Lianjun Li and   
                Lingjia Liu and   
                        Yang Yi   A Cost-Efficient Digital ESN
                                  Architecture on FPGA for OFDM Symbol
                                  Detection  . . . . . . . . . . . . . . . 47:1--47:15
               Chuliang Guo and   
                   Li Zhang and   
                  Xian Zhou and   
             Grace Li Zhang and   
                    Bing Li and   
               Weikang Qian and   
                Xunzhao Yin and   
                     Cheng Zhuo   A Reconfigurable Multiplier for Signed
                                  Multiplications with Asymmetric
                                  Bit-Widths . . . . . . . . . . . . . . . 48:1--48:16
           Dharanidhar Dang and   
Sai Vineel Reddy Chittamuru and   
            Sudeep Pasricha and   
             Rabi Mahapatra and   
                 Debashis Sahoo   BPLight-CNN: a Photonics-Based
                                  Backpropagation Accelerator for Deep
                                  Learning . . . . . . . . . . . . . . . . 49:1--49:26
                    He Wang and   
    Nicoleta Cucu Laurenciu and   
                Yande Jiang and   
                 Sorin Cotofana   Graphene-Based Artificial Synapses with
                                  Tunable Plasticity . . . . . . . . . . . 50:1--50:21
                  Qing Yang and   
                Jiachen Mao and   
               Zuoguan Wang and   
               ``Helen'' Li Hai   Dynamic Regularization on Activation
                                  Sparsity for Neural Network Efficiency
                                  Improvement  . . . . . . . . . . . . . . 51:1--51:16
                  Sumon Dey and   
                  Lee Baker and   
             Joshua Schabel and   
                   Weifu Li and   
                Paul D. Franzon   A Scalable Cluster-based Hierarchical
                                  Hardware Accelerator for a Cortically
                                  Inspired Algorithm . . . . . . . . . . . 52:1--52:29
       Bruno Henrique Meyer and   
Aurora Trinidad Ramirez Pozo and   
           Wagner M. Nunan Zola   Improving Barnes--Hut $t$-SNE Algorithm
                                  in Modern GPU Architectures with Random
                                  Forest KNN and Simulated Wide-Warp . . . 53:1--53:26
                Wentao Chen and   
                Hailong Qiu and   
                Jian Zhuang and   
              Chutong Zhang and   
                      Yu Hu and   
                    Qing Lu and   
              Tianchen Wang and   
                   Yiyu Shi and   
              Meiping Huang and   
                      Xiaowe Xu   Quantization of Deep Neural Networks for
                                  Accurate Edge Computing  . . . . . . . . 54:1--54:11
                Serena Wang and   
                 Maya Gupta and   
                    Seungil You   Quit When You Can: Efficient Evaluation
                                  of Ensembles by Optimized Ordering . . . 55:1--55:20
          Md Musabbir Adnan and   
     Sagarvarma Sayyaparaju and   
            Samuel D. Brown and   
     Mst Shamim Ara Shawkat and   
       Catherine D. Schuman and   
                Garrett S. Rose   Design of a Robust Memristive Spiking
                                  Neuromorphic System with Unsupervised
                                  Learning in Hardware . . . . . . . . . . 56:1--56:26
            Mahmoud Masadeh and   
        Yassmeen Elderhalli and   
                Osman Hasan and   
                  Sofiene Tahar   A Quality-assured Approximate Hardware
                                  Accelerators-based on Machine Learning
                                  and Dynamic Partial Reconfiguration  . . 57:1--57:19
                  Xiaowe Xu and   
               Jiawei Zhang and   
                Jinglan Liu and   
                 Yukun Ding and   
              Tianchen Wang and   
                Hailong Qiu and   
                Haiyun Yuan and   
                Jian Zhuang and   
                    Wen Xie and   
                 Yuhao Dong and   
                Qianjun Jia and   
              Meiping Huang and   
                       Yiyu Shi   Multi-Cycle-Consistent Adversarial
                                  Networks for Edge Denoising of Computed
                                  Tomography Images  . . . . . . . . . . . 58:1--58:16
                Shijun Gong and   
                  Jiajun Li and   
                  Wenyan Lu and   
                 Guihai Yan and   
                     Xiaowei Li   ShuntFlowPlus: an Efficient and Scalable
                                  Dataflow Accelerator Architecture for
                                  Stream Applications  . . . . . . . . . . 59:1--59:24
                    Wen Xie and   
                 Zeyang Yao and   
                  Erchao Ji and   
                Hailong Qiu and   
                 Zewen Chen and   
                Huiming Guo and   
                Jian Zhuang and   
                Qianjun Jia and   
                  Meiping Huang   Artificial Intelligence-based Computed
                                  Tomography Processing Framework for
                                  Surgical Telementoring of Congenital
                                  Heart Disease  . . . . . . . . . . . . . 60:1--60:24
             Febin P. Sunny and   
           Ebadollah Taheri and   
              Mahdi Nikdast and   
                Sudeep Pasricha   A Survey on Silicon Photonics for Deep
                                  Learning . . . . . . . . . . . . . . . . 61:1--61:57
           Ulbert J. Botero and   
              Ronald Wilson and   
                 Hangwei Lu and   
        Mir Tanjidur Rahman and   
        Mukhil A. Mallaiyan and   
              Fatemeh Ganji and   
         Navid Asadizanjani and   
        Mark M. Tehranipoor and   
           Damon L. Woodard and   
                  Domenic Forte   Hardware Trust and Assurance through
                                  Reverse Engineering: a Tutorial and
                                  Outlook from Image Analysis and Machine
                                  Learning Perspectives  . . . . . . . . . 62:1--62:53
                Shihao Song and   
              Jui Hanamshet and   
             Adarsha Balaji and   
                   Anup Das and   
        Jeffrey L. Krichmar and   
              Nikil D. Dutt and   
        Nagarajan Kandasamy and   
               Francky Catthoor   Dynamic Reliability Management in
                                  Neuromorphic Computing . . . . . . . . . 63:1--63:27


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 18, Number 1, January, 2022

          Saraju P. Mohanty and   
            Jim Plusquellic and   
            Garrett S. Rose and   
                  Wei Zhang and   
               Maria K. Michael   Introduction to the Special Issue on
                                  Hardware-Assisted Security for Emerging
                                  Internet of Things . . . . . . . . . . . 1:1--1:3
              Nick Roessler and   
             André DeHon   SCALPEL: Exploring the Limits of
                                  Tag-enforced Compartmentalization  . . . 2:1--2:28
                Solon Falas and   
   Charalambos Konstantinou and   
               Maria K. Michael   A Modular End-to-End Framework for
                                  Secure Firmware Updates on Embedded
                                  Systems  . . . . . . . . . . . . . . . . 3:1--3:19
               Josef Danial and   
                Debayan Das and   
              Anupam Golder and   
              Santosh Ghosh and   
        Arijit Raychowdhury and   
                    Shreyas Sen   EM-X-DL: Efficient Cross-device Deep
                                  Learning Side-channel Attack With Noisy
                                  EM Signatures  . . . . . . . . . . . . . 4:1--4:17
             David Thompson and   
                     Haibo Wang   Integrated Power Signature Generation
                                  Circuit for IoT Abnormality Detection    5:1--5:13
      Abdelrahman Elkanishy and   
              Paul M. Furth and   
          Derrick T. Rivera and   
         Abdel-Hameed A. Badawy   Low-overhead Hardware Supervision for
                                  Securing an IoT Bluetooth-enabled
                                  Device: Monitoring Radio Frequency and
                                  Supply Voltage . . . . . . . . . . . . . 6:1--6:28
           Georgios Fragkos and   
             Cyrus Minwalla and   
   Eirini Eleni Tsiropoulou and   
                Jim Plusquellic   Enhancing Privacy in PUF-Cash through
                                  Multiple Trusted Third Parties and
                                  Reinforcement Learning . . . . . . . . . 7:1--7:26
             Carson Labrado and   
         Himanshu Thapliyal and   
              Saraju P. Mohanty   Fortifying Vehicular Security through
                                  Low Overhead Physically Unclonable
                                  Functions  . . . . . . . . . . . . . . . 8:1--8:18
      Mahabub Hasan Mahalat and   
          Dipankar Karmakar and   
             Anindan Mondal and   
                    Bibhash Sen   PUF based Secure and Lightweight
                                  Authentication and Key-Sharing Scheme
                                  for Wireless Sensor Network  . . . . . . 9:1--9:23
               Robert Wille and   
                 Rolf Drechsler   Introduction to the Special Issue on
                                  Design Automation for Quantum Computing  10:1--10:2
               Mario Simoni and   
    Giovanni Amedeo Cirillo and   
           Giovanna Turvani and   
       Mariagrazia Graziano and   
               Maurizio Zamboni   Towards Compact Modeling of Noisy
                                  Quantum Computers: a
                                  Molecular-Spin-Qubit Case of Study . . . 11:1--11:26
Evandro Chagas Ribeiro Da Rosa and   
             Rafael De Santiago   Ket Quantum Programming  . . . . . . . . 12:1--12:25
               N. Khammassi and   
                  I. Ashraf and   
              J. V. Someren and   
                    R. Nane and   
                 A. M. Krol and   
                  M. A. Rol and   
                     L. Lao and   
                 K. Bertels and   
                C. G. Almudever   \pkgOpenQL: a Portable Quantum
                                  Programming Framework for Quantum
                                  Accelerators . . . . . . . . . . . . . . 13:1--13:24
             Nikita Acharya and   
           Miroslav Urbanek and   
            Wibe A. De Jong and   
            Samah Mohamed Saeed   Test Points for Online Monitoring of
                                  Quantum Circuits . . . . . . . . . . . . 14:1--14:19
                Jianhui Han and   
                  Xiang Fei and   
                 Zhaolin Li and   
                   Youhui Zhang   Polyhedral-Based Compilation Framework
                                  for In-Memory Neural Network
                                  Accelerators . . . . . . . . . . . . . . 15:1--15:23
        Hassnaa El-Derhalli and   
        Léa Constans and   
   Sébastien Le Beux and   
           Alfredo De Rossi and   
            Fabrice Raineri and   
                Sofi\`ene Tahar   Towards All-optical Stochastic Computing
                                  Using Photonic Crystal Nanocavities  . . 16:1--16:25
                   Weifu Li and   
               Paul Franzon and   
                  Sumon Dey and   
                 Joshua Schabel   Hardware Implementation of Hierarchical
                                  Temporal Memory Algorithm  . . . . . . . 17:1--17:23
        Dwaipayan Choudhury and   
    Aravind Sukumaran Rajam and   
        Ananth Kalyanaraman and   
            Partha Pratim Pande   High-Performance and Energy-Efficient
                                  $3$D Manycore GPU Architecture for
                                  Accelerating Graph Analytics . . . . . . 18:1--18:19
   Sébastien Thuries and   
              Aida Todri-Sanial   Introduction to the Special Issue on
                                  Monolithic $3$D: Technology, Design and
                                  Computing Systems Applications
                                  Perspectives . . . . . . . . . . . . . . 19:1--19:3
                 Edward Lee and   
                Daehyun Kim and   
                 Jinwoo Kim and   
               Sung Kyu Lim and   
            Saibal Mukhopadhyay   A ReRAM Memory Compiler for Monolithic
                                  $3$D Integrated Circuits in a Carbon
                                  Nanotube Process . . . . . . . . . . . . 20:1--20:20
                Lingjun Zhu and   
            Arjun Chaudhuri and   
          Sanmitra Banerjee and   
           Gauthaman Murali and   
       Pruek Vanna-Iampikul and   
     Krishnendu Chakrabarty and   
                   Sung Kyu Lim   Design Automation and Test Solutions for
                                  Monolithic $3$D ICs  . . . . . . . . . . 21:1--21:49
            Arjun Chaudhuri and   
          Sanmitra Banerjee and   
                 Jinwoo Kim and   
               Heechun Park and   
               Bon Woong Ku and   
           Sukeshwar Kannan and   
     Krishnendu Chakrabarty and   
                   Sung Kyu Lim   Built-in Self-Test and Fault
                                  Localization for Inter-Layer Vias in
                                  Monolithic $3$D ICs  . . . . . . . . . . 22:1--22:37
          Javad Bagherzadeh and   
            Aporva Amarnath and   
                 Jielun Tan and   
              Subhankar Pal and   
           Ronald G. Dreslinski   A Holistic Solution for Reliability of
                                  $3$D Parallel Systems  . . . . . . . . . 23:1--23:27

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 18, Number 2, April, 2022

                   Yiyu Shi and   
                Yongpan Liu and   
                Jianxu Chen and   
                    Steve Jiang   Guest Editorial: ACM JETC Special Issue
                                  on Hardware-Aware Learning for Medical
                                  Applications . . . . . . . . . . . . . . 24:1--24:3
                Weijia Wang and   
                       Bill Lin   Optimizing $3$D U-Net-based Brain Tumor
                                  Segmentation with Integer-arithmetic
                                  Deep Learning Accelerators . . . . . . . 25:1--25:16
               Suraj Mishra and   
              Danny Z. Chen and   
                   X. Sharon Hu   Image Complexity Guided Network
                                  Compression for Biomedical Image
                                  Segmentation . . . . . . . . . . . . . . 26:1--26:23
                 Yufei Chen and   
                 Tingtao Li and   
              Qinming Zhang and   
                    Wei Mao and   
                   Nan Guan and   
                   Mei Tian and   
                     Hao Yu and   
                     Cheng Zhuo   ANT-UNet: Accurate and Noise-Tolerant
                                  Segmentation for Pathology Image
                                  Processing . . . . . . . . . . . . . . . 27:1--27:17
                   Dawei Li and   
                  Yang Zhou and   
               Shaopin Chen and   
                     Xiaowei Xu   A Quasi-digital QPSK Modulator Design
                                  for Biomedical Devices . . . . . . . . . 28:1--28:16
               Yongan Zhang and   
                Anton Banta and   
                 Yonggan Fu and   
            Mathews M. John and   
               Allison Post and   
               Mehdi Razavi and   
           Joseph Cavallaro and   
            Behnaam Aazhang and   
                    Yingyan Lin   RT-RCG: Neural Network and Accelerator
                                  Search Towards Effective and Real-time
                                  ECG Reconstruction from Intracardiac
                                  Electrograms . . . . . . . . . . . . . . 29:1--29:25
           Sourabh Kulkarni and   
        Mario Michael Krell and   
               Seth Nabarro and   
            Csaba Andras Moritz   Hardware-accelerated Simulation-based
                                  Inference of Stochastic Epidemiology
                                  Models for COVID-19  . . . . . . . . . . 30:1--30:24
              Said Hamdioui and   
       Elena-Ioana Vatajelu and   
                  Alberto Bosio   Guest Editorial: Computation-In-Memory
                                  (CIM): from Device to Applications . . . 31:1--31:3
            Mahta Mayahinia and   
             Abhairaj Singh and   
         Christopher Bengel and   
             Stefan Wiefels and   
            Muath A. Lebdeh and   
             Stephan Menzel and   
            Dirk J. Wouters and   
       Anteneh Gebregiorgis and   
           Rajendra Bishnoi and   
                Rajiv Joshi and   
                  Said Hamdioui   A Voltage-Controlled, Oscillation-Based
                                  ADC Design for Computation-in-Memory
                                  Architectures Using Emerging ReRAMs  . . 32:1--32:25
                    Zhe Wan and   
                Tianyi Wang and   
                Yiming Zhou and   
        Subramanian S. Iyer and   
          Vwani P. Roychowdhury   Accuracy and Resiliency of Analog
                                  Compute-in-Memory Inference Engines  . . 33:1--33:23
             Gokul Krishnan and   
            Sumit K. Mandal and   
       Chaitali Chakrabarti and   
                Jae-Sun Seo and   
              Umit Y. Ogras and   
                         Yu Cao   Impact of On-chip Interconnect on
                                  In-memory Acceleration of Deep Neural
                                  Networks . . . . . . . . . . . . . . . . 34:1--34:22
                Yandong Luo and   
                 Panni Wang and   
                     Shimeng Yu   Accelerating On-Chip Training with
                                  Ferroelectric-Based Hybrid Precision
                                  Synapse  . . . . . . . . . . . . . . . . 35:1--35:20
            Alexander Jones and   
                 Aaron Ruen and   
                     Rashmi Jha   A Spiking Neuromorphic Architecture
                                  Using Gated-RRAM for Associative Memory  36:1--36:22
              Saransh Gupta and   
               Mohsen Imani and   
               Joonseop Sim and   
               Andrew Huang and   
                     Fan Wu and   
              Jaeyoung Kang and   
                Yeseong Kim and   
        Tajana Simuni\'c Rosing   COSMO: Computing with Stochastic Numbers
                                  in Memory  . . . . . . . . . . . . . . . 37:1--37:25
               Bon Woong Ku and   
       Catherine D. Schuman and   
          Md Musabbir Adnan and   
           Tiffany M. Mintz and   
             Raphael Pooser and   
       Kathleen E. Hamilton and   
            Garrett S. Rose and   
                   Sung Kyu Lim   Unsupervised Digit Recognition Using
                                  Cosine Similarity In A Neuromemristive
                                  Competitive Learning System  . . . . . . 38:1--38:20
João Paulo Cardoso de Lima and   
         Marcelo Brandalero and   
        Michael Hübner and   
                    Luigi Carro   STAP: an Architecture and Design Tool
                                  for Automata Processing on Memristor
                                  TCAMs  . . . . . . . . . . . . . . . . . 39:1--39:22
                 Maha Kooli and   
             Antoine Heraud and   
       Henri-Pierre Charles and   
             Bastien Giraud and   
               Roman Gauchi and   
              Mona Ezzadeen and   
                Kevin Mambu and   
            Valentin Egloff and   
             Jean-Philippe Noel   Towards a Truly Integrated Vector
                                  Processing Unit for Memory-bound
                                  Applications Based on a Cost-competitive
                                  Computational SRAM Design Solution . . . 40:1--40:26
            Saman Froehlich and   
        Saeideh Shirinzadeh and   
                 Rolf Drechsler   Parallel Computing of Graph-based
                                  Functions in ReRAM . . . . . . . . . . . 41:1--41:24
             Md Adnan Zaman and   
               Rajeev Joshi and   
              Srinivas Katkoori   Early Design Space Exploration Framework
                                  for Memristive Crossbar Arrays . . . . . 42:1--42:26
                Ronny Ronen and   
                 Adi Eliahu and   
          Orian Leitersdorf and   
                Natan Peled and   
           Kunal Korgaonkar and   
       Anupam Chattopadhyay and   
                 Ben Perach and   
               Shahar Kvatinsky   The Bitlet Model: a Parameterized
                                  Analytical Model to Compare PIM and CPU
                                  Systems  . . . . . . . . . . . . . . . . 43:1--43:29

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 18, Number 3, July, 2022

               Mahdi Zahedi and   
            Muah Abu Lebdeh and   
         Christopher Bengel and   
               Dirk Wouters and   
             Stephan Menzel and   
            Manuel Le Gallo and   
              Abu Sebastian and   
               Stephan Wong and   
                  Said Hamdioui   MNEMOSENE: Tile Architecture and
                                  Simulator for Memristor-based
                                  Computation-in-memory  . . . . . . . . . 44:1--44:24
Venkata Sai Praneeth Karempudi and   
                Febin Sunny and   
           Ishan G. Thakkar and   
Sai Vineel Reddy Chittamuru and   
              Mahdi Nikdast and   
                Sudeep Pasricha   Photonic Networks-on-Chip Employing
                                  Multilevel Signaling: a Cross-Layer
                                  Comparative Study  . . . . . . . . . . . 45:1--45:36
           Wassila Lalouani and   
             Mohamed Younis and   
      Mohammad Ebrahimabadi and   
                 Naghmeh Karimi   Countering Modeling Attacks in PUF-based
                                  IoT Security Solutions . . . . . . . . . 46:1--46:28
               Nitin Pundir and   
         Sohrab Aftabjahani and   
          Rosario Cammarota and   
           Mark Tehranipoor and   
             Farimah Farahmandi   Analyzing Security Vulnerabilities
                                  Induced by High-level Synthesis  . . . . 47:1--47:22
             Bodo Rueckauer and   
               Connor Bybee and   
             Ralf Goettsche and   
          Yashwardhan Singh and   
              Joyesh Mishra and   
                   Andreas Wild   NxTF: an API and Compiler for Deep
                                  Spiking Neural Networks on Intel Loihi   48:1--48:22
               Ammar Karkar and   
                Nizar Dahir and   
               Terrence Mak and   
                   Kin-Fai Tong   Thermal and Performance Efficient
                                  On-Chip Surface-Wave Communication for
                                  Many-Core Systems in Dark Silicon Era    49:1--49:18
          Mario Barbareschi and   
           Salvatore Barone and   
              Alberto Bosio and   
                    Jie Han and   
               Marcello Traiola   A Genetic-algorithm-based Approach to
                                  the Design of DCT Hardware Accelerators  50:1--50:25
                Manaar Alam and   
             Sayandeep Saha and   
       Debdeep Mukhopadhyay and   
                   Sandip Kundu   NN-Lock: a Lightweight Authorization to
                                  Prevent IP Threats of Deep Learning
                                  Models . . . . . . . . . . . . . . . . . 51:1--51:19
             Moritz Fieback and   
 Guilherme Cardoso Medeiros and   
                  Lizhou Wu and   
               Hassen Aziza and   
           Rajendra Bishnoi and   
        Mottaqiallah Taouil and   
                  Said Hamdioui   Defects, Fault Modeling, and Test
                                  Development Framework for RRAMs  . . . . 52:1--52:26
               Kevin Volkel and   
              Kyle J. Tomek and   
            Albert J. Keung and   
                  James M. Tuck   DINOS: Data INspired Oligo Synthesis for
                                  DNA Data Storage . . . . . . . . . . . . 53:1--53:35
                Mehmet Ince and   
                Bora Bilgic and   
                      Sule Ozev   Digital Fault-based Built-in Self-test
                                  and Evaluation of Low Dropout Voltage
                                  Regulators . . . . . . . . . . . . . . . 54:1--54:20
                   Yier Jin and   
                Tsung-Yi Ho and   
              Stjepan Picek and   
                 Siddharth Garg   Guest Editorial: Trustworthy AI  . . . . 55:1--55:3
                 Anuj Dubey and   
          Rosario Cammarota and   
              Vikram Suresh and   
                     Aydin Aysu   Guarding Machine Learning Hardware
                                  Against Physical Side-channel Attacks    56:1--56:31
               Brooks Olney and   
                   Robert Karam   Diverse, Neural Trojan Resilient
                                  Ecosystem of Neural Network IP . . . . . 57:1--57:23
                      Ge Li and   
               Mohit Tiwari and   
              Michael Orshansky   Power-based Attacks on Spatial DNN
                                  Accelerators . . . . . . . . . . . . . . 58:1--58:18
               Po-Hao Huang and   
                Honggang Yu and   
                 Max Panoff and   
                  Ting-Chi Wang   Generation of Black-box Audio
                                  Adversarial Examples Based on Gradient
                                  Approximation and Autoencoders . . . . . 59:1--59:19
              Tianjin Huang and   
            Vlado Menkovski and   
                 Yulong Pei and   
                 Yuhao Wang and   
             Mykola Pechenizkiy   Direction-aggregated Attack for
                                  Transferable Adversarial Examples  . . . 60:1--60:22
                   Yuan Liu and   
                Jinxin Dong and   
                 Pingqiang Zhou   Defending against Adversarial Attacks in
                                  Deep Learning with Robust Auxiliary
                                  Classifiers Utilizing Bit-plane Slicing  61:1--61:17
                 Max Panoff and   
                Honggang Yu and   
                 Haoqi Shan and   
                       Yier Jin   A Review and Comparison of AI-enhanced
                                  Side Channel Analysis  . . . . . . . . . 62:1--62:20

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 18, Number 4, October, 2022

               Vanessa Chen and   
        Mohammad AL Faruque and   
                   Fadi Kurdahi   Guest Editorial: Secure Radio-Frequency
                                  (RF)-Analog Electronics and
                                  Electromagnetics . . . . . . . . . . . . 63:1--63:??
        Alireza Nooraiepour and   
   Shaghayegh Vosoughitabar and   
       Chung-Tse Michael Wu and   
            Waheed U. Bajwa and   
            Narayan B. Mandayam   Time-varying Metamaterial-enabled
                                  Directional Modulation Schemes for
                                  Physical Layer Security in Wireless
                                  Communication Links  . . . . . . . . . . 64:1--64:??
          Tahoura Mosavirik and   
              Fatemeh Ganji and   
          Patrick Schaumont and   
                   Shahin Tajik   \pkgScatterVerif: Verification of
                                  Electronic Boards Using Reflection
                                  Response of Power Distribution Network   65:1--65:??
                Arslan Riaz and   
                 Dylan Nash and   
               Jonathan Ngo and   
            Chiraag Juvekar and   
             Phillip Nadeau and   
                     Tao Yu and   
          Rabia Tugce Yazicigil   Security Assessment of Phase-Based
                                  Ranging Systems in a Multipath
                                  Environment  . . . . . . . . . . . . . . 66:1--66:??
             Maitreyi Ashok and   
          Matthew J. Turner and   
        Ronald L. Walsworth and   
            Edlyn V. Levine and   
        Anantha P. Chandrakasan   Hardware Trojan Detection Using
                                  Unsupervised Deep Learning on Quantum
                                  Diamond Microscope Magnetic Field Images 67:1--67:??
              Jeong-Jun Lee and   
               Wenrui Zhang and   
                   Yuan Xie and   
                        Peng Li   SaARSP: an Architecture for
                                  Systolic-Array Acceleration of Recurrent
                                  Spiking Neural Networks  . . . . . . . . 68:1--68:??
          Mohsen Riahi Alam and   
           M. Hassan Najafi and   
               Nima Taherinejad   Sorting in Memristive Memory . . . . . . 69:1--69:??
          Dilip Kumar Maity and   
          Surajit Kumar Roy and   
                   Chandan Giri   A Cost-Effective Built-In Self-Test
                                  Mechanism for Post-Manufacturing TSV
                                  Defects in $3$D ICs  . . . . . . . . . . 70:1--70:??
                 Kangwei Xu and   
             Dongrong Zhang and   
                  Qiang Ren and   
             Yuanqing Cheng and   
                 Patrick Girard   All-spin PUF: an Area-efficient and
                                  Reliable PUF Design with Signature
                                  Improvement for Spin-transfer Torque
                                  Magnetic Cell-based All-spin Circuits    71:1--71:??
       N. Nalla Anandakumar and   
         Mohammad S. Hashmi and   
         Somitra Kumar Sanadhya   Design and Analysis of FPGA-based PUFs
                                  with Enhanced Performance for
                                  Hardware-oriented Security . . . . . . . 72:1--72:??
             Simone Ruffini and   
               Luca Caronti and   
       Kasim Sinan Yildirim and   
                Davide Brunelli   NORM: an FPGA-based Non-volatile Memory
                                  Emulation Framework for Intermittent
                                  Computing  . . . . . . . . . . . . . . . 73:1--73:??
     Yavar Safaei Mehrabani and   
   Samaneh Goldani Gigasari and   
           Mohammad Mirzaei and   
            Hamidreza Uoosefian   A Novel Highly-Efficient Inexact Full
                                  Adder Cell for Motion and Edge Detection
                                  Systems of Image Processing in CNFET
                                  Technology . . . . . . . . . . . . . . . 74:1--74:??
                 Yulhwa Kim and   
               Hyungjun Kim and   
                   Jae-Joon Kim   Extreme Partial-Sum Quantization for
                                  Analog Computing-In-Memory Neural
                                  Network Accelerators . . . . . . . . . . 75:1--75:??
                Haiyang Han and   
            Theoni Alexoudi and   
             Chris Vagionas and   
               Nikos Pleros and   
              Nikos Hardavellas   A Practical Shared Optical Cache With
                                  Hybrid MWSR/R-SWMR NoC for Multicore
                                  Processors . . . . . . . . . . . . . . . 76:1--76:??
              Meysam Zaeemi and   
               Siamak Mohammadi   High-level Modeling and Verification
                                  Platform for Elastic Circuits with
                                  Process Variation Considerations . . . . 77:1--77:??
             Amal Thomas K. and   
           Soumyajit Poddar and   
           Hemanta Kumar Mondal   A CNN Hardware Accelerator Using
                                  Triangle-based Convolution . . . . . . . 78:1--78:??
       Anteneh Gebregiorgis and   
        Hoang Anh Du Nguyen and   
                  Jintao Yu and   
           Rajendra Bishnoi and   
        Mottaqiallah Taouil and   
           Francky Catthoor and   
                  Said Hamdioui   A Survey on Memory-centric Computer
                                  Architectures  . . . . . . . . . . . . . 79:1--79:??
                     You Wu and   
                         Lin Li   \pkgZallocator: a High Throughput
                                  Write-Optimized Persistent Allocator for
                                  Non-Volatile Memory  . . . . . . . . . . 80:1--80:??
                Jiaxin Peng and   
            Yousra Alkabani and   
                Krunal Puri and   
                Xiaoxuan Ma and   
              Volker Sorger and   
               Tarek El-Ghazawi   A Deep Neural Network Accelerator using
                                  Residue Arithmetic in a Hybrid
                                  Optoelectronic System  . . . . . . . . . 81:1--81:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 19, Number 1, January, 2023

                Yuri Ardesi and   
           Umberto Garlando and   
            Fabrizio Riente and   
           Giuliana Beretta and   
         Gianluca Piccinini and   
           Mariagrazia Graziano   Taming Molecular Field-Coupling for
                                  Nanocomputing Design . . . . . . . . . . 1:1--1:??
             Prerana Samant and   
         Naveen Kumar Macha and   
              Mostafizur Rahman   A Neoteric Approach for Logic with
                                  Embedded Memory Leveraging Crosstalk
                                  Computing  . . . . . . . . . . . . . . . 2:1--2:??
              Freddy Forero and   
             Victor Champac and   
                Michel Renovell   B-open Defect: a Novel Defect Model in
                                  FinFET Technology  . . . . . . . . . . . 3:1--3:??
         Farimah Farahmandi and   
           Ankur Srivastava and   
          Giorgio Di Natale and   
               Mark Tehranipoor   Introduction to the Special Issue on CAD
                                  for Security: Pre-silicon Security
                                  Sign-off Solutions Through Design Cycle  4:1--4:??
        Alvaro Cintas Canto and   
   Mehran Mozaffari Kermani and   
              Reza Azarderakhsh   Reliable Constructions for the Key
                                  Generator of Code-based Post-quantum
                                  Cryptosystems on FPGA  . . . . . . . . . 5:1--5:??
               Ferhat Erata and   
                Shuwen Deng and   
            Faisal Zaghloul and   
               Wenjie Xiong and   
                 Onur Demir and   
                   Jakub Szefer   Survey of Approaches and Techniques for
                                  Security Verification of Computer
                                  Systems  . . . . . . . . . . . . . . . . 6:1--6:??
           Mojan Javaheripi and   
             Jung-Woo Chang and   
             Farinaz Koushanfar   AccHashtag: Accelerated Hashing for
                                  Detecting Fault-Injection Attacks on
                                  Embedded Neural Networks . . . . . . . . 7:1--7:??
           Hasini Witharana and   
             Aruna Jayasena and   
             Andrew Whigham and   
                 Prabhat Mishra   Automated Generation of Security
                                  Assertions for RTL Models  . . . . . . . 8:1--8:??
               Kazuki Monta and   
                   Lang Lin and   
                  Jimin Wen and   
           Harsh Shrivastav and   
                Calvin Chow and   
                   Hua Chen and   
                 Joao Geada and   
           Sreeja Chowdhury and   
               Nitin Pundir and   
               Norman Chang and   
                  Makoto Nagata   Silicon-correlated Simulation
                                  Methodology of EM Side-channel Leakage
                                  Analysis . . . . . . . . . . . . . . . . 9:1--9:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 19, Number 2, April, 2023

              Dipojjwal Ray and   
               Yogendra Sao and   
             Santosh Biswas and   
                  Sk Subidh Ali   On Securing Cryptographic ICs against
                                  Scan-based Attacks: a Hamming Weight
                                  Distribution Perspective . . . . . . . . 10:1--10:??
    B. M. S. Bahar Talukder and   
              Farah Ferdaus and   
             Md Tauhidur Rahman   A Noninvasive Technique to Detect
                                  Authentic/Counterfeit SRAM Chips . . . . 11:1--11:??
           Saswat Kumar Ram and   
      Sauvagya Ranjan Sahoo and   
          Banee Bandana Das and   
      Kamalakanta Mahapatra and   
              Saraju P. Mohanty   Eternal-thing 2.0:
                                  Analog-Trojan-resilient Ripple-less
                                  Solar Harvesting System for Sustainable
                                  IoT  . . . . . . . . . . . . . . . . . . 12:1--12:??
               Xiangru Chen and   
             Maneesh Merugu and   
                Jiaqi Zhang and   
                     Sandip Ray   AroMa: Evaluating Deep Learning Systems
                                  for Stealthy Integrity Attacks on
                                  Multi-tenant Accelerators  . . . . . . . 13:1--13:??
               Mingdai Yang and   
                 Qiuwen Lou and   
               Ramin Rajaei and   
        Mohammad Reza Jokar and   
                  Junyi Qiu and   
                 Yuming Liu and   
                Aditi Udupa and   
          Frederic T. Chong and   
         John M. Dallesasse and   
                Milton Feng and   
         Lynford L. Goddard and   
               X. Sharon Hu and   
                     Yanjing Li   A Hybrid Optical-Electrical Analog Deep
                                  Learning Accelerator Using Incoherent
                                  Optical Signals  . . . . . . . . . . . . 14:1--14:??
                      Yu Ma and   
              Linfeng Zheng and   
                 Pingqiang Zhou   A Mapping Method Tolerating SAF and
                                  Variation for Memristor Crossbar Array
                                  Based Neural Network Inference on Edge
                                  Devices  . . . . . . . . . . . . . . . . 15:1--15:??
               Siyuan Huang and   
           Brian D. Hoskins and   
         Matthew W. Daniels and   
             Mark D. Stiles and   
                   Gina C. Adam   Low-Rank Gradient Descent for
                                  Memory-Efficient Training of Deep
                                  In-Memory Arrays . . . . . . . . . . . . 16:1--16:??
            Nathan Jessurun and   
    Olivia P. Dizon-Paradis and   
             Jacob Harrison and   
               Shajib Ghosh and   
        Mark M. Tehranipoor and   
           Damon L. Woodard and   
             Navid Asadizanjani   FPIC: a Novel Semantic Dataset for
                                  Optical PCB Assurance  . . . . . . . . . 17:1--17:??
Troya Çagil Köylü and   
Cezar Rodolfo Wedig Reinbrecht and   
       Anteneh Gebregiorgis and   
              Said Hamdioui and   
            Mottaqiallah Taouil   A Survey on Machine Learning in Hardware
                                  Security . . . . . . . . . . . . . . . . 18:1--18:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 19, Number 3, July, 2023

              Amlan Ganguly and   
       Salvatore Monteleone and   
           Diana Goehringer and   
               Cristinel Ababei   Guest Editors Introduction: Special
                                  Issue on Network-on-Chip Architectures
                                  of the Future (NoCArc) . . . . . . . . . 19:1--19:??
      Sidhartha Sankar Rout and   
               Mitali Sinha and   
                      Sujay Deb   $2$DMAC: a Sustainable and Efficient
                                  Medium Access Control Mechanism for
                                  Future Wireless NoCs . . . . . . . . . . 20:1--20:??
                  Usman Ali and   
 Sheikh Abdul Rasheed Sahni and   
                      Omer Khan   Characterization of Timing-based
                                  Software Side-channel Attacks and
                                  Mitigations on Network-on-Chip Hardware  21:1--21:??
             Ahmad Patooghy and   
           Mahdi Hasanzadeh and   
                Amin Sarihi and   
         Mostafa Abdelrehim and   
         Abdel-Hameed A. Badawy   Securing Network-on-chips Against
                                  Fault-injection and Crypto-analysis
                                  Attacks via Stochastic Anonymous Routing 22:1--22:??
               Md Farhadur Reza   Machine Learning Enabled Solutions for
                                  Design and Optimization Challenges in
                                  Networks-on-Chip based Multi/Many-Core
                                  Architectures  . . . . . . . . . . . . . 23:1--23:??
        Md. Mahfuz Al Hasan and   
   Mohammad Tahsin Mostafiz and   
               Thomas An Le and   
                 Jake Julia and   
           Nidish Vashistha and   
              Shayan Taheri and   
             Navid Asadizanjani   EVHA: Explainable Vision System for
                                  Hardware Testing and Assurance --- an
                                  Overview . . . . . . . . . . . . . . . . 24:1--24:??
             Pravin Gaikwad and   
              Jonathan Cruz and   
      Prabuddha Chakraborty and   
              Swarup Bhunia and   
                 Tamzidul Hoque   Hardware IP Assurance against Trojan
                                  Attacks with Machine Learning and
                                  Post-processing  . . . . . . . . . . . . 25:1--25:??
           Douglas Densmore and   
          Nathan J. Hillson and   
               Eric Klavins and   
                Chris Myers and   
               Jean Peccoud and   
         Giovanni Stracquadanio   Introduction to the Special Issue on
                                  BioFoundries and Cloud Laboratories  . . 26:1--26:??
              Caleb Winston and   
                Max Willsey and   
                      Luis Ceze   Virtualizing Existing Fluidic Programs   27:1--27:??
              Bryan Bartley and   
                 Jacob Beal and   
               Miles Rogers and   
               Daniel Bryce and   
          Robert P. Goldman and   
            Benjamin Keller and   
                  Peter Lee and   
            Vanessa Biggers and   
               Joshua Nowak and   
                    Mark Weston   Building an Open Representation for
                                  Biological Protocols . . . . . . . . . . 28:1--28:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 19, Number 4, October, 2023

             Anindan Mondal and   
            Debasish Kalita and   
            Archisman Ghosh and   
             Suchismita Roy and   
                    Bibhash Sen   Toward the Generation of Test Vectors
                                  for the Detection of Hardware Trojan
                                  Targeting Effective Switching Activity   29:1--29:??
           Cansu Demirkiran and   
                Furkan Eris and   
                Gongyu Wang and   
          Jonathan Elmhurst and   
                 Nick Moore and   
         Nicholas C. Harris and   
            Ayon Basumallik and   
         Vijay Janapa Reddi and   
                 Ajay Joshi and   
                Darius Bunandar   An Electro-Photonic System for
                                  Accelerating Deep Neural Networks  . . . 30:1--30:??
                   John Kim and   
                 Tushar Krishna   Introduction to the Special Issue on
                                  Next-Generation On-Chip and Off-Chip
                                  Communication Architectures for Edge,
                                  Cloud and HPC  . . . . . . . . . . . . . 31:1--31:??
Francisco Muñoz-Martínez and   
José L. Abellán and   
           Manuel E. Acacio and   
                 Tushar Krishna   STIFT: a Spatio-Temporal Integrated
                                  Folding Tree for Efficient Reductions in
                                  Flexible DNN Accelerators  . . . . . . . 32:1--32:??
                Sachin Bhat and   
                  Mingyu Li and   
           Sourabh Kulkarni and   
            Csaba Andras Moritz   SkyBridge 2.0: a Fine-grained Vertical
                                  $3$D-IC Technology for Future ICs  . . . 33:1--33:??
        David Selasi Koblah and   
           Ulbert J. Botero and   
           Sean P. Costello and   
    Olivia P. Dizon-Paradis and   
              Fatemeh Ganji and   
           Damon L. Woodard and   
                  Domenic Forte   A Fast Object Detection-Based Framework
                                  for Via Modeling on PCB X-Ray CT Images  34:1--34:??


ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 20, Number 1, January, 2024

              Ikenna Okafor and   
  Akshay Krishna Ramanathan and   
Nagadastagiri Reddy Challapalle and   
                   Zheyu Li and   
        Vijaykrishnan Narayanan   Fusing In-storage and Near-storage
                                  Acceleration of Convolutional Neural
                                  Networks . . . . . . . . . . . . . . . . 1:1--1:??
          Soyed Tuhin Ahmed and   
            Mahta Mayahinia and   
         Michael Hefenbrock and   
     Christopher Münch and   
               Mehdi B. Tahoori   Design-time Reference Current Generation
                                  for Robust Spintronic-based Neuromorphic
                                  Architecture . . . . . . . . . . . . . . 2:1--2:??
                 Sourav Roy and   
             Dipnarayan Das and   
                    Bibhash Sen   Secure and Lightweight Authentication
                                  Protocol Using PUF for the IoT-based
                                  Wireless Sensor Network  . . . . . . . . 3:1--3:??
                Omais Shafi and   
     Mohammad Khalid Pandit and   
             Amarjeet Saini and   
  Gayathri Ananthanarayanan and   
                  Rijurekha Sen   Repercussions of Using DNN Compilers on
                                  Edge GPUs for Real Time and Safety
                                  Critical Systems: a Quantitative Audit   4:1--4:??
             Fabiha Nowshin and   
                  Hongyu An and   
                        Yang Yi   Towards Energy-Efficient Spiking Neural
                                  Networks: a Robust Hybrid
                                  CMOS-Memristive Accelerator  . . . . . . 5:1--5:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 20, Number 2, April, 2024

Venkata Sai Praneeth Karempudi and   
             Janibul Bashir and   
               Ishan G. Thakkar   An Analysis of Various Design Pathways
                                  Towards Multi-Terabit Photonic
                                  On-Interposer Interconnects  . . . . . . 6:1--6:??
 Patricia Gonzalez-Guerrero and   
                 Kylie Huch and   
           Nirmalendu Patra and   
              Thom Popovici and   
        George Michelogiannakis   Toward Practical Superconducting
                                  Accelerators for Machine Learning Using
                                  U-SFQ  . . . . . . . . . . . . . . . . . 7:1--7:??

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume 20, Number 3, July, 2024

           Cristian Tirelli and   
               Juan Sapriza and   
Rubén Rodríguez Álvarez and   
           Lorenzo Ferretti and   
        Beno\^\it Denkinger and   
          Giovanni Ansaloni and   
 José Miranda Calero and   
              David Atienza and   
                    Laura Pozzi   SAT-Based Exact Modulo Scheduling
                                  Mapping for Resource-Constrained CGRAs   8:1--8:??
              Benjamin Bean and   
             Cyrus Minwalla and   
   Eirini Eleni Tsiropoulou and   
                Jim Plusquellic   PUF-based Digital Money with
                                  Propagation-of-Provenance and Offline
                                  Transfers between Two Parties  . . . . . 9:1--9:??
                   Ziwen Li and   
                      Yu Ma and   
               Jindong Zhou and   
                 Pingqiang Zhou   Spiking-NeRF: Spiking Neural Network for
                                  Energy-Efficient Neural Rendering  . . . 10:1--10:??
          Morteza Amouzegar and   
        Morteza Rezaalipour and   
             Masoud Dehyadegari   Genetic Cache: a Machine Learning
                                  Approach to Designing DRAM Cache
                                  Controllers in HBM Systems . . . . . . . 11:1--11:??