Table of contents for issues of ACM Transactions on Design Automation of Electronic Systems

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Volume 1, Number 1, January, 1996
Volume 1, Number 2, April, 1996
Volume 1, Number 3, July, 1996
Volume 1, Number 4, October, 1996
Volume 2, Number 1, January, 1997
Volume 2, Number 2, January, 1997
Volume 2, Number 3, January, 1997
Volume 2, Number 4, January, 1997
Volume 3, Number 1, January, 1998
Volume 3, Number 2, April, 1998
Volume 3, Number 3, July, 1998
Volume 3, Number 4, October, 1998
Volume 4, Number 1, January, 1999
Volume 4, Number 2, April, 1999
Volume 4, Number 3, July, 1999
Volume 4, Number 4, October, 1999
Volume 5, Number 1, January, 2000
Volume 5, Number 2, January, 2000
Volume 5, Number 3, January, 2000
Volume 5, Number 4, January, 2000
Volume 6, Number 1, April, 2001
Volume 6, Number 2, January, 2001
Volume 6, Number 3, July, 2001
Volume 6, Number 4, October, 2001
Volume 7, Number 1, January, 2002
Volume 7, Number 2, April, 2002
Volume 7, Number 3, July, 2002
Volume 7, Number 4, October, 2002
Volume 8, Number 1, January, 2003
Volume 8, Number 2, April, 2003
Volume 8, Number 3, July, 2003
Volume 8, Number 4, October, 2003
Volume 9, Number 1, January, 2004
Volume 9, Number 2, April, 2004
Volume 9, Number 3, July, 2004
Volume 9, Number 4, October, 2004
Volume 10, Number 1, January, 2005
Volume 10, Number 2, April, 2005
Volume 10, Number 3, July, 2005
Volume 10, Number 4, October, 2005
Volume 11, Number 1, January, 2006
Volume 11, Number 2, April, 2006
Volume 11, Number 3, July, 2006
Volume 11, Number 4, October, 2006
Volume 12, Number 1, January, 2007
Volume 12, Number 2, April, 2007
Volume 12, Number 3, August, 2007
Volume 12, Number 4, September, 2007
Volume 13, Number 1, January, 2008
Volume 13, Number 2, April, 2008
Volume 13, Number 3, July, 2008
Volume 13, Number 4, September, 2008
Volume 14, Number 1, January, 2009
Volume 14, Number 2, March, 2009
Volume 14, Number 3, May, 2009
Volume 14, Number 4, August, 2009
Volume 15, Number 1, December, 2009
Volume 15, Number 2, February, 2010
Volume 15, Number 3, May, 2010
Volume 15, Number 4, September, 2010
Volume 16, Number 1, November, 2010
Volume 16, Number 2, March, 2011
Volume 16, Number 3, June, 2011
Volume 16, Number 4, October, 2011
Volume 17, Number 1, January, 2012
Volume 17, Number 2, April, 2012
Volume 17, Number 3, June, 2012
Volume 17, Number 4, October, 2012
Volume 18, Number 1, December, 2012
Volume 18, Number 2, March, 2013
Volume 18, Number 3, July, 2013
Volume 18, Number 4, October, 2013
Volume 19, Number 1, December, 2013
Volume 19, Number 2, March, 2014
Volume 19, Number 3, June, 2014
Volume 19, Number 4, August, 2014
Volume 20, Number 1, November, 2014
Volume 20, Number 2, February, 2015
Volume 20, Number 3, June, 2015
Volume 20, Number 4, September, 2015
Volume 21, Number 1, November, 2015
Volume 21, Number 2, January, 2016
Volume 21, Number 3, July, 2016
Volume 21, Number 4, September, 2016
Volume 22, Number 1, December, 2016
Volume 22, Number 2, March, 2017
Volume 22, Number 3, May, 2017
Volume 22, Number 4, July, 2017
Volume 23, Number 1, October, 2017


ACM Transactions on Design Automation of Electronic Systems
Volume 1, Number 1, January, 1996

                 Massoud Pedram   Power minimization in IC design:
                                  principles and applications  . . . . . . 3--56
           Kwang-Ting Cheng and   
             A. S. Krishnakumar   Automatic generation of functional
                                  vectors using the extended finite state
                                  machine model  . . . . . . . . . . . . . 57--79
              Yao-Wen Chang and   
                 D. F. Wong and   
                     C. K. Wong   Universal switch modules for FPGA design 80--101
          Shashidhar Thakur and   
                     D. F. Wong   Series-parallel functions and FPGA logic
                                  module design  . . . . . . . . . . . . . 102--122
          Venkat Thanvantri and   
                   Sartaj Sahni   Optimal folding of standard and custom
                                  cells  . . . . . . . . . . . . . . . . . 123--143

ACM Transactions on Design Automation of Electronic Systems
Volume 1, Number 2, April, 1996

                 Jason Cong and   
                   Yuzheng Ding   Combinational logic synthesis for LUT
                                  based field programmable gate arrays . . 145--204
     Peter F. A. Middelhoek and   
             Sreeranga P. Rajan   From VHDL to efficient and
                                  first-time-right designs: a formal
                                  approach . . . . . . . . . . . . . . . . 205--250
            David J. Kolson and   
          Alexandru Nicolau and   
                 Nikil Dutt and   
                    Ken Kennedy   Optimal register assignment to loops for
                                  embedded code generation . . . . . . . . 251--279
               S. C. Prasad and   
                         K. Roy   Transistor reordering for power
                                  minimization under delay constraint  . . 280--300

ACM Transactions on Design Automation of Electronic Systems
Volume 1, Number 3, July, 1996

                     Wayne Wolf   Object-oriented cosynthesis of
                                  distributed embedded systems . . . . . . 301--314
              Sue-Hong Chow and   
                Yi-Cheng Ho and   
             TingTing Hwang and   
                      C. L. Liu   Low power realization of finite state
                                  machines --- a decomposition approach    315--340
          Dimitrios Kagaris and   
               Spyros Tragoudas   A fast algorithm for minimizing FPGA
                                  combinational and sequential modules . . 341--351
              En-Shou Chang and   
           Daniel D. Gajski and   
                 Sanjiv Narayan   An optimal clock period selection method
                                  based on slack minimization criteria . . 352--370
             Mario A. Lopez and   
                Dinesh P. Mehta   Efficient decomposition of polygons into
                                  L-shapes with application to VLSI
                                  layouts  . . . . . . . . . . . . . . . . 371--395
                  R. Moreno and   
                 R. Hermida and   
            M. Fernández   Register estimation in unscheduled
                                  dataflow graphs  . . . . . . . . . . . . 396--403

ACM Transactions on Design Automation of Electronic Systems
Volume 1, Number 4, October, 1996

               Kwang-Ting Cheng   Gate-level test generation for
                                  sequential circuits  . . . . . . . . . . 405--442
                M. Langevin and   
                       E. Cerny   A recursive technique for computing
                                  lower-bound performance of schedules . . 443--455
                Rok Sosi\=c and   
                     Jun Gu and   
              Robert R. Johnson   The Unison algorithm: fast evaluation of
                                  Boolean expressions  . . . . . . . . . . 456--477
                 Jason Cong and   
                         Lei He   Optimal wiresizing for interconnects
                                  with multiple sources  . . . . . . . . . 478--511
           Joseph L. Ganley and   
                James P. Cohoon   Rectilinear Steiner trees on a
                                  checkerboard . . . . . . . . . . . . . . 512--522


ACM Transactions on Design Automation of Electronic Systems
Volume 2, Number 1, January, 1997

                  Youn-Long Lin   Recent developments in high-level
                                  synthesis  . . . . . . . . . . . . . . . 2--21
                   Jie Gong and   
           Daniel D. Gajski and   
                   Smita Bakshi   Model refinement for hardware-software
                                  codesign . . . . . . . . . . . . . . . . 22--41
    Dilvan de Abreu Moreira and   
              Les T. Walczowski   AGENTS a distributed client-server
                                  system for leaf cell generation  . . . . 42--61
            Henrik Esbensen and   
                  Ernest S. Kuh   A performance-driven IC/MCM placement
                                  algorithm featuring explicit design
                                  space exploration  . . . . . . . . . . . 62--80

ACM Transactions on Design Automation of Electronic Systems
Volume 2, Number 2, January, 1997

               Yann-Rue Lin and   
          Cheng-Tsung Hwang and   
                 Allen C.-H. Wu   Scheduling techniques for variable
                                  voltage low power designs  . . . . . . . 81--97
                   F. Fummi and   
                  U. Rovati and   
                      D. Sciuto   Functional design for testability of
                                  control-dominated architectures  . . . . 98--122
            Maciek Kormicki and   
              Ausif Mahmood and   
             Bradley S. Carlson   Parallel logic simulation on a network
                                  of workstations using parallel virtual
                                  machine  . . . . . . . . . . . . . . . . 123--134
           Cheng-Hsing Yang and   
             Chia-Chun Tsai and   
                Jan-Ming Ho and   
                   Sao-Jie Chen   Hmap: a fast mapper for EPGAs using
                                  extended GBDD hash tables  . . . . . . . 135--150
                Wai-Kei Mak and   
                     D. F. Wong   Board-level multiterminal net routing
                                  for FPGA-based logic emulation . . . . . 151--167
            Andrew B. Kahng and   
                 Sudhakar Muddu   Analysis of RC interconnections under
                                  ramp input . . . . . . . . . . . . . . . 168--192

ACM Transactions on Design Automation of Electronic Systems
Volume 2, Number 3, January, 1997

                Luca Benini and   
            Giovanni De Micheli   A survey of Boolean matching techniques
                                  for library binding  . . . . . . . . . . 193--226
            Mark C. Johnson and   
                    Kaushik Roy   Datapath scheduling with multiple supply
                                  voltages and level converters  . . . . . 227--248
               Hakan Yalcin and   
                  John P. Hayes   Event propagation conditions in circuit
                                  delay computation  . . . . . . . . . . . 249--280
            Paul Thadikaran and   
        Sreejit Chakravarty and   
                    Janak Patel   Algorithms to compute bridging fault
                                  coverage of IDDQ test sets . . . . . . . 281--305

ACM Transactions on Design Automation of Electronic Systems
Volume 2, Number 4, January, 1997

                     Min Xu and   
                Fadi J. Kurdahi   Layout-driven RTL binding techniques for
                                  high-level synthesis using accurate
                                  estimators . . . . . . . . . . . . . . . 312--343
         Michael Münch and   
               Norbert Wehn and   
                Manfred Glesner   An efficient ILP-based scheduling
                                  algorithm for control-dominated VHDL
                                  descriptions . . . . . . . . . . . . . . 344--364
                  L. Freund and   
                  M. Israel and   
                F. Rousseau and   
         J. M. Bergé and   
                  M. Auguin and   
                C. Belleudy and   
                     G. Gogniat   A codesign experiment in acoustic echo
                                  cancellation GMDF  . . . . . . . . . . . 365--383
        Preeti Ranjan Panda and   
              Nikil D. Dutt and   
              Alexandru Nicolau   Memory data organization for improved
                                  cache performance in embedded processor
                                  applications . . . . . . . . . . . . . . 384--409
          Hiroyuki Tomiyama and   
                 Hiroto Yasuura   Code placement techniques for cache miss
                                  rate reduction . . . . . . . . . . . . . 410--429


ACM Transactions on Design Automation of Electronic Systems
Volume 3, Number 1, January, 1998

              E. W. Johnson and   
                 J. B. Brockman   Measurement and analysis of sequential
                                  design processes . . . . . . . . . . . . 1--20
                 K. Khordoc and   
                       E. Cerny   Semantics and verification of action
                                  diagrams with linear timing  . . . . . . 21--50
                    S. Liao and   
                 K. Keutzer and   
                  S. Tjiang and   
                     S. Devadas   A new viewpoint on code generation for
                                  directed acyclic graphs  . . . . . . . . 51--75
                  C.-J. Shi and   
               J. A. Brzozowski   Cluster-cover a theoretical framework
                                  for a class of VLSI-CAD optimization
                                  problems . . . . . . . . . . . . . . . . 76--107

ACM Transactions on Design Automation of Electronic Systems
Volume 3, Number 2, April, 1998

             Pao-Ann Hsiung and   
           Chung-Hwang Chen and   
              Trong-Yen Lee and   
                   Sao-Jie Chen   ICOS: an intelligent concurrent
                                  object-oriented synthesis methodology
                                  for multiprocessor systems . . . . . . . 109--135
               Guido Araujo and   
                   Sharad Malik   Code generation for fixed-point DSPs . . 136--161
              Giri Tiruvuri and   
                     Moon Chung   Estimation of lower bounds in scheduling
                                  algorithms for high-level synthesis  . . 162--180
                Frank Vahid and   
                 Thuy Dm Le and   
                    Yu-Chin Hsu   Functional partitioning improvements
                                  over structural partitioning for
                                  packaging constraints and synthesis:
                                  tool performance . . . . . . . . . . . . 181--208
             Gernot H. Koch and   
              W. Rosenstiel and   
                   U. Kebschull   Breakpoints and breakpoint detection in
                                  source-level emulation . . . . . . . . . 209--230
             Irith Pomeranz and   
              Sudhakar M. Reddy   Functional test generation for delay
                                  faults in combinational circuits . . . . 231--248
                 X. T. Chen and   
                F. J. Meyer and   
                    F. Lombardi   Structural diagnosis of interconnects by
                                  coloring . . . . . . . . . . . . . . . . 249--271
                Dinesh P. Mehta   Estimating the storage requirements of
                                  the rectangular and L-shaped corner
                                  stitching data structures  . . . . . . . 272--284
     Subhrajit Bhattacharya and   
                  Sujit Dey and   
                  Franc Breglez   Effects of resource sharing on circuit
                                  delay: an assignment algorithm for clock
                                  period optimization  . . . . . . . . . . 285--307

ACM Transactions on Design Automation of Electronic Systems
Volume 3, Number 3, July, 1998

           Gianpiero Cabodi and   
             Paolo Camurati and   
                   Stefano Quer   Auxiliary variables for BDD-based
                                  representation and manipulation of
                                  Boolean functions  . . . . . . . . . . . 309--340
                 Jason Cong and   
            Andrew B. Kahng and   
              Cheng-Kok Koh and   
              C.-W. Albert Tsao   Bounded-skew clock and Steiner routing   341--388
               Wen-Ben Jone and   
                     K. S. Tsai   Confidence analysis for defect-level
                                  estimation of VLSI random testing  . . . 389--407
               Anmol Mathur and   
                 Ali Dasdan and   
                Rajesh K. Gupta   Rate analysis for embedded systems . . . 408--436
                Peichen Pan and   
                      C. L. Liu   Optimal clock period FPGA technology
                                  mapping for sequential circuits  . . . . 437--462
           Michael A. Riepe and   
              Karem A. Sakallah   The edge-based design rule model
                                  revisited  . . . . . . . . . . . . . . . 463--486
                    Alan Su and   
                Yu-Chin Hsu and   
                Ta-Yung Liu and   
            Mike Tien-Chien Lee   Eliminating false loops caused by
                                  sharing in control path  . . . . . . . . 487--495
                   Hai Zhou and   
                     D. F. Wong   Optimal river routing with crosstalk
                                  constraints  . . . . . . . . . . . . . . 496--514

ACM Transactions on Design Automation of Electronic Systems
Volume 3, Number 4, October, 1998

               C. Passerone and   
                  C. Sansoe and   
                 L. Lavagno and   
                  R. McGeer and   
                  J. Martin and   
               R. Passerone and   
     A. Sangiovanni-Vincentelli   Modeling reactive systems in Java  . . . 515--523
                 Li-C. Wang and   
            Magdy S. Abadir and   
                      Jing Zeng   On measuring the effectiveness of
                                  various design validation approaches for
                                  PowerPC microprocessor embedded arrays   524--532
                 Ali Dasdan and   
          Dinesh Ramanathan and   
                Rajesh K. Gupta   A timing-driven design and validation
                                  methodology for embedded real-time
                                  systems  . . . . . . . . . . . . . . . . 533--553
                S. P. Rajan and   
                  M. Fujita and   
                    K. Yuan and   
                    M. T-C. Lee   ATM switch design by high-level
                                  modeling, formal verification and
                                  high-level synthesis . . . . . . . . . . 554--562
           James K. Huggins and   
           David Van Campenhout   Specification and verification of
                                  pipelining in the ARM2 RISC
                                  microprocessor . . . . . . . . . . . . . 563--580
          D. Van Campenhout and   
                H. Al-Asaad and   
                J. P. Hayes and   
                   T. Mudge and   
                    R. B. Brown   High-level design verification of
                                  microprocessors via error modeling . . . 581--599
                 G. Hasteer and   
                  A. Mathur and   
                    P. Banerjee   Efficient equivalence checking of
                                  multi-phase designs using phase
                                  abstraction and retiming . . . . . . . . 600--625
                   A. Benso and   
                P. Prinetto and   
              M. Rebaudengo and   
                M. Sonza Reorda   EXFI: a low-cost fault injection system
                                  for embedded microprocessor-based boards 626--634


ACM Transactions on Design Automation of Electronic Systems
Volume 4, Number 1, January, 1999

           Michael Gasteier and   
                Manfred Glesner   Bus-based communication synthesis on
                                  system level . . . . . . . . . . . . . . 1--11
                  Stan Liao and   
           Srinivas Devadas and   
                   Kurt Keutzer   A text-compression-based method for code
                                  size minimization in embedded systems    12--38
                Xiaoyu Song and   
                      Yuke Wang   On the crossing distribution problem . . 39--51
              Jyh-Mou Tseng and   
                  Jing-Yang Jou   Two-level logic minimization for low
                                  power  . . . . . . . . . . . . . . . . . 52--69
                    Frank Vahid   Procedure cloning: a transformation for
                                  improved system-level functional
                                  partitioning . . . . . . . . . . . . . . 70--96
                    Qi Wang and   
       Sarma B. K. Vrudhula and   
                  Gary Yeap and   
               Shantanu Ganguly   Power reduction and power-delay
                                  trade-offs using logic transformations   97--121

ACM Transactions on Design Automation of Electronic Systems
Volume 4, Number 2, April, 1999

             Christoph Kern and   
            Mark R. Greenstreet   Formal verification in hardware design:
                                  a survey . . . . . . . . . . . . . . . . 123--193
              Kuen-Jong Lee and   
              Jing-Jou Tang and   
                Tsung-Chu Huang   BIFEST: a built-in intermediate fault
                                  effect sensing and test generation
                                  system for CMOS bridging faults  . . . . 194--218
             M. A. Thornton and   
                  V. S. S. Nair   Behavioral synthesis of combinational
                                  logic using spectral-based heuristics    219--230

ACM Transactions on Design Automation of Electronic Systems
Volume 4, Number 3, July, 1999

              Wei-Kai Cheng and   
                  Youn-Long Lin   Code generation of nested loops for DSP
                                  processors with heterogeneous registers
                                  and structural pipelining  . . . . . . . 231--256
         Yau-Tsun Steven Li and   
               Sharad Malik and   
                   Andrew Wolfe   Performance estimation of embedded
                                  software with instruction cache modeling 257--279
          C.-J. Richard Shi and   
                Michael W. Tian   Simulation and sensitivity of linear
                                  analog circuits under parameter
                                  variations by Robust interval analysis   280--312
                Bernd Wurth and   
           Ulf Schlichtmann and   
                 Klaus Eckl and   
               Kurt J. Antreich   Functional multiple-output decomposition
                                  with application to technology mapping
                                  for lookup table-based FPGAs . . . . . . 313--350

ACM Transactions on Design Automation of Electronic Systems
Volume 4, Number 4, October, 1999

                  L. Benini and   
              G. De Micheli and   
                   E. Macii and   
                 M. Poncino and   
                      R. Scarsi   Symbolic synthesis of clock-gating logic
                                  for power optimization of synchronous
                                  controllers  . . . . . . . . . . . . . . 351--375
              Kyumyung Choi and   
              Steven P. Levitan   A flexible datapath allocation method
                                  for architectural synthesis  . . . . . . 376--404
                  Inki Hong and   
          Miodrag Potkonjak and   
                   Ramesh Karri   Power optimization using
                                  divide-and-conquer techniques for
                                  minimization of the number of operations 405--429
          Miodrag Potkonjak and   
                     Wayne Wolf   A methodology and algorithms for the
                                  design of hard real-time multitasking
                                  ASICs  . . . . . . . . . . . . . . . . . 430--459


ACM Transactions on Design Automation of Electronic Systems
Volume 5, Number 1, January, 2000

      Luiz C. V. Dos Santos and   
        M. J. M. Heijligers and   
          C. A. J. Van Eijk and   
          J. Van Eijndhoven and   
                  J. A. G. Jess   A code-motion pruning technique for
                                  global scheduling  . . . . . . . . . . . 1--33
              Wen-Jong Fang and   
                 Allen C.-H. Wu   Multiway FPGA partitioning by fully
                                  exploiting design hierarchy  . . . . . . 34--50
                 Pao-Ann Hsiung   CMAPS: a cosynthesis methodology for
                                  application-oriented parallel systems    51--81
            Dinesh P. Mehta and   
                Naveed Sherwani   On the use of flexible, rectilinear
                                  blocks to obtain minimum-area floorplans
                                  in mixed block and cell designs  . . . . 82--97
       Sachin S. Sapatnekar and   
                 Weitong Chuang   Power-delay optimizations in gate sizing 98--114

ACM Transactions on Design Automation of Electronic Systems
Volume 5, Number 2, January, 2000

                Luca Benini and   
            Giovanni de Micheli   System-level power optimization:
                                  techniques and tools . . . . . . . . . . 115--192
                 Jason Cong and   
                 Yean-Yow Hwang   Structural gate decomposition for
                                  depth-optimal technology mapping in
                                  LUT-based FPGA designs . . . . . . . . . 193--225
             Chi-Hong Hwang and   
                 Allen C.-H. Wu   A predictive system shutdown method for
                                  energy saving of event-driven
                                  computation  . . . . . . . . . . . . . . 226--241
           Ashok Sudarsanam and   
                   Sharad Malik   Simultaneous reference allocation in
                                  code generation for dual data memory
                                  bank ASIPs . . . . . . . . . . . . . . . 242--264

ACM Transactions on Design Automation of Electronic Systems
Volume 5, Number 3, January, 2000

                Mary Jane Irwin   Editorial  . . . . . . . . . . . . . . . 265--266
              R. Iris Bahar and   
            Ernest T. Lampe and   
                   Enrico Macii   Power optimization of
                                  technology-dependent circuits based on
                                  symbolic computation of logic
                                  implications . . . . . . . . . . . . . . 267--293
            M. Balakrishnan and   
                   Heman Khanna   Allocation of FIFO structures in RTL
                                  data paths . . . . . . . . . . . . . . . 294--310
                  L. Benini and   
                  G. De Micheli   Synthesis of low-power
                                  selectively-clocked systems from
                                  high-level specification . . . . . . . . 311--321
          Stephen A. Blythe and   
               Robert A. Walker   Efficient optimal design space
                                  characterization methodologies . . . . . 322--336
        Alessandro Bogliolo and   
                Luca Benini and   
            Giovanni De Micheli   Regression-based RTL power modeling  . . 337--372
             Surendra Bommu and   
              Niall O'Neill and   
              Maciej Ciesielski   Retiming-based factorization for
                                  sequential logic optimization  . . . . . 373--398
         Vincenza Carchiolo and   
            Michele Malgeri and   
              Giuseppe Mangioni   Hardware/software synthesis of formal
                                  specifications in codesign of embedded
                                  systems  . . . . . . . . . . . . . . . . 399--432
              Yao-Wen Chang and   
                    Kai Zhu and   
                     D. F. Wong   Timing-driven routing for symmetrical
                                  array-based FPGAs  . . . . . . . . . . . 433--450
           Donald S. Gelosh and   
             Dorothy E. Setliff   Modeling layout tools to derive forward
                                  estimates of area and delay at the RTL
                                  level  . . . . . . . . . . . . . . . . . 451--491
                 G. Gogniat and   
                  M. Auguin and   
                  L. Bianco and   
                  A. Pegatoquet   A codesign back-end approach for
                                  embedded system design . . . . . . . . . 492--509
           Avaneendra Gupta and   
                  John P. Hayes   CLIP: integer-programming-based optimal
                                  layout synthesis of $2$D CMOS cells  . . 510--547
           Michael S. Hsiao and   
       Elizabeth M. Rudnick and   
                 Janak H. Patel   Dynamic state traversal for sequential
                                  circuit test generation  . . . . . . . . 548--565
              Pradip K. Jha and   
                  Nikil D. Dutt   High-level library mapping for memories  566--603
           Kumar N. Lalgudi and   
    Marios C. Papaefthymiou and   
              Miodrag Potkonjak   Optimizing computations for effective
                                  block-processing . . . . . . . . . . . . 604--630
              David E. Long and   
             Mahesh A. Iyer and   
               Miron Abramovici   FILL and FUNI: algorithms to identify
                                  illegal states and sequentially
                                  untestable faults  . . . . . . . . . . . 631--657
           Diana Marculescu and   
            Radu Marculescu and   
                 Massoud Pedram   Stochastic sequential machine synthesis
                                  with application to constrained sequence
                                  generation . . . . . . . . . . . . . . . 658--681
        Preeti Ranjan Panda and   
              Nikil D. Dutt and   
              Alexandru Nicolau   On-chip vs. off-chip memory: the data
                                  partitioning problem in embedded
                                  processor-based systems  . . . . . . . . 682--704
              Richard Raimi and   
               Ramin Hojati and   
              Kedar S. Namjoshi   Environment modeling and language
                                  universality . . . . . . . . . . . . . . 705--725
                    Jin-Tai Yan   Three-layer bubble-sorting-based
                                  nonManhattan channel routing . . . . . . 726--734
           Cheng-Hsing Yang and   
               Sao-Jie Chen and   
                Jan-Ming Ho and   
                 Chia-Chun Tsai   Efficient routability check algorithms
                                  for segmented channel routing  . . . . . 735--747

ACM Transactions on Design Automation of Electronic Systems
Volume 5, Number 4, January, 2000

                 Peter Marwedel   Guest Editorial  . . . . . . . . . . . . 749--751
               Shail Aditya and   
            Scott A. Mahlke and   
             B. Ramakrishna Rau   Code size minimization and retargetable
                                  assembly for custom EPIC and VLIW
                                  instruction formats  . . . . . . . . . . 752--773
              Koen Van Eijk and   
                Bart Mesman and   
       Carlos A. Alba Pinto and   
                   Qin Zhao and   
              Marco Bekooij and   
         Jef Van Meerbergen and   
                    Jochen Jess   Constraint analysis for code generation:
                                  basic techniques and applications in
                                  FACTS  . . . . . . . . . . . . . . . . . 774--793
             Rainer Leupers and   
                Steven Bashford   Graph-based code selection techniques
                                  for embedded processors  . . . . . . . . 794--814
                Stefan Pees and   
           Andreas Hoffmann and   
                  Heinrich Meyr   Retargetable compiled simulation of
                                  embedded processors using a machine
                                  description language . . . . . . . . . . 815--834


ACM Transactions on Design Automation of Electronic Systems
Volume 6, Number 1, April, 2001

               Smita Bakshi and   
               Daniel D. Gajski   Performance-constrained hierarchical
                                  pipelining for behaviors, loops, and
                                  operations . . . . . . . . . . . . . . . 1--25
         Krishnendu Chakrabarty   Optimal test access architectures for
                                  system-on-a-chip . . . . . . . . . . . . 26--49
               Rita Yu Chen and   
            Mary Jane Irwin and   
              Raminder S. Bajwa   Architecture-level power estimation and
                                  design experiments . . . . . . . . . . . 50--66
                 Pao-Ann Hsiung   POSE: a parallel object-oriented
                                  synthesis environment  . . . . . . . . . 67--92
                  Ing-Jer Huang   Co-synthesis of pipelined structures and
                                  instruction reordering constraints for
                                  instruction set processors . . . . . . . 93--121
             E. P. Mariatos and   
               A. N. Birbas and   
                   M. K. Birbas   A mapping algorithm for
                                  computer-assisted exploration in the
                                  design of embedded systems . . . . . . . 122--147

ACM Transactions on Design Automation of Electronic Systems
Volume 6, Number 2, January, 2001

                P. R. Panda and   
                F. Catthoor and   
                 N. D. Dutt and   
               K. Danckaert and   
              E. Brockmeyer and   
                C. Kulkarni and   
          A. Vandercappelle and   
               P. G. Kjeldsberg   Data and memory optimization techniques
                                  for embedded systems . . . . . . . . . . 149--206
             Nagaraj Shenoy and   
             Alok Choudhary and   
            Prithviraj Banerjee   An algorithm for synthesis of large
                                  time-constrained heterogeneous adaptive
                                  systems  . . . . . . . . . . . . . . . . 207--225
                Chauchin Su and   
             Yue-Tsang Chen and   
                   Shyh-Jye Jou   Intrinsic response for analog module
                                  testing using an analog testability bus  226--243
               Shi-Yu Huang and   
           Kwang-Ting Cheng and   
               Kuang-Chien Chen   Verifying sequential equivalence using
                                  ATPG techniques  . . . . . . . . . . . . 244--275

ACM Transactions on Design Automation of Electronic Systems
Volume 6, Number 3, July, 2001

               J. Van Praet and   
                 D. Lanneer and   
                  W. Geurts and   
                    G. Goossens   Processor modeling and code selection
                                  for retargetable compilation . . . . . . 277--307
                 D. Kagaris and   
                   S. Tragoudas   Von Neumann hybrid cellular automata for
                                  generating deterministic test sequences  308--321
                Swanwa Liao and   
             Mario A. Lopez and   
                   Dinesh Mehta   Constrained polygon transformations for
                                  incremental floorplanning  . . . . . . . 322--342
                  Chris Chu and   
                     D. F. Wong   Closed form solutions to simultaneous
                                  buffer insertion/sizing and wire sizing  343--371
           Xiaobo Sharon Hu and   
              Danny Z. Chen and   
          Rajeshkumar Sambandam   Efficient list-approximation techniques
                                  for floorplan area minimization  . . . . 372--400
            Mehrdad Nourani and   
              Joan Carletta and   
          Christos Papachristou   Integrated test of interacting
                                  controllers and datapaths  . . . . . . . 401--422
            Ishwar Parulkar and   
           Sandeep K. Gupta and   
               Melvin A. Breuer   Introducing redundant computations in
                                  RTL data paths for reducing BIST
                                  resources  . . . . . . . . . . . . . . . 423--445

ACM Transactions on Design Automation of Electronic Systems
Volume 6, Number 4, October, 2001

     Parthasarathi Dasgupta and   
              Susmita Sur-Kolay   Slicible rectangular graphs and their
                                  optimal floorplans . . . . . . . . . . . 447--470
             Ismed Hartanto and   
      Srikanth Venkataraman and   
              W. Kent Fuchs and   
       Elizabeth M. Rudnick and   
             Janak H. Patel and   
            Sreejit Chakravarty   Diagnostic simulation of stuck-at faults
                                  in sequential circuits using compact
                                  lists  . . . . . . . . . . . . . . . . . 471--489
              M. Narasimhan and   
                   J. Ramanujam   A fast approach to computing exact
                                  solutions to the resource-constrained
                                  scheduling problem . . . . . . . . . . . 490--500
               Ramesh Karri and   
              Balakrishnan Iyer   Introspection: a register transfer level
                                  technique for cocurrent error detection
                                  and diagnosis in data dominated designs  501--515
   François R. Boyer and   
     El Mostapha Aboulhamid and   
               Yvon Savaria and   
                   Michel Boyer   Optimal design of synchronous circuits
                                  using software pipelining techniques . . 516--532
                  Jeroen Voeten   On the fundamental limitations of
                                  transformational design  . . . . . . . . 533--552
            Wen-Tsong Shiue and   
Sathishkumar Udayanarayanan and   
           Chaitali Chakrabarti   Data memory design and exploration for
                                  low-power embedded systems . . . . . . . 553--568
               Pranav Ashar and   
                Aarti Gupta and   
                   Sharad Malik   Using complete-$1$-distinguishability
                                  for FSM equivalence checking . . . . . . 569--590
               Tai-Hung Liu and   
                 Adnan Aziz and   
                 Vigyan Singhal   Optimizing designs containing black
                                  boxes  . . . . . . . . . . . . . . . . . 591--601
             Partha S. Roop and   
                  A. Sowmya and   
                      S. Ramesh   Forced simulation: a technique for
                                  automating component reuse in embedded
                                  systems  . . . . . . . . . . . . . . . . 602--628
            Paulo F. Flores and   
     Horácio C. Neto and   
   João P. Marques-Silva   An exact solution to the minimum size
                                  test pattern problem . . . . . . . . . . 629--644


ACM Transactions on Design Automation of Electronic Systems
Volume 7, Number 1, January, 2002

             Amit Chowdhary and   
                  John P. Hayes   General technology mapping for
                                  field-programmable gate arrays based on
                                  lookup tables  . . . . . . . . . . . . . 1--32
                 M. Michael and   
                   S. Tragoudas   ATPG tools for delay faults at the
                                  functional level . . . . . . . . . . . . 33--57
              Roman Lysecky and   
                    Frank Vahid   Prefetching for improved bus wrapper
                                  performance in cores . . . . . . . . . . 58--90
              Shantanu Dutt and   
                   Wenyong Deng   Cluster-aware iterative improvement
                                  techniques for partitioning large VLSI
                                  circuits . . . . . . . . . . . . . . . . 91--121
            Laurence Goodby and   
           Alex Orailo\uglu and   
                   Paul M. Chau   Microarchitectural synthesis of
                                  performance-constrained, low-power VLSI
                                  designs  . . . . . . . . . . . . . . . . 122--136
 Luís Guerra e Silva and   
  João Marques-Silva and   
         L. Miguel Silveira and   
              Karem A. Sakallah   Satisfiability models and algorithms for
                                  circuit delay computation  . . . . . . . 137--158
                Alain Darte and   
           Robert Schreiber and   
         B. Ramakrishna Rau and   
  Frédéric Vivien   Constructing and exploiting linear
                                  schedules with prescribed parallelism    159--172
          Ashok Jagannathan and   
               Sung-Woo Hur and   
                    John Lillis   A fast algorithm for context-aware
                                  buffer insertion . . . . . . . . . . . . 173--188
               Ranga Vemuri and   
          Srinivas Katkoori and   
             Meenakshi Kaul and   
                        Jay Roy   An efficient register optimization
                                  algorithm for high-level synthesis from
                                  hierarchical behavioral specifications   189--216
         Shi-Zheng Eric Lin and   
             Chieh Changfan and   
                Yu-Chin Hsu and   
                 Fur-Shing Tsai   Optimal time borrowing analysis and
                                  timing budgeting optimization for
                                  latch-based designs  . . . . . . . . . . 217--230

ACM Transactions on Design Automation of Electronic Systems
Volume 7, Number 2, April, 2002

     Parthasarathi Dasgupta and   
                Peichen Pan and   
            Subhas C. Nandy and   
        Bhargab B. Bhattacharya   Monotone bipartitioning problem in a
                                  planar point set with applications to
                                  VLSI . . . . . . . . . . . . . . . . . . 231--248
                   F. Corno and   
                P. Prinetto and   
              M. Rebaudengo and   
            M. Sonza Reorda and   
                   G. Squillero   Initializability analysis of synchronous
                                  sequential circuits  . . . . . . . . . . 249--264
                Ki-Wook Kim and   
                Taewhan Kim and   
            Ting-Ting Hwang and   
               Sung-Mo Kang and   
                      C. L. Liu   Logic transformation for low-power
                                  synthesis  . . . . . . . . . . . . . . . 265--283
                Russell Tessier   Fast placement approaches for FPGAs  . . 284--305
                   Min Zhao and   
           Sachin S. Sapatnekar   Technology mapping algorithms for domino
                                  logic  . . . . . . . . . . . . . . . . . 306--335
               Guido Araujo and   
           Guilherme Ottoni and   
                 Marcelo Cintra   Global array reference allocation  . . . 336--357

ACM Transactions on Design Automation of Electronic Systems
Volume 7, Number 3, July, 2002

      Chung-wen Albert Tsao and   
                  Cheng-kok Koh   UST/DME: a clock tree router for general
                                  skew constraints . . . . . . . . . . . . 359--379
    Apostolos A. Kountouris and   
            Christophe Wolinski   Efficient scheduling of conditional
                                  behaviors for high-level synthesis . . . 380--412
                    Frank Vahid   Partitioning sequential programs for CAD
                                  using a three-step approach  . . . . . . 413--429
        Viktor S. Lapinskii and   
        Margarida F. Jacome and   
          Gustavo A. De Veciana   Cluster assignment for high-performance
                                  embedded VLIW processors . . . . . . . . 430--454
              Vikram Saxena and   
              Farid N. Najm and   
                Ibrahim N. Hajj   Estimation of state line statistics in
                                  sequential circuits  . . . . . . . . . . 455--473
                  A. Glebov and   
                S. Gavrilov and   
                  D. Blaauw and   
                     V. Zolotov   False-noise analysis using logic
                                  implications . . . . . . . . . . . . . . 474--498

ACM Transactions on Design Automation of Electronic Systems
Volume 7, Number 4, October, 2002

          Majid Sarrafzadeh and   
               Rajeev Jayaraman   Guest editorial  . . . . . . . . . . . . 499--500
               Navin Vemuri and   
              Priyank Kalla and   
                Russell Tessier   BDD-based logic synthesis for LUT-based
                                  FPGAs  . . . . . . . . . . . . . . . . . 501--525
               Hongbing Fan and   
                 Jiping Liu and   
                Yu-Liang Wu and   
                     C. K. Wong   Reduction design for generic universal
                                  switch blocks  . . . . . . . . . . . . . 526--546
           Andreas Dandalis and   
             Viktor K. Prasanna   Run-time performance optimization of an
                                  FPGA-based deduction engine for SAT
                                  solvers  . . . . . . . . . . . . . . . . 547--562
                 Haibo Wang and   
           Sarma B. K. Vrudhula   Behavioral synthesis of field
                                  programmable analog array circuits . . . 563--604
                 R. Kastner and   
                  A. Kaplan and   
           S. Ogrenci Memik and   
                 E. Bozorgzadeh   Instruction generation for hybrid
                                  reconfigurable systems . . . . . . . . . 605--627
              Guang-Ming Wu and   
               Jai-Ming Lin and   
                  Yao-Wen Chang   Performance-driven placement for
                                  dynamically reconfigurable FPGAs . . . . 628--642
                 Amit Singh and   
    Ganapathy Parthasarathy and   
     Ma\lgorzata Marek-Sadowska   Efficient circuit clustering for area
                                  and power reduction in FPGAs . . . . . . 643--663
              Shantanu Dutt and   
                Vinay Verma and   
                   Hasan Arslan   A search-based bump-and-refit approach
                                  to incremental routing for ECO
                                  applications in FPGAs  . . . . . . . . . 664--693


ACM Transactions on Design Automation of Electronic Systems
Volume 8, Number 1, January, 2003

               S. Tragoudas and   
                       N. Denny   Path delay fault testing using test
                                  points . . . . . . . . . . . . . . . . . 1--10
              Yao-Wen Chang and   
                    Kai Zhu and   
              Guang-Ming Wu and   
                 D. F. Wong and   
                     C. K. Wong   Analysis of FPGA/FPIC switch modules . . 11--37
                 W.-B. Jone and   
                 J. S. Wang and   
                 Hsueh-I Lu and   
                  I. P. Hsu and   
                     J.-Y. Chen   Design theory and implementation for
                                  low-power segmented bus systems  . . . . 38--54
                     Bo Yao and   
                Hongyu Chen and   
           Chung-Kuan Cheng and   
                  Ronald Graham   Floorplan representations: Complexity
                                  and connections  . . . . . . . . . . . . 55--80
           Michael A. Riepe and   
              Karem A. Sakallah   Transistor placement for
                                  noncomplementary digital VLSI cell
                                  synthesis  . . . . . . . . . . . . . . . 81--107
      R. D. (Shawn) Blanton and   
                  John P. Hayes   On the properties of the input pattern
                                  fault model  . . . . . . . . . . . . . . 108--124
         Tanja Van Achteren and   
           Francky Catthoor and   
            Rudy Lauwereins and   
                Geert Deconinck   Search space definition and exploration
                                  for nonuniform data reuse opportunities
                                  in data-dominant applications  . . . . . 125--139

ACM Transactions on Design Automation of Electronic Systems
Volume 8, Number 2, April, 2003

             Stephen A. Edwards   Tutorial: Compiling concurrent languages
                                  for sequential processors  . . . . . . . 141--187
              Guang-Ming Wu and   
             Yun-Chih Chang and   
                  Yao-Wen Chang   Rectilinear block placement using
                                  B*-trees . . . . . . . . . . . . . . . . 188--202
                Ki-Wook Kim and   
             Seong-Ook Jung and   
                Taewhan Kim and   
                   Sung-Mo Kang   Minimum delay optimization for domino
                                  logic circuits---a coupling-aware
                                  approach . . . . . . . . . . . . . . . . 203--213
                  Ali Pinar and   
                      C. L. Liu   Compacting sequences with invariant
                                  transition frequencies . . . . . . . . . 214--221
             Vigyan Singhal and   
                Carl Pixley and   
                 Adnan Aziz and   
                Shaz Qadeer and   
                 Robert Brayton   Sequential optimization in the absence
                                  of global reset  . . . . . . . . . . . . 222--251
               Chingren Lee and   
              Jenq Kuen Lee and   
             Tingting Hwang and   
                  Shi-Chun Tsai   Compiler optimization on VLIW
                                  instruction scheduling for low power . . 252--268

ACM Transactions on Design Automation of Electronic Systems
Volume 8, Number 3, July, 2003

Marisa López-Vallejo and   
       Juan Carlos López   On the hardware-software partitioning
                                  problem: System modeling and
                                  partitioning techniques  . . . . . . . . 269--297
      Stefan Thomas Obenaus and   
               Ted H. Szymanski   Gravity: Fast placement for $3$-D VLSI   298--315
                    X. Yang and   
                    M. Wang and   
                 R. Kastner and   
                  S. Ghiasi and   
                 M. Sarrafzadeh   Congestion reduction during placement
                                  with provably good approximation bound   316--333
       G. A. Constantinides and   
            P. Y. K. Cheung and   
                         W. Luk   Synthesis of saturation arithmetic
                                  architectures  . . . . . . . . . . . . . 334--354
           Krzysztof Kuchcinski   Constraints-driven scheduling and
                                  resource assignment  . . . . . . . . . . 355--383
                  J.-Y. Lee and   
                     I.-C. Park   Address code generation for DSP
                                  instruction-set architectures  . . . . . 384--395

ACM Transactions on Design Automation of Electronic Systems
Volume 8, Number 4, October, 2003

             Shishpal Rawat and   
        Hans-Joachim Wunderlich   Introduction . . . . . . . . . . . . . . 397--398
         Sandeep Kumar Goel and   
            Erik Jan Marinissen   SOC test architecture design for
                                  efficient utilization of test bandwidth  399--429
          Aiman H. El-Maleh and   
                 Yahya E. Osais   Test vector decomposition-based static
                                  compaction algorithms for combinational
                                  circuits . . . . . . . . . . . . . . . . 430--459
          Sudhakar M. Reddy and   
               Kohei Miyase and   
             Seiji Kajihara and   
                 Irith Pomeranz   On test data volume reduction for
                                  multiple scan chain designs  . . . . . . 460--469
                     Lei Li and   
     Krishnendu Chakrabarty and   
                   Nur A. Touba   Test data compression using dictionaries
                                  with selective entries and fixed-length
                                  indices  . . . . . . . . . . . . . . . . 470--490
              Adit D. Singh and   
             Markus Seuring and   
        Michael Gössel and   
             Egor S. Sogomonyan   Multimode scan: Test per clock BIST for
                                  IP cores . . . . . . . . . . . . . . . . 491--505
            Muhammad Nummer and   
                  Manoj Sachdev   Testing high-performance pipelined
                                  circuits with slow-speed testers . . . . 506--521
        Kumar Parthasarathy and   
               Turker Kuyel and   
                 Dana Price and   
                     Le Jin and   
                Degang Chen and   
                 Randall Geiger   BIST and production testing of ADCs
                                  using imprecise stimulus . . . . . . . . 522--545
                    Zhuo Li and   
                   Xiang Lu and   
                 Wangqi Qiu and   
                Weiping Shi and   
                D. M. H. Walker   A circuit level fault model for
                                  resistive bridges  . . . . . . . . . . . 546--559
            Dirk Niggemeyer and   
           Elizabeth M. Rudnick   A data acquisition methodology for
                                  on-chip repair of embedded memories  . . 560--576
          Gustavo Neuberger and   
           Fernanda de Lima and   
                Luigi Carro and   
                   Ricardo Reis   A multiple bit upset tolerant SRAM
                                  memory . . . . . . . . . . . . . . . . . 577--590


ACM Transactions on Design Automation of Electronic Systems
Volume 9, Number 1, January, 2004

             Annette Bunker and   
      Ganesh Gopalakrishnan and   
                 Sally A. Mckee   Formal hardware specification languages
                                  for protocol compliance verification . . 1--32
                     Hao Li and   
          Srinivas Katkoori and   
                    Wai-Kei Mak   Power minimization algorithms for
                                  LUT-based FPGA technology mapping  . . . 33--51
               Jeonghun Cho and   
              Yunheung Paek and   
                  David Whalley   Fast memory bank assignment for
                                  fixed-point digital signal processors    52--74
                 Sandip Das and   
          Susmita Sur-Kolay and   
        Bhargab B. Bhattacharya   Manhattan-diagonal routing in channels
                                  and switchboxes  . . . . . . . . . . . . 75--104
               Lieh-Ming Wu and   
               Kuochen Wang and   
                 Chuang-Yi Chiu   A BNF-based automatic test program
                                  generator for compatible microprocessor
                                  verification . . . . . . . . . . . . . . 105--132

ACM Transactions on Design Automation of Electronic Systems
Volume 9, Number 2, April, 2004

           P. G. Kjeldsberg and   
                F. Catthoor and   
                      E. J. Aas   Storage requirement estimation for
                                  optimized design of data intensive
                                  applications . . . . . . . . . . . . . . 133--158
            Sagar S. Sabade and   
               Duncan M. Walker   I$_{\mbox {DDX}}$-based test methods: a
                                  survey . . . . . . . . . . . . . . . . . 159--198
                  Yuchun Ma and   
              Xianlong Hong and   
                Sheqin Dong and   
                   Yici Cai and   
           Chung-Kuan Cheng and   
                         Jun Gu   Stairway compaction using corner block
                                  list and its applications with
                                  rectilinear blocks . . . . . . . . . . . 199--211
          Praveen K. Murthy and   
        Shuvra S. Bhattacharyya   Buffer merging---a powerful technique
                                  for reducing memory requirements of
                                  synchronous dataflow specifications  . . 212--237
                Alex Doboli and   
              Nagu Dhanwada and   
        Adrian Nunez-Aldana and   
                   Ranga Vemuri   A two-layer library-based approach to
                                  synthesis of analog systems from
                                  VHDL-AMS specifications  . . . . . . . . 238--271

ACM Transactions on Design Automation of Electronic Systems
Volume 9, Number 3, July, 2004

         Vijay Sundararajan and   
       Sachin S. Sapatnekar and   
                Keshab K. Parhi   A new approach for integration of
                                  min-area retiming and min-delay padding
                                  for simultaneously addressing short-path
                                  and long-path constraints  . . . . . . . 273--289
             Kevin M. Lepak and   
                     Min Xu and   
                   Jun Chen and   
                         Lei He   Simultaneous shield insertion and net
                                  ordering for capacitive and inductive
                                  coupling minimization  . . . . . . . . . 290--309
            Juan D. Vicente and   
             Juan Lanchares and   
           Román Hermida   Annealing placement by thermodynamic
                                  combinatorial optimization . . . . . . . 310--332
           Andreas Dandalis and   
             Viktor K. Prasanna   An adaptive cryptographic engine for
                                  Internet protocol security architectures 333--353
                   Jun Yang and   
                Rajiv Gupta and   
                 Chuanjun Zhang   Frequent value encoding for low power
                                  data buses . . . . . . . . . . . . . . . 354--384

ACM Transactions on Design Automation of Electronic Systems
Volume 9, Number 4, October, 2004

                     Ali Dasdan   Experimental analysis of the fastest
                                  optimum cycle ratio and mean algorithms  385--418
               Arijit Ghosh and   
                  Tony Givargis   Cache optimization for embedded
                                  processor cores: an analytical approach  419--440
                Sumit Gupta and   
         Rajesh Kumar Gupta and   
              Nikil D. Dutt and   
              Alexandru Nicolau   Coordinated parallelizing compiler
                                  optimizations and high-level synthesis   441--470
          Érika Cota and   
                Luigi Carro and   
            Marcelo Lubaszewski   Reusing an on-chip network for the test
                                  of core-based systems  . . . . . . . . . 471--499
              C. V. Krishna and   
                Abhijit Jas and   
                   Nur A. Touba   Achieving high encoding efficiency with
                                  partial dynamic LFSR reseeding . . . . . 500--516
         William N. N. Hung and   
                Xiaoyu Song and   
     El Mostapha Aboulhamid and   
            Andrew Kennings and   
                   Alan Coppola   Segmented channel routability via
                                  satisfiability . . . . . . . . . . . . . 517--528


ACM Transactions on Design Automation of Electronic Systems
Volume 10, Number 1, January, 2005

                     Nikil Dutt   Editorial  . . . . . . . . . . . . . . . 1--2
                 Jason Cong and   
                  Hui Huang and   
                       Xin Yuan   Technology mapping and architecture
                                  evaluation for $ k / m$-macrocell-based
                                  FPGAs  . . . . . . . . . . . . . . . . . 3--23
            Shanq-Jang Ruan and   
               Kun-Lin Tsai and   
              Edwin Naroska and   
                     Feipei Lai   Bipartitioning and encoding in low-power
                                  pipelined circuits . . . . . . . . . . . 24--32
         Seda Ogrenci Memik and   
               Ryan Kastner and   
         Elaheh Bozorgzadeh and   
              Majid Sarrafzadeh   A scheduling algorithm for optimization
                                  and early planning in high-level
                                  synthesis  . . . . . . . . . . . . . . . 33--57
                 S. N. Adya and   
                   I. L. Markov   Combinatorial techniques for mixed-size
                                  placement  . . . . . . . . . . . . . . . 58--90
            Mehrdad Nourani and   
        Mohammad H. Tehranipour   RL-Huffman encoding for test compression
                                  and power reduction in scan applications 91--115
                Gene Eu Jan and   
               Ki-Yin Chang and   
                     Su Gao and   
                   Ian Parberry   A $4$-geometry maze router and its
                                  application on multiterminal nets  . . . 116--135
  Péter Arató and   
Zoltán Ádám Mann and   
     András Orbán   Algorithmic aspects of hardware/software
                                  partitioning . . . . . . . . . . . . . . 136--156
                Dimitri Kagaris   A unified method for phase shifter
                                  computation  . . . . . . . . . . . . . . 157--167
               Chi-Chou Kao and   
                    Yen-Tai Lai   An efficient algorithm for finding the
                                  minimal-area FPGA technology mapping . . 168--186

ACM Transactions on Design Automation of Electronic Systems
Volume 10, Number 2, April, 2005

         Noureddine Chabini and   
     El Mostapha Aboulhamid and   
          Isma\"\il Chabini and   
                   Yvon Savaria   Scheduling and optimal register
                                  placement for synchronous circuits
                                  derived using software pipelining
                                  techniques . . . . . . . . . . . . . . . 187--204
                  Aiqun Cao and   
          Naran Sirisantana and   
              Cheng-Kok Koh and   
                    Kaushik Roy   Synthesis of skewed logic circuits . . . 205--228
                 I. Kadayif and   
         A. Sivasubramaniam and   
                M. Kandemir and   
               G. Kandiraju and   
                        G. Chen   Optimizing instruction TLB energy using
                                  software and hardware techniques . . . . 229--257
                   Xiao Liu and   
           Michael S. Hsiao and   
        Sreejit Chakravarty and   
             Paul J. Thadikaran   Efficient techniques for transition
                                  testing  . . . . . . . . . . . . . . . . 258--278
            Kara K. W. Poon and   
        Steven J. E. Wilton and   
                       Andy Yan   A detailed power model for
                                  field-programmable gate arrays . . . . . 279--302
      Soumendu Bhattacharya and   
             Abhijit Chatterjee   Optimized wafer-probe and assembled
                                  package test design for analog circuits  303--329
          Saraju P. Mohanty and   
                 N. Ranganathan   Energy-efficient datapath scheduling
                                  using multiple voltages and dynamic
                                  clocking . . . . . . . . . . . . . . . . 330--353
             Azadeh Davoodi and   
               Ankur Srivastava   Voltage scheduling under
                                  unpredictabilities: a risk management
                                  paradigm . . . . . . . . . . . . . . . . 354--368
                 Zhong Wang and   
               Xiaobo Sharon Hu   Energy-aware variable partitioning and
                                  instruction scheduling for multibank
                                  memory architectures . . . . . . . . . . 369--388
                 Jason Cong and   
         Joseph R. Shinnerl and   
                    Min Xie and   
                   Tim Kong and   
                       Xin Yuan   Large-scale circuit placement  . . . . . 389--430

ACM Transactions on Design Automation of Electronic Systems
Volume 10, Number 3, July, 2005

              Joann M. Paul and   
           Donald E. Thomas and   
              Andrew S. Cassidy   High-level modeling and simulation of
                                  single-chip programmable heterogeneous
                                  multiprocessors  . . . . . . . . . . . . 431--461
                  Arnab Roy and   
                S. K. Panda and   
               Rajeev Kumar and   
              P. P. Chakrabarti   A framework for systematic validation
                                  and debugging of pipeline simulators . . 462--491
           Ansuman Banerjee and   
                Pallab Dasgupta   The open family of temporal logics:
                                  Annotating temporal operators with input
                                  constraints  . . . . . . . . . . . . . . 492--522
         Farinaz Koushanfar and   
                  Inki Hong and   
              Miodrag Potkonjak   Behavioral synthesis techniques for
                                  intellectual property protection . . . . 523--545
               Puneet Gupta and   
            Andrew B. Kahng and   
                Stefanus Mantik   Routing-aware scan chain ordering  . . . 546--560
                  Hua Xiang and   
              Xiaoping Tang and   
              Martin D. F. Wong   An algorithm for integrated pin
                                  assignment and buffer planning . . . . . 561--572
           Jaehwan John Lee and   
        Vincent John Mooney III   An $ o(\mbox {min}(m, n)) $ parallel
                                  deadlock detection algorithm . . . . . . 573--586

ACM Transactions on Design Automation of Electronic Systems
Volume 10, Number 4, October, 2005

                  Ian G. Harris   Introduction . . . . . . . . . . . . . . 587--588
             Syed M. Suhaib and   
      Deepak A. Mathaikutty and   
          Sandeep K. Shukla and   
                   David Berner   XFM: an incremental methodology for
                                  developing formal models . . . . . . . . 589--609
                Masahiro Fujita   Equivalence checking between behavioral
                                  and RTL descriptions with virtual
                                  controllers and datapaths  . . . . . . . 610--626
                   Tao Feng and   
                  Li-C Wang and   
     Kwang-Ting (Tim) Cheng and   
          Chih-Chang (Andy) Lin   Using $2$-domain partitioned OBDD data
                                  structure in an enhanced symbolic
                                  simulator  . . . . . . . . . . . . . . . 627--650
           Jason T. Higgins and   
                Mark D. Aagaard   Simplifying the design and automating
                                  the verification of pipelines with
                                  structural hazards . . . . . . . . . . . 651--672
            Saeed Shamshiri and   
          Hadi Esmaeilzadeh and   
            Zainalabdein Navabi   Instruction-level test methodology for
                                  CPU core self-testing  . . . . . . . . . 673--689
         Ahmad A. Al-Yamani and   
            Edward J. McCluskey   Test chip experimental results on
                                  high-level structural test . . . . . . . 690--701
              Calin Ciordas and   
                Twan Basten and   
         Andrei R\uadulescu and   
              Kees Goossens and   
             Jef Van Meerbergen   An event-based monitoring service for
                                  networks on chip . . . . . . . . . . . . 702--723


ACM Transactions on Design Automation of Electronic Systems
Volume 11, Number 1, January, 2006

                     Nikil Dutt   Editorial  . . . . . . . . . . . . . . . 1--2
                  Tony Givargis   Zero cost indexing for improved
                                  processor cache performance  . . . . . . 3--25
       George A. Constantinides   Word-length optimization for
                                  differentiable nonlinear systems . . . . 26--43
                    Qing Su and   
                 Jamil Kawa and   
             Charles Chiang and   
                  Yehia Massoud   Accurate modeling of substrate resistive
                                  coupling for floating substrates . . . . 44--51
             Azadeh Davoodi and   
               Ankur Srivastava   Effective techniques for the generalized
                                  low-power binding problem  . . . . . . . 52--69
          Patrick Schaumont and   
                Doris Ching and   
             Ingrid Verbauwhede   An interactive codesign environment for
                                  domain-specific coprocessors . . . . . . 70--87
          Iris Hui-Ru Jiang and   
                Song-Ra Pan and   
              Yao-Wen Chang and   
                  Jing-Yang Jou   Reliable crosstalk-driven interconnect
                                  optimization . . . . . . . . . . . . . . 88--103
         Dhananjay Kulkarni and   
            Walid A. Najjar and   
              Robert Rinker and   
                Fadi J. Kurdahi   Compile-time area estimation for
                                  LUT-based FPGAs  . . . . . . . . . . . . 104--122
         Aviral Shrivastava and   
              Partha Biswas and   
              Ashok Halambi and   
                 Nikil Dutt and   
                   Alex Nicolau   Compilation framework for code size
                                  reduction using reduced bit-width ISAs
                                  (rISAs)  . . . . . . . . . . . . . . . . 123--146
                Yi-Ping You and   
               Chingren Lee and   
                  Jenq Kuen Lee   Compilers for leakage power reduction    147--164
                  Zili Shao and   
                   Bin Xiao and   
                   Chun Xue and   
             Qingfeng Zhuge and   
                Edwin H.-M. Sha   Loop scheduling with timing and
                                  switching-activity minimization for VLIW
                                  DSP  . . . . . . . . . . . . . . . . . . 165--185
          Saraju P. Mohanty and   
             N. Ranganathan and   
              Sunil K. Chappidi   ILP models for simultaneous energy and
                                  transient power minimization during
                                  behavioral synthesis . . . . . . . . . . 186--212
     Muhammet Mustafa Ozdal and   
              Martin D. F. Wong   Two-layer bus routing for high-speed
                                  printed circuit boards . . . . . . . . . 213--227
                M. Kandemir and   
               J. Ramanujam and   
                       U. Sezer   Improving the energy behavior of block
                                  buffering using compiler optimizations   228--250

ACM Transactions on Design Automation of Electronic Systems
Volume 11, Number 2, April, 2006

     M. Ayala-Rincón and   
               C. H. Llanos and   
               R. P. Jacobi and   
              R. W. Hartenstein   Prototyping time- and space-efficient
                                  computations of algebraic operations
                                  over dynamically reconfigurable systems
                                  modeled by rewriting-logic . . . . . . . 251--281
                Javed Absar and   
               Francky Catthoor   Reuse analysis of indirectly indexed
                                  arrays . . . . . . . . . . . . . . . . . 282--305
                 Ali Dasdan and   
                       Ivan Hom   Handling inverted temperature dependence
                                  in static timing analysis  . . . . . . . 306--324
                 Zuoyuan Li and   
              Xianlong Hong and   
                 Qiang Zhou and   
                Jinian Bian and   
             Hannah H. Yang and   
               Vijay Pitchumani   Efficient thermal-oriented $3$D
                                  floorplanning and thermal via planning
                                  for two-stacked-die integration  . . . . 325--345
       Saravanan Padmanaban and   
               Spyros Tragoudas   Implicit grading of multiple path delay
                                  faults . . . . . . . . . . . . . . . . . 346--361
                Deming Chen and   
                 Jason Cong and   
                     Junjuan Xu   Optimal simultaneous module and
                                  multivoltage assignment for low power    362--386
                 Haikun Zhu and   
           Chung-Kuan Cheng and   
                  Ronald Graham   On the construction of zero-deficiency
                                  parallel prefix circuits with minimum
                                  depth  . . . . . . . . . . . . . . . . . 387--409
         Mahmut Taylan Kandemir   Reducing energy consumption of
                                  multiprocessor SoC architectures by
                                  exploiting memory bank locality  . . . . 410--441
                     Fei Su and   
                  Sule Ozev and   
         Krishnendu Chakrabarty   Concurrent testing of digital
                                  microfluidics-based biochips . . . . . . 442--464
              David Atienza and   
            Jose M. Mendias and   
       Stylianos Mamagkakis and   
          Dimitrios Soudris and   
               Francky Catthoor   Systematic dynamic memory management
                                  design methodology for reduced memory
                                  footprint  . . . . . . . . . . . . . . . 465--489
                     Wei Li and   
             Daniel Blakely and   
             Scott Van Sooy and   
                 Keven Dunn and   
                 David Kidd and   
          Robert Rogenmoser and   
                      Dian Zhou   LVS verification across multiple power
                                  domains for a quad-core microprocessor   490--500
          Jason A. Cheatham and   
             John M. Emmert and   
                  Stan Baumgart   A survey of fault tolerant methodologies
                                  for FPGAs  . . . . . . . . . . . . . . . 501--533

ACM Transactions on Design Automation of Electronic Systems
Volume 11, Number 3, July, 2006

                 Massoud Pedram   Introduction to special issue: Novel
                                  paradigms in system-level design . . . . 535--536
           Alessandro Pinto and   
           Alvise Bonivento and   
Allberto L. Sangiovanni-Vincentelli and   
          Roberto Passerone and   
                    Marco Sgroi   System level design paradigms:
                                  Platform-based design and communication
                                  synthesis  . . . . . . . . . . . . . . . 537--563
            Radu Marculescu and   
              Umit Y. Ogras and   
             Nicholas H. Zamora   Computation and communication refinement
                                  for multiprocessor SoC design: a
                                  system-level perspective . . . . . . . . 564--592
                   Paul Pop and   
                 Petru Eles and   
                  Zebo Peng and   
                     Traian Pop   Analysis and optimization of distributed
                                  real-time embedded systems . . . . . . . 593--625
             Prabhat Mishra and   
         Aviral Shrivastava and   
                     Nikil Dutt   Architecture description language
                                  (ADL)-driven software toolkit generation
                                  for architectural exploration of
                                  programmable SOCs  . . . . . . . . . . . 626--658
              Roman Lysecky and   
                 Greg Stitt and   
                    Frank Vahid   Warp Processors  . . . . . . . . . . . . 659--681
                     Fei Su and   
         Krishnendu Chakrabarty   Module placement for fault-tolerant
                                  microfluidics-based biochips . . . . . . 682--710
          Narender Hanchate and   
          Nagarajan Ranganathan   A game-theoretic framework for
                                  multimetric optimization of interconnect
                                  delay, power, and crosstalk noise during
                                  wire sizing  . . . . . . . . . . . . . . 711--739
                  Gang Chen and   
                     Jason Cong   Simultaneous placement with clustering
                                  and duplication  . . . . . . . . . . . . 740--772
            Sanjukta Bhanja and   
Karthikeyan Lingasubramanian and   
                 N. Ranganathan   A stimulus-free graphical probabilistic
                                  switching model for sequential circuits
                                  using dynamic Bayesian networks  . . . . 773--796

ACM Transactions on Design Automation of Electronic Systems
Volume 11, Number 4, October, 2006

                  Aiqun Cao and   
                 Ruibing Lu and   
                    Chen Li and   
                  Cheng-Kok Koh   Postlayout optimization for synthesis of
                                  Domino circuits  . . . . . . . . . . . . 797--821
André C. Nácul and   
                  Tony Givargis   Synthesis of time-constrained
                                  multitasking embedded software . . . . . 822--847
               Kunhyuk Kang and   
              Bipul C. Paul and   
                    Kaushik Roy   Statistical timing analysis using
                                  levelized covariance propagation
                                  considering systematic and random
                                  variations of process parameters . . . . 848--879
                  Wu-An Kuo and   
             Tingting Hwang and   
                 Allen C.-H. Wu   Decomposition of instruction decoders
                                  for low-power designs  . . . . . . . . . 880--889
                  Yi-Yu Liu and   
               Kuo-Hua Wang and   
                 Tingting Hwang   Crosstalk minimization in logic
                                  synthesis for PLAs . . . . . . . . . . . 890--915
           Sezer Gören and   
               F. Joel Ferguson   Test sequence generation for controller
                                  verification and test with high coverage 916--938
              Zhong-Zhen Wu and   
               Shih-Chieh Chang   Multiple wire reconnections based on
                                  implication flow graph . . . . . . . . . 939--952
             Chi-Shong Wang and   
                   Chingwei Yeh   Performance-driven technology mapping
                                  with MSG partition and selective gate
                                  duplication  . . . . . . . . . . . . . . 953--973


ACM Transactions on Design Automation of Electronic Systems
Volume 12, Number 1, January, 2007

               Anup Gangwar and   
            M. Balakrishnan and   
                   Anshul Kumar   Impact of intercluster communication
                                  mechanisms on ILP in clustered VLIW
                                  architectures  . . . . . . . . . . . . . 1:1--1:??
         Nicholas H. Zamora and   
                Xiaoping Hu and   
                Radu Marculescu   System-level performance/power analysis
                                  for platform-based design of multimedia
                                  applications . . . . . . . . . . . . . . 2:1--2:??
             Chiu-Wing Sham and   
         Evangeline F. Y. Young   Area reduction by deadspace utilization
                                  on interconnect optimized floorplan  . . 3:1--3:??
                     Lei Li and   
              Zhanglei Wang and   
         Krishnendu Chakrabarty   Scan-BIST based on cluster analysis and
                                  the encoding of repeating sequences  . . 4:1--4:??
                   Yuan Cai and   
          Marcus T. Schmitz and   
       Bashir M. Al-Hashimi and   
              Sudhakar M. Reddy   Workload-ahead-driven online energy
                                  minimization techniques for
                                  battery-powered embedded systems with
                                  time-constraints . . . . . . . . . . . . 5:1--5:??
                Xinping Zhu and   
                   Sharad Malik   A hierarchical modeling framework for
                                  on-chip communication architectures of
                                  multiprocessing SoCs . . . . . . . . . . 6:1--6:??
         Subhashis Majumder and   
          Susmita Sur-Kolay and   
    Bhargab B. Bhattacharya and   
               Swarup Kumar Das   Hierarchical partitioning of VLSI
                                  floorplans by staircases . . . . . . . . 7:1--7:??
               Jong-Eun Lee and   
               Kiyoung Choi and   
                  Nikil D. Dutt   Instruction set synthesis with efficient
                                  instruction encoding for configurable
                                  processors . . . . . . . . . . . . . . . 8:1--8:??

ACM Transactions on Design Automation of Electronic Systems
Volume 12, Number 2, April, 2007

                     Nikil Dutt   Editorial  . . . . . . . . . . . . . . . 9:1--9:??
                  Chao Wang and   
               Zijiang Yang and   
         Franjo Ivan\vci\'c and   
                    Aarti Gupta   Disjunctive image computation for
                                  software verification  . . . . . . . . . 10:1--10:??
              Bren Mochocki and   
           Xiaobo Sharon Hu and   
                      Gang Quan   Transition-overhead-aware voltage
                                  scheduling for fixed-priority real-time
                                  systems  . . . . . . . . . . . . . . . . 11:1--11:??
            Hongliang Chang and   
           Sachin S. Sapatnekar   Prediction of leakage power under
                                  process uncertainties  . . . . . . . . . 12:1--12:??
              Sumit Mohanty and   
             Viktor K. Prasanna   A model-based extensible framework for
                                  efficient application design using FPGA  13:1--13:??
                 Weiyu Tang and   
             Arun Kejariwal and   
    Alexander V. Veidenbaum and   
              Alexandru Nicolau   A predictive decode filter cache for
                                  reducing power consumption in embedded
                                  processors . . . . . . . . . . . . . . . 14:1--14:??
               Ilya Issenin and   
            Erik Brockmeyer and   
             Miguel Miranda and   
                     Nikil Dutt   DRDU: a data reuse analysis technique
                                  for efficient scratch-pad memory
                                  management . . . . . . . . . . . . . . . 15:1--15:??
      Mohammad Hosseinabady and   
        Pejman Lotfi-Kamran and   
            Zainalabedin Navabi   Low test application time resource
                                  binding for behavioral synthesis . . . . 16:1--16:??
         Mohammed Elshoukry and   
       Mohammad Tehranipoor and   
                C. P. Ravikumar   A critical-path-aware partial gating
                                  approach for test power reduction  . . . 17:1--17:??
             Irith Pomeranz and   
              Sudhakar M. Reddy   Forming N-detection test sets without
                                  test generation  . . . . . . . . . . . . 18:1--18:??
               Hongbing Fan and   
                 Jiping Liu and   
                Yu-Liang Wu and   
              Chak-Chung Cheung   The exact channel density and compound
                                  design for generic universal switch
                                  blocks . . . . . . . . . . . . . . . . . 19:1--19:??

ACM Transactions on Design Automation of Electronic Systems
Volume 12, Number 3, August, 2007

               Sung Kyu Lim and   
                 Massoud Pedram   Introduction to special issue on
                                  demonstrable software systems and
                                  hardware platforms . . . . . . . . . . . 20:1--20:??
               Chia-Jui Hsu and   
               Ming-Yung Ko and   
    Shuvra S. Bhattacharyya and   
            Suren Ramasubbu and   
          José Luis Pino   Efficient simulation of critical
                                  synchronous dataflow graphs  . . . . . . 21:1--21:??
           Fernando Herrera and   
                 Eugenio Villar   A framework for heterogeneous
                                  specification and design of electronic
                                  embedded systems in SystemC  . . . . . . 22:1--22:??
              Hyung Gyu Lee and   
             Naehyuck Chang and   
              Umit Y. Ogras and   
                Radu Marculescu   On-chip communication architecture
                                  exploration: a quantitative evaluation
                                  of point-to-point, bus, and
                                  network-on-chip approaches . . . . . . . 23:1--23:??
                 Soonhoi Ha and   
               Sungchan Kim and   
             Choonseung Lee and   
                Youngmin Yi and   
              Seongnam Kwon and   
                  Young-Pyo Joo   PeaCE: a hardware-software codesign
                                  environment for multimedia embedded
                                  systems  . . . . . . . . . . . . . . . . 24:1--24:??
              David Atienza and   
         Pablo G. Del Valle and   
               Giacomo Paci and   
          Francesco Poletti and   
                Luca Benini and   
        Giovanni De Micheli and   
            Jose M. Mendias and   
                  Roman Hermida   HW-SW emulation framework for
                                  temperature-aware design in MPSoCs . . . 26:1--26:??
                     Wei Wu and   
               Lingling Jin and   
                   Jun Yang and   
                     Pu Liu and   
              Sheldon X.-D. Tan   Efficient power modeling and software
                                  thermal sensing for runtime temperature
                                  monitoring . . . . . . . . . . . . . . . 26:1--26:??
              Po-Kuan Huang and   
                  Soheil Ghiasi   Efficient and scalable compiler-directed
                                  energy optimization for realtime
                                  applications . . . . . . . . . . . . . . 27:1--27:??
                   Yiyu Shi and   
                  Paul Mesa and   
                     Hao Yu and   
                         Lei He   Circuit-simulated obstacle-aware Steiner
                                  routing  . . . . . . . . . . . . . . . . 28:1--28:??
      Lakshmi N. Chakrapani and   
              Pinar Korkmaz and   
          Bilge E. S. Akgul and   
               Krishna V. Palem   Probabilistic system-on-a-chip
                                  architectures  . . . . . . . . . . . . . 29:1--29:??
             Ang-Chih Hsieh and   
               Tzu-Teng Lin and   
           Tsuang-Wei Chang and   
                 Tingting Hwang   A functionality-directed clustering
                                  technique for low-power MTCMOS
                                  design---computation of simultaneously
                                  discharging current  . . . . . . . . . . 30:1--30:??
     Tathagato Rai Dastidar and   
              P. P. Chakrabarti   A verification system for transient
                                  response of analog circuits  . . . . . . 31:1--31:??
              Kai-Hui Chang and   
             Igor L. Markov and   
               Valeria Bertacco   Postplacement rewiring by exhaustive
                                  search for functional symmetries . . . . 32:1--32:??
         Deepak Mathaikutty and   
                Hiren Patel and   
             Sandeep Shukla and   
                   Axel Jantsch   EWD: a metamodeling driven customizable
                                  multi-MoC system modeling framework  . . 33:1--33:??
                 Greg Stitt and   
                    Frank Vahid   Binary synthesis . . . . . . . . . . . . 34:1--34:??
        Michalis D. Galanis and   
      Gregory Dimitroulakos and   
           Spyros Tragoudas and   
               Costas E. Goutis   Speedups in embedded systems with a
                                  high-performance coprocessor datapath    35:1--35:??
             Suchismita Roy and   
          P. P. Chakrabarti and   
                Pallab Dasgupta   Event propagation for accurate circuit
                                  delay calculation using SAT  . . . . . . 36:1--36:??

ACM Transactions on Design Automation of Electronic Systems
Volume 12, Number 4, September, 2007

              Ping-Hung Yuh and   
              Chia-Lin Yang and   
                  Yao-Wen Chang   Temporal floorplanning using the
                                  three-dimensional transitive closure
                                  subGraph . . . . . . . . . . . . . . . . 37:1--37:??
                Jinfeng Liu and   
                    Pai H. Chou   Idle energy minimization by mode
                                  sequence optimization  . . . . . . . . . 38:1--38:??
              Bita Gorjiara and   
          Nader Bagherzadeh and   
                    Pai H. Chou   Ultra-fast and efficient algorithm for
                                  energy optimization by gradient-based
                                  stochastic voltage and task scheduling   39:1--39:??
        Peter Vanbroekhoven and   
             Gerda Janssens and   
         Maurice Bruynooghe and   
               Francky Catthoor   A practical dynamic single assignment
                                  transformation . . . . . . . . . . . . . 40:1--40:??
             Yuki Kobayashi and   
            Murali Jayapala and   
           Praveen Raghavan and   
           Francky Catthoor and   
                  Masaharu Imai   Methodology for operation shuffling and
                                  L0 cluster generation for low energy
                                  heterogeneous VLIW processors  . . . . . 41:1--41:??
                  D. Maslov and   
                G. W. Dueck and   
                   D. M. Miller   Techniques for the synthesis of
                                  reversible Toffoli networks  . . . . . . 42:1--42:??
          Youcef Bouchebaba and   
             Bruno Girodias and   
         Gabriela Nicolescu and   
     El Mostapha Aboulhamid and   
            Bruno Lavigueur and   
                  Pierre Paulin   MPSoC memory optimization using program
                                  transformation . . . . . . . . . . . . . 43:1--43:??
               Dipankar Das and   
          P. P. Chakrabarti and   
                   Rajeev Kumar   Functional verification of task
                                  partitioning for multiprocessor embedded
                                  systems  . . . . . . . . . . . . . . . . 44:1--44:??
             Shih-Hsu Huang and   
                  Yow-Tyng Nieh   Clock skew scheduling with race
                                  conditions considered  . . . . . . . . . 45:1--45:??
                  Gang Wang and   
                Wenrui Gong and   
              Brian Derenzi and   
                   Ryan Kastner   Exploring time/resource trade-offs by
                                  solving dual scheduling problems with
                                  the ant colony optimization  . . . . . . 46:1--46:??
              Swaroop Ghosh and   
              Swarup Bhunia and   
                    Kaushik Roy   Low-Power and Testable Circuit Synthesis
                                  Using Shannon Decomposition  . . . . . . 47:1--47:??
               Chris Ostler and   
            Karam S. Chatha and   
           Vijay Ramamurthi and   
            Krishnan Srinivasan   ILP and heuristic techniques for
                                  system-level design on network processor
                                  architectures  . . . . . . . . . . . . . 48:1--48:??
     Sivaram Gopalakrishnan and   
                  Priyank Kalla   Optimization of polynomial datapaths
                                  using finite ring algebra  . . . . . . . 49:1--49:??
                      Q. Hu and   
           P. G. Kjeldsberg and   
           A. Vandecappelle and   
                M. Palkovic and   
                    F. Catthoor   Incremental hierarchical memory size
                                  estimation for steering of loop
                                  transformations  . . . . . . . . . . . . 50:1--50:??
                Yi-Ping You and   
            Chung-Wen Huang and   
                  Jenq Kuen Lee   Compilation for compact power-gating
                                  controls . . . . . . . . . . . . . . . . 51:1--51:??
                  Gang Chen and   
                Xiaoyu Song and   
                   Feng Liu and   
               Qingping Tan and   
                         Fei He   A note on ``A mapping algorithm for
                                  computer-assisted exploration in the
                                  design of embedded systems'' . . . . . . 52:1--52:??


ACM Transactions on Design Automation of Electronic Systems
Volume 13, Number 1, January, 2008

                     Nikil Dutt   Editorial  . . . . . . . . . . . . . . . 1:1--1:??
           Michael S. Hsiao and   
                Robert B. Jones   Introduction to special section on
                                  high-level design, validation, and test  2:1--2:??
           Gianpiero Cabodi and   
             Marco Murciano and   
               Sergio Nocco and   
                   Stefano Quer   Boosting interpolation with dynamic
                                  localized abstraction and redundancy
                                  removal  . . . . . . . . . . . . . . . . 3:1--3:??
          Marc Boulé and   
                   Zeljko Zilic   Automata-based assertion-checker
                                  synthesis of PSL properties  . . . . . . 4:1--4:??
                 H. Rahaman and   
                  J. Mathew and   
              D. K. Pradhan and   
                    A. M. Jabir   C-testable bit parallel multipliers over
                                  $ {\rm GF}(2^m) $  . . . . . . . . . . . 5:1--5:??
                Sami Taktak and   
       Jean-Lou Desbarbieux and   
            Emmanuelle Encrenaz   A tool for automatic detection of
                                  deadlock in wormhole networks on chip    6:1--6:??
                       Hai Zhou   A new efficient retiming algorithm
                                  derived by formal manipulation . . . . . 7:1--7:??
         Smita Krishnaswamy and   
        George F. Viamontes and   
             Igor L. Markov and   
                  John P. Hayes   Probabilistic transfer matrices in
                                  symbolic reliability analysis of logic
                                  circuits . . . . . . . . . . . . . . . . 8:1--8:??
             Chao-Wen Tzeng and   
            Jheng-Syun Yang and   
                   Shi-Yu Huang   A versatile paradigm for scan chain
                                  diagnosis of complex faults using signal
                                  processing techniques  . . . . . . . . . 9:1--9:??
            F. Ryan Johnson and   
                  Joann M. Paul   Interrupt modeling for efficient
                                  high-level scheduler design space
                                  exploration  . . . . . . . . . . . . . . 10:1--10:??
              Umit Y. Ogras and   
                Radu Marculescu   Analysis and optimization of
                                  prediction-based flow control in
                                  networks-on-chip . . . . . . . . . . . . 11:1--11:??
           Kuei-Chung Chang and   
             Jih-Sheng Shen and   
                   Tien-Fu Chen   Tailoring circuit-switched
                                  network-on-chip to application-specific
                                  system-on-chip by two optimization
                                  schemes  . . . . . . . . . . . . . . . . 12:1--12:??
                A. Abbasian and   
                  S. Hatami and   
            A. Afzali-Kusha and   
                      M. Pedram   Wavelet-based dynamic power management
                                  for nonstationary service requests . . . 13:1--13:??
                 Yu-Shih Su and   
             Po-Hsien Chang and   
           Shih-Chieh Chang and   
                 Tingting Hwang   Synthesis of a novel timing-error
                                  detection architecture . . . . . . . . . 14:1--14:??
              Andreas Raabe and   
        Philipp A. Hartmann and   
              Joachim K. Anlauf   ReChannel: Describing and simulating
                                  reconfigurable hardware in systemC . . . 15:1--15:??
             Xiangrong Zhou and   
                 Chenjie Yu and   
               Alokika Dash and   
                   Peter Petrov   Application-aware snoop filtering for
                                  low-power cache coherence in embedded
                                  multiprocessors  . . . . . . . . . . . . 16:1--16:??
                Yongjin Ahn and   
                Keesung Han and   
                Ganghee Lee and   
               Hyunjik Song and   
                 Junhee Yoo and   
               Kiyoung Choi and   
                 Xingguang Feng   SoCDAL: System-on-chip design
                                  AcceLerator  . . . . . . . . . . . . . . 17:1--17:??
         Nicholas H. Zamora and   
                Xiaoping Hu and   
              Umit Y. Ogras and   
                Radu Marculescu   Enabling multimedia using
                                  resource-constrained video processing
                                  techniques: a node-centric perspective   18:1--18:??
               Kyungsoo Lee and   
             Naehyuck Chang and   
                Jianli Zhuo and   
       Chaitali Chakrabarti and   
           Sudheendra Kadri and   
                 Sarma Vrudhula   A fuel-cell-battery hybrid for portable
                                  embedded systems . . . . . . . . . . . . 19:1--19:??
             Wei-Chung Chao and   
                    Wai-Kei Mak   Low-power gated and buffered clock
                                  network construction . . . . . . . . . . 20:1--20:??
             Chiu-Wing Sham and   
     Evangeline F. Y. Young and   
                       Hai Zhou   Optimizing wirelength and routability by
                                  searching alternative packings in
                                  floorplanning  . . . . . . . . . . . . . 21:1--21:??
              Meng-Chiou Wu and   
               Rung-Bin Lin and   
                Shih-Cheng Tsai   Chip placement in a reticle for
                                  multiple-project wafer fabrication . . . 22:1--22:??

ACM Transactions on Design Automation of Electronic Systems
Volume 13, Number 2, April, 2008

                     Nikil Dutt   Editorial  . . . . . . . . . . . . . . . 23:1--23:??
              Nikhil Saluja and   
           Kanupriya Gulati and   
                Sunil P. Khatri   SAT-based ATPG using multilevel
                                  compatible don't-cares . . . . . . . . . 24:1--24:??
    Kishore Kumar Muchherla and   
               Pinhong Chen and   
               Dongsheng Ma and   
             Janet Meiling Wang   A noniterative equivalent waveform model
                                  for timing analysis in presence of
                                  crosstalk  . . . . . . . . . . . . . . . 25:1--25:??
                    Jin-Tai Yan   Timing-driven octilinear Steiner tree
                                  construction based on Steiner-point
                                  reassignment and path reconstruction . . 26:1--26:??
        Alexandro Baldassin and   
         Paulo Centoducatte and   
                Sandro Rigo and   
           Daniel Casarotto and   
          Luiz C. V. Santos and   
                Max Schultz and   
                 Olinto Furtado   An open-source binary utility generator  27:1--27:??
              James Moscola and   
           John W. Lockwood and   
                   Young H. Cho   Reconfigurable content-based router
                                  using hardware-accelerated language
                                  parser . . . . . . . . . . . . . . . . . 28:1--28:??
              Alex K. Jones and   
          Swapna Dontharaju and   
              Shenchih Tung and   
                   Leo Mats and   
          Peter J. Hawrylak and   
           Raymond R. Hoare and   
              James T. Cain and   
               Marlin H. Mickle   Radio frequency identification
                                  prototyping  . . . . . . . . . . . . . . 29:1--29:??
                      Yu Hu and   
                    Yan Lin and   
                     Lei He and   
                       Tim Tuan   Physical synthesis for FPGA interconnect
                                  power reduction by dual-Vdd budgeting
                                  and retiming . . . . . . . . . . . . . . 30:1--30:??
             Iyad Al Khatib and   
          Francesco Poletti and   
            Davide Bertozzi and   
                Luca Benini and   
            Mohamed Bechara and   
             Hasan Khalifeh and   
               Axel Jantsch and   
                  Rustam Nabiev   A multiprocessor system-on-chip for
                                  real-time biomedical monitoring and
                                  analysis: ECG prototype architectural
                                  design space exploration . . . . . . . . 31:1--31:??
             Xiangrong Zhou and   
                   Peter Petrov   Heterogeneously tagged caches for
                                  low-power embedded systems with virtual
                                  memory support . . . . . . . . . . . . . 32:1--32:??
                   Fang Liu and   
                  Sule Ozev and   
              Plamen K. Nikolov   Parametric variability analysis for
                                  multistage analog circuits using
                                  analytical sensitivity modeling  . . . . 33:1--33:??
                  Lei Cheng and   
                Deming Chen and   
              Martin D. F. Wong   A fast simultaneous input vector
                                  generation and gate replacement
                                  algorithm for leakage power reduction    34:1--34:??
            Anna Bernasconi and   
          Valentina Ciriani and   
                Roberto Cordone   The optimization of kEP-SOPs:
                                  Computational complexity,
                                  approximability and experiments  . . . . 35:1--35:??
              R. Iris Bahar and   
         Krishnendu Chakrabarty   Introduction to joint ACM JETC/TODAES
                                  special issue on new, emerging, and
                                  specialized technologies . . . . . . . . 36:1--36:??

ACM Transactions on Design Automation of Electronic Systems
Volume 13, Number 3, July, 2008

                     Nikil Dutt   Editorial  . . . . . . . . . . . . . . . 37:1--37:??
              Alex K. Jones and   
                  Robert Walker   Introduction to the special section on
                                  demonstrable software systems and
                                  hardware platforms II  . . . . . . . . . 38:1--38:??
              Seongnam Kwon and   
                Yongjoo Kim and   
              Woo-Chul Jeun and   
                 Soonhoi Ha and   
                  Yunheung Paek   A retargetable parallel-programming
                                  framework for MPSoC  . . . . . . . . . . 39:1--39:??
                Akash Kumar and   
           Shakith Fernando and   
                   Yajun Ha and   
                Bart Mesman and   
                 Henk Corporaal   Multiprocessor systems synthesis for
                                  multiple use-cases of multiple
                                  applications on FPGA . . . . . . . . . . 40:1--40:??
           Ronny Krashinsky and   
         Christopher Batten and   
               Krste Asanovi\'c   Implementing the Scale vector-thread
                                  processor  . . . . . . . . . . . . . . . 41:1--41:??
             Prabhat Mishra and   
                     Nikil Dutt   Specification-driven directed test
                                  generation for validation of pipelined
                                  processors . . . . . . . . . . . . . . . 42:1--42:??
                Yongsoo Joo and   
               Youngjin Cho and   
               Donghwa Shin and   
               Jaehyun Park and   
                 Naehyuck Chang   An energy characterization platform for
                                  memory devices and energy-aware data
                                  compression for multilevel-cell flash
                                  memory . . . . . . . . . . . . . . . . . 43:1--43:??
               Ted Huffmire and   
           Brett Brotherton and   
             Nick Callegari and   
          Jonathan Valamehr and   
                 Jeff White and   
               Ryan Kastner and   
                   Tim Sherwood   Designing secure systems on
                                  reconfigurable hardware  . . . . . . . . 44:1--44:??
        Panagiotis Manolios and   
        Sudarshan K. Srinivasan   Automatic verification of safety and
                                  liveness for pipelined machines using
                                  WEB refinement . . . . . . . . . . . . . 45:1--45:??
                 Huaizhi Wu and   
          Martin D. F. Wong and   
                   Wilsin Gosti   Postplacement voltage assignment under
                                  performance constraints  . . . . . . . . 46:1--46:??
            Nicola Bombieri and   
               Franco Fummi and   
            Graziano Pravadelli   Reuse and optimization of testbenches
                                  and properties in a TLM-to-RTL design
                                  flow . . . . . . . . . . . . . . . . . . 47:1--47:??
              Hiroaki Inoue and   
                Junji Sakai and   
                 Masato Edahiro   Processor virtualization for secure
                                  mobile terminals . . . . . . . . . . . . 48:1--48:??
     Concepción Sanz and   
              Manuel Prieto and   
José Ignacio Gómez and   
       Antonis Papanikolaou and   
             Miguel Miranda and   
               Francky Catthoor   Combining system scenarios and
                                  configurable memories to tolerate
                                  unpredictability . . . . . . . . . . . . 49:1--49:??
               Ozcan Ozturk and   
                Mahmut Kandemir   ILP-based energy minimization techniques
                                  for banked memories  . . . . . . . . . . 50:1--50:??
             Sabyasachi Das and   
                Sunil P. Khatri   Resource sharing among mutually
                                  exclusive sum-of-product blocks for area
                                  reduction  . . . . . . . . . . . . . . . 51:1--51:??
                I-Lun Tseng and   
                   Adam Postula   Partitioning parameterized 45-degree
                                  polygons with constraint programming . . 52:1--52:??
               Anuja Sehgal and   
      Sudarshan Bahukudumbi and   
         Krishnendu Chakrabarty   Power-aware SoC test planning for
                                  effective utilization of port-scalable
                                  testers  . . . . . . . . . . . . . . . . 53:1--53:??
              Tomas Pecenka and   
             Lukas Sekanina and   
                 Zdenek Kotasek   Evolution of synthetic RTL benchmark
                                  circuits with predefined testability . . 54:1--54:??

ACM Transactions on Design Automation of Electronic Systems
Volume 13, Number 4, September, 2008

                 Massoud Pedram   Editorial  . . . . . . . . . . . . . . . 55:1--55:??
                   Nan Guan and   
                Qingxu Deng and   
                 Zonghua Gu and   
                  Wenyao Xu and   
                          Ge Yu   Schedulability analysis of preemptive
                                  and nonpreemptive EDF on partial
                                  runtime-reconfigurable FPGAs . . . . . . 56:1--56:??
         Rajarshi Mukherjee and   
                   Song Liu and   
         Seda Ogrenci Memik and   
               Somsubhra Mondal   A high-level clustering algorithm
                                  targeting dual V$_{dd}$ FPGAs  . . . . . 57:1--57:??
              Javier Resano and   
      Juan Antonio Clemente and   
            Carlos Gonzalez and   
               Daniel Mozos and   
               Francky Catthoor   Efficiently scheduling runtime
                                  reconfigurations . . . . . . . . . . . . 58:1--58:??
             Siddharth Garg and   
               Diana Marculescu   System-level throughput analysis for
                                  process variation aware multiple
                                  voltage-frequency island designs . . . . 59:1--59:??
               Ozcan Ozturk and   
            Mahmut Kandemir and   
                   Guangyu Chen   Access pattern-based code compression
                                  for memory-constrained systems . . . . . 60:1--60:??
         Nastaran Baradaran and   
                 Pedro C. Diniz   A compiler approach to managing storage
                                  and memory bandwidth in configurable
                                  architectures  . . . . . . . . . . . . . 61:1--61:??
           Ansuman Banerjee and   
            Pallab Dasgupta and   
              P. P. Chakrabarti   Auxiliary state machines +
                                  context-triggered properties in
                                  verification . . . . . . . . . . . . . . 62:1--62:??
                S. K. Panda and   
                  Arnab Roy and   
          P. P. Chakrabarti and   
                   Rajeev Kumar   Simulation-based verification using
                                  Temporally Attributed Boolean Logic  . . 63:1--63:??
            Sying-Jyan Wang and   
               Kuo-Lin Peng and   
           Kuang-Cyun Hsiao and   
           Katherine Shu-Min Li   Layout-aware scan chain reorder for
                                  launch-off-shift transition test
                                  coverage . . . . . . . . . . . . . . . . 64:1--64:??
         Konstantin Moiseev and   
            Avinoam Kolodny and   
                   Shmuel Wimer   Timing-aware power-optimal ordering of
                                  signals  . . . . . . . . . . . . . . . . 65:1--65:??
               Chao-Hung Lu and   
             Hung-Ming Chen and   
            Chien-Nan Jimmy Liu   Effective decap insertion in area-array
                                  SoC floorplan design . . . . . . . . . . 66:1--66:??
         Michael D. Moffitt and   
              Jarrod A. Roy and   
             Igor L. Markov and   
              Martha E. Pollack   Constraint-driven floorplan repair . . . 67:1--67:??
     Muhammet Mustafa Ozdal and   
          Martin D. F. Wong and   
            Philip S. Honsinger   Optimal routing algorithms for
                                  rectilinear pin clusters in high-density
                                  multichip modules  . . . . . . . . . . . 68:1--68:??


ACM Transactions on Design Automation of Electronic Systems
Volume 14, Number 1, January, 2009

            Joachim Keinert and   
      Martin Streubühr and   
          Thomas Schlichter and   
               Joachim Falk and   
              Jens Gladigau and   
          Christian Haubelt and   
          Jürgen Teich and   
               Michael Meredith   SystemCoDesigner --- an automatic ESL
                                  synthesis approach by design space
                                  exploration and behavioral synthesis for
                                  streaming applications . . . . . . . . . 1:1--1:??
            Andreas Hansson and   
              Kees Goossens and   
              Marco Bekooij and   
                    Jos Huisken   CoMPSoC: a template for composable and
                                  predictable multi-processor system on
                                  chips  . . . . . . . . . . . . . . . . . 2:1--2:??
 Stefan Valentin Gheorghita and   
            Martin Palkovic and   
                Juan Hamers and   
       Arnout Vandecappelle and   
         Stelios Mamagkakis and   
                Twan Basten and   
            Lieven Eeckhout and   
             Henk Corporaal and   
           Francky Catthoor and   
        Frederik Vandeputte and   
              Koen De Bosschere   System-scenario-based design of dynamic
                                  embedded systems . . . . . . . . . . . . 3:1--3:??
                   Qiang Xu and   
                Yubin Zhang and   
         Krishnendu Chakrabarty   SOC test-architecture optimization for
                                  the testing of embedded cores and
                                  signal-integrity faults on core-external
                                  interconnects  . . . . . . . . . . . . . 4:1--4:??
               Zhong-Yi Jin and   
             Curt Schurgers and   
                Rajesh K. Gupta   A gateway node with duty-cycled radio
                                  and processing subsystems for wireless
                                  sensor networks  . . . . . . . . . . . . 5:1--5:??
                  Chin-Hsien Wu   An energy-efficient I/O request
                                  mechanism for multi-bank flash-memory
                                  storage systems  . . . . . . . . . . . . 6:1--6:??
          Swapna Dontharaju and   
              Shenchih Tung and   
              James T. Cain and   
                Leonid Mats and   
           Marlin H. Mickle and   
                  Alex K. Jones   A design automation and power estimation
                                  flow for RFID systems  . . . . . . . . . 7:1--7:??
                     Ali Dasdan   Provably efficient algorithms for
                                  resolving temporal and spatial
                                  difference constraint violations . . . . 8:1--8:??
                Arnab Sinha and   
            Pallab Dasgupta and   
                Bhaskar Pal and   
               Sayantan Das and   
             Prasenjit Basu and   
              P. P. Chakrabarti   Design intent coverage revisited . . . . 9:1--9:??
               Zijiang Yang and   
                  Chao Wang and   
                Aarti Gupta and   
            Franjo Ivanv\vci\'c   Model checking sequential software
                                  programs via mixed symbolic analysis . . 10:1--10:??
              Gayatri Mehta and   
             Justin Stander and   
                Mustafa Baz and   
             Brady Hunsaker and   
                  Alex K. Jones   Interconnect customization for a
                                  hardware fabric  . . . . . . . . . . . . 11:1--11:??
             Chiu-Wing Sham and   
     Evangeline F. Y. Young and   
                     Jingwei Lu   Congestion prediction in early stages of
                                  physical design  . . . . . . . . . . . . 12:1--12:??
                     Yi Zhu and   
                Yuanfang Hu and   
          Michael B. Taylor and   
               Chung-Kuan Cheng   Energy and switch area optimizations for
                                  FPGA global routing architectures  . . . 13:1--13:??
             Shih-Hsu Huang and   
            Chia-Ming Chang and   
                  Yow-Tyng Nieh   Opposite-phase register switching for
                                  peak current minimization  . . . . . . . 14:1--14:??
               Yen-Chun Lin and   
                   Li-Ling Hung   Straightforward construction of
                                  depth-size optimal, parallel prefix
                                  circuits with fan-out 2  . . . . . . . . 15:1--15:??
            Andrew B. Kahng and   
             Chul-Hong Park and   
              Puneet Sharma and   
                     Qinke Wang   Lens aberration aware placement for
                                  timing yield . . . . . . . . . . . . . . 16:1--16:??
              Chih-Da Chien and   
             Cheng-An Chien and   
               Jui-Chin Chu and   
                Jiun-In Guo and   
                Ching-Hwa Cheng   A 252Kgates/4.9Kbytes SRAM/71mW
                                  multistandard video decoder for high
                                  definition video applications  . . . . . 17:1--17:??
            Pedro Reviriego and   
           Juan Antonio Maestro   Efficient error detection codes for
                                  multiple-bit upset correction in SRAMs
                                  with BICS  . . . . . . . . . . . . . . . 18:1--18:??

ACM Transactions on Design Automation of Electronic Systems
Volume 14, Number 2, March, 2009

                   K. Avnit and   
                 V. D'silva and   
                  A. Sowmya and   
                  S. Ramesh and   
                S. Parameswaran   Provably correct on-chip communication:
                                  a formal approach to automatic protocol
                                  converter synthesis  . . . . . . . . . . 19:1--19:??
            Sudeep Pasricha and   
            Young-Hwan Park and   
                 Nikil Dutt and   
                Fadi J. Kurdahi   System-level PVT variation-aware power
                                  exploration of on-chip communication
                                  architectures  . . . . . . . . . . . . . 20:1--20:??
       Rajdeep Mukhopadhyay and   
                S. K. Panda and   
            Pallab Dasgupta and   
                     John Gough   Instrumenting AMS assertion verification
                                  on commercial platforms  . . . . . . . . 21:1--21:??
            Martin Palkovic and   
           Francky Catthoor and   
                 Henk Corporaal   Trade-offs in loop transformations . . . 22:1--22:??
               Franco Fummi and   
                Mirko Loghi and   
            Massimo Poncino and   
            Graziano Pravadelli   A cosimulation methodology for HW/SW
                                  validation and performance estimation    23:1--23:??
              Hiroaki Inoue and   
               Tsuyoshi Abe and   
          Kazuhisa Ishizaka and   
                Junji Sakai and   
                 Masato Edahiro   Dynamic security domain scaling on
                                  embedded symmetric multiprocessors . . . 24:1--24:??
                Meikang Qiu and   
                Edwin H.-M. Sha   Cost minimization while satisfying
                                  hard/soft timing constraints for
                                  heterogeneous embedded systems . . . . . 25:1--25:??
             Xiangrong Zhou and   
                 Chenjie Yu and   
                   Peter Petrov   Temperature-aware register reallocation
                                  for register file power-density
                                  minimization . . . . . . . . . . . . . . 26:1--26:??
                 Yu-Ru Hong and   
                Juinn-Dar Huang   Reducing fault dictionary size for
                                  million-gate large circuits  . . . . . . 27:1--27:??
  Xrysovalantis Kavousianos and   
           Dimitris Bakalis and   
               Dimitris Nikolos   Efficient partial scan cell gating for
                                  low-power scan-based testing . . . . . . 28:1--28:??
                Daler Rakhmatov   Battery voltage modeling for portable
                                  systems  . . . . . . . . . . . . . . . . 29:1--29:??
               Yokesh Kumar and   
                Prosenjit Gupta   External memory layout vs. schematic . . 30:1--30:??
               Po-Yuan Chen and   
              Kuan-Hsien Ho and   
                 Tingting Hwang   Skew-aware polarity assignment in clock
                                  tree . . . . . . . . . . . . . . . . . . 31:1--31:??
                 Minsik Cho and   
                 Katrina Lu and   
                   Kun Yuan and   
                   David Z. Pan   BoxRouter 2.0: a hybrid and robust
                                  global router with layer assignment for
                                  routability  . . . . . . . . . . . . . . 32:1--32:??
           Kanupriya Gulati and   
               Suganth Paul and   
            Sunil P. Khatri and   
             Srinivas Patil and   
                    Abhijit Jas   FPGA-based hardware acceleration for
                                  Boolean satisfiability . . . . . . . . . 33:1--33:??

ACM Transactions on Design Automation of Electronic Systems
Volume 14, Number 3, May, 2009

              Avinash Malik and   
               Zoran Salcic and   
                 Partha S. Roop   SystemJ compilation using the Tandem
                                  Virtual Machine approach . . . . . . . . 34:1--34:??
                 Jason Cong and   
                 Yiping Fan and   
                     Junjuan Xu   Simultaneous resource binding and
                                  interconnection optimization based on a
                                  distributed register-file
                                  microarchitecture  . . . . . . . . . . . 35:1--35:??
           Praveen Raghavan and   
            Murali Jayapala and   
            Andy Lambrechts and   
                Javed Absar and   
               Francky Catthoor   Playing the trade-off game: Architecture
                                  exploration using Coffeee  . . . . . . . 36:1--36:??
               Dipankar Das and   
          P. P. Chakrabarti and   
                   Rajeev Kumar   Scenario-based timing verification of
                                  multiprocessor embedded applications . . 37:1--37:??
            Philippe Grosse and   
                Yves Durand and   
                 Paul Feautrier   Methods for power optimization in
                                  SOC-based data flow systems  . . . . . . 38:1--38:??
         Jonathan A. Clarke and   
   George A. Constantinides and   
             Peter Y. K. Cheung   Word-length selection for power
                                  minimization via nonlinear optimization  39:1--39:??
         P. Marques Morgado and   
            Paulo F. Flores and   
             L. Miguel Silveira   Generating realistic stimuli for
                                  accurate power grid analysis . . . . . . 40:1--40:??
                     Hao Yu and   
                  Joanna Ho and   
                         Lei He   Allocating power ground vias in $3$D ICs
                                  for simultaneous power and thermal
                                  integrity  . . . . . . . . . . . . . . . 41:1--41:??
                     Bo Liu and   
Francisco V. Fernández and   
             Georges Gielen and   
     R. Castro-López and   
                        E. Roca   A memetic approach to the automatic
                                  design of high-performance analog
                                  integrated circuits  . . . . . . . . . . 42:1--42:??
                   Madhu Mutyam   Selective shielding technique to
                                  eliminate crosstalk transitions  . . . . 43:1--43:??
               Baris Taskin and   
              Joseph Demaio and   
                Owen Farell and   
          Michael Hazeltine and   
                    Ryan Ketner   Custom topology rotary clock router with
                                  tree subnetworks . . . . . . . . . . . . 44:1--44:??
              Chih-Hung Liu and   
               Shih-Yi Yuan and   
                 Sy-Yen Kuo and   
                   Szu-Chi Wang   High-performance obstacle-avoiding
                                  rectilinear Steiner tree construction    45:1--45:??
                    Tan Yan and   
              Martin D. F. Wong   Theories and algorithms on single-detour
                                  routing for untangling twisted bus . . . 46:1--46:??

ACM Transactions on Design Automation of Electronic Systems
Volume 14, Number 4, August, 2009

     Sivaram Gopalakrishnan and   
                  Priyank Kalla   2009 ACM TODAES best paper award:
                                  Optimization of polynomial datapaths
                                  using finite ring algebra  . . . . . . . 47:1--47:??
              Peter Bertels and   
                Wim Heirman and   
           Erik D'Hollander and   
                Dirk Stroobandt   Efficient memory management for hardware
                                  accelerated Java Virtual Machines  . . . 48:1--48:??
             Miad Faezipour and   
            Mehrdad Nourani and   
                 Rina Panigrahy   A hardware platform for efficient worm
                                  outbreak detection . . . . . . . . . . . 49:1--49:??
              Byunghyun Lee and   
              Ki-Seok Chung and   
                 Bontae Koo and   
              Nak-Woong Eum and   
                    Taewhan Kim   Thermal sensor allocation and placement
                                  for reconfigurable systems . . . . . . . 50:1--50:??
              Ping-Hung Yuh and   
              Chia-Lin Yang and   
                  Yao-Wen Chang   T-trees: a tree-based representation for
                                  temporal and three-dimensional
                                  floorplanning  . . . . . . . . . . . . . 51:1--51:??
              Ping-Hung Yuh and   
              Chia-Lin Yang and   
                Chi-Feng Li and   
               Chung-Hsiang Lin   Leakage-aware task scheduling for
                                  partially dynamically reconfigurable
                                  FPGAs  . . . . . . . . . . . . . . . . . 52:1--52:??
               Po-Yuan Chen and   
            Chiao-Chen Fang and   
             Tingting Hwang and   
                     Hsi-Pin Ma   Leakage reduction, delay compensation
                                  using partition-based tunable
                                  body-biasing techniques  . . . . . . . . 53:1--53:??
      Nagarajan Ranganathan and   
               Upavan Gupta and   
        Venkataraman Mahalingam   Variation-aware multimetric optimization
                                  during gate sizing . . . . . . . . . . . 54:1--54:??
         Konstantin Moiseev and   
            Avinoam Kolodny and   
                   Shmuel Wimer   Power-delay optimization in VLSI
                                  microprocessors by wire spacing  . . . . 55:1--55:??
               Piet Engelke and   
               Bernd Becker and   
            Michel Renovell and   
         Juergen Schloeffel and   
          Bettina Braitling and   
                    Ilia Polian   SUPERB: Simulator Utilizing Parallel
                                  Evaluation of Resistive Bridges  . . . . 56:1--56:??


ACM Transactions on Design Automation of Electronic Systems
Volume 15, Number 1, December, 2009

               Li-Pin Chang and   
                     Chun-Da Du   Design and implementation of an
                                  efficient wear-leveling algorithm for
                                  solid-state-disk microcontrollers  . . . 6:1--6:??
                Bert Geelen and   
       Vissarion Ferentinos and   
           Francky Catthoor and   
           Gauthier Lafruit and   
           Diederik Verkest and   
            Rudy Lauwereins and   
              Thanos Stouraitis   Spatial locality exploitation for
                                  runtime reordering of JPEG2000 wavelet
                                  data layouts . . . . . . . . . . . . . . 8:1--8:??
               Kurt Keutzer and   
                    Peng Li and   
                   Li Shang and   
                       Hai Zhou   ACM Transactions on Design Automation of
                                  Electronic Systems (TODAES) special
                                  section call for papers: Parallel CAD:
                                  Algorithm design and programming . . . . 9:1--9:??
                Jaehyun Kim and   
                 Chungki Oh and   
                  Youngsoo Shin   Minimizing leakage power of sequential
                                  circuits through mixed-$ V_t $
                                  flip-flops and multi-$ V_t $
                                  combinational gates  . . . . . . . . . . 4:1--4:??
                Jingqing Mu and   
                  Roman Lysecky   Autonomous hardware/software
                                  partitioning and voltage/frequency
                                  scaling for low-power embedded systems   2:1--2:??
             Irith Pomeranz and   
              Sudhakar M. Reddy   Using stuck-at tests to form scan-based
                                  tests for transition faults in
                                  standard-scan circuits . . . . . . . . . 7:1--7:??
              Rajeev R. Rao and   
                Vivek Joshi and   
               David Blaauw and   
               Dennis Sylvester   Circuit optimization techniques to
                                  mitigate the effects of soft errors in
                                  combinational logic  . . . . . . . . . . 5:1--5:??
        Christophe Wolinski and   
       Krzysztof Kuchcinski and   
                   Erwan Raffin   Automatic design of application-specific
                                  reconfigurable processor extensions with
                                  UPaK synthesis kernel  . . . . . . . . . 1:1--1:??
               Meng-Chen Wu and   
              Ming-Ching Lu and   
             Hung-Ming Chen and   
                  Jing-Yang Jou   Performance-constrained voltage
                                  assignment in multiple supply voltage
                                  SoC floorplanning  . . . . . . . . . . . 3:1--3:??

ACM Transactions on Design Automation of Electronic Systems
Volume 15, Number 2, February, 2010

           Gianpiero Cabodi and   
            Luciano Lavagno and   
             Marco Murciano and   
            Alex Kondratyev and   
              Yosinori Watanabe   Speeding-up heuristic allocation,
                                  scheduling and binding with SAT-based
                                  abstraction/refinement techniques  . . . 12:1--12:??
             Naehyuck Chang and   
               Jörg Henkel   Call for papers: ACM Transactions on
                                  Design Automation of Electronic Systems
                                  (TODAES) special section on low-power
                                  electronics and design . . . . . . . . . 20:1--20:??
               Dipankar Das and   
          P. P. Chakrabarti and   
                   Rajeev Kumar   Thermal analysis of multiprocessor SoC
                                  applications by simulation and
                                  verification . . . . . . . . . . . . . . 15:1--15:??
             Peter Jamieson and   
              Tobias Becker and   
         Peter Y. K. Cheung and   
                  Wayne Luk and   
                 Tero Rissa and   
            Teemu Pitkänen   Benchmarking and evaluating
                                  reconfigurable architectures targeting
                                  the mobile domain  . . . . . . . . . . . 14:1--14:??
          Masanori Kurimoto and   
             Hiroaki Suzuki and   
                Rei Akiyama and   
             Tadao Yamanaka and   
            Haruyuki Ohkuma and   
            Hidehiro Takata and   
             Hirofumi Shinohara   Phase-adjustable error detection
                                  flip-flops with 2-stage hold-driven
                                  optimization, slack-based grouping
                                  scheme and slack distribution control
                                  for dynamic voltage scaling  . . . . . . 17:1--17:??
              Seongnam Kwon and   
                     Soonhoi Ha   Serialized parallel code generation
                                  framework for MPSoC  . . . . . . . . . . 11:1--11:??
                     Duo Li and   
          Sheldon X.-D. Tan and   
         Eduardo H. Pacheco and   
                 Murli Tirumala   Parameterized architecture-level dynamic
                                  thermal models for multicore
                                  microprocessors  . . . . . . . . . . . . 16:1--16:??
               Somnath Paul and   
             Hamid Mahmoodi and   
                  Swarup Bhunia   Low-overhead $ F_{\hbox {max}} $
                                  calibration at multiple operating points
                                  using delay-sensitivity-based path
                                  selection  . . . . . . . . . . . . . . . 19:1--19:??
            Pedro Reviriego and   
       Juan Antonio Maestro and   
              Chris J. Bleakley   Reliability analysis of memories
                                  protected with BICS and a per-word
                                  parity bit . . . . . . . . . . . . . . . 18:1--18:??
             Gunar Schirner and   
         Andreas Gerstlauer and   
              Rainer Dömer   Fast and accurate processor models for
                                  efficient MPSoC design . . . . . . . . . 10:1--10:??
              Mingxuan Yuan and   
                 Zonghua Gu and   
                Xiuqiang He and   
                    Xue Liu and   
                      Lei Jiang   Hardware/software partitioning and
                                  pipelined scheduling on runtime
                                  reconfigurable FPGAs . . . . . . . . . . 13:1--13:??

ACM Transactions on Design Automation of Electronic Systems
Volume 15, Number 3, May, 2010

              Nicolas Blanc and   
                Daniel Kroening   Race analysis for SystemC using model
                                  checking . . . . . . . . . . . . . . . . 21:1--21:??
               Waseem Ahmed and   
                  Douglas Myers   Concept-based partitioning for large
                                  multidomain multifunctional embedded
                                  systems  . . . . . . . . . . . . . . . . 22:1--22:??
                R. K. Raval and   
            C. H. Fernandez and   
                 C. J. Bleakley   Low-power TinyOS tuned processor
                                  platform for wireless sensor network
                                  motes  . . . . . . . . . . . . . . . . . 23:1--23:??
                  Xuan Guan and   
                      Yunsi Fei   Register file partitioning and
                                  recompilation for register file power
                                  reduction  . . . . . . . . . . . . . . . 24:1--24:??
                 Yufu Zhang and   
           Ankur Srivastava and   
                 Mohamed Zahran   On-chip sensor-driven efficient thermal
                                  profile estimation algorithms  . . . . . 25:1--25:??
              Kai-Hui Chang and   
           Valeria Bertacco and   
             Igor L. Markov and   
                Alan Mishchenko   Logic synthesis and circuit
                                  customization using extensive external
                                  don't-cares  . . . . . . . . . . . . . . 26:1--26:??
               Shenghua Liu and   
              Guoqiang Chen and   
              Tom Tong Jing and   
                     Lei He and   
                 Robi Dutta and   
                 Xian-Long Hong   Effective congestion reduction for IC
                                  package substrate routing  . . . . . . . 27:1--27:??

ACM Transactions on Design Automation of Electronic Systems
Volume 15, Number 4, September, 2010

              Youngsoo Shin and   
                 Jun Seomun and   
             Kyu-Myung Choi and   
               Takayasu Sakurai   Power gating: Circuits, design
                                  methodologies, and best practice for
                                  standard-cell VLSI designs . . . . . . . 28:1--28:??
              Cheng-Juei Yu and   
                 Yi-Hsin Wu and   
                  Sheng-De Wang   An in-place search algorithm for the
                                  resource constrained scheduling problem
                                  during high-level synthesis  . . . . . . 29:1--29:??
              Kyoungwoo Lee and   
         Aviral Shrivastava and   
                 Nikil Dutt and   
      Nalini Venkatasubramanian   Partitioning techniques for partially
                                  protected caches in resource-constrained
                                  embedded systems . . . . . . . . . . . . 30:1--30:??
                Talal Bonny and   
               Jörg Henkel   Huffman-based code compression
                                  techniques for embedded processors . . . 31:1--31:??
                 Zhifang Li and   
                Wenjian Luo and   
                  Lihua Yue and   
                      Xufa Wang   On the completeness of the polymorphic
                                  gate set . . . . . . . . . . . . . . . . 32:1--32:??
               Renshen Wang and   
           Evangeline Young and   
               Chung-Kuan Cheng   Complexity of $3$-D floorplans by
                                  analysis of graph cuboidal dual hardness 33:1--33:??


ACM Transactions on Design Automation of Electronic Systems
Volume 16, Number 1, November, 2010

             Naehyuck Chang and   
               Jörg Henkel   Guest Editorial: Current Trends in
                                  Low-Power Design . . . . . . . . . . . . 1:1--1:??
                  David Bol and   
              Denis Flandre and   
              Jean-Didier Legat   Nanometer MOSFET Effects on the
                                  Minimum-Energy Point of Sub-45nm
                                  Subthreshold Logic---Mitigation at
                                  Technology and Circuit Levels  . . . . . 2:1--2:??
            Andrea Calimera and   
               Enrico Macii and   
                Massimo Poncino   NBTI-Aware Clustered Power Gating  . . . 3:1--3:??
                 Jason Cong and   
                    Bin Liu and   
             Rupak Majumdar and   
                    Zhiru Zhang   Behavior-Level Observability Analysis
                                  for Operation Gating in Low-Power
                                  Behavioral Synthesis . . . . . . . . . . 4:1--4:??
     Thorlindur Thorolfsson and   
             Samson Melamed and   
             W. Rhett Davis and   
                Paul D. Franzon   Low-Power Hypercube Divided Memory FFT
                                  Engine Using $3$D Integration  . . . . . 5:1--5:??
              Gaurav Dhiman and   
          Giacomo Marchetti and   
                  Tajana Rosing   vGreen: a System for Energy-Efficient
                                  Management of Virtual Machines . . . . . 6:1--6:??
                 Jinsik Kim and   
                    Pai H. Chou   Energy-Efficient Progressive Remote
                                  Update for Flash-Based Firmware of
                                  Networked Embedded Systems . . . . . . . 7:1--7:??
                 Chenjie Yu and   
                   Peter Petrov   Energy- and Performance-Efficient
                                  Communication Framework for Embedded
                                  MPSoCs through Application-Driven
                                  Release Consistency  . . . . . . . . . . 8:1--8:??
           Nikhil Jayakumar and   
                Sunil P. Khatri   A Simultaneous Input Vector Control and
                                  Circuit Modification Technique to Reduce
                                  Leakage with Zero Delay Penalty  . . . . 9:1--9:??
                   Yu-Ze Wu and   
               Mango C.-T. Chao   Scan-Cell Reordering for Minimizing
                                  Scan-Shift Power Based on Nonspecified
                                  Test Cubes . . . . . . . . . . . . . . . 10:1--10:??
               Montek Singh and   
               Steven M. Nowick   ACM Journal on Emerging Technologies in
                                  Computing Systems  . . . . . . . . . . . 11:1--11:??

ACM Transactions on Design Automation of Electronic Systems
Volume 16, Number 2, March, 2011

                 Massoud Pedram   Call for papers: Verification issue and
                                  challenges with multicore systems  . . . 12:1--12:??
            Anna Bernasconi and   
              Valentina Ciriani   Dimension-reducible Boolean functions
                                  based on affine spaces . . . . . . . . . 13:1--13:??
                    Yi Wang and   
                    Hui Liu and   
                    Duo Liu and   
                 Zhiwei Qin and   
                  Zili Shao and   
                Edwin H.-M. Sha   Overhead-aware energy optimization for
                                  real-time streaming applications on
                                  multiprocessor System-on-Chip  . . . . . 14:1--14:??
                 Jason Cong and   
                  Wei Jiang and   
                    Bin Liu and   
                         Yi Zou   Automatic memory partitioning and
                                  scheduling for throughput and power
                                  optimization . . . . . . . . . . . . . . 15:1--15:??
                 Guihai Yan and   
                  Yinhe Han and   
                    Hui Liu and   
              Xiaoyao Liang and   
                     Xiaowei Li   MicroFix: Using timing interpolation and
                                  delay sensors for power reduction  . . . 16:1--16:??
             Irith Pomeranz and   
              Sudhakar M. Reddy   Reducing the switching activity of test
                                  sequences under transparent-scan . . . . 17:1--17:??
             Stephen Cauley and   
Venkataramanan Balakrishnan and   
              Y. Charlie Hu and   
                  Cheng-Kok Koh   A parallel branch-and-cut approach for
                                  detailed placement . . . . . . . . . . . 18:1--18:??
                Yih-Lang Li and   
              Yu-Ning Chang and   
                  Wen-Nai Cheng   A gridless routing system with
                                  nonslicing floorplanning-based crosstalk
                                  reduction on gridless track assignment   19:1--19:??
                     Yu Liu and   
                  Kaijie Wu and   
                   Ramesh Karri   Scan-based attacks on linear feedback
                                  shift register based stream ciphers  . . 20:1--20:??

ACM Transactions on Design Automation of Electronic Systems
Volume 16, Number 3, June, 2011

               Kurt Keutzer and   
                    Peng Li and   
                   Li Shang and   
                       Hai Zhou   A Special Section on Multicore Parallel
                                  CAD: Algorithm Design and Programming    21:1--21:??
              Adrian Ludwin and   
                    Vaughn Betz   Efficient and Deterministic Parallel
                                  Placement for FPGAs  . . . . . . . . . . 22:1--22:??
                 Yiding Han and   
        Koushik Chakraborty and   
            Sanghamitra Roy and   
          Vilasita Kuntamukkala   Design and Implementation of a
                                  Throughput-Optimized GPU Floorplanning
                                  Algorithm  . . . . . . . . . . . . . . . 23:1--23:??
                 Yifang Liu and   
                       Jiang Hu   GPU-Based Parallelization for Fast
                                  Circuit Optimization . . . . . . . . . . 24:1--24:??
               Chia-Jui Hsu and   
      José Luis Pino and   
        Shuvra S. Bhattacharyya   Multithreaded Simulation for Synchronous
                                  Dataflow Graphs  . . . . . . . . . . . . 25:1--25:??
              Xiongfei Liao and   
        Thambipillai Srikanthan   Accelerating UNISIM-Based Cycle-Level
                                  Microarchitectural Simulations on
                                  Multicore Platforms  . . . . . . . . . . 26:1--26:??
Antonio García-Dopico and   
       Antonio Pérez and   
  Santiago Rodríguez and   
María Isabel García   A New Algorithm for VHDL Parallel
                                  Simulation . . . . . . . . . . . . . . . 27:1--27:??
                 Zhiyu Zeng and   
                  Zhuo Feng and   
                    Peng Li and   
                    Vivek Sarin   Locality-Driven Parallel Static Analysis
                                  for Power Delivery Networks  . . . . . . 28:1--28:??
                  Yuhao Zhu and   
                    Bo Wang and   
                  Yangdong Deng   Massively Parallel Logic Simulation with
                                  GPUs . . . . . . . . . . . . . . . . . . 29:1--29:??
       Debapriya Chatterjee and   
              Andrew Deorio and   
               Valeria Bertacco   Gate-Level Simulation with GPU Computing 30:1--30:??
            Rajdeep Bondade and   
                   Dongsheng Ma   Hardware-Software Codesign of an
                                  Embedded Multiple-Supply Power
                                  Management Unit for Multicore SoCs Using
                                  an Adaptive Global/Local Power
                                  Allocation and Processing Scheme . . . . 31:1--31:??
                 Greg Stitt and   
                    Frank Vahid   Thread Warping: Dynamic and Transparent
                                  Synthesis of Thread Accelerators . . . . 32:1--32:??
                 Antara Ain and   
                 Debjit Pal and   
            Pallab Dasgupta and   
    Siddhartha Mukhopadhyay and   
       Rajdeep Mukhopadhyay and   
                     John Gough   Chassis: a Platform for Verifying PMU
                                  Integration Using Autogenerated
                                  Behavioral Models  . . . . . . . . . . . 33:1--33:??
                     Yue Yu and   
              Shangping Ren and   
               Xiaobo Sharon Hu   A Metric for Quantifying Similarity
                                  between Timing Constraint Sets in
                                  Real-Time Systems  . . . . . . . . . . . 34:1--34:??
              Fady Abouzeid and   
              Sylvain Clerc and   
              Fabian Firmin and   
              Marc Renaudin and   
                 Tiempo Sas and   
                  Gilles Sicard   40nm CMOS 0.35V-Optimized Standard Cell
                                  Libraries for Ultra-Low Power
                                  Applications . . . . . . . . . . . . . . 35:1--35:??

ACM Transactions on Design Automation of Electronic Systems
Volume 16, Number 4, October, 2011

                Meikang Qiu and   
                Edwin H.-M. Sha   2011 ACM TODAES best paper award . . . . 36:1--36:??
                      Alper Sen   Concurrency-oriented verification and
                                  coverage of system-level designs . . . . 37:1--37:??
           Laurent Fournier and   
                    Avi Ziv and   
            Ekaterina Kutsy and   
                 Ofer Strichman   A probabilistic analysis of coverage
                                  methods  . . . . . . . . . . . . . . . . 38:1--38:??
               Wei-Tsun Sun and   
                   Zoran Salcic   GALS-Designer: a design framework for
                                  GALS software systems  . . . . . . . . . 39:1--39:??
            Kartikey Mittal and   
                Arpit Joshi and   
                   Madhu Mutyam   Timing variation-aware scheduling and
                                  resource binding in high-level synthesis 40:1--40:??
              Xiaofang Wang and   
                   Pallav Gupta   Resource-constrained multiprocessor
                                  synthesis for floating-point
                                  applications on FPGAs  . . . . . . . . . 41:1--41:??
                Yongjoo Kim and   
                Jongeun Lee and   
         Aviral Shrivastava and   
                  Yunheung Paek   Memory access optimization in
                                  compilation for coarse-grained
                                  reconfigurable architectures . . . . . . 42:1--42:??
              Karel Bruneel and   
                Wim Heirman and   
                Dirk Stroobandt   Dynamic data folding with
                                  parameterizable FPGA configurations  . . 43:1--43:??
                   Wei Dong and   
                        Peng Li   Parallel circuit simulation with
                                  adaptively controlled projective
                                  integration  . . . . . . . . . . . . . . 44:1--44:??
       Juan Antonio Maestro and   
            Pedro Reviriego and   
             Sanghyeon Baeg and   
                 Shijie Wen and   
                   Richard Wong   Mitigating the effects of large multiple
                                  cell upsets (MCUs) in memories . . . . . 45:1--45:??
           Michael B. Healy and   
             Fayez Mohamood and   
          Hsien-Hsin S. Lee and   
                   Sung Kyu Lim   Integrated microarchitectural
                                  floorplanning and run-time controller
                                  for inductive noise mitigation . . . . . 46:1--46:??
                    Jin-Tai Yan   IO connection assignment and RDL routing
                                  for flip-chip designs  . . . . . . . . . 47:1--47:??
               Tak-Yung Kim and   
                    Taewhan Kim   Clock Tree synthesis for TSV-based $3$D
                                  IC designs . . . . . . . . . . . . . . . 48:1--48:??
                Jianchao Lu and   
                   Baris Taskin   Clock buffer polarity assignment with
                                  skew tuning  . . . . . . . . . . . . . . 49:1--49:??
                Shaoxi Wang and   
               Xinzhang Jia and   
              Arthur B. Yeh and   
                   Lihong Zhang   Analog layout retargeting using
                                  geometric programming  . . . . . . . . . 50:1--50:??
              Filipa Duarte and   
                Jos Hulzink and   
                   Jun Zhou and   
                 Jan Stuijt and   
                Jos Huisken and   
                Harmke De Groot   A 36$ \mu $W heartbeat-detection
                                  processor for a wireless sensor node . . 51:1--51:??


ACM Transactions on Design Automation of Electronic Systems
Volume 17, Number 1, January, 2012

              Freek Verbeek and   
                Julien Schmaltz   Easy Formal Specification and Validation
                                  of Unbounded Networks-on-Chips
                                  Architectures  . . . . . . . . . . . . . 1:1--1:??
       Muhammad Adeel Pasha and   
             Steven Derrien and   
               Olivier Sentieys   System-Level Synthesis for Wireless
                                  Sensor Node Controllers: a Complete
                                  Design Flow  . . . . . . . . . . . . . . 2:1--2:??
               Levent Aksoy and   
              Eduardo Costa and   
               Paulo Flores and   
                  Jose Monteiro   Optimization Algorithms for the
                                  Multiplierless Realization of Linear
                                  Transforms . . . . . . . . . . . . . . . 3:1--3:??
          Mario K. Y. Leung and   
            Eric K. I. Chio and   
         Evangeline F. Y. Young   Postplacement Voltage Island Generation  4:1--4:??
                   Hai Wang and   
          Sheldon X.-D. Tan and   
                     Ryan Rakib   Compact Modeling of Interconnect
                                  Circuits over Wide Frequency Band by
                                  Adaptive Complex-Valued Sampling Method  5:1--5:??
               Jing-Wei Lin and   
                Tsung-Yi Ho and   
              Iris Hui-Ru Jiang   Reliability-Driven Power/Ground Routing
                                  for Analog ICs . . . . . . . . . . . . . 6:1--6:??
      Charalambos Ioannides and   
                Kerstin I. Eder   Coverage-Directed Test Generation
                                  Automated by Machine Learning --- a
                                  Review . . . . . . . . . . . . . . . . . 7:1--7:??
              Zhaoliang Pan and   
               Melvin A. Breuer   Error Rate Estimation for Defective
                                  Circuits via Ones Counting . . . . . . . 8:1--8:??
              Huan-Kai Peng and   
           Hsuan-Ming Huang and   
                Yu-Hsin Kuo and   
              Charles H.-P. Wen   Statistical Soft Error Rate (SSER)
                                  Analysis for Scaled CMOS Designs . . . . 9:1--9:??
                  Fang Gong and   
                 Xuexin Liu and   
                     Hao Yu and   
          Sheldon X. D. Tan and   
                 Junyan Ren and   
                         Lei He   A Fast Non-Monte-Carlo Yield Analysis
                                  and Optimization by Stochastic
                                  Orthogonal Polynomials . . . . . . . . . 10:1--10:??

ACM Transactions on Design Automation of Electronic Systems
Volume 17, Number 2, April, 2012

               Meng-Huan Wu and   
             Peng-Chih Wang and   
              Cheng-Yang Fu and   
                  Ren-Song Tsay   An Extended SystemC Framework for
                                  Efficient HW/SW Co-Simulation  . . . . . 11:1--11:??
             Pingqiang Zhou and   
              Ping-Hung Yuh and   
           Sachin S. Sapatnekar   Optimized $3$D Network-on-Chip Design
                                  Using Simulated Allocation . . . . . . . 12:1--12:??
                Guangyu Sun and   
              Huazhong Yang and   
                       Yuan Xie   Performance/Thermal-Aware Design of
                                  $3$D-Stacked L2 Caches for CMPs  . . . . 13:1--13:??
              Chin-Hsien Wu and   
                  Hsin-Hung Lin   Timing Analysis of System Initialization
                                  and Crash Recovery for a Segment-Based
                                  Flash Translation Layer  . . . . . . . . 14:1--14:??
               Peter Milder and   
           Franz Franchetti and   
               James C. Hoe and   
            Markus Püschel   Computer Generation of Hardware for
                                  Linear Digital Signal Processing
                                  Transforms . . . . . . . . . . . . . . . 15:1--15:??
             Shih-Hung Weng and   
                 Yu-Min Kuo and   
               Shih-Chieh Chang   Timing Optimization in Sequential
                                  Circuit by Exploiting Clock-Gating Logic 16:1--16:??
          Masanori Kurimoto and   
             Jun Matsushima and   
          Shigeki Ohbayashi and   
             Yoshiaki Fukui and   
              Michio Komoda and   
                 Nobuhiro Tsuda   A Yield and Reliability Improvement
                                  Methodology Based on Logic Redundant
                                  Repair with a Repairable Scan Flip-Flop
                                  Designed by Push Rule  . . . . . . . . . 17:1--17:??
                 Dong Xiang and   
                  Zhen Chen and   
               Laung-Terng Wang   Scan Flip-Flop Grouping to Compress Test
                                  Data and Compact Test Responses for
                                  Launch-on-Capture Delay Testing  . . . . 18:1--18:??

ACM Transactions on Design Automation of Electronic Systems
Volume 17, Number 3, June, 2012

                 Sandip Ray and   
             Jayanta Bhadra and   
            Magdy S. Abadir and   
                 Li-C. Wang and   
                    Aarti Gupta   Introduction to special section on
                                  verification challenges in the
                                  concurrent world . . . . . . . . . . . . 19:1--19:??
              Freek Verbeek and   
                Julien Schmaltz   Towards the formal verification of cache
                                  coherency at the architectural level . . 20:1--20:??
                   Jim Holt and   
           Jaideep Dastidar and   
             David Lindberg and   
                  John Pape and   
                      Peng Yang   A full lifecycle performance
                                  verification methodology for multicore
                                  systems-on-chip  . . . . . . . . . . . . 21:1--21:??
            Mohamed Elwakil and   
                   Zijiang Yang   Deterministic replay for
                                  message-passing-based concurrent
                                  programs . . . . . . . . . . . . . . . . 22:1--22:??
                 Etem Deniz and   
                  Alper Sen and   
                       Jim Holt   Verification and coverage of message
                                  passing multicore applications . . . . . 23:1--23:??
                 Xiaoke Qin and   
                 Prabhat Mishra   Directed test generation for validation
                                  of multicore architectures . . . . . . . 24:1--24:??
             Padmaraj Singh and   
    Vijaykrishnan Narayanan and   
                David L. Landis   Targeted random test generation for
                                  power-aware multicore designs  . . . . . 25:1--25:??
              Wooyoung Jang and   
                   David Z. Pan   A3MAP: Architecture-aware analytic
                                  mapping for networks-on-chip . . . . . . 26:1--26:??
  Mohammad H. Foroozannejad and   
              Trevor Hodges and   
              Matin Hashemi and   
                  Soheil Ghiasi   Postscheduling buffer management
                                  trade-offs in streaming software
                                  synthesis  . . . . . . . . . . . . . . . 27:1--27:??
              Hassan Salamy and   
                   J. Ramanujam   An ILP solution to address code
                                  generation for embedded applications on
                                  digital signal processors  . . . . . . . 28:1--28:??
   Benjamin Carrion Schafer and   
          Kazutoshi Wakabayashi   Divide and conquer high-level synthesis
                                  design space exploration . . . . . . . . 29:1--29:??
              Chandan Karfa and   
        Chittaranjan Mandal and   
                Dipankar Sarkar   Formal verification of code motion
                                  techniques using data-flow-driven
                                  equivalence checking . . . . . . . . . . 30:1--30:??
      Éamonn Linehan and   
             Eamonn O'Toole and   
          Siobhán Clarke   Model-driven automation for
                                  simulation-based functional verification 31:1--31:??
               Haifeng Qian and   
       Sachin S. Sapatnekar and   
                    Eren Kursun   Fast Poisson Solvers for thermal
                                  analysis . . . . . . . . . . . . . . . . 32:1--32:??
         Matthew R. Guthaus and   
                   Xuchu Hu and   
              Gustavo Wilke and   
            Guilherme Flach and   
                   Ricardo Reis   High-performance clock mesh optimization 33:1--33:??
                Kuan-Yu Lin and   
              Hong-Ting Lin and   
                Tsung-Yi Ho and   
                 Chia-Chun Tsai   Load-balanced clock tree synthesis with
                                  adjustable delay buffer insertion for
                                  clock skew reduction in multiple dynamic
                                  supply voltage designs . . . . . . . . . 34:1--34:??
        Chien-Nan Jimmy Liu and   
              Yen-Lung Chen and   
             Chin-Cheng Kuo and   
                   I-Ching Tsai   A fast heuristic approach for parametric
                                  yield enhancement of analog designs  . . 35:1--35:??

ACM Transactions on Design Automation of Electronic Systems
Volume 17, Number 4, October, 2012

               Chia-Heng Tu and   
              Shih-Hao Hung and   
                Tung-Chieh Tsai   MCEmu: a Framework for Software
                                  Development and Performance Analysis of
                                  Multicore Systems  . . . . . . . . . . . 36:1--36:??
                 Bijan Alizadeh   Formal Verification and Debugging of
                                  Precise Interrupts on High Performance
                                  Microprocessors  . . . . . . . . . . . . 37:1--37:??
        Subhankar Mukherjee and   
            Pallab Dasgupta and   
    Siddhartha Mukhopadhyay and   
               Scott Little and   
              John Havlicek and   
        Srikanth Chandrasekaran   Synchronizing AMS Assertions with AMS
                                  Simulation: From Theory to Practice  . . 38:1--38:??
                    Hai Lin and   
                      Yunsi Fei   Resource Sharing of Pipelined Custom
                                  Hardware Extension for Energy-Efficient
                                  Application-Specific Instruction Set
                                  Processor Design . . . . . . . . . . . . 39:1--39:??
                    Hai Lin and   
                  Tiansi Hu and   
                      Yunsi Fei   A Hardware/Software Cooperative Custom
                                  Register Binding Approach for Register
                                  Spill Elimination in
                                  Application-Specific Instruction Set
                                  Processors . . . . . . . . . . . . . . . 40:1--40:??
               An-Ping Wang and   
                 Jiwon Hahn and   
              Mahshid Roumi and   
                    Pai H. Chou   Buffer Optimization and Dispatching
                                  Scheme for Embedded Systems with
                                  Behavioral Transparency  . . . . . . . . 41:1--41:??
          Matthew B. Gately and   
              Mark B. Yeary and   
                 Choon Yik Tang   An Algorithm for Jointly Optimizing
                                  Quantization and Multiple Constant
                                  Multiplication . . . . . . . . . . . . . 42:1--42:??
               Yonghwan Kim and   
              Sanghoon Kwak and   
                    Taewhan Kim   Synthesis of Adaptable Hybrid Adders for
                                  Area Optimization under Timing
                                  Constraint . . . . . . . . . . . . . . . 43:1--43:??
             John D. Backes and   
                 Marc D. Riedel   The Synthesis of Cyclic Dependencies
                                  with Boolean Satisfiability  . . . . . . 44:1--44:??
              David R. Bild and   
             Robert P. Dick and   
                 Gregory E. Bok   Static NBTI Reduction Using Internal
                                  Node Control . . . . . . . . . . . . . . 45:1--45:??
              Nai-Wen Chang and   
                Tzu-Yin Lin and   
                 Sun-Yuan Hsieh   Conditional Diagnosability of $k$-Ary
                                  $n$-Cubes under the PMC Model  . . . . . 46:1--46:??
              Arijit Mondal and   
          P. P. Chakrabarti and   
                Pallab Dasgupta   Symbolic-Event-Propagation-Based Minimal
                                  Test Set Generation for Robust Path
                                  Delay Faults . . . . . . . . . . . . . . 47:1--47:??
               Shianling Wu and   
           Laung-Terng Wang and   
               Xiaoqing Wen and   
               Wen-Ben Jone and   
           Michael S. Hsiao and   
                Fangfang Li and   
          James Chien-Mo Li and   
                Jiun-Lang Huang   Launch-on-Shift Test Generation for
                                  Testing Scan Designs Containing
                                  Synchronous and Asynchronous Clock
                                  Domains  . . . . . . . . . . . . . . . . 48:1--48:??
             Mohammed G. Khatib   Migration-Resistant Policies for
                                  Probe-Wear Leveling in MEMS Storage
                                  Devices  . . . . . . . . . . . . . . . . 49:1--49:??
                Tak-Kei Lam and   
             Wai-Chung Tang and   
              Xiaoqing Yang and   
                    Yu-Liang Wu   ECR: a Powerful and Low-Complexity Error
                                  Cancellation Rewiring Scheme . . . . . . 50:1--50:??
               Ruijing Shen and   
          Sheldon X.-D. Tan and   
                   Hai Wang and   
                   Jinjun Xiong   Fast Statistical Full-Chip Leakage
                                  Analysis for Nanometer VLSI Systems  . . 51:1--51:??


ACM Transactions on Design Automation of Electronic Systems
Volume 18, Number 1, December, 2012

       Ayse Kivilcim Coskun and   
             Yung-Hsiang Lu and   
                      Qinru Qiu   Introduction to the special section on
                                  adaptive power management for energy and
                                  temperature-aware computing systems  . . 1:1--1:??
                 Vahid Lari and   
          Shravan Muddasani and   
             Srinivas Boppu and   
               Frank Hannig and   
              Moritz Schmid and   
              Jürgen Teich   Hierarchical power management for
                                  adaptive tightly-coupled processor
                                  arrays . . . . . . . . . . . . . . . . . 2:1--2:??
            Meeta Srivastav and   
                M. B. Henry and   
               Leyla Nazhandali   Design of energy-efficient, adaptable
                                  throughput systems at near/sub-threshold
                                  voltage  . . . . . . . . . . . . . . . . 3:1--3:??
                    Jin Sun and   
                  Rui Zheng and   
            Jyothi Velamala and   
                     Yu Cao and   
              Roman Lysecky and   
            Karthik Shankar and   
                   Janet Roveda   A self-tuning design methodology for
                                  power-efficient multi-core systems . . . 4:1--4:??
            Rance Rodrigues and   
      Arunachalam Annamalai and   
               Israel Koren and   
                   Sandip Kundu   Improving performance per watt of
                                  asymmetric multi-core processors via
                                  online program phase classification and
                                  adaptive core morphing . . . . . . . . . 5:1--5:??
           Francesco Zanini and   
              David Atienza and   
             Colin N. Jones and   
                Luca Benini and   
            Giovanni De Micheli   Online thermal control methods for
                                  multiprocessor systems . . . . . . . . . 6:1--6:??
               Ryan Cochran and   
                   Sherief Reda   Thermal prediction and adaptive control
                                  through workload phase detection . . . . 7:1--7:??
                  Liang Shi and   
                 Jianhua Li and   
             Chun Jason Xue and   
                    Xuehai Zhou   Hybrid nonvolatile disk cache for
                                  energy-efficient and high-performance
                                  systems  . . . . . . . . . . . . . . . . 8:1--8:??
           Amit Kumar Singh and   
                Akash Kumar and   
        Thambipillai Srikanthan   Accelerating throughput-aware runtime
                                  mapping for heterogeneous MPSoCs . . . . 9:1--9:??
              Kalyan Saladi and   
        Harikumar Somakumar and   
            Mahadevan Ganapathi   Concurrency-aware compiler optimizations
                                  for hardware description languages . . . 10:1--10:??
             Sotirios Xydis and   
           Kiamal Pekmestzi and   
          Dimitrios Soudris and   
              George Economakos   Compiler-in-the-loop exploration during
                                  datapath synthesis for higher quality
                                  delay-area trade-offs  . . . . . . . . . 11:1--11:??
          Masanori Kurimoto and   
           Takeshi Yamamoto and   
             Satoshi Nakano and   
              Atsuto Hanami and   
                 Hiroyuki Kondo   Verification work reduction methodology
                                  in low-power chip implementation . . . . 12:1--12:??
               Naifeng Jing and   
                Ju-Yueh Lee and   
                   Zhe Feng and   
                 Weifeng He and   
                Zhigang Mao and   
                         Lei He   SEU fault evaluation and characteristics
                                  for SRAM-based FPGA architectures and
                                  synthesis algorithms . . . . . . . . . . 13:1--13:??
            Jennifer Dworak and   
               Kundan Nepal and   
                 Nuno Alves and   
                  Yiwen Shi and   
         Nicholas Imbriglia and   
                  R. Iris Bahar   Using implications to choose tests
                                  through suspect fault identification . . 14:1--14:??
               Santiago Mok and   
                   John Lee and   
                   Puneet Gupta   Discrete sizing for leakage power
                                  optimization in physical design: a
                                  comparative study  . . . . . . . . . . . 15:1--15:??
                   John Lee and   
                   Puneet Gupta   ECO cost measurement and incremental
                                  gate sizing for late process changes . . 16:1--16:??

ACM Transactions on Design Automation of Electronic Systems
Volume 18, Number 2, March, 2013

          Georgios Kornaros and   
        Dionisios Pnevmatikatos   A survey and taxonomy of on-chip
                                  monitoring of multicore systems-on-chip  17:1--17:??
              Rico Backasch and   
       Christian Hochberger and   
            Alexander Weiss and   
             Martin Leucker and   
                Richard Lasslop   Runtime verification for multicore SoC
                                  with high-quality trace data . . . . . . 18:1--18:??
       José C. Costa and   
        José C. Monteiro   Coverage-directed observability-based
                                  validation for embedded software . . . . 19:1--19:??
               Chun-An Chen and   
                 Sun-Yuan Hsieh   $ t / t $-Diagnosability of regular
                                  graphs under the PMC model . . . . . . . 20:1--20:??
                 Chen Huang and   
              Bailey Miller and   
                Frank Vahid and   
                  Tony Givargis   Synthesis of networks of custom
                                  processing elements for real-time
                                  physical system emulation  . . . . . . . 21:1--21:??
              Domenic Forte and   
               Ankur Srivastava   Resource-aware architectures for
                                  adaptive particle filter based visual
                                  target tracking  . . . . . . . . . . . . 22:1--22:??
               Baoxian Zhao and   
                Hakan Aydin and   
                      Dakai Zhu   Shared recovery for energy efficiency
                                  and reliability enhancements in
                                  real-time applications with precedence
                                  constraints  . . . . . . . . . . . . . . 23:1--23:??
                   Hao Shen and   
                   Ying Tan and   
                     Jun Lu and   
                    Qing Wu and   
                      Qinru Qiu   Achieving autonomous power management
                                  using reinforcement learning . . . . . . 24:1--24:??
                Jongwon Lee and   
            Jonghee M. Youn and   
                 Doosan Cho and   
                  Yunheung Paek   Reducing instruction bit-width for
                                  low-power VLIW architectures . . . . . . 25:1--25:??
           Mehrdad Majzoobi and   
                Joonho Kong and   
             Farinaz Koushanfar   Low-power resource binding by
                                  postsilicon customization  . . . . . . . 26:1--26:??
             Shih-Hsu Huang and   
                 Wen-Pin Tu and   
            Chia-Ming Chang and   
                   Song-Bin Pan   Low-power anti-aging zero skew clock
                                  gating . . . . . . . . . . . . . . . . . 27:1--27:??
                   Hai Wang and   
          Sheldon X.-D. Tan and   
                     Duo Li and   
               Ashish Gupta and   
                      Yuan Yuan   Composable thermal modeling and
                                  simulation for architecture-level
                                  thermal designs of multicore
                                  microprocessors  . . . . . . . . . . . . 28:1--28:??
                 Zhiyu Zeng and   
                 Suming Lai and   
                        Peng Li   IC power delivery: Voltage regulation
                                  and conversion, system-level
                                  cooptimization and technology
                                  implications . . . . . . . . . . . . . . 29:1--29:??
                Ren-Jie Lee and   
                 Hung-Ming Chen   A study of row-based area-array I/O
                                  design planning in concurrent
                                  chip-package design flow . . . . . . . . 30:1--30:??
         Matthew R. Guthaus and   
              Gustavo Wilke and   
                   Ricardo Reis   Revisiting automated physical synthesis
                                  of high-performance clock networks . . . 31:1--31:??
             Michael Gester and   
           Dirk Müller and   
                Tim Nieberg and   
           Christian Panten and   
          Christian Schulte and   
                     Jens Vygen   BonnRoute: Algorithms and data
                                  structures for fast and good VLSI
                                  routing  . . . . . . . . . . . . . . . . 32:1--32:??
               Amit Agarwal and   
                 Jason Cong and   
                   Brian Tagiku   The survivability of design-specific
                                  spare placement in FPGA architectures
                                  with high defect rates . . . . . . . . . 33:1--33:??

ACM Transactions on Design Automation of Electronic Systems
Volume 18, Number 3, July, 2013

         Raj Rao Nadakuditi and   
                 Igor L. Markov   On bottleneck analysis in stochastic
                                  stream processing  . . . . . . . . . . . 34:1--34:??
           Fatma Abouelella and   
               Tom Davidson and   
                  Wim Meeus and   
              Karel Bruneel and   
                Dirk Stroobandt   How to efficiently implement dynamic
                                  circuit specialization systems . . . . . 35:1--35:??
           Gianpiero Cabodi and   
               Sergio Nocco and   
                   Stefano Quer   Thread-based multi-engine model checking
                                  for multicore platforms  . . . . . . . . 36:1--36:??
                 Sehwan Kim and   
                    Pai H. Chou   Analysis and minimization of
                                  power-transmission loss in locally
                                  daisy-chained systems by local energy
                                  buffering  . . . . . . . . . . . . . . . 37:1--37:??
                Saket Gupta and   
           Sachin S. Sapatnekar   Employing circadian rhythms to enhance
                                  power and reliability  . . . . . . . . . 38:1--38:??
            Mei-Hsiang Tsai and   
                Po-Yang Hsu and   
                 Hung-Yi Li and   
              Yi-Huang Hung and   
                      Yi-Yu Liu   Routability optimization for
                                  crossbar-switch structured ASIC design   39:1--39:??
         Sean Shih-Ying Liu and   
                Wan-Ting Lo and   
              Chieh-Jui Lee and   
                 Hung-Ming Chen   Agglomerative-based flip-flop merging
                                  and relocation for signal wirelength and
                                  clock tree optimization  . . . . . . . . 40:1--40:??
                 Yu-Min Lee and   
                   Pei-Yu Huang   An efficient method for analyzing
                                  on-chip thermal reliability considering
                                  process variations . . . . . . . . . . . 41:1--41:??
                   Yiyu Shi and   
               Jinjun Xiong and   
           Vladimir Zolotov and   
            Chandu Visweswariah   Order statistics for correlated random
                                  variables and its application to
                                  at-speed testing . . . . . . . . . . . . 42:1--42:??
                   Wei Zhao and   
                  Junxia Ma and   
       Mohammad Tehranipoor and   
            Sreejit Chakravarty   Power-safe application of tdf patterns
                                  to flip-chip designs during wafer test   43:1--43:??
                 Dong Xiang and   
                  Jianbo Li and   
     Krishnendu Chakrabarty and   
                    Xijiang Lin   Test compaction for small-delay defects
                                  using an effective path selection scheme 44:1--44:??

ACM Transactions on Design Automation of Electronic Systems
Volume 18, Number 4, October, 2013

                      Anonymous   Call for nominations for editor-in-chief 44:1--44:??
           Diana Marculescu and   
                      Chita Das   Editorial to special section on networks
                                  on chip: Architecture, tools, and
                                  methodologies  . . . . . . . . . . . . . 45:1--45:??
                Paul Bogdan and   
            Radu Marculescu and   
                 Siddharth Jain   Dynamic power management for multidomain
                                  system-on-chip platforms: an optimal
                                  control approach . . . . . . . . . . . . 46:1--46:??
                    Xi Chen and   
                   Zheng Xu and   
               Hyungjun Kim and   
                 Paul Gratz and   
                   Jiang Hu and   
        Michael Kishinevsky and   
                     Umit Ogras   In-network monitoring and control policy
                                  for DVFS of CMP networks-on-chip and
                                  last level caches  . . . . . . . . . . . 47:1--47:??
                 Jaekyu Lee and   
                      Si Li and   
                Hyesoon Kim and   
          Sudhakar Yalamanchili   Adaptive virtual channel partitioning
                                  for network-on-chip in heterogeneous
                                  architectures  . . . . . . . . . . . . . 48:1--48:??
            Ahmed Abousamra and   
              Alex K. Jones and   
                    Rami Melhem   Ordering circuit establishment in
                                  multiplane NoCs  . . . . . . . . . . . . 49:1--49:??
                  Jinho Lee and   
                Dongwoo Lee and   
                Sunwook Kim and   
                   Kiyoung Choi   Deflection routing in $3$D
                                  network-on-chip with limited vertical
                                  bandwidth  . . . . . . . . . . . . . . . 50:1--50:??
              Hamid Shojaei and   
                Twan Basten and   
                Marc Geilen and   
                 Azadeh Davoodi   A fast and scalable multidimensional
                                  multiple-choice knapsack heuristic . . . 51:1--51:??
            Jonghee W. Yoon and   
                Jongeun Lee and   
              Sanghyun Park and   
                Yongjoo Kim and   
                Jinyong Lee and   
              Yunheung Paek and   
                     Doosan Cho   Architecture customization of on-chip
                                  reconfigurable accelerators  . . . . . . 52:1--52:??
            Reiley Jeyapaul and   
             Aviral Shrivastava   Enabling energy efficient reliability in
                                  embedded systems through smart cache
                                  cleaning . . . . . . . . . . . . . . . . 53:1--53:??
             Ismail Kadayif and   
              Mahir Turkcan and   
            Seher Kiziltepe and   
                   Ozcan Ozturk   Hardware/software approaches for
                                  reducing the process variation impact on
                                  instruction fetches  . . . . . . . . . . 54:1--54:??
                Guanying Wu and   
                   Xubin He and   
                 Ningde Xie and   
                     Tong Zhang   Exploiting workload dynamics to improve
                                  SSD read latency via differentiated
                                  error correction codes . . . . . . . . . 55:1--55:??
              Po-Chun Huang and   
             Yuan-Hao Chang and   
                    Tei-Wei Kuo   An index-based management scheme with
                                  adaptive caching for huge-scale low-cost
                                  embedded flash storages  . . . . . . . . 56:1--56:??
                    Bo Zhao and   
                   Jun Yang and   
               Youtao Zhang and   
                 Yiran Chen and   
                         Hai Li   Common-source-line array: an area
                                  efficient memory architecture for
                                  bipolar nonvolatile devices  . . . . . . 57:1--57:??
               Jean Da Rolt and   
          Giorgio Di Natale and   
         Marie-Lise Flottes and   
                 Bruno Rouzeyre   A novel differential scan attack on
                                  advanced DFT structures  . . . . . . . . 58:1--58:??
              Yao-Lin Chang and   
                    I-Lun Tseng   A parallel dual-scanline algorithm for
                                  partitioning parameterized 45-degree
                                  polygons . . . . . . . . . . . . . . . . 59:1--59:??
     Rohit Sunkam Ramanujam and   
                       Bill Lin   Destination-based congestion awareness
                                  for adaptive routing in $2$D mesh
                                  networks . . . . . . . . . . . . . . . . 60:1--60:??
                    Tan Yan and   
                   Qiang Ma and   
            Scott Chilstedt and   
          Martin D. F. Wong and   
                    Deming Chen   A routing algorithm for graphene
                                  nanoribbon circuit . . . . . . . . . . . 61:1--61:??


ACM Transactions on Design Automation of Electronic Systems
Volume 19, Number 1, December, 2013

                 Raid Ayoub and   
                 Rajib Nath and   
          Tajana Simunic Rosing   CoMETC: Coordinated management of
                                  energy/thermal/cooling in servers  . . . 1:1--1:??
           Ra'ed Al-Dujaily and   
                Nizar Dahir and   
               Terrence Mak and   
                    Fei Xia and   
                  Alex Yakovlev   Dynamic programming-based runtime
                                  thermal management (DPRTM): an online
                                  thermal control strategy for $3$D-NoC
                                  systems  . . . . . . . . . . . . . . . . 2:1--2:??
              Yen-Jen Chang and   
                   Hsiang-Yu Lu   Improving the performance of port range
                                  check for network packet filtering . . . 3:1--3:??
        Angeliki Kritikakou and   
           Francky Catthoor and   
        Vasilios Kelefouras and   
                  Costas Goutis   Near-optimal and scalable intrasignal
                                  in-place optimization for
                                  non-overlapping and irregular access
                                  schemes  . . . . . . . . . . . . . . . . 4:1--4:??
                 Jianhua Li and   
                  Liang Shi and   
                  Qingan Li and   
             Chun Jason Xue and   
                 Yiran Chen and   
                 Yinlong Xu and   
                       Wei Wang   Low-energy volatile STT--RAM cache
                                  design using cache-coherence-enabled
                                  adaptive refresh . . . . . . . . . . . . 5:1--5:??
                Xue-Xin Liu and   
          Sheldon X.-D. Tan and   
Adolfo Adair Palma-Rodriguez and   
      Esteban Tlelo-Cuautle and   
                    Guoyong Shi   Performance bound analysis of analog
                                  circuits in frequency- and time-domain
                                  considering process variations . . . . . 6:1--6:??
           Chien-Chih Huang and   
              Chin-Long Wey and   
                 Jwu-E Chen and   
                    Pei-Wen Luo   Optimal common-centroid-based unit
                                  capacitor placements for yield
                                  enhancement of switched-capacitor
                                  circuits . . . . . . . . . . . . . . . . 7:1--7:??
                 Irith Pomeranz   Built-in generation of multicycle
                                  functional broadside tests with
                                  observation points . . . . . . . . . . . 8:1--8:??
              Jason G. Tong and   
          Marc Boulé and   
                   Zeljko Zilic   Test compaction techniques for
                                  assertion-based test generation  . . . . 9:1--9:??

ACM Transactions on Design Automation of Electronic Systems
Volume 19, Number 2, March, 2014

               Chia-Heng Tu and   
               Hui-Hsin Hsu and   
               Jen-Hao Chen and   
              Chun-Han Chen and   
                  Shih-Hao Hung   Performance and power profiling for
                                  emulated Android systems . . . . . . . . 10:1--10:??
           Kunal Ganeshpure and   
                   Sandip Kundu   Performance-driven dynamic thermal
                                  management of MPSoC based on task
                                  rescheduling . . . . . . . . . . . . . . 11:1--11:??
             Brett H. Meyer and   
            Adam S. Hartman and   
               Donald E. Thomas   Cost-effective lifetime and yield
                                  optimization for NoC-based MPSoCs  . . . 12:1--12:??
                Jongeun Lee and   
              Seongseok Seo and   
             Jongkyung Paek and   
                   Kiyoung Choi   Configurable range memory for effective
                                  data reuse on programmable accelerators  13:1--13:??
                 Eddie Hung and   
            Steven J. E. Wilton   Accelerating FPGA debug: Increasing
                                  visibility using a runtime
                                  reconfigurable observation and
                                  triggering network . . . . . . . . . . . 14:1--14:??
            Jacopo Panerati and   
              Giovanni Beltrame   A comparative evaluation of
                                  multi-objective exploration algorithms
                                  for high-level design  . . . . . . . . . 15:1--15:??
               Seokhyun Lee and   
                   Kiyoung Choi   Critical-path-aware high-level synthesis
                                  with distributed controller for fast
                                  timing closure . . . . . . . . . . . . . 16:1--16:??
               Yaoguang Wei and   
                  Cliff Sze and   
      Natarajan Viswanathan and   
                    Zhuo Li and   
          Charles J. Alpert and   
              Lakshmi Reddy and   
            Andrew D. Huber and   
          Gustavo E. Tellez and   
             Douglas Keller and   
           Sachin S. Sapatnekar   Techniques for scalable and effective
                                  routability evaluation . . . . . . . . . 17:1--17:??
                 Irith Pomeranz   Low-power skewed-load tests based on
                                  functional broadside tests . . . . . . . 18:1--18:??
                 Irith Pomeranz   Design-for-testability for multi-cycle
                                  broadside tests by holding of state
                                  variables  . . . . . . . . . . . . . . . 19:1--19:??
              Sounil Biswas and   
               Hongfei Wang and   
          R. D. (Shawn) Blanton   Reducing test cost of integrated,
                                  heterogeneous systems using pass-fail
                                  test data analysis . . . . . . . . . . . 20:1--20:??
               Da-Wei Chang and   
             Hsin-Hung Chen and   
              Dau-Jieu Yang and   
                Hsung-Pin Chang   BLAS: Block-level adaptive striping for
                                  solid-state drives . . . . . . . . . . . 21:1--21:??

ACM Transactions on Design Automation of Electronic Systems
Volume 19, Number 3, June, 2014

       Luis Angel D. Bathen and   
                  Nikil D. Dutt   SPMCloud: Towards the Single-Chip
                                  Embedded ScratchPad Memory-Based Storage
                                  Cloud  . . . . . . . . . . . . . . . . . 22:1--22:??
             Rafael Rosales and   
              Michael Glass and   
          Jürgen Teich and   
                    Bo Wang and   
                    Yang Xu and   
               Ralph Hasholzner   MAESTRO --- Holistic Actor-Oriented
                                  Modeling of Nonfunctional Properties and
                                  Firmware Behavior for MPSoCs . . . . . . 23:1--23:??
                 Libo Huang and   
               Zhiying Wang and   
                  Nong Xiao and   
               Yongwen Wang and   
                      Qiang Dou   Integrated Coherence Prediction: Towards
                                  Efficient Cache Coherence on NoC-Based
                                  Multicore Architectures  . . . . . . . . 24:1--24:??
              Po-Chun Huang and   
             Yuan-Hao Chang and   
                Kam-Yiu Lam and   
              Jian-Tao Wang and   
               Chien-Chin Huang   Garbage Collection for Multiversion
                                  Index in Flash-Based Embedded Databases  25:1--25:??
                  Jieun Lim and   
  Nagesh B. Lakshminarayana and   
                Hyesoon Kim and   
               William Song and   
      Sudhakar Yalamanchili and   
                   Wonyong Sung   Power Modeling for GPU Architectures
                                  Using McPAT  . . . . . . . . . . . . . . 26:1--26:??
               Chia-Wei Lee and   
                 Sun-Yuan Hsieh   Diagnosability of Component-Composition
                                  Graphs in the MM* Model  . . . . . . . . 27:1--27:??
                Dominik Erb and   
          Michael A. Kochte and   
             Matthias Sauer and   
         Stefan Hillebrecht and   
            Tobias Schubert and   
    Hans-Joachim Wunderlich and   
                   Bernd Becker   Exact Logic and Fault Simulation in
                                  Presence of Unknowns . . . . . . . . . . 28:1--28:??
              Jackey Z. Yan and   
      Natarajan Viswanathan and   
                      Chris Chu   An Effective Floorplan-Guided Placement
                                  Algorithm for Large-Scale Mixed-Size
                                  Designs  . . . . . . . . . . . . . . . . 29:1--29:??
               Minseok Kang and   
                    Taewhan Kim   Integrated Resource Allocation and
                                  Binding in Clock Mesh Synthesis  . . . . 30:1--30:??
           Baktash Boghrati and   
           Sachin S. Sapatnekar   Incremental Analysis of Power Grids
                                  Using Backward Random Walks  . . . . . . 31:1--31:??

ACM Transactions on Design Automation of Electronic Systems
Volume 19, Number 4, August, 2014

         Reinhard Schneider and   
                Dip Goswami and   
       Samarjit Chakraborty and   
            Unmesh Bordoloi and   
                 Petru Eles and   
                      Zebo Peng   Quantifying Notions of Extensibility in
                                  FlexRay Schedule Synthesis . . . . . . . 32:1--32:??
                Gung-Yu Pan and   
              Jing-Yang Jou and   
                   Bo-Cheng Lai   Scalable Power Management Using
                                  Multilevel Reinforcement Learning for
                                  Multiprocessors  . . . . . . . . . . . . 33:1--33:??
             Yoon Seok Yang and   
              Reeshav Kumar and   
                  Gwan Choi and   
                  Paul V. Gratz   WaveSync: Low-Latency Source-Synchronous
                                  Bypass Network-on-Chip Architecture  . . 34:1--34:??
                  John Jose and   
                   Madhu Mutyam   Implementation and Analysis of
                                  History-Based Output Channel Selection
                                  Strategies for Adaptive Routers in Mesh
                                  NoCs . . . . . . . . . . . . . . . . . . 35:1--35:??
               Kun-Lin Tsai and   
               Hao-Tse Chen and   
                      Yo-An Lin   Power and Area Efficiency NoC Router
                                  Design for Application-Specific SoC by
                                  Using Buffer Merging and Resource
                                  Sharing  . . . . . . . . . . . . . . . . 36:1--36:??
             Nadereh Hatami and   
           Rafal Baranowski and   
             Paolo Prinetto and   
        Hans-Joachim Wunderlich   Multilevel Simulation of Nonfunctional
                                  Properties by Piecewise Evaluation . . . 37:1--37:??
              Srivaths Ravi and   
                 Michael Joseph   High-Level Test Synthesis: a Survey from
                                  Synthesis Process Flow Perspective . . . 38:1--38:??
              Da-Cheng Juan and   
             Siddharth Garg and   
               Diana Marculescu   Statistical Peak Temperature Prediction
                                  and Thermal Yield Improvement for $3$D
                                  Chip Multiprocessors . . . . . . . . . . 39:1--39:??
     Vinicius S. Livramento and   
             Chrystian Guth and   
José Luís Güntzel and   
              Marcelo O. Johann   A Hybrid Technique for Discrete Gate
                                  Sizing Based on Lagrangian Relaxation    40:1--40:??
                   Yenpo Ho and   
             Garng M. Huang and   
                        Peng Li   Understanding SRAM Stability via
                                  Bifurcation Analysis: Analytical Models
                                  and Scaling Trends . . . . . . . . . . . 41:1--41:??


ACM Transactions on Design Automation of Electronic Systems
Volume 20, Number 1, November, 2014

             Naehyuck Chang and   
               David Z. Pan and   
                       Yuan Xie   Editorial: \booktitleACM Transactions on
                                  Design Automation of Electronics Systems
                                  and Beyond . . . . . . . . . . . . . . . 1:1--1:??
                     Wei Hu and   
                   Dejun Mu and   
                Jason Oberg and   
                 Baolei Mao and   
               Mohit Tiwari and   
           Timothy Sherwood and   
                   Ryan Kastner   Gate-Level Information Flow Tracking for
                                  Security Lattices  . . . . . . . . . . . 2:1--2:??
              Chun-Kai Wang and   
              Yeh-Chi Chang and   
             Hung-Ming Chen and   
                  Ching-Yu Chin   Clock Tree Synthesis Considering Slew
                                  Effect on Supply Voltage Variation . . . 3:1--3:??
                 Lingyi Liu and   
               Shobha Vasudevan   Scaling Input Stimulus Generation
                                  through Hybrid Static and Dynamic
                                  Analysis of RTL  . . . . . . . . . . . . 4:1--4:??
               Sharad Sinha and   
        Thambipillai Srikanthan   Dataflow Graph Partitioning for
                                  Area-Efficient High-Level Synthesis with
                                  Systems Perspective  . . . . . . . . . . 5:1--5:??
               Graeme Gange and   
  Harald Sòndergaard and   
               Peter J. Stuckey   Synthesizing Optimal Switching Lattices  6:1--6:??
               An-Che Cheng and   
       Chia-Chih (Jack) Yen and   
              Celina G. Val and   
                Sam Bayless and   
                 Alan J. Hu and   
          Iris Hui-Ru Jiang and   
                  Jing-Yang Jou   Efficient Coverage-Driven Stimulus
                                  Generation Using Simultaneous SAT
                                  Solving, with Application to
                                  SystemVerilog  . . . . . . . . . . . . . 7:1--7:??
                Xueliang Li and   
                 Guihai Yan and   
                  Yinhe Han and   
                     Xiaowei Li   SmartCap: Using Machine Learning for
                                  Power Adaptation of Smartphone's
                                  Application Processor  . . . . . . . . . 8:1--8:??
                Wen-Li Shih and   
                Yi-Ping You and   
            Chung-Wen Huang and   
                  Jenq Kuen Lee   Compiler Optimization for Reducing
                                  Leakage Power in Multithread BSP
                                  Programs . . . . . . . . . . . . . . . . 9:1--9:??
                Bojan Maric and   
               Jaume Abella and   
       Francisco J. Cazorla and   
                   Mateo Valero   Hybrid Cache Designs for Reliable Hybrid
                                  High and Ultra-Low Voltage Operation . . 10:1--10:??
            Seungcheol Baek and   
              Hyung Gyu Lee and   
    Chrysostomos Nicopoulos and   
                    Jongman Kim   Designing Hybrid DRAM/PCM Main Memory
                                  Systems Utilizing Dual-Phase Compression 11:1--11:??
              Hsien-Kai Kuo and   
       Bo-Cheng Charles Lai and   
                  Jing-Yang Jou   Reducing Contention in Shared Last-Level
                                  Cache for Throughput Processors  . . . . 12:1--12:??
               Roopak Sinha and   
              Alain Girault and   
            Gregor Goessler and   
                 Partha S. Roop   A Formal Approach to Incremental
                                  Converter Synthesis for System-on-Chip
                                  Design . . . . . . . . . . . . . . . . . 13:1--13:??
               Levent Aksoy and   
               Paulo Flores and   
                  Jose Monteiro   Multiplierless Design of Folded DSP
                                  Blocks . . . . . . . . . . . . . . . . . 14:1--14:??
     Mohamed Asan Basiri M. and   
               Noor Mahammad Sk   An Efficient Hardware-Based Higher Radix
                                  Floating Point MAC Design  . . . . . . . 15:1--15:??
         Cristiana Bolchini and   
              Chiara Sandionigi   Design of Hardened Embedded Systems on
                                  Multi-FPGA Platforms . . . . . . . . . . 16:1--16:??

ACM Transactions on Design Automation of Electronic Systems
Volume 20, Number 2, February, 2015

                 Jingwei Lu and   
               Pengwen Chen and   
            Chin-Chih Chang and   
                     Lu Sha and   
      Dennis Jen-Hsin Huang and   
              Chin-Chi Teng and   
               Chung-Kuan Cheng   ePlace: Electrostatics-Based Placement
                                  Using Fast Fourier Transform and
                                  Nesterov's Method  . . . . . . . . . . . 17:1--17:??
                     Qi Guo and   
               Tianshi Chen and   
               Zhi-Hua Zhou and   
              Olivier Temam and   
                    Ling Li and   
                 Depei Qian and   
                     Yunji Chen   Robust Design Space Modeling . . . . . . 18:1--18:??
        Mottaqiallah Taouil and   
              Said Hamdioui and   
            Erik Jan Marinissen   Yield Improvement for $3$D
                                  Wafer-to-Wafer Stacked ICs Using Wafer
                                  Matching . . . . . . . . . . . . . . . . 19:1--19:??
               Naiwen Chang and   
                Eddie Cheng and   
                  Sunyuan Hsieh   Conditional Diagnosability of Cayley
                                  Graphs Generated by Transposition Trees
                                  under the PMC Model  . . . . . . . . . . 20:1--20:??
                  Qing Duan and   
                   Jun Zeng and   
     Krishnendu Chakrabarty and   
                   Gary Dispoto   Data-Driven Optimization of Order
                                  Admission Policies in a Digital Print
                                  Factory  . . . . . . . . . . . . . . . . 21:1--21:??
              Cheng-Yen Lin and   
            Chung-Wen Huang and   
              Chi-Bang Kuan and   
               Shi-Yu Huang and   
                  Jenq-Kuen Lee   The Design and Experiments of a
                                  SID-Based Power-Aware Simulator for
                                  Embedded Multicore Systems . . . . . . . 22:1--22:??
            Marjan Asadinia and   
          Mohammad Arjomand and   
             Hamid Sarbazi Azad   Prolonging Lifetime of PCM-Based Main
                                  Memories through On-Demand Page Pairing  23:1--23:??
                 Xing Huang and   
               Genggeng Liu and   
               Wenzhong Guo and   
                 Yuzhen Niu and   
                   Guolong Chen   Obstacle-Avoiding Algorithm in
                                  X-Architecture Based on Discrete
                                  Particle Swarm Optimization for VLSI
                                  Design . . . . . . . . . . . . . . . . . 24:1--24:??
           Hung-Sheng Chang and   
             Yuan-Hao Chang and   
              Pi-Cheng Hsiu and   
                Tei-Wei Kuo and   
                 Hsiang-Pang Li   Marching-Based Wear-Leveling for
                                  PCM-Based Storage Systems  . . . . . . . 25:1--25:??
                  Gang Chen and   
                  Kai Huang and   
            Christian Buckl and   
                    Alois Knoll   Applying Pay-Burst-Only-Once Principle
                                  for Periodic Power Management in Hard
                                  Real-Time Pipelined Multiprocessor
                                  Systems  . . . . . . . . . . . . . . . . 26:1--26:??
               Franck Yonga and   
            Michael Mefenza and   
               Christophe Bobda   ASP-Based Encoding Model of Architecture
                                  Synthesis for Smart Cameras in
                                  Distributed Networks . . . . . . . . . . 27:1--27:??
                Lok-Won Kim and   
                 Dong-U Lee and   
                John Villasenor   Automated Iterative Pipelining for ASIC
                                  Design . . . . . . . . . . . . . . . . . 28:1--28:??
                 Irith Pomeranz   A Generalized Definition of Unnecessary
                                  Test Vectors in Functional Test
                                  Sequences  . . . . . . . . . . . . . . . 29:1--29:??
           Rafal Baranowski and   
          Michael A. Kochte and   
        Hans-Joachim Wunderlich   Reconfigurable Scan Networks: Modeling,
                                  Verification, and Optimal Pattern
                                  Generation . . . . . . . . . . . . . . . 30:1--30:??
               Kamel Beznia and   
            Ahcene Bounceur and   
            Reinhardt Euler and   
                   Salvador Mir   A Tool for Analog/RF BIST Evaluation
                                  Using Statistical Models of Circuit
                                  Parameters . . . . . . . . . . . . . . . 31:1--31:??
               Adwait Gupte and   
             Sudhanshu Vyas and   
               Phillip H. Jones   A Fault-Aware Toolchain Approach for
                                  FPGA Fault Tolerance . . . . . . . . . . 32:1--32:??
              Jiliang Zhang and   
                 Yaping Lin and   
                        Gang Qu   Reconfigurable Binding against FPGA
                                  Replay Attacks . . . . . . . . . . . . . 33:1--33:??

ACM Transactions on Design Automation of Electronic Systems
Volume 20, Number 3, June, 2015

            Meeta Srivastav and   
     Mohammed Ehteshamuddin and   
               Kyle Stegner and   
               Leyla Nazhandali   Design of Ultra-Low Power
                                  Scalable-Throughput Many-Core DSP
                                  Applications . . . . . . . . . . . . . . 34:1--34:??
             Fahimeh Jafari and   
                Zhonghai Lu and   
                   Axel Jantsch   Least Upper Delay Bound for VBR Flows in
                                  Networks-on-Chip with Virtual Channels   35:1--35:??
            Nicola Bombieri and   
               Franco Fummi and   
                     Sara Vinco   A Methodology to Recover RTL IP
                                  Functionality for Automatic Generation
                                  of SW Applications . . . . . . . . . . . 36:1--36:??
               Stefan Holst and   
           Michael E. Imhof and   
        Hans-Joachim Wunderlich   High-Throughput Logic Timing Simulation
                                  on GPGPUs  . . . . . . . . . . . . . . . 37:1--37:??
                    Tong Xu and   
                    Peng Li and   
         Savithri Sundareswaran   Decoupling Capacitance Design Strategies
                                  for Power Delivery Networks with Power
                                  Gating . . . . . . . . . . . . . . . . . 38:1--38:??
            Farshad Firouzi and   
                Fangming Ye and   
     Krishnendu Chakrabarty and   
               Mehdi B. Tahoori   Aging- and Variation-Aware Delay
                                  Monitoring Using Representative Critical
                                  Path Selection . . . . . . . . . . . . . 39:1--39:??
               Heejong Park and   
              Avinash Malik and   
                   Zoran Salcic   Scheduling Globally Asynchronous Locally
                                  Synchronous Programs for Guaranteed
                                  Response Times . . . . . . . . . . . . . 40:1--40:??
                 Qiuping Yi and   
               Zijiang Yang and   
                   Jian Liu and   
                  Chen Zhao and   
                      Chao Wang   Explaining Software Failures by Cascade
                                  Fault Localization . . . . . . . . . . . 41:1--41:??
              Jong Chul Lee and   
                  Roman Lysecky   System-Level Observation Framework for
                                  Non-Intrusive Runtime Monitoring of
                                  Embedded Systems . . . . . . . . . . . . 42:1--42:??
                   Qi Zhang and   
                Xuandong Li and   
              Linzhang Wang and   
                 Tian Zhang and   
                    Yi Wang and   
                      Zili Shao   Lazy-RTGC: a Real-Time Lazy Garbage
                                  Collection Mechanism with Jointly
                                  Optimizing Average and Worst Performance
                                  for NAND Flash Memory Storage Systems    43:1--43:??
              Namita Sharma and   
        Preeti Ranjan Panda and   
           Francky Catthoor and   
           Praveen Raghavan and   
                  Tom Vander Aa   Array Interleaving --- An
                                  Energy-Efficient Data Layout
                                  Transformation . . . . . . . . . . . . . 44:1--44:??
                  Sudip Roy and   
      Partha P. Chakrabarti and   
               Srijan Kumar and   
     Krishnendu Chakrabarty and   
        Bhargab B. Bhattacharya   Layout-Aware Mixture Preparation of
                                  Biochemical Fluids on
                                  Application-Specific Digital
                                  Microfluidic Biochips  . . . . . . . . . 45:1--45:??
       Chandra K. H. Suresh and   
                  Sule Ozev and   
                Ozgur Sinanoglu   Adaptive Generation of Unique IDs for
                                  Digital Chips through Analog Excitation  46:1--46:??

ACM Transactions on Design Automation of Electronic Systems
Volume 20, Number 4, September, 2015

               Hai-Bao Chen and   
                Ying-Chi Li and   
          Sheldon X.-D. Tan and   
                  Xin Huang and   
                   Hai Wang and   
                      Ngai Wong   $H$-Matrix-Based Finite-Element-Based
                                  Thermal Analysis for $3$D ICs  . . . . . 47:1--47:??
                Karel Heyse and   
           Brahim Al Farisi and   
              Karel Bruneel and   
                Dirk Stroobandt   TCONMAP: Technology Mapping for
                                  Parameterised FPGA Configurations  . . . 48:1--48:??
              Steffen Peter and   
                  Tony Givargis   Component-Based Synthesis of Embedded
                                  Systems Using Satisfiability Modulo
                                  Theories . . . . . . . . . . . . . . . . 49:1--49:??
                 Ali Mirtar and   
                  Sujit Dey and   
              Anand Raghunathan   An Application Adaptation Approach to
                                  Mitigate the Impact of Dynamic Thermal
                                  Management on Video Encoding . . . . . . 50:1--50:??
               Da-Wei Chang and   
             Hsin-Hung Chen and   
                    Wei-Jian Su   VSSD: Performance Isolation in a
                                  Solid-State Drive  . . . . . . . . . . . 51:1--51:??
                  Qing Duan and   
            Abhishek Koneru and   
                   Jun Zeng and   
     Krishnendu Chakrabarty and   
                   Gary Dispoto   Accurate Analysis and Prediction of
                                  Enterprise Service-Level Performance . . 52:1--52:??
                  Ingoo Heo and   
                  Minsu Kim and   
                 Yongje Lee and   
               Changho Choi and   
                Jinyong Lee and   
       Brent Byunghoon Kang and   
                  Yunheung Paek   Implementing an Application-Specific
                                  Instruction-Set Processor for
                                  System-Level Dynamic Program Analysis
                                  Engines  . . . . . . . . . . . . . . . . 53:1--53:??
                  Lei Jiang and   
                    Bo Zhao and   
                   Jun Yang and   
                   Youtao Zhang   Constructing Large and Fast On-Chip
                                  Cache for Mobile Processors with
                                  Multilevel Cell STT--MRAM Technology . . 54:1--54:??
Mohammad Hossein Samavatian and   
          Mohammad Arjomand and   
            Ramin Bashizade and   
             Hamid Sarbazi-Azad   Architecting the Last-Level Cache for
                                  GPUs using STT-RAM Technology  . . . . . 55:1--55:??
   Leandro Soares Indrusiak and   
               James Harbin and   
        Osmar Marchi Dos Santos   Fast Simulation of Networks-on-Chip with
                                  Priority-Preemptive Arbitration  . . . . 56:1--56:??
                 Irith Pomeranz   FOLD: Extreme Static Test Compaction by
                                  Folding of Functional Test Sequences . . 57:1--57:??
                   Ran Wang and   
     Krishnendu Chakrabarty and   
                Sudipta Bhawmik   Built-In Self-Test and Test Scheduling
                                  for Interposer-Based $ 2.5 $D IC . . . . 58:1--58:??
              R. Iris Bahar and   
              Alex K. Jones and   
                       Yuan Xie   Introduction to the Special Issue on
                                  Reliable, Resilient, and Robust Design
                                  of Circuits and Systems  . . . . . . . . 59:1--59:??
          Bradley T. Kiddie and   
        William H. Robinson and   
             Daniel B. Limbrick   Single-Event Multiple-Transient
                                  Characterization and Mitigation via
                                  Alternative Standard Cell Placement
                                  Methods  . . . . . . . . . . . . . . . . 60:1--60:??
       Leila Delshadtehrani and   
               Hamed Farbeh and   
         Seyed Ghassem Miremadi   In-Scratchpad Memory Replication:
                                  Protecting Scratchpad Memories in
                                  Multicore Embedded Systems against Soft
                                  Errors . . . . . . . . . . . . . . . . . 61:1--61:??
        Nikolaos Papandreou and   
             Thomas Parnell and   
         Haralampos Pozidis and   
        Thomas Mittelholzer and   
      Evangelos Eleftheriou and   
               Charles Camp and   
             Thomas Griffin and   
              Gary Tressler and   
                   Andrew Walls   Enhancing the Reliability of MLC NAND
                                  Flash Memory Systems by Read Channel
                                  Optimization . . . . . . . . . . . . . . 62:1--62:??
                    Cong Xu and   
                  Dimin Niu and   
                 Yang Zheng and   
                 Shimeng Yu and   
                       Yuan Xie   Impact of Cell Failure on Reliable
                                  Cross-Point Resistive Memory Design  . . 63:1--63:??
              Renyuan Zhang and   
                   Mineo Kaneko   Robust and Low-Power Digitally
                                  Programmable Delay Element Designs
                                  Employing Neuron-MOS Mechanism . . . . . 64:1--64:??
               Hyungjun Kim and   
    Siva Bhanu Krishna Boga and   
         Arseniy Vitkovskiy and   
   Stavros Hadjitheophanous and   
              Paul V. Gratz and   
            Vassos Soteriou and   
               Maria K. Michael   Use It or Lose It: Proactive,
                                  Deterministic Longevity in Future Chip
                                  Multiprocessors  . . . . . . . . . . . . 65:1--65:??
            Andrew B. Kahng and   
            Seokhyeong Kang and   
                  Jiajia Li and   
           Jose Pineda De Gyvez   An Improved Methodology for Resilient
                                  Design Implementation  . . . . . . . . . 66:1--66:??


ACM Transactions on Design Automation of Electronic Systems
Volume 21, Number 1, November, 2015

               Debashri Roy and   
              Prasun Ghosal and   
                 Saraju Mohanty   FuzzRoute: a Thermally Efficient
                                  Congestion-Free Global Routing Method
                                  for Three-Dimensional Integrated
                                  Circuits . . . . . . . . . . . . . . . . 1:1--1:??
                   Ye Zhang and   
              Wai-Shing Luk and   
               Yunfeng Yang and   
                   Hai Zhou and   
               Changhao Yan and   
               David Z. Pan and   
                      Xuan Zeng   Layout Decomposition with Pairwise
                                  Coloring and Adaptive Multi-Start for
                                  Triple Patterning Lithography  . . . . . 2:1--2:??
                    Hu Chen and   
            Sanghamitra Roy and   
            Koushik Chakraborty   DARP-MP: Dynamically Adaptable Resilient
                                  Pipeline Design in Multicore Processors  3:1--3:??
               Myungsun Kim and   
                 Jinkyu Koo and   
                Hyojung Lee and   
                James R. Geraci   Memory Management Scheme to Improve
                                  Utilization Efficiency and Provide Fast
                                  Contiguous Allocation without a
                                  Statically Reserved Area . . . . . . . . 4:1--4:??
              Fabian Oboril and   
               Mehdi B. Tahoori   Exploiting Instruction Set Encoding for
                                  Aging-Aware Microprocessor Design  . . . 5:1--5:??
                 Ankit More and   
                   Baris Taskin   Locality-Aware Network Utilization
                                  Balancing in NoCs  . . . . . . . . . . . 6:1--6:??
           Hsiang-Yun Cheng and   
            Mary Jane Irwin and   
                       Yuan Xie   Adaptive Burst-Writes (ABW): Memory
                                  Requests Scheduling to Reduce
                                  Write-Induced Interference . . . . . . . 7:1--7:??
        Gilberto Ochoa-Ruiz and   
   Sébastien Guillet and   
         Florent De Lamotte and   
                Eric Rutten and   
          El-Bay Bourennane and   
       Jean-Philippe Diguet and   
                    Guy Gogniat   An MDE Approach for Rapid Prototyping
                                  and Implementation of Dynamic
                                  Reconfigurable Systems . . . . . . . . . 8:1--8:??
             Shih-Hsu Huang and   
               Hua-Hsin Yeh and   
                  Yow-Tyng Nieh   Clock Period Minimization with Minimum
                                  Leakage Power  . . . . . . . . . . . . . 9:1--9:??
     Anupama R. Subramaniam and   
               Janet Roveda and   
                         Yu Cao   A Finite-Point Method for Efficient Gate
                                  Characterization Under Multiple Input
                                  Switching  . . . . . . . . . . . . . . . 10:1--10:??
                Dongha Jung and   
                Hokyoon Lee and   
                  Seon Wook Kim   Lowering Minimum Supply Voltage for
                                  Power-Efficient Cache Design by
                                  Exploiting Data Redundancy . . . . . . . 11:1--11:??
                   Ying Qin and   
               Shengyu Shen and   
                  Qingbo Wu and   
                Huadong Dai and   
                        Yan Jia   Complementary Synthesis for Encoder with
                                  Flow Control Mechanism . . . . . . . . . 12:1--12:??
                 Irith Pomeranz   Enhanced Test Compaction for Multicycle
                                  Broadside Tests by Using State
                                  Complementation  . . . . . . . . . . . . 13:1--13:??
             Seetal Potluri and   
           A. Satya Trinadh and   
            Sobhan Babu Ch. and   
                V. Kamakoti and   
           Nitin Chandrachoodan   DFT Assisted Techniques for Peak
                                  Launch-to-Capture Power Reduction during
                                  Launch-On-Shift At-Speed Testing . . . . 14:1--14:??
           Chien-Chih Huang and   
              Chin-Long Wey and   
                 Jwu-E Chen and   
                    Pei-Wen Luo   Performance-Driven Unit-Capacitor
                                  Placement of
                                  Successive-Approximation-Register ADCs   15:1--15:??
                    Jin Sun and   
           Claudio Talarico and   
              Priyank Gupta and   
                   Janet Roveda   A New Uncertainty Budgeting-Based Method
                                  for Robust Analog/Mixed-Signal Design    16:1--16:??
              Debasis Mitra and   
         Sarmishtha Ghoshal and   
            Hafizur Rahaman and   
     Krishnendu Chakrabarty and   
        Bhargab B. Bhattacharya   Offline Washing Schemes for Residue
                                  Removal in Digital Microfluidic Biochips 17:1--17:??
              Chung-Wei Lin and   
                Bowen Zheng and   
                     Qi Zhu and   
Alberto Sangiovanni-Vincentelli   Security-Aware Design Methodology and
                                  Optimization for Automotive Systems  . . 18:1--18:??

ACM Transactions on Design Automation of Electronic Systems
Volume 21, Number 2, January, 2016

               Daming Zhang and   
              Shuangchen Li and   
                Yongpan Liu and   
           Xiaobo Sharon Hu and   
                   Xinyu He and   
               Yining Zhang and   
                  Pei Zhang and   
                  Huazhong Yang   A C2RTL Framework Supporting Partition,
                                  Parallelization, and FIFO Sizing for
                                  Streaming Applications . . . . . . . . . 19:1--19:??
                Laurence Pierre   Auxiliary Variables in Temporal
                                  Specifications: Semantic and Practical
                                  Analysis for System-Level Requirements   20:1--20:??
                    Jin-Tai Yan   Performance-Driven Assignment of
                                  Buffered I/O Signals in Area-I/O
                                  Flip-Chip Designs  . . . . . . . . . . . 21:1--21:??
        Angeliki Kritikakou and   
           Francky Catthoor and   
        Vasilios Kelefouras and   
                  Costas Goutis   Array Size Computation under Uniform
                                  Overlapping and Irregular Accesses . . . 22:1--22:??
               Youngsik Kim and   
                Sungjoo Yoo and   
                     Sunggu Lee   Improving Write Performance by
                                  Controlling Target Resistance
                                  Distributions in MLC PRAM  . . . . . . . 23:1--23:??
                 Dong Xiang and   
                      Kele Shen   A New Unicast-Based Multicast Scheme for
                                  Network-on-Chip Router and Interconnect
                                  Testing  . . . . . . . . . . . . . . . . 24:1--24:??
                  Zipeng Li and   
                Tsung-Yi Ho and   
         Krishnendu Chakrabarty   Optimization of $3$D Digital
                                  Microfluidic Biochips for the
                                  Multiplexed Polymerase Chain Reaction    25:1--25:??
                   Le Zhang and   
                    Vivek Sarin   Parallel Power Grid Analysis Based on
                                  Enlarged Partitions  . . . . . . . . . . 26:1--26:??
                   Song Jin and   
                Songwei Pei and   
                  Yinhe Han and   
                      Huawei Li   A Cost-Effective Energy Optimization
                                  Framework of Multicore SoCs Based on
                                  Dynamically Reconfigurable
                                  Voltage-Frequency Islands  . . . . . . . 27:1--27:??
                Mehdi Kamal and   
           Ali Afzali-Kusha and   
               Saeed Safari and   
                 Massoud Pedram   Yield and Speedup Improvements in
                                  Extensible Processors by Allocating
                                  Extra Cycles to Some Custom Instructions 28:1--28:??
               Guoqing Chen and   
                      Yi Xu and   
                    Xing Hu and   
              Xiangyang Guo and   
                     Jun Ma and   
                      Yu Hu and   
                       Yuan Xie   TSocket: Thermal Sustainable Power
                                  Budgeting  . . . . . . . . . . . . . . . 29:1--29:??
                 Liang Chen and   
           Mojtaba Ebrahimi and   
               Mehdi B. Tahoori   Reliability-Aware Resource Allocation
                                  and Binding in High-Level Synthesis  . . 30:1--30:??
              Jeremy Dubeuf and   
                 David Hely and   
               Vincent Beroulle   ECDSA Passive Attacks, Leakage Sources,
                                  and Common Design Mistakes . . . . . . . 31:1--31:??
         Martin Lukasiewycz and   
           Philipp Mundhenk and   
           Sebastian Steinhorst   Security-Aware Obfuscated Priority
                                  Assignment for Automotive CAN Platforms  32:1--32:??
       Chandra K. H. Suresh and   
            Ozgur Sinanoglu and   
                      Sule Ozev   Adapting to Varying Distribution of
                                  Unknown Response Bits  . . . . . . . . . 33:1--33:??
             Jingweijia Tan and   
                     Zhi Li and   
              Mingsong Chen and   
                         Xin Fu   Exploring Soft-Error Robust and
                                  Energy-Efficient Register File in GPGPUs
                                  using Resistive Memory . . . . . . . . . 34:1--34:??
                 Irith Pomeranz   Design-for-Testability for Functional
                                  Broadside Tests under Primary Input
                                  Constraints  . . . . . . . . . . . . . . 35:1--35:??

ACM Transactions on Design Automation of Electronic Systems
Volume 21, Number 3, July, 2016

           Evangeline Young and   
                 Azadeh Davoodi   Preface to Special Section on New
                                  Physical Design Techniques for the Next
                                  Generation of Integration Technology . . 36:1--36:??
       Nima Karimpour Darav and   
            Andrew Kennings and   
       Aysa Fakheri Tabrizi and   
             David Westwick and   
                   Laleh Behjat   Eh?Placer: a High-Performance Modern
                                  Technology-Driven Placer . . . . . . . . 37:1--37:??
        Vinicius Livramento and   
                Renan Netto and   
             Chrystian Guth and   
José Luís Güntzel and   
          Luiz C. V. Dos Santos   Clock-Tree-Aware Incremental
                                  Timing-Driven Placement  . . . . . . . . 38:1--38:??
                 Po-Hsun Wu and   
           Mark Po-Hung Lin and   
                     Xin Li and   
                    Tsung-Yi Ho   Parasitic-Aware Common-Centroid FinFET
                                  Placement and Routing for Current-Ratio
                                  Matching . . . . . . . . . . . . . . . . 39:1--39:??
              Jinglei Huang and   
                  Song Chen and   
                  Wei Zhong and   
              Wenchao Zhang and   
               Shengxi Diao and   
                    Fujiang Lin   Floorplanning and Topology Synthesis for
                                  Application-Specific Network-on-Chips
                                  with RF-Interconnect . . . . . . . . . . 40:1--40:??
                   Chang Xu and   
                 Guojie Luo and   
                  Peixin Li and   
                   Yiyu Shi and   
              Iris Hui-Ru Jiang   Analytical Clustering Score with
                                  Application to Postplacement Register
                                  Clustering . . . . . . . . . . . . . . . 41:1--41:??
                Xiaoqing Xu and   
                     Bei Yu and   
              Jhih-Rong Gao and   
                Che-Lun Hsu and   
                   David Z. Pan   PARR: Pin-Access Planning and Regular
                                  Routing for Self-Aligned Double
                                  Patterning . . . . . . . . . . . . . . . 42:1--42:??
                     Bei Yu and   
                   Kun Yuan and   
              Jhih-Rong Gao and   
                  Shiyan Hu and   
                   David Z. Pan   EBL Overlapping Aware Stencil Planning
                                  for MCC System . . . . . . . . . . . . . 43:1--43:??
               Seungwon Kim and   
            Seokhyeong Kang and   
                 Ki Jin Han and   
                   Youngmin Kim   Novel Adaptive Power-Gating Strategy and
                                  Tapered TSV Structure in Multilayer $3$D
                                  IC . . . . . . . . . . . . . . . . . . . 44:1--44:??
                  Gong Chen and   
              Toru Fujimura and   
                  Qing Dong and   
        Shigetoshi Nakatake and   
                        Bo Yang   DC Characteristics and Variability on
                                  90nm CMOS Transistor Array-Style Analog
                                  Layout . . . . . . . . . . . . . . . . . 45:1--45:??
                  Chao Wang and   
            Chuansheng Dong and   
                 Haibo Zeng and   
                     Zonghua Gu   Minimizing Stack Memory for Hard
                                  Real-Time Applications on Multicore
                                  Platforms with Partitioned
                                  Fixed-Priority or EDF Scheduling . . . . 46:1--46:??
              Sungkwang Lee and   
                 Taemin Lee and   
               Hyunsun Park and   
                Junwhan Ahn and   
                Sungjoo Yoo and   
                 Youjip Won and   
                     Sunggu Lee   Differential Write-Conscious Software
                                  Design on Phase-Change Memory: an SQLite
                                  Case Study . . . . . . . . . . . . . . . 47:1--47:??
                 Xing Huang and   
               Wenzhong Guo and   
               Genggeng Liu and   
                   Guolong Chen   FH-OAOS: a Fast Four-Step Heuristic for
                                  Obstacle-Avoiding Octilinear Steiner
                                  Tree Construction  . . . . . . . . . . . 48:1--48:??
                  Sparsh Mittal   A Survey of Techniques for Cache Locking 49:1--49:??
Ramachandran Venkatasubramanian and   
                Robert Elio and   
                      Sule Ozev   Process Independent Design Methodology
                                  for the Active RC and
                                  Single-Inverter-Based Rail Clamp . . . . 50:1--50:??
                Sangmin Kim and   
            Seokhyeong Kang and   
                  Youngsoo Shin   Synthesis of Dual-Mode Circuits Through
                                  Library Design, Gate Sizing, and
                                  Clock-Tree Optimization  . . . . . . . . 51:1--51:??
              Zhiliang Qian and   
                Paul Bogdan and   
              Chi-Ying Tsui and   
                Radu Marculescu   Performance Evaluation of NoC-Based
                                  Multicore Systems: From Traffic Analysis
                                  to NoC Latency Modeling  . . . . . . . . 52:1--52:??
                Hany Kashif and   
                Hiren Patel and   
         Sebastian Fischmeister   Path Selection for Real-Time
                                  Communication on Priority-Aware NoCs . . 53:1--53:??
              Chuangwen Liu and   
                 Peishan Tu and   
                  Pangbo Wu and   
                 Haomo Tang and   
                Yande Jiang and   
                 Jian Kuang and   
         Evangeline F. Y. Young   An Effective Chemical Mechanical
                                  Polishing Fill Insertion Approach  . . . 54:1--54:??

ACM Transactions on Design Automation of Electronic Systems
Volume 21, Number 4, September, 2016

            Marcela Zuluaga and   
               Peter Milder and   
            Markus Püschel   Streaming Sorting Networks . . . . . . . 55:1--55:??
                   Yue Zhao and   
               Taeyoung Kim and   
                Hosoon Shin and   
          Sheldon X.-D. Tan and   
                     Xin Li and   
                Haibao Chen and   
                       Hai Wang   Statistical Rare-Event Analysis and
                                  Parameter Guidance by Elite Learning
                                  Sample Selection . . . . . . . . . . . . 56:1--56:??
              Rickard Ewetz and   
                  Cheng-Kok Koh   Construction of Reconfigurable Clock
                                  Trees for MCMM Designs Using Mode
                                  Separation and Scenario Compression  . . 57:1--57:??
         Hassan Ghasemzadeh and   
          Ramin Fallahzadeh and   
                 Roozbeh Jafari   A Hardware-Assisted Energy-Efficient
                                  Processing Model for Activity
                                  Recognition Using Wearables  . . . . . . 58:1--58:??
                 Adam Teman and   
               Davide Rossi and   
        Pascal Meinerzhagen and   
                Luca Benini and   
                   Andreas Burg   Power, Area, and Performance
                                  Optimization of Standard Cell Memory
                                  Arrays Through Controlled Placement  . . 59:1--59:??
  Swaminathan Narayanaswamy and   
          Steffen Schlueter and   
       Sebastian Steinhorst and   
         Martin Lukasiewycz and   
       Samarjit Chakraborty and   
             Harry Ernst Hoster   On Battery Recovery Effect in Wireless
                                  Sensor Nodes . . . . . . . . . . . . . . 60:1--60:??
                Dani Tannir and   
                    Ya Wang and   
                        Peng Li   Accurate Modeling of Nonideal Low-Power
                                  PWM DC--DC Converters Operating in CCM
                                  and DCM using Enhanced Circuit-Averaging
                                  Techniques . . . . . . . . . . . . . . . 61:1--61:??
       Sebastian Steinhorst and   
             Matthias Kauer and   
                 Arne Meeuw and   
  Swaminathan Narayanaswamy and   
         Martin Lukasiewycz and   
           Samarjit Chakraborty   Cyber-Physical Co-Simulation Framework
                                  for Smart Cells in Scalable Battery
                                  Packs  . . . . . . . . . . . . . . . . . 62:1--62:??
                Ujjwal Guin and   
                 Qihang Shi and   
              Domenic Forte and   
            Mark M. Tehranipoor   FORTIS: a Comprehensive Solution for
                                  Establishing Forward Trust for
                                  Protecting IPs and ICs . . . . . . . . . 63:1--63:??
                William Lee and   
               Vikas S. Vij and   
             Kenneth S. Stevens   Timing Path-Driven Cycle Cutting for
                                  Sequential Controllers . . . . . . . . . 64:1--64:??
                    Yang Xu and   
              Jürgen Teich   Hierarchical Statistical Leakage
                                  Analysis and Its Application . . . . . . 65:1--65:??
              Ramprasath S. and   
               Vinita Vasudevan   Efficient Algorithms for Discrete Gate
                                  Sizing and Threshold Voltage Assignment
                                  Based on an Accurate Analytical
                                  Statistical Yield Gradient . . . . . . . 66:1--66:??
               Hongfei Wang and   
          R. D. (Shawn) Blanton   Ensemble Reduction via Logic
                                  Minimization . . . . . . . . . . . . . . 67:1--67:??
                 Irith Pomeranz   $N$-Detection Test Sets for Circuits
                                  with Multiple Independent Scan Chains    68:1--68:??
               Jae-Yeon Won and   
              Paul V. Gratz and   
        Srinivas Shakkottai and   
                       Jiang Hu   Resource Sharing Centric Dynamic Voltage
                                  and Frequency Scaling for CMP Cores,
                                  Uncore, and Memory . . . . . . . . . . . 69:1--69:??
             Ching-Hsuan Ho and   
             Yung-Chih Chen and   
              Chun-Yao Wang and   
             Ching-Yi Huang and   
                Suman Datta and   
        Vijaykrishnan Narayanan   Area-Aware Decomposition for
                                  Single-Electron Transistor Arrays  . . . 70:1--70:??
                 Fubing Mao and   
              Yi-Chung Chen and   
                  Wei Zhang and   
             Hai (Helen) Li and   
                   Bingsheng He   Library-Based Placement and Routing in
                                  FPGAs with Support of Partial
                                  Reconfiguration  . . . . . . . . . . . . 71:1--71:??
            Anna Bernasconi and   
              Valentina Ciriani   Index-Resilient Zero-Suppressed BDDs:
                                  Definition and Operations  . . . . . . . 72:1--72:??


ACM Transactions on Design Automation of Electronic Systems
Volume 22, Number 1, December, 2016

                   Hai Wang and   
                    Jian Ma and   
          Sheldon X.-D. Tan and   
                  Chi Zhang and   
                    He Tang and   
               Keheng Huang and   
                Zhenghong Zhang   Hierarchical Dynamic Thermal Management
                                  Method for High-Performance Many-Core
                                  Microprocessors  . . . . . . . . . . . . 1:1--1:??
               Sudip Poddar and   
         Sarmishtha Ghoshal and   
     Krishnendu Chakrabarty and   
        Bhargab B. Bhattacharya   Error-Correcting Sample Preparation with
                                  Cyberphysical Digital Microfluidic
                                  Lab-on-Chip  . . . . . . . . . . . . . . 2:1--2:??
          Robert Czerwinski and   
                  Dariusz Kania   State Assignment and Optimization of
                                  Ultra-High-Speed FSMs Utilizing Tristate
                                  Buffers  . . . . . . . . . . . . . . . . 3:1--3:??
             Shirshendu Das and   
             Hemangee K. Kapoor   A Framework for Block Placement,
                                  Migration, and Fast Searching in
                                  Tiled-DNUCA Architecture . . . . . . . . 4:1--4:??
                  Yu-Wei Wu and   
                   Yiyu Shi and   
                  Sudip Roy and   
                    Tsung-Yi Ho   Obstacle-Avoiding Wind Turbine Placement
                                  for Power Loss and Wake Effect
                                  Optimization . . . . . . . . . . . . . . 5:1--5:??
                    K. Xiao and   
                   D. Forte and   
                     Y. Jin and   
                   R. Karri and   
                  S. Bhunia and   
                 M. Tehranipoor   Hardware Trojans: Lessons Learned after
                                  One Decade of Research . . . . . . . . . 6:1--6:??
                 Irith Pomeranz   Periodic Scan-In States to Reduce the
                                  Input Test Data Volume for Partially
                                  Functional Broadside Tests . . . . . . . 7:1--7:??
                Jinyong Lee and   
                  Ingoo Heo and   
                 Yongje Lee and   
                  Yunheung Paek   Efficient Security Monitoring with the
                                  Core Debug Interface in an Embedded
                                  Processor  . . . . . . . . . . . . . . . 8:1--8:??
              Yu-Ming Chang and   
              Pi-Cheng Hsiu and   
             Yuan-Hao Chang and   
               Chi-Hao Chen and   
                Tei-Wei Kuo and   
        Cheng-Yuan Michael Wang   Improving PCM Endurance with a
                                  Constant-Cost Wear Leveling Design . . . 9:1--9:??
                      Xu He and   
                   Yao Wang and   
                   Yang Guo and   
         Evangeline F. Y. Young   Ripple 2.0: Improved Movement of Cells
                                  in Routability-Driven Placement  . . . . 10:1--10:??
        Bodhisatwa Mazumdar and   
             Sk. Subidh Ali and   
                Ozgur Sinanoglu   A Compact Implementation of Salsa20 and
                                  Its Power Analysis Vulnerabilities . . . 11:1--11:??
      Prasenjit Chakraborty and   
        Preeti Ranjan Panda and   
                    Sandeep Sen   Partitioning and Data Mapping in
                                  Reconfigurable Cache and Scratchpad
                                  Memory-Based Architectures . . . . . . . 12:1--12:??
              Hossein Mehri and   
                 Bijan Alizadeh   Genetic-Algorithm-Based FPGA
                                  Architectural Exploration Using
                                  Analytical Models  . . . . . . . . . . . 13:1--13:??
             Ganesh Gingade and   
                 Wenyi Chen and   
             Yung-Hsiang Lu and   
               Jan Allebach and   
Hernan Ildefonso Gutierrez-Vazquez   Hybrid Power Management for Office
                                  Equipment  . . . . . . . . . . . . . . . 14:1--14:??
        Joost-Pieter Katoen and   
                         Hao Wu   Probabilistic Model Checking for
                                  Uncertain Scenario-Aware Data Flow . . . 15:1--15:??
                 Qixiao Liu and   
              Miquel Moreto and   
               Jaume Abella and   
       Francisco J. Cazorla and   
                   Mateo Valero   DReAM: an Approach to Estimate per-Task
                                  DRAM Energy in Multicore Systems . . . . 16:1--16:??
    Ahish Mysore Somashekar and   
           Spyros Tragoudas and   
       Rathish Jayabharathi and   
            Sreenivas Gangadhar   Non-enumerative Generation of Path Delay
                                  Distributions and Its Application to
                                  Critical Path Selection  . . . . . . . . 17:1--17:??
                    Yi Wang and   
                 Zhiwei Qin and   
                Renhai Chen and   
                  Zili Shao and   
               Laurence T. Yang   An Adaptive Demand-Based Caching
                                  Mechanism for NAND Flash Memory Storage
                                  Systems  . . . . . . . . . . . . . . . . 18:1--18:??
 Piyoosh Purushothaman Nair and   
               Arnab Sarkar and   
               N. M. Harsha and   
               Megha Gandhi and   
          P. P. Chakrabarti and   
                    Sujoy Ghose   ERfair Scheduler with Processor
                                  Suspension for Real-Time Multiprocessor
                                  Embedded Systems . . . . . . . . . . . . 19:1--19:??

ACM Transactions on Design Automation of Electronic Systems
Volume 22, Number 2, March, 2017

           Phuong Ha Nguyen and   
         Durga Prasad Sahoo and   
   Rajat Subhra Chakraborty and   
           Debdeep Mukhopadhyay   Security Analysis of Arbiter PUF and Its
                                  Lightweight Compositions Under
                                  Predictability Test  . . . . . . . . . . 20:1--20:??
                     Di Zhu and   
                   Siyu Yue and   
             Massoud Pedram and   
                   Lizhong Chen   CALM: Contention-Aware Latency-Minimal
                                  Application Mapping for Flattened
                                  Butterfly On-Chip Networks . . . . . . . 21:1--21:??
      Mohammad Reza Azarbad and   
                 Bijan Alizadeh   Scalable SMT-Based Equivalence Checking
                                  of Nested Loop Pipelining in Behavioral
                                  Synthesis  . . . . . . . . . . . . . . . 22:1--22:??
              Qingling Zhao and   
             Zaid Al-Bayati and   
                 Zonghua Gu and   
                     Haibo Zeng   Optimized Implementation of Multirate
                                  Mixed-Criticality Synchronous Reactive
                                  Models . . . . . . . . . . . . . . . . . 23:1--23:??
           Hazem Ismail Ali and   
              Sander Stuijk and   
              Benny Akesson and   
       Luís Miguel Pinho   Reducing the Complexity of Dataflow
                                  Graphs Using Slack-Based Merging . . . . 24:1--24:??
           Philipp Mundhenk and   
              Andrew Paverd and   
               Artur Mrowca and   
       Sebastian Steinhorst and   
         Martin Lukasiewycz and   
            Suhaib A. Fahmy and   
           Samarjit Chakraborty   Security in Automotive Networks:
                                  Lightweight Authentication and
                                  Authorization  . . . . . . . . . . . . . 25:1--25:??
              Xianwei Zhang and   
               Youtao Zhang and   
          Bruce R. Childers and   
                       Jun Yang   On the Restore Time Variations of Future
                                  DRAM Memory  . . . . . . . . . . . . . . 26:1--26:??
                Ye-Jyun Lin and   
              Chia-Lin Yang and   
             Hsiang-Pang Li and   
        Cheng-Yuan Michael Wang   A Hybrid DRAM/PCM Buffer Cache
                                  Architecture for Smartphones with QoS
                                  Consideration  . . . . . . . . . . . . . 27:1--27:??
                    Hang Su and   
                  Dakai Zhu and   
                   Scott Brandt   An Elastic Mixed-Criticality Task Model
                                  and Early-Release EDF Scheduling
                                  Algorithms . . . . . . . . . . . . . . . 28:1--28:??
                 Irith Pomeranz   Computation of Seeds for LFSR-Based
                                  $n$-Detection Test Generation  . . . . . 29:1--29:??
               Can Hankendi and   
           Ayse Kivilcim Coskun   Scale & Cap: Scaling-Aware Resource
                                  Management for Consolidated
                                  Multi-threaded Applications  . . . . . . 30:1--30:??
               Jerry Backer and   
                 David Hely and   
                   Ramesh Karri   Secure and Flexible Trace-Based
                                  Debugging of Systems-on-Chip . . . . . . 31:1--31:??
            Ioannis Latifis and   
          Karthick Parashar and   
     Grigoris Dimitroulakos and   
              Hans Cappelle and   
           Christakis Lezos and   
      Konstantinos Masselos and   
               Francky Catthoor   A MATLAB Vectorizing Compiler Targeting
                                  Application-Specific Instruction Set
                                  Processors . . . . . . . . . . . . . . . 32:1--32:28
                 Rui Santos and   
   Shyamsundar Venkataraman and   
                    Akash Kumar   Scrubbing Mechanism for Heterogeneous
                                  Applications in Reconfigurable Devices   33:1--33:??
              Andrea Enrici and   
           Ludovic Apvrille and   
                 Renaud Pacalet   A Model-Driven Engineering Methodology
                                  to Design Parallel and Distributed
                                  Embedded Systems . . . . . . . . . . . . 34:1--34:??
                Twan Basten and   
            Orlando Moreira and   
               Robert de Groote   Special Section: Integrating Dataflow,
                                  Embedded Computing and Architecture  . . 35:1--35:??
               Junchul Choi and   
                     Soonhoi Ha   Worst-Case Response Time Analysis of a
                                  Synchronous Dataflow Graph in a
                                  Multiprocessor System with Real-Time
                                  Tasks  . . . . . . . . . . . . . . . . . 36:1--36:??
              Hanwoong Jung and   
                  Hyunok Oh and   
                     Soonhoi Ha   Multiprocessor Scheduling of a
                                  Multi-Mode Dataflow Graph Considering
                                  Mode Transition Delay  . . . . . . . . . 37:1--37:??
              Adnan Bouakaz and   
              Pascal Fradet and   
                  Alain Girault   A Survey of Parametric Dataflow Models
                                  of Computation . . . . . . . . . . . . . 38:1--38:??
              Adnan Bouakaz and   
              Pascal Fradet and   
                  Alain Girault   Symbolic Analyses of Dataflow Graphs . . 39:1--39:??

ACM Transactions on Design Automation of Electronic Systems
Volume 22, Number 3, May, 2017

               Jaehyun Park and   
            Seungcheol Baek and   
              Hyung Gyu Lee and   
    Chrysostomos Nicopoulos and   
               Vinson Young and   
                Junghee Lee and   
                    Jongman Kim   HoPE: Hot-Cacheline Prediction for
                                  Dynamic Early Decompression in
                                  Compressed LLCs  . . . . . . . . . . . . 40:1--40:??
                    Li Tang and   
         Richard F. Barrett and   
               Jeanine Cook and   
                   X. Sharon Hu   PeaPaw: Performance and Energy-Aware
                                  Partitioning of Workload on
                                  Heterogeneous Platforms  . . . . . . . . 41:1--41:??
                   Kun Yang and   
              Domenic Forte and   
            Mark M. Tehranipoor   CDTA: a Comprehensive Solution for
                                  Counterfeit Detection, Traceability, and
                                  Authentication in the IoT Supply Chain   42:1--42:??
                 Irith Pomeranz   Generation of Transparent-Scan Sequences
                                  for Diagnosis of Scan Chain Faults . . . 43:1--43:??
         Korosh Vatanparvar and   
   Mohammad Abdullah Al Faruque   Application-Specific Residential
                                  Microgrid Design Methodology . . . . . . 44:1--44:??
                    Jin-Tai Yan   Layer Assignment of Escape Buses with
                                  Consecutive Constraints in PCB Designs   45:1--45:??
               Yin-Chi Peng and   
            Chien-Chih Chen and   
            Hsiang-Jen Tsai and   
              Keng-Hao Yang and   
              Pei-Zhe Huang and   
           Shih-Chieh Chang and   
               Wen-Ben Jone and   
                   Tien-Fu Chen   Leak Stopper: an Actively Revitalized
                                  Snoop Filter Architecture with Effective
                                  Generation Control . . . . . . . . . . . 46:1--46:??
                Guoyong Shi and   
                  Hanbin Hu and   
                    Shuwen Deng   Topological Approach to Automatic
                                  Symbolic Macromodel Generation for
                                  Analog Integrated Circuits . . . . . . . 47:1--47:??
                 Miseon Han and   
               Youngsun Han and   
              Seon Wook Kim and   
                Hokyoon Lee and   
                        Il Park   Content-Aware Bit Shuffling for
                                  Maximizing PCM Endurance . . . . . . . . 48:1--48:??
                Shamik Saha and   
                Prabal Basu and   
Chidhambaranathan Rajamanikkam and   
                Aatreyi Bal and   
        Koushik Chakraborty and   
                Sanghamitra Roy   SSAGA: SMs Synthesized for Asymmetric
                                  GPGPU Applications . . . . . . . . . . . 49:1--49:??
                 Tiantao Lu and   
               Ankur Srivastava   Low-Power Clock Tree Synthesis for
                                  $3$D-ICs . . . . . . . . . . . . . . . . 50:1--50:??
                 Woojoo Lee and   
               Kyuseung Han and   
                Yanzhi Wang and   
               Tiansong Cui and   
            Shahin Nazarian and   
                 Massoud Pedram   TEI-power: Temperature Effect
                                  Inversion-Aware Dynamic Thermal
                                  Management . . . . . . . . . . . . . . . 51:1--51:??
                 Yongje Lee and   
                Jinyong Lee and   
                  Ingoo Heo and   
               Dongil Hwang and   
                  Yunheung Paek   Using CoreSight PTM to Integrate CRA
                                  Monitoring IPs in an ARM-Based SoC . . . 52:1--52:??
                Yuankun Xue and   
                      Ji Li and   
            Shahin Nazarian and   
                    Paul Bogdan   Fundamental Challenges Toward Making the
                                  IoT a Reachable Reality: a Model-Centric
                                  Investigation  . . . . . . . . . . . . . 53:1--53:??
                   Zimu Guo and   
                     Jia Di and   
        Mark M. Tehranipoor and   
                  Domenic Forte   Obfuscation-Based Protection Framework
                                  against Printed Circuit Boards
                                  Unauthorized Operation and Reverse
                                  Engineering  . . . . . . . . . . . . . . 54:1--54:??
            Mohammad Torabi and   
                   Lihong Zhang   A Fast Hierarchical Adaptive Analog
                                  Routing Algorithm Based on Integer
                                  Linear Programming . . . . . . . . . . . 55:1--55:??
                  Yang Song and   
              Kambiz Samadi and   
                       Bill Lin   A Single-Tier Virtual Queuing Memory
                                  Controller Architecture for
                                  Heterogeneous MPSoCs . . . . . . . . . . 56:1--56:??
                      Ji Li and   
                 Jeffrey Draper   Accelerated Soft-Error-Rate (SER)
                                  Estimation for Combinational and
                                  Sequential Circuits  . . . . . . . . . . 57:1--57:??

ACM Transactions on Design Automation of Electronic Systems
Volume 22, Number 4, July, 2017

                  Kaige Yan and   
                    Lu Peng and   
              Mingsong Chen and   
                         Xin Fu   Exploring Energy-Efficient Cache Design
                                  in Emerging Mobile Platforms . . . . . . 58:1--58:??
                Taehyun Kim and   
                Jongbum Lim and   
                  Jinku Kim and   
              Woo-Cheol Cho and   
            Eui-Young Chung and   
                   Hyuk-Jun Lee   Scalable Bandwidth Shaping Scheme via
                                  Adaptively Managed Parallel Heaps in
                                  Manycore-Based Network Processors  . . . 59:1--59:??
            Prabhav Agrawal and   
            Mike Broxterman and   
       Biswadeep Chatterjee and   
             Patrick Cuevas and   
           Kathy H. Hayashi and   
            Andrew B. Kahng and   
            Pranay K. Myana and   
                Siddhartha Nath   Optimal Scheduling and Allocation for IC
                                  Design Management and Cost Reduction . . 60:1--60:??
            Tobias Isenberg and   
             Marco Platzner and   
             Heike Wehrheim and   
                Tobias Wiersema   Proof-Carrying Hardware via Inductive
                                  Invariants . . . . . . . . . . . . . . . 61:1--61:??
             Andrea Bonetti and   
            Nicholas Preyss and   
                 Adam Teman and   
                   Andreas Burg   Automated Integration of Dual-Edge
                                  Clocking for Low-Power Operation in
                                  Nanometer Nodes  . . . . . . . . . . . . 62:1--62:??
       Katherine Shu-Min Li and   
                Sying-Jyan Wang   Design Methodology of Fault-Tolerant
                                  Custom $3$D Network-on-Chip  . . . . . . 63:1--63:??
    Daniele Jahier Pagliari and   
               Enrico Macii and   
                Massimo Poncino   Approximate Energy-Efficient Encoding
                                  for Serial Interfaces  . . . . . . . . . 64:1--64:??
       Benjamin Carrion Schafer   Parallel High-Level Synthesis Design
                                  Space Exploration for Behavioral IPs of
                                  Exact Latencies  . . . . . . . . . . . . 65:1--65:??
             Zahi Moudallal and   
                  Farid N. Najm   Generating Current Constraints to
                                  Guarantee RLC Power Grid Safety  . . . . 66:1--66:??
             Irith Pomeranz and   
           M. Enamul Amyeen and   
          Srikanth Venkataraman   Test Modification for Reduced Volumes of
                                  Fail Data  . . . . . . . . . . . . . . . 67:1--67:??
                    Ya Wang and   
                     Di Gao and   
                Dani Tannir and   
                  Ning Dong and   
              G. Peter Fang and   
                   Wei Dong and   
                        Peng Li   Multiharmonic Small-Signal Modeling of
                                  Low-Power PWM DC-DC Converters . . . . . 68:1--68:??
            Hassan Albalawi and   
                Yuanning Li and   
                         Xin Li   Training Fixed-Point Classifiers for
                                  On-Chip Low-Power Implementation . . . . 69:1--69:??
         Mohaddeseh Hoveida and   
      Fatemeh Aghaaliakbari and   
            Ramin Bashizade and   
          Mohammad Arjomand and   
             Hamid Sarbazi-Azad   Efficient Mapping of Applications for
                                  Future Chip-Multiprocessors in Dark
                                  Silicon Era  . . . . . . . . . . . . . . 70:1--70:??
               Sangeet Saha and   
               Arnab Sarkar and   
              Amlan Chakrabarti   Spatio-Temporal Scheduling of Preemptive
                                  Real-Time Tasks on Partially
                                  Reconfigurable Systems . . . . . . . . . 71:1--71:??
               Jaume Abella and   
              Maria Padilla and   
          Joan Del Castillo and   
           Francisco J. Cazorla   Measurement-Based Worst-Case Execution
                                  Time Estimation Using the Coefficient of
                                  Variation  . . . . . . . . . . . . . . . 72:1--72:??
               Zoran Salcic and   
               Heejong Park and   
          Jürgen Teich and   
              Avinash Malik and   
                Muhammad Nadeem   Noc-HMP: a Heterogeneous Multicore
                                  Processor for Embedded Systems Designed
                                  in SystemJ . . . . . . . . . . . . . . . 73:1--73:??
           Lalatendu Behera and   
               Purandar Bhaduri   Time-Triggered Scheduling of
                                  Mixed-Criticality Systems  . . . . . . . 74:1--74:??
                 Derong Liu and   
                     Bei Yu and   
            Salim Chowdhury and   
                   David Z. Pan   Incremental Layer Assignment for Timing
                                  Optimization . . . . . . . . . . . . . . 75:1--75:??


ACM Transactions on Design Automation of Electronic Systems
Volume 23, Number 1, October, 2017

                  Zhaori Bi and   
                  Dian Zhou and   
             Sheng-Guo Wang and   
                      Xuan Zeng   Optimization and Quality Estimation of
                                  Circuit Design via Random Region
                                  Covering Method  . . . . . . . . . . . . 1:1--1:??
            Jae Woong Jeong and   
       Vishwanath Natarajan and   
                Shreyas Sen and   
                     Tm Mak and   
           Jennifer Kitchen and   
                      Sule Ozev   A Comprehensive BIST Solution for Polar
                                  Transceivers Using On-Chip Resources . . 2:1--2:??
         Korosh Vatanparvar and   
   Mohammad Abdullah Al Faruque   Electric Vehicle Optimized Charge and
                                  Drive Management . . . . . . . . . . . . 3:1--3:??
                 Shuai Wang and   
             Guangshan Duan and   
                  Yupeng Li and   
                   Qianhao Dong   Word- and Partition-Level Write
                                  Variation Reduction for Improving
                                  Non-Volatile Cache Lifetime  . . . . . . 4:1--4:??
           A. Satya Trinadh and   
             Seetal Potluri and   
            Sobhan Babu Ch. and   
                V. Kamakoti and   
              Shiv Govind Singh   Optimal Don't Care Filling for
                                  Minimizing Peak Toggles During At-Speed
                                  Stuck-At Testing . . . . . . . . . . . . 5:1--5:??
                Xingquan Li and   
                    Wenxing Zhu   Two-Stage Layout Decomposition for
                                  Hybrid E-Beam and Triple Patterning
                                  Lithography  . . . . . . . . . . . . . . 6:1--6:??
                 Sourav Das and   
                Dongjin Lee and   
                 Wonje Choi and   
        Janardhan Rao Doppa and   
        Partha Pratim Pande and   
         Krishnendu Chakrabarty   VFI-Based Power Management to Enhance
                                  the Lifetime of High-Performance $3$D
                                  NoCs . . . . . . . . . . . . . . . . . . 7:1--7:??
    Shanmugakumar Murugesan and   
               Noor Mahammad Sk   A Novel Range Matching Architecture for
                                  Packet Classification Without Rule
                                  Expansion  . . . . . . . . . . . . . . . 8:1--8:??
             P. R. Chithira and   
               Vinita Vasudevan   A Hierarchical Technique for Statistical
                                  Path Selection and Criticality
                                  Computation  . . . . . . . . . . . . . . 9:1--9:??
               Hyungon Moon and   
                Jinyong Lee and   
               Dongil Hwang and   
               Seonhwa Jung and   
                  Jiwon Seo and   
                  Yunheung Paek   Architectural Supports to Protect OS
                                  Kernels from Code-Injection Attacks and
                                  Their Applications . . . . . . . . . . . 10:1--10:??
               Yunfeng Yang and   
              Wai-Shing Luk and   
                   Hai Zhou and   
               David Z. Pan and   
                  Dian Zhou and   
               Changhao Yan and   
                      Xuan Zeng   An Effective Layout Decomposition Method
                                  for DSA with Multiple Patterning in
                                  Contact-Hole Generation  . . . . . . . . 11:1--11:??
                  Chao Chen and   
              Giovanni Beltrame   An Adaptive Markov Model for the Timing
                                  Analysis of Probabilistic Caches . . . . 12:1--12:??