Last update:
Wed Mar 20 07:29:20 MDT 2024
Duncan Buell and
Wayne Luk Introduction . . . . . . . . . . . . . . 1:1--1:??
André DeHon and
Mike Hutton Guest Editorial: TRETS Special Edition
on the 15th International Symposium on
FPGAs . . . . . . . . . . . . . . . . . 2:1--2:??
Yohei Matsumoto and
Masakazu Hioki and
Takashi Kawanami and
Hanpei Koike and
Toshiyuki Tsutsumi and
Tadashi Nakagawa and
Toshihiro Sekigawa Suppression of Intrinsic Delay Variation
in FPGAs using Multiple Configurations 3:1--3:??
Satish Sivaswamy and
Kia Bazargan Statistical Analysis and Process
Variation-Aware Routing and Skew
Assignment for FPGAs . . . . . . . . . . 4:1--4:??
Shih-Lien L. Lu and
Peter Yiannacouras and
Taeweon Suh and
Rolf Kassa and
Michael Konow A Desktop Computer with a Reconfigurable
Pentium\reg . . . . . . . . . . . . . . 5:1--5:??
Wenyi Feng and
Sinan Kaptanoglu Designing Efficient Input Interconnect
Blocks for LUT Clusters Using Counting
and Entropy . . . . . . . . . . . . . . 6:1--6:??
Steven J. E. Wilton and
Chun Hok Ho and
Bradley Quinton and
Philip H. W. Leong and
Wayne Luk A Synthesizable Datapath-Oriented
Embedded FPGA Fabric for Silicon Debug
Applications . . . . . . . . . . . . . . 7:1--7:??
Tim Güneysu and
Christof Paar and
Jan Pelzl Special-Purpose Hardware for Solving the
Elliptic Curve Discrete Logarithm
Problem . . . . . . . . . . . . . . . . 8:1--8:??
Arpith Jacob and
Joseph Lancaster and
Jeremy Buhler and
Brandon Harris and
Roger D. Chamberlain Mercury BLASTP: Accelerating Protein
Sequence Alignment . . . . . . . . . . . 9:1--9:??
Pete Sedcole and
Peter Y. K. Cheung Parametric Yield Modeling and
Simulations of FPGA Circuits Considering
Within-Die Delay Variations . . . . . . 10:1--10:??
Bita Gorjiara and
Mehrdad Reshadi and
Daniel Gajski Merged Dictionary Code Compression for
FPGA Implementation of Custom Microcoded
PEs . . . . . . . . . . . . . . . . . . 11:1--11:??
David B. Thomas and
Wayne Luk Multivariate Gaussian Random Number
Generation Targeting Reconfigurable
Hardware . . . . . . . . . . . . . . . . 12:1--12:??
Julien Lamoureux and
Steven J. E. Wilton On the trade-off between power and
flexibility of FPGA clock networks . . . 13:1--13:??
David Slogsnat and
Alexander Giese and
Mondrian Nüssle and
Ulrich Brüning An open-source HyperTransport core . . . 14:1--14:??
John S. Beeckler and
Warren J. Gross Particle graphics on reconfigurable
hardware . . . . . . . . . . . . . . . . 15:1--15:??
David Grant and
Guy Lemieux Perturb $+$ mutate: Semisynthetic
circuit generation for incremental
placement and routing . . . . . . . . . 16:1--16:??
Pao-Ann Hsiung and
Chao-Sheng Lin and
Chih-Feng Liao Perfecto: a SystemC-based design-space
exploration framework for dynamically
reconfigurable architectures . . . . . . 17:1--17:??
Scott Y. L. Chin and
Steven J. E. Wilton Static and Dynamic Memory Footprint
Reduction for FPGA Routing Algorithms 18:1--18:??
Ning-Yi Xu and
Xiong-Fei Cai and
Rui Gao and
Lei Zhang and
Feng-Hsiung Hsu FPGA Acceleration of RankBoost in Web
Search Engines . . . . . . . . . . . . . 19:1--19:??
C. D. Patterson and
S. W. Ellingson and
B. S. Martin and
K. Deshpande and
J. H. Simonetti and
M. Kavic and
S. E. Cutchin Searching for Transient Pulses with the
ETA Radio Telescope . . . . . . . . . . 20:1--20:??
Esam El-Araby and
Ivan Gonzalez and
Tarek El-Ghazawi Exploiting Partial Runtime
Reconfiguration for High-Performance
Reconfigurable Computing . . . . . . . . 21:1--21:??
Brian Holland and
Karthik Nagarajan and
Alan D. George RAT: RC Amenability Test for Rapid
Performance Prediction . . . . . . . . . 22:1--22:??
S. Murtaza and
A. G. Hoekstra and
P. M. A. Sloot Compute Bound and I/O Bound Cellular
Automata Simulations on FPGA Logic . . . 23:1--23:??
Christos-S. Bouganis and
Sung-Boem Park and
George A. Constantinides and
Peter Y. K. Cheung Synthesis and Optimization of $2$D
Filter Designs for Heterogeneous FPGAs 24:1--24:??
Patrick R. Schaumont and
Alex K. Jones and
Steve Trimberger Guest Editors' Introduction to Security
in Reconfigurable Systems Design . . . . 1:1--1:??
Maurice Keller and
Andrew Byrne and
William P. Marnane Elliptic Curve Cryptography on FPGA for
Low-Power Applications . . . . . . . . . 2:1--2:??
Robert P. McEvoy and
Colin C. Murphy and
William P. Marnane and
Michael Tunstall Isolated WDDL: a Hiding Countermeasure
for Differential Power Analysis on FPGAs 3:1--3:??
Laurent Sauvage and
Sylvain Guilley and
Yves Mathieu Electromagnetic Radiations of FPGAs:
High Spatial Resolution Cartography and
Attack on a Cryptographic Module . . . . 4:1--4:??
Mehrdad Majzoobi and
Farinaz Koushanfar and
Miodrag Potkonjak Techniques for Design and Implementation
of Secure Reconfigurable PUFs . . . . . 5:1--5:??
Shantanu Dutt and
Li Li Trust-Based Design and Check of FPGA
Circuits Using Two-Level Randomized ECC
Structures . . . . . . . . . . . . . . . 6:1--6:??
Hideharu Amano and
Tadao Nakamura Guest editors' introduction: ICFPT 2007 7:1--7:??
Weisheng Zhao and
Eric Belhaire and
Claude Chappert and
Bernard Dieny and
Guillaume Prenat TAS-MRAM-Based Low-Power High-Speed
Runtime Reconfiguration (RTR) FPGA . . . 8:1--8:??
Dirk Koch and
Christian Beckhoff and
Jürgen Teich Hardware Decompression Techniques for
FPGA-Based Embedded Systems . . . . . . 9:1--9:??
Justin S. J. Wong and
Pete Sedcole and
Peter Y. K. Cheung Self-Measurement of Combinatorial
Circuit Delays in FPGAs . . . . . . . . 10:1--10:??
G. Seetharaman and
B. Venkataramani Automation Schemes for FPGA
Implementation of Wave-Pipelined
Circuits . . . . . . . . . . . . . . . . 11:1--11:??
Jason Yu and
Christopher Eagleston and
Christopher Han-Yu Chou and
Maxime Perreault and
Guy Lemieux Vector Processing as a Soft Processor
Accelerator . . . . . . . . . . . . . . 12:1--12:??
Alessandro Cevrero and
Panagiotis Athanasopoulos and
Hadi Parandeh-Afshar and
Ajay K. Verma and
Hosein Seyed Attarzadeh Niaki and
Chrysostomos Nicopoulos and
Frank K. Gurkaynak and
Philip Brisk and
Yusuf Leblebici and
Paolo Ienne Field Programmable Compressor Trees:
Acceleration of Multi-Input Addition on
FPGAs . . . . . . . . . . . . . . . . . 13:1--13:??
Stephen Jang and
Billy Chan and
Kevin Chung and
Alan Mishchenko WireMap: FPGA Technology Mapping for
Improved Routability and Enhanced LUT
Merging . . . . . . . . . . . . . . . . 14:1--14:??
Eric S. Chung and
Michael K. Papamichael and
Eriko Nurvitadhi and
James C. Hoe and
Ken Mai and
Babak Falsafi ProtoFlex: Towards Scalable, Full-System
Multiprocessor Simulations Using FPGAs 15:1--15:??
Michael Pellauer and
Muralidaran Vijayaraghavan and
Michael Adler and
Arvind and
Joel Emer A-Port Networks: Preserving the Timed
Behavior of Synchronous Systems for
Modeling on FPGAs . . . . . . . . . . . 16:1--16:??
Jason Cong and
Yi Zou FPGA-Based Hardware Acceleration of
Lithographic Aerial Image Simulation . . 17:1--17:??
Taneem Ahmed and
Paul D. Kundarewich and
Jason H. Anderson Packing Techniques for Virtex-5 FPGAs 18:1--18:??
Hadi Parandeh-Afshar and
Philip Brisk and
Paolo Ienne An FPGA Logic Cell and Carry Chain
Configurable as a 6:2 or 7:2 Compressor 19:1--19:??
Katherine Compton and
Roger Woods and
Christos Bouganis and
Pedro Diniz Introduction to the Special Issue ARC'08 20:1--20:??
Qiwei Jin and
David B. Thomas and
Wayne Luk and
Benjamin Cope Exploring Reconfigurable Architectures
for Tree-Based Option Pricing Models . . 21:1--21:??
Maria E. Angelopoulou and
Christos-Savvas Bouganis and
Peter Y. K. Cheung and
George A. Constantinides Robust Real-Time Super-Resolution on
FPGA and an Application to Video
Enhancement . . . . . . . . . . . . . . 22:1--22:??
Chia-Tien Dan Lo and
Yi-Gang Tai Space Optimization on Counters for
FPGA-Based Perl Compatible Regular
Expressions . . . . . . . . . . . . . . 23:1--23:??
Nikolaos Vassiliadis and
George Theodoridis and
Spiridon Nikolaidis An Application Development Framework for
ARISE Reconfigurable Processors . . . . 24:1--24:??
Ozana Silvia Dragomir and
Todor Stefanov and
Koen Bertels Optimal Loop Unrolling and Shifting for
Reconfigurable Architectures . . . . . . 25:1--25:??
Keith D. Underwood and
K. Scott Hemmert and
Craig D. Ulmer From Silicon to Science: The Long Road
to Production Reconfigurable
Supercomputing . . . . . . . . . . . . . 26:1--26:??
Antonio Roldao and
George A. Constantinides A High Throughput FPGA-Based Floating
Point Conjugate Gradient Implementation
for Dense Matrices . . . . . . . . . . . 1:1--1:??
David Dubois and
Andrew Dubois and
Thomas Boorman and
Carolyn Connor and
Steve Poole Sparse Matrix-Vector Multiplication on a
Reconfigurable Supercomputer with
Application . . . . . . . . . . . . . . 2:1--2:??
Saar Drimer and
Tim Güneysu and
Christof Paar DSPs, BRAMs, and a Pinch of Logic:
Extended Recipes for AES on FPGAs . . . 3:1--3:??
Shannon Koh and
Oliver Diessel Configuration Merging in Point-to-Point
Networks for Module-Based FPGA
Reconfiguration . . . . . . . . . . . . 4:1--4:??
John Curreri and
Seth Koehler and
Alan D. George and
Brian Holland and
Rafael Garcia Performance Analysis Framework for
High-Level Language Applications in
Reconfigurable Computing . . . . . . . . 5:1--5:??
John Bodily and
Brent Nelson and
Zhaoyi Wei and
Dah-Jye Lee and
Jeff Chase A Comparison Study on Implementing
Optical Flow and Digital Communications
on FPGAs and GPUs . . . . . . . . . . . 6:1--6:??
Konstantinos Papadopoulos and
Ioannis Papaefstathiou Titan-R: a Multigigabit Reconfigurable
Combined Compression/Decompression Unit 7:1--7:??
Beno\^\it Badrignans and
David Champagne and
Reouven Elbaz and
Catherine Gebotys and
Lionel Torres SARFUM: Security Architecture for Remote
FPGA Update and Monitoring . . . . . . . 8:1--8:??
Sang-Kyung Yoo and
Deniz Karakoyunlu and
Berk Birand and
Berk Sunar Improving the Robustness of Ring
Oscillator TRNGs . . . . . . . . . . . . 9:1--9:??
Ted Huffmire and
Timothy Levin and
Thuy Nguyen and
Cynthia Irvine and
Brett Brotherton and
Gang Wang and
Timothy Sherwood and
Ryan Kastner Security Primitives for Reconfigurable
Hardware-Based Systems . . . . . . . . . 10:1--10:??
K. Scott Hemmert and
Keith D. Underwood Fast, Efficient Floating-Point Adders
and Multipliers for FPGAs . . . . . . . 11:1--11:??
Ahmad Sghaier and
Shawki Areibi and
Robert Dony Implementation Approaches Trade-Offs for
WiMax OFDM Functions on Reconfigurable
Platforms . . . . . . . . . . . . . . . 12:1--12:??
Alastair M. Smith and
George A. Constantinides and
Peter Y. K. Cheung An Automated Flow for Arithmetic
Component Generation in
Field-Programmable Gate Arrays . . . . . 13:1--13:??
James Moscola and
Ron K. Cytron and
Young H. Cho Hardware-Accelerated RNA
Secondary-Structure Alignment . . . . . 14:1--14:??
Yosi Ben-Asher and
Danny Meisler and
Nadav Rotem Reducing Memory Constraints in Modulo
Scheduling Synthesis for FPGAs . . . . . 15:1--15:??
Xiaojun Wang and
Miriam Leeser VFloat: a Variable Precision Fixed- and
Floating-Point Library for
Reconfigurable Hardware . . . . . . . . 16:1--16:??
Madhura Purnaprajna and
Mario Porrmann and
Ulrich Rueckert and
Michael Hussmann and
Michael Thies and
Uwe Kastens Runtime Reconfiguration of
Multiprocessors Based on Compile-Time
Analysis . . . . . . . . . . . . . . . . 17:1--17:??
Sudarshan Banerjee and
Elaheh Bozorgzadeh and
Juanjo Noguera and
Nikil Dutt Bandwidth Management in Application
Mapping for Dynamically Reconfigurable
Architectures . . . . . . . . . . . . . 18:1--18:??
Jason Williams and
Chris Massie and
Alan D. George and
Justin Richardson and
Kunal Gosrani and
Herman Lam Characterization of Fixed and
Reconfigurable Multi-Core Devices for
Application Acceleration . . . . . . . . 19:1--19:??
Miaoqing Huang and
Vikram K. Narayana and
Harald Simmler and
Olivier Serres and
Tarek El-Ghazawi Reconfiguration and Communication-Aware
Task Scheduling for High-Performance
Reconfigurable Computing . . . . . . . . 20:1--20:??
Kentaro Sano and
Wang Luzhou and
Yoshiaki Hatsuda and
Takanori Iizuka and
Satoru Yamamoto FPGA-Array with Bandwidth-Reduction
Mechanism for Scalable and
Power-Efficient Numerical Simulations
Based on Finite Difference Methods . . . 21:1--21:??
Manuel Saldaña and
Arun Patel and
Christopher Madill and
Daniel Nunes and
Danyao Wang and
Paul Chow and
Ralph Wittig and
Henry Styles and
Andrew Putnam MPI as a Programming Model for
High-Performance Reconfigurable
Computers . . . . . . . . . . . . . . . 22:1--22:??
Matt Chiu and
Martin C. Herbordt Molecular Dynamics Simulations on
High-Performance Reconfigurable
Computing Systems . . . . . . . . . . . 23:1--23:??
Alessio Montone and
Marco D. Santambrogio and
Donatella Sciuto and
Seda Ogrenci Memik Placement and Floorplanning in
Dynamically Reconfigurable FPGAs . . . . 24:1--24:??
Casey Reardon and
Eric Grobelny and
Alan D. George and
Gongyu Wang A Simulation Framework for Rapid
Analysis of Reconfigurable Computing
Systems . . . . . . . . . . . . . . . . 25:1--25:??
Xiang Tian and
Khaled Benkrid High-Performance Quasi-Monte Carlo
Financial Simulation: FPGA vs. GPP vs.
GPU . . . . . . . . . . . . . . . . . . 26:1--26:??
Roger Woods and
Jürgen Becker and
Peter Athanas and
Fearghal Morgan Guest Editorial ARC 2009 . . . . . . . . 1:1--1:??
Chalermpol Saiprasert and
Christos-S. Bouganis and
George A. Constantinides An Optimized Hardware Architecture of a
Multivariate Gaussian Random Number
Generator . . . . . . . . . . . . . . . 2:1--2:??
Asma Kahoul and
Alastair M. Smith and
George A. Constantinides and
Peter Y. K. Cheung Efficient Heterogeneous Architecture
Floorplan Optimization using Analytical
Methods . . . . . . . . . . . . . . . . 3:1--3:??
K. Kepa and
F. Morgan and
K. Ko\'sciuszkiewicz and
L. Braun and
M. Hübner and
J. Becker Design Assurance Strategy and Toolset
for Partially Reconfigurable FPGA
Systems . . . . . . . . . . . . . . . . 4:1--4:??
Kazuki Inoue and
Qian Zhao and
Yasuhiro Okamoto and
Hiroki Yosho and
Motoki Amagasaki and
Masahiro Iida and
Toshinori Sueyoshi A Variable-Grain Logic Cell and Routing
Architecture for a Reconfigurable IP
Core . . . . . . . . . . . . . . . . . . 5:1--5:??
Xu Guo and
Patrick Schaumont Optimized System-on-Chip Integration of
a Programmable ECC Coprocessor . . . . . 6:1--6:??
Luca Sterpone A New Timing Driven Placement Algorithm
for Dependable Circuits on SRAM-based
FPGAs . . . . . . . . . . . . . . . . . 7:1--7:??
M. Lanuzza and
P. Zicari and
F. Frustaci and
S. Perri and
P. Corsonello Exploiting Self-Reconfiguration
Capability to Improve SRAM-based FPGA
Robustness in Space and Avionics
Applications . . . . . . . . . . . . . . 8:1--8:??
Pao-Ann Hsiung and
Chun-Hsian Huang and
Jih-Sheng Shen and
Chen-Chi Chiang Scheduling and Placement of
Hardware/Software Real-Time Relocatable
Tasks in Dynamically Partially
Reconfigurable Systems . . . . . . . . . 9:1--9:??
Kenji Kanazawa and
Tsutomu Maruyama An Approach for Solving Large SAT
Problems on FPGA . . . . . . . . . . . . 10:1--10:??
Yingxi Lu and
Maire O'Neill and
John McCanny Evaluation of Random Delay Insertion
against DPA on FPGAs . . . . . . . . . . 11:1--11:??
Etienne Bergeron and
Louis-David Perron and
Marc Feeley and
Jean Pierre David Logarithmic-Time FPGA Bitstream
Analysis: a Step Towards JIT Hardware
Compilation . . . . . . . . . . . . . . 12:1--12:??
Pranav Vaidya and
Jaehwan John Lee A Novel Multicontext Coarse-Grained
Reconfigurable Architecture (CGRA) For
Accelerating Column-Oriented Databases 13:1--13:??
Shane O'Neill and
Roger Francis Woods and
Alan James Marshall and
Qi Zhang A Scalable and Programmable Modular
Traffic Manager Architecture . . . . . . 14:1--14:??
Mao Nakajima and
Minoru Watanabe Fast Optical Reconfiguration of a
Nine-Context DORGA Using a Speed
Adjustment Control . . . . . . . . . . . 15:1--15:??
Tzu-Chiang Tai and
Yen-Tai Lai A Performance-Oriented Algorithm with
Consideration on Communication Cost for
Dynamically Reconfigurable FPGA
Partitioning . . . . . . . . . . . . . . 16:1--16:??
Melina Demertzi and
Pedro C. Diniz and
Mary W. Hall and
Anna C. Gilbert and
Yi Wang Domain-Specific Optimization of Signal
Recognition Targeting FPGAs . . . . . . 17:1--17:??
Carlo Galuzzi and
Koen Bertels The Instruction-Set Extension Problem: a
Survey . . . . . . . . . . . . . . . . . 18:1--18:28
Kyle Rupnow and
Keith D. Underwood and
Katherine Compton Scientific Application Demands on a
Reconfigurable Functional Unit Interface 19:1--19:??
Alexander Kaganov and
Asif Lakhany and
Paul Chow FPGA Acceleration of MultiFactor CDO
Pricing . . . . . . . . . . . . . . . . 20:1--20:??
Martin Labrecque and
Mark C. Jeffrey and
J. Gregory Steffan Application-specific signatures for
transactional memory in soft processors 21:1--21:??
David Boland and
George A. Constantinides Optimizing memory bandwidth use and
performance for matrix-vector
multiplication in iterative methods . . 22:1--22:??
Johann Glaser and
Markus Damm and
Jan Haase and
Christoph Grimm TR-FSM: Transition-Based reconfigurable
finite state machine . . . . . . . . . . 23:1--23:??
Husain Parvez and
Zied Marrakchi and
Alp Kilic and
Habib Mehrez Application-Specific FPGA using
heterogeneous logic blocks . . . . . . . 24:1--24:??
Jing Yan and
Ning-Yi Xu and
Xiong-Fei Cai and
Rui Gao and
Yu Wang and
Rong Luo and
Feng-Hsiung Hsu An FPGA-based accelerator for LambdaRank
in Web search engines . . . . . . . . . 25:1--25:??
Vikas Aggarwal and
Alan D. George and
Changil Yoon and
Kishore Yalamanchili and
Herman Lam SHMEM+: a multilevel-PGAS programming
model for reconfigurable supercomputing 26:1--26:??
Brian Holland and
Alan D. George and
Herman Lam and
Melissa C. Smith An analytical model for multilevel
performance prediction of Multi-FPGA
systems . . . . . . . . . . . . . . . . 27:1--27:??
Lesley Shannon and
Paul Chow Leveraging reconfigurability in the
hardware/software codesign process . . . 28:1--28:??
Federico Nava and
Donatella Sciuto and
Marco Domenico Santambrogio and
Stefan Herbrechtsmeier and
Mario Porrmann and
Ulf Witkowski and
Ulrich Rueckert Applying dynamic reconfiguration in the
mobile robotics domain: a case study on
computer vision algorithms . . . . . . . 29:1--29:??
Seth Koehler and
Greg Stitt and
Alan D. George Platform-aware bottleneck detection for
reconfigurable computing applications 30:1--30:??
Peter Y. K. Cheung Introduction to special section FPGA
2009 . . . . . . . . . . . . . . . . . . 31:1--31:??
Jason Luu and
Ian Kuon and
Peter Jamieson and
Ted Campbell and
Andy Ye and
Wei Mark Fang and
Kenneth Kent and
Jonathan Rose VPR 5.0: FPGA CAD and architecture
exploration tools with single-driver
routing, heterogeneity and process
scaling . . . . . . . . . . . . . . . . 32:1--32:??
Raphael Rubin and
André Dehon Choose-your-own-adventure routing:
Lightweight load-time defect avoidance 33:1--33:??
Alan Mishchenko and
Robert Brayton and
Jie-Hong R. Jiang and
Stephen Jang Scalable don't-care-based logic
optimization and resynthesis . . . . . . 34:1--34:??
Andrew Kennings and
Kristofer Vorwerk and
Arun Kundu and
Val Pevzner and
Andy Fox FPGA technology mapping with encoded
libraries and staged priority cuts . . . 35:1--35:??
Kyprianos Papadimitriou and
Apostolos Dollas and
Scott Hauck Performance of partial reconfiguration
in FPGA systems: a survey and a cost
model . . . . . . . . . . . . . . . . . 36:1--36:??
Xiaoheng Chen and
Venkatesh Akella Exploiting data-level parallelism for
energy-efficient implementation of LDPC
decoders and DCT on an FPGA . . . . . . 37:1--37:??
Lakshmi Easwaran and
Ali Akoglu Net-length-based routability-driven
power-aware clustering . . . . . . . . . 38:1--38:??
Hadi Parandeh-Afshar and
Arkosnato Neogy and
Philip Brisk and
Paolo Ienne Compressor tree synthesis on commercial
high-performance FPGAs . . . . . . . . . 39:1--39:??
Hiroaki Inoue and
Junya Yamada and
Hideyuki Yoneda and
Katsumi Togawa and
Masato Motomura and
Koichiro Furuta Test compression for dynamically
reconfigurable processors . . . . . . . 40:1--40:??
Kenneth M. Zick and
John P. Hayes Low-cost sensing with ring oscillator
arrays for healthier reconfigurable
systems . . . . . . . . . . . . . . . . 1:1--1:??
Harris E. Michail and
George S. Athanasiou and
Vasilis Kelefouras and
George Theodoridis and
Costas E. Goutis On the exploitation of a high-throughput
SHA-256 FPGA design for HMAC . . . . . . 2:1--2:??
Joaquín Olivares Reconfigurable architecture for VBSME
with variable pixel precision . . . . . 3:1--3:??
Kostas Siozios and
Vasilis F. Pavlidis and
Dimitrios Soudris A novel framework for exploring $3$-D
FPGAs with heterogeneous interconnect
fabric . . . . . . . . . . . . . . . . . 4:1--4:??
Shigeyuki Takano Design and analysis of adaptive
processor . . . . . . . . . . . . . . . 5:1--5:??
Wei Zhang and
Vaughn Betz and
Jonathan Rose Portable and scalable FPGA-based
acceleration of a direct linear system
solver . . . . . . . . . . . . . . . . . 6:1--6:??
Vikas Aggarwal and
Greg Stitt and
Alan George and
Changil Yoon SCF: a Framework for Task-Level
Coordination in Reconfigurable,
Heterogeneous Systems . . . . . . . . . 7:1--7:??
Sándor P. Fekete and
Tom Kamphans and
Nils Schweer and
Christopher Tessars and
Jan C. van der Veen and
Josef Angermeier and
Dirk Koch and
Jürgen Teich Dynamic Defragmentation of
Reconfigurable Devices . . . . . . . . . 8:1--8:??
Lerong Cheng and
Wenyao Xu and
Fang Gong and
Yan Lin and
Ho-Yan Wong and
Lei He Statistical Timing and Power
Optimization of Architecture and Device
for FPGAs . . . . . . . . . . . . . . . 9:1--9:??
Kevin Martin and
Christophe Wolinski and
Krzysztof Kuchcinski and
Antoine Floch and
François Charot Constraint Programming Approach to
Reconfigurable Processor Extension
Generation and Application Compilation 10:1--10:??
Michael Hübner Introduction to the Special Issue on
ReCoSoC 2011 . . . . . . . . . . . . . . 11:1--11:??
John Shield and
Jean-Philippe Diguet and
Guy Gogniat Asymmetric Cache Coherency: Policy
Modifications to Improve Multicore
Performance . . . . . . . . . . . . . . 12:1--12:??
Benjamin Thielmann and
Jens Huthmann and
Andreas Koch Memory Latency Hiding by Load Value
Speculation for Reconfigurable Computers 13:1--13:??
Laurent Gantel and
Amel Khiar and
Benoit Miramond and
Mohamed El Amine Benkhelifa and
Lounis Kessal and
Fabrice Lemonnier and
Jimmy Le Rhun Enhancing Reconfigurable Platforms
Programmability for Synchronous
Data-Flow Applications . . . . . . . . . 14:1--14:??
Angelo Kuti Lusala and
Jean-Didier Legat A SDM--TDM-Based Circuit-Switched Router
for On-Chip Networks . . . . . . . . . . 15:1--15:??
Lubos Gaspar and
Viktor Fischer and
Lilian Bossuet and
Robert Fouquet Secure Extension of FPGA General Purpose
Processors for Symmetric Key
Cryptography with Partial
Reconfiguration Capabilities . . . . . . 16:1--16:??
Luciano Ost and
Sameer Varyani and
Leandro Soares Indrusiak and
Marcelo Mandelli and
Gabriel Marchesan Almeida and
Eduardo Wachter and
Fernando Moraes and
Gilles Sassatelli Enabling Adaptive Techniques in
Heterogeneous MPSoCs Based on
Virtualization . . . . . . . . . . . . . 17:1--17:??
Fearghal Morgan and
Seamus Cawley and
David Newell Remote FPGA Lab for Enhancing Learning
of Digital Systems . . . . . . . . . . . 18:1--18:??
Armin Krieg and
Johannes Grinschgl and
Christian Steger and
Reinhold Weiss and
Holger Bock and
Josef Haid POWER-MODES: POWer-EmulatoR- and
MOdel-Based DEpendability and Security
Evaluations . . . . . . . . . . . . . . 19:1--19:??
Atukem Nabina and
Jose Luis Nunez-Yanez Adaptive Voltage Scaling in a
Dynamically Reconfigurable FPGA-Based
Platform . . . . . . . . . . . . . . . . 20:1--20:??
Adam Jacobs and
Grzegorz Cieslewski and
Alan D. George and
Ann Gordon-Ross and
Herman Lam Reconfigurable Fault Tolerance: a
Comprehensive Framework for Reliable and
Adaptive FPGA-Based Space Computing . . 21:1--21:??
Fabio Cancare and
Davide B. Bartolini and
Matteo Carminati and
Donatella Sciuto and
Marco D. Santambrogio On the Evolution of Hardware Circuits
via Reconfigurable Architectures . . . . 22:1--22:??
Tarek Ould-Bachir and
Jean Pierre David Self-Alignment Schemes for the
Implementation of Addition-Related
Floating-Point Operators . . . . . . . . 1:1--1:??
Yan Zhang and
Fan Zhang and
Zheming Jin and
Jason D. Bakos An FPGA-Based Accelerator for Frequent
Itemset Mining . . . . . . . . . . . . . 2:1--2:??
Roel Meeuws and
S. Arash Ostadzadeh and
Carlo Galuzzi and
Vlad Mihai Sima and
Razvan Nane and
Koen Bertels Quipu: a Statistical Model for
Predicting Hardware Resources . . . . . 3:1--3:??
Florent de Dinechin and
Pedro Echeverría and
Marisa López-Vallejo and
Bogdan Pasca Floating-Point Exponentiation Units for
Reconfigurable Computing . . . . . . . . 4:1--4:??
Christopher E. Neely and
Gordon Brebner and
Weijia Shang ReShape: Towards a High-Level Approach
to Design and Operation of Modular
Reconfigurable Systems . . . . . . . . . 5:1--5:??
Diana Goehringer and
René Cumplido Introduction to the special section on
19th Reconfigurable Architectures
Workshop (RAW 2012) . . . . . . . . . . 6:1--6:??
Harry Sidiropoulos and
Kostas Siozios and
Peter Figuli and
Dimitrios Soudris and
Michael Hübner and
Jürgen Becker JITPR: a framework for supporting fast
application's implementation onto FPGAs 7:1--7:??
Jan Heisswolf and
Aurang Zaib and
Andreas Weichslgartner and
Ralf König and
Thomas Wild and
Jürgen Teich and
Andreas Herkersdorf and
Jürgen Becker Virtual networks --- distributed
communication resource management . . . 8:1--8:??
Thilan Ganegedara and
Viktor Prasanna A comprehensive performance analysis of
virtual routers on FPGA . . . . . . . . 9:1--9:??
Joydip Das and
Steven J. E. Wilton Towards development of an analytical
model relating FPGA architecture
parameters to routability . . . . . . . 10:1--10:??
Chun-Hsian Huang and
Pao-Ann Hsiung Virtualizable hardware/software design
infrastructure for dynamically partially
reconfigurable systems . . . . . . . . . 11:1--11:??
Hanyu Liu and
Senthilkumar T. Rajavel and
Ali Akoglu Integration of Net-Length Factor with
Timing- and Routability-Driven
Clustering Algorithms . . . . . . . . . 12:1--12:??
Gayatri Mehta and
Carson Crawford and
Xiaozhong Luo and
Natalie Parde and
Krunalkumar Patel and
Brandon Rodgers and
Anil Kumar Sistla and
Anil Yadav and
Marc Reisner UNTANGLED: a Game Environment for
Discovery of Creative Mapping Strategies 13:1--13:??
Javier Hormigo and
Gabriel Caffarena and
Juan P. Oliver and
Eduardo Boemo Self-Reconfigurable Constant Multiplier
for FPGA . . . . . . . . . . . . . . . . 14:1--14:??
Farnaz Gharibian and
Lesley Shannon and
Peter Jamieson and
Kevin Chung Analyzing System-Level Information's
Correlation to FPGA Placement . . . . . 15:1--15:??
Franjo Plavec and
Zvonko Vranesic and
Stephen Brown Exploiting Task- and Data-Level
Parallelism in Streaming Applications
Implemented in FPGAs . . . . . . . . . . 16:1--16:??
T. Ananthan and
M. V. Vaidyan A Reconfigurable Parallel Hardware
Implementation of the Self-Tuning
Regulator . . . . . . . . . . . . . . . 17:1--17:??
Yoon Kah Leow and
Ali Akoglu and
Susan Lysecky An Analytical Model for Evaluating
Static Power of Homogeneous FPGA
Architectures . . . . . . . . . . . . . 18:1--18:??
Yosi Ben-Asher and
Ron Meldiner and
Nadav Rotem Optimizing Wait States in the Synthesis
of Memory References with Unpredictable
Latencies . . . . . . . . . . . . . . . 19:1--19:??
George Kornaros and
Dionisios Pnevmatikatos Dynamic Power and Thermal Management of
NoC-Based Heterogeneous MPSoCs . . . . . 1:1--1:??
Yousef Iskander and
Cameron Patterson and
Stephen Craven High-Level Abstractions and Modular
Debugging for FPGA Design Validation . . 2:1--2:??
Minxi Jin and
Tsutomu Maruyama Fast and Accurate Stereo Vision System
on FPGA . . . . . . . . . . . . . . . . 3:1--3:??
Onur Ulusel and
Kumud Nepal and
R. Iris Bahar and
Sherief Reda Fast Design Exploration for Performance,
Power and Accuracy Tradeoffs in
FPGA-Based Accelerators . . . . . . . . 4:1--4:??
Lok-Won Kim and
Sameh Asaad and
Ralph Linsker A Fully Pipelined FPGA Architecture of a
Factored Restricted Boltzmann Machine
Artificial Neural Network . . . . . . . 5:1--5:??
Jason Luu and
Jeffrey Goeders and
Michael Wainberg and
Andrew Somerville and
Thien Yu and
Konstantin Nasartschuk and
Miad Nasr and
Sen Wang and
Tim Liu and
Nooruddin Ahmed and
Kenneth B. Kent and
Jason Anderson and
Jonathan Rose and
Vaughn Betz VTR 7.0: Next Generation Architecture
and CAD System for FPGAs . . . . . . . . 6:1--6:??
Soumya J. and
Ashish Sharma and
Santanu Chattopadhyay Multi-Application Network-on-Chip Design
using Global Mapping and Local
Reconfiguration . . . . . . . . . . . . 7:1--7:??
Yuanwu Lei and
Lei Guo and
Yong Dou and
Sheng Ma and
Jinbo Xu FPGA Implementation of a Special-Purpose
VLIW Structure for Double-Precision
Elementary Function . . . . . . . . . . 8:1--8:??
Juan Antonio Clemente and
Ivan Beretta and
Vincenzo Rana and
David Atienza and
Donatella Sciuto A Mapping-Scheduling Algorithm for
Hardware Acceleration on Reconfigurable
Platforms . . . . . . . . . . . . . . . 9:1--9:??
Anh-Tuan Hoang and
Takeshi Fujino Intra-Masking Dual-Rail Memory on LUT
Implementation for SCA-Resistant AES on
FPGA . . . . . . . . . . . . . . . . . . 10:1--10:??
Tobias Becker Introduction to the TRETS Special
Section on the Workshop on
Self-Awareness in Reconfigurable
Computing Systems (SRCS'12) . . . . . . 11:1--11:??
Jacopo Panerati and
Martina Maggio and
Matteo Carminati and
Filippo Sironi and
Marco Triverio and
Marco D. Santambrogio Coordination of Independent Loops in
Self-Adaptive Systems . . . . . . . . . 12:1--12:??
Andreas Agne and
Markus Happe and
Achim Lösch and
Christian Plessl and
Marco Platzner Self-Awareness as a Model for Designing
and Operating Heterogeneous Multicores 13:1--13:??
Christian Beckhoff and
Dirk Koch and
Jim Torresen Design Tools for Implementing Self-Aware
and Fault-Tolerant Systems on FPGAs . . 14:1--14:??
Xinyu Niu and
Qiwei Jin and
Wayne Luk and
Stephen Weston A Self-Aware Tuning and Self-Aware
Evaluation Method for Finite-Difference
Applications in Reconfigurable Systems 15:1--15:??
Charles Eric Laforest and
Zimo Li and
Tristan O'rourke and
Ming G. Liu and
J. Gregory Steffan Composing Multi-Ported Memories on FPGAs 16:1--16:??
Yuanxi Peng and
Manuel Saldaña and
Christopher A. Madill and
Xiaofeng Zou and
Paul Chow Benefits of Adding Hardware Support for
Broadcast and Reduce Operations in MPSoC
Applications . . . . . . . . . . . . . . 17:1--17:??
Jason Anderson and
Kiyoung Choi Introduction to the Special Issue on the
11th International Conference on
Field-Programmable Technology (FPT'12) 18:1--18:??
Hui Yan Cheah and
Fredrik Brosser and
Suhaib A. Fahmy and
Douglas L. Maskell The iDEA DSP Block-Based Soft Processor
for FPGAs . . . . . . . . . . . . . . . 19:1--19:??
Mohamed S. Abdelfattah and
Vaughn Betz Networks-on-Chip for FPGAs: Hard, Soft
or Mixed? . . . . . . . . . . . . . . . 20:1--20:??
Liang Chen and
Tulika Mitra Graph Minor Approach for Application
Mapping on CGRAs . . . . . . . . . . . . 21:1--21:??
Changmoo Kim and
Mookyoung Chung and
Yeongon Cho and
Mario Konijnenburg and
Soojung Ryu and
Jeongwook Kim ULP-SRP: Ultra Low-Power Samsung
Reconfigurable Processor for Biomedical
Applications . . . . . . . . . . . . . . 22:1--22:??
Nikolaos Voros and
Guy Gogniat Introduction to the Special Issue on the
7th International Workshop on
Reconfigurable Communication-centric
Systems-on-Chip (ReCoSoC'12) . . . . . . 23:1--23:??
Christian Brugger and
Dominic Hillenbrand and
Matthias Balzer RIVER: Reconfigurable Flow and Fabric
for Real-Time Signal Processing on FPGAs 24:1--24:??
Fábio Itturiet and
Gabriel Nazar and
Ronaldo Ferreira and
Álvaro Moreira and
Luigi Carro Adaptive Parallelism Exploitation under
Physical and Real-Time Constraints for
Resilient Systems . . . . . . . . . . . 25:1--25:??
Siew-Kei Lam and
Christopher T. Clarke and
Thambipillai Srikanthan Exploiting FPGA-Aware Merging of Custom
Instructions for Runtime Reconfiguration 26:1--26:??
Sébastien Guillet and
Florent de Lamotte and
Nicolas le Griguer and
Éric Rutten and
Guy Gogniat and
Jean-Philippe Diguet Extending UML/MARTE to Support Discrete
Controller Synthesis, Application to
Reconfigurable Systems-on-Chip Modeling 27:1--27:??
Jon T. Butler and
Tsutomu Sasao High-Speed Hardware Partition Generation 1:1--1:??
Nuno Paulino and
João Canas Ferreira and
João M. P. Cardoso A Reconfigurable Architecture for Binary
Acceleration of Loops with Memory
Accesses . . . . . . . . . . . . . . . . 2:1--2:??
Udit Dhawan and
André Dehon Area-Efficient Near-Associative Memories
on FPGAs . . . . . . . . . . . . . . . . 3:1--3:??
Daniel Llamocca and
Marios Pattichis Dynamic Energy, Performance, and
Accuracy Optimization and Management
Using Automatically Generated
Constraints for Separable $2$D FIR
Filtering for Digital Video Processing 4:1--4:??
Benjamin Gojman and
Sirisha Nalmela and
Nikil Mehta and
Nicholas Howarth and
André Dehon GROK-LAB: Generating Real On-chip
Knowledge for Intra-cluster Delays Using
Timing Extraction . . . . . . . . . . . 5:1--5:??
Atabak Mahram and
Martin C. Herbordt NCBI BLASTP on High-Performance
Reconfigurable Computing Systems . . . . 6:1--6:??
Pawel Swierczynski and
Amir Moradi and
David Oswald and
Christof Paar Physical Security Evaluation of the
Bitstream Encryption Mechanism of Altera
Stratix II and Stratix III FPGAs . . . . 7:1--7:??
Jo Vliegen and
Nele Mentens and
Ingrid Verbauwhede Secure, Remote, Dynamic Reconfiguration
of FPGAs . . . . . . . . . . . . . . . . 8:1--8:??
Thomas C. P. Chau and
Xinyu Niu and
Alison Eele and
Jan Maciejowski and
Peter Y. K. Cheung and
Wayne Luk Mapping Adaptive Particle Filters to
Heterogeneous Reconfigurable Systems . . 9:1--9:??
Bailey Miller and
Frank Vahid and
Tony Givargis and
Philip Brisk Graph-Based Approaches to Placement of
Processing Element Networks on FPGAs for
Physical Model Simulation . . . . . . . 10:1--10:??
Stefano Di Carlo and
Giulio Gambardella and
Paolo Prinetto and
Daniele Rolfo and
Pascal Trotta SATTA: a Self-Adaptive Temperature-Based
TDF Awareness Methodology for
Dynamically Reconfigurable FPGAs . . . . 1:1--1:??
Patrick Cooke and
Jeremy Fowers and
Greg Brown and
Greg Stitt A Tradeoff Analysis of FPGAs, GPUs, and
Multicores for Sliding-Window
Applications . . . . . . . . . . . . . . 2:1--2:??
Heather Quinn and
Diane Roussel-Dupre and
Mike Caffrey and
Paul Graham and
Michael Wirthlin and
Keith Morgan and
Anthony Salazar and
Tony Nelson and
Will Howes and
Eric Johnson and
Jon Johnson and
Brian Pratt and
Nathan Rollins and
Jim Krone The Cibola Flight Experiment . . . . . . 3:1--3:??
Tom Davidson and
Elias Vansteenkiste and
Karel Heyse and
Karel Bruneel and
Dirk Stroobandt Identification of Dynamic Circuit
Specialization Opportunities in RTL Code 4:1--4:??
Xabier Iturbe and
Khaled Benkrid and
Chuan Hong and
Ali Ebrahim and
Raul Torrego and
Tughrul Arslan Microkernel Architecture and Hardware
Abstraction Layer of a Reliable
Reconfigurable Real-Time Operating
System (R3TOS) . . . . . . . . . . . . . 5:1--5:??
Kan Shi and
David Boland and
George A. Constantinides Imprecise Datapath Design: an
Overclocking Approach . . . . . . . . . 6:1--6:??
Louis Woods and
Gustavo Alonso and
Jens Teubner Parallelizing Data Processing on FPGAs
with Shifter Lists . . . . . . . . . . . 7:1--7:??
João M. P. Cardoso and
Pedro C. Diniz and
Katherine (Compton) Morrow Guest Editorial: FPL 2013 . . . . . . . 8:1--8:??
Ricardo Ferreira and
Luciana Rocha and
André G. Santos and
José A. M. Nacif and
Stephan Wong and
Luigi Carro A Runtime FPGA Placement and Routing
Using Low-Complexity Graph Traversal . . 9:1--9:??
Kevin E. Murray and
Scott Whitty and
Suya Liu and
Jason Luu and
Vaughn Betz Timing-Driven Titan: Enabling Large
Benchmarks and Exploring the Gap between
Academic and Commercial CAD . . . . . . 10:1--10:??
Lin Gan and
Haohuan Fu and
Wayne Luk and
Chao Yang and
Wei Xue and
Xiaomeng Huang and
Youhui Zhang and
Guangwen Yang Solving the Global Atmospheric Equations
through Heterogeneous Reconfigurable
Platforms . . . . . . . . . . . . . . . 11:1--11:??
Anup Das and
Shyamsundar Venkataraman and
Akash Kumar Autonomous Soft-Error Tolerance of FPGA
Configuration Bits . . . . . . . . . . . 12:1--12:??
Zsolt István and
Gustavo Alonso and
Michaela Blott and
Kees Vissers A Hash Table for Line-Rate Data
Processing . . . . . . . . . . . . . . . 13:1--13:??
Qijing Huang and
Ruolong Lian and
Andrew Canis and
Jongsok Choi and
Ryan Xi and
Nazanin Calagar and
Stephen Brown and
Jason Anderson The Effect of Compiler Optimizations on
High-Level Synthesis-Generated Hardware 14:1--14:??
Xinyu Niu and
Thomas C. P. Chau and
Qiwei Jin and
Wayne Luk and
Qiang Liu and
Oliver Pell Automating Elimination of Idle Functions
by Runtime Reconfiguration . . . . . . . 15:1--15:??
Shivam Bhasin and
Jean-Luc Danger and
Sylvain Guilley and
Wei He Exploiting FPGA Block Memories for
Protected Cryptographic Implementations 16:1--16:??
Juan Fernando Eusse and
Christopher Williams and
Rainer Leupers CoEx: a Novel Profiling-Based
Algorithm/Architecture Co-Exploration
for ASIP Design . . . . . . . . . . . . 17:1--17:??
Anup Das and
Amit Kumar Singh and
Akash Kumar Execution Trace-Driven
Energy-Reliability Optimization for
Multimedia MPSoCs . . . . . . . . . . . 18:1--18:??
Yu Ren and
Leibo Liu and
Shouyi Yin and
Jie Han and
Shaojun Wei Efficient Fault-Tolerant Topology
Reconfiguration Using a Maximum Flow
Algorithm . . . . . . . . . . . . . . . 19:1--19:??
Roland Dobai and
Lukas Sekanina Low-Level Flexible Architecture with
Hybrid Reconfiguration for Evolvable
Hardware . . . . . . . . . . . . . . . . 20:1--20:??
Robert Kirchgessner and
Alan D. George and
Greg Stitt Low-Overhead FPGA Middleware for
Application Portability and Productivity 21:1--21:??
Matthew Jacobsen and
Dustin Richmond and
Matthew Hogains and
Ryan Kastner RIFFA 2.1: a Reusable Integration
Framework for FPGA Accelerators . . . . 22:1--22:??
David B. Thomas The Table-Hadamard GRNG: an
Area-Efficient FPGA Gaussian Random
Number Generator . . . . . . . . . . . . 23:1--23:??
Zheming Jin and
Jason D. Bakos Memory Interface Design for $3$D Stencil
Kernels on a Massively Parallel Memory
System . . . . . . . . . . . . . . . . . 24:1--24:??
Guangming Tan and
Chunming Zhang and
Wendi Wang and
Peiheng Zhang SuperDragon: a Heterogeneous Parallel
System for Accelerating $3$D
Reconstruction of Cryo-Electron
Microscopy Images . . . . . . . . . . . 25:1--25:??
Alexander Biedermann and
Sorin A. Huss and
Adeel Israr Safe Dynamic Reshaping of Reconfigurable
MPSoC Embedded Systems for Self-Healing
and Self-Adaption Purposes . . . . . . . 26:1--26:??
Joonseok Park and
Pedro C. Diniz Program-Invariant Checking for
Soft-Error Detection using
Reconfigurable Hardware . . . . . . . . 1:1--1:??
Neil Scicluna and
Christos-Savvas Bouganis ARC 2014: a Multidimensional FPGA-Based
Parallel DBSCAN Architecture . . . . . . 2:1--2:??
Pascal Sasdrich and
Tim Güneysu Implementing Curve25519 for
Side-Channel--Protected Elliptic Curve
Cryptography . . . . . . . . . . . . . . 3:1--3:??
Jianfeng Zhang and
Paul Chow and
Hengzhu Liu An Enhanced Adaptive Recoding Rotation
CORDIC . . . . . . . . . . . . . . . . . 4:1--4:??
Diana Goehringer and
Marco D. Santambrogio and
João M. P. Cardoso and
Koen Bertels Guest Editorial: ARC 2014 . . . . . . . 5:1--5:??
Karel Heyse and
Jente Basteleus and
Brahim Al Farisi and
Dirk Stroobandt and
Oliver Kadlcek and
Oliver Pell On the Impact of Replacing Low-Speed
Configuration Buses on FPGAs with the
Chip's Internal Configuration
Infrastructure . . . . . . . . . . . . . 6:1--6:??
Rui Policarpo Duarte and
Christos-Savvas Bouganis ARC 2014 Over-Clocking KLT Designs on
FPGAs under Process, Voltage, and
Temperature Variation . . . . . . . . . 7:1--7:??
Yuhui Bai and
Syed Zahid Ahmed and
Bertrand Granado ARC 2014: Towards a Fast FPGA
Implementation of a Heap-Based Priority
Queue for Image Coding Using a Parallel
Index-Aware Tree . . . . . . . . . . . . 8:1--8:??
Jianfeng Zhang and
Paul Chow and
Hengzhu Liu CORDIC-Based Enhanced Systolic Array
Architecture for $ Q R $ Decomposition 9:1--9:??
Felix J. Winterstein and
Samuel R. Bayliss and
George A. Constantinides Separation Logic for High-Level
Synthesis . . . . . . . . . . . . . . . 10:1--10:??
Jinwei Xu and
Jingfei Jiang and
Yong Dou and
Xiaolong Shen and
Zhiqiang Liu Coarse-Grained Architecture for
Fingerprint Matching . . . . . . . . . . 12:1--12:??
Ali Mustafa Zaidi and
David Greaves Value State Flow Graph: a Dataflow
Compiler IR for Accelerating
Control-Intensive Code in Spatial
Hardware . . . . . . . . . . . . . . . . 14:1--14:??
Michael Raitza and
Markus Vogt and
Christian Hochberger and
Thilo Pionteck RAW 2014: Random Number Generators on
FPGAs . . . . . . . . . . . . . . . . . 15:1--15:??
Osama G. Attia and
Kevin R. Townsend and
Phillip H. Jones and
Joseph Zambreno A Reconfigurable Architecture for the
Detection of Strongly Connected
Components . . . . . . . . . . . . . . . 16:1--16:??
Nachiket Kapre Optimizing Soft Vector Processing in
FPGA-Based Embedded Systems . . . . . . 17:1--17:??
André Dehon and
Derek Chiou Introduction to Special Issue on
Reconfigurable Components with Source
Code . . . . . . . . . . . . . . . . . . 19:1--19:??
Xin Fang and
Miriam Leeser Open-Source Variable-Precision
Floating-Point Library for Major
Commercial FPGAs . . . . . . . . . . . . 1--17
David Wilson and
Greg Stitt The Unified Accumulator Architecture: a
Configurable, Portable, and Extensible
Floating-Point Accumulator . . . . . . . 21:1--21:??
Ameer M. S. Abdelhadi and
Guy G. F. Lemieux Modular Switched Multiported SRAM-Based
Memories . . . . . . . . . . . . . . . . 22:1--22:??
Greg Stitt and
Eric Schwartz and
Patrick Cooke A Parallel Sliding-Window Generator for
High-Performance Digital-Signal
Processing on FPGAs . . . . . . . . . . 23:1--23:??
Zain Ul-Abdin and
Bertil Svensson A Retargetable Compilation Framework for
Heterogeneous Reconfigurable Computing 24:1--24:??
Daniel Ziener and
Florian Bauer and
Andreas Becher and
Christopher Dennl and
Klaus Meyer-Wegener and
Ute Schürfeld and
Jürgen Teich and
Jörg-Stephan Vogt and
Helmut Weber FPGA-Based Dynamically Reconfigurable
SQL Query Processing . . . . . . . . . . 25:1--25:??
Eric Matthews and
Lesley Shannon and
Alexandra Fedorova Shared Memory Multicore MicroBlaze
System with SMP Linux Support . . . . . 26:1--26:??
Ting Yu and
Chris Bradley and
Oliver Sinnen ODoST: Automatic Hardware Acceleration
for Biomedical Model Integration . . . . 27:1--27:??
Deming Chen Introduction . . . . . . . . . . . . . . 28:1--28:??
Evan Wegley and
Yanhua Yi and
Qinhai Zhang Application of Specific Delay Window
Routing for Timing Optimization in FPGA
Designs . . . . . . . . . . . . . . . . 29:1--29:??
Edin Kadric and
David Lakata and
André Dehon Impact of Parallelism and Memory
Architecture on FPGA Communication
Energy . . . . . . . . . . . . . . . . . 30:1--30:??
Alex Rodionov and
David Biancolin and
Jonathan Rose Fine-Grained Interconnect Synthesis . . 31:1--31:??
Nicholas Wulf and
Alan D. George and
Ann Gordon-Ross A Framework for Evaluating and
Optimizing FPGA-Based SoCs for Aerospace
Computing . . . . . . . . . . . . . . . 1:1--1:??
Justin Richardson and
Alan George and
Kevin Cheng and
Herman Lam Analysis of Fixed, Reconfigurable, and
Hybrid Devices with Computational,
Memory, I/O, & Realizable-Utilization
Metrics . . . . . . . . . . . . . . . . 2:1--2:??
Hung-Lin Chao and
Sheng-Ya Tung and
Pao-Ann Hsiung Dynamic Task Mapping with Congestion
Speculation for Reconfigurable
Network-on-Chip . . . . . . . . . . . . 3:1--3:??
Bertrand Le Gal and
Yérom-David Bromberg and
Laurent Réveill\`ere and
Jigar Solanki A Flexible SoC and Its Methodology for
Parser-Based Applications . . . . . . . 4:1--4:??
Yeyong Pang and
Shaojun Wang and
Yu Peng and
Xiyuan Peng and
Nicholas J. Fraser and
Philip H. W. Leong A Microcoded Kernel Recursive Least
Squares Processor Using FPGA Technology 5:1--5:??
Qing Y. Tang and
Mohammed A. S. Khalid Acceleration of $k$-Means Algorithm
Using Altera SDK for OpenCL . . . . . . 6:1--6:??
Henry Wong and
Vaughn Betz and
Jonathan Rose Microarchitecture and Circuits for a 200
MHz Out-of-Order Soft Processor Memory
System . . . . . . . . . . . . . . . . . 7:1--7:??
Bita Darvish Rouhani and
Azalia Mirhoseini and
Ebrahim M. Songhori and
Farinaz Koushanfar Automated Real-Time Analysis of
Streaming Big and Dense Data on
Reconfigurable Platforms . . . . . . . . 8:1--8:??
Alban Bourge and
Olivier Muller and
Frédéric Rousseau Generating Efficient Context-Switch
Capable Circuits through Autonomous
Design Flow . . . . . . . . . . . . . . 9:1--9:??
João M. P. Cardoso and
Cristina Silvano Introduction to the Special Section on
FPL 2015 . . . . . . . . . . . . . . . . 10:1--10:??
Jin Hee Kim and
Jason H. Anderson Synthesizable Standard Cell FPGA Fabrics
Targetable by the Verilog-to-Routing CAD
Flow . . . . . . . . . . . . . . . . . . 11:1--11:??
Pavel Burovskiy and
Paul Grigoras and
Spencer Sherwin and
Wayne Luk Efficient Assembly for High-Order
Unstructured FEM Meshes (FPL 2015) . . . 12:1--12:??
Hsin-Jung Yang and
Kermin Fleming and
Felix Winterstein and
Michael Adler and
Joel Emer (FPL 2015) Scavenger: Automating the
Construction of Application-Optimized
Memory Hierarchies . . . . . . . . . . . 13:1--13:??
Nachiket Kapre and
Jan Gray Hoplite: a Deflection-Routed Directional
Torus NoC for FPGAs . . . . . . . . . . 14:1--14:??
Philip H. W. Leong and
Hideharu Amano and
Jason Anderson and
Koen Bertels and
João M. P. Cardoso and
Oliver Diessel and
Guy Gogniat and
Mike Hutton and
Junkyu Lee and
Wayne Luk and
Patrick Lysaght and
Marco Platzner and
Viktor K. Prasanna and
Tero Rissa and
Cristina Silvano and
Hayden Kwok-Hay So and
Yu Wang The First 25 Years of the FPL
Conference: Significant Papers . . . . . 15:1--15:??
Shigeyuki Takano Performance Scalability of Adaptive
Processor Architecture . . . . . . . . . 16:1--16:??
Zhiqiang Liu and
Yong Dou and
Jingfei Jiang and
Jinwei Xu and
Shijie Li and
Yongmei Zhou and
Yingnan Xu Throughput-Optimized FPGA Accelerator
for Deep Convolutional Neural Networks 17:1--17:??
Tomohiro Ueno and
Kentaro Sano and
Satoru Yamamoto Bandwidth Compression of Floating-Point
Numerical Data Streams for FPGA-Based
High-Performance Computing . . . . . . . 18:1--18:??
Charles Eric Laforest and
Jason H. Anderson Microarchitectural Comparison of the MXP
and Octavo Soft-Processor FPGA Overlays 19:1--19:??
Chongyan Gu and
Neil Hanley and
Máire O'neill Improved Reliability of FPGA-Based PUF
Identification Generator Design . . . . 20:1--20:??
Adrien Prost-Boucle and
Frédéric Pétrot and
Vincent Leroy and
Hande Alemdar Efficient and Versatile FPGA
Acceleration of Support Counting for
Stream Mining of Sequences and Frequent
Itemsets . . . . . . . . . . . . . . . . 21:1--21:??
Ilian Tili and
Kalin Ovtcharov and
J. Gregory Steffan Reducing the Performance Gap between
Soft Scalar CPUs and Custom Hardware
with TILT . . . . . . . . . . . . . . . 22:1--22:??
Nicholas Wulf and
Alan D. George and
Ann Gordon-Ross Optimizing FPGA Performance, Power, and
Dependability with Linear Programming 23:1--23:??
Heinrich Riebler and
Michael Lass and
Robert Mittendorf and
Thomas Löcke and
Christian Plessl Efficient Branch and Bound on FPGAs
Using Work Stealing and
Instance-Specific Designs . . . . . . . 24:1--24:??
Eduardo A. Gerlein and
T. M. Mcginnity and
Ammar Belatreche and
Sonya Coleman Network on Chip Architecture for
Multi-Agent Systems in FPGA . . . . . . 25:1--25:??
Nicholas J. Fraser and
Junkyu Lee and
Duncan J. M. Moss and
Julian Faraone and
Stephen Tridgell and
Craig T. Jin and
Philip H. W. Leong FPGA Implementations of Kernel
Normalised Least Mean Squares Processors 26:1--26:??
Thiem Van Chu and
Shimpei Sato and
Kenji Kise Fast and Cycle-Accurate Emulation of
Large-Scale Networks-on-Chip Using a
Single FPGA . . . . . . . . . . . . . . 27:1--27:??
Masato Yoshimi and
Yasin Oge and
Tsutomu Yoshinaga Pipelined Parallel Join and Its
FPGA-Based Acceleration . . . . . . . . 28:1--28:??
Pieter Fabry and
David Thomas Efficient Reconfigurable Architecture
for Pricing Exotic Options . . . . . . . 29:1--29:??
Jason D. Bakos Introduction to the Special Section on
FCCM'16 . . . . . . . . . . . . . . . . 1:1--1:??
Henry Wong and
Vaughn Betz and
Jonathan Rose High-Performance Instruction Scheduling
Circuits for Superscalar Out-of-Order
Soft Processors . . . . . . . . . . . . 1:1--1:??
James J. Davis and
Eddie Hung and
Joshua M. Levine and
Edward A. Stott and
Peter Y. K. Cheung and
George A. Constantinides KAPow: High-Accuracy, Low-Overhead
Online Per-Module Power Estimation for
FPGA Designs . . . . . . . . . . . . . . 2:1--2:??
Hans Giesen and
Benjamin Gojman and
Raphael Rubin and
Ji Kim and
André Dehon Continuous Online Self-Monitoring
Introspection Circuitry for Timing
Repair by Incremental
Partial-Reconfiguration (COSMIC TRIP) 3:1--3:??
Zhuoran Zhao and
Nguyen T. H. Nguyen and
Dimitris Agiakatsikas and
Ganghee Lee and
Ediz Cetin+ and
Oliver Diessel Fine-Grained Module-Based Error Recovery
in FPGA-Based TMR Systems . . . . . . . 4:1--4:??
Muhammed Al Kadi and
Benedikt Janssen and
Jones Yudi and
Michael Huebner General-Purpose Computing with Soft GPUs
on FPGAs . . . . . . . . . . . . . . . . 5:1--5:??
Kosuke Tatsumura and
Sadegh Yazdanshenas and
Vaughn Betz Enhancing FPGAs with Magnetic Tunnel
Junction-Based Block RAMs . . . . . . . 6:1--6:??
Robert Stewart and
Kirsty Duncan and
Greg Michaelson and
Paulo Garcia and
Deepayan Bhowmik and
Andrew Wallace RIPL: a Parallel Image Processing
Language for FPGAs . . . . . . . . . . . 7:1--7:??
Farheen Fatima Khan and
Andy Ye An Evaluation on the Accuracy of the
Minimum-Width Transistor Area Models in
Ranking the Layout Area of FPGA
Architectures . . . . . . . . . . . . . 8:1--8:??
Deshya Wijesundera and
Alok Prakash and
Thambipillai Srikanthan and
Achintha Ihalage Framework for Rapid Performance
Estimation of Embedded Soft Core
Processors . . . . . . . . . . . . . . . 9:1--9:??
Enrico Rossi and
Marvin Damschen and
Lars Bauer and
Giorgio Buttazzo and
Jörg Henkel Preemption of the Partial
Reconfiguration Process to Enable
Real-Time Computing With FPGAs . . . . . 10:1--10:??
Oleg Petelin and
Vaughn Betz Wotan: Evaluating FPGA Architecture
Routability without Benchmarks . . . . . 11:1--11:??
N. Nalla Anandakumar and
M. Prem Laxman Das and
Somitra K. Sanadhya and
Mohammad S. Hashmi Reconfigurable Hardware Architecture for
Authenticated Key Agreement Protocol
Over Binary Edwards Curve . . . . . . . 12:1--12:??
Marc-Andre Daigneault and
Jean Pierre David Automated Synthesis of Streaming
Transfer Level Hardware Designs . . . . 13:1--13:??
Deming Chen and
Andrew Putnam and
Steve Wilton Introduction to the Special Section on
Deep Learning in FPGAs . . . . . . . . . 14:1--14:??
Adrien Prost-Boucle and
Alban Bourge and
Frédéric Pétrot High-Efficiency Convolutional Ternary
Neural Networks with Custom Adder Trees
and Weight Compression . . . . . . . . . 15:1--15:??
Michaela Blott and
Thomas B. Preußer and
Nicholas J. Fraser and
Giulio Gambardella and
Kenneth O'brien and
Yaman Umuroglu and
Miriam Leeser and
Kees Vissers FINN-R: an End-to-End Deep-Learning
Framework for Fast Exploration of
Quantized Neural Networks . . . . . . . 16:1--16:??
Ruizhou Ding and
Zeye Liu and
R. D. (Shawn) Blanton and
Diana Marculescu Lightening the Load with Highly Accurate
Storage- and Energy-Efficient LightNNs 17:1--17:??
Paolo Meloni and
Alessandro Capotondi and
Gianfranco Deriu and
Michele Brian and
Francesco Conti and
Davide Rossi and
Luigi Raffo and
Luca Benini NEURAghe: Exploiting CPU--FPGA Synergies
for Efficient and Flexible CNN Inference
Acceleration on Zynq SoCs . . . . . . . 18:1--18:??
Shuanglong Liu and
Hongxiang Fan and
Xinyu Niu and
Ho-cheung Ng and
Yang Chu and
Wayne Luk Optimizing CNN-based Segmentation with
Deeply Customized Convolutional and
Deconvolutional Architectures on FPGA 19:1--19:??
Andrew Boutros and
Sadegh Yazdanshenas and
Vaughn Betz You Cannot Improve What You Do not
Measure: FPGA vs. ASIC Efficiency Gaps
for Convolutional Neural Network
Inference . . . . . . . . . . . . . . . 20:1--20:??
Bita Darvish Rouhani and
Siam Umar Hussain and
Kristin Lauter and
Farinaz Koushanfar ReDCrypt: Real-Time Privacy-Preserving
Deep Learning Inference in Clouds Using
FPGAs . . . . . . . . . . . . . . . . . 21:1--21:??
Jincheng Yu and
Guangjun Ge and
Yiming Hu and
Xuefei Ning and
Jiantao Qiu and
Kaiyuan Guo and
Yu Wang and
Huazhong Yang Instruction Driven Cross-layer CNN
Accelerator for Fast Detection on FPGA 22:1--22:??
Wensong Li and
Fan Yang and
Hengliang Zhu and
Xuan Zeng and
Dian Zhou An Efficient Memory Partitioning
Approach for Multi-Pattern Data Access
via Data Reuse . . . . . . . . . . . . . 1:1--1:??
Kaiyuan Guo and
Shulin Zeng and
Jincheng Yu and
Yu Wang and
Huazhong Yang [DL] A Survey of FPGA-based Neural
Network Inference Accelerators . . . . . 2:1--2:??
Sadegh Yazdanshenas and
Vaughn Betz COFFE 2: Automatic Modelling and
Optimization of Complex and
Heterogeneous FPGA Architectures . . . . 3:1--3:??
Young-Kyu Choi and
Jason Cong and
Zhenman Fang and
Yuchen Hao and
Glenn Reinman and
Peng Wei In-Depth Analysis on Microarchitectures
of Modern Heterogeneous CPU--FPGA
Platforms . . . . . . . . . . . . . . . 4:1--4:??
Shijie Cao and
Lanshun Nie and
Dechen Zhan and
Wenqiang Wang and
Ningyi Xu and
Ramashis Das and
Ming Wu and
Lintao Zhang and
Derek Chiou FlexSaaS: a Reconfigurable Accelerator
for Web Search Selection . . . . . . . . 5:1--5:??
Gai Liu and
Zhiru Zhang PIMap: a Flexible Framework for
Improving LUT-Based Technology Mapping
via Parallelized Iterative Optimization 23:1--23:??
Haomiao Wang and
Prabu Thiagaraj and
Oliver Sinnen FPGA-based Acceleration of FT
Convolution for Pulsar Search Using
OpenCL . . . . . . . . . . . . . . . . . 24:1--24:??
Alexander Kroh and
Oliver Diessel Efficient Fine-grained Processor-logic
Interactions on the Cache-coherent Zynq
Platform . . . . . . . . . . . . . . . . 25:1--25:??
Naveen Kumar Dumpala and
Shivukumar B. Patil and
Daniel Holcomb and
Russell Tessier Loop Unrolling for Energy Efficiency in
Low-Cost Field-Programmable Gate Arrays 26:1--26:??
Deming Chen Editorial: a Message from the New
Editor-in-Chief . . . . . . . . . . . . 6:1--6:??
Raghid Morcel and
Hazem Hajj and
Mazen A. R. Saghir and
Haitham Akkary and
Hassan Artail and
Rahul Khanna and
Anil Keshavamurthy FeatherNet: an Accelerated Convolutional
Neural Network Design for
Resource-constrained FPGAs . . . . . . . 6:1--6:??
Xuegong Zhou and
Lingli Wang and
Alan Mishchenko Fast Adjustable NPN Classification Using
Generalized Symmetries . . . . . . . . . 7:1--7:??
Julian Oppermann and
Melanie Reuter-Oppermann and
Lukas Sommer and
Andreas Koch and
Oliver Sinnen Exact and Practical Modulo Scheduling
for High-Level Synthesis . . . . . . . . 8:1--8:??
Chunkun Bo and
Vinh Dang and
Ted Xie and
Jack Wadden and
Mircea Stan and
Kevin Skadron Automata Processing in Reconfigurable
Architectures: In-the-Cloud Deployment,
Cross-Platform Evaluation, and Fast
Symbol-Only Reconfiguration . . . . . . 9:1--9:??
Van Luan Dinh and
Xuan Truong Nguyen and
Hyuk-Jae Lee A Novel FPGA Implementation of a
Time-to-Digital Converter Supporting
Run-Time Estimation and Compensation . . 10:1--10:??
Chistophe Bobda and
Ken Eguro Introduction to the Special Section on
Security in FPGA-accelerated Cloud and
Datacenters . . . . . . . . . . . . . . 11:1--11:??
Ilias Giechaskiel and
Ken Eguro and
Kasper B. Rasmussen Leakier Wires: Exploiting FPGA Long
Wires for Covert- and Side-channel
Attacks . . . . . . . . . . . . . . . . 11:1--11:??
Jonas Krautter and
Dennis R. E. Gnad and
Mehdi B. Tahoori Mitigating Electrical-level Attacks
towards Secure Multi-Tenant FPGAs in the
Cloud . . . . . . . . . . . . . . . . . 12:1--12:??
Muhammad E. S. Elrabaa and
Mohamed A. Al-Asli and
Marwan H. Abu-Amara A Protection and Pay-per-use Licensing
Scheme for On-cloud FPGA Circuit IPs . . 13:1--13:??
Jiliang Zhang and
Gang Qu Recent Attacks and Defenses on
FPGA-based Systems . . . . . . . . . . . 14:1--14:??
Yaman Umuroglu and
Davide Conficconi and
Lahiru Rasnayake and
Thomas B. Preusser and
Magnus Själander Optimizing Bit-Serial Matrix
Multiplication for Reconfigurable
Computing . . . . . . . . . . . . . . . 15:1--15:??
Abeer Al-Hyari and
Ziad Abuowaimer and
Timothy Martin and
Gary Gréwal and
Shawki Areibi and
Anthony Vannelli Novel Congestion-estimation and
Routability-prediction Methods based on
Machine Learning for Modern FPGAs . . . 16:1--16:??
Muhsen Owaida and
Amit Kulkarni and
Gustavo Alonso Distributed Inference over Decision Tree
Ensembles on Clusters of FPGAs . . . . . 17:1--17:??
Ibrahim Ahmed and
Shuze Zhao and
James Meijers and
Olivier Trescases and
Vaughn Betz FRoC 2.0: Automatic BRAM and Logic
Testing to Enable Dynamic Voltage
Scaling for FPGA Applications . . . . . 20:1--20:??
Stephen Tridgell and
Martin Kumm and
Martin Hardieck and
David Boland and
Duncan Moss and
Peter Zipf and
Philip H. W. Leong Unrolling Ternary Neural Networks . . . 22:1--22:??
François Serre and
Markus Püschel DSL-Based Hardware Generation with
Scala: Example Fast Fourier Transforms
and Sorting Networks . . . . . . . . . . 1:1--1:23
Nikolaos Alachiotis and
Charalampos Vatsolakis and
Grigorios Chrysos and
Dionisios Pnevmatikatos RAiSD-X: a Fast and Accurate FPGA System
for the Detection of Positive Selection
in Thousands of Genomes . . . . . . . . 2:1--2:30
Sameh Attia and
Vaughn Betz Feel Free to Interrupt: Safe Task
Stopping to Enable FPGA Checkpointing
and Context Switching . . . . . . . . . 3:1--3:27
Al-Shahna Jamal and
Eli Cahill and
Jeffrey Goeders and
Steven J. E. Wilton Fast Turnaround HLS Debugging Using
Dependency Analysis and Debug Overlays 4:1--4:26
Alexandra Kourfali and
Dirk Stroobandt In-Circuit Debugging with Dynamic
Reconfiguration of FPGA Interconnects 5:1--5:29
Tushar Garg and
Saud Wasly and
Rodolfo Pellizzoni and
Nachiket Kapre HopliteBuf: Network Calculus-Based
Design of FPGA NoCs with Provably
Stall-Free FIFOs . . . . . . . . . . . . 6:1--6:35
Nicholas J. Fraser and
Philip H. W. Leong Kernel Normalised Least Mean Squares
with Delayed Model Adaptation . . . . . 7:1--7:30
Maciej Besta and
Marc Fischer and
Tal Ben-Nun and
Dimitri Stanojevic and
Johannes De Fine Licht and
Torsten Hoefler Substream-Centric Maximum Matchings on
FPGA . . . . . . . . . . . . . . . . . . 8:1--8:33
Kevin E. Murray and
Oleg Petelin and
Sheng Zhong and
Jia Min Wang and
Mohamed Eldafrawy and
Jean-Philippe Legault and
Eugene Sha and
Aaron G. Graham and
Jean Wu and
Matthew J. P. Walker and
Hanqing Zeng and
Panagiotis Patros and
Jason Luu and
Kenneth B. Kent and
Vaughn Betz VTR 8: High-performance CAD and
Customizable FPGA Architecture Modelling 9:1--9:55
Yann Delomier and
Bertrand Le Gal and
Jerémie Crenne and
Christophe Jego Model-based Design of Hardware SC Polar
Decoders for FPGAs . . . . . . . . . . . 10:1--10:27
Zhiyuan Shao and
Chenhao Liu and
Ruoshi Li and
Xiaofei Liao and
Hai Jin Processing Grid-format Real-world Graphs
on DRAM-based FPGA Accelerators with
Application-specific Caching Mechanisms 11:1--11:33
Mohamed Eldafrawy and
Andrew Boutros and
Sadegh Yazdanshenas and
Vaughn Betz FPGA Logic Block Architectures for
Efficient Deep Learning Inference . . . 12:1--12:34
Jiandong Mu and
Wei Zhang and
Hao Liang and
Sharad Sinha Optimizing OpenCL-Based CNN Design on
FPGA with Comprehensive Design Space
Exploration and Collaborative
Performance Modeling . . . . . . . . . . 13:1--13:28
Sebastian Sabogal and
Alan George and
Christopher Wilson Reconfigurable Framework for
Environmentally Adaptive Resilience in
Hybrid Space Systems . . . . . . . . . . 14:1--14:32
Tuan Minh La and
Kaspar Matas and
Nikola Grunchevski and
Khoa Dang Pham and
Dirk Koch FPGADefender: Malicious Self-oscillator
Scanning for Xilinx UltraScale + FPGAs 15:1--15:31
Qi Tang and
Zhe Wang and
Biao Guo and
Li-Hua Zhu and
Ji-Bo Wei Partitioning and Scheduling with Module
Merging on Dynamic Partial
Reconfigurable FPGAs . . . . . . . . . . 16:1--16:24
André Dehon Introduction to Special Section on FCCM
2019 . . . . . . . . . . . . . . . . . . 17:1--17:2
Yun Zhou and
Dries Vercruyce and
Dirk Stroobandt Accelerating FPGA Routing Through
Algorithmic Enhancements and
Connection-aware Parallelization . . . . 18:1--18:26
Jialiang Zhang and
Yue Zha and
Nicholas Beckwith and
Bangya Liu and
Jing Li MEG: a RISCV-based System Emulation
Infrastructure for Near-data Processing
Using FPGAs and High-bandwidth Memory 19:1--19:24
Anuj Vaishnav and
Khoa Dang Pham and
Joseph Powell and
Dirk Koch FOS: a Modular FPGA Operating System for
Dynamic Workloads . . . . . . . . . . . 20:1--20:28
Aggelos D. Ioannou and
Konstantinos Georgopoulos and
Pavlos Malakonakis and
Dionisios N. Pnevmatikatos and
Vassilis D. Papaefstathiou and
Ioannis Papaefstathiou and
Iakovos Mavroidis UNILOGIC: a Novel Architecture for
Highly Parallel Reconfigurable Systems 21:1--21:32
Xuzhi Zhang and
Xiaozhe Shao and
George Provelengios and
Naveen Kumar Dumpala and
Lixin Gao and
Russell Tessier CoNFV: a Heterogeneous Platform for
Scalable Network Function Virtualization 1:1--1:29
Alexander E. Beasley and
C. T. Clarke and
R. J. Watson An OpenGL Compliant Hardware
Implementation of a Graphic Processing
Unit Using Field Programmable Gate
Array-System on Chip Technology . . . . 2:1--2:24
Kaan Kara and
Gustavo Alonso PipeArch: Generic and Context-Switch
Capable Data Processing on FPGAs . . . . 3:1--3:28
Soheil Mohajer and
Zhiheng Wang and
Kia Bazargan and
Yuyang Li Parallel Unary Computing Based on
Function Derivatives . . . . . . . . . . 4:1--4:25
Nikolaos Kyparissas and
Apostolos Dollas Large-scale Cellular Automata on FPGAs:
a New Generic Architecture and a
Framework . . . . . . . . . . . . . . . 5:1--5:32
Adriaan Peetermans and
Vladimir Rozi\'c and
Ingrid Verbauwhede Design and Analysis of Configurable Ring
Oscillators for True Random Number
Generation Based on Coherent Sampling 7:1--7:20
Shenghsun Cho and
Mrunal Patel and
Michael Ferdman and
Peter Milder Practical Model Checking on FPGAs . . . 8:1--8:18
Rui Ma and
Jia-Ching Hsu and
Tian Tan and
Eriko Nurvitadhi and
David Sheffield and
Rob Pelt and
Martin Langhammer and
Jaewoong Sim and
Aravind Dasu and
Derek Chiou Specializing FGPU for Persistent Deep
Learning . . . . . . . . . . . . . . . . 10:1--10:23
Zhen Zhou and
Debiao He and
Zhe Liu and
Min Luo and
Kim-Kwang Raymond Choo A Software/Hardware Co-Design of
Crystals-Dilithium Signature Scheme . . 11:1--11:21
Ryota Yasudo and
José G. F. Coutinho and
Ana-Lucia Varbanescu and
Wayne Luk and
Hideharu Amano and
Tobias Becker and
Ce Guo Analytical Performance Estimation for
Large-Scale Reconfigurable Dataflow
Platforms . . . . . . . . . . . . . . . 12:1--12:21
Endri Taka and
Konstantinos Maragos and
George Lentaris and
Dimitrios Soudris Process Variability Analysis in
Interconnect, Logic, and Arithmetic
Blocks of 16-nm FinFET FPGAs . . . . . . 13:1--13:30
Arif Sasongko and
I. M. Narendra Kumara and
Arief Wicaksana and
Frédéric Rousseau and
Olivier Muller Hardware Context Switch-based
Cryptographic Accelerator for Handling
Multiple Streams . . . . . . . . . . . . 14:1--14:25
Enrico Reggiani and
Emanuele Del Sozzo and
Davide Conficconi and
Giuseppe Natale and
Carlo Moroni and
Marco D. Santambrogio Enhancing the Scalability of Multi-FPGA
Stencil Computations via Highly
Optimized HDL Components . . . . . . . . 15:1--15:33
Abeer Al-Hyari and
Hannah Szentimrey and
Ahmed Shamli and
Timothy Martin and
Gary Gréwal and
Shawki Areibi A Deep Learning Framework to Predict
Routability for FPGA Circuit Placement 16:1--16:28
Yi-Hsiang Lai and
Ecenur Ustun and
Shaojie Xiang and
Zhenman Fang and
Hongbo Rong and
Zhiru Zhang Programming and Synthesis for
Software-defined FPGA Acceleration:
Status and Future Prospects . . . . . . 17:1--17:39
Tao Yang and
Zhezhi He and
Tengchuan Kou and
Qingzheng Li and
Qi Han and
Haibao Yu and
Fangxin Liu and
Yun Liang and
Li Jiang BISWSRBS: a Winograd-based CNN
Accelerator with a Fine-grained Regular
Sparsity Pattern and Mixed Precision
Quantization . . . . . . . . . . . . . . 18:1--18:28
Mark Wijtvliet and
Henk Corporaal and
Akash Kumar CGRA-EAM-Rapid Energy and Area
Estimation for Coarse-grained
Reconfigurable Architectures . . . . . . 19:1--19:28
Zhenghua Gu and
Wenqing Wan and
Jundong Xie and
Chang Wu Dependency Graph-based High-level
Synthesis for Maximum Instruction
Parallelism . . . . . . . . . . . . . . 20:1--20:15
José Romero Hung and
Chao Li and
Pengyu Wang and
Chuanming Shao and
Jinyang Guo and
Jing Wang and
Guoyong Shi ACE-GCN: a Fast Data-driven FPGA
Accelerator for GCN Embedding . . . . . 21:1--21:23
Sebastian Sabogal and
Alan George and
Gary Crum Reconfigurable Framework for Resilient
Semantic Segmentation for Space
Applications . . . . . . . . . . . . . . 22:1--22:32
Lesley Shannon Introduction to Special Section on FPGA
2020 . . . . . . . . . . . . . . . . . . 1:1--1:2
Vladimir Rybalkin and
Jonas Ney and
Menbere Kina Tekleyohannes and
Norbert Wehn When Massive GPU Parallelism Ain't
Enough: a Novel Hardware Architecture of
$2$D-LSTM Neural Network . . . . . . . . 2:1--2:35
Philippos Papaphilippou and
Jiuxi Meng and
Nadeen Gebara and
Wayne Luk Hipernetch: High-Performance FPGA
Network Switch . . . . . . . . . . . . . 3:1--3:31
Lana Josipovi\'c and
Shabnam Sheikhha and
Andrea Guerrieri and
Paolo Ienne and
Jordi Cortadella Buffer Placement and Sizing for
High-Performance Dataflow Circuits . . . 4:1--4:32
Mathieu Gross and
Konrad Hohentanner and
Stefan Wiehler and
Georg Sigl Enhancing the Security of FPGA-SoCs via
the Usage of ARM TrustZone and a
Hybrid-TPM . . . . . . . . . . . . . . . 5:1--5:26
Chen Wu and
Mingyu Wang and
Xinyuan Chu and
Kun Wang and
Lei He Low-precision Floating-point Arithmetic
for High-performance FPGA-based CNN
Acceleration . . . . . . . . . . . . . . 6:1--6:21
Deming Chen Note from the TRETS EiC about the new
Journal-first track in FPT'21 . . . . . 7e:1--7e:1
Franz-Josef Streit and
Paul Krüger and
Andreas Becher and
Stefan Wildermann and
Jürgen Teich Design and Evaluation of a Tunable PUF
Architecture for FPGAs . . . . . . . . . 7:1--7:27
Yun Zhou and
Pongstorn Maidee and
Chris Lavin and
Alireza Kaviani and
Dirk Stroobandt RWRoute: an Open-source Timing-driven
Router for Commercial FPGAs . . . . . . 8:1--8:27
Seyedramin Rasoulinezhad and
Esther Roorda and
Steve Wilton and
Philip H. W. Leong and
David Boland Rethinking Embedded Blocks for Machine
Learning Applications . . . . . . . . . 9:1--9:30
Johannes Menzel and
Christian Plessl and
Tobias Kenter The Strong Scaling Advantage of FPGAs in
HPC for $N$-body Simulations . . . . . . 10:1--10:30
Ken Eguro and
Stephen Neuendorffer and
Viktor Prasanna and
Hongbo Rong Introduction to Special Issue on FPGAs
in Data Centers . . . . . . . . . . . . 11:1--11:2
Andrew M. Keller and
Michael J. Wirthlin The Impact of Terrestrial Radiation on
FPGAs in Data Centers . . . . . . . . . 12:1--12:21
Mikhail Asiatici and
Paolo Ienne Request, Coalesce, Serve, and Forget:
Miss-Optimized Memory Systems for
Bandwidth-Bound Cache-Unfriendly
Applications on FPGAs . . . . . . . . . 13:1--13:33
Atakan Dogan and
Kemal Ebcioglu Cloud Building Block Chip for Creating
FPGA and ASIC Clouds . . . . . . . . . . 14:1--14:35
Tobias Alonso and
Lucian Petrica and
Mario Ruiz and
Jakoba Petri-Koenig and
Yaman Umuroglu and
Ioannis Stamelos and
Elias Koromilas and
Michaela Blott and
Kees Vissers Elastic-DF: Scaling Performance of DNN
Inference in FPGA Clouds through
Automatic Partitioning . . . . . . . . . 15:1--15:34
Sahand Salamat and
Hui Zhang and
Yang Seok Ki and
Tajana Rosing \pkgNASCENT2: Generic Near-Storage Sort
Accelerator for Data Analytics on
SmartSSD . . . . . . . . . . . . . . . . 16:1--16:29
Andrea Damiani and
Giorgia Fiscaletti and
Marco Bacis and
Rolando Brondolin and
Marco D. Santambrogio \pkgBlastFunction: a Full-stack
Framework Bringing FPGA Hardware
Acceleration to Cloud-native
Applications . . . . . . . . . . . . . . 17:1--17:27
Paolo D'Alberto and
Victor Wu and
Aaron Ng and
Rahul Nimaiyar and
Elliott Delaye and
Ashish Sirasao \pkgxDNN: Inference for Deep
Convolutional Neural Networks . . . . . 18:1--18:29
Joel Mandebi Mbongue and
Danielle Tchuinkou Kwadjo and
Alex Shuping and
Christophe Bobda Deploying Multi-tenant FPGAs within
Linux-based Cloud Infrastructure . . . . 19:1--19:31
Tom Hogervorst and
Razvan Nane and
Giacomo Marchiori and
Tong Dong Qiu and
Markus Blatt and
Alf Birger Rustad Hardware Acceleration of
High-Performance Computational Flow
Dynamics Using High-Bandwidth
Memory-Enabled Field-Programmable Gate
Arrays . . . . . . . . . . . . . . . . . 20:1--20:35
Gongjin Sun and
Seongyoung Kang and
Sang-Woo Jun \pkgBurstZ+: Eliminating The
Communication Bottleneck of Scientific
Computing Accelerators via Accelerated
Compression . . . . . . . . . . . . . . 21:1--21:34
Ken Eguro and
Stephen Neuendorffer and
Viktor Prasanna and
Hongbo Rong Introduction to Special Issue on FPGAs
in Data Centers, Part II . . . . . . . . 22:1--22:2
Naif Tarafdar and
Giuseppe Di Guglielmo and
Philip C. Harris and
Jeffrey D. Krupa and
Vladimir Loncar and
Dylan S. Rankin and
Nhan Tran and
Zhenbin Wu and
Qianfeng Shen and
Paul Chow AIgean: an Open Framework for Deploying
Machine Learning on Heterogeneous
Clusters . . . . . . . . . . . . . . . . 23:1--23:32
Shulin Zeng and
Guohao Dai and
Hanbo Sun and
Jun Liu and
Shiyao Li and
Guangjun Ge and
Kai Zhong and
Kaiyuan Guo and
Yu Wang and
Huazhong Yang A Unified FPGA Virtualization Framework
for General-Purpose Deep Neural Networks
in the Cloud . . . . . . . . . . . . . . 24:1--24:31
Nikolaos Alachiotis and
Panagiotis Skrimponis and
Manolis Pissadakis and
Dionisios Pnevmatikatos Scalable Phylogeny Reconstruction with
Disaggregated Near-memory Processing . . 25:1--25:32
Stefan Brennsteiner and
Tughrul Arslan and
John Thompson and
Andrew McCormick A Real-Time Deep Learning OFDM Receiver 26:1--26:25
Christian Lienen and
Marco Platzner Design of Distributed Reconfigurable
Robotics Systems with ReconROS . . . . . 27:1--27:20
Eli Cahill and
Brad Hutchings and
Jeffrey Goeders Approaches for FPGA Design Assurance . . 28:1--28:29
S. Rasoul Faraji and
Pierre Abillama and
Kia Bazargan Approximate Constant-Coefficient
Multiplication Using Hybrid Binary-Unary
Computing for FPGAs . . . . . . . . . . 29:1--29:25
Gaoming Du and
Bangyi Chen and
Zhenmin Li and
Zhenxing Tu and
Junjie Zhou and
Shenya Wang and
Qinghao Zhao and
Yongsheng Yin and
Xiaolei Wang A BNN Accelerator Based on
Edge-skip-calculation Strategy and
Consolidation Compressed Tree . . . . . 30:1--30:20
Florian Dewald and
Johanna Rohde and
Christian Hochberger and
Heiko Mantel Improving Loop Parallelization by a
Combination of Static and Dynamic
Analyses in HLS . . . . . . . . . . . . 31:1--31:31
Eric Matthews and
Alec Lu and
Zhenman Fang and
Lesley Shannon Quick-Div: Rethinking Integer Divider
Design for FPGA-based Soft-processors 32:1--32:27
Esther Roorda and
Seyedramin Rasoulinezhad and
Philip H. W. Leong and
Steven J. E. Wilton FPGA Architecture Exploration for DNN
Acceleration . . . . . . . . . . . . . . 33:1--33:37
Christophe Bobda and
Joel Mandebi Mbongue and
Paul Chow and
Mohammad Ewais and
Naif Tarafdar and
Juan Camilo Vega and
Ken Eguro and
Dirk Koch and
Suranga Handagala and
Miriam Leeser and
Martin Herbordt and
Hafsah Shahzad and
Peter Hofste and
Burkhard Ringlein and
Jakub Szefer and
Ahmed Sanaullah and
Russell Tessier The Future of FPGA Acceleration in
Datacenters and the Cloud . . . . . . . 34:1--34:42
Nele Mentens and
Lionel Sousa and
Pedro Trancoso Introduction to the Special Section on
FPL 2020 . . . . . . . . . . . . . . . . 35:1--35:??
Runbin Shi and
Kaan Kara and
Christoph Hagleitner and
Dionysios Diamantopoulos and
Dimitris Syrivelis and
Gustavo Alonso Exploiting HBM on FPGAs for Data
Processing . . . . . . . . . . . . . . . 36:1--36:??
Stefan Nikoli\'c and
Grace Zgheib and
Paolo Ienne Detailed Placement for Dedicated
LUT-Level FPGA Interconnect . . . . . . 37:1--37:??
Niansong Zhang and
Xiang Chen and
Nachiket Kapre RapidLayout: Fast Hard Block Placement
of FPGA-optimized Systolic Arrays Using
Evolutionary Algorithm . . . . . . . . . 38:1--38:??
Gagandeep Singh and
Dionysios Diamantopoulos and
Juan Gómez-Luna and
Christoph Hagleitner and
Sander Stuijk and
Henk Corporaal and
Onur Mutlu Accelerating Weather Prediction Using
Near-Memory Reconfigurable Fabric . . . 39:1--39:??
Gurshaant Malik and
Ian Elmore Lang and
Rodolfo Pellizzoni and
Nachiket Kapre HopliteML: Evolving Application
Customized FPGA NoCs with Adaptable
Routers and Regulators . . . . . . . . . 40:1--40:??
Hayden Cook and
Jacob Arscott and
Brent George and
Tanner Gaskin and
Jeffrey Goeders and
Brad Hutchings Inducing Non-uniform FPGA Aging Using
Configuration-based Short Circuits . . . 41:1--41:??
Philip H. W. Leong Introduction to Special Section on FPGA
2021 . . . . . . . . . . . . . . . . . . 42:1--42:??
Alec Lu and
Zhenman Fang and
Lesley Shannon Demystifying the Soft and Hardened
Memory Systems of Modern FPGAs for
Software Programmers through
Microbenchmarking . . . . . . . . . . . 43:1--43:??
Xinyu Chen and
Feng Cheng and
Hongshi Tan and
Yao Chen and
Bingsheng He and
Weng-Fai Wong and
Deming Chen ThunderGP: Resource-Efficient Graph
Processing Framework on FPGAs with HLS 44:1--44:??
Martin Langhammer and
Eriko Nurvitadhi and
Sergey Gribok and
Bogdan Pasca Stratix 10 NX Architecture . . . . . . . 45:1--45:??
Aman Arora and
Moinak Ghosh and
Samidh Mehta and
Vaughn Betz and
Lizy K. John Tensor Slices: FPGA Building Blocks For
the Deep Learning Era . . . . . . . . . 46:1--46:??
Kemal Ebcioglu and
Ismail San Highly Parallel Multi-FPGA System
Compilation from Sequential C/C++ Code
in the AWS Cloud . . . . . . . . . . . . 47:1--47:??
Sathish Panchapakesan and
Zhenman Fang and
Jian Li SyncNN: Evaluating and Accelerating
Spiking Neural Networks on FPGAs . . . . 48:1--48:??
Kahlan Gibson and
Esther Roorda and
Daniel Holanda Noronha and
Steven J. E. Wilton Adaptive Clock Management of
HLS-generated Circuits on FPGAs . . . . 49:1--49:??
Krystine Dawn Sherwin and
Kevin I-Kai Wang and
Prabu Thiagaraj and
Ben Stappers and
Oliver Sinnen Median Filters on FPGAs for Infinite
Data and Large, Rectangular Windows . . 50:1--50:??
Jason Cong and
Jason Lau and
Gai Liu and
Stephen Neuendorffer and
Peichen Pan and
Kees Vissers and
Zhiru Zhang FPGA HLS Today: Successes, Challenges,
and Opportunities . . . . . . . . . . . 51:1--51:??
Oliver Sinnen and
Qiang Liu and
Azadeh Davoodi Introduction to Special Section on
FPT'20 . . . . . . . . . . . . . . . . . 1:1--1:??
Kaichuang Shi and
Xuegong Zhou and
Hao Zhou and
Lingli Wang An Optimized GIB Routing Architecture
with Bent Wires for FPGA . . . . . . . . 2:1--2:??
Xiang Li and
Peter Stanwicks and
George Provelengios and
Russell Tessier and
Daniel Holcomb Jitter-based Adaptive True Random Number
Generation Circuits for FPGAs in the
Cloud . . . . . . . . . . . . . . . . . 3:1--3:??
Zhiqiang Que and
Hiroki Nakahara and
Hongxiang Fan and
He Li and
Jiuxi Meng and
Kuen Hung Tsoi and
Xinyu Niu and
Eriko Nurvitadhi and
Wayne Luk Remarn: a Reconfigurable Multi-threaded
Multi-core Accelerator for Recurrent
Neural Networks . . . . . . . . . . . . 4:1--4:??
Niklas Schelten and
Fritjof Steinert and
Justin Knapheide and
Anton Schulte and
Benno Stabernack A High-Throughput, Resource-Efficient
Implementation of the RoCEv2 Remote DMA
Protocol and its Application . . . . . . 5:1--5:??
Ilias Giechaskiel and
Shanquan Tian and
Jakub Szefer Cross-VM Covert- and Side-Channel
Attacks in Cloud FPGAs . . . . . . . . . 6:1--6:??
Dennis Leander Wolf and
Christoph Spang and
Daniel Diener and
Christian Hochberger Advantages of a Statistical Estimation
Approach for Clock Frequency Estimation
of Heterogeneous and Irregular CGRAs . . 7:1--7:??
Lenos Ioannou and
Suhaib A. Fahmy Streaming Overlay Architecture for
Lightweight LSTM Computation on FPGA
SoCs . . . . . . . . . . . . . . . . . . 8:1--8:??
Xiangwei Li and
Douglas L. Maskell and
Carol Jingyi Li and
Philip H. W. Leong and
David Boland A Scalable Systolic Accelerator for
Estimation of the Spectral Correlation
Density Function and Its FPGA
Implementation . . . . . . . . . . . . . 9:1--9:??
Zhuofu Tao and
Chen Wu and
Yuan Liang and
Kun Wang and
Lei He LW-GCN: a Lightweight FPGA-based Graph
Convolutional Network Accelerator . . . 10:1--10:??
Shayan Moini and
Aleksa Deric and
Xiang Li and
George Provelengios and
Wayne Burleson and
Russell Tessier and
Daniel Holcomb Voltage Sensor Implementations for
Remote Power Attacks on FPGAs . . . . . 11:1--11:??
Amin Kalantar and
Zachary Zimmerman and
Philip Brisk FPGA-based Acceleration of Time Series
Similarity Prediction: From Cloud to
Edge . . . . . . . . . . . . . . . . . . 12:1--12:??
Mário Véstias and
Rui P. Duarte and
José T. de Sousa and
Horácio Neto Efficient Design of Low Bitwidth
Convolutional Neural Networks on FPGA
with Optimized Dot Product Units . . . . 13:1--13:??
Rafael Fão de Moura and
Joao Paulo Cardoso de Lima and
Luigi Carro Data and Computation Reuse in CNNs Using
Memristor TCAMs . . . . . . . . . . . . 14:1--14:??
Riadh Ben Abdelhamid and
Yoshiki Yamaguchi and
Taisuke Boku A Scalable Many-core Overlay
Architecture on an HBM2-enabled
Multi-Die FPGA . . . . . . . . . . . . . 15:1--15:??
Veronia Iskandar and
Mohamed A. Abd El Ghany and
Diana Göhringer Near-memory Computing on FPGAs with
$3$D-stacked Memories: Applications,
Architectures, and Optimizations . . . . 16:1--16:??
Soheil Nazar Shahsavani and
Arash Fayyazi and
Mahdi Nazemi and
Massoud Pedram Efficient Compilation and Mapping of
Fixed Function Combinational Logic onto
Digital Signal Processors Targeting
Neural Network Inference and Utilizing
High-level Synthesis . . . . . . . . . . 17:1--17:??
Young-Kyu Choi and
Carlos Santillana and
Yujia Shen and
Adnan Darwiche and
Jason Cong FPGA Acceleration of Probabilistic
Sentential Decision Diagrams with
High-level Synthesis . . . . . . . . . . 18:1--18:??
Chanaka Ganewattha and
Zaheer Khan and
Janne Lehtomäki and
Matti Latva-Aho Hardware-accelerated Real-time
Drift-awareness for Robust Deep Learning
on Wireless RF Data . . . . . . . . . . 19:1--19:??
Alexandre Proulx and
Jean-Yves Chouinard and
Paul Fortier and
Amine Miled A Survey on FPGA Cybersecurity Design
Strategies . . . . . . . . . . . . . . . 20:1--20:??
Stephanie Soldavini and
Karl Friebel and
Mattia Tibaldi and
Gerald Hempel and
Jeronimo Castrillon and
Christian Pilato Automatic Creation of High-bandwidth
Memory Architectures from
Domain-specific Languages: The Case of
Computational Fluid Dynamics . . . . . . 21:1--21:??
Gangqiang Yang and
Zhengyuan Shi and
Cheng Chen and
Hailiang Xiong and
Fudong Li and
Honggang Hu and
Zhiguo Wan Hardware Optimizations of Fruit-80
Stream Cipher: Smaller than Grain . . . 22:1--22:??
Suhail Basalama and
Atefeh Sohrabizadeh and
Jie Wang and
Licheng Guo and
Jason Cong FlexCNN: an End-to-end Framework for
Composing CNN Accelerators on FPGA . . . 23:1--23:??
Marius Meyer and
Tobias Kenter and
Christian Plessl Multi-FPGA Designs and Scaling of HPC
Challenge Benchmarks via MPI and
Circuit-switched Inter-FPGA Networks . . 24:1--24:??
Tomohiro Ueno and
Kentaro Sano VCSN: Virtual Circuit-Switching Network
for Flexible and Simple-to-Operate
Communication in HPC FPGA Cluster . . . 25:1--25:??
Ankita Nayak and
Keyi Zhang and
Rajsekhar Setaluri and
Alex Carsello and
Makai Mann and
Christopher Torng and
Stephen Richardson and
Rick Bahr and
Pat Hanrahan and
Mark Horowitz and
Priyanka Raina Improving Energy Efficiency of CGRAs
with Low-Overhead Fine-Grained Power
Domains . . . . . . . . . . . . . . . . 26:1--26:??
Kang Zhao and
Yuchun Ma and
Ruining He and
Jixing Zhang and
Ning Xu and
Jinian Bian Adaptive Selection and Clustering of
Partial Reconfiguration Modules for
Modern FPGA Design Flow . . . . . . . . 27:1--27:??
Xingyu Tian and
Zhifan Ye and
Alec Lu and
Licheng Guo and
Yuze Chi and
Zhenman Fang SASA: a Scalable and Automatic Stencil
Acceleration Framework for Optimized
Hybrid Spatial and Temporal Parallelism
on HBM-based FPGAs . . . . . . . . . . . 28:1--28:??
Dhayalakumar M. and
Noor Mahammad Sk Deterministic Approach for
Range-enhanced Reconfigurable Packet
Classification Engine . . . . . . . . . 29:1--29:??
Andreas Koch and
Wei Zhang Introduction to the Special Issue on FPT
2021 . . . . . . . . . . . . . . . . . . 30:1--30:??
Sameh Attia and
Vaughn Betz Toward Software-like Debugging for FPGAs
via Checkpointing and Transaction-based
Co-Simulation . . . . . . . . . . . . . 31:1--31:??
Richard Gebauer and
Nick Karcher and
Mehmed Güler and
Oliver Sander QiCells: a Modular RFSoC-based Approach
to Interface Superconducting Quantum
Bits . . . . . . . . . . . . . . . . . . 32:1--32:??
Han-Sok Suh and
Jian Meng and
Ty Nguyen and
Vijay Kumar and
Yu Cao and
Jae-Sun Seo Algorithm--hardware Co-optimization for
Energy-efficient Drone Detection on
Resource-constrained FPGA . . . . . . . 33:1--33:??
Alex R. Bucknall and
Suhaib A. Fahmy ZyPR: End-to-end Build Tool and Runtime
Manager for Partial Reconfiguration of
FPGA SoCs at the Edge . . . . . . . . . 34:1--34:??
Reinout Corts and
Nikolaos Alachiotis A Survey of Processing Systems for
Phylogenetics and Population Genetics 35:1--35:??
Pedro Machado and
João Filipe Ferreira and
Andreas Oikonomou and
T. M. McGinnity NeuroHSMD: Neuromorphic Hybrid Spiking
Motion Detector . . . . . . . . . . . . 36:1--36:??
Prajith Ramakrishnan Geethakumari and
Ioannis Sourdis Stream Aggregation with Compressed
Sliding Windows . . . . . . . . . . . . 37:1--37:??
Rasha Karakchi and
Jason D. Bakos NAPOLY: a Non-deterministic Automata
Processor OverLaY . . . . . . . . . . . 38:1--38:??
Gopal Raut and
Saurabh Karkun and
Santosh Kumar Vishvakarma An Empirical Approach to Enhance
Performance for Scalable CORDIC-Based
Deep Neural Networks . . . . . . . . . . 39:1--39:??
Miriam Leeser Artifact Evaluation for ACM TRETS Papers
Submitted from the FPT Journal Track . . 40:1--40:??
Carol Jingyi Li and
Xiangwei Li and
Binglei Lou and
Craig T. Jin and
David Boland and
Philip H. W. Leong Fixed-point FPGA Implementation of the
FFT Accumulation Method for Real-time
Cyclostationary Analysis . . . . . . . . 41:1--41:??
Binglei Lou and
David Boland and
Philip Leong fSEAD: a Composable FPGA-based Streaming
Ensemble Anomaly Detection Library . . . 42:1--42:??
Zhengyuan Shi and
Cheng Chen and
Gangqiang Yang and
Hailiang Xiong and
Fudong Li and
Honggang Hu and
Zhiguo Wan Design Space Exploration of Galois and
Fibonacci Configuration Based on
Espresso Stream Cipher . . . . . . . . . 43:1--43:??
Gaoyu Mao and
Donglong Chen and
Guangyan Li and
Wangchen Dai and
Abdurrashid Ibrahim Sanka and
Çetin Kaya Koç and
Ray C. C. Cheung High-performance and Configurable SW/HW
Co-design of Post-quantum Signature
CRYSTALS-Dilithium . . . . . . . . . . . 44:1--44:??
Pengzhou He and
Tianyou Bao and
Jiafeng Xie and
Moeness Amin FPGA Implementation of Compact Hardware
Accelerators for Ring-Binary-LWE-based
Post-quantum Cryptography . . . . . . . 45:1--45:??
Hyegang Jun and
Hanchen Ye and
Hyunmin Jeong and
Deming Chen AutoScaleDSE: a Scalable Design Space
Exploration Engine for High-Level
Synthesis . . . . . . . . . . . . . . . 46:1--46:??
Liang Chang and
Xin Zhao and
Jun Zhou ADAS: a High Computational Utilization
Dynamic Reconfigurable Hardware
Accelerator for Super Resolution . . . . 47:1--47:??
Christian Skubich and
Peter Reichel and
Marc Reichenbach Increasing the Robustness of TERO-TRNGs
Against Process Variation . . . . . . . 48:1--48:??
Nicolai Fiege and
Peter Zipf BLOOP: Boolean Satisfiability-based
Optimized Loop Pipelining . . . . . . . 49:1--49:??
Aman Arora and
Atharva Bhamburkar and
Aatman Borda and
Tanmay Anand and
Rishabh Sehgal and
Bagus Hanindhito and
Pierre-Emmanuel Gaillardon and
Jaydeep Kulkarni and
Lizy K. John CoMeFa: Deploying Compute-in-Memory on
FPGAs for Deep Learning Acceleration . . 50:1--50:??
Jing Li and
Martin Herbordt Introduction to the Special Section on
FCCM 2022 . . . . . . . . . . . . . . . 51:1--51:??
Guiming Wu and
Qianwen He and
Jiali Jiang and
Zhenxiang Zhang and
Yuan Zhao and
Yinchao Zou and
Jie Zhang and
Changzheng Wei and
Ying Yan and
Hui Zhang Topgun: an ECC Accelerator for Private
Set Intersection . . . . . . . . . . . . 52:1--52:??
Tiancheng Xu and
Scott Rixner and
Alan L. Cox An FPGA Accelerator for Genome Variant
Calling . . . . . . . . . . . . . . . . 53:1--53:??
Lana Josipovi\'c and
Axel Marmet and
Andrea Guerrieri and
Paolo Ienne Resource Sharing in Dataflow Circuits 54:1--54:??
Jianyi Cheng and
Lana Josipovi\'c and
John Wickerson and
George A. Constantinides Parallelising Control Flow in
Dynamic-scheduling High-level Synthesis 55:1--55:??
Paolo Ienne Introduction to the Special Section on
FPGA 2022 . . . . . . . . . . . . . . . 56:1--56:??
Erwei Wang and
Marie Auffret and
Georgios-Ilias Stavrou and
Peter Y. K. Cheung and
George A. Constantinides and
Mohamed S. Abdelfattah and
James J. Davis Logic Shrinkage: Learned Connectivity
Sparsification for LUT-Based Neural
Networks . . . . . . . . . . . . . . . . 57:1--57:??
Yizhao Gao and
Song Wang and
Hayden Kwok-Hay So A Reconfigurable Architecture for
Real-time Event-based Multi-Object
Tracking . . . . . . . . . . . . . . . . 58:1--58:??
Licheng Guo and
Pongstorn Maidee and
Yun Zhou and
Chris Lavin and
Eddie Hung and
Wuxi Li and
Jason Lau and
Weikang Qiao and
Yuze Chi and
Linghao Song and
Yuanlong Xiao and
Alireza Kaviani and
Zhiru Zhang and
Jason Cong RapidStream 2.0: Automated Parallel
Implementation of Latency-Insensitive
FPGA Designs Through Partial
Reconfiguration . . . . . . . . . . . . 59:1--59:??
Anouar Nechi and
Lukas Groth and
Saleh Mulhem and
Farhad Merchant and
Rainer Buchty and
Mladen Berekovic FPGA-based Deep Learning Inference
Accelerators: Where Are We Standing? . . 60:1--60:??
Marcos T. Leipnitz and
Gabriel L. Nazar Constraint-Aware Multi-Technique
Approximate High-Level Synthesis for
FPGAs . . . . . . . . . . . . . . . . . 61:1--61:??
Kenneth Liu and
Alec Lu and
Kartik Samtani and
Zhenman Fang and
Licheng Guo CHIP-KNNv2: a Configurable and
High-Performance $K$-Nearest Neighbors
Accelerator on HBM-based FPGAs . . . . . 62:1--62:??
Licheng Guo and
Yuze Chi and
Jason Lau and
Linghao Song and
Xingyu Tian and
Moazin Khatti and
Weikang Qiao and
Jie Wang and
Ecenur Ustun and
Zhenman Fang and
Zhiru Zhang and
Jason Cong TAPA: a Scalable Task-parallel Dataflow
Programming Framework for Modern FPGAs
with Co-optimization of HLS and Physical
Design . . . . . . . . . . . . . . . . . 63:1--63:??
Yingchun Lu and
Yun Yang and
Rong Hu and
Huaguo Liang and
Maoxiang Yi and
Huang Zhengfeng and
Yuanming Ma and
Tian Chen and
Liang Yao High-efficiency TRNG Design Based on
Multi-bit Dual-ring Oscillator . . . . . 64:1--64:??
Anupreetham Anupreetham and
Mohamed Ibrahim and
Mathew Hall and
Andrew Boutros and
Ajay Kuzhively and
Abinash Mohanty and
Eriko Nurvitadhi and
Vaughn Betz and
Yu Cao and
Jae-Sun Seo High Throughput FPGA-Based Object
Detection via Algorithm-Hardware
Co-Design . . . . . . . . . . . . . . . 1:1--1:??
Zimeng Fan and
Wei Hu and
Fang Liu and
Dian Xu and
Hong Guo and
Yanxiang He and
Min Peng A Hardware Design Framework for Computer
Vision Models Based on Reconfigurable
Devices . . . . . . . . . . . . . . . . 2:1--2:??
Fabio Maschi and
Gustavo Alonso Strega: an HTTP Server for FPGAs . . . . 3:1--3:??
Yunhui Qiu and
Yiqing Mao and
Xuchen Gao and
Sichao Chen and
Jiangnan Li and
Wenbo Yin and
Lingli Wang FDRA: a Framework for a Dynamically
Reconfigurable Accelerator Supporting
Multi-Level Parallelism . . . . . . . . 4:1--4:??
John Kalomiros and
John Vourvoulakis and
Stavros Vologiannidis A Hardware Accelerator for the
Semi-Global Matching Stereo Algorithm:
an Efficient Implementation for the
Stratix V and Zynq UltraScale+ FPGA
Technology . . . . . . . . . . . . . . . 5:1--5:??
Miguel Reis and
Mário Véstias and
Horácio Neto Designing Deep Learning Models on FPGA
with Multiple Heterogeneous Engines . . 6:1--6:??
Rafael Fão De Moura and
Luigi Carro Reprogrammable Non-Linear Circuits Using
ReRAM for NN Accelerators . . . . . . . 7:1--7:??
Alexandre Honorat and
Mickaël Dardaillon and
Hugo Miomandre and
Jean-François Nezan Automated Buffer Sizing of Dataflow
Applications in a High-level Synthesis
Workflow . . . . . . . . . . . . . . . . 8:1--8:??
Louis Noyez and
Nadia El Mrabet and
Olivier Potin and
Pascal Veron Montgomery Multiplication Scalable
Systolic Designs Optimized for DSP48E2 9:1--9:??
Parastoo Soleimani and
David W. Capson and
Kin Fun Li A Partitioned CAM Architecture with FPGA
Acceleration for Binary Descriptor
Matching . . . . . . . . . . . . . . . . 10:1--10:??
Olivia Weng and
Gabriel Marcano and
Vladimir Loncar and
Alireza Khodamoradi and
Abarajithan G. and
Nojan Sheybani and
Andres Meza and
Farinaz Koushanfar and
Kristof Denolf and
Javier Mauricio Duarte and
Ryan Kastner Tailor: Altering Skip Connections for
Resource-Efficient Inference . . . . . . 11:1--11:??
Jennifer Hasler and
Cong Hao Programmable Analog System Benchmarks
Leading to Efficient Analog Computation
Synthesis . . . . . . . . . . . . . . . 12:1--12:??
Diana Göhringer and
Georgios Keramidas and
Akash Kumar Introduction to the FPL 2021 Special
Section . . . . . . . . . . . . . . . . 13:1--13:??
Stefan Nikoli\'c and
Paolo Ienne Exploring FPGA Switch-Blocks without
Explicitly Listing Connectivity Patterns 14:1--14:??
Zhengyan Liu and
Qiang Liu and
Shun Yan and
Ray C. C. Cheung An Efficient FPGA-based Depthwise
Separable Convolutional Neural Network
Accelerator with Hardware Pruning . . . 15:1--15:??
Jeffrey Chen and
Sang-Woo Jun and
Sehwan Hong and
Warrick He and
Jinyeong Moon Eciton: Very Low-power Recurrent Neural
Network Accelerator for Real-time
Inference at the Edge . . . . . . . . . 16:1--16:??
Sajjad Rostami Sani and
Andy Ye Evaluating the Impact of Using
Multiple-Metal Layers on the Layout Area
of Switch Blocks for Tile-Based FPGAs in
FinFET 7nm . . . . . . . . . . . . . . . 17:1--17:??
Yonggen Li and
Xin Li and
Haibin Shen and
Jicong Fan and
Yanfeng Xu and
Kejie Huang An All-digital Compute-in-memory FPGA
Architecture for Deep Learning
Acceleration . . . . . . . . . . . . . . 18:1--18:??