Table of contents for issues of ACM Transactions on Reconfigurable Technology and Systems (TRETS)

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Volume 1, Number 1, March, 2008
Volume 1, Number 2, June, 2008
Volume 1, Number 3, September, 2008
Volume 1, Number 4, January, 2009
Volume 2, Number 1, March, 2009
Volume 2, Number 2, June, 2009
Volume 2, Number 3, September, 2009
Volume 2, Number 4, September, 2009
Volume 3, Number 1, January, 2010
Volume 3, Number 2, May, 2010
Volume 3, Number 3, September, 2010
Volume 3, Number 4, November, 2010
Volume 4, Number 1, December, 2010
Volume 4, Number 2, May, 2011
Volume 4, Number 3, August, 2011
Volume 4, Number 4, December, 2011
Volume 5, Number 1, March, 2012
Volume 5, Number 2, June, 2012
Volume 5, Number 3, October, 2012
Volume 5, Number 4, December, 2012
Volume 6, Number 1, May, 2013
Volume 6, Number 2, July, 2013
Volume 6, Number 3, October, 2013
Volume 6, Number 4, December, 2013
Volume 7, Number 1, February, 2014
Volume 7, Number 2, June, 2014
Volume 7, Number 3, August, 2014
Volume 7, Number 4, January, 2015
Volume 8, Number 1, February, 2015
Volume 8, Number 2, April, 2015
Volume 8, Number 3, May, 2015
Volume 8, Number 4, October, 2015
Volume 9, Number 1, November, 2015
Volume 9, Number 2, February, 2016
Volume 9, Number 3, July, 2016
Volume 9, Number 4, September, 2016
Volume 10, Number 1, December, 2016
Volume 10, Number 2, April, 2017
Volume 10, Number 3, July, 2017
Volume 10, Number 4, December, 2017


ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 1, Number 1, March, 2008

               Duncan Buell and   
                      Wayne Luk   Introduction . . . . . . . . . . . . . . 1:1--1:??
         André DeHon and   
                    Mike Hutton   Guest Editorial: TRETS Special Edition
                                  on the 15th International Symposium on
                                  FPGAs  . . . . . . . . . . . . . . . . . 2:1--2:??
            Yohei Matsumoto and   
             Masakazu Hioki and   
           Takashi Kawanami and   
               Hanpei Koike and   
         Toshiyuki Tsutsumi and   
           Tadashi Nakagawa and   
             Toshihiro Sekigawa   Suppression of Intrinsic Delay Variation
                                  in FPGAs using Multiple Configurations   3:1--3:??
           Satish Sivaswamy and   
                   Kia Bazargan   Statistical Analysis and Process
                                  Variation-Aware Routing and Skew
                                  Assignment for FPGAs . . . . . . . . . . 4:1--4:??
            Shih-Lien L. Lu and   
         Peter Yiannacouras and   
                Taeweon Suh and   
                 Rolf Kassa and   
                  Michael Konow   A Desktop Computer with a Reconfigurable
                                  Pentium\reg  . . . . . . . . . . . . . . 5:1--5:??
                 Wenyi Feng and   
               Sinan Kaptanoglu   Designing Efficient Input Interconnect
                                  Blocks for LUT Clusters Using Counting
                                  and Entropy  . . . . . . . . . . . . . . 6:1--6:??
        Steven J. E. Wilton and   
                Chun Hok Ho and   
            Bradley Quinton and   
         Philip H. W. Leong and   
                      Wayne Luk   A Synthesizable Datapath-Oriented
                                  Embedded FPGA Fabric for Silicon Debug
                                  Applications . . . . . . . . . . . . . . 7:1--7:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 1, Number 2, June, 2008

           Tim Güneysu and   
              Christof Paar and   
                      Jan Pelzl   Special-Purpose Hardware for Solving the
                                  Elliptic Curve Discrete Logarithm
                                  Problem  . . . . . . . . . . . . . . . . 8:1--8:??
               Arpith Jacob and   
           Joseph Lancaster and   
              Jeremy Buhler and   
             Brandon Harris and   
           Roger D. Chamberlain   Mercury BLASTP: Accelerating Protein
                                  Sequence Alignment . . . . . . . . . . . 9:1--9:??
               Pete Sedcole and   
             Peter Y. K. Cheung   Parametric Yield Modeling and
                                  Simulations of FPGA Circuits Considering
                                  Within-Die Delay Variations  . . . . . . 10:1--10:??
              Bita Gorjiara and   
            Mehrdad Reshadi and   
                  Daniel Gajski   Merged Dictionary Code Compression for
                                  FPGA Implementation of Custom Microcoded
                                  PEs  . . . . . . . . . . . . . . . . . . 11:1--11:??
            David B. Thomas and   
                      Wayne Luk   Multivariate Gaussian Random Number
                                  Generation Targeting Reconfigurable
                                  Hardware . . . . . . . . . . . . . . . . 12:1--12:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 1, Number 3, September, 2008

           Julien Lamoureux and   
            Steven J. E. Wilton   On the trade-off between power and
                                  flexibility of FPGA clock networks . . . 13:1--13:??
             David Slogsnat and   
            Alexander Giese and   
       Mondrian Nüssle and   
            Ulrich Brüning   An open-source HyperTransport core . . . 14:1--14:??
           John S. Beeckler and   
                Warren J. Gross   Particle graphics on reconfigurable
                                  hardware . . . . . . . . . . . . . . . . 15:1--15:??
                David Grant and   
                    Guy Lemieux   Perturb $+$ mutate: Semisynthetic
                                  circuit generation for incremental
                                  placement and routing  . . . . . . . . . 16:1--16:??
             Pao-Ann Hsiung and   
             Chao-Sheng Lin and   
                 Chih-Feng Liao   Perfecto: a SystemC-based design-space
                                  exploration framework for dynamically
                                  reconfigurable architectures . . . . . . 17:1--17:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 1, Number 4, January, 2009

           Scott Y. L. Chin and   
            Steven J. E. Wilton   Static and Dynamic Memory Footprint
                                  Reduction for FPGA Routing Algorithms    18:1--18:??
                 Ning-Yi Xu and   
              Xiong-Fei Cai and   
                    Rui Gao and   
                  Lei Zhang and   
                Feng-Hsiung Hsu   FPGA Acceleration of RankBoost in Web
                                  Search Engines . . . . . . . . . . . . . 19:1--19:??
            C. D. Patterson and   
            S. W. Ellingson and   
               B. S. Martin and   
               K. Deshpande and   
            J. H. Simonetti and   
                   M. Kavic and   
                  S. E. Cutchin   Searching for Transient Pulses with the
                                  ETA Radio Telescope  . . . . . . . . . . 20:1--20:??
              Esam El-Araby and   
              Ivan Gonzalez and   
               Tarek El-Ghazawi   Exploiting Partial Runtime
                                  Reconfiguration for High-Performance
                                  Reconfigurable Computing . . . . . . . . 21:1--21:??
              Brian Holland and   
          Karthik Nagarajan and   
                 Alan D. George   RAT: RC Amenability Test for Rapid
                                  Performance Prediction . . . . . . . . . 22:1--22:??
                 S. Murtaza and   
             A. G. Hoekstra and   
                 P. M. A. Sloot   Compute Bound and I/O Bound Cellular
                                  Automata Simulations on FPGA Logic . . . 23:1--23:??
       Christos-S. Bouganis and   
             Sung-Boem Park and   
   George A. Constantinides and   
             Peter Y. K. Cheung   Synthesis and Optimization of $2$D
                                  Filter Designs for Heterogeneous FPGAs   24:1--24:??


ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 2, Number 1, March, 2009

       Patrick R. Schaumont and   
              Alex K. Jones and   
               Steve Trimberger   Guest Editors' Introduction to Security
                                  in Reconfigurable Systems Design . . . . 1:1--1:??
             Maurice Keller and   
               Andrew Byrne and   
             William P. Marnane   Elliptic Curve Cryptography on FPGA for
                                  Low-Power Applications . . . . . . . . . 2:1--2:??
           Robert P. McEvoy and   
            Colin C. Murphy and   
         William P. Marnane and   
               Michael Tunstall   Isolated WDDL: a Hiding Countermeasure
                                  for Differential Power Analysis on FPGAs 3:1--3:??
            Laurent Sauvage and   
            Sylvain Guilley and   
                   Yves Mathieu   Electromagnetic Radiations of FPGAs:
                                  High Spatial Resolution Cartography and
                                  Attack on a Cryptographic Module . . . . 4:1--4:??
           Mehrdad Majzoobi and   
         Farinaz Koushanfar and   
              Miodrag Potkonjak   Techniques for Design and Implementation
                                  of Secure Reconfigurable PUFs  . . . . . 5:1--5:??
              Shantanu Dutt and   
                          Li Li   Trust-Based Design and Check of FPGA
                                  Circuits Using Two-Level Randomized ECC
                                  Structures . . . . . . . . . . . . . . . 6:1--6:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 2, Number 2, June, 2009

             Hideharu Amano and   
                 Tadao Nakamura   Guest editors' introduction: ICFPT 2007  7:1--7:??
              Weisheng Zhao and   
              Eric Belhaire and   
            Claude Chappert and   
              Bernard Dieny and   
               Guillaume Prenat   TAS-MRAM-Based Low-Power High-Speed
                                  Runtime Reconfiguration (RTR) FPGA . . . 8:1--8:??
                  Dirk Koch and   
         Christian Beckhoff and   
              Jürgen Teich   Hardware Decompression Techniques for
                                  FPGA-Based Embedded Systems  . . . . . . 9:1--9:??
          Justin S. J. Wong and   
               Pete Sedcole and   
             Peter Y. K. Cheung   Self-Measurement of Combinatorial
                                  Circuit Delays in FPGAs  . . . . . . . . 10:1--10:??
             G. Seetharaman and   
               B. Venkataramani   Automation Schemes for FPGA
                                  Implementation of Wave-Pipelined
                                  Circuits . . . . . . . . . . . . . . . . 11:1--11:??
                   Jason Yu and   
      Christopher Eagleston and   
    Christopher Han-Yu Chou and   
           Maxime Perreault and   
                    Guy Lemieux   Vector Processing as a Soft Processor
                                  Accelerator  . . . . . . . . . . . . . . 12:1--12:??
         Alessandro Cevrero and   
  Panagiotis Athanasopoulos and   
       Hadi Parandeh-Afshar and   
              Ajay K. Verma and   
Hosein Seyed Attarzadeh Niaki and   
    Chrysostomos Nicopoulos and   
         Frank K. Gurkaynak and   
               Philip Brisk and   
            Yusuf Leblebici and   
                    Paolo Ienne   Field Programmable Compressor Trees:
                                  Acceleration of Multi-Input Addition on
                                  FPGAs  . . . . . . . . . . . . . . . . . 13:1--13:??
               Stephen Jang and   
                 Billy Chan and   
                Kevin Chung and   
                Alan Mishchenko   WireMap: FPGA Technology Mapping for
                                  Improved Routability and Enhanced LUT
                                  Merging  . . . . . . . . . . . . . . . . 14:1--14:??
              Eric S. Chung and   
     Michael K. Papamichael and   
           Eriko Nurvitadhi and   
               James C. Hoe and   
                    Ken Mai and   
                  Babak Falsafi   ProtoFlex: Towards Scalable, Full-System
                                  Multiprocessor Simulations Using FPGAs   15:1--15:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 2, Number 3, September, 2009

           Michael Pellauer and   
 Muralidaran Vijayaraghavan and   
              Michael Adler and   
                     Arvind and   
                      Joel Emer   A-Port Networks: Preserving the Timed
                                  Behavior of Synchronous Systems for
                                  Modeling on FPGAs  . . . . . . . . . . . 16:1--16:??
                 Jason Cong and   
                         Yi Zou   FPGA-Based Hardware Acceleration of
                                  Lithographic Aerial Image Simulation . . 17:1--17:??
               Taneem Ahmed and   
        Paul D. Kundarewich and   
              Jason H. Anderson   Packing Techniques for Virtex-5 FPGAs    18:1--18:??
       Hadi Parandeh-Afshar and   
               Philip Brisk and   
                    Paolo Ienne   An FPGA Logic Cell and Carry Chain
                                  Configurable as a 6:2 or 7:2 Compressor  19:1--19:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 2, Number 4, September, 2009

          Katherine Compton and   
                Roger Woods and   
          Christos Bouganis and   
                    Pedro Diniz   Introduction to the Special Issue ARC'08 20:1--20:??
                  Qiwei Jin and   
            David B. Thomas and   
                  Wayne Luk and   
                  Benjamin Cope   Exploring Reconfigurable Architectures
                                  for Tree-Based Option Pricing Models . . 21:1--21:??
      Maria E. Angelopoulou and   
   Christos-Savvas Bouganis and   
         Peter Y. K. Cheung and   
       George A. Constantinides   Robust Real-Time Super-Resolution on
                                  FPGA and an Application to Video
                                  Enhancement  . . . . . . . . . . . . . . 22:1--22:??
           Chia-Tien Dan Lo and   
                    Yi-Gang Tai   Space Optimization on Counters for
                                  FPGA-Based Perl Compatible Regular
                                  Expressions  . . . . . . . . . . . . . . 23:1--23:??
       Nikolaos Vassiliadis and   
         George Theodoridis and   
            Spiridon Nikolaidis   An Application Development Framework for
                                  ARISE Reconfigurable Processors  . . . . 24:1--24:??
      Ozana Silvia Dragomir and   
             Todor Stefanov and   
                   Koen Bertels   Optimal Loop Unrolling and Shifting for
                                  Reconfigurable Architectures . . . . . . 25:1--25:??
         Keith D. Underwood and   
           K. Scott Hemmert and   
                 Craig D. Ulmer   From Silicon to Science: The Long Road
                                  to Production Reconfigurable
                                  Supercomputing . . . . . . . . . . . . . 26:1--26:??


ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 3, Number 1, January, 2010

             Antonio Roldao and   
       George A. Constantinides   A High Throughput FPGA-Based Floating
                                  Point Conjugate Gradient Implementation
                                  for Dense Matrices . . . . . . . . . . . 1:1--1:??
               David Dubois and   
              Andrew Dubois and   
             Thomas Boorman and   
             Carolyn Connor and   
                    Steve Poole   Sparse Matrix-Vector Multiplication on a
                                  Reconfigurable Supercomputer with
                                  Application  . . . . . . . . . . . . . . 2:1--2:??
                Saar Drimer and   
           Tim Güneysu and   
                  Christof Paar   DSPs, BRAMs, and a Pinch of Logic:
                                  Extended Recipes for AES on FPGAs  . . . 3:1--3:??
                Shannon Koh and   
                 Oliver Diessel   Configuration Merging in Point-to-Point
                                  Networks for Module-Based FPGA
                                  Reconfiguration  . . . . . . . . . . . . 4:1--4:??
               John Curreri and   
               Seth Koehler and   
             Alan D. George and   
              Brian Holland and   
                  Rafael Garcia   Performance Analysis Framework for
                                  High-Level Language Applications in
                                  Reconfigurable Computing . . . . . . . . 5:1--5:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 3, Number 2, May, 2010

                John Bodily and   
               Brent Nelson and   
                 Zhaoyi Wei and   
                Dah-Jye Lee and   
                     Jeff Chase   A Comparison Study on Implementing
                                  Optical Flow and Digital Communications
                                  on FPGAs and GPUs  . . . . . . . . . . . 6:1--6:??
  Konstantinos Papadopoulos and   
         Ioannis Papaefstathiou   Titan-R: a Multigigabit Reconfigurable
                                  Combined Compression/Decompression Unit  7:1--7:??
       Beno\^\it Badrignans and   
            David Champagne and   
              Reouven Elbaz and   
          Catherine Gebotys and   
                  Lionel Torres   SARFUM: Security Architecture for Remote
                                  FPGA Update and Monitoring . . . . . . . 8:1--8:??
             Sang-Kyung Yoo and   
          Deniz Karakoyunlu and   
                Berk Birand and   
                     Berk Sunar   Improving the Robustness of Ring
                                  Oscillator TRNGs . . . . . . . . . . . . 9:1--9:??
               Ted Huffmire and   
              Timothy Levin and   
                Thuy Nguyen and   
             Cynthia Irvine and   
           Brett Brotherton and   
                  Gang Wang and   
           Timothy Sherwood and   
                   Ryan Kastner   Security Primitives for Reconfigurable
                                  Hardware-Based Systems . . . . . . . . . 10:1--10:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 3, Number 3, September, 2010

           K. Scott Hemmert and   
             Keith D. Underwood   Fast, Efficient Floating-Point Adders
                                  and Multipliers for FPGAs  . . . . . . . 11:1--11:??
              Ahmad Sghaier and   
              Shawki Areibi and   
                    Robert Dony   Implementation Approaches Trade-Offs for
                                  WiMax OFDM Functions on Reconfigurable
                                  Platforms  . . . . . . . . . . . . . . . 12:1--12:??
          Alastair M. Smith and   
   George A. Constantinides and   
             Peter Y. K. Cheung   An Automated Flow for Arithmetic
                                  Component Generation in
                                  Field-Programmable Gate Arrays . . . . . 13:1--13:??
              James Moscola and   
              Ron K. Cytron and   
                   Young H. Cho   Hardware-Accelerated RNA
                                  Secondary-Structure Alignment  . . . . . 14:1--14:??
             Yosi Ben-Asher and   
              Danny Meisler and   
                    Nadav Rotem   Reducing Memory Constraints in Modulo
                                  Scheduling Synthesis for FPGAs . . . . . 15:1--15:??
               Xiaojun Wang and   
                  Miriam Leeser   VFloat: a Variable Precision Fixed- and
                                  Floating-Point Library for
                                  Reconfigurable Hardware  . . . . . . . . 16:1--16:??
        Madhura Purnaprajna and   
             Mario Porrmann and   
            Ulrich Rueckert and   
           Michael Hussmann and   
              Michael Thies and   
                    Uwe Kastens   Runtime Reconfiguration of
                                  Multiprocessors Based on Compile-Time
                                  Analysis . . . . . . . . . . . . . . . . 17:1--17:??
         Sudarshan Banerjee and   
         Elaheh Bozorgzadeh and   
             Juanjo Noguera and   
                     Nikil Dutt   Bandwidth Management in Application
                                  Mapping for Dynamically Reconfigurable
                                  Architectures  . . . . . . . . . . . . . 18:1--18:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 3, Number 4, November, 2010

             Jason Williams and   
               Chris Massie and   
             Alan D. George and   
          Justin Richardson and   
              Kunal Gosrani and   
                     Herman Lam   Characterization of Fixed and
                                  Reconfigurable Multi-Core Devices for
                                  Application Acceleration . . . . . . . . 19:1--19:??
             Miaoqing Huang and   
         Vikram K. Narayana and   
             Harald Simmler and   
             Olivier Serres and   
               Tarek El-Ghazawi   Reconfiguration and Communication-Aware
                                  Task Scheduling for High-Performance
                                  Reconfigurable Computing . . . . . . . . 20:1--20:??
               Kentaro Sano and   
                Wang Luzhou and   
           Yoshiaki Hatsuda and   
            Takanori Iizuka and   
                Satoru Yamamoto   FPGA-Array with Bandwidth-Reduction
                                  Mechanism for Scalable and
                                  Power-Efficient Numerical Simulations
                                  Based on Finite Difference Methods . . . 21:1--21:??
      Manuel Saldaña and   
                 Arun Patel and   
         Christopher Madill and   
               Daniel Nunes and   
                Danyao Wang and   
                  Paul Chow and   
               Ralph Wittig and   
               Henry Styles and   
                  Andrew Putnam   MPI as a Programming Model for
                                  High-Performance Reconfigurable
                                  Computers  . . . . . . . . . . . . . . . 22:1--22:??
                  Matt Chiu and   
             Martin C. Herbordt   Molecular Dynamics Simulations on
                                  High-Performance Reconfigurable
                                  Computing Systems  . . . . . . . . . . . 23:1--23:??
            Alessio Montone and   
      Marco D. Santambrogio and   
           Donatella Sciuto and   
             Seda Ogrenci Memik   Placement and Floorplanning in
                                  Dynamically Reconfigurable FPGAs . . . . 24:1--24:??
              Casey Reardon and   
              Eric Grobelny and   
             Alan D. George and   
                    Gongyu Wang   A Simulation Framework for Rapid
                                  Analysis of Reconfigurable Computing
                                  Systems  . . . . . . . . . . . . . . . . 25:1--25:??
                 Xiang Tian and   
                 Khaled Benkrid   High-Performance Quasi-Monte Carlo
                                  Financial Simulation: FPGA vs. GPP vs.
                                  GPU  . . . . . . . . . . . . . . . . . . 26:1--26:??


ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 4, Number 1, December, 2010

                Roger Woods and   
         Jürgen Becker and   
              Peter Athanas and   
                Fearghal Morgan   Guest Editorial ARC 2009 . . . . . . . . 1:1--1:??
      Chalermpol Saiprasert and   
       Christos-S. Bouganis and   
       George A. Constantinides   An Optimized Hardware Architecture of a
                                  Multivariate Gaussian Random Number
                                  Generator  . . . . . . . . . . . . . . . 2:1--2:??
                Asma Kahoul and   
          Alastair M. Smith and   
   George A. Constantinides and   
             Peter Y. K. Cheung   Efficient Heterogeneous Architecture
                                  Floorplan Optimization using Analytical
                                  Methods  . . . . . . . . . . . . . . . . 3:1--3:??
                    K. Kepa and   
                  F. Morgan and   
       K. Ko\'sciuszkiewicz and   
                   L. Braun and   
             M. Hübner and   
                      J. Becker   Design Assurance Strategy and Toolset
                                  for Partially Reconfigurable FPGA
                                  Systems  . . . . . . . . . . . . . . . . 4:1--4:??
               Kazuki Inoue and   
                  Qian Zhao and   
           Yasuhiro Okamoto and   
               Hiroki Yosho and   
           Motoki Amagasaki and   
              Masahiro Iida and   
             Toshinori Sueyoshi   A Variable-Grain Logic Cell and Routing
                                  Architecture for a Reconfigurable IP
                                  Core . . . . . . . . . . . . . . . . . . 5:1--5:??
                     Xu Guo and   
              Patrick Schaumont   Optimized System-on-Chip Integration of
                                  a Programmable ECC Coprocessor . . . . . 6:1--6:??
                  Luca Sterpone   A New Timing Driven Placement Algorithm
                                  for Dependable Circuits on SRAM-based
                                  FPGAs  . . . . . . . . . . . . . . . . . 7:1--7:??
                 M. Lanuzza and   
                  P. Zicari and   
                F. Frustaci and   
                   S. Perri and   
                  P. Corsonello   Exploiting Self-Reconfiguration
                                  Capability to Improve SRAM-based FPGA
                                  Robustness in Space and Avionics
                                  Applications . . . . . . . . . . . . . . 8:1--8:??
             Pao-Ann Hsiung and   
           Chun-Hsian Huang and   
             Jih-Sheng Shen and   
                Chen-Chi Chiang   Scheduling and Placement of
                                  Hardware/Software Real-Time Relocatable
                                  Tasks in Dynamically Partially
                                  Reconfigurable Systems . . . . . . . . . 9:1--9:??
             Kenji Kanazawa and   
               Tsutomu Maruyama   An Approach for Solving Large SAT
                                  Problems on FPGA . . . . . . . . . . . . 10:1--10:??
                  Yingxi Lu and   
              Maire O'Neill and   
                   John McCanny   Evaluation of Random Delay Insertion
                                  against DPA on FPGAs . . . . . . . . . . 11:1--11:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 4, Number 2, May, 2011

           Etienne Bergeron and   
         Louis-David Perron and   
                Marc Feeley and   
              Jean Pierre David   Logarithmic-Time FPGA Bitstream
                                  Analysis: a Step Towards JIT Hardware
                                  Compilation  . . . . . . . . . . . . . . 12:1--12:??
              Pranav Vaidya and   
               Jaehwan John Lee   A Novel Multicontext Coarse-Grained
                                  Reconfigurable Architecture (CGRA) For
                                  Accelerating Column-Oriented Databases   13:1--13:??
              Shane O'Neill and   
        Roger Francis Woods and   
        Alan James Marshall and   
                       Qi Zhang   A Scalable and Programmable Modular
                                  Traffic Manager Architecture . . . . . . 14:1--14:??
               Mao Nakajima and   
                Minoru Watanabe   Fast Optical Reconfiguration of a
                                  Nine-Context DORGA Using a Speed
                                  Adjustment Control . . . . . . . . . . . 15:1--15:??
             Tzu-Chiang Tai and   
                    Yen-Tai Lai   A Performance-Oriented Algorithm with
                                  Consideration on Communication Cost for
                                  Dynamically Reconfigurable FPGA
                                  Partitioning . . . . . . . . . . . . . . 16:1--16:??
            Melina Demertzi and   
             Pedro C. Diniz and   
               Mary W. Hall and   
            Anna C. Gilbert and   
                        Yi Wang   Domain-Specific Optimization of Signal
                                  Recognition Targeting FPGAs  . . . . . . 17:1--17:??
              Carlo Galuzzi and   
                   Koen Bertels   The Instruction-Set Extension Problem: a
                                  Survey . . . . . . . . . . . . . . . . . 18:1--18:28
                Kyle Rupnow and   
         Keith D. Underwood and   
              Katherine Compton   Scientific Application Demands on a
                                  Reconfigurable Functional Unit Interface 19:1--19:??
          Alexander Kaganov and   
               Asif Lakhany and   
                      Paul Chow   FPGA Acceleration of MultiFactor CDO
                                  Pricing  . . . . . . . . . . . . . . . . 20:1--20:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 4, Number 3, August, 2011

           Martin Labrecque and   
            Mark C. Jeffrey and   
             J. Gregory Steffan   Application-specific signatures for
                                  transactional memory in soft processors  21:1--21:??
               David Boland and   
       George A. Constantinides   Optimizing memory bandwidth use and
                                  performance for matrix-vector
                                  multiplication in iterative methods  . . 22:1--22:??
              Johann Glaser and   
                Markus Damm and   
                  Jan Haase and   
                Christoph Grimm   TR-FSM: Transition-Based reconfigurable
                                  finite state machine . . . . . . . . . . 23:1--23:??
              Husain Parvez and   
             Zied Marrakchi and   
                  Alp Kilic and   
                   Habib Mehrez   Application-Specific FPGA using
                                  heterogeneous logic blocks . . . . . . . 24:1--24:??
                   Jing Yan and   
                 Ning-Yi Xu and   
              Xiong-Fei Cai and   
                    Rui Gao and   
                    Yu Wang and   
                   Rong Luo and   
                Feng-Hsiung Hsu   An FPGA-based accelerator for LambdaRank
                                  in Web search engines  . . . . . . . . . 25:1--25:??
             Vikas Aggarwal and   
             Alan D. George and   
               Changil Yoon and   
       Kishore Yalamanchili and   
                     Herman Lam   SHMEM+: a multilevel-PGAS programming
                                  model for reconfigurable supercomputing  26:1--26:??
              Brian Holland and   
             Alan D. George and   
                 Herman Lam and   
               Melissa C. Smith   An analytical model for multilevel
                                  performance prediction of Multi-FPGA
                                  systems  . . . . . . . . . . . . . . . . 27:1--27:??
             Lesley Shannon and   
                      Paul Chow   Leveraging reconfigurability in the
                                  hardware/software codesign process . . . 28:1--28:??
              Federico Nava and   
           Donatella Sciuto and   
Marco Domenico Santambrogio and   
     Stefan Herbrechtsmeier and   
             Mario Porrmann and   
              Ulf Witkowski and   
                Ulrich Rueckert   Applying dynamic reconfiguration in the
                                  mobile robotics domain: a case study on
                                  computer vision algorithms . . . . . . . 29:1--29:??
               Seth Koehler and   
                 Greg Stitt and   
                 Alan D. George   Platform-aware bottleneck detection for
                                  reconfigurable computing applications    30:1--30:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 4, Number 4, December, 2011

             Peter Y. K. Cheung   Introduction to special section FPGA
                                  2009 . . . . . . . . . . . . . . . . . . 31:1--31:??
                  Jason Luu and   
                   Ian Kuon and   
             Peter Jamieson and   
               Ted Campbell and   
                    Andy Ye and   
              Wei Mark Fang and   
               Kenneth Kent and   
                  Jonathan Rose   VPR 5.0: FPGA CAD and architecture
                                  exploration tools with single-driver
                                  routing, heterogeneity and process
                                  scaling  . . . . . . . . . . . . . . . . 32:1--32:??
              Raphael Rubin and   
             André Dehon   Choose-your-own-adventure routing:
                                  Lightweight load-time defect avoidance   33:1--33:??
            Alan Mishchenko and   
             Robert Brayton and   
          Jie-Hong R. Jiang and   
                   Stephen Jang   Scalable don't-care-based logic
                                  optimization and resynthesis . . . . . . 34:1--34:??
            Andrew Kennings and   
          Kristofer Vorwerk and   
                 Arun Kundu and   
                Val Pevzner and   
                       Andy Fox   FPGA technology mapping with encoded
                                  libraries and staged priority cuts . . . 35:1--35:??
    Kyprianos Papadimitriou and   
           Apostolos Dollas and   
                    Scott Hauck   Performance of partial reconfiguration
                                  in FPGA systems: a survey and a cost
                                  model  . . . . . . . . . . . . . . . . . 36:1--36:??
              Xiaoheng Chen and   
               Venkatesh Akella   Exploiting data-level parallelism for
                                  energy-efficient implementation of LDPC
                                  decoders and DCT on an FPGA  . . . . . . 37:1--37:??
           Lakshmi Easwaran and   
                     Ali Akoglu   Net-length-based routability-driven
                                  power-aware clustering . . . . . . . . . 38:1--38:??
       Hadi Parandeh-Afshar and   
            Arkosnato Neogy and   
               Philip Brisk and   
                    Paolo Ienne   Compressor tree synthesis on commercial
                                  high-performance FPGAs . . . . . . . . . 39:1--39:??
              Hiroaki Inoue and   
               Junya Yamada and   
            Hideyuki Yoneda and   
             Katsumi Togawa and   
            Masato Motomura and   
                Koichiro Furuta   Test compression for dynamically
                                  reconfigurable processors  . . . . . . . 40:1--40:??


ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 5, Number 1, March, 2012

            Kenneth M. Zick and   
                  John P. Hayes   Low-cost sensing with ring oscillator
                                  arrays for healthier reconfigurable
                                  systems  . . . . . . . . . . . . . . . . 1:1--1:??
          Harris E. Michail and   
       George S. Athanasiou and   
         Vasilis Kelefouras and   
         George Theodoridis and   
               Costas E. Goutis   On the exploitation of a high-throughput
                                  SHA-256 FPGA design for HMAC . . . . . . 2:1--2:??
        Joaquín Olivares   Reconfigurable architecture for VBSME
                                  with variable pixel precision  . . . . . 3:1--3:??
             Kostas Siozios and   
        Vasilis F. Pavlidis and   
              Dimitrios Soudris   A novel framework for exploring $3$-D
                                  FPGAs with heterogeneous interconnect
                                  fabric . . . . . . . . . . . . . . . . . 4:1--4:??
               Shigeyuki Takano   Design and analysis of adaptive
                                  processor  . . . . . . . . . . . . . . . 5:1--5:??
                  Wei Zhang and   
                Vaughn Betz and   
                  Jonathan Rose   Portable and scalable FPGA-based
                                  acceleration of a direct linear system
                                  solver . . . . . . . . . . . . . . . . . 6:1--6:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 5, Number 2, June, 2012

             Vikas Aggarwal and   
                 Greg Stitt and   
                Alan George and   
                   Changil Yoon   SCF: a Framework for Task-Level
                                  Coordination in Reconfigurable,
                                  Heterogeneous Systems  . . . . . . . . . 7:1--7:??
    Sándor P. Fekete and   
               Tom Kamphans and   
               Nils Schweer and   
        Christopher Tessars and   
        Jan C. van der Veen and   
           Josef Angermeier and   
                  Dirk Koch and   
              Jürgen Teich   Dynamic Defragmentation of
                                  Reconfigurable Devices . . . . . . . . . 8:1--8:??
               Lerong Cheng and   
                  Wenyao Xu and   
                  Fang Gong and   
                    Yan Lin and   
                Ho-Yan Wong and   
                         Lei He   Statistical Timing and Power
                                  Optimization of Architecture and Device
                                  for FPGAs  . . . . . . . . . . . . . . . 9:1--9:??
               Kevin Martin and   
        Christophe Wolinski and   
       Krzysztof Kuchcinski and   
              Antoine Floch and   
         François Charot   Constraint Programming Approach to
                                  Reconfigurable Processor Extension
                                  Generation and Application Compilation   10:1--10:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 5, Number 3, October, 2012

            Michael Hübner   Introduction to the Special Issue on
                                  ReCoSoC 2011 . . . . . . . . . . . . . . 11:1--11:??
                John Shield and   
       Jean-Philippe Diguet and   
                    Guy Gogniat   Asymmetric Cache Coherency: Policy
                                  Modifications to Improve Multicore
                                  Performance  . . . . . . . . . . . . . . 12:1--12:??
         Benjamin Thielmann and   
              Jens Huthmann and   
                   Andreas Koch   Memory Latency Hiding by Load Value
                                  Speculation for Reconfigurable Computers 13:1--13:??
             Laurent Gantel and   
                 Amel Khiar and   
            Benoit Miramond and   
Mohamed El Amine Benkhelifa and   
              Lounis Kessal and   
          Fabrice Lemonnier and   
                  Jimmy Le Rhun   Enhancing Reconfigurable Platforms
                                  Programmability for Synchronous
                                  Data-Flow Applications . . . . . . . . . 14:1--14:??
         Angelo Kuti Lusala and   
              Jean-Didier Legat   A SDM--TDM-Based Circuit-Switched Router
                                  for On-Chip Networks . . . . . . . . . . 15:1--15:??
               Lubos Gaspar and   
             Viktor Fischer and   
             Lilian Bossuet and   
                 Robert Fouquet   Secure Extension of FPGA General Purpose
                                  Processors for Symmetric Key
                                  Cryptography with Partial
                                  Reconfiguration Capabilities . . . . . . 16:1--16:??
                Luciano Ost and   
             Sameer Varyani and   
   Leandro Soares Indrusiak and   
           Marcelo Mandelli and   
  Gabriel Marchesan Almeida and   
            Eduardo Wachter and   
            Fernando Moraes and   
              Gilles Sassatelli   Enabling Adaptive Techniques in
                                  Heterogeneous MPSoCs Based on
                                  Virtualization . . . . . . . . . . . . . 17:1--17:??
            Fearghal Morgan and   
              Seamus Cawley and   
                   David Newell   Remote FPGA Lab for Enhancing Learning
                                  of Digital Systems . . . . . . . . . . . 18:1--18:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 5, Number 4, December, 2012

                Armin Krieg and   
         Johannes Grinschgl and   
           Christian Steger and   
             Reinhold Weiss and   
                Holger Bock and   
                     Josef Haid   POWER-MODES: POWer-EmulatoR- and
                                  MOdel-Based DEpendability and Security
                                  Evaluations  . . . . . . . . . . . . . . 19:1--19:??
              Atukem Nabina and   
          Jose Luis Nunez-Yanez   Adaptive Voltage Scaling in a
                                  Dynamically Reconfigurable FPGA-Based
                                  Platform . . . . . . . . . . . . . . . . 20:1--20:??
                Adam Jacobs and   
        Grzegorz Cieslewski and   
             Alan D. George and   
            Ann Gordon-Ross and   
                     Herman Lam   Reconfigurable Fault Tolerance: a
                                  Comprehensive Framework for Reliable and
                                  Adaptive FPGA-Based Space Computing  . . 21:1--21:??
              Fabio Cancare and   
        Davide B. Bartolini and   
           Matteo Carminati and   
           Donatella Sciuto and   
          Marco D. Santambrogio   On the Evolution of Hardware Circuits
                                  via Reconfigurable Architectures . . . . 22:1--22:??


ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 6, Number 1, May, 2013

          Tarek Ould-Bachir and   
              Jean Pierre David   Self-Alignment Schemes for the
                                  Implementation of Addition-Related
                                  Floating-Point Operators . . . . . . . . 1:1--1:??
                  Yan Zhang and   
                  Fan Zhang and   
                Zheming Jin and   
                 Jason D. Bakos   An FPGA-Based Accelerator for Frequent
                                  Itemset Mining . . . . . . . . . . . . . 2:1--2:??
                Roel Meeuws and   
        S. Arash Ostadzadeh and   
              Carlo Galuzzi and   
            Vlad Mihai Sima and   
                Razvan Nane and   
                   Koen Bertels   Quipu: a Statistical Model for
                                  Predicting Hardware Resources  . . . . . 3:1--3:??
        Florent de Dinechin and   
    Pedro Echeverría and   
Marisa López-Vallejo and   
                   Bogdan Pasca   Floating-Point Exponentiation Units for
                                  Reconfigurable Computing . . . . . . . . 4:1--4:??
       Christopher E. Neely and   
             Gordon Brebner and   
                   Weijia Shang   ReShape: Towards a High-Level Approach
                                  to Design and Operation of Modular
                                  Reconfigurable Systems . . . . . . . . . 5:1--5:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 6, Number 2, July, 2013

           Diana Goehringer and   
           René Cumplido   Introduction to the special section on
                                  19th Reconfigurable Architectures
                                  Workshop (RAW 2012)  . . . . . . . . . . 6:1--6:??
         Harry Sidiropoulos and   
             Kostas Siozios and   
               Peter Figuli and   
          Dimitrios Soudris and   
        Michael Hübner and   
             Jürgen Becker   JITPR: a framework for supporting fast
                                  application's implementation onto FPGAs  7:1--7:??
              Jan Heisswolf and   
                Aurang Zaib and   
     Andreas Weichslgartner and   
            Ralf König and   
                Thomas Wild and   
          Jürgen Teich and   
        Andreas Herkersdorf and   
             Jürgen Becker   Virtual networks --- distributed
                                  communication resource management  . . . 8:1--8:??
          Thilan Ganegedara and   
                Viktor Prasanna   A comprehensive performance analysis of
                                  virtual routers on FPGA  . . . . . . . . 9:1--9:??
                 Joydip Das and   
            Steven J. E. Wilton   Towards development of an analytical
                                  model relating FPGA architecture
                                  parameters to routability  . . . . . . . 10:1--10:??
           Chun-Hsian Huang and   
                 Pao-Ann Hsiung   Virtualizable hardware/software design
                                  infrastructure for dynamically partially
                                  reconfigurable systems . . . . . . . . . 11:1--11:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 6, Number 3, October, 2013

                  Hanyu Liu and   
    Senthilkumar T. Rajavel and   
                     Ali Akoglu   Integration of Net-Length Factor with
                                  Timing- and Routability-Driven
                                  Clustering Algorithms  . . . . . . . . . 12:1--12:??
              Gayatri Mehta and   
            Carson Crawford and   
              Xiaozhong Luo and   
              Natalie Parde and   
          Krunalkumar Patel and   
            Brandon Rodgers and   
          Anil Kumar Sistla and   
                 Anil Yadav and   
                   Marc Reisner   UNTANGLED: a Game Environment for
                                  Discovery of Creative Mapping Strategies 13:1--13:??
             Javier Hormigo and   
          Gabriel Caffarena and   
             Juan P. Oliver and   
                  Eduardo Boemo   Self-Reconfigurable Constant Multiplier
                                  for FPGA . . . . . . . . . . . . . . . . 14:1--14:??
           Farnaz Gharibian and   
             Lesley Shannon and   
             Peter Jamieson and   
                    Kevin Chung   Analyzing System-Level Information's
                                  Correlation to FPGA Placement  . . . . . 15:1--15:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 6, Number 4, December, 2013

              Franjo Plavec and   
            Zvonko Vranesic and   
                  Stephen Brown   Exploiting Task- and Data-Level
                                  Parallelism in Streaming Applications
                                  Implemented in FPGAs . . . . . . . . . . 16:1--16:??
                T. Ananthan and   
                  M. V. Vaidyan   A Reconfigurable Parallel Hardware
                                  Implementation of the Self-Tuning
                                  Regulator  . . . . . . . . . . . . . . . 17:1--17:??
              Yoon Kah Leow and   
                 Ali Akoglu and   
                  Susan Lysecky   An Analytical Model for Evaluating
                                  Static Power of Homogeneous FPGA
                                  Architectures  . . . . . . . . . . . . . 18:1--18:??
             Yosi Ben-Asher and   
               Ron Meldiner and   
                    Nadav Rotem   Optimizing Wait States in the Synthesis
                                  of Memory References with Unpredictable
                                  Latencies  . . . . . . . . . . . . . . . 19:1--19:??


ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 7, Number 1, February, 2014

            George Kornaros and   
        Dionisios Pnevmatikatos   Dynamic Power and Thermal Management of
                                  NoC-Based Heterogeneous MPSoCs . . . . . 1:1--1:??
            Yousef Iskander and   
          Cameron Patterson and   
                 Stephen Craven   High-Level Abstractions and Modular
                                  Debugging for FPGA Design Validation . . 2:1--2:??
                  Minxi Jin and   
               Tsutomu Maruyama   Fast and Accurate Stereo Vision System
                                  on FPGA  . . . . . . . . . . . . . . . . 3:1--3:??
                Onur Ulusel and   
                Kumud Nepal and   
              R. Iris Bahar and   
                   Sherief Reda   Fast Design Exploration for Performance,
                                  Power and Accuracy Tradeoffs in
                                  FPGA-Based Accelerators  . . . . . . . . 4:1--4:??
                Lok-Won Kim and   
                Sameh Asaad and   
                  Ralph Linsker   A Fully Pipelined FPGA Architecture of a
                                  Factored Restricted Boltzmann Machine
                                  Artificial Neural Network  . . . . . . . 5:1--5:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 7, Number 2, June, 2014

                  Jason Luu and   
            Jeffrey Goeders and   
           Michael Wainberg and   
          Andrew Somerville and   
                   Thien Yu and   
     Konstantin Nasartschuk and   
                  Miad Nasr and   
                   Sen Wang and   
                    Tim Liu and   
            Nooruddin Ahmed and   
            Kenneth B. Kent and   
             Jason Anderson and   
              Jonathan Rose and   
                    Vaughn Betz   VTR 7.0: Next Generation Architecture
                                  and CAD System for FPGAs . . . . . . . . 6:1--6:??
                  Soumya J. and   
              Ashish Sharma and   
          Santanu Chattopadhyay   Multi-Application Network-on-Chip Design
                                  using Global Mapping and Local
                                  Reconfiguration  . . . . . . . . . . . . 7:1--7:??
                 Yuanwu Lei and   
                    Lei Guo and   
                   Yong Dou and   
                   Sheng Ma and   
                       Jinbo Xu   FPGA Implementation of a Special-Purpose
                                  VLIW Structure for Double-Precision
                                  Elementary Function  . . . . . . . . . . 8:1--8:??
      Juan Antonio Clemente and   
               Ivan Beretta and   
              Vincenzo Rana and   
              David Atienza and   
               Donatella Sciuto   A Mapping-Scheduling Algorithm for
                                  Hardware Acceleration on Reconfigurable
                                  Platforms  . . . . . . . . . . . . . . . 9:1--9:??
             Anh-Tuan Hoang and   
                 Takeshi Fujino   Intra-Masking Dual-Rail Memory on LUT
                                  Implementation for SCA-Resistant AES on
                                  FPGA . . . . . . . . . . . . . . . . . . 10:1--10:??
                  Tobias Becker   Introduction to the TRETS Special
                                  Section on the Workshop on
                                  Self-Awareness in Reconfigurable
                                  Computing Systems (SRCS'12)  . . . . . . 11:1--11:??
            Jacopo Panerati and   
             Martina Maggio and   
           Matteo Carminati and   
             Filippo Sironi and   
             Marco Triverio and   
          Marco D. Santambrogio   Coordination of Independent Loops in
                                  Self-Adaptive Systems  . . . . . . . . . 12:1--12:??
               Andreas Agne and   
               Markus Happe and   
           Achim Lösch and   
           Christian Plessl and   
                 Marco Platzner   Self-Awareness as a Model for Designing
                                  and Operating Heterogeneous Multicores   13:1--13:??
         Christian Beckhoff and   
                  Dirk Koch and   
                   Jim Torresen   Design Tools for Implementing Self-Aware
                                  and Fault-Tolerant Systems on FPGAs  . . 14:1--14:??
                  Xinyu Niu and   
                  Qiwei Jin and   
                  Wayne Luk and   
                 Stephen Weston   A Self-Aware Tuning and Self-Aware
                                  Evaluation Method for Finite-Difference
                                  Applications in Reconfigurable Systems   15:1--15:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 7, Number 3, August, 2014

      Charles Eric Laforest and   
                    Zimo Li and   
           Tristan O'rourke and   
                Ming G. Liu and   
             J. Gregory Steffan   Composing Multi-Ported Memories on FPGAs 16:1--16:??
                Yuanxi Peng and   
      Manuel Saldaña and   
      Christopher A. Madill and   
               Xiaofeng Zou and   
                      Paul Chow   Benefits of Adding Hardware Support for
                                  Broadcast and Reduce Operations in MPSoC
                                  Applications . . . . . . . . . . . . . . 17:1--17:??
             Jason Anderson and   
                   Kiyoung Choi   Introduction to the Special Issue on the
                                  11th International Conference on
                                  Field-Programmable Technology (FPT'12)   18:1--18:??
              Hui Yan Cheah and   
            Fredrik Brosser and   
            Suhaib A. Fahmy and   
             Douglas L. Maskell   The iDEA DSP Block-Based Soft Processor
                                  for FPGAs  . . . . . . . . . . . . . . . 19:1--19:??
     Mohamed S. Abdelfattah and   
                    Vaughn Betz   Networks-on-Chip for FPGAs: Hard, Soft
                                  or Mixed?  . . . . . . . . . . . . . . . 20:1--20:??
                 Liang Chen and   
                   Tulika Mitra   Graph Minor Approach for Application
                                  Mapping on CGRAs . . . . . . . . . . . . 21:1--21:??
               Changmoo Kim and   
            Mookyoung Chung and   
                Yeongon Cho and   
         Mario Konijnenburg and   
                Soojung Ryu and   
                  Jeongwook Kim   ULP-SRP: Ultra Low-Power Samsung
                                  Reconfigurable Processor for Biomedical
                                  Applications . . . . . . . . . . . . . . 22:1--22:??
             Nikolaos Voros and   
                    Guy Gogniat   Introduction to the Special Issue on the
                                  7th International Workshop on
                                  Reconfigurable Communication-centric
                                  Systems-on-Chip (ReCoSoC'12) . . . . . . 23:1--23:??
          Christian Brugger and   
        Dominic Hillenbrand and   
                Matthias Balzer   RIVER: Reconfigurable Flow and Fabric
                                  for Real-Time Signal Processing on FPGAs 24:1--24:??
      Fábio Itturiet and   
              Gabriel Nazar and   
           Ronaldo Ferreira and   
      Álvaro Moreira and   
                    Luigi Carro   Adaptive Parallelism Exploitation under
                                  Physical and Real-Time Constraints for
                                  Resilient Systems  . . . . . . . . . . . 25:1--25:??
               Siew-Kei Lam and   
      Christopher T. Clarke and   
        Thambipillai Srikanthan   Exploiting FPGA-Aware Merging of Custom
                                  Instructions for Runtime Reconfiguration 26:1--26:??
   Sébastien Guillet and   
         Florent de Lamotte and   
         Nicolas le Griguer and   
         Éric Rutten and   
                Guy Gogniat and   
           Jean-Philippe Diguet   Extending UML/MARTE to Support Discrete
                                  Controller Synthesis, Application to
                                  Reconfigurable Systems-on-Chip Modeling  27:1--27:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 7, Number 4, January, 2015

              Jon T. Butler and   
                  Tsutomu Sasao   High-Speed Hardware Partition Generation 1:1--1:??
               Nuno Paulino and   
 João Canas Ferreira and   
      João M. P. Cardoso   A Reconfigurable Architecture for Binary
                                  Acceleration of Loops with Memory
                                  Accesses . . . . . . . . . . . . . . . . 2:1--2:??
                Udit Dhawan and   
             André Dehon   Area-Efficient Near-Associative Memories
                                  on FPGAs . . . . . . . . . . . . . . . . 3:1--3:??
            Daniel Llamocca and   
               Marios Pattichis   Dynamic Energy, Performance, and
                                  Accuracy Optimization and Management
                                  Using Automatically Generated
                                  Constraints for Separable $2$D FIR
                                  Filtering for Digital Video Processing   4:1--4:??
            Benjamin Gojman and   
            Sirisha Nalmela and   
                Nikil Mehta and   
           Nicholas Howarth and   
             André Dehon   GROK-LAB: Generating Real On-chip
                                  Knowledge for Intra-cluster Delays Using
                                  Timing Extraction  . . . . . . . . . . . 5:1--5:??
              Atabak Mahram and   
             Martin C. Herbordt   NCBI BLASTP on High-Performance
                                  Reconfigurable Computing Systems . . . . 6:1--6:??
         Pawel Swierczynski and   
                Amir Moradi and   
               David Oswald and   
                  Christof Paar   Physical Security Evaluation of the
                                  Bitstream Encryption Mechanism of Altera
                                  Stratix II and Stratix III FPGAs . . . . 7:1--7:??
                 Jo Vliegen and   
               Nele Mentens and   
             Ingrid Verbauwhede   Secure, Remote, Dynamic Reconfiguration
                                  of FPGAs . . . . . . . . . . . . . . . . 8:1--8:??
          Thomas C. P. Chau and   
                  Xinyu Niu and   
                Alison Eele and   
            Jan Maciejowski and   
         Peter Y. K. Cheung and   
                      Wayne Luk   Mapping Adaptive Particle Filters to
                                  Heterogeneous Reconfigurable Systems . . 9:1--9:??
              Bailey Miller and   
                Frank Vahid and   
              Tony Givargis and   
                   Philip Brisk   Graph-Based Approaches to Placement of
                                  Processing Element Networks on FPGAs for
                                  Physical Model Simulation  . . . . . . . 10:1--10:??


ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 8, Number 1, February, 2015

           Stefano Di Carlo and   
         Giulio Gambardella and   
             Paolo Prinetto and   
              Daniele Rolfo and   
                  Pascal Trotta   SATTA: a Self-Adaptive Temperature-Based
                                  TDF Awareness Methodology for
                                  Dynamically Reconfigurable FPGAs . . . . 1:1--1:??
              Patrick Cooke and   
              Jeremy Fowers and   
                 Greg Brown and   
                     Greg Stitt   A Tradeoff Analysis of FPGAs, GPUs, and
                                  Multicores for Sliding-Window
                                  Applications . . . . . . . . . . . . . . 2:1--2:??
              Heather Quinn and   
        Diane Roussel-Dupre and   
               Mike Caffrey and   
                Paul Graham and   
           Michael Wirthlin and   
               Keith Morgan and   
            Anthony Salazar and   
                Tony Nelson and   
                 Will Howes and   
               Eric Johnson and   
                Jon Johnson and   
                Brian Pratt and   
             Nathan Rollins and   
                      Jim Krone   The Cibola Flight Experiment . . . . . . 3:1--3:??
               Tom Davidson and   
        Elias Vansteenkiste and   
                Karel Heyse and   
              Karel Bruneel and   
                Dirk Stroobandt   Identification of Dynamic Circuit
                                  Specialization Opportunities in RTL Code 4:1--4:??
              Xabier Iturbe and   
             Khaled Benkrid and   
                 Chuan Hong and   
                Ali Ebrahim and   
               Raul Torrego and   
                 Tughrul Arslan   Microkernel Architecture and Hardware
                                  Abstraction Layer of a Reliable
                                  Reconfigurable Real-Time Operating
                                  System (R3TOS) . . . . . . . . . . . . . 5:1--5:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 8, Number 2, April, 2015

                    Kan Shi and   
               David Boland and   
       George A. Constantinides   Imprecise Datapath Design: an
                                  Overclocking Approach  . . . . . . . . . 6:1--6:??
                Louis Woods and   
             Gustavo Alonso and   
                   Jens Teubner   Parallelizing Data Processing on FPGAs
                                  with Shifter Lists . . . . . . . . . . . 7:1--7:??
  João M. P. Cardoso and   
             Pedro C. Diniz and   
     Katherine (Compton) Morrow   Guest Editorial: FPL 2013  . . . . . . . 8:1--8:??
           Ricardo Ferreira and   
              Luciana Rocha and   
     André G. Santos and   
    José A. M. Nacif and   
               Stephan Wong and   
                    Luigi Carro   A Runtime FPGA Placement and Routing
                                  Using Low-Complexity Graph Traversal . . 9:1--9:??
            Kevin E. Murray and   
               Scott Whitty and   
                   Suya Liu and   
                  Jason Luu and   
                    Vaughn Betz   Timing-Driven Titan: Enabling Large
                                  Benchmarks and Exploring the Gap between
                                  Academic and Commercial CAD  . . . . . . 10:1--10:??
                    Lin Gan and   
                 Haohuan Fu and   
                  Wayne Luk and   
                  Chao Yang and   
                    Wei Xue and   
             Xiaomeng Huang and   
               Youhui Zhang and   
                  Guangwen Yang   Solving the Global Atmospheric Equations
                                  through Heterogeneous Reconfigurable
                                  Platforms  . . . . . . . . . . . . . . . 11:1--11:??
                   Anup Das and   
   Shyamsundar Venkataraman and   
                    Akash Kumar   Autonomous Soft-Error Tolerance of FPGA
                                  Configuration Bits . . . . . . . . . . . 12:1--12:??
        Zsolt István and   
             Gustavo Alonso and   
             Michaela Blott and   
                   Kees Vissers   A Hash Table for Line-Rate Data
                                  Processing . . . . . . . . . . . . . . . 13:1--13:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 8, Number 3, May, 2015

               Qijing Huang and   
               Ruolong Lian and   
               Andrew Canis and   
               Jongsok Choi and   
                    Ryan Xi and   
            Nazanin Calagar and   
              Stephen Brown and   
                 Jason Anderson   The Effect of Compiler Optimizations on
                                  High-Level Synthesis-Generated Hardware  14:1--14:??
                  Xinyu Niu and   
          Thomas C. P. Chau and   
                  Qiwei Jin and   
                  Wayne Luk and   
                  Qiang Liu and   
                    Oliver Pell   Automating Elimination of Idle Functions
                                  by Runtime Reconfiguration . . . . . . . 15:1--15:??
              Shivam Bhasin and   
            Jean-Luc Danger and   
            Sylvain Guilley and   
                         Wei He   Exploiting FPGA Block Memories for
                                  Protected Cryptographic Implementations  16:1--16:??
        Juan Fernando Eusse and   
       Christopher Williams and   
                 Rainer Leupers   CoEx: a Novel Profiling-Based
                                  Algorithm/Architecture Co-Exploration
                                  for ASIP Design  . . . . . . . . . . . . 17:1--17:??
                   Anup Das and   
           Amit Kumar Singh and   
                    Akash Kumar   Execution Trace-Driven
                                  Energy-Reliability Optimization for
                                  Multimedia MPSoCs  . . . . . . . . . . . 18:1--18:??
                     Yu Ren and   
                  Leibo Liu and   
                 Shouyi Yin and   
                    Jie Han and   
                    Shaojun Wei   Efficient Fault-Tolerant Topology
                                  Reconfiguration Using a Maximum Flow
                                  Algorithm  . . . . . . . . . . . . . . . 19:1--19:??
               Roland Dobai and   
                 Lukas Sekanina   Low-Level Flexible Architecture with
                                  Hybrid Reconfiguration for Evolvable
                                  Hardware . . . . . . . . . . . . . . . . 20:1--20:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 8, Number 4, October, 2015

        Robert Kirchgessner and   
             Alan D. George and   
                     Greg Stitt   Low-Overhead FPGA Middleware for
                                  Application Portability and Productivity 21:1--21:??
           Matthew Jacobsen and   
            Dustin Richmond and   
            Matthew Hogains and   
                   Ryan Kastner   RIFFA 2.1: a Reusable Integration
                                  Framework for FPGA Accelerators  . . . . 22:1--22:??
                David B. Thomas   The Table-Hadamard GRNG: an
                                  Area-Efficient FPGA Gaussian Random
                                  Number Generator . . . . . . . . . . . . 23:1--23:??
                Zheming Jin and   
                 Jason D. Bakos   Memory Interface Design for $3$D Stencil
                                  Kernels on a Massively Parallel Memory
                                  System . . . . . . . . . . . . . . . . . 24:1--24:??
              Guangming Tan and   
             Chunming Zhang and   
                 Wendi Wang and   
                  Peiheng Zhang   SuperDragon: a Heterogeneous Parallel
                                  System for Accelerating $3$D
                                  Reconstruction of Cryo-Electron
                                  Microscopy Images  . . . . . . . . . . . 25:1--25:??
       Alexander Biedermann and   
              Sorin A. Huss and   
                    Adeel Israr   Safe Dynamic Reshaping of Reconfigurable
                                  MPSoC Embedded Systems for Self-Healing
                                  and Self-Adaption Purposes . . . . . . . 26:1--26:??


ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 9, Number 1, November, 2015

              Joonseok Park and   
                 Pedro C. Diniz   Program-Invariant Checking for
                                  Soft-Error Detection using
                                  Reconfigurable Hardware  . . . . . . . . 1:1--1:??
              Neil Scicluna and   
       Christos-Savvas Bouganis   ARC 2014: a Multidimensional FPGA-Based
                                  Parallel DBSCAN Architecture . . . . . . 2:1--2:??
            Pascal Sasdrich and   
               Tim Güneysu   Implementing Curve25519 for
                                  Side-Channel--Protected Elliptic Curve
                                  Cryptography . . . . . . . . . . . . . . 3:1--3:??
             Jianfeng Zhang and   
                  Paul Chow and   
                    Hengzhu Liu   An Enhanced Adaptive Recoding Rotation
                                  CORDIC . . . . . . . . . . . . . . . . . 4:1--4:??
           Diana Goehringer and   
      Marco D. Santambrogio and   
  João M. P. Cardoso and   
                   Koen Bertels   Guest Editorial: ARC 2014  . . . . . . . 5:1--5:??
                Karel Heyse and   
            Jente Basteleus and   
           Brahim Al Farisi and   
            Dirk Stroobandt and   
             Oliver Kadlcek and   
                    Oliver Pell   On the Impact of Replacing Low-Speed
                                  Configuration Buses on FPGAs with the
                                  Chip's Internal Configuration
                                  Infrastructure . . . . . . . . . . . . . 6:1--6:??
       Rui Policarpo Duarte and   
       Christos-Savvas Bouganis   ARC 2014 Over-Clocking KLT Designs on
                                  FPGAs under Process, Voltage, and
                                  Temperature Variation  . . . . . . . . . 7:1--7:??
                  Yuhui Bai and   
           Syed Zahid Ahmed and   
               Bertrand Granado   ARC 2014: Towards a Fast FPGA
                                  Implementation of a Heap-Based Priority
                                  Queue for Image Coding Using a Parallel
                                  Index-Aware Tree . . . . . . . . . . . . 8:1--8:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 9, Number 2, February, 2016

             Jianfeng Zhang and   
                  Paul Chow and   
                    Hengzhu Liu   CORDIC-Based Enhanced Systolic Array
                                  Architecture for $ Q R $ Decomposition   9:1--9:??
       Felix J. Winterstein and   
          Samuel R. Bayliss and   
       George A. Constantinides   Separation Logic for High-Level
                                  Synthesis  . . . . . . . . . . . . . . . 10:1--10:??
                  Jinwei Xu and   
              Jingfei Jiang and   
                   Yong Dou and   
              Xiaolong Shen and   
                   Zhiqiang Liu   Coarse-Grained Architecture for
                                  Fingerprint Matching . . . . . . . . . . 12:1--12:??
          Ali Mustafa Zaidi and   
                  David Greaves   Value State Flow Graph: a Dataflow
                                  Compiler IR for Accelerating
                                  Control-Intensive Code in Spatial
                                  Hardware . . . . . . . . . . . . . . . . 14:1--14:??
             Michael Raitza and   
                Markus Vogt and   
       Christian Hochberger and   
                 Thilo Pionteck   RAW 2014: Random Number Generators on
                                  FPGAs  . . . . . . . . . . . . . . . . . 15:1--15:??
             Osama G. Attia and   
          Kevin R. Townsend and   
           Phillip H. Jones and   
                Joseph Zambreno   A Reconfigurable Architecture for the
                                  Detection of Strongly Connected
                                  Components . . . . . . . . . . . . . . . 16:1--16:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 9, Number 3, July, 2016

                 Nachiket Kapre   Optimizing Soft Vector Processing in
                                  FPGA-Based Embedded Systems  . . . . . . 17:1--17:??
         André Dehon and   
                    Derek Chiou   Introduction to Special Issue on
                                  Reconfigurable Components with Source
                                  Code . . . . . . . . . . . . . . . . . . 19:1--19:??
               David Wilson and   
                     Greg Stitt   The Unified Accumulator Architecture: a
                                  Configurable, Portable, and Extensible
                                  Floating-Point Accumulator . . . . . . . 21:1--21:??
      Ameer M. S. Abdelhadi and   
              Guy G. F. Lemieux   Modular Switched Multiported SRAM-Based
                                  Memories . . . . . . . . . . . . . . . . 22:1--22:??
                 Greg Stitt and   
              Eric Schwartz and   
                  Patrick Cooke   A Parallel Sliding-Window Generator for
                                  High-Performance Digital-Signal
                                  Processing on FPGAs  . . . . . . . . . . 23:1--23:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 9, Number 4, September, 2016

              Zain Ul-Abdin and   
                Bertil Svensson   A Retargetable Compilation Framework for
                                  Heterogeneous Reconfigurable Computing   24:1--24:??
              Daniel Ziener and   
              Florian Bauer and   
             Andreas Becher and   
          Christopher Dennl and   
        Klaus Meyer-Wegener and   
         Ute Schürfeld and   
          Jürgen Teich and   
     Jörg-Stephan Vogt and   
                   Helmut Weber   FPGA-Based Dynamically Reconfigurable
                                  SQL Query Processing . . . . . . . . . . 25:1--25:??
              Eric Matthews and   
             Lesley Shannon and   
             Alexandra Fedorova   Shared Memory Multicore MicroBlaze
                                  System with SMP Linux Support  . . . . . 26:1--26:??
                    Ting Yu and   
              Chris Bradley and   
                  Oliver Sinnen   ODoST: Automatic Hardware Acceleration
                                  for Biomedical Model Integration . . . . 27:1--27:??
                    Deming Chen   Introduction . . . . . . . . . . . . . . 28:1--28:??
                Evan Wegley and   
                  Yanhua Yi and   
                   Qinhai Zhang   Application of Specific Delay Window
                                  Routing for Timing Optimization in FPGA
                                  Designs  . . . . . . . . . . . . . . . . 29:1--29:??
                Edin Kadric and   
               David Lakata and   
             André Dehon   Impact of Parallelism and Memory
                                  Architecture on FPGA Communication
                                  Energy . . . . . . . . . . . . . . . . . 30:1--30:??
              Alex Rodionov and   
            David Biancolin and   
                  Jonathan Rose   Fine-Grained Interconnect Synthesis  . . 31:1--31:??


ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 10, Number 1, December, 2016

              Nicholas Wulf and   
             Alan D. George and   
                Ann Gordon-Ross   A Framework for Evaluating and
                                  Optimizing FPGA-Based SoCs for Aerospace
                                  Computing  . . . . . . . . . . . . . . . 1:1--1:??
          Justin Richardson and   
                Alan George and   
                Kevin Cheng and   
                     Herman Lam   Analysis of Fixed, Reconfigurable, and
                                  Hybrid Devices with Computational,
                                  Memory, I/O, & Realizable-Utilization
                                  Metrics  . . . . . . . . . . . . . . . . 2:1--2:??
              Hung-Lin Chao and   
              Sheng-Ya Tung and   
                 Pao-Ann Hsiung   Dynamic Task Mapping with Congestion
                                  Speculation for Reconfigurable
                                  Network-on-Chip  . . . . . . . . . . . . 3:1--3:??
            Bertrand Le Gal and   
Yérom-David Bromberg and   
Laurent Réveill\`ere and   
                  Jigar Solanki   A Flexible SoC and Its Methodology for
                                  Parser-Based Applications  . . . . . . . 4:1--4:??
                Yeyong Pang and   
               Shaojun Wang and   
                    Yu Peng and   
                Xiyuan Peng and   
         Nicholas J. Fraser and   
             Philip H. W. Leong   A Microcoded Kernel Recursive Least
                                  Squares Processor Using FPGA Technology  5:1--5:??
               Qing Y. Tang and   
          Mohammed A. S. Khalid   Acceleration of $k$-Means Algorithm
                                  Using Altera SDK for OpenCL  . . . . . . 6:1--6:??
                 Henry Wong and   
                Vaughn Betz and   
                  Jonathan Rose   Microarchitecture and Circuits for a 200
                                  MHz Out-of-Order Soft Processor Memory
                                  System . . . . . . . . . . . . . . . . . 7:1--7:??
       Bita Darvish Rouhani and   
          Azalia Mirhoseini and   
        Ebrahim M. Songhori and   
             Farinaz Koushanfar   Automated Real-Time Analysis of
                                  Streaming Big and Dense Data on
                                  Reconfigurable Platforms . . . . . . . . 8:1--8:??
               Alban Bourge and   
             Olivier Muller and   
Frédéric Rousseau   Generating Efficient Context-Switch
                                  Capable Circuits through Autonomous
                                  Design Flow  . . . . . . . . . . . . . . 9:1--9:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 10, Number 2, April, 2017

  João M. P. Cardoso and   
               Cristina Silvano   Introduction to the Special Section on
                                  FPL 2015 . . . . . . . . . . . . . . . . 10:1--10:??
                Jin Hee Kim and   
              Jason H. Anderson   Synthesizable Standard Cell FPGA Fabrics
                                  Targetable by the Verilog-to-Routing CAD
                                  Flow . . . . . . . . . . . . . . . . . . 11:1--11:??
            Pavel Burovskiy and   
              Paul Grigoras and   
            Spencer Sherwin and   
                      Wayne Luk   Efficient Assembly for High-Order
                                  Unstructured FEM Meshes (FPL 2015) . . . 12:1--12:??
             Hsin-Jung Yang and   
             Kermin Fleming and   
          Felix Winterstein and   
              Michael Adler and   
                      Joel Emer   (FPL 2015) Scavenger: Automating the
                                  Construction of Application-Optimized
                                  Memory Hierarchies . . . . . . . . . . . 13:1--13:??
             Nachiket Kapre and   
                       Jan Gray   Hoplite: a Deflection-Routed Directional
                                  Torus NoC for FPGAs  . . . . . . . . . . 14:1--14:??
         Philip H. W. Leong and   
             Hideharu Amano and   
             Jason Anderson and   
               Koen Bertels and   
  João M. P. Cardoso and   
             Oliver Diessel and   
                Guy Gogniat and   
                Mike Hutton and   
                 Junkyu Lee and   
                  Wayne Luk and   
            Patrick Lysaght and   
             Marco Platzner and   
         Viktor K. Prasanna and   
                 Tero Rissa and   
           Cristina Silvano and   
         Hayden Kwok-Hay So and   
                        Yu Wang   The First 25 Years of the FPL
                                  Conference: Significant Papers . . . . . 15:1--15:??
               Shigeyuki Takano   Performance Scalability of Adaptive
                                  Processor Architecture . . . . . . . . . 16:1--16:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 10, Number 3, July, 2017

               Zhiqiang Liu and   
                   Yong Dou and   
              Jingfei Jiang and   
                  Jinwei Xu and   
                  Shijie Li and   
               Yongmei Zhou and   
                     Yingnan Xu   Throughput-Optimized FPGA Accelerator
                                  for Deep Convolutional Neural Networks   17:1--17:??
              Tomohiro Ueno and   
               Kentaro Sano and   
                Satoru Yamamoto   Bandwidth Compression of Floating-Point
                                  Numerical Data Streams for FPGA-Based
                                  High-Performance Computing . . . . . . . 18:1--18:??
      Charles Eric Laforest and   
              Jason H. Anderson   Microarchitectural Comparison of the MXP
                                  and Octavo Soft-Processor FPGA Overlays  19:1--19:??
                Chongyan Gu and   
                Neil Hanley and   
           Máire O'neill   Improved Reliability of FPGA-Based PUF
                                  Identification Generator Design  . . . . 20:1--20:??
        Adrien Prost-Boucle and   
FRédéric Pétrot and   
              Vincent Leroy and   
                  Hande Alemdar   Efficient and Versatile FPGA
                                  Acceleration of Support Counting for
                                  Stream Mining of Sequences and Frequent
                                  Itemsets . . . . . . . . . . . . . . . . 21:1--21:??
                 Ilian Tili and   
            Kalin Ovtcharov and   
             J. Gregory Steffan   Reducing the Performance Gap between
                                  Soft Scalar CPUs and Custom Hardware
                                  with TILT  . . . . . . . . . . . . . . . 22:1--22:??
              Nicholas Wulf and   
             Alan D. George and   
                Ann Gordon-Ross   Optimizing FPGA Performance, Power, and
                                  Dependability with Linear Programming    23:1--23:??
           Heinrich Riebler and   
               Michael Lass and   
          Robert Mittendorf and   
          Thomas Löcke and   
               Christian Plessl   Efficient Branch and Bound on FPGAs
                                  Using Work Stealing and
                                  Instance-Specific Designs  . . . . . . . 24:1--24:??

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Volume 10, Number 4, December, 2017

         Eduardo A. Gerlein and   
            T. M. Mcginnity and   
           Ammar Belatreche and   
                  Sonya Coleman   Network on Chip Architecture for
                                  Multi-Agent Systems in FPGA  . . . . . . 25:1--25:??
         Nicholas J. Fraser and   
                 Junkyu Lee and   
          Duncan J. M. Moss and   
             Julian Faraone and   
           Stephen Tridgell and   
               Craig T. Jin and   
             Philip H. W. Leong   FPGA Implementations of Kernel
                                  Normalised Least Mean Squares Processors 26:1--26:??
              Thiem Van Chu and   
               Shimpei Sato and   
                     Kenji Kise   Fast and Cycle-Accurate Emulation of
                                  Large-Scale Networks-on-Chip Using a
                                  Single FPGA  . . . . . . . . . . . . . . 27:1--27:??
             Masato Yoshimi and   
                  Yasin Oge and   
              Tsutomu Yoshinaga   Pipelined Parallel Join and Its
                                  FPGA-Based Acceleration  . . . . . . . . 28:1--28:??
               Pieter Fabry and   
                   David Thomas   Efficient Reconfigurable Architecture
                                  for Pricing Exotic Options . . . . . . . 29:1--29:??