Valid HTML 4.0! Valid CSS!
%%% -*-BibTeX-*-
%%% ====================================================================
%%%  BibTeX-file{
%%%     author          = "Nelson H. F. Beebe",
%%%     version         = "2.05",
%%%     date            = "16 February 2024",
%%%     time            = "08:11:19 MST",
%%%     filename        = "risc-v.bib",
%%%     address         = "University of Utah
%%%                        Department of Mathematics, 110 LCB
%%%                        155 S 1400 E RM 233
%%%                        Salt Lake City, UT 84112-0090
%%%                        USA",
%%%     telephone       = "+1 801 581 5254",
%%%     FAX             = "+1 801 581 4148",
%%%     URL             = "https://www.math.utah.edu/~beebe",
%%%     checksum        = "04751 16325 70000 712697",
%%%     email           = "beebe at math.utah.edu, beebe at acm.org,
%%%                        beebe at computer.org (Internet)",
%%%     codetable       = "ISO/ASCII",
%%%     keywords        = "bibliography; BibTeX; open-source instruction
%%%                        set architecture; RISC-V; RISC-V32; RISC-V64",
%%%     license         = "public domain",
%%%     supported       = "yes",
%%%     docstring       = "This is a bibliography of publications about
%%%                        the RISC-V processor architecture, a recent
%%%                        instruction set design that is open source,
%%%                        and intended to receive wide use from small
%%%                        embedded systems, to desktop computers, and
%%%                        to high-performance computing servers.
%%%
%%%                        Major documentation of the RISC-V architecture
%%%                        can be found via links at this site:
%%%
%%%                            https://riscv.org/technical/specifications/
%%%
%%%                        As the table below suggests, most of the
%%%                        literature on RISC-V is found in conference
%%%                        proceedings articles, possibly reflecting
%%%                        rapid development in this area.
%%%
%%%                        At version 2.05, the year coverage looked
%%%                        like this:
%%%
%%%                             2013 (   1)    2017 (  30)    2021 ( 165)
%%%                             2014 (   2)    2018 (  31)    2022 ( 161)
%%%                             2015 (   4)    2019 (  68)    2023 ( 183)
%%%                             2016 (   9)    2020 (  94)    2024 (   5)
%%%
%%%                             Article:        165
%%%                             Book:             5
%%%                             InProceedings:  563
%%%                             Misc:            14
%%%                             Proceedings:      5
%%%                             TechReport:       1
%%%
%%%                             Total entries:  753
%%%
%%%                        The checksum field above contains a CRC-16
%%%                        checksum as the first value, followed by the
%%%                        equivalent of the standard UNIX wc (word
%%%                        count) utility output of lines, words, and
%%%                        characters.  This is produced by Robert
%%%                        Solovay's checksum utility.",
%%%  }
%%% ====================================================================
@Preamble{
    "\ifx \undefined \booktitle \def \booktitle #1{{{\em #1}}}  \fi" #
    "\ifx \undefined \circled   \def \circled   #1{(#1)}        \fi" #
    "\ifx \undefined \dbar      \def \dbar        {\leavevmode\raise0.2ex\hbox{--}\kern-0.5emd} \fi" #
    "\ifx \undefined \Dbar      \def \Dbar        {\leavevmode\raise0.2ex\hbox{--}\kern-0.5emD} \fi" #
    "\ifx \undefined \pkg       \def \pkg       #1{{{\tt #1}}}  \fi" #
    "\ifx \undefined \reg       \def \reg         {\circled{R}} \fi"
}

%%% ====================================================================
%%% Acknowledgement abbreviations:
@String{ack-nhfb = "Nelson H. F. Beebe,
                    University of Utah,
                    Department of Mathematics, 110 LCB,
                    155 S 1400 E RM 233,
                    Salt Lake City, UT 84112-0090, USA,
                    Tel: +1 801 581 5254,
                    FAX: +1 801 581 4148,
                    e-mail: \path|beebe@math.utah.edu|,
                            \path|beebe@acm.org|,
                            \path|beebe@computer.org| (Internet),
                    URL: \path|https://www.math.utah.edu/~beebe/|"}

%%% ====================================================================
%%% Journal abbreviations:
@String{j-CACM                  = "Communications of the Association
                                  for Computing Machinery"}

@String{j-CCPE                  = "Concurrency and Computation: Prac\-tice and
                                   Experience"}

@String{j-COMP-ARCH-NEWS        = "ACM SIGARCH Computer Architecture News"}

@String{j-COMP-SURV             = "ACM Computing Surveys"}

@String{j-COMPUT-SECUR          = "Computers \& Security"}

@String{j-COMPUTER              = "Computer"}

@String{j-DTRAP                 = "Digital Threats: Research and Practice
                                  (DTRAP)"}

@String{j-ELECTRONICS           = "Electronics"}

@String{j-FUT-GEN-COMP-SYS      = "Future Generation Computer Systems"}

@String{j-FUTURE-INTERNET       = "Future Internet"}

@String{j-IEEE-ACCESS           = "IEEE Access"}

@String{j-IEEE-COMPUT-ARCHIT-LETT = "IEEE Computer Architecture Letters"}

@String{j-IEEE-J-SOLID-STATE-CIRCUITS = "IEEE Journal of Solid-State Circuits"}

@String{j-IEEE-MICRO            = "IEEE Micro"}

@String{j-IEEE-SPECTRUM         = "IEEE Spectrum"}

@String{j-IEEE-TRANS-AEROSP-ELECTRON-SYST = "IEEE Transactions on Aerospace and
                                  Electronic Systems"}

@String{j-IEEE-TRANS-CAD-ICS    = "IEEE Transactions on Computer-Aided Design of
                                  Integrated Circuits and Systems"}

@String{j-IEEE-TRANS-CIRCUITS-SYST-1 = "IEEE Transactions on Circuits and
                                Systems I: Regular Papers"}

@String{j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS = "IEEE Transactions on
                                  Circuits and Systems II: Express Briefs"}

@String{j-IEEE-TRANS-COMPUT     = "IEEE Transactions on Computers"}

@String{j-IEEE-TRANS-EMERG-TOP-COMPUT = "IEEE Transactions on Emerging Topics in
                                  Computing"}

@String{j-IEEE-TRANS-MAGNETICS  = "IEEE Transactions on Magnetics"}

@String{j-IEEE-TRANS-NUCL-SCI   = "IEEE Transactions on Nuclear Science"}

@String{j-IEEE-TRANS-VLSI-SYST  = "IEEE Transactions on Very Large Scale
                                  Integration (VLSI) Systems"}

@String{j-J-CRYPTO-ENG          = "Journal of Cryptographic Engineering"}

@String{j-J-SUPERCOMPUTING      = "The Journal of Supercomputing"}

@String{j-JETC                  = "ACM Journal on Emerging Technologies
                                  in Computing Systems (JETC)"}

@String{j-OPER-SYS-REV          = "Operating Systems Review"}

@String{j-SENSORS-BASEL         = "Sensors (Basel)"}

@String{j-SIGPLAN               = "ACM SIG{\-}PLAN Notices"}

@String{j-SOFTWAREX             = "SoftwareX"}

@String{j-TACO                  = "ACM Transactions on Architecture and
                                  Code Optimization"}

@String{j-TCBB                  = "IEEE/ACM Transactions on Computational
                                  Biology and Bioinformatics"}

@String{j-TECS                  = "ACM Transactions on Embedded Computing
                                  Systems"}

@String{j-TODAES                = "ACM Transactions on Design Automation of
                                   Electronic Systems"}

@String{j-TRETS                 = "ACM Transactions on Reconfigurable Technology
                                  and Systems (TRETS)"}

%%% ====================================================================
%%% Publishers and their addresses:
@String{pub-ACM                 = "ACM Press"}
@String{pub-ACM:adr             = "New York, NY 10036, USA"}

@String{pub-IEEE                = "IEEE Computer Society Press"}
@String{pub-IEEE:adr            = "1109 Spring Street, Suite 300, Silver
                                   Spring, MD 20910, USA"}

@String{pub-SV                  = "Spring{\-}er-Ver{\-}lag"}
@String{pub-SV:adr              = "Berlin, Germany~/ Heidelberg,
                                  Germany~/ London, UK~/ etc."}

%%% ====================================================================
%%% Bibliography entries, sorted by year, and then by citation label,
%%% with "bibsort --byyear":
@InProceedings{Waterman:2013:RVI,
  author =       "Andrew Waterman and Yunsup Lee and Rimas Avizienis and
                 Henry Cook and David Patterson and Krste Asanovic",
  editor =       "{IEEE}",
  booktitle =    "{2013 IEEE Hot Chips 25 Symposium (HCS)}",
  title =        "The {RISC-V} instruction set",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--1",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/HOTCHIPS.2013.7478332",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@TechReport{Asanovic:2014:ISS,
  author =       "K. Asanovi{\'c} and D. A. Patterson",
  title =        "Instruction sets should be free: the case for
                 {RISC-V}",
  type =         "Technical Report",
  number =       "UCB/EECS-2014-146",
  institution =  "Department of Electrical Engineering and Computer
                 Science, University of California, Berkeley",
  address =      "Berkeley, CA, USA",
  pages =        "7",
  day =          "6",
  month =        aug,
  year =         "2014",
  bibdate =      "Tue Dec 19 07:33:25 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.pdf",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lee:2014:DPG,
  author =       "Yunsup Lee and Andrew Waterman and Rimas Avizienis and
                 Henry Cook and Chen Sun and Vladimir Stojanovi{\'c} and
                 Krste Asanovi{\'c}",
  editor =       "{IEEE}",
  booktitle =    "{ESSCIRC 2014 --- 40th European Solid State Circuits
                 Conference (ESSCIRC)}",
  title =        "A 45nm {1.3GHz 16.7} double-precision {GFLOPS\slash W
                 RISC-V} processor with vector accelerators",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "199--202",
  year =         "2014",
  DOI =          "https://doi.org/10.1109/ESSCIRC.2014.6942056",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lee:2015:RRV,
  author =       "Yunsup Lee and Brian Zimmer and Andrew Waterman and
                 Alberto Puggelli and Jaehwa Kwak and Ruzica Jevtic and
                 Ben Keller and Stevo Bailey and Milovan Blagojevic and
                 Pi-Feng Chiu and Henry Cook and Rimas Avizienis and
                 Brian Richards and Elad Alon and Borivoje Nikolic and
                 Krste Asanovic",
  editor =       "{IEEE}",
  booktitle =    "{2015 IEEE Hot Chips 27 Symposium (HCS)}",
  title =        "{Raven}: a 28nm {RISC-V} vector processor with
                 integrated switched-capacitor {DC-DC} converters and
                 adaptive clocking",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--45",
  year =         "2015",
  DOI =          "https://doi.org/10.1109/HOTCHIPS.2015.7477469",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Patil:2015:OFP,
  author =       "Vinayak Patil and Aneesh Raveendran and P. M. Sobha
                 and A. David Selvakumar and D. Vivian",
  editor =       "{IEEE}",
  booktitle =    "{2015 19th International Symposium on VLSI Design and
                 Test}",
  title =        "Out of order floating point coprocessor for {RISC V
                 ISA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2015",
  DOI =          "https://doi.org/10.1109/ISVDAT.2015.7208116",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Raveendran:2015:RVO,
  author =       "Aneesh Raveendran and Vinayak Patil and Vivian
                 Desalphine and P. M. Sobha and A. David Selvakumar",
  editor =       "{IEEE}",
  booktitle =    "{2015 19th International Symposium on VLSI Design and
                 Test}",
  title =        "{RISC-V} out-of-order data conversion co-processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--2",
  year =         "2015",
  DOI =          "https://doi.org/10.1109/ISVDAT.2015.7208117",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zimmer:2015:RVV,
  author =       "Brian Zimmer and Yunsup Lee and Alberto Puggelli and
                 Jaehwa Kwak and Ruzica Jevtic and Ben Keller and Stevo
                 Bailey and Milovan Blagojevic and Pi-Feng Chiu and
                 Hanh-Phuc Le and Po-Hung Chen and Nicholas Sutardja and
                 Rimas Avizienis and Andrew Waterman and Brian Richards
                 and Philippe Flatresse and Elad Alon and Krste
                 Asanovi{\'c} and Borivoje Nikoli{\'c}",
  editor =       "{IEEE}",
  booktitle =    "{2015 Symposium on VLSI Circuits (VLSI Circuits)}",
  title =        "A {RISC-V} vector processor with tightly-integrated
                 switched-capacitor {DC-DC} converters in 28nm {FDSOI}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "C316--C317",
  year =         "2015",
  DOI =          "https://doi.org/10.1109/VLSIC.2015.7231305",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Duran:2016:BRV,
  author =       "Ckristian Duran and D. Luis Rueda and Giovanny
                 Castillo and Anderson Agudelo and Camilo Rojas and Luis
                 Chaparro and Harry Hurtado and Juan Romero and Wilmer
                 Ramirez and Hector Gomez and Javier Ardila and Luis
                 Rueda and Hugo Hernandez and Jose Amaya and Elkim Roa",
  editor =       "{IEEE}",
  booktitle =    "{2016 IEEE 7th Latin American Symposium on Circuits \&
                 Systems (LASCAS)}",
  title =        "A 32-bit {RISC-V AXI4-lite} bus-based microcontroller
                 with 10-bit {SAR ADC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "315--318",
  year =         "2016",
  DOI =          "https://doi.org/10.1109/LASCAS.2016.7451073",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gray:2016:GPM,
  author =       "Jan Gray",
  editor =       "{IEEE}",
  booktitle =    "{2016 IEEE 24th Annual International Symposium on
                 Field-Programmable Custom Computing Machines (FCCM)}",
  title =        "{GRVI Phalanx}: a Massively Parallel {RISC-V FPGA}
                 Accelerator Accelerator",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "17--20",
  year =         "2016",
  DOI =          "https://doi.org/10.1109/FCCM.2016.12",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Kim:2016:SCD,
  author =       "Channoh Kim and Sungmin Kim and Hyeon Gyu Cho and
                 Dooyoung Kim and Jaehyeok Kim and Young H. Oh and
                 Hakbeom Jang and Jae W. Lee",
  title =        "Short-circuit dispatch: accelerating virtual machine
                 interpreters on embedded processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "44",
  number =       "3",
  pages =        "291--303",
  month =        jun,
  year =         "2016",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/3007787.3001168",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Thu Jan 12 18:43:43 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigarch.bib;
                 https://www.math.utah.edu/pub/tex/bib/virtual-machines.bib",
  abstract =     "Interpreters are widely used to implement high-level
                 language virtual machines (VMs), especially on
                 resource-constrained embedded platforms. Many scripting
                 languages employ interpreter-based VMs for their
                 advantages over native code compilers, such as
                 portability, smaller resource footprint, and compact
                 codes. For efficient interpretation a script (program)
                 is first compiled into an intermediate representation,
                 or bytecodes. The canonical interpreter then runs an
                 infinite loop that fetches, decodes, and executes one
                 bytecode at a time. This bytecode dispatch loop is a
                 well-known source of inefficiency, typically featuring
                 a large jump table with a hard-to-predict indirect
                 jump. Most existing techniques to optimize this loop
                 focus on reducing the misprediction rate of this
                 indirect jump in both hardware and software. However,
                 these techniques are much less effective on embedded
                 processors with shallow pipelines and low IPCs.
                 Instead, we tackle another source of inefficiency more
                 prominent on embedded platforms--redundant computation
                 in the dispatch loop. To this end, we propose
                 Short-Circuit Dispatch (SCD), a low-cost architectural
                 extension that enables fast, hardware-based bytecode
                 dispatch with fewer instructions. The key idea of SCD
                 is to overlay the software-created bytecode jump table
                 on a branch target buffer (BTB). Once a bytecode is
                 fetched, the BTB is looked up using the bytecode,
                 instead of PC, as key. If it hits, the interpreter
                 directly jumps to the target address retrieved from the
                 BTB; otherwise, it goes through the original dispatch
                 path. This effectively eliminates redundant computation
                 in the dispatcher code for decode, bound check, and
                 target address calculation, thus significantly reducing
                 total instruction count. Our simulation results
                 demonstrate that SCD achieves geomean speedups of
                 19.9\% and 14.1\% for two production-grade script
                 interpreters for Lua and JavaScript, respectively.
                 Moreover, our fully synthesizable RTL design based on a
                 RISC-V embedded processor shows that SCD improves the
                 EDP of the Lua interpreter by 24.2\%, while increasing
                 the chip area by only 0.72\% at a 40nm technology
                 node.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
  remark =       "ISCA '16 conference proceedings.",
}

@Article{Lee:2016:AAB,
  author =       "Yunsup Lee and Andrew Waterman and Henry Cook and
                 Brian Zimmer and Ben Keller and Alberto Puggelli and
                 Jaehwa Kwak and Ruzica Jevtic and Stevo Bailey and
                 Milovan Blagojevic and Pi-Feng Chiu and Rimas Avizienis
                 and Brian Richards and Jonathan Bachrach and David
                 Patterson and Elad Alon and Bora Nikolic and Krste
                 Asanovic",
  title =        "An Agile Approach to Building {RISC-V}
                 Microprocessors",
  journal =      j-IEEE-MICRO,
  volume =       "36",
  number =       "2",
  pages =        "8--20",
  month =        mar # "\slash " # apr,
  year =         "2016",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2016.11",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Tue Apr 19 06:31:19 MDT 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "http://www.computer.org/csdl/mags/mi/2016/02/mmi2016020008-abs.html",
  abstract-URL = "http://www.computer.org/csdl/mags/mi/2016/02/mmi2016020008-abs.html",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
}

@InProceedings{Melo:2016:OBP,
  author =       "Cecil Accetti R. A. Melo and Edna Barros",
  editor =       "{IEEE}",
  booktitle =    "{2016 IEEE 27th International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP)}",
  title =        "{Oolong}: a Baseband processor extension to the
                 {RISC-V ISA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "241--242",
  year =         "2016",
  DOI =          "https://doi.org/10.1109/ASAP.2016.7760808",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Raveendran:2016:RVI,
  author =       "Aneesh Raveendran and Vinayak Baramu Patil and David
                 Selvakumar and Vivian Desalphine",
  editor =       "{IEEE}",
  booktitle =    "{2016 International Conference on VLSI Systems,
                 Architectures, Technology and Applications
                 (VLSI-SATA)}",
  title =        "A {RISC-V} instruction set
                 processor-micro-architecture design and analysis",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2016",
  DOI =          "https://doi.org/10.1109/VLSI-SATA.2016.7593047",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Tan:2016:NVC,
  author =       "Yong Kiam Tan and Magnus O. Myreen and Ramana Kumar
                 and Anthony Fox and Scott Owens and Michael Norrish",
  title =        "A new verified compiler backend for {CakeML}",
  journal =      j-SIGPLAN,
  volume =       "51",
  number =       "9",
  pages =        "60--73",
  month =        sep,
  year =         "2016",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/3022670.2951924",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sat Sep 16 10:18:13 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  abstract =     "We have developed and mechanically verified a new
                 compiler backend for CakeML. Our new compiler features
                 a sequence of intermediate languages that allows it to
                 incrementally compile away high-level features and
                 enables verification at the right levels of semantic
                 detail. In this way, it resembles mainstream
                 (unverified) compilers for strict functional languages.
                 The compiler supports efficient curried multi-argument
                 functions, configurable data representations,
                 exceptions that unwind the call stack, register
                 allocation, and more. The compiler targets several
                 architectures: x86-64, ARMv6, ARMv8, MIPS-64, and
                 RISC-V. In this paper, we present the overall structure
                 of the compiler, including its 12 intermediate
                 languages, and explain how everything fits together. We
                 focus particularly on the interaction between the
                 verification of the register allocator and the garbage
                 collector, and memory representations. The entire
                 development has been carried out within the HOL4
                 theorem prover.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  remark =       "ICFP '16 conference proceedings.",
}

@InProceedings{Zimmer:2016:RRC,
  author =       "Brian Zimmer and Pi-Feng Chiu and Borivoje Nikoli{\'c}
                 and Krste Asanovi{\'c}",
  editor =       "{IEEE}",
  booktitle =    "{2016 IEEE Asian Solid-State Circuits Conference
                 (A-SSCC)}",
  title =        "Reprogrammable redundancy for cache {Vmin} reduction
                 in a 28nm {RISC-V} processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "121--124",
  year =         "2016",
  DOI =          "https://doi.org/10.1109/ASSCC.2016.7844150",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Zimmer:2016:RVV,
  author =       "Brian Zimmer and Yunsup Lee and Alberto Puggelli and
                 Jaehwa Kwak and Ruzica Jevti{\'c} and Ben Keller and
                 Steven Bailey and Milovan Blagojevi{\'c} and Pi-Feng
                 Chiu and Hanh-Phuc Le and Po-Hung Chen and Nicholas
                 Sutardja and Rimas Avizienis and Andrew Waterman and
                 Brian Richards and Philippe Flatresse and Elad Alon and
                 Krste Asanovi{\'c} and Borivoje Nikoli{\'c}",
  title =        "A {RISC-V} Vector Processor With
                 Simultaneous-Switching Switched-Capacitor {DC--DC}
                 Converters in 28 nm {FDSOI}",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "51",
  number =       "4",
  pages =        "930--942",
  year =         "2016",
  CODEN =        "IJSCBC",
  DOI =          "https://doi.org/10.1109/JSSC.2016.2519386",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
}

@InProceedings{Amarnath:2017:CNT,
  author =       "Aporva Amarnath and Siying Feng and Subhankar Pal and
                 Tutu Ajayi and Austin Rovinski and Ronald G.
                 Dreslinski",
  editor =       "{IEEE}",
  booktitle =    "{2017 {IEEE\slash ACM} International Symposium on Low
                 Power Electronics and Design (ISLPED)}",
  title =        "A carbon nanotube transistor based {RISC-V} processor
                 using pass transistor logic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ISLPED.2017.8009156",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Baumann:2017:HNS,
  author =       "Andrew Baumann",
  editor =       "{ACM}",
  booktitle =    "{HotOS '17: Workshop on Hot Topics in Operating
                 Systems, Whistler, BC, Canada, May 7--10, 2017}",
  title =        "Hardware is the New Software",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "132--137",
  year =         "2017",
  DOI =          "https://doi.org/10.1145/3102980.3103002",
  bibdate =      "Mon Dec 18 14:09:09 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://dl.acm.org/doi/pdf/10.1145/3102980.3103002",
  acknowledgement = ack-nhfb,
  book-DOI =     "https://doi.org/10.1145/3102980",
  book-URL =     "https://dl.acm.org/doi/proceedings/10.1145/3102980",
  keywords =     "RISC-V",
}

@InProceedings{Dennis:2017:SCR,
  author =       "Don Kurian Dennis and Ayushi Priyam and Sukhpreet
                 Singh Virk and Sajal Agrawal and Tanuj Sharma and
                 Arijit Mondal and Kailash Chandra Ray",
  editor =       "{IEEE}",
  booktitle =    "{2017 7th International Symposium on Embedded
                 Computing and System Design (ISED)}",
  title =        "Single cycle {RISC-V} micro architecture processor and
                 its {FPGA} prototype",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ISED.2017.8303926",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Dietrich:2017:OVA,
  author =       "Christian Dietrich and Daniel Lohmann",
  title =        "{OSEK-V}: application-specific {RTOS} instantiation in
                 hardware",
  journal =      j-SIGPLAN,
  volume =       "52",
  number =       "4",
  pages =        "111--120",
  month =        may,
  year =         "2017",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/3140582.3081030",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sat Sep 16 10:18:15 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  abstract =     "The employment of a real-time operating system (RTOS)
                 in an embedded control systems is often an
                 all-or-nothing decision: While the RTOS-abstractions
                 provide for easier software composition and
                 development, the price in terms of event latencies and
                 memory costs are high. Especially in HW/SW codesign
                 settings, system developers try to avoid the employment
                 of a full-blown RTOS as far as possible. In OSEK-V, we
                 mitigate this trade-off by a very aggressive tailoring
                 of the concrete RTOS instance into the hardware.
                 Instead of implementing generic OS components as custom
                 hardware devices, we capture the actually possible
                 application-kernel interactions as a finite-state
                 machine and integrate the tailored RTOS semantics
                 directly into the processor pipeline. In our
                 experimental results with an OSEK-based implementation
                 of a quadrotor flight controller into the Rocket/RISC-V
                 softcore, we thereby can significantly reduce event
                 latencies, interrupt lock times, and memory footprint
                 at moderate costs in terms of FPGA resources.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  remark =       "LCTES '17 conference proceedings.",
}

@InProceedings{Duran:2017:SCP,
  author =       "Ckristian Duran and Luis E. Rueda G. and Andres Amaya
                 and Rolando Torres and Javier Ardila and Luis Rueda D.
                 and Giovanny Castillo and Anderson Agudelo and Camilo
                 Rojas and Luis Chaparro and Harry Hurtado and Juan
                 Romero and Wilmer Ramirez and Hector Gomez and Hugo
                 Hernandez and Elkim Roa",
  editor =       "{IEEE}",
  booktitle =    "{2017 IEEE 8th Latin American Symposium on Circuits \&
                 Systems (LASCAS)}",
  title =        "A system-on-chip platform for the {Internet of Things}
                 featuring a 32-bit {RISC-V} based microcontroller",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/LASCAS.2017.8126878",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Gautschi:2017:NTR,
  author =       "Michael Gautschi and Pasquale Davide Schiavone and
                 Andreas Traber and Igor Loi and Antonio Pullini and
                 Davide Rossi and Eric Flamand and Frank K.
                 G{\"u}rkaynak and Luca Benini",
  title =        "Near-Threshold {RISC-V} Core With {DSP} Extensions for
                 Scalable {IoT} Endpoint Devices",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "25",
  number =       "10",
  pages =        "2700--2713",
  year =         "2017",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2017.2654506",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}

@Article{Kapre:2017:HDR,
  author =       "Nachiket Kapre and Jan Gray",
  title =        "{Hoplite}: a Deflection-Routed Directional Torus {NoC}
                 for {FPGAs}",
  journal =      j-TRETS,
  volume =       "10",
  number =       "2",
  pages =        "14:1--14:??",
  month =        apr,
  year =         "2017",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3027486",
  ISSN =         "1936-7406 (print), 1936-7414 (electronic)",
  ISSN-L =       "1936-7406",
  bibdate =      "Sat Dec 23 10:23:01 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/trets.bib",
  abstract =     "We can design an FPGA-optimized lightweight
                 network-on-chip (NoC) router for flit-oriented
                 packet-switched communication that is an order of
                 magnitude smaller (in terms of LUTs and FFs) than
                 state-of-the-art FPGA overlay routers available today.
                 We present Hoplite, an efficient, lightweight, and fast
                 FPGA overlay NoC that is designed to be small and
                 compact by (1) using deflection routing instead of
                 buffered switching to eliminate expensive FIFO buffers
                 and (2) using a torus topology to reduce the cost of
                 switch crossbar. Buffering and crossbar implementation
                 complexities have traditionally limited speeds and
                 imposed heavy resource costs in conventional FPGA
                 overlay NoCs. We take care to exploit the fracturable
                 lookup tables (LUT) organization of the FPGA to further
                 improve the resource efficiency of mapping the
                 expensive crossbar multiplexers. Hoplite can outperform
                 classic, bidirectional, buffered mesh networks for
                 single-flit-oriented FPGA applications by as much as $
                 1.5 \times $ (best achievable throughputs for a $ 10
                 \times 10 $ system) or $ 2.5 \times $ (allocating same
                 amount of FPGA resources to both NoCs) for uniform
                 random traffic. When compared to buffered mesh
                 switches, FPGA-based deflection routers are $ \approx
                 3.5 \times $ smaller (HLS-generated switch) and $ 2.5
                 \times $ faster (clock period) for 32b payloads. In a
                 separate experiment, we hand-crafted an RTL version of
                 our switch with location constraints that requires only
                 60 LUTs and 100 FFs per router and runs at 2.9ns. We
                 conduct additional layout experiments on modern Xilinx
                 and Altera FPGAs and demonstrate wide-channel
                 chip-spanning layouts that run in excess of 300MHz
                 while consuming 10--15\% of overall chip resources. We
                 also demonstrate a clustered RISC-V multiprocessor
                 organization that uses Hoplite to help deliver the high
                 processing throughputs of the FPGA architecture to user
                 applications.",
  acknowledgement = ack-nhfb,
  articleno =    "14",
  fjournal =     "ACM Transactions on Reconfigurable Technology and
                 Systems (TRETS)",
  journal-URL =  "http://portal.acm.org/toc.cfm?id=J1151",
}

@Article{Keller:2017:RVP,
  author =       "Ben Keller and Martin Cochet and Brian Zimmer and
                 Jaehwa Kwak and Alberto Puggelli and Yunsup Lee and
                 Milovan Blagojevi{\'c} and Stevo Bailey and Pi-Feng
                 Chiu and Palmer Dabbelt and Colin Schmidt and Elad Alon
                 and Krste Asanovi{\'c} and Borivoje Nikoli{\'c}",
  title =        "A {RISC-V} Processor {SoC} With Integrated Power
                 Management at Submicrosecond Timescales in 28 nm
                 {FD-SOI}",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "52",
  number =       "7",
  pages =        "1863--1875",
  year =         "2017",
  CODEN =        "IJSCBC",
  DOI =          "https://doi.org/10.1109/JSSC.2017.2690859",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
}

@Article{Kim:2017:TAAa,
  author =       "Channoh Kim and Jaehyeok Kim and Sungmin Kim and
                 Dooyoung Kim and Namho Kim and Gitae Na and Young H. Oh
                 and Hyeon Gyu Cho and Jae W. Lee",
  title =        "Typed Architectures: Architectural Support for
                 Lightweight Scripting",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "45",
  number =       "1",
  pages =        "77--90",
  month =        mar,
  year =         "2017",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/3093337.3037726",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Jun 5 18:01:58 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/java2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Dynamic scripting languages are becoming more and more
                 widely adopted not only for fast prototyping but also
                 for developing production-grade applications. They
                 provide high-productivity programming environments
                 featuring high levels of abstraction with powerful
                 built-in functions, automatic memory management,
                 object-oriented programming paradigm and dynamic
                 typing. However, their flexible, dynamic type systems
                 easily become the source of inefficiency in terms of
                 instruction count, memory footprint, and energy
                 consumption. This overhead makes it challenging to
                 deploy these high-productivity programming technologies
                 on emerging single-board computers for IoT
                 applications. Addressing this challenge, this paper
                 introduces Typed Architectures, a high-efficiency,
                 low-cost execution substrate for dynamic scripting
                 languages, where each data variable retains high-level
                 type information at an ISA level. Typed Architectures
                 calculate and check the dynamic type of each variable
                 implicitly in hardware, rather than explicitly in
                 software, hence significantly reducing instruction
                 count for dynamic type checking. Besides, Typed
                 Architectures introduce polymorphic instructions (e.g.,
                 xadd), which are bound to the correct native
                 instruction at runtime within the pipeline (e.g., add
                 or fadd) to efficiently implement polymorphic
                 operators. Finally, Typed Architectures provide
                 hardware support for flexible yet efficient type tag
                 extraction and insertion, capturing common data layout
                 patterns of tag-value pairs. Our evaluation using a
                 fully synthesizable RISC-V RTL design on FPGA shows
                 that Typed Architectures achieve geomean speedups of
                 11.2\% and 9.9\% with maximum speedups of 32.6\% and
                 43.5\% for two production-grade scripting engines for
                 JavaScript and Lua, respectively. Moreover, Typed
                 Architectures improve the energy-delay product (EDP) by
                 19.3\% for JavaScript and 16.5\% for Lua with an area
                 overhead of 1.6\% at a 40nm technology node.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
  remark =       "ASPLOS'17 conference proceedings",
}

@Article{Kim:2017:TAAb,
  author =       "Channoh Kim and Jaehyeok Kim and Sungmin Kim and
                 Dooyoung Kim and Namho Kim and Gitae Na and Young H. Oh
                 and Hyeon Gyu Cho and Jae W. Lee",
  title =        "Typed Architectures: Architectural Support for
                 Lightweight Scripting",
  journal =      j-OPER-SYS-REV,
  volume =       "51",
  number =       "2",
  pages =        "77--90",
  month =        jun,
  year =         "2017",
  CODEN =        "OSRED8",
  DOI =          "https://doi.org/10.1145/3093315.3037726",
  ISSN =         "0163-5980 (print), 1943-586X (electronic)",
  ISSN-L =       "0163-5980",
  bibdate =      "Mon Jul 24 18:36:23 MDT 2017",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/opersysrev.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  abstract =     "Dynamic scripting languages are becoming more and more
                 widely adopted not only for fast prototyping but also
                 for developing production-grade applications. They
                 provide high-productivity programming environments
                 featuring high levels of abstraction with powerful
                 built-in functions, automatic memory management,
                 object-oriented programming paradigm and dynamic
                 typing. However, their flexible, dynamic type systems
                 easily become the source of inefficiency in terms of
                 instruction count, memory footprint, and energy
                 consumption. This overhead makes it challenging to
                 deploy these high-productivity programming technologies
                 on emerging single-board computers for IoT
                 applications. Addressing this challenge, this paper
                 introduces Typed Architectures, a high-efficiency,
                 low-cost execution substrate for dynamic scripting
                 languages, where each data variable retains high-level
                 type information at an ISA level. Typed Architectures
                 calculate and check the dynamic type of each variable
                 implicitly in hardware, rather than explicitly in
                 software, hence significantly reducing instruction
                 count for dynamic type checking. Besides, Typed
                 Architectures introduce polymorphic instructions (e.g.,
                 xadd), which are bound to the correct native
                 instruction at runtime within the pipeline (e.g., add
                 or fadd) to efficiently implement polymorphic
                 operators. Finally, Typed Architectures provide
                 hardware support for flexible yet efficient type tag
                 extraction and insertion, capturing common data layout
                 patterns of tag-value pairs. Our evaluation using a
                 fully synthesizable RISC-V RTL design on FPGA shows
                 that Typed Architectures achieve geomean speedups of
                 11.2\% and 9.9\% with maximum speedups of 32.6\% and
                 43.5\% for two production-grade scripting engines for
                 JavaScript and Lua, respectively. Moreover, Typed
                 Architectures improve the energy-delay product (EDP) by
                 19.3\% for JavaScript and 16.5\% for Lua with an area
                 overhead of 1.6\% at a 40nm technology node.",
  acknowledgement = ack-nhfb,
  fjournal =     "Operating Systems Review",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J597",
}

@Article{Kim:2017:TAAc,
  author =       "Channoh Kim and Jaehyeok Kim and Sungmin Kim and
                 Dooyoung Kim and Namho Kim and Gitae Na and Young H. Oh
                 and Hyeon Gyu Cho and Jae W. Lee",
  title =        "Typed Architectures: Architectural Support for
                 Lightweight Scripting",
  journal =      j-SIGPLAN,
  volume =       "52",
  number =       "4",
  pages =        "77--90",
  month =        apr,
  year =         "2017",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/3093336.3037726",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sat Sep 16 10:18:16 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  abstract =     "Dynamic scripting languages are becoming more and more
                 widely adopted not only for fast prototyping but also
                 for developing production-grade applications. They
                 provide high-productivity programming environments
                 featuring high levels of abstraction with powerful
                 built-in functions, automatic memory management,
                 object-oriented programming paradigm and dynamic
                 typing. However, their flexible, dynamic type systems
                 easily become the source of inefficiency in terms of
                 instruction count, memory footprint, and energy
                 consumption. This overhead makes it challenging to
                 deploy these high-productivity programming technologies
                 on emerging single-board computers for IoT
                 applications. Addressing this challenge, this paper
                 introduces Typed Architectures, a high-efficiency,
                 low-cost execution substrate for dynamic scripting
                 languages, where each data variable retains high-level
                 type information at an ISA level. Typed Architectures
                 calculate and check the dynamic type of each variable
                 implicitly in hardware, rather than explicitly in
                 software, hence significantly reducing instruction
                 count for dynamic type checking. Besides, Typed
                 Architectures introduce polymorphic instructions (e.g.,
                 xadd), which are bound to the correct native
                 instruction at runtime within the pipeline (e.g., add
                 or fadd) to efficiently implement polymorphic
                 operators. Finally, Typed Architectures provide
                 hardware support for flexible yet efficient type tag
                 extraction and insertion, capturing common data layout
                 patterns of tag-value pairs. Our evaluation using a
                 fully synthesizable RISC-V RTL design on FPGA shows
                 that Typed Architectures achieve geomean speedups of
                 11.2\% and 9.9\% with maximum speedups of 32.6\% and
                 43.5\% for two production-grade scripting engines for
                 JavaScript and Lua, respectively. Moreover, Typed
                 Architectures improve the energy-delay product (EDP) by
                 19.3\% for JavaScript and 16.5\% for Lua with an area
                 overhead of 1.6\% at a 40nm technology node.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  remark =       "ASPLOS '17 conference proceedings.",
}

@InProceedings{Koenig:2017:HAC,
  author =       "Jack Koenig and David Biancolin and Jonathan Bachrach
                 and Krste Asanovic",
  title =        "A Hardware Accelerator for Computing an Exact Dot
                 Product",
  crossref =     "Burgess:2017:ISC",
  pages =        "114--121",
  month =        jul,
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ARITH.2017.38",
  ISSN =         "1063-6889",
  bibdate =      "Fri Nov 17 09:10:14 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  abstract =     "We study the implementation of a hardware accelerator
                 that computes a dot product of IEEE-754 floating-point
                 numbers exactly. The accelerator uses a wide (640 or
                 4288 bits for single or double-precision respectively)
                 fixed-point representation into which intermediate
                 floating-point products are accumulated. We designed
                 the accelerator as a generator in Chisel, which can
                 synthesize various configurations of the accelerator
                 that make different area-performance trade-offs. We
                 integrated eight different configurations into an SoC
                 comprised of RISC-V in-order scalar core, split L1
                 instruction and data caches, and unified L2 cache. In a
                 TSMC 45 nm technology, the accelerator area ranges from
                 0.05 mm2 to 0.32 mm2, and all configurations could be
                 clocked at frequencies in excess of 900MHz. The
                 accelerator successfully saturates the SoC's memory
                 system, achieving the same per-element efficiency (1
                 cycle-per-element) as Intel MKL running on an x86
                 machine with a similar cache configuration.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point dot product; accurate
                 floating-point summation; area-performance trade-offs;
                 Bandwidth; cache configuration; cache storage; Chisel;
                 Coprocessors; data caches; exact dot product; fixed
                 point arithmetic; fixed-point representation; floating
                 point arithmetic; Generators; Hardware; hardware
                 accelerator; IEEE-754 floating-point numbers; Intel
                 MKL; intermediate floating-point products;
                 Microarchitecture; Registers; RISC-V in-order scalar
                 core; Rockets; size 45 nm; SoC memory system; split L1
                 instruction; system-on-chip; TSMC technology; unified
                 L2 cache",
}

@InProceedings{Li:2017:ADS,
  author =       "Lei Li and Michael Gautschi and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2017 27th International Symposium on Power and Timing
                 Modeling, Optimization and Simulation (PATMOS)}",
  title =        "Approximate {DIV} and {SQRT} instructions for the
                 {RISC-V ISA}: an efficiency vs. accuracy analysis",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/PATMOS.2017.8106987",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Matthews:2017:TNR,
  author =       "Eric Matthews and Lesley Shannon",
  editor =       "{IEEE}",
  booktitle =    "{2017 27th International Conference on Field
                 Programmable Logic and Applications (FPL)}",
  title =        "{TAIGA}: a new {RISC-V} soft-processor framework
                 enabling high performance {CPU} architectural
                 features",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2017",
  DOI =          "https://doi.org/10.23919/FPL.2017.8056766",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Menon:2017:SRV,
  author =       "A. Menon and S. Murugan and C. Rebeiro and N. Gala and
                 K. Veezhinathan",
  editor =       "{ACM}",
  booktitle =    "Proceedings of {Hardware and Architectural Support for
                 Security and Privacy (HASP), 25 June 2017, Toronto,
                 Canada}",
  title =        "{Shakti-T}: a {RISC-V} processor with light weight
                 security extensions",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "1--8",
  year =         "2017",
  DOI =          "https://doi.org/10.1145/3092627.3092629",
  ISBN =         "1-4503-5266-9",
  ISBN-13 =      "978-1-4503-5266-6",
  bibdate =      "Tue Dec 19 08:19:26 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3092627.3092629",
  abstract =     "With increased usage of compute cores for sensitive
                 applications, including e-commerce, there is a need to
                 provide additional hardware support for securing
                 information from memory based attacks. This work
                 presents a unified hardware framework for handling
                 spatial and temporal memory attacks. The paper
                 integrates the proposed hardware framework with a
                 RISC-V based micro-architecture with an enhanced
                 application binary interface that enables software
                 layers to use these features to protect sensitive data.
                 We demonstrate the effectiveness of the proposed scheme
                 through practical case studies in addition to taking
                 the design through a VLSI CAD design flow. The proposed
                 processor reduces the metadata storage overhead up to 4
                 x in comparison with the existing solutions, while
                 incurring an area overhead of just 1914 LUTs and 2197
                 flip flops on an FPGA, without affecting the critical
                 path delay of the processor.",
  acknowledgement = ack-nhfb,
}

@InProceedings{Olivieri:2017:IOP,
  author =       "Mauro Olivieri and Abdallah Cheikh and Gianmarco
                 Cerutti and Antonio Mastrandrea and Francesco
                 Menichelli",
  editor =       "{IEEE}",
  booktitle =    "{2017 New Generation of CAS (NGCAS)}",
  title =        "Investigation on the Optimal Pipeline Organization in
                 {RISC-V} Multi-threaded Soft Processor Cores",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "45--48",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/NGCAS.2017.61",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Patterson:2017:RIS,
  author =       "David Patterson",
  title =        "Reduced Instruction Set Computers Then and Now",
  journal =      j-COMPUTER,
  volume =       "50",
  number =       "12",
  pages =        "10--12",
  month =        dec,
  year =         "2017",
  CODEN =        "CPTRB4",
  DOI =          "https://doi.org/10.1109/MC.2017.4451206",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Sat Dec 23 07:58:37 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computer2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://www.computer.org/csdl/mags/co/2017/12/mco2017120010.html",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "RISC-I; RISC-V",
}

@Book{Patterson:2017:RVR,
  author =       "David Patterson and Andrew Waterman",
  title =        "The {RISC-V} Reader: an Open Architecture Atlas",
  publisher =    "Strawberry Canyon",
  address =      "San Francisco, CA, USA",
  pages =        "xiv + 180",
  year =         "2017",
  ISBN =         "0-9992491-1-8",
  ISBN-13 =      "978-0-9992491-1-6",
  LCCN =         "QA76.9.A73 P388 2017",
  bibdate =      "Mon Nov 18 18:47:27 MST 2019",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/master.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  shorttableofcontents = "RISC-V Reference Card / i \\
                 List of Figures / ix \\
                 Preface / xii \\
                 1 Why RISC-V? / 2 \\
                 2 RV32I: RISC-V Base Integer ISA / 14 \\
                 3 RISC-V Assembly Language / 32 \\
                 4 RV32M: Multiply and Divide / / 44 \\
                 5 RV32FD: Single/Double Floating Point / 48 \\
                 6 RV32A: Atomic / / 60 \\
                 7 RV32C: Compressed Instructions / 64 \\
                 8 RV32V: Vector / 72 \\
                 9 RV64: 64-bit Address Instructions / / 86 \\
                 10 RV32/64 Privileged Architecture / 100 \\
                 11 Future RISC-V Optional Extensions / 118 \\
                 Appendix A: RISC-V Instruction Listings / 120 \\
                 Appendix B: Transliteration from RISC-V / 168 \\
                 Index / 174",
  tableofcontents = "List of Figures / x \\
                 Preface / xii \\
                 1 Why RISC-V? / 2 \\
                 1.1 Introduction / 2 \\
                 1.2 Modular vs. Incremental ISAs / 4 \\
                 1.3 ISA Design 101 / 5 \\
                 1.4 An Overview of this Book / 10 \\
                 1.5 Concluding Remarks / 11 \\
                 1.6 To Learn More / 12 \\
                 2 RV32I: RISC-V Base Integer ISA / 14 \\
                 2.1 Introduction / 14 \\
                 2.2 RV32I Instruction formats / 14 \\
                 2.3 RV32I Registers / 18 \\
                 2.4 RV32I Integer Computation. / 18 \\
                 2.5 RV32I Loads and Stores / 20 \\
                 2.6 RV32I Conditional Branch / 21 \\
                 2.7 RV32I Unconditional Jump / 22 \\
                 2.8 RV32I Miscellaneous / 23 \\
                 2.9 Comparing RV32I, ARM-32, MIPS-32, and x86-32 / 23
                 \\
                 2.10 Concluding Remarks / 24 \\
                 2.11 To Learn More / 26 \\
                 3 RISC-V Assembly Language / 32 \\
                 3.1 Introduction / 32 \\
                 3.2 Calling convention / 32 \\
                 3.3 Assembly / 35 \\
                 3.4 Linker / 40 \\
                 3.5 Static vs. Dynamic Linking / 41 \\
                 3.6 Loader / 42 \\
                 3.7 Concluding Remarks / 42 \\
                 3.8 To Learn More / 42 \\
                 4 RV32M: Multiply and Divide / 44 \\
                 4.1 Introduction / 44 \\
                 4.2 Concluding Remarks / 46 \\
                 4.3 To Learn More / 46 \\
                 5 RV32FD: Single/Double Floating Point / 48 \\
                 5.1 Introduction / 48 \\
                 5.2 Floating-Point Registers / 48 \\
                 5.3 Floating-Point Loads, Stores, and Arithmetic / 49
                 \\
                 5.4 Floating-Point Moves and Converts / 53 \\
                 5.5 Miscellaneous Floating-Point Instructions / 53 \\
                 5.6 Comparing RV32FD, ARM-32, MIPS-32, and x86-32 using
                 DAXPY / 55 \\
                 5.7 Concluding Remarks / 55 \\
                 5.8 To Learn More / 56 \\
                 6 RV32A: Atomic / 60 \\
                 6.1 Introduction / 60 \\
                 6.2 Concluding Remarks / 62 \\
                 6.3 To Learn More / 62 \\
                 7 RV32C: Compressed Instructions / 64 \\
                 7 1 Introduction / 64 \\
                 7.2 Comparing RV32GC, Thumb-2, microMIPS, and x86-32 /
                 66 \\
                 7.3 Concluding Remarks / 66 \\
                 7.4 To Learn More / 67 \\
                 8. RV32V: Vector / 72 \\
                 8.1 Introduction / 72 \\
                 8.2 Vector Computation Instructions / 73 \\
                 8.3 Vector Registers and Dynamic Typing / 74 \\
                 8.4 Vector Loads and Stores / 75 \\
                 8.5 Parallelism During Vector Execution / 76 \\
                 8.6 Conditional Execution of Vector Operations / 76 \\
                 8.7 Miscellaneous Vector Instructions / 77 \\
                 8.8 Vector Example: DAXPY in RV32V / 78 \\
                 8.9 Comparing RV32V, MIPS-32 MSA SIMD, and x86-32 AVX
                 SIMD / 79 \\
                 8.10 Concluding Remarks / 81 \\
                 8.11 To Learn More / 82 \\
                 9 RV64: 64-bit Address Instructions / 86 \\
                 9.1 Introduction / 86 \\
                 9.2 Comparison to Other 64-bit ISAs using Insertion
                 Sort / 90 \\
                 9.3 Program size / 92 \\
                 9.4 Concluding Remarks / 93 \\
                 9.5 To Learn More / 93 \\
                 10 RV32/64 Privileged Architecture / 100 \\
                 10.1 Introduction / 100 \\
                 10.2 Machine Mode for Simple Embedded Systems. / 101
                 \\
                 10.3 Machine-Mode Exception Handling / 103 \\
                 10.4 User Mode and Process Isolation in Embedded
                 Systems / 106 \\
                 10.5 Supervisor Mode for Modern Operating Systems / 108
                 \\
                 10.6 Page-Based Virtual Memory / 111 \\
                 10.7 Identification and Performance CSRs / 114 \\
                 10.8 Concluding Remarks / 115 \\
                 10.9 To Learn More / 117 \\
                 11 Future RISC-V Optional Extensions / 118 \\
                 11.1 ``B'' Standard Extension for Bit Manipulation /
                 118 \\
                 11.2 ``E'' Standard Extension for Embedded / 118 \\
                 11.3 ``H'' Privileged Architecture Extension for
                 Hypervisor Support / 118 \\
                 11.4 ``J'' Standard Extension for Dynamically
                 Translated Languages / 118 \\
                 11.5 ``L'' Standard Extension for Decimal
                 Floating-Point / 118 \\
                 11.6 ``N'' Standard Extension for User-Level Interrupts
                 / 119 \\
                 11.7 ``P'' Standard Extension for Packed-SIMD
                 Instructions / 119 \\
                 11.8 ``Q'' Standard Extension for Quad-Precision
                 Floating-Point / 119 \\
                 11.9 Concluding Remarks / 119 \\
                 A RISC-V Instruction Listings / 120 \\
                 B Transliteration from RISC-V / 168 \\
                 B.1 Introduction / 168 \\
                 B.2 Comparing RV32I, ARM-32, and x86-32 using Tree Sum
                 / 170 \\
                 B.3 Conclusion / 171 \\
                 Index / 174",
}

@Misc{Patterson:2017:SIC,
  author =       "David Patterson and Andrew Waterman",
  title =        "{SIMD} Instructions Considered Harmful",
  howpublished = "ACM Web site",
  day =          "18",
  month =        sep,
  year =         "2017",
  bibdate =      "Mon Dec 18 13:49:13 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://www.sigarch.org/simd-instructions-considered-harmful/",
  abstract =     "In the process of writing a short introduction to
                 RISC-V, we compared RISC-V vector code to SIMD. We were
                 struck by the insidiousness of the SIMD instruction
                 extensions of ARM, MIPS, and x86. We decided to share
                 those insights in this blog, based on Chapter 8 of our
                 book.",
  acknowledgement = ack-nhfb,
}

@InProceedings{Salazar-Garcia:2017:RVB,
  author =       "Carlos Salazar-Garc{\'\i}a and Reinaldo
                 Castro-Gonz{\'a}lez and Alfonso
                 Chac{\'o}n-Rodr{\'\i}guez",
  editor =       "{IEEE}",
  booktitle =    "{2017 IEEE 8th Latin American Symposium on Circuits \&
                 Systems (LASCAS)}",
  title =        "{RISC-V} based sound classifier intended for acoustic
                 surveillance in protected natural environments",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/LASCAS.2017.7948070",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Sartori:2017:GFM,
  author =       "Marcos L. L. Sartori and Ney L. V. Calazans",
  editor =       "{IEEE}",
  booktitle =    "{2017 24th IEEE International Conference on
                 Electronics, Circuits and Systems (ICECS)}",
  title =        "{Go} functional model for a {RISC-V} asynchronous
                 organisation --- {ARV}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "381--348",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ICECS.2017.8292066",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/go.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Scheipel:2017:SAP,
  author =       "Tobias Scheipel and Fabian Mauroner and Marcel
                 Baunach",
  editor =       "{IEEE}",
  booktitle =    "{2017 Euromicro Conference on Digital System Design
                 (DSD)}",
  title =        "System-Aware Performance Monitoring Unit for {RISC-V}
                 Architectures",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "86--93",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/DSD.2017.28",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Schiavone:2017:SSW,
  author =       "Pasquale Davide Schiavone and Francesco Conti and
                 Davide Rossi and Michael Gautschi and Antonio Pullini
                 and Eric Flamand and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2017 27th International Symposium on Power and Timing
                 Modeling, Optimization and Simulation (PATMOS)}",
  title =        "Slow and steady wins the race? {A} comparison of
                 ultra-low-power {RISC-V} cores for {Internet-of-Things}
                 applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/PATMOS.2017.8106976",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Trippel:2017:TMMa,
  author =       "Caroline Trippel and Yatin A. Manerkar and Daniel
                 Lustig and Michael Pellauer and Margaret Martonosi",
  title =        "{TriCheck}: Memory Model Verification at the
                 Trisection of Software, Hardware, and {ISA}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "45",
  number =       "1",
  pages =        "119--133",
  month =        mar,
  year =         "2017",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/3093337.3037719",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Jun 5 18:01:58 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Memory consistency models (MCMs) which govern
                 inter-module interactions in a shared memory system,
                 are a significant, yet often under-appreciated, aspect
                 of system design. MCMs are defined at the various
                 layers of the hardware-software stack, requiring
                 thoroughly verified specifications, compilers, and
                 implementations at the interfaces between layers.
                 Current verification techniques evaluate segments of
                 the system stack in isolation, such as proving compiler
                 mappings from a high-level language (HLL) to an ISA or
                 proving validity of a microarchitectural implementation
                 of an ISA. This paper makes a case for full-stack MCM
                 verification and provides a toolflow, TriCheck, capable
                 of verifying that the HLL, compiler, ISA, and
                 implementation collectively uphold MCM requirements.
                 The work showcases TriCheck's ability to evaluate a
                 proposed ISA MCM in order to ensure that each layer and
                 each mapping is correct and complete. Specifically, we
                 apply TriCheck to the open source RISC-V ISA [55],
                 seeking to verify accurate, efficient, and legal
                 compilations from C11. We uncover under-specifications
                 and potential inefficiencies in the current RISC-V ISA
                 documentation and identify possible solutions for each.
                 As an example, we find that a RISC-V-compliant
                 microarchitecture allows 144 outcomes forbidden by C11
                 to be observed out of 1,701 litmus tests examined.
                 Overall, this paper demonstrates the necessity of
                 full-stack verification for detecting MCM-related bugs
                 in the hardware-software stack.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
  remark =       "ASPLOS'17 conference proceedings",
}

@Article{Trippel:2017:TMMb,
  author =       "Caroline Trippel and Yatin A. Manerkar and Daniel
                 Lustig and Michael Pellauer and Margaret Martonosi",
  title =        "{TriCheck}: Memory Model Verification at the
                 Trisection of Software, Hardware, and {ISA}",
  journal =      j-OPER-SYS-REV,
  volume =       "51",
  number =       "2",
  pages =        "119--133",
  month =        jun,
  year =         "2017",
  CODEN =        "OSRED8",
  DOI =          "https://doi.org/10.1145/3093315.3037719",
  ISSN =         "0163-5980 (print), 1943-586X (electronic)",
  ISSN-L =       "0163-5980",
  bibdate =      "Mon Jul 24 18:36:23 MDT 2017",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/opersysrev.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  abstract =     "Memory consistency models (MCMs) which govern
                 inter-module interactions in a shared memory system,
                 are a significant, yet often under-appreciated, aspect
                 of system design. MCMs are defined at the various
                 layers of the hardware-software stack, requiring
                 thoroughly verified specifications, compilers, and
                 implementations at the interfaces between layers.
                 Current verification techniques evaluate segments of
                 the system stack in isolation, such as proving compiler
                 mappings from a high-level language (HLL) to an ISA or
                 proving validity of a microarchitectural implementation
                 of an ISA. This paper makes a case for full-stack MCM
                 verification and provides a toolflow, TriCheck, capable
                 of verifying that the HLL, compiler, ISA, and
                 implementation collectively uphold MCM requirements.
                 The work showcases TriCheck's ability to evaluate a
                 proposed ISA MCM in order to ensure that each layer and
                 each mapping is correct and complete. Specifically, we
                 apply TriCheck to the open source RISC-V ISA [55],
                 seeking to verify accurate, efficient, and legal
                 compilations from C11. We uncover under-specifications
                 and potential inefficiencies in the current RISC-V ISA
                 documentation and identify possible solutions for each.
                 As an example, we find that a RISC-V-compliant
                 microarchitecture allows 144 outcomes forbidden by C11
                 to be observed out of 1,701 litmus tests examined.
                 Overall, this paper demonstrates the necessity of
                 full-stack verification for detecting MCM-related bugs
                 in the hardware-software stack.",
  acknowledgement = ack-nhfb,
  fjournal =     "Operating Systems Review",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J597",
}

@Article{Trippel:2017:TMMc,
  author =       "Caroline Trippel and Yatin A. Manerkar and Daniel
                 Lustig and Michael Pellauer and Margaret Martonosi",
  title =        "{TriCheck}: Memory Model Verification at the
                 Trisection of Software, Hardware, and {ISA}",
  journal =      j-SIGPLAN,
  volume =       "52",
  number =       "4",
  pages =        "119--133",
  month =        apr,
  year =         "2017",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/3093336.3037719",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Sat Sep 16 10:18:16 MDT 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  abstract =     "Memory consistency models (MCMs) which govern
                 inter-module interactions in a shared memory system,
                 are a significant, yet often under-appreciated, aspect
                 of system design. MCMs are defined at the various
                 layers of the hardware-software stack, requiring
                 thoroughly verified specifications, compilers, and
                 implementations at the interfaces between layers.
                 Current verification techniques evaluate segments of
                 the system stack in isolation, such as proving compiler
                 mappings from a high-level language (HLL) to an ISA or
                 proving validity of a microarchitectural implementation
                 of an ISA. This paper makes a case for full-stack MCM
                 verification and provides a toolflow, TriCheck, capable
                 of verifying that the HLL, compiler, ISA, and
                 implementation collectively uphold MCM requirements.
                 The work showcases TriCheck's ability to evaluate a
                 proposed ISA MCM in order to ensure that each layer and
                 each mapping is correct and complete. Specifically, we
                 apply TriCheck to the open source RISC-V ISA [55],
                 seeking to verify accurate, efficient, and legal
                 compilations from C11. We uncover under-specifications
                 and potential inefficiencies in the current RISC-V ISA
                 documentation and identify possible solutions for each.
                 As an example, we find that a RISC-V-compliant
                 microarchitecture allows 144 outcomes forbidden by C11
                 to be observed out of 1,701 litmus tests examined.
                 Overall, this paper demonstrates the necessity of
                 full-stack verification for detecting MCM-related bugs
                 in the hardware-software stack.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  remark =       "ASPLOS '17 conference proceedings.",
}

@InProceedings{Wang:2017:LWF,
  author =       "Angie Wang and Brian Richards and Palmer Dabbelt and
                 Howard Mao and Stevo Bailey and Jaeduk Han and Eric
                 Chang and James Dunn and Elad Alon and Borivoje
                 Nikoli{\'c}",
  editor =       "{IEEE}",
  booktitle =    "{2017 IEEE Asian Solid-State Circuits Conference
                 (A-SSCC)}",
  title =        "A 0.37mm2 {LTE\slash Wi-Fi} compatible, memory-based,
                 runtime-reconfigurable 2n3m5k {FFT} accelerator
                 integrated with a {RISC-V} core in 16nm {FinFET}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "305--308",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ASSCC.2017.8240277",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wang:2017:RFH,
  author =       "Yanpeng Wang and Mei Wen and Chunyuan Zhang and Jie
                 Lin",
  editor =       "{IEEE}",
  booktitle =    "{2017 IEEE 28th International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP)}",
  title =        "{RVNet}: a fast and high energy efficiency network
                 packet processing system on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "107--110",
  year =         "2017",
  DOI =          "https://doi.org/10.1109/ASAP.2017.7995266",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Zimmer:2017:RRS,
  author =       "Brian Zimmer and Pi-Feng Chiu and Borivoje Nikoli{\'c}
                 and Krste Asanovi{\'c}",
  title =        "Reprogrammable Redundancy for {SRAM}-Based Cache {$
                 V_{\min } $} Reduction in a 28-nm {RISC-V} Processor",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "52",
  number =       "10",
  pages =        "2589--2600",
  year =         "2017",
  CODEN =        "IJSCBC",
  DOI =          "https://doi.org/10.1109/JSSC.2017.2715798",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
}

@InProceedings{Alizadeh:2018:ERV,
  author =       "M. Alizadeh and M. Sharifkhani",
  editor =       "{IEEE}",
  booktitle =    "{2018 8th International Conference on Computer and
                 Knowledge Engineering (ICCKE)}",
  title =        "Extending {RISC-V ISA} for Accelerating the
                 {H.265\slash HEVC} Deblocking Filter",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "126--129",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ICCKE.2018.8566467",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Bailey:2018:GMS,
  author =       "Stevo Bailey and Jaeduk Han and Paul Rigge and Richard
                 Lin and Eric Chang and Howard Mao and Zhongkai Wang and
                 Chick Markley and Adam Izraelevitz and Angie Wang and
                 Nathan Narevsky and Woorham Bae and Steve Shauck and
                 Sergio Montano and Justin Norsworthy and Munir Razzaque
                 and Wen Hau Ma and Akalu Lentiro and Matthew Doerflein
                 and Darin Heckendorn and Jim McGrath and Franco DeSeta
                 and Ronen Shoham and Mike Stellfox and Mark Snowden and
                 Joseph Cole and Dan Fuhrman and Brian Richards and
                 Jonathan Bachrach and Elad Alon and Borivoje
                 Nikoli{\'c}",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE Asian Solid-State Circuits Conference
                 (A-SSCC)}",
  title =        "A Generated Multirate Signal Analysis {RISC-V SoC} in
                 16nm {FinFET}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "285--288",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ASSCC.2018.8579326",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Budi:2018:RVI,
  author =       "Suseela Budi and Pradeep Gupta and Kuruvilla Varghese
                 and Amrutur Bharadwaj",
  editor =       "{IEEE}",
  booktitle =    "{2018 International Symposium on Devices, Circuits and
                 Systems (ISDCS)}",
  title =        "A {RISC-V ISA} compatible processor {IP} for {SoC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ISDCS.2018.8379629",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Cai:2018:IDR,
  author =       "Jingyong Cai and Masashi Takemoto and Hironori
                 Nakajo",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE 7th Global Conference on Consumer
                 Electronics (GCCE)}",
  title =        "Implementation of {DNN} on a {RISC-V} Open Source
                 Microprocessor for {IoT} devices",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "295--299",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/GCCE.2018.8574663",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Chiu:2018:CRT,
  author =       "Pi-Feng Chiu and Christopher Celio and Krste
                 Asanovi{\'c} and Borivoje Nikoli{\'c} and David
                 Patterson",
  title =        "Cache Resiliency Techniques for a Low-Voltage {RISC-V}
                 Out-of-Order Processor in 28-nm {CMOS}",
  journal =      "IEEE Solid-State Circuits Letters",
  volume =       "1",
  number =       "12",
  pages =        "229--232",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/LSSC.2019.2900148",
  ISSN =         "2573-9603",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Chiu:2018:ORV,
  author =       "Pi-Feng Chiu and Christopher Celio and Krste
                 Asanovi{\'c} and David Patterson and Borivoje
                 Nikoli{\'c}",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE Symposium on VLSI Circuits}",
  title =        "An Out-of-Order {RISC-V} Processor with Resilient
                 Low-Voltage Operation in {28NM CMOS}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "61--62",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/VLSIC.2018.8502320",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Cho:2018:IMD,
  author =       "Hyungmin Cho",
  title =        "Impact of Microarchitectural Differences of {RISC-V}
                 Processor Cores on Soft Error Effects",
  journal =      j-IEEE-ACCESS,
  volume =       "6",
  number =       "",
  pages =        "41302--41313",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ACCESS.2018.2858773",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  note =         "See correction \cite{Cho:2019:CIM}.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Chupilko:2018:TPG,
  author =       "Mikhail Chupilko and Alexander Kamkin and Artem
                 Kotsynyak and Alexander Protsenko and Sergey Smolov and
                 Andrei Tatarnikov",
  editor =       "{IEEE}",
  booktitle =    "{2018 19th International Workshop on Microprocessor
                 and SOC Test and Verification (MTV)}",
  title =        "Test Program Generator {MicroTESK} for {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "6--11",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/MTV.2018.00011",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Davidson:2018:COS,
  author =       "Scott Davidson and Shaolin Xie and Christopher Torng
                 and Khalid Al-Hawai and Austin Rovinski and Tutu Ajayi
                 and Luis Vega and Chun Zhao and Ritchie Zhao and Steve
                 Dai and Aporva Amarnath and Bandhav Veluri and Paul Gao
                 and Anuj Rao and Gai Liu and Rajesh K. Gupta and Zhiru
                 Zhang and Ronald Dreslinski and Christopher Batten and
                 Michael Bedford Taylor",
  title =        "The {Celerity} Open-Source 511-Core {RISC-V} Tiered
                 Accelerator Fabric: Fast Architectures and Design
                 Methodologies for Fast Chips",
  journal =      j-IEEE-MICRO,
  volume =       "38",
  number =       "2",
  pages =        "30--41",
  month =        mar # "\slash " # apr,
  year =         "2018",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2018.022071133",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Apr 28 13:18:45 MDT 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/gnu.bib;
                 https://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://www.computer.org/csdl/mags/mi/2018/02/mmi2018020030-abs.html",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
}

@Article{Delshadtehrani:2018:NPM,
  author =       "Leila Delshadtehrani and Schuyler Eldridge and
                 Sadullah Canakci and Manuel Egele and Ajay Joshi",
  title =        "{Nile}: a Programmable Monitoring Coprocessor",
  journal =      j-IEEE-COMPUT-ARCHIT-LETT,
  volume =       "17",
  number =       "1",
  pages =        "92--95",
  month =        jan # "\slash " # jun,
  year =         "2018",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/LCA.2017.2784416",
  ISSN =         "1556-6056 (print), 1556-6064 (electronic)",
  ISSN-L =       "1556-6056",
  bibdate =      "Tue Jun 25 07:41:05 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeecomputarchitlett.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  abstract =     "Researchers widely employ hardware performance
                 counters (HPCs) as well as debugging and profiling
                 tools in processors for monitoring different events
                 such as cache hits, cache misses, and branch prediction
                 statistics during the execution of programs. The
                 collected information can be used for power,
                 performance, and thermal management of the system as
                 well as detecting anomalies or malicious behavior in
                 the software. However, monitoring new or complex events
                 using HPCs and existing tools is a challenging task
                 because HPCs only provide a fixed pool of raw events to
                 monitor. To address this challenge, we propose the
                 implementation of a programmable hardware monitor in a
                 complete system framework including the hardware
                 monitor architecture and its interface with an in-order
                 single-issue RISC-V processor as well as an operating
                 system. As a proof of concept, we demonstrate how to
                 programmatically implement a shadow stack using our
                 hardware monitor and how the programmed shadow stack
                 detects stack buffer overflow attacks. Our hardware
                 monitor design incurs a 26 percent power overhead and a
                 15 percent area overhead over an unmodified RISC-V
                 processor. Our programmed shadow stack has less than 3
                 percent performance overhead in the worst case.",
  acknowledgement = ack-nhfb,
  affiliation =  "Delshadtehrani, L (Reprint Author), Boston Univ, Dept
                 Elect \& Comp Engn, Boston, MA 02215 USA.
                 Delshadtehrani, Leila; Eldridge, Schuyler; Canakci,
                 Sadullah; Egele, Manuel; Joshi, Ajay, Boston Univ, Dept
                 Elect \& Comp Engn, Boston, MA 02215 USA.",
  author-email = "delshad@bu.edu schuye@bu.edu scanakci@bu.edu
                 megele@bu.edu joshi@bu.edu",
  da =           "2019-06-20",
  doc-delivery-number = "FZ6EO",
  eissn =        "1556-6064",
  fjournal =     "IEEE Computer Architecture Letters",
  funding-acknowledgement = "NSF [CCF-1533663]",
  funding-text = "We thank Prof. Jonathan Appavoo for providing
                 invaluable help in designing the OS support and the
                 software interface for Nile. This work was supported in
                 part by NSF grant CCF-1533663.",
  journal-iso =  "IEEE Comput. Archit. Lett.",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10208",
  keywords =     "branch prediction statistics; cache hits; cache
                 misses; cache storage; complete system framework;
                 complex events; coprocessors; Coprocessors; debugging;
                 fixed pool; Hardware; Hardware coprocessor; hardware
                 monitor architecture; hardware monitor design; hardware
                 performance counters; HPCs; Linux; malicious behavior;
                 Monitoring; Nile; operating system; operating systems
                 (computers); Pattern matching; performance evaluation;
                 performance overhead; power overhead; profiling tools;
                 Program processors; programmable hardware; programmable
                 hardware monitor; programmable monitoring coprocessor;
                 programmed shadow stack; raw events; reduced
                 instruction set computing; Rockets; security; shadow
                 stack; single-issue RISC-V processor; stack buffer
                 overflow attack; stack buffer overflow attacks; thermal
                 management; unmodified RISC-V processor",
  number-of-cited-references = "17",
  ORCID-numbers = "Joshi, AJay/0000-0002-3256-9942",
  research-areas = "Computer Science",
  times-cited =  "0",
  unique-id =    "Delshadtehrani:2018:NPM",
  web-of-science-categories = "Computer Science, Hardware \&
                 Architecture",
}

@InProceedings{Elmohr:2018:RFG,
  author =       "Mahmoud A. Elmohr and Ahmed S. Eissa and Moamen
                 Ibrahim and Mostafa Khamis and Sameh El-Ashry and Ahmed
                 Shalaby and Mohamed AbdElsalam and M. Watheq
                 El-Kharashi",
  editor =       "{IEEE}",
  booktitle =    "{2018 26th Euromicro International Conference on
                 Parallel, Distributed and Network-based Processing
                 (PDP)}",
  title =        "{RVNoC}: a Framework for Generating {RISC-V NoC-Based
                 MPSoC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "617--621",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/PDP2018.2018.00103",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Flamand:2018:GRV,
  author =       "Eric Flamand and Davide Rossi and Francesco Conti and
                 Igor Loi and Antonio Pullini and Florent Rotenberg and
                 Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE 29th International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP)}",
  title =        "{GAP-8}: a {RISC-V SoC} for {AI} at the Edge of the
                 {IoT}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ASAP.2018.8445101",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ghosh:2018:TMT,
  author =       "Kunal Promode Ghosh and Anagha K. Ghosh",
  editor =       "{IEEE}",
  booktitle =    "{2018 China Semiconductor Technology International
                 Conference (CSTIC)}",
  title =        "Technology mediated tutorial on {RISC-V CPU} core
                 implementation and sign-off using revolutionary {EDA}
                 management system {(EMS)} --- {VSDFLOW}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--3",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/CSTIC.2018.8369332",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gur:2018:FIB,
  author =       "Etki G{\"u}r and Zekiye Eda Sataner and Yusuf H.
                 Durkaya and Salih Bayar",
  editor =       "{IEEE}",
  booktitle =    "{2018 International Symposium on Fundamentals of
                 Electrical Engineering (ISFEE)}",
  title =        "{FPGA} Implementation of 32-bit {RISC-V} Processor
                 with Web-Based Assembler--Disassembler",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ISFEE.2018.8742406",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Hennessy:2018:NGA,
  author =       "John Hennessy and David Patterson",
  editor =       "{IEEE}",
  booktitle =    "{2018 ACM\slash IEEE 45th Annual International
                 Symposium on Computer Architecture: 1--6 June 2018, Los
                 Angeles, CA, USA}",
  title =        "A new golden age for computer architecture:
                 Domain-specific hardware\slash software co-design,
                 enhanced",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "27--29",
  year =         "2018",
  ISBN =         "1-5386-5985-9 (e-book)",
  ISBN-13 =      "978-1-5386-5985-4 (e-book)",
  LCCN =         "QA76.9.A73 .A568 2018",
  bibdate =      "Tue Dec 19 07:57:34 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Herdt:2018:ECR,
  author =       "Vladimir Herdt and Daniel Gro{\ss}e and Hoang M. Le
                 and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2018 Forum on Specification \& Design Languages
                 (FDL)}",
  title =        "Extensible and Configurable {RISC-V} Based Virtual
                 Prototype",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "5--16",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/FDL.2018.8524047",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ishimaru:2018:FBR,
  author =       "Pedro J. A. Ishimaru and Antonyus P. A. Ferreira and
                 Vanessa O. Ogg and R. A. M. Cecil Accetti and Edna N.
                 S. Barros",
  editor =       "{IEEE}",
  booktitle =    "{2018 31st Symposium on Integrated Circuits and
                 Systems Design (SBCCI)}",
  title =        "An {FPGA-Based RFID} Baseband Processor Using a
                 {RISC-V} Platform",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/SBCCI.2018.8533242",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Khamis:2018:CRV,
  author =       "Mostafa Khamis and Sameh El-Ashry and Ahmed Shalaby
                 and Mohamed AbdElsalam and M. Watheq El-Kharashi",
  editor =       "{IEEE}",
  booktitle =    "{2018 11th International Workshop on Network on Chip
                 Architectures (NoCArc)}",
  title =        "A Configurable {RISC-V} for {NoC}-Based {MPSoCs}: a
                 Framework for Hardware Emulation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/NOCARC.2018.8541158",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Leidel:2018:GRV,
  author =       "John D. Leidel and Xi Wang and Yong Chen",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE High Performance extreme Computing
                 Conference (HPEC)}",
  title =        "{GoblinCore-64}: a {RISC-V} Based Architecture for
                 Data Intensive Computing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/HPEC.2018.8547560",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lupori:2018:THP,
  author =       "Leandro Lupori and Vanderson Rosario and Edson Borin",
  editor =       "{IEEE}",
  booktitle =    "{2018 Symposium on High Performance Computing Systems
                 (WSCAD)}",
  title =        "Towards a High-Performance {RISC-V} Emulator",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "213--220",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/WSCAD.2018.00041",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Matthews:2018:EPE,
  author =       "Eric Matthews and Zavier Aguila and Lesley Shannon",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE 26th Annual International Symposium on
                 Field-Programmable Custom Computing Machines (FCCM)}",
  title =        "Evaluating the Performance Efficiency of a
                 Soft-Processor, Variable-Length,
                 Parallel-Execution-Unit Architecture for {FPGAs} Using
                 the {RISC-V ISA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/FCCM.2018.00010",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Munir:2018:FRV,
  author =       "Abdelfattah Munir and Mina Magdy and Samer Ahmed and
                 Sherouk Nasr and Sameh El-Ashry and Ahmed Shalaby",
  editor =       "{IEEE}",
  booktitle =    "{2018 19th International Workshop on Microprocessor
                 and SOC Test and Verification (MTV)}",
  title =        "Fast Reliable Verification Methodology for {RISC-V}
                 Without a Reference Model",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "12--17",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/MTV.2018.00012",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Oh:2018:DGS,
  author =       "Hyunyoung Oh and Junmo Park and Myonghoon Yang and
                 Dongil Hwang and Yunheung Paek",
  editor =       "{IEEE}",
  booktitle =    "{2018 International SoC Design Conference (ISOCC)}",
  title =        "Design of a Generic Security Interface for {RISC-V}
                 Processors and its Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "40--41",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ISOCC.2018.8649968",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Palmiero:2018:DID,
  author =       "Christian Palmiero and Giuseppe {Di Guglielmo} and
                 Luciano Lavagno and Luca P. Carloni",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE High Performance extreme Computing
                 Conference (HPEC)}",
  title =        "Design and Implementation of a Dynamic Information
                 Flow Tracking Architecture to Secure a {RISC-V} Core
                 for {IoT} Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/HPEC.2018.8547578",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Patterson:2018:YCA,
  author =       "David Patterson",
  editor =       "{IEEE}",
  booktitle =    "{2018 IEEE International Solid-State Circuits
                 Conference --- (ISSCC)}",
  title =        "50 Years of computer architecture: From the mainframe
                 {CPU} to the domain-specific {TPU} and the open
                 {RISC-V} instruction set",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "27--31",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ISSCC.2018.8310168",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "TPU (Tensor Processing Unit)",
}

@InProceedings{Pekkarinen:2018:MRV,
  author =       "Esko Pekkarinen and Timo D. H{\"a}m{\"a}l{\"a}inen",
  editor =       "{IEEE}",
  booktitle =    "{2018 21st Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "Modeling {RISC-V} Processor in {IP-XACT}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "140--147",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/DSD.2018.00036",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Richmond:2018:ECT,
  author =       "Dustin Richmond and Michael Barrow and Ryan Kastner",
  editor =       "{IEEE}",
  booktitle =    "{2018 28th International Conference on Field
                 Programmable Logic and Applications (FPL)}",
  title =        "Everyone's a Critic: a Tool for Exploring {RISC-V}
                 Projects",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "260--2604",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/FPL.2018.00052",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Schiavone:2018:OSV,
  author =       "Pasquale Davide Schiavone and Ernesto Sanchez and
                 Annachiara Ruospo and Francesco Minervini and Florian
                 Zaruba and Germain Haugou and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2018 {IFIP\slash IEEE} International Conference on
                 Very Large Scale Integration (VLSI-SoC)}",
  title =        "An Open-Source Verification Framework for Open-Source
                 Cores: a {RISC-V} Case Study",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "43--48",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/VLSI-SoC.2018.8644818",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Uytterhoeven:2018:SPC,
  author =       "Roel Uytterhoeven and Wim Dehaene",
  editor =       "{IEEE}",
  booktitle =    "{ESSCIRC 2018 --- IEEE 44th European Solid State
                 Circuits Conference (ESSCIRC)}",
  title =        "A sub 10 {pJ\slash Cycle} Over a 2 to 200 {MHz}
                 Performance Range {RISC-V} Microprocessor in 28 nm
                 {FDSOI}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "236--239",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ESSCIRC.2018.8494259",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wang:2018:RTA,
  author =       "Angie Wang and Woorham Bae and Jaeduk Han and Stevo
                 Bailey and Paul Rigge and Orhan Ocal and Zhongkai Wang
                 and Kannan Ramchandran and Elad Alon and Borivoje
                 Nikoli{\'c}",
  editor =       "{IEEE}",
  booktitle =    "{ESSCIRC 2018 --- IEEE 44th European Solid State
                 Circuits Conference (ESSCIRC)}",
  title =        "A Real-Time, {Analog\slash Digital} Co-Designed
                 {1.89-GHz} Bandwidth, {175-kHz} Resolution Sparse
                 Spectral Analysis {RISC-V SoC} in 16-nm {FinFET}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "322--325",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ESSCIRC.2018.8494317",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhang:2018:DRC,
  author =       "Quan Zhang and Yujie Huang and Yujie Cai and Yalong
                 Pang and Jun Han",
  editor =       "{IEEE}",
  booktitle =    "{2018 14th IEEE International Conference on
                 Solid-State and Integrated Circuit Technology
                 (ICSICT)}",
  title =        "Design of {RLWE} Cryptoprocessor Based on
                 Vector-Instruction Extension with {RISC-V}
                 Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--3",
  year =         "2018",
  DOI =          "https://doi.org/10.1109/ICSICT.2018.8564985",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Auer:2019:SAR,
  author =       "Lukas Auer and Christian Skubich and Matthias Hiller",
  editor =       "{IEEE}",
  booktitle =    "{2019 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "A Security Architecture for {RISC-V} based {IoT}
                 Devices",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1154--1159",
  year =         "2019",
  DOI =          "https://doi.org/10.23919/DATE.2019.8714822",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Bailey:2019:MSR,
  author =       "Steven Bailey and Paul Rigge and Jaeduk Han and
                 Richard Lin and Eric Y. Chang and Howard Mao and
                 Zhongkai Wang and Chick Markley and Adam M. Izraelevitz
                 and Angie Wang and Nathan Narevsky and Woorham Bae and
                 Steve Shauck and Sergio Montano and Justin Norsworthy
                 and Munir Razzaque and Wen Hau Ma and Akalu Lentiro and
                 Matthew Doerflein and Darin Heckendorn and Jim McGrath
                 and Franco DeSeta and Ronen Shoham and Mike Stellfox
                 and Mark Snowden and Joseph Cole and Daniel R. Fuhrman
                 and Brian Richards and Jonathan Bachrach and Elad Alon
                 and Borivoje Nikoli{\'c}",
  title =        "A Mixed-Signal {RISC-V} Signal Analysis {SoC}
                 Generator With a 16-nm {FinFET} Instance",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "54",
  number =       "10",
  pages =        "2786--2801",
  year =         "2019",
  CODEN =        "IJSCBC",
  DOI =          "https://doi.org/10.1109/JSSC.2019.2924090",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
}

@InProceedings{Bocco:2019:DPN,
  author =       "Andrea Bocco and Yves Durand and Florent de Dinechin",
  title =        "Dynamic Precision Numerics Using a Variable-Precision
                 {UNUM Type I HW} Coprocessor",
  crossref =     "Takagi:2019:ISC",
  pages =        "104--107",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00028",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  abstract =     "A very large internal accumulation register has been
                 proposed to increase the accuracy of scientific code.
                 However, there is a general class of iterative kernels
                 where a vector of high-precision data must be saved
                 from one iteration to the next. Saving the large
                 internal accumulator to memory is impractical in such
                 cases. This work proposes a Variable Precision (VP)
                 Floating Point (FP) arithmetic co-processor
                 architecture based on RISC-V, which 1/ supports legacy
                 IEEE formats for input and output variables, 2/ uses
                 variable length internal registers (up to 512 bits of
                 mantissa) for inner loop multiply-add and 3/ supports
                 loads and stores of intermediate results to cache
                 memory with a dynamically adjustable precision (up to
                 256 bits of mantissa). It exploits the UNUM type I
                 floating point format, proposing solutions to address
                 some of its pitfalls such as the variable latency of
                 the internal operation, and the variable memory
                 footprint of the intermediate variables. This work is
                 integrated on FPGA and demonstrated on a representative
                 example.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26; Arrays; cache storage; Computational
                 modeling; coprocessors; Coprocessors; dynamic Precision
                 numerics; field programmable gate arrays; floating
                 point arithmetic; floating point arithmetic
                 co-processor architecture; FPGA; internal accumulation
                 register; iterative kernels; iterative methods; Kernel;
                 Programming; reduced instruction set computing;
                 Registers; RISC-V; Variable Precision; Variable
                 precision, Floating-point, UNUM, Scientific computing,
                 Instruction set design, Hardware architecture, RISC-V,
                 Coprocessor, Multiple precision, FPGA, ASIC;
                 variable-precision UNUM Type I HW coprocessor",
}

@InProceedings{Bocco:2019:SSM,
  author =       "Andrea Bocco and Yves Durand and Florent de Dinechin",
  title =        "{SMURF}: {Scalar Multiple-precision Unum RISC-V
                 Floating-point} Accelerator for Scientific Computing",
  crossref =     "Gustafson:2019:PCN",
  pages =        "1:1--1:8",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316279.3316280",
  bibdate =      "Mon Feb 10 09:31:49 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://hal.inria.fr/hal-02087098",
  abstract =     "This paper proposes an innovative Floating Point (FP)
                 architecture for Variable Precision (VP) computation
                 suitable for high precision FP computing, based on a
                 refined version of the UNUM type I format. This
                 architecture supports VP FP intervals where each
                 interval endpoint can have up to 512 bits of mantissa.
                 The proposed hardware architecture is pipelined and has
                 an internal word-size of 64 bits. Computations on
                 longer mantissas are performed iteratively on the
                 existing hardware. The prototype is integrated in a
                 RISC-V environment, it is exposed to the user through
                 an instruction set extension. The paper we provide an
                 example of software usage. The system has been
                 prototyped on a FPGA (Field-Programmable Gate Array)
                 platform and also synthesized for a 28nm FDSOI process
                 technology. The respective working frequency of FPGA
                 and ASIC implementations are 50MHz and 600MHz. The
                 estimated chip area is 1.5mm 2 and the estimated power
                 consumption is 95mW. The flops performance of this
                 architecture remains within the range of a regular
                 fixed-precision IEEE FPU while enabling arbitrary
                 precision computation at reasonable cost.",
  acknowledgement = ack-nhfb,
  articleno =    "Article 1",
  keywords =     "ASIC, UNUM, Floating-point, RISC-V, Coprocessor,
                 Instruction set design, Variable precision, Scientific
                 computing, Hardware architecture, Multiple precision,
                 FPGA",
}

@InProceedings{Calicchia:2019:DSP,
  author =       "L. Calicchia and V. Ciotoli and G. C. Cardarilli and
                 L. di Nunzio and R. Fazzolari and A. Nannarelli and M.
                 Re",
  editor =       "{IEEE}",
  booktitle =    "{2019 26th IEEE International Conference on
                 Electronics, Circuits and Systems (ICECS)}",
  title =        "Digital Signal Processing Accelerator for {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "703--706",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ICECS46596.2019.8964670",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Cho:2019:CIM,
  author =       "Hyungmin Cho",
  title =        "Correction to {``Impact of Microarchitectural
                 Differences of RISC-V Processor Cores on Soft Error
                 Effects''}",
  journal =      j-IEEE-ACCESS,
  volume =       "7",
  number =       "",
  pages =        "35034--35034",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ACCESS.2019.2904033",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  note =         "See \cite{Cho:2018:IMD}.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Chupilko:2019:OSV,
  author =       "Mikhail Chupilko and Alexander Kamkin and Alexander
                 Protsenko",
  editor =       "{IEEE}",
  booktitle =    "{2019 20th International Workshop on
                 {Microprocessor\slash SoC} Test, Security and
                 Verification (MTV)}",
  title =        "Open-Source Validation Suite for {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "7--12",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/MTV48867.2019.00010",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Cieslak:2019:RMI,
  author =       "Sebastian Cieslak and Adrian Oleksiak and Krzysztof
                 Marcinek and Witold A. Pleskacz",
  editor =       "{IEEE}",
  booktitle =    "{2019 MIXDES --- 26th International Conference "Mixed
                 Design of Integrated Circuits and Systems"}",
  title =        "Retargeting the {MIPS-II CPU} Core to the {RISC-V}
                 Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "261--264",
  year =         "2019",
  DOI =          "https://doi.org/10.23919/MIXDES.2019.8787018",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Das:2019:SMR,
  author =       "S. Das and R. H. Unnithan and A. Menon and C. Rebeiro
                 and K. Veezhinathan",
  editor =       "Jian-Jia Chen and Aviral Shrivastava",
  booktitle =    "{LCTES '19: 20th ACM SIGPLAN\slash SIGBED Conference
                 on Languages, Compilers, and Tools for Embedded
                 Systems. Phoenix, AZ, USA. 23 June 2019}",
  title =        "{SHAKTI-MS}: a {RISC-V} processor for memory safety in
                 {C}",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "19--32",
  year =         "2019",
  DOI =          "https://doi.org/10.1145/3316482.3326356",
  ISBN =         "1-4503-6724-0",
  ISBN-13 =      "978-1-4503-6724-0",
  bibdate =      "Tue Dec 19 08:28:42 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3316482.3326356",
  abstract =     "In this era of IoT devices, security is very often
                 traded off for smaller device footprint and low power
                 consumption. Considering the exponentially growing
                 security threats of IoT and cyber-physical systems, it
                 is important that these devices have built-in features
                 that enhance security. In this paper, we present
                 Shakti-MS, a lightweight RISC-V processor with built-in
                 support for both temporal and spatial memory
                 protection. At run time, Shakti-MS can detect and
                 stymie memory misuse in C and C++ programs, with
                 minimum runtime overheads. The solution uses a novel
                 implementation of fat-pointers to efficiently detect
                 misuse of pointers at runtime. Our proposal is to use
                 stack-based cookies for crafting fat-pointers instead
                 of having object-based identifiers. We store the
                 fat-pointer on the stack, which eliminates the use of
                 shadow memory space, or any table to store the pointer
                 metadata. This reduces the storage overheads by a great
                 extent. The cookie also helps to preserve control flow
                 of the program by ensuring that the return address
                 never gets modified by vulnerabilities like buffer
                 overflows. Shakti-MS introduces new instructions in the
                 microprocessor hardware, and also a modified compiler
                 that automatically inserts these new instructions to
                 enable memory protection. This co-design approach is
                 intended to reduce runtime and area overheads, and also
                 provides an end-to-end solution. The hardware has an
                 area overhead of 700 LUTs on a Xilinx Virtex Ultrascale
                 FPGA and 4100 cells on an open 55nm technology node.
                 The clock frequency of the processor is not affected by
                 the security extensions, while there is a marginal
                 increase in the code size by 11\% with an average
                 runtime overhead of 13\%.",
  acknowledgement = ack-nhfb,
}

@InProceedings{De:2019:FFI,
  author =       "Asmit De and Aditya Basu and Swaroop Ghosh and Trent
                 Jaeger",
  editor =       "{IEEE}",
  booktitle =    "{2019 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "{FIXER}: Flow Integrity Extensions for Embedded
                 {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "348--353",
  year =         "2019",
  DOI =          "https://doi.org/10.23919/DATE.2019.8714980",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{DeMulder:2019:IPR,
  author =       "Elke {De Mulder} and Samatha Gummalla and Michael
                 Hutter",
  editor =       "{IEEE}",
  booktitle =    "{2019 56th {ACM\slash IEEE} Design Automation
                 Conference (DAC)}",
  title =        "{INVITED}: Protecting {RISC-V} against Side-Channel
                 Attacks",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2019",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Dogan:2019:ASU,
  author =       "Halit Dogan and Masab Ahmad and Brian Kahne and Omer
                 Khan",
  title =        "Accelerating Synchronization Using Moving Compute to
                 Data Model at 1,000-core Multicore Scale",
  journal =      j-TACO,
  volume =       "16",
  number =       "1",
  pages =        "4:1--4:??",
  month =        mar,
  year =         "2019",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3300208",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Mon Mar 11 19:00:20 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  abstract =     "Thread synchronization using shared memory hardware
                 cache coherence paradigm is prevalent in multicore
                 processors. However, as the number of cores increase on
                 a chip, cache line ping-pong prevents performance
                 scaling for algorithms that deploy fine-grain
                 synchronization. This article proposes an in-hardware
                 moving computation to data model (MC) that pins shared
                 data at dedicated cores. The critical code sections are
                 serialized and executed at these cores in a spatial
                 setting to enable data locality optimizations.
                 In-hardware messages enable non-blocking and blocking
                 communication between cores, without involving the
                 cache coherence protocol. The in-hardware MC model is
                 implemented on Tilera Tile-Gx72 multicore platform to
                 evaluate 8- to 64-core count scale. A simulated RISC-V
                 multicore environment is built to further evaluate the
                 performance scaling advantages of the MC model at
                 1,024-cores scale. The evaluation using graph and
                 machine-learning benchmarks illustrates that atomic
                 instructions based synchronization scales up to 512
                 cores, and the MC model at the same core count
                 outperforms by 27\% in completion time and 39\% in
                 dynamic energy consumption.",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J924",
}

@InProceedings{Dong:2019:SSE,
  author =       "Jiajie Dong and Long Xi and Mengxi Yu and Zeming
                 Zhang",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE 19th International Conference on Software
                 Quality, Reliability and Security Companion (QRS-C)}",
  title =        "Software Simulation Error Injection in {RAM} on
                 {RISC-V} of {PolarFire FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "499--502",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/QRS-C.2019.00095",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Eassa:2019:RVB,
  author =       "Hossameldin Eassa and Ihab Adly and Hanady H. Issa",
  editor =       "{IEEE}",
  booktitle =    "{2019 31st International Conference on
                 Microelectronics (ICM)}",
  title =        "{RISC-V} based implementation of Programmable Logic
                 Controller on {FPGA} for Industry 4.0",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "98--102",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ICM48031.2019.9021939",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Eggimann:2019:RVB,
  author =       "Manuel Eggimann and Stefan Mach and Michele Magno and
                 Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE 8th International Workshop on Advances in
                 Sensors and Interfaces (IWASI)}",
  title =        "A {RISC-V} Based Open Hardware Platform for Always-On
                 Wearable Smart Sensing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "169--174",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/IWASI.2019.8791364",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Farshchi:2019:IND,
  author =       "Farzad Farshchi and Qijing Huang and Heechul Yun",
  editor =       "{IEEE}",
  booktitle =    "{2019 2nd Workshop on Energy Efficient Machine
                 Learning and Cognitive Computing for Embedded
                 Applications (EMC2)}",
  title =        "Integrating {NVIDIA} Deep Learning Accelerator
                 {(NVDLA)} with {RISC-V SoC} on {FireSim}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "21--25",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/EMC249363.2019.00012",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Feng:2019:ILN,
  author =       "Shanggong Feng and Junning Wu and Shengang Zhou and
                 Renwei Li",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE 10th International Conference on Software
                 Engineering and Service Science (ICSESS)}",
  title =        "The Implementation of {LeNet-5} with {NVDLA} on
                 {RISC-V SoC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "39--42",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ICSESS47205.2019.9040769",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Fiolhais:2019:LEH,
  author =       "Lu{\'\i}s Fiolhais and Fernando Gon{\c{c}}alves and
                 Rui P. Duarte and M{\'a}rio V{\'e}stias and Jose T. de
                 Sousa",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Low Energy Heterogeneous Computing with Multiple
                 {RISC-V} and {CGRA} Cores",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ISCAS.2019.8702538",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Fritzmann:2019:TRS,
  author =       "Tim Fritzmann and Uzair Sharif and Daniel
                 M{\"u}ller-Gritschneder and Cezar Reinbrecht and Ulf
                 Schlichtmann and Johanna Sepulveda",
  editor =       "{IEEE}",
  booktitle =    "{2019 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Towards Reliable and Secure Post-Quantum Co-Processors
                 based on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1148--1153",
  year =         "2019",
  DOI =          "https://doi.org/10.23919/DATE.2019.8715173",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Garofalo:2019:PNC,
  author =       "Angelo Garofalo and Manuele Rusci and Francesco Conti
                 and Davide Rossi and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2019 26th IEEE International Conference on
                 Electronics, Circuits and Systems (ICECS)}",
  title =        "{PULP-NN}: a Computing Library for Quantized Neural
                 Network inference at the edge on {RISC-V} Based
                 Parallel Ultra Low Power Clusters",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "33--36",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ICECS46596.2019.8965067",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Haj-Yahya:2019:LSB,
  author =       "Jawad Haj-Yahya and Ming Ming Wong and Vikramkumar
                 Pudi and Shivam Bhasin and Anupam Chattopadhyay",
  editor =       "{IEEE}",
  booktitle =    "{20th International Symposium on Quality Electronic
                 Design (ISQED)}",
  title =        "Lightweight Secure-Boot Architecture for {RISC-V}
                 {System-on-Chip}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "216--223",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ISQED.2019.8697657",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Heinz:2019:CHE,
  author =       "Carsten Heinz and Yannick Lavan and Jaco Hofmann and
                 Andreas Koch",
  editor =       "{IEEE}",
  booktitle =    "{2019 International Conference on ReConFigurable
                 Computing and FPGAs (ReConFig)}",
  title =        "A Catalog and In-Hardware Evaluation of Open-Source
                 Drop-In Compatible {RISC-V} Softcore Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ReConFig48160.2019.8994796",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Herdt:2019:ECT,
  author =       "Vladimir Herdt and Daniel Gro{\ss}e and Hoang M. Le
                 and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2019 56th {ACM\slash IEEE} Design Automation
                 Conference (DAC)}",
  title =        "Early Concolic Testing of Embedded Binaries with
                 Virtual Prototypes: a {RISC-V} Case Study",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2019",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Herdt:2019:SRV,
  author =       "Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler
                 and Christoph Gerum and Alexander Jung and Joscha-Joel
                 Benz and Oliver Bringmann and Michael Schwarz and
                 Dominik Stoffel and Wolfgang Kunz",
  editor =       "{IEEE}",
  booktitle =    "{2019 Forum for Specification and Design Languages
                 (FDL)}",
  title =        "Systematic {RISC-V} based Firmware Design",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/FDL.2019.8876945",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Holler:2019:OSR,
  author =       "Roland H{\"o}ller and Dominic Haselberger and Dominik
                 Ballek and Peter R{\"o}ssler and Markus Krapfenbauer
                 and Martin Linauer",
  editor =       "{IEEE}",
  booktitle =    "{2019 8th Mediterranean Conference on Embedded
                 Computing (MECO)}",
  title =        "Open-Source {RISC-V} Processor {IP} Cores for {FPGAs}
                 --- Overview and Evaluation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/MECO.2019.8760205",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Huang:2019:ILA,
  author =       "Bo-Yuan Huang and Hongce Zhang and Pramod Subramanyan
                 and Yakir Vizel and Aarti Gupta and Sharad Malik",
  title =        "Instruction-Level Abstraction {(ILA)}: a Uniform
                 Specification for {System-on-Chip (SoC)} Verification",
  journal =      j-TODAES,
  volume =       "24",
  number =       "1",
  pages =        "10:1--10:??",
  month =        jan,
  year =         "2019",
  CODEN =        "ATASFO",
  DOI =          "https://doi.org/10.1145/3282444",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Fri Mar 22 16:58:40 MDT 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/todaes.bib",
  abstract =     "Modern Systems-on-Chip (SoC) designs are increasingly
                 heterogeneous and contain specialized semi-programmable
                 accelerators in addition to programmable processors. In
                 contrast to the pre-accelerator era, when the ISA
                 played an important role in verification by enabling a
                 clean separation of concerns between software and
                 hardware, verification of these ``accelerator-rich''
                 SoCs presents new challenges. From the perspective of
                 hardware designers, there is a lack of a common
                 framework for formal functional specification of
                 accelerator behavior. From the perspective of software
                 developers, there exists no unified framework for
                 reasoning about software/hardware interactions of
                 programs that interact with accelerators. This article
                 addresses these challenges by providing a formal
                 specification and high-level abstraction for
                 accelerator functional behavior. It formalizes the
                 concept of an Instruction Level Abstraction (ILA),
                 developed informally in our previous work, and shows
                 its application in modeling and verification of
                 accelerators. This formal ILA extends the familiar
                 notion of instructions to accelerators and provides a
                 uniform, modular, and hierarchical abstraction for
                 modeling software-visible behavior of both accelerators
                 and programmable processors. We demonstrate the
                 applicability of the ILA through several case studies
                 of accelerators (for image processing, machine
                 learning, and cryptography), and a general-purpose
                 processor (RISC-V). We show how the ILA model
                 facilitates equivalence checking between two ILAs, and
                 between an ILA and its hardware finite-state machine
                 (FSM) implementation. Further, this equivalence
                 checking supports accelerator upgrades using the notion
                 of ILA compatibility, similar to processor upgrades
                 using ISA compatibility.",
  acknowledgement = ack-nhfb,
  articleno =    "10",
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J776",
}

@InProceedings{Ince:2019:BOS,
  author =       "M. Numan Ince and Joseph Ledet and Melih Gunay",
  editor =       "{IEEE}",
  booktitle =    "{2019 1st International Informatics and Software
                 Engineering Conference (UBMYK)}",
  title =        "Building An Open Source {Linux} Computing System On
                 {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/UBMYK48245.2019.8965559",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/linux.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/unix.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kamaleldin:2019:MMS,
  author =       "Ahmed Kamaleldin and Muhammad Ali and Pedram Amini Rad
                 and Marcus Gottschalk and Diana G{\"o}hringer",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE 13th International Symposium on Embedded
                 {Multicore\slash Many-core} Systems-on-Chip (MCSoC)}",
  title =        "Modular Memory System for {RISC-V} Based {MPSoCs} on
                 {Xilinx FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "68--73",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/MCSoC.2019.00017",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kanamoto:2019:SSR,
  author =       "Toshiki Kanamoto and Masami Fukushima and Koichi
                 Kitagishi and Seijin Nakayama and Hideki Ishihara and
                 Koki Kasai and Atsushi Kurokawa and Masashi Imai",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE 62nd International Midwest Symposium on
                 Circuits and Systems (MWSCAS)}",
  title =        "A Single-Stage {RISC-V} Processor to Mitigate the {von
                 Neumann} Bottleneck",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1085--1088",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/MWSCAS.2019.8884919",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kimura:2019:PSV,
  author =       "Yoshiki Kimura and Tomoya Kikuchi and Kanemitsu Ootsu
                 and Takashi Yokota",
  editor =       "{IEEE}",
  booktitle =    "{2019 Seventh International Symposium on Computing and
                 Networking Workshops (CANDARW)}",
  title =        "Proposal of Scalable Vector Extension for Embedded
                 {RISC-V} Soft-Core Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "435--439",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/CANDARW.2019.00082",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Koppelmann:2019:RVE,
  author =       "Bastian Koppelmann and Peer Adelt and Wolfgang Mueller
                 and Christoph Scheytt",
  editor =       "{IEEE}",
  booktitle =    "{2019 29th International Symposium on Power and Timing
                 Modeling, Optimization and Simulation (PATMOS)}",
  title =        "{RISC-V} Extensions for Bit Manipulation
                 Instructions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "41--48",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/PATMOS.2019.8862170",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kumar:2019:ISR,
  author =       "Vinay B. Y. Kumar and Anupam Chattopadhyay and Jawad
                 Haj-Yahya and Avi Mendelson",
  editor =       "{IEEE}",
  booktitle =    "{2019 32nd IEEE International System-on-Chip
                 Conference (SOCC)}",
  title =        "{ITUS}: a Secure {RISC-V System-on-Chip}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "418--423",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/SOCC46988.2019.1570564307",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Laurent:2019:FIH,
  author =       "Johan Laurent and Vincent Beroulle and Christophe
                 Deleuze and Florian Pebay-Peyroula",
  editor =       "{IEEE}",
  booktitle =    "{2019 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Fault Injection on Hidden Registers in a {RISC-V}
                 {Rocket} Processor and Software Countermeasures",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "252--255",
  year =         "2019",
  DOI =          "https://doi.org/10.23919/DATE.2019.8715158",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Li:2019:DIC,
  author =       "Zhenhao Li and Wei Hu and Shuang Chen",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE 21st International Conference on High
                 Performance Computing and Communications; IEEE 17th
                 International Conference on Smart City; IEEE 5th
                 International Conference on Data Science and Systems
                 {(HPCC\slash SmartCity\slash DSS)}}",
  title =        "Design and Implementation of {CNN} Custom Processor
                 Based on {RISC-V} Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1945--1950",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/HPCC/SmartCity/DSS.2019.00268",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Liu:2019:RGH,
  author =       "Gai Liu and Joseph Primmer and Zhiru Zhang",
  editor =       "{IEEE}",
  booktitle =    "{2019 56th {ACM\slash IEEE} Design Automation
                 Conference (DAC)}",
  title =        "Rapid Generation of High-Quality {RISC-V} Processors
                 from Functional Instruction Set Specifications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2019",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Mach:2019:FSB,
  author =       "Stefan Mach and Fabian Schuiki and Florian Zaruba and
                 Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2019 IFIP\slash IEEE 27th International Conference on
                 Very Large Scale Integration (VLSI-SoC)}",
  title =        "A {0.80pJ\slash flop, 1.24Tflop\slash sW} 8-to-64 bit
                 Transprecision Floating-Point Unit for a 64 bit
                 {RISC-V} Processor in 22nm {FD-SOI}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "95--98",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/VLSI-SoC.2019.8920307",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Mashimo:2019:OSF,
  author =       "Susumu Mashimo and Akifumi Fujita and Reoma Matsuo and
                 Seiya Akaki and Akifumi Fukuda and Toru Koizumi and
                 Junichiro Kadomoto and Hidetsugu Irie and Masahiro
                 Goshima and Koji Inoue and Ryota Shioya",
  editor =       "{IEEE}",
  booktitle =    "{2019 International Conference on Field-Programmable
                 Technology (ICFPT)}",
  title =        "An Open Source {FPGA-Optimized} Out-of-Order {RISC-V}
                 Soft Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "63--71",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ICFPT47387.2019.00016",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{McGrew:2019:FTU,
  author =       "Tyler McGrew and Eric Schonauer and Peter Jamieson",
  editor =       "{IEEE}",
  booktitle =    "{2019 International Conference on Computational
                 Science and Computational Intelligence (CSCI)}",
  title =        "Framework and Tools for Undergraduates Designing
                 {RISC-V} Processors on an {FPGA} in Computer
                 Architecture Education",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "778--781",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/CSCI49370.2019.00148",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Mian:2019:CAE,
  author =       "Riaz-ul-haque Mian and Michihiro Shintani and Michiko
                 Inoue",
  editor =       "{IEEE}",
  booktitle =    "{2019 32nd IEEE International System-on-Chip
                 Conference (SOCC)}",
  title =        "Cycle-Accurate Evaluation of Software-Hardware
                 Co-Design of Decimal Computation in {RISC-V}
                 Ecosystem",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "412--417",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/SOCC46988.2019.1570559752",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Decimal arithmetic; Decimal multiplication; Evaluation
                 framework; Hardware accelerator; RISC-V; RoCC; Rocket
                 chip",
}

@InProceedings{Moon:2019:RFS,
  author =       "Hyeon-gyun Moon and Jeonghun Cho and Daejin Park",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE Intl Conf on Dependable, Autonomic and
                 Secure Computing, Intl Conf on Pervasive Intelligence
                 and Computing, Intl Conf on Cloud and Big Data
                 Computing, Intl Conf on Cyber Science and Technology
                 Congress {(DASC\slash PiCom\slash CBDCom\slash
                 CyberSciTech)}}",
  title =        "Reconfigurable Fault-Safe Processor Platform Based on
                 {RISC-V} for Large-Scaled {IoT-Driven} Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "627--632",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/DASC/PiCom/CBDCom/CyberSciTech.2019.00119",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Morales:2019:LAD,
  author =       "Hanssel Morales and Ckristian Duran and Elkim Roa",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE 10th Latin American Symposium on Circuits
                 \& Systems (LASCAS)}",
  title =        "A Low-Area Direct Memory Access Controller
                 Architecture for a {RISC-V} Based Low-Power
                 Microcontroller",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "97--100",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/LASCAS.2019.8667579",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Oleksiak:2019:DVE,
  author =       "Adrian Oleksiak and Sebastian Cie{\'s}lak and
                 Krzysztof Marcinek and Witold A. Pleskacz",
  editor =       "{IEEE}",
  booktitle =    "{2019 MIXDES --- 26th International Conference "Mixed
                 Design of Integrated Circuits and Systems"}",
  title =        "Design and Verification Environment for {RISC-V}
                 Processor Cores",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "206--209",
  year =         "2019",
  DOI =          "https://doi.org/10.23919/MIXDES.2019.8787108",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Payvar:2019:IER,
  author =       "Saman Payvar and Esko Pekkarinen and Rafael Stahl and
                 Daniel Mueller-Gritschneder and Timo D.
                 H{\"a}m{\"a}l{\"a}inen",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE Nordic Circuits and Systems Conference
                 (NORCAS): NORCHIP and International Symposium of
                 System-on-Chip (SoC)}",
  title =        "Instruction Extension of a {RISC-V} Processor Modeled
                 with {IP-XACT}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/NORCHIP.2019.8906975",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Porter:2019:ESC,
  author =       "Ross Porter and Sam Morgan and Morteza
                 Biglari-Abhari",
  editor =       "{IEEE}",
  booktitle =    "{2019 International Conference on Computational
                 Science and Computational Intelligence (CSCI)}",
  title =        "Extending a Soft-Core {RISC-V} Processor to Accelerate
                 {CNN} Inference",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "694--697",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/CSCI49370.2019.00130",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Ramos:2019:APM,
  author =       "A. Ramos and R. G. Toral and P. Reviriego and J. A.
                 Maestro",
  title =        "An {ALU} Protection Methodology for Soft Processors on
                 {SRAM}-Based {FPGAs}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "68",
  number =       "9",
  pages =        "1404--1410",
  month =        sep,
  year =         "2019",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2019.2907238",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Aug 30 05:58:40 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "adaptive protection; ALU; ALU protection methodology;
                 application-based methodology; arithmetic logic unit;
                 cosmic background radiation; cosmic radiation; digital
                 arithmetic; fault tolerance; Fault tolerant systems;
                 Field programmable gate arrays; field programmable gate
                 arrays; FPGA; hardware configuration library;
                 integrated circuit reliability; logic testing;
                 Microprocessors; modular redundancy techniques; Program
                 processors; radiation hardening (electronics);
                 redundancy; Redundancy; RISC-V; soft core; soft error;
                 soft errors; soft processor; space missions; SRAM
                 chips; SRAM-based FPGA; TMR configurations",
}

@InProceedings{Rodrigues:2019:THF,
  author =       "Cristiano Rodrigues and Ivo Marques and Sandro Pinto
                 and Tiago Gomes and Adriano Tavares",
  editor =       "{IEEE}",
  booktitle =    "{IECON 2019 --- 45th Annual Conference of the IEEE
                 Industrial Electronics Society}",
  title =        "Towards a Heterogeneous Fault-Tolerance Architecture
                 based on {Arm} and {RISC-V} Processors",
  volume =       "1",
  number =       "",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "3112--3117",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/IECON.2019.8926844",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Rogers:2019:SLB,
  author =       "Samuel Rogers and Joshua Slycord and Ronak Raheja and
                 Hamed Tabkhi",
  title =        "Scalable {LLVM}-Based Accelerator Modeling in gem5",
  journal =      j-IEEE-COMPUT-ARCHIT-LETT,
  volume =       "18",
  number =       "1",
  pages =        "18--21",
  month =        jan # "\slash " # jun,
  year =         "2019",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/LCA.2019.2893932",
  ISSN =         "1556-6056 (print), 1556-6064 (electronic)",
  ISSN-L =       "1556-6056",
  bibdate =      "Tue Jun 25 07:41:05 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeecomputarchitlett.bib;
                 https://www.math.utah.edu/pub/tex/bib/python.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  abstract =     "This article proposes a scalable integrated system
                 architecture modeling for hardware accelerator based in
                 gem5 simulation framework. The core of proposed
                 modeling is a LLVM-based simulation engine for modeling
                 any customized data-path with respect to inherent
                 data/instruction-level parallelism (derived by
                 algorithms) and available compute units (defined by the
                 user). The simulation framework also offers a
                 general-purpose communication interface that allows a
                 scalable and flexible connection into the gem5
                 ecosystem. Python API of gem5, enabling modifications
                 to the system hierarchy without the need to rebuild the
                 underlying simulator. Our simulation framework
                 currently supports full-system simulation (both
                 bare-metal and a full Linux kernel) for ARM-based
                 systems, with future plans to add support for RISC-V.
                 The LLVM-based modeling and modular integration to gem5
                 allow long-term simulation expansion and sustainable
                 design modeling for emerging applications with demands
                 for acceleration.",
  acknowledgement = ack-nhfb,
  affiliation =  "Rogers, S (Reprint Author), Univ Noth Carolina, Dept
                 Elect \& Comp Engn, Charlotte, NC 28223 USA. Rogers,
                 Samuel; Slycord, Joshua; Raheja, Ronak; Tabkhi, Hamed,
                 Univ Noth Carolina, Dept Elect \& Comp Engn, Charlotte,
                 NC 28223 USA.",
  author-email = "sroger48@uncc.edu jslycord@uncc.edu rraheja@uncc.edu
                 htabkhiv@uncc.edu",
  da =           "2019-06-20",
  doc-delivery-number = "HL5MF",
  eissn =        "1556-6064",
  fjournal =     "IEEE Computer Architecture Letters",
  journal-iso =  "IEEE Comput. Archit. Lett.",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10208",
  keywords =     "application program interfaces; ARM-based systems;
                 Computational modeling; Computer architecture
                 simulation; customized data-path; Engines; field
                 programmable gate arrays; flexible connection;
                 full-system simulation; gem5 ecosystem; gem5 simulation
                 framework; general-purpose communication interface;
                 Hardware; hardware accelerator; hardware accelerators;
                 heterogeneous systems; inherent data; instruction-level
                 parallelism; Linux; LLVM-based modeling; LLVM-based
                 simulation engine; logic design; long-term simulation
                 expansion; microprocessor chips; multiprocessing
                 systems; parallel architectures; parallel programming;
                 program compilers; reduced instruction set computing;
                 Registers; RISC-V; Runtime; scalable connection;
                 scalable integrated system architecture modeling;
                 scalable LLVM-based accelerator modeling; Space
                 exploration; sustainable design modeling;
                 Synchronization; system hierarchy",
  number-of-cited-references = "11",
  ORCID-numbers = "Slycord, Joshua/0000-0002-0569-4094 Rogers,
                 Samuel/0000-0002-9697-2933",
  research-areas = "Computer Science",
  times-cited =  "0",
  unique-id =    "Rogers:2019:SLB",
  web-of-science-categories = "Computer Science, Hardware \&
                 Architecture",
}

@Article{Rovinski:2019:ECN,
  author =       "Austin Rovinski and Chun Zhao and Khalid Al-Hawaj and
                 Paul Gao and Shaolin Xie and Christopher Torng and
                 Scott Davidson and Aporva Amarnath and Luis Vega and
                 Bandhav Veluri and Anuj Rao and Tutu Ajayi and Julian
                 Puscar and Steve Dai and Ritchie Zhao and Dustin
                 Richmond and Zhiru Zhang and Ian Galton and Christopher
                 Batten and Michael B. Taylor and Ronald G. Dreslinski",
  title =        "Evaluating {Celerity}: a 16-nm 695 {Giga-RISC-V}
                 Instructions/s Manycore Processor With Synthesizable
                 {PLL}",
  journal =      "IEEE Solid-State Circuits Letters",
  volume =       "2",
  number =       "12",
  pages =        "289--292",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/LSSC.2019.2953847",
  ISSN =         "2573-9603",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Rovinski:2019:GGR,
  author =       "Austin Rovinski and Chun Zhao and Khalid Al-Hawaj and
                 Paul Gao and Shaolin Xie and Christopher Torng and
                 Scott Davidson and Aporva Amarnath and Luis Vega and
                 Bandhav Veluri and Anuj Rao and Tutu Ajayi and Julian
                 Puscar and Steve Dai and Ritchie Zhao and Dustin
                 Richmond and Zhiru Zhang and Ian Galton and Christopher
                 Batten and Michael B. Taylor and Ronald G. Dreslinski",
  editor =       "{IEEE}",
  booktitle =    "{2019 Symposium on VLSI Circuits}",
  title =        "A 1.4 {GHz 695} Giga {RISC-V} Inst/s 496-Core Manycore
                 Processor With Mesh On-Chip Network and an All-Digital
                 Synthesized {PLL} in 16nm {CMOS}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "C30--C31",
  year =         "2019",
  DOI =          "https://doi.org/10.23919/VLSIC.2019.8778031",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ruospo:2019:LTA,
  author =       "Annachiara Ruospo and Riccardo Cantoro and Ernesto
                 Sanchez and Pasquale Davide Schiavone and Angelo
                 Garofalo and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "On-line Testing for Autonomous Systems driven by
                 {RISC-V} Processor Design Verification",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/DFT.2019.8875345",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Shirley:2019:IFT,
  author =       "Geraldine Shirley and Fareena Saqib",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE 16th International Conference on Smart
                 Cities: Improving Quality of Life Using ICT \& {IoT}
                 and AI (HONET-ICT)}",
  title =        "Information Flow Tracking in {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "199--200",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/HONET.2019.8908033",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Siddiqui:2019:SDF,
  author =       "Ali Shuja Siddiqui and Geraldine Shirley and Shreya
                 Bendre and Girija Bhagwat and Jim Plusquellic and
                 Fareena Saqib",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE 4th International Verification and Security
                 Workshop (IVSW)}",
  title =        "Secure Design Flow of {FPGA} Based {RISC-V}
                 Implementation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "37--42",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/IVSW.2019.8854418",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Misc{SRC:2019:RVM,
  author =       "{SEMICO Research Corporation}",
  title =        "{RISC-V} Market Analysis: The New Kid on the Block",
  howpublished = "Web document.",
  pages =        "8",
  month =        nov,
  year =         "2019",
  bibdate =      "Tue Dec 19 07:38:44 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  note =         "Study number CC315-19.",
  URL =          "https://semico.com/sites/default/files/TOC_CC315-19.pdf",
  acknowledgement = ack-nhfb,
  remark =       "PDF file is truncated after table of contents: full
                 report is about 90 pages.",
}

@InProceedings{Stazi:2019:QAA,
  author =       "Giulia Stazi and Antonio Mastrandrea and Mauro
                 Olivieri and Francesco Menichelli",
  editor =       "{IEEE}",
  booktitle =    "{2019 15th Conference on Ph.D Research in
                 Microelectronics and Electronics (PRIME)}",
  title =        "Quality Aware Approximate Memory in {RISC-V} {Linux}
                 Kernel",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "177--180",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/PRIME.2019.8787745",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tagliavini:2019:DES,
  author =       "Giuseppe Tagliavini and Stefan Mach and Davide Rossi
                 and Andrea Marongiu and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2019 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Design and Evaluation of {SmallFloat SIMD} extensions
                 to the {RISC-V ISA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "654--657",
  year =         "2019",
  DOI =          "https://doi.org/10.23919/DATE.2019.8714897",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Tiwari:2019:PPE,
  author =       "Sugandha Tiwari and Neel Gala and Chester Rebeiro and
                 V. Kamakoti",
  title =        "{PERI}: a Posit Enabled {RISC-V} Core",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--14",
  month =        nov,
  year =         "2019",
  bibdate =      "Thu Apr 09 15:06:39 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://arxiv.org/pdf/1908.01466.pdf",
  abstract =     "Owing to the failure of Dennard's scaling the last
                 decade has seen a steep growth of prominent new
                 paradigms leveraging opportunities in computer
                 architecture. Two technologies of interest are Posit
                 and RISC-V. Posit was introduced in mid-2017 as a
                 viable alternative to IEEE 754-2008. Posit promises
                 more accuracy, higher dynamic range and fewer unused
                 states along with simpler hardware designs as compared
                 to IEEE 754- 2008. RISC-V, on the other hand, provides
                 a commercial-grade open-source ISA. It is not only
                 elegant and simple but also highly extensible and
                 customizable, thereby facilitating novel
                 micro-architectural research and exploration. In this
                 paper, we bring these two technologies together and
                 propose the first Posit Enabled RISC-V core. The paper
                 provides insights on how the current 'F' extension and
                 the custom op-code space of RISCV can be
                 leveraged/modified to support Posit arithmetic. We also
                 present implementation details of a parameterized and
                 feature-complete Posit FPU which is integrated with the
                 RISC-V compliant SHAKTI C-class core either as an
                 execution unit or as an accelerator. To fully leverage
                 the potential of Posit, we further enhance our Posit
                 FPU, with minimal overheads, to support two different
                 exponent sizes (with posit-size being 32-bits). This
                 allows applications to switch from high-accuracy
                 computation mode to a mode with higher dynamic-range at
                 run-time. In the absence of viable software tool-chain
                 to enable porting of applications in the Posit domain,
                 we present a workaround on how certain applications can
                 be modified minimally to exploit the existing RISC-V
                 tool-chain. We also provide examples of applications
                 which can perform better with Posit as compared to IEEE
                 754-2008. The proposed Posit FPU consumes 3507 slice
                 LUTs and 1294 slice registers on an Artix-7-100T Xilinx
                 FPGA while capable of operating at 100 MHz.",
  acknowledgement = ack-nhfb,
  keywords =     "floating-point; IEEE-754; Posit; processor; RISC-V",
}

@Article{Truesdell:2019:NHK,
  author =       "Daniel S. Truesdell and Jacob Breiholz and Sumanth
                 Kamineni and Ningxi Liu and Albert Magyar and Benton H.
                 Calhoun",
  title =        "A {6--140-nW 11 Hz--8.2-kHz DVFS RISC-V}
                 Microprocessor Using Scalable Dynamic
                 Leakage-Suppression Logic",
  journal =      "IEEE Solid-State Circuits Letters",
  volume =       "2",
  number =       "8",
  pages =        "57--60",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/LSSC.2019.2938897",
  ISSN =         "2573-9603",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wang:2019:ASM,
  author =       "Yajie Wang and Nianxiong Tan",
  editor =       "{IEEE}",
  booktitle =    "{2019 International Conference on IC Design and
                 Technology (ICICDT)}",
  title =        "An Application-Specific Microprocessor for Energy
                 Metering Based on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ICICDT.2019.8790918",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wang:2019:OOM,
  author =       "Jiawei Wang and Yuejun Zhang and Pengjun Wang and
                 Zhicun Luan and Liwei Li",
  editor =       "{IEEE}",
  booktitle =    "{2019 China Semiconductor Technology International
                 Conference (CSTIC)}",
  title =        "An Orthogonal Obfuscation Method on Extend Instruction
                 Sets for Sequrity {RISC-V} Circuit",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--3",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/CSTIC.2019.8755704",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Wang:2019:RTG,
  author =       "Angie Wang and Woorham Bae and Jaeduk Han and Stevo
                 Bailey and Orhan Ocal and Paul Rigge and Zhongkai Wang
                 and Kannan Ramchandran and Elad Alon and Borivoje
                 Nikoli{\'c}",
  title =        "A Real-Time, {1.89-GHz} Bandwidth, {175-kHz}
                 Resolution Sparse Spectral Analysis {RISC-V SoC} in
                 16-nm {FinFET}",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "54",
  number =       "7",
  pages =        "1993--2008",
  year =         "2019",
  CODEN =        "IJSCBC",
  DOI =          "https://doi.org/10.1109/JSSC.2019.2913099",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
}

@InProceedings{Werner:2019:PRV,
  author =       "Mario Werner and Robert Schilling and Thomas
                 Unterluggauer and Stefan Mangard",
  editor =       "{IEEE}",
  booktitle =    "{2019 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Protecting {RISC-V} Processors against Physical
                 Attacks",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1136--1141",
  year =         "2019",
  DOI =          "https://doi.org/10.23919/DATE.2019.8714811",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wilson:2019:NRT,
  author =       "Andrew Elbert Wilson and Michael Wirthlin",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE Space Computing Conference (SCC)}",
  title =        "Neutron Radiation Testing of Fault Tolerant {RISC-V}
                 Soft Processor on {Xilinx SRAM}-based {FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "25--32",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/SpaceComp.2019.00008",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zang:2019:RRV,
  author =       "Zhenya Zang and Yao Liu and Ray C. C. Cheung",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE International Conference on Industrial
                 Technology (ICIT)}",
  title =        "Reconfigurable {RISC-V} Secure Processor and {SoC}
                 Integration",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "827--832",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ICIT.2019.8755206",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Zaruba:2019:CAC,
  author =       "Florian Zaruba and Luca Benini",
  title =        "The Cost of Application-Class Processing: Energy and
                 Performance Analysis of a {Linux}-Ready {1.7-GHz 64-Bit
                 RISC-V} Core in 22-nm {FDSOI} Technology",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "27",
  number =       "11",
  pages =        "2629--2640",
  year =         "2019",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2019.2926114",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/linux.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/unix.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}

@Article{Zhang:2019:CBB,
  author =       "S. Zhang and A. Wright and T. Bourgeat",
  title =        "Composable Building Blocks to Open Up Processor
                 Design",
  journal =      j-IEEE-MICRO,
  volume =       "39",
  number =       "3",
  pages =        "47--55",
  month =        may # "\slash " # jun,
  year =         "2019",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2019.2910012",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Jul 25 15:33:44 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
  keywords =     "atomic rules; atomic updates; CMD ensure
                 composability; composable building blocks; composable
                 modular design; Concurrent computing; instantaneous
                 access; interface method; Linux; Microarchitecture;
                 microprocessor chips; Out of order; out-of-order
                 processors; out-of-order RISC-V processor; processor
                 design; reduced instruction set computing; Registers;
                 software architecture; state elements; System recovery;
                 Timing; Wires",
}

@InProceedings{Zhang:2019:RVB,
  author =       "Guohe Zhang and Kepeng Zhao and Bin Wu and Yiqun Sun
                 and Li Sun and Feng Liang",
  editor =       "{IEEE}",
  booktitle =    "{2019 IEEE International Conference of Intelligent
                 Applied Systems on Engineering (ICIASE)}",
  title =        "A {RISC-V} based hardware accelerator designed for
                 {Yolo} object detection system",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "9--11",
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ICIASE45644.2019.9074051",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Abella:2020:ARV,
  author =       "Jaume Abella and Calvin Bulla and Guillem Cabo and
                 Francisco J. Cazorla and Adri{\'a}n Cristal and Max
                 Doblas and Roger Figueras and Alberto Gonz{\'a}lez and
                 Carles Hern{\'a}ndez and C{\'e}sar Hern{\'a}ndez and
                 V{\'\i}ctor Jim{\'e}nez and Leonidas Kosmidis and
                 Vatistas Kostalabros and Rub{\'e}n Langarita and Neiel
                 Leyva and Guillem L{\'o}pez-Parad{\'\i}s and Joan
                 Marimon and Ricardo Mart{\'\i}nez and Jonnatan Mendoza
                 and Francesc Moll and Miquel Moret{\'o} and Juli{\'a}n
                 Pav{\'o}n and Crist{\'o}bal Ram{\'\i}rez and Marco A.
                 Ram{\'\i}rez and Carlos Rojas and Antonio Rubio and
                 Abraham Ruiz and Nehir Sonmez and V{\'\i}ctor Soria and
                 Llu{\'\i}s Ter{\'e}s and Osman Unsal and Mateo Valero
                 and Iv{\'a}n Vargas and Lu{\'\i}s Villa and
                 Crist{\'o}bal Ram{\'\i}{\'\i}ez",
  editor =       "{IEEE}",
  booktitle =    "{2020 XXXV Conference on Design of Circuits and
                 Integrated Systems (DCIS)}",
  title =        "An Academic {RISC-V} Silicon Implementation Based on
                 Open-Source Components",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/DCIS51330.2020.9268664",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Adelt:2020:SPQ,
  author =       "Peer Adelt and Bastian Koppelmann and Wolfgang Mueller
                 and Christoph Scheytt",
  editor =       "{IEEE}",
  booktitle =    "{MBMV 2020 --- Methods and Description Languages for
                 Modelling and Verification of Circuits and Systems;
                 {GMM\slash ITG\slash GI-Workshop}}",
  title =        "A Scalable Platform for {QEMU} Based Fault Effect
                 Analysis for {RISC-V} Hardware Architectures",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2020",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Andersson:2020:DNV,
  author =       "Jan Andersson",
  editor =       "{IEEE}",
  booktitle =    "{2020 50th Annual {IEEE\slash IFIP} International
                 Conference on Dependable Systems and Networks Workshops
                 (DSN-W)}",
  title =        "Development of a {NOEL-V RISC-V SoC} Targeting Space
                 Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "66--67",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/DSN-W50199.2020.00020",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Andri:2020:ERV,
  author =       "Renzo Andri and Tomas Henriksson and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2020 57th {ACM\slash IEEE} Design Automation
                 Conference (DAC)}",
  title =        "Extending the {RISC-V ISA} for Efficient {RNN-based
                 5G} Radio Resource Management",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/DAC18072.2020.9218496",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Misc{Anonymous:2020:RVE,
  author =       "Anonymous",
  title =        "{RISC-V} embedded variant {RV32E} now fully supported
                 by {SEGGER}'s Floating-Point library",
  howpublished = "Web site",
  day =          "21",
  month =        sep,
  year =         "2020",
  bibdate =      "Thu Jan 28 18:02:53 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://www.design-reuse.com/news/48672/segger-s-floating-point-library-risc-v-rv32e.html",
  acknowledgement = ack-nhfb,
  remark =       "The story reports a significant code size reduction,
                 and speedup, over the GNU floating-point library.",
}

@InProceedings{Arnaud:2020:RVB,
  author =       "A. Arnaud and M. Miguez and J. Gak and R. Puyol and R.
                 Garcia-Ramirez and E. Solera-Bolanos and R.
                 Castro-Gonzalez and R. Molina-Robles and A.
                 Chacon-Rodriguez and R. Rimolo-Donadio",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 11th Latin American Symposium on Circuits
                 \& Systems (LASCAS)}",
  title =        "A {RISC-V} Based Medical Implantable {SoC} for High
                 Voltage and Current Tissue Stimulus",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/LASCAS45839.2020.9068969",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{AskariHemmat:2020:RVB,
  author =       "MohammadHossein AskariHemmat and Olexa Bilaniuk and
                 Sean Wagner and Yvon Savaria and Jean-Pierre David",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 28th Annual International Symposium on
                 Field-Programmable Custom Computing Machines (FCCM)}",
  title =        "{RISC-V} Barrel Processor for Accelerator Control",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "212--212",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/FCCM48280.2020.00063",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Barbirotta:2020:FRA,
  author =       "Marcello Barbirotta and Antonio Mastrandrea and
                 Francesco Menichelli and Francesco Vigli and Luigi
                 Blasi and Abdallah Cheikh and Stefano Sordillo and
                 Fabio {Di Gennaro} and Mauro Olivieri",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "Fault resilience analysis of a {RISC-V} microprocessor
                 design through a dedicated {UVM} environment",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/DFT50435.2020.9250871",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Barriga:2020:RVP,
  author =       "Angel Barriga",
  editor =       "{IEEE}",
  booktitle =    "{2020 XXXV Conference on Design of Circuits and
                 Integrated Systems (DCIS)}",
  title =        "{RISC-V} processors design: a methodology for cores
                 development",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/DCIS51330.2020.9268639",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Birari:2020:RVI,
  author =       "Akshay Birari and Piyush Birla and Kuruvilla Varghese
                 and Amrutur Bharadwaj",
  editor =       "{IEEE}",
  booktitle =    "{2020 24th International Symposium on VLSI Design and
                 Test (VDAT)}",
  title =        "A {RISC-V ISA} Compatible Processor {IP}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/VDAT50263.2020.9190558",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Cappellone:2020:BST,
  author =       "Danilo Cappellone and Stefano {Di Mascio} and Gianluca
                 Furano and Alessandra Menicucci and Marco Ottavi",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "On-Board Satellite Telemetry Forecasting with {RNN} on
                 {RISC-V} Based Multicore Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/DFT50435.2020.9250796",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Cavalcante:2020:AGS,
  author =       "Matheus Cavalcante and Fabian Schuiki and Florian
                 Zaruba and Michael Schaffner and Luca Benini",
  title =        "{Ara}: a {1-GHz+} Scalable and Energy-Efficient
                 {RISC-V} Vector Processor With Multiprecision
                 Floating-Point Support in 22-nm {FD-SOI}",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "28",
  number =       "2",
  pages =        "530--543",
  year =         "2020",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2019.2950087",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}

@InProceedings{Chen:2020:EOT,
  author =       "Yi-Ru Chen and Hui-Hsin Liao and Chia-Hsuan Chang and
                 Che-Chia Lin and Chao-Lin Lee and Yuan-Ming Chang and
                 Chun-Chieh Yang and Jenq-Kuen Lee",
  editor =       "{IEEE}",
  booktitle =    "{2020 International Symposium on VLSI Design,
                 Automation and Test (VLSI-DAT)}",
  title =        "Experiments and optimizations for {TVM} on {RISC-V}
                 architectures with {P} Extension",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/VLSI-DAT49148.2020.9196477",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Chen:2020:XCM,
  author =       "Chen Chen and Xiaoyan Xiang and Chang Liu and Yunhai
                 Shang and Ren Guo and Dongqi Liu and Yimin Lu and Ziyi
                 Hao and Jiahui Luo and Zhijian Chen and Chunqiang Li
                 and Yu Pu and Jianyi Meng and Xiaolang Yan and Yuan Xie
                 and Xiaoning Qi",
  editor =       "{IEEE}",
  booktitle =    "{2020 ACM\slash IEEE 47th Annual International
                 Symposium on Computer Architecture (ISCA)}",
  title =        "{Xuantie-910}: a Commercial Multi-Core 12-Stage
                 Pipeline Out-of-Order 64-bit High Performance {RISC-V}
                 Processor with Vector Extension: Industrial Product",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "52--64",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ISCA45697.2020.00016",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Chen:2020:XIC,
  author =       "Chen Chen and Xiaoyan Xiang and Chang Liu and Yunhai
                 Shang and Ren Guo and Dongqi Liu and Yimin Lu and Ziyi
                 Hao and Jiahui Luo and Zhijjan Chen and Chunqiang Li
                 and Yu Pu and Jianyi Meng and Xiaolang Yan and Yuan Xie
                 and Xiaoning Qi",
  editor =       "{IEEE}",
  booktitle =    "Proceedings of the {IEEE Hot Chips 32 Symposium (HCS),
                 August, 2020}",
  title =        "{Xuantie-910}: Innovating Cloud and Edge Computing by
                 {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--19",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/HCS49909.2020.9220630",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://ieeexplore.ieee.org/document/9220630",
  acknowledgement = ack-nhfb,
  remark =       "Contains only slides from the conference talk.",
}

@InProceedings{Dao:2020:FRV,
  author =       "Nguyen Dao and Andrew Attwood and Bea Healy and Dirk
                 Koch",
  editor =       "{IEEE}",
  booktitle =    "{2020 International Conference on Field-Programmable
                 Technology (ICFPT)}",
  title =        "{FlexBex}: a {RISC-V} with a Reconfigurable
                 Instruction Extension",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "190--195",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICFPT51103.2020.00034",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{De:2020:HAB,
  author =       "Asmit De and Aditya Basu and Swaroop Ghosh and Trent
                 Jaeger",
  title =        "Hardware Assisted Buffer Protection Mechanisms for
                 Embedded {RISC-V}",
  journal =      j-IEEE-TRANS-CAD-ICS,
  volume =       "39",
  number =       "12",
  pages =        "4453--4465",
  year =         "2020",
  CODEN =        "ITCSDI",
  DOI =          "https://doi.org/10.1109/TCAD.2020.2984407",
  ISSN =         "0278-0070 (print), 1937-4151 (electronic)",
  ISSN-L =       "0278-0070",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computer-Aided Design of
                 Integrated Circuits and Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43",
}

@Article{deOliveira:2020:ESC,
  author =       "{\'A}dria B. de Oliveira and Lucas A. Tambara and
                 Fabio Benevenuti and Luis A. C. Benites and Nemitala
                 Added and Vitor A. P. Aguiar and Nilberto H. Medina and
                 Marcilei A. G. Silveira and Fernanda L. Kastensmidt",
  title =        "Evaluating Soft Core {RISC-V} Processor in
                 {SRAM}-Based {FPGA} Under Radiation Effects",
  journal =      j-IEEE-TRANS-NUCL-SCI,
  volume =       "67",
  number =       "7",
  pages =        "1503--1510",
  year =         "2020",
  CODEN =        "IRNSAM",
  DOI =          "https://doi.org/10.1109/TNS.2020.2995729",
  ISSN =         "0018-9499 (print), 1558-1578 (electronic)",
  ISSN-L =       "0018-9499",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Nuclear Science",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=23",
}

@InProceedings{Desalphine:2020:NMV,
  author =       "Vivian Desalphine and Somya Dashora and Laxita Mali
                 and K. Suhas and Aneesh Raveendran and David
                 Selvakumar",
  editor =       "{IEEE}",
  booktitle =    "{2020 24th International Symposium on VLSI Design and
                 Test (VDAT)}",
  title =        "Novel Method for Verification and Performance
                 Evaluation of a Non-Blocking Level-1 Instruction Cache
                 designed for Out-of-Order {RISC-V} Superscaler
                 Processor on {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/VDAT50263.2020.9190377",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Duran:2020:EER,
  author =       "Ckristian Duran and Megan Wachs and Luis E. Rueda G.
                 and Albert Huntington and Javier Ardila and Jack Kang
                 and Andres Amaya and Hector Gomez and Juan Romero and
                 Laude Fernandez and Felipe Flechas and Rolando Torres
                 and Juan Moya and Wilmer Ramirez and Julian Arenas and
                 Juan Gomez and Hanssel Morales and Camilo Rojas and
                 Alex Mantilla and Elkim Roa and Krste Asanovic",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE Custom Integrated Circuits Conference
                 (CICC)}",
  title =        "An Energy-Efficient {RISC-V RV32IMAC} Microcontroller
                 for Periodical-Driven Sensing Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/CICC48029.2020.9075877",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Duran:2020:SFB,
  author =       "Ckristian Duran and Hanssel Morales and Camilo Rojas
                 and Annachiara Ruospo and Ernesto Sanchez and Elkim
                 Roa",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Simulation and Formal: The Best of Both Domains for
                 Instruction Set Verification of {RISC-V} Based
                 Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ISCAS45731.2020.9180589",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Eckert:2020:UTI,
  author =       "Marcel Eckert and Jan Haase and Bernd Klauer",
  editor =       "{IEEE}",
  booktitle =    "{IECON 2020 The 46th Annual Conference of the IEEE
                 Industrial Electronics Society}",
  title =        "Unifying Timer and Interrupt Management for an
                 {ARM-RISC-V-Heterogeneous} Multi-Core",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2302--2309",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/IECON43393.2020.9255193",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Elmohr:2020:EFI,
  author =       "Mahmoud A. Elmohr and Haohao Liao and Catherine H.
                 Gebotys",
  editor =       "{IEEE}",
  booktitle =    "{2020 21st International Symposium on Quality
                 Electronic Design (ISQED)}",
  title =        "{EM} Fault Injection on {ARM} and {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "206--212",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ISQED48828.2020.9137051",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Elsabbagh:2020:VOC,
  author =       "Fares Elsabbagh and Blaise Tine and Priyadarshini
                 Roshan and Ethan Lyons and Euna Kim and Da Eun Shim and
                 Lingjun Zhu and Sung Kyu Lim and Hyesoon Kim",
  title =        "{Vortex}: {OpenCL} compatible {RISC-V GPGPU}",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--7",
  day =          "27",
  month =        feb,
  year =         "2020",
  DOI =          "https://doi.org/10.48550/arXiv.2002.12151",
  bibdate =      "Tue Dec 19 07:42:22 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://arxiv.org/abs/2002.12151",
  abstract =     "The current challenges in technology scaling are
                 pushing the semiconductor industry towards hardware
                 specialization, creating a proliferation of
                 heterogeneous systems-on-chip, delivering orders of
                 magnitude performance and power benefits compared to
                 traditional general-purpose architectures. This
                 transition is getting a significant boost with the
                 advent of RISC-V with its unique modular and extensible
                 ISA, allowing a wide range of low-cost processor
                 designs for various target applications. In addition,
                 OpenCL is currently the most widely adopted programming
                 framework for heterogeneous platforms available on
                 mainstream CPUs, GPUs, as well as FPGAs and custom DSP.
                 In this work, we present Vortex, a RISC-V
                 General-Purpose GPU that supports OpenCL. Vortex
                 implements a SIMT architecture with a minimal ISA
                 extension to RISC-V that enables the execution of
                 OpenCL programs. We also extended OpenCL runtime
                 framework to use the new ISA. We evaluate this design
                 using 15nm technology. We also show the performance and
                 energy numbers of running them with a subset of
                 benchmarks from the Rodinia Benchmark suite.",
  acknowledgement = ack-nhfb,
}

@Article{Felzmann:2020:RCA,
  author =       "Isa{\'\i}as Felzmann and Jo{\~a}o Fabr{\'\i}cio Filho
                 and Lucas Wanner",
  title =        "{Risk-5}: Controlled Approximations for {RISC-V}",
  journal =      j-IEEE-TRANS-CAD-ICS,
  volume =       "39",
  number =       "11",
  pages =        "4052--4063",
  year =         "2020",
  CODEN =        "ITCSDI",
  DOI =          "https://doi.org/10.1109/TCAD.2020.3012312",
  ISSN =         "0278-0070 (print), 1937-4151 (electronic)",
  ISSN-L =       "0278-0070",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computer-Aided Design of
                 Integrated Circuits and Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43",
}

@InProceedings{Fibich:2020:EOS,
  author =       "Christian Fibich and Stefan Tauner and Peter
                 R{\"o}ssler and Martin Horauer",
  editor =       "{IEEE}",
  booktitle =    "{2020 15th Conference on Computer Science and
                 Information Systems (FedCSIS)}",
  title =        "Evaluation of Open-Source Linear Algebra Libraries
                 targeting {ARM} and {RISC-V} Architectures",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "663--672",
  year =         "2020",
  DOI =          "https://doi.org/10.15439/2020F145",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Fritzmann:2020:ERV,
  author =       "Tim Fritzmann and Georg Sigl and Johanna
                 Sep{\'u}lveda",
  editor =       "{IEEE}",
  booktitle =    "{2020 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Extending the {RISC-V} Instruction Set for Hardware
                 Acceleration of the Post-Quantum Scheme {LAC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1420--1425",
  year =         "2020",
  DOI =          "https://doi.org/10.23919/DATE48585.2020.9116567",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Garcia-Ramirez:2020:SRV,
  author =       "R. Garcia-Ramirez and A. Chacon-Rodriguez and R.
                 Castro-Gonzalez and A. Arnaud and M. Miguez and J. Gak
                 and R. Molina-Robles and G. Madrigal-Boza and M.
                 Oviedo-Hernandez and E. Solera-Bolanos and D.
                 Salazar-Sibaja and D. Sanchez-Jimenez and M.
                 Fonseca-Rodriguez and J. Arrieta-Solorzano and R.
                 Rimolo-Donadio",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 11th Latin American Symposium on Circuits
                 \& Systems (LASCAS)}",
  title =        "{Siwa}: a {RISC-V RV32I} based Micro-Controller for
                 Implantable Medical Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/LASCAS45839.2020.9068952",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Garofalo:2020:XAQ,
  author =       "Angelo Garofalo and Giuseppe Tagliavini and Francesco
                 Conti and Davide Rossi and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2020 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "{XpulpNN}: Accelerating Quantized Neural Networks on
                 {RISC-V} Processors Through {ISA} Extensions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "186--191",
  year =         "2020",
  DOI =          "https://doi.org/10.23919/DATE48585.2020.9116529",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gokulan:2020:DBD,
  author =       "T Gokulan and Akshay Muraleedharan and Kuruvilla
                 Varghese",
  editor =       "{IEEE}",
  booktitle =    "{2020 23rd Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "Design of a 32-bit, dual pipeline superscalar {RISC-V}
                 processor on {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "340--343",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/DSD51259.2020.00062",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Greengard:2020:NWR,
  author =       "Samuel Greengard",
  title =        "News: Will {RISC-V} revolutionize computing?",
  journal =      j-CACM,
  volume =       "63",
  number =       "5",
  pages =        "30--32",
  month =        may,
  year =         "2020",
  CODEN =        "CACMA2",
  DOI =          "https://doi.org/10.1145/3386377",
  ISSN =         "0001-0782 (print), 1557-7317 (electronic)",
  ISSN-L =       "0001-0782",
  bibdate =      "Tue Apr 21 15:30:10 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cacm2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://dl.acm.org/doi/abs/10.1145/3386377",
  abstract =     "The open instruction set for microprocessors promises
                 to reshape computing and introduce new, more powerful
                 capabilities.",
  acknowledgement = ack-nhfb,
  fjournal =     "Communications of the ACM",
  journal-URL =  "https://dl.acm.org/loi/cacm",
}

@Article{Harb:2020:FPC,
  author =       "Hassan Harb and Cyrille Chavet",
  title =        "Fully parallel circular-shift rotation network for
                 communication standards",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "67",
  number =       "12",
  pages =        "3412--3416",
  month =        dec,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/TCSII.2020.2997691",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Tue Dec 19 08:23:53 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://ieeexplore.ieee.org/document/9099895",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Circuits Syst. II, Exp. Briefs",
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
}

@InProceedings{He:2020:HPR,
  author =       "Jiongrui He and Seok-Bum Ko",
  editor =       "{IEEE}",
  booktitle =    "{2020 International Conference on Electronics,
                 Information, and Communication (ICEIC)}",
  title =        "High-performance {RISC-V} processor with improved
                 dispatch and commit schemes",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICEIC49074.2020.9051258",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Herdt:2020:ASV,
  author =       "Vladimir Herdt and Daniel Gro{\ss}e and S{\"o}ren
                 Tempel and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 38th International Conference on Computer
                 Design (ICCD)}",
  title =        "Adaptive Simulation with Virtual Prototypes for
                 {RISC-V}: Switching Between Fast and Accurate at
                 Runtime",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "312--315",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICCD50377.2020.00059",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Herdt:2020:CRV,
  author =       "Vladimir Herdt and Daniel Gro{\ss}e and Rolf
                 Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2020 57th {ACM\slash IEEE} Design Automation
                 Conference (DAC)}",
  title =        "Closing the {RISC-V} Compliance Gap: Looking from the
                 Negative Testing Side",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/DAC18072.2020.9218629",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Herdt:2020:ECL,
  author =       "Vladimir Herdt and Daniel Gro{\ss}e and Eyck Jentzsch
                 and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2020 Forum for Specification and Design Languages
                 (FDL)}",
  title =        "Efficient Cross-Level Testing for Processor
                 Verification: a {RISC-V} Case-Study",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/FDL50818.2020.9232941",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Herdt:2020:FAP,
  author =       "Vladimir Herdt and Daniel Gro{\ss}e and Rolf
                 Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2020 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Fast and Accurate Performance Evaluation for {RISC-V}
                 using Virtual Prototypes",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "618--621",
  year =         "2020",
  DOI =          "https://doi.org/10.23919/DATE48585.2020.9116522",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Herdt:2020:TST,
  author =       "Vladimir Herdt and Daniel Gro{\ss}e and Rolf
                 Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2020 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Towards Specification and Testing of {RISC-V ISA}
                 Compliance",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "995--998",
  year =         "2020",
  DOI =          "https://doi.org/10.23919/DATE48585.2020.9116193",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Hoang:2020:CAT,
  author =       "Trong-Thuc Hoang and Ckristian Duran and Akira
                 Tsukamoto and Kuniyasu Suzaki and Cong-Kha Pham",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Cryptographic Accelerators for Trusted Execution
                 Environment in {RISC-V} Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ISCAS45731.2020.9180551",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Horne:2020:GSF,
  author =       "Mitchell Horne",
  title =        "Getting Started with {FreeBSD\slash RISC-V}",
  journal =      "FreeBSD Journal",
  volume =       "??",
  number =       "??",
  pages =        "12--17",
  month =        jan # "\slash " # feb,
  year =         "2020",
  bibdate =      "Fri Dec 23 11:24:52 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://freebsdfoundation.org/wp-content/uploads/2020/03/Getting-Started-With-FreeBSD-RISC-V.pdf",
  acknowledgement = ack-nhfb,
  journal-URL =  "https://freebsdfoundation.org/our-work/journal/",
  remark =       "This article contains a clear description of
                 cross-compiling a kernel for FreeBSD on RISC-V on
                 another (non-RISC-V) FreeBSD system, creating a virtual
                 image, booting the new image with qemu-system-riscv64,
                 enabling networking, and later doing cross-compiled
                 kernel updates.",
}

@InProceedings{Imianosky:2020:ECC,
  author =       "Carolina Imianosky and Paulo R. O. Valim and Cesar A.
                 Zeferino and Felipe Viel",
  editor =       "{IEEE}",
  booktitle =    "{2020 X Brazilian Symposium on Computing Systems
                 Engineering (SBESC)}",
  title =        "Evaluating the {CCSDS 123} Compressor Running on
                 {RISC-V} and {ARM} Architectures",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/SBESC51047.2020.9277854",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Jain:2020:IEB,
  author =       "Vineet Jain and Abhishek Sharma and Eduardo Augusto
                 Bezerra",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 9th International Conference on
                 Communication Systems and Network Technologies
                 (CSNT)}",
  title =        "Implementation and Extension of Bit Manipulation
                 Instruction on {RISC-V} Architecture using {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "167--172",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/CSNT48778.2020.9115759",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Johns:2020:MRV,
  author =       "Matthew Johns and Tom J. Kazmierski",
  editor =       "{IEEE}",
  booktitle =    "{2020 Forum for Specification and Design Languages
                 (FDL)}",
  title =        "A Minimal {RISC-V} Vector Processor for Embedded
                 Systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/FDL50818.2020.9232940",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kadomoto:2020:RVP,
  author =       "Junichiro Kadomoto and Hidetsugu Irie and Shuichi
                 Sakai",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE Symposium in Low-Power and High-Speed Chips
                 (COOL CHIPS)}",
  title =        "A {RISC-V} Processor with an Inter-Chiplet Wireless
                 Communication Interface for Shape-Changeable
                 Computers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--3",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/COOLCHIPS49199.2020.9097641",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Kamaleldin:2020:TMR,
  author =       "Ahmed Kamaleldin and Salma Hesham and Diana
                 G{\"o}hringer",
  title =        "Towards a Modular {RISC-V} Based Many-Core
                 Architecture for {FPGA} Accelerators",
  journal =      j-IEEE-ACCESS,
  volume =       "8",
  number =       "",
  pages =        "148812--148826",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ACCESS.2020.3015706",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Karabulut:2020:RRV,
  author =       "Emre Karabulut and Aydin Aysu",
  editor =       "{IEEE}",
  booktitle =    "{2020 30th International Conference on
                 Field-Programmable Logic and Applications (FPL)}",
  title =        "{RANTT}: a {RISC-V} Architecture Extension for the
                 Number Theoretic Transform",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "26--32",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/FPL50879.2020.00016",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kim:2020:FCC,
  author =       "Jungwoo Kim and Jae Min Kim and Sangwook Han and
                 Pritesh Vora and Pranav Dayal and Hyunggi Kim and
                 Jonghwan Lee and Daeyoung Yoon and Jeiyoung Lee and
                 Tienyu Chang and Ivan Siu-Chuang Lu and Kee-Bong Song
                 and Sang Won Son and Jongwoo Lee",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE Radio Frequency Integrated Circuits
                 Symposium (RFIC)}",
  title =        "A Flexible Control and Calibration Architecture Using
                 {RISC-V MCU} for {5G} Millimeter-wave Mobile {RF}
                 Transceivers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "203--206",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/RFIC49505.2020.9218424",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kim:2020:RIL,
  author =       "Haeyoung Kim and Jinjae Lee and Derry Pratama and Asep
                 Muhamad Awaludin and Howon Kim and Donghyun Kwon",
  editor =       "{IEEE}",
  booktitle =    "{2020 {IEEE\slash ACM} International Conference On
                 Computer Aided Design (ICCAD)}",
  title =        "{RIMI}: Instruction-level Memory Isolation for
                 Embedded Systems on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--9",
  year =         "2020",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lee:2020:RVF,
  author =       "Jaewon Lee and Hanning Chen and Jeffrey Young and
                 Hyesoon Kim",
  editor =       "{IEEE}",
  booktitle =    "{2020 30th International Conference on
                 Field-Programmable Logic and Applications (FPL)}",
  title =        "{RISC-V FPGA} Platform Toward {ROS}-Based Robotics
                 Application",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "370--370",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/FPL50879.2020.00075",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lei:2020:HRP,
  author =       "Mai Lei and Tian-Yu Yin and Yu-Chao Zhou and Jun Han",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 15th International Conference on
                 Solid-State \& Integrated Circuit Technology
                 (ICSICT)}",
  title =        "Highly Reconfigurable Performance Monitoring Unit on
                 {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--3",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICSICT49897.2020.9278263",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Li:2020:IMS,
  author =       "Renwei Li and Junning Wu and Enqiang Dai",
  editor =       "{IEEE}",
  booktitle =    "{2020 International Conference on Intelligent
                 Computing, Automation and Systems (ICICAS)}",
  title =        "An Improved {M/T} Speed Algorithm Based on {RISC-V
                 DSP}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "105--108",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICICAS51530.2020.00029",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lima:2020:ORV,
  author =       "Pedro Lima and Caio Vieira and Jorge Reis and
                 Alexandre Almeida and Jarbas Silveira and Roger Goerl
                 and C{\'e}sar Marcon",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE Latin-American Test Symposium (LATS)}",
  title =        "Optimizing {RISC-V ISA} Usage by Sharing Coprocessors
                 on {MPSoC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/LATS49555.2020.9093677",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lu:2020:DIS,
  author =       "Liangliang Lu and Ming Zhang and Dingxin He",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 2nd International Conference on Civil
                 Aviation Safety and Information Technology (ICCASIT)}",
  title =        "Design and Implementation of a Smart Home System Based
                 on the {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "300--304",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICCASIT50869.2020.9368845",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Madhavan:2020:AVA,
  author =       "B. Madhavan and A. Kamerish and R. Manimegalai",
  editor =       "{IEEE}",
  booktitle =    "{2020 Third International Conference on Smart Systems
                 and Inventive Technology (ICSSIT)}",
  title =        "{ATGP\_RISC-V}: Automation of Test Generator using
                 Pluggy for {RISC-V} Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "484--491",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICSSIT48917.2020.9214255",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Mantovani:2020:HBR,
  author =       "Paolo Mantovani and Robert Margelli and Davide Giri
                 and Luca P. Carloni",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE Custom Integrated Circuits Conference
                 (CICC)}",
  title =        "{HL5}: a 32-bit {RISC-V} Processor Designed with
                 High-Level Synthesis",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/CICC48029.2020.9075913",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Martins:2020:BMLa,
  author =       "J. Martins and S. Pinto",
  editor =       "Marko Bertogna and Federico Terraneo",
  booktitle =    "Workshop on {Next Generation Real-Time Embedded
                 Systems (NG-RES 2020)}",
  title =        "{Bao}: A modern lightweight embedded hypervisor",
  publisher =    "????",
  address =      "????",
  pages =        "3:1--3:14",
  year =         "2020",
  bibdate =      "Tue Dec 19 08:06:14 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://drops.dagstuhl.de/storage/01oasics/oasics-vol077-ng-res2020/OASIcs.NG-RES.2020.3/OASIcs.NG-RES.2020.3.pdf",
  acknowledgement = ack-nhfb,
  articleno =    "3",
}

@InProceedings{Martins:2020:BMLb,
  author =       "J. Martins and S. Pinto",
  editor =       "????",
  booktitle =    "Proceedings of the {Embedded World Conference,
                 February 2020}",
  title =        "{Bao}: A modern lightweight embedded hypervisor",
  publisher =    "????",
  address =      "????",
  pages =        "1--5",
  year =         "2020",
  bibdate =      "Tue Dec 19 08:06:14 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://sandro2pinto.github.io/files/ew2020-bao.pdf",
  acknowledgement = ack-nhfb,
}

@InProceedings{Molina-Robles:2020:CFV,
  author =       "Roberto Molina-Robles and Edgar Solera-Bolanos and
                 Ronny Garc{\'\i}a-Ram{\'\i}rez and Alfonso
                 Chac{\'o}n-Rodr{\'\i}guez and Alfredo Arnaud and Renato
                 Rimolo-Donadio",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 3rd Conference on PhD Research in
                 Microelectronics and Electronics in Latin America
                 (PRIME-LA)}",
  title =        "A compact functional verification flow for a {RISC-V
                 32I} based core",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/PRIME-LA47693.2020.9062717",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Nicholas:2020:SAS,
  author =       "Geraldine Shirley Nicholas and Yutian Gui and Fareena
                 Saqib",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 63rd International Midwest Symposium on
                 Circuits and Systems (MWSCAS)}",
  title =        "A Survey and Analysis on {SoC} Platform Security in
                 {ARM}, {Intel} and {RISC-V} Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "718--721",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/MWSCAS48704.2020.9184573",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ottavi:2020:MPR,
  author =       "Gianmarco Ottavi and Angelo Garofalo and Giuseppe
                 Tagliavini and Francesco Conti and Luca Benini and
                 Davide Rossi",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE Computer Society Annual Symposium on VLSI
                 (ISVLSI)}",
  title =        "A Mixed-Precision {RISC-V} Processor for Extreme-Edge
                 {DNN} Inference",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "512--517",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ISVLSI49217.2020.000-5",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Papadopoulos:2020:CTH,
  author =       "Nikolaos Charalampos Papadopoulos and Vasileios
                 Karakostas and Konstantinos Nikas and Nectarios Koziris
                 and Dionisios N. Pnevmatikatos",
  editor =       "{IEEE}",
  booktitle =    "{2020 30th International Conference on
                 Field-Programmable Logic and Applications (FPL)}",
  title =        "A Configurable {TLB} Hierarchy for the {RISC-V}
                 Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "85--90",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/FPL50879.2020.00024",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Park:2020:DFA,
  author =       "Heechun Park and Jinwoo Kim and Venkata Chaitanya
                 Krishna Chekuri and Majid Ahadi Dolatsara and Mohammed
                 Nabeel and Alabi Bojesomo and Satwik Patnaik and Ozgur
                 Sinanoglu and Madhavan Swaminathan and Saibal
                 Mukhopadhyay and Johann Knechtel and Sung Kyu Lim",
  title =        "Design Flow for Active Interposer-Based 2.5-D {ICs}
                 and Study of {RISC-V} Architecture With Secure {NoC}",
  journal =      "IEEE Transactions on Components, Packaging and
                 Manufacturing Technology",
  volume =       "10",
  number =       "12",
  pages =        "2047--2060",
  year =         "2020",
  CODEN =        "ITCPC8",
  DOI =          "https://doi.org/10.1109/TCPMT.2020.3033136",
  ISSN =         "2156-3950 (print), 2156-3985 (electronic)",
  ISSN-L =       "2156-3950",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Patsidis:2020:RVS,
  author =       "Kariofyllis Patsidis and Chrysostomos Nicopoulos and
                 Georgios Ch. Sirakoulis and Giorgos Dimitrakopoulos",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "{RISC-V$^2$}: a Scalable {RISC-V} Vector Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ISCAS45731.2020.9181071",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Petrisko:2020:BAO,
  author =       "Daniel Petrisko and Farzam Gilani and Mark Wyse and
                 Dai Cheol Jung and Scott Davidson and Paul Gao and Chun
                 Zhao and Zahra Azad and Sadullah Canakci and Bandhav
                 Veluri and Tavio Guarino and Ajay Joshi and Mark Oskin
                 and Michael Bedford Taylor",
  title =        "{BlackParrot}: an Agile Open-Source {RISC-V} Multicore
                 for Accelerator {SoCs}",
  journal =      j-IEEE-MICRO,
  volume =       "40",
  number =       "4",
  pages =        "93--102",
  month =        jul # "\slash " # aug,
  year =         "2020",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2020.2996145",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/gnu.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 https://www.math.utah.edu/pub/tex/bib/linux.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/unix.bib",
  abstract =     "This article introduces BlackParrot, which aims to be
                 the default open-source, Linux-capable, cache-coherent,
                 64-bit RISC-V multicore used by the world. In executing
                 this goal, our research aims to advance the world's
                 knowledge about the software engineering of hardware.
                 Although originally bootstrapped by the University of
                 Washington and Boston University via DARPA funding,
                 BlackParrot strives to be community driven and
                 infrastructure agnostic; a multicore which is Pareto
                 optimal in terms of power, performance, area, and
                 complexity. In order to ensure BlackParrot is easy to
                 use, extend, and, most importantly, trust, development
                 is guided by three core principles: Be Tiny, Be
                 Modular, and Be Friendly. Development efforts have
                 prioritized the use of intentional interfaces and
                 modularity and silicon validation as first-order design
                 metrics, so that users can quickly get started and
                 trust that their design will perform as expected when
                 deployed. BlackParrot has been validated in a
                 GlobalFoundries 12-nm FinFET tapeout. BlackParrot is
                 ideal as a standalone Linux processor or as a malleable
                 fabric for an agile accelerator SoC design flow.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
}

@InProceedings{Pnevmatikou:2020:FPC,
  author =       "Arsinoe Pnevmatikou and George Lentaris and Dimitrios
                 Soudris and Nikos Kokkalis",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Fast Packet Classification using {RISC-V} and
                 {HyperSplit} Acceleration on {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ISCAS45731.2020.9180588",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Poorhosseini:2020:CCR,
  author =       "Mehrdad Poorhosseini and Wolfgang Nebel and Kim
                 Gr{\"u}ttner",
  editor =       "{IEEE}",
  booktitle =    "{2020 International Conference on Omni-layer
                 Intelligent Systems (COINS)}",
  title =        "A Compiler Comparison in the {RISC-V} Ecosystem",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/COINS49042.2020.9191411",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "gcc; LLVM/clang",
}

@Article{Qui:2020:DIB,
  author =       "Nguyen My Qui and Chang Hong Lin and Poki Chen",
  title =        "Design and Implementation of a 256-Bit {RISC-V}-Based
                 Dynamically Scheduled Very Long Instruction Word on
                 {FPGA}",
  journal =      j-IEEE-ACCESS,
  volume =       "8",
  number =       "",
  pages =        "172996--173007",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ACCESS.2020.3024851",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Ramirez:2020:FDR,
  author =       "Wilmer Ramirez and Marco Sarmiento and Elkim Roa",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 11th Latin American Symposium on Circuits
                 \& Systems (LASCAS)}",
  title =        "A Flexible Debugger for a {RISC-V} Based 32-bit
                 {System-on-Chip}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/LASCAS45839.2020.9068995",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ravaglia:2020:MLA,
  author =       "Leonardo Ravaglia and Manuele Rusci and Alessandro
                 Capotondi and Francesco Conti and Lorenzo Pellegrini
                 and Vincenzo Lomonaco and Davide Maltoni and Luca
                 Benini",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE Workshop on Signal Processing Systems
                 (SiPS)}",
  title =        "Memory-Latency-Accuracy Trade-Offs for Continual
                 Learning on a {RISC-V} Extreme-Edge Node",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/SiPS50750.2020.9195220",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Roy:2020:EHS,
  author =       "Debapriya Basu Roy and Tim Fritzmann and Georg Sigl",
  editor =       "{IEEE}",
  booktitle =    "{2020 {IEEE\slash ACM} International Conference On
                 Computer Aided Design (ICCAD)}",
  title =        "Efficient Hardware\slash Software Co-Design for
                 Post-Quantum Crypto Algorithm {SIKE} on {ARM} and
                 {RISC-V} based Microcontrollers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--9",
  year =         "2020",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Santos:2020:LCF,
  author =       "Douglas Almeida Santos and Lucas Matana Luza and Cesar
                 Albenes Zeferino and Luigi Dilillo and Douglas Rossi
                 Melo",
  editor =       "{IEEE}",
  booktitle =    "{2020 15th Design \& Technology of Integrated Systems
                 in Nanoscale Era (DTIS)}",
  title =        "A Low-Cost Fault-Tolerant {RISC-V} Processor for Space
                 Systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/DTIS48698.2020.9081185",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Schmidt:2020:PFG,
  author =       "Colin Schmidt and Alon Amid and John Wright and Ben
                 Keller and Howard Mao and Keertana Settaluri and Jarno
                 Salomaa and Jerry Zhao and Albert Ou and Krste
                 Asanovi{\'c} and Borivoje Nikoli{\'c}",
  title =        "Programmable Fine-Grained Power Management and System
                 Analysis of {RISC-V} Vector Processors in 28-nm
                 {FD-SOI}",
  journal =      "IEEE Solid-State Circuits Letters",
  volume =       "3",
  number =       "",
  pages =        "210--213",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/LSSC.2020.3010295",
  ISSN =         "2573-9603",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Misc{SEGGER:2020:SFP,
  author =       "{SEGGER Microcontroller}",
  title =        "{SEGGER} Floating-Point Library",
  howpublished = "Web site.",
  month =        jan,
  year =         "2020",
  bibdate =      "Fri Feb 07 06:02:26 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://www.segger.com/products/development-tools/runtime-library/technology/floating-point-library/",
  abstract =     "The floating-point library contains complete, fully
                 optimized and verified floating point functionality,
                 which is required for devices without an FPU. The
                 floating-point emulator, a crucial part of the
                 floating-point library, of the Arm and RISC-V variants
                 are written in assembly language, optimized either for
                 small code size or increased execution speed. For other
                 processor architectures the library has a portable C
                 implementation. \ldots{} The SEGGER Floating-Point
                 Library is delivered in source code, with optional
                 rights for redistribution in object code form. All
                 source files, a mix of C code and assembly, are fully
                 commented. The floating-point emulator, providing the
                 low-level functions, is entirely written in assembly.
                 Higher level functions are implemented as a mix of
                 primarily C code with some assembly routines. The code
                 can be compiled with any ANSO-compliant C compiler,
                 such as GCC, Clang, or IAR.",
  acknowledgement = ack-nhfb,
}

@Article{Sharma:2020:CRV,
  author =       "Niraj Sharma and Riya Jain and Madhumita Mohan and
                 Sachin Patkar and Rainer Leupers and Nikhil Rishiyur
                 and Farhad Merchant",
  title =        "{CLARINET}: a {RISC-V} Based Framework for Posit
                 Arithmetic Empiricism",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--20",
  day =          "30",
  month =        may,
  year =         "2020",
  DOI =          "https://doi.org/10.48550/arXiv.2006.00364",
  bibdate =      "Sat Dec 16 10:27:27 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://arxiv.org/abs/2006.00364",
  abstract =     "Many engineering and scientific applications require
                 high precision arithmetic. IEEE 754-2008 compliant
                 (floating-point) arithmetic is the de facto standard
                 for performing these computations. Recently, posit
                 arithmetic has been proposed as a drop-in replacement
                 for floating-point arithmetic. The posit{\TM} data
                 representation and arithmetic claim several absolute
                 advantages over the floating-point format and
                 arithmetic, including higher dynamic range, better
                 accuracy, and superior performance-area trade-offs.
                 However, there does not exist any accessible, holistic
                 framework that facilitates the validation of these
                 claims of posit arithmetic, especially when the claims
                 involve long accumulations (quire).\par

                 In this paper, we present a consolidated
                 general-purpose processor-based framework to support
                 posit arithmetic empiricism. The end-users of the
                 framework have the liberty to seamlessly experiment
                 with their applications using posit and floating-point
                 arithmetic since the framework is designed for the two
                 number systems to coexist. Melodica is a posit
                 arithmetic core that implements parametric fused
                 operations that uniquely involve the quire data type.
                 Clarinet is a Melodica-enabled processor based on the
                 RISC-V ISA. To the best of our knowledge, this is the
                 first-ever integration of quire with a RISC-V core. To
                 show the effectiveness of the Clarinet platform, we
                 perform an extensive application study and benchmark
                 some of the common linear algebra and computer vision
                 kernels. We emulate Clarinet on a Xilinx FPGA and
                 present utilization and timing data. Clarinet and
                 Melodica remain actively under development and are
                 available in open-source for posit arithmetic
                 empiricism.",
  acknowledgement = ack-nhfb,
}

@InProceedings{Singh:2020:DIB,
  author =       "Aslesa Singh and Neil Franklin and Nidhi Gaur and
                 Paursuh Bhulania",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 5th International Conference on Computing
                 Communication and Automation (ICCCA)}",
  title =        "Design and Implementation of a 32-bit {ISA RISC-V}
                 Processor Core using {Virtex-7} and
                 {Virtex-UltraScale}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "126--130",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICCCA49541.2020.9250850",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Su:2020:RRV,
  author =       "Charlie Hong-Men Su",
  editor =       "{IEEE}",
  booktitle =    "{2020 International Symposium on VLSI Design,
                 Automation and Test (VLSI-DAT)}",
  title =        "The Rise of {RISC-V} from Edge to Cloud",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--1",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/VLSI-DAT49148.2020.9196271",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Suzaki:2020:LIP,
  author =       "Kuniyasu Suzaki and Kenta Nakajima and Tsukasa Oi and
                 Akira Tsukamoto",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 19th International Conference on Trust,
                 Security and Privacy in Computing and Communications
                 (TrustCom)}",
  title =        "Library Implementation and Performance Analysis of
                 {GlobalPlatform TEE} Internal {API} for {Intel SGX} and
                 {RISC-V} Keystone",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1200--1208",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/TrustCom50675.2020.00161",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tada:2020:IGS,
  author =       "Jubee Tada and Keiichi Sato",
  editor =       "{IEEE}",
  booktitle =    "{2020 Eighth International Symposium on Computing and
                 Networking Workshops (CANDARW)}",
  title =        "An Implementation of a Grid Square Codes Generator on
                 a {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "294--297",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/CANDARW51189.2020.00064",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tehrani:2020:RVE,
  author =       "Etienne Tehrani and Tarik Graba and Abdelmalek Si
                 Merabet and Jean-Luc Danger",
  editor =       "{IEEE}",
  booktitle =    "{2020 23rd Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "{RISC-V} Extension for Lightweight Cryptography",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "222--228",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/DSD51259.2020.00045",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Torres-Sanchez:2020:DAI,
  author =       "Enrique Torres-S{\'a}nchez and Jes{\'u}s
                 Alastruey-Bened{\'e} and Enrique Torres-Moreno",
  editor =       "{IEEE}",
  booktitle =    "{2020 XXXV Conference on Design of Circuits and
                 Integrated Systems (DCIS)}",
  title =        "Developing an {AI IoT} application with open software
                 on a {RISC-V SoC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/DCIS51330.2020.9268645",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Uytterhoeven:2020:CDB,
  author =       "Roel Uytterhoeven and Wim Dehaene",
  title =        "Completion Detection-Based Timing Error Detection and
                 Correction in a Near-Threshold {RISC-V} Microprocessor
                 in {FDSOI 28} nm",
  journal =      "IEEE Solid-State Circuits Letters",
  volume =       "3",
  number =       "",
  pages =        "230--233",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/LSSC.2020.3006626",
  ISSN =         "2573-9603",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wali:2020:AIO,
  author =       "Imran Wali and Alfonso S{\'a}nchez-Maci{\'a}n and
                 Alexis Ramos and Juan Antonio Maestro",
  editor =       "{IEEE}",
  booktitle =    "{2020 27th IEEE International Conference on
                 Electronics, Circuits and Systems (ICECS)}",
  title =        "Analyzing the impact of the Operating System on the
                 Reliability of a {RISC-V FPGA} Implementation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICECS49266.2020.9294858",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wang:2020:RAE,
  author =       "X. Wang and B. Williams and J. D. Leidel and A. Ehret
                 and M. Kinsy and Y. Chen",
  editor =       "{ACM}",
  booktitle =    "Proceedings of the {57th ACM\slash IEEE Design
                 Automation Conference (DAC), July 2020}",
  title =        "{Remote Atomic Extension (RAE)} for scalable high
                 performance computing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  bookpages =    "1378",
  pages =        "1--6",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/DAC18072.2020.9218589",
  ISBN =         "1-4503-6725-9, 1-72812-426-3",
  ISBN-13 =      "978-1-4503-6725-7, 978-1-72812-426-1",
  LCCN =         "TA174 .D458 2019",
  bibdate =      "Tue Dec 19 08:14:42 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://ieeexplore.ieee.org/document/9218589",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wang:2020:UVP,
  author =       "Jiayi Wang and Nianxiong Tan and Yangfan Zhou and Ting
                 Li and Junhu Xia",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 5th International Conference on Integrated
                 Circuits and Microsystems (ICICM)}",
  title =        "A {UVM} Verification Platform for {RISC-V SoC} from
                 Module to System Level",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "242--246",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICICM50929.2020.9292250",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Wright:2020:DCR,
  author =       "John Charles Wright and Colin Schmidt and Ben Keller
                 and Daniel Palmer Dabbelt and Jaehwa Kwak and Vighnesh
                 Iyer and Nandish Mehta and Pi-Feng Chiu and Stevo
                 Bailey and Krste Asanovi{\'c} and Borivoje
                 Nikoli{\'c}",
  title =        "A Dual-Core {RISC-V} Vector Processor With On-Chip
                 Fine-Grain Power Management in 28-nm {FD-SOI}",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "28",
  number =       "12",
  pages =        "2721--2725",
  year =         "2020",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2020.3030243",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}

@Article{Xin:2020:VDS,
  author =       "Guozhu Xin and Jun Han and Tianyu Yin and Yuchao Zhou
                 and Jianwei Yang and Xu Cheng and Xiaoyang Zeng",
  title =        "{VPQC}: a Domain-Specific Vector Processor for
                 Post-Quantum Cryptography Based on {RISC-V}
                 Architecture",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-1,
  volume =       "67",
  number =       "8",
  pages =        "2672--2684",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/TCSI.2020.2983185",
  ISSN =         "1549-8328 (print), 1558-0806 (electronic)",
  ISSN-L =       "1549-8328",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I: Regular
                 Papers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919",
}

@InProceedings{Yang:2020:AAR,
  author =       "Chia-Hsiang Yang",
  editor =       "{IEEE}",
  booktitle =    "{2020 International Symposium on VLSI Design,
                 Automation and Test (VLSI-DAT)}",
  title =        "{AI} Acceleration with {RISC-V} for Edge Computing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--1",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/VLSI-DAT49148.2020.9196404",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Yin:2020:HHP,
  author =       "Tianyu Yin and Guozhu Xin and Jun Han",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 15th International Conference on
                 Solid-State \& Integrated Circuit Technology
                 (ICSICT)}",
  title =        "{HPME}: a High-Performance Hardware Memory Encryption
                 Engine Based on {RISC-V TEE}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--3",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICSICT49897.2020.9278286",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zaruba:2020:CRV,
  author =       "Florian Zaruba and Fabian Schuiki and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE Hot Chips 32 Symposium (HCS)}",
  title =        "A 4096-core {RISC-V} Chiplet Architecture for
                 Ultra-efficient Floating-point Computing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--24",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/HCS49909.2020.9220474",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  remark =       "This article consists only of a collection of slides
                 from the author's conference presentation",
}

@Article{Zhang:2020:MRB,
  author =       "Jialiang Zhang and Yue Zha and Nicholas Beckwith and
                 Bangya Liu and Jing Li",
  title =        "{MEG}: a {RISCV}-based System Emulation Infrastructure
                 for Near-data Processing Using {FPGAs} and
                 High-bandwidth Memory",
  journal =      j-TRETS,
  volume =       "13",
  number =       "4",
  pages =        "19:1--19:24",
  month =        oct,
  year =         "2020",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3409114",
  ISSN =         "1936-7406 (print), 1936-7414 (electronic)",
  ISSN-L =       "1936-7406",
  bibdate =      "Fri Oct 2 07:58:13 MDT 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/trets.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3409114",
  abstract =     "Emerging three-dimensional (3D) memory technologies,
                 such as the Hybrid Memory Cube (HMC) and High Bandwidth
                 Memory (HBM), provide high-bandwidth and massive
                 memory-level parallelism. With the growing
                 heterogeneity and complexity of computer systems
                 \ldots{}",
  acknowledgement = ack-nhfb,
  articleno =    "19",
  fjournal =     "ACM Transactions on Reconfigurable Technology and
                 Systems (TRETS)",
  journal-URL =  "https://dl.acm.org/loi/trets",
}

@InProceedings{Zhang:2020:ULP,
  author =       "Yong-Liang Zhang and Wei-Zhen Wang and Qiang Li and
                 Zhi-Yan Jia and Jun Han and Xiao-Yang Zeng and Xu
                 Cheng",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE 15th International Conference on
                 Solid-State \& Integrated Circuit Technology
                 (ICSICT)}",
  title =        "An Ultra-low-power High-precision Dynamic Gesture
                 Recognition Coprocessor Based On {RISC-V}
                 Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/ICSICT49897.2020.9278334",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhong:2020:RVS,
  author =       "Xinchao Zhong and Chiu-Wing Sham and Longyu Ma",
  editor =       "{IEEE}",
  booktitle =    "{2020 IEEE Asia Pacific Conference on Circuits and
                 Systems (APCCAS)}",
  title =        "A {RISC-V SoC} for Mobile Payment Based on Visible
                 Light Communication",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "102--105",
  year =         "2020",
  DOI =          "https://doi.org/10.1109/APCCAS50809.2020.9301688",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhou:2020:RVG,
  author =       "Yuzhi Zhou and Xi Jin and Tian Xiang",
  editor =       "ACM",
  booktitle =    "{SBDAI '20: 2020 2nd International Conference on Big
                 Data and Artificial Intelligence, Johannesburg, South
                 Africa, April 28--30, 2020}",
  title =        "{RISC-V} graphics rendering instruction set extensions
                 for embedded {AI} chips implementation",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "85--88",
  year =         "2020",
  DOI =          "https://doi.org/10.1145/3378904.3378926",
  ISBN =         "1-4503-7645-2",
  ISBN-13 =      "978-1-4503-7645-7",
  bibdate =      "Tue Dec 19 08:12:20 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://dl.acm.org/doi/pdf/10.1145/3378904.3378926",
  acknowledgement = ack-nhfb,
}

@Article{Zhu:2020:HIR,
  author =       "Lingjun Zhu and Lennart Bamberg and Anthony Agnesina
                 and Francky Catthoor and Dragomir Milojevic and Manu
                 Komalan and Julien Ryckaert and Alberto Garcia-Ortiz
                 and Sung Kyu Lim",
  title =        "Heterogeneous {3D} Integration for a {RISC-V} System
                 With {STT-MRAM}",
  journal =      j-IEEE-COMPUT-ARCHIT-LETT,
  volume =       "19",
  number =       "1",
  pages =        "51--54",
  month =        jan # "\slash " # jun,
  year =         "2020",
  DOI =          "https://doi.org/10.1109/LCA.2020.2992644",
  ISSN =         "1556-6056 (print), 1556-6064 (electronic)",
  ISSN-L =       "1556-6056",
  bibdate =      "Thu May 27 16:19:32 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeecomputarchitlett.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Computer Architecture Letters",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10208",
}

@InProceedings{Abella:2021:SRT,
  author =       "Jaume Abella and Sergi Alcaide and Jens Anders and
                 Francisco Bas and Steffen Becker and Elke {De Mulder}
                 and Nourhan Elhamawy and Frank K. G{\"u}rkaynak and
                 Helena Handschuh and Carles Hernandez and Mike Hutter
                 and Leonidas Kosmidis and Ilia Polian and Matthias
                 Sauer and Stefan Wagner and Francesco Regazzoni",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE European Test Symposium (ETS)}",
  title =        "Security, Reliability and Test Aspects of the {RISC-V}
                 Ecosystem",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--10",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ETS50041.2021.9465449",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Adel:2021:IFV,
  author =       "Abdelrahman Adel and Dina Saad and Mahmoud Abd {El
                 Mawgoed} and Mohamed Sharshar and Zyad Ahmed and Hala
                 Ibrahim and Hassan Mostafa",
  editor =       "{IEEE}",
  booktitle =    "{2021 International Conference on Microelectronics
                 (ICM)}",
  title =        "Implementation and Functional Verification of {RISC-V}
                 Core for Secure {IoT} Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "254--257",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICM52667.2021.9664926",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Adelt:2021:RIC,
  author =       "Peer Adelt and Bastian Koppelmann and Wolfgang Mueller
                 and Christoph Scheytt",
  editor =       "{IEEE}",
  booktitle =    "{MBMV 2021; 24th Workshop}",
  title =        "Register and Instruction Coverage Analysis for
                 Different {RISC-V ISA} Modules",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2021",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ahmadi-Pour:2021:CRV,
  author =       "Sallar Ahmadi-Pour and Vladimir Herdt and Rolf
                 Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{MBMV 2021; 24th Workshop}",
  title =        "Constrained Random Verification for {RISC-V}:
                 Overview, Evaluation and Discussion",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2021",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ahmadi-Pour:2021:RVA,
  author =       "Sallar Ahmadi-Pour and Vladimir Herdt and Rolf
                 Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2021 Forum on specification \& Design Languages
                 (FDL)}",
  title =        "{RISC-V AMS VP}: an Open Source Evaluation Platform
                 for Cyber-Physical Systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "01--07",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/FDL53530.2021.9568387",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{AlAssir:2021:ARV,
  author =       "Imad {Al Assir} and Mohamad {El Iskandarani} and Hadi
                 Rayan {Al Sandid} and Mazen A. R. Saghir",
  title =        "{Arrow}: a {RISC-V} Vector Accelerator for Machine
                 Learning Inference",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--6",
  day =          "15",
  month =        jul,
  year =         "2021",
  DOI =          "https://doi.org/10.48550/arXiv.2107.07169",
  bibdate =      "Tue Dec 19 08:04:01 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://arxiv.org/abs/2107.07169",
  abstract =     "In this paper we present Arrow, a configurable
                 hardware accelerator architecture that implements a
                 subset of the RISC-V v0.9 vector ISA extension aimed at
                 edge machine learning inference. Our experimental
                 results show that an Arrow co-processor can execute a
                 suite of vector and matrix benchmarks fundamental to
                 machine learning inference 2--78x faster than a scalar
                 RISC processor while consuming 20\%--99\% less energy
                 when implemented in a Xilinx XC7A200T-1SBG484C FPGA.",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ali:2021:VPU,
  author =       "Muhammad Ali and Matthias von Ameln and Diana
                 Goehringer",
  editor =       "{IEEE}",
  booktitle =    "{2021 24th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "Vector Processing Unit: a {RISC-V} based {SIMD}
                 Co-processor for Embedded Processing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "30--34",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/DSD53832.2021.00014",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Misc{Anonymous:2021:SFS,
  author =       "Anonymous",
  title =        "Source Files for {SiFive}'s {Freedom} Platforms",
  howpublished = "Web document.",
  year =         "2021",
  bibdate =      "Tue Dec 19 07:54:50 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://github.com/sifive/freedom",
  acknowledgement = ack-nhfb,
  remark =       "Archived and made read-only on 2 March 2021.",
}

@InProceedings{Aponte-Moreno:2021:RER,
  author =       "Alexander Aponte-Moreno and Felipe Restrepo-Calle and
                 Cesar Pedraza",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 22nd Latin American Test Symposium
                 (LATS)}",
  title =        "Reliability Evaluation of {RISC-V} and {ARM}
                 Microprocessors Through a New Fault Injection Tool",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/LATS53581.2021.9651874",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{AskariHemmat:2021:RVB,
  author =       "MohammadHossein AskariHemmat and Olexa Bilaniuk and
                 Sean Wagner and Yvon Savaria and Jean-Pierre David",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "{RISC-V} Barrel Processor for Deep Neural Network
                 Acceleration",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISCAS51556.2021.9401617",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Austin:2021:MIR,
  author =       "Todd Austin and Austin Harris and Tarunesh Verma and
                 Shijia Wei and Alex Kisil and Misiker Aga and Valeria
                 Bertacco and Baris Kasikci and Mohit Tiwari",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE Hot Chips 33 Symposium (HCS)}",
  title =        "{Morpheus II}: a {RISC-V} Security Extension for
                 Protecting Vulnerable Software and Hardware",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--18",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/HCS52781.2021.9567000",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Babu:2021:EBM,
  author =       "P. S. Babu and Snehashri Sivaraman and Deepa N. Sarma
                 and Tripti S. Warrier",
  editor =       "{IEEE}",
  booktitle =    "{2021 34th International Conference on VLSI Design and
                 2021 20th International Conference on Embedded Systems
                 (VLSID)}",
  title =        "Evaluation of Bit Manipulation Instructions in
                 Optimization of Size and Speed in {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "54--59",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/VLSID51830.2021.00014",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Bai:2021:BER,
  author =       "Chen Bai and Qi Sun and Jianwang Zhai and Yuzhe Ma and
                 Bei Yu and Martin D. F. Wong",
  editor =       "{IEEE}",
  booktitle =    "{2021 {IEEE\slash ACM} International Conference On
                 Computer Aided Design (ICCAD)}",
  title =        "{BOOM-Explorer}: {RISC-V BOOM} Microarchitecture
                 Design Space Exploration Framework",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--9",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICCAD51958.2021.9643455",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Bai:2021:HFI,
  author =       "Jiyuan Bai and Xiang Wang and Zikang Zhang and Chang
                 Cai and Gengsheng Chen",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 14th International Conference on ASIC
                 (ASICON)}",
  title =        "A Hierarchical Fault Injection System for {RISC-V}
                 Processors Targeting Single Event Upsets in
                 Flip-Flops",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ASICON52560.2021.9620299",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Balas:2021:RVR,
  author =       "Robert Balas and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2021 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "{RISC-V} for Real-time {MCUs} --- Software
                 Optimization and Microarchitectural Gap Analysis",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "874--877",
  year =         "2021",
  DOI =          "https://doi.org/10.23919/DATE51398.2021.9474114",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Barbirotta:2021:FTS,
  author =       "Marcello Barbirotta and Abdallah Cheikh and Antonio
                 Mastrandrea and Francesco Menichelli and Francesco
                 Vigli and Mauro Olivieri",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "A Fault Tolerant soft-core obtained from an
                 Interleaved-Multi-Threading {RISC-V} microprocessor
                 design",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/DFT52944.2021.9568368",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Bellocchi:2021:RVB,
  author =       "Gianluca Bellocchi and Alessandro Capotondi and
                 Francesco Conti and Andrea Marongiu",
  editor =       "{IEEE}",
  booktitle =    "{2021 24th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "A {RISC-V}-based {FPGA} Overlay to Simplify Embedded
                 Accelerator Deployment",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "9--17",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/DSD53832.2021.00011",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Bertaccini:2021:TFL,
  author =       "Luca Bertaccini and Matteo Perotti and Stefan Mach and
                 Pasquale Davide Schiavone and Florian Zaruba and Luca
                 Benini",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "{Tiny-FPU}: Low-Cost Floating-Point Support for Small
                 {RISC-V MCU} Cores",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISCAS51556.2021.9401149",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Biswas:2021:CSI,
  author =       "Arnab Kumar Biswas",
  title =        "Cryptographic Software {IP} Protection without
                 Compromising Performance or Timing Side-channel
                 Leakage",
  journal =      j-TACO,
  volume =       "18",
  number =       "2",
  pages =        "20:1--20:20",
  month =        mar,
  year =         "2021",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3443707",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Sat Mar 20 17:25:10 MDT 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3443707",
  abstract =     "Program obfuscation is a widely used cryptographic
                 software intellectual property (IP) protection
                 technique against reverse engineering attacks in
                 embedded systems. However, very few works have studied
                 the impact of combining various obfuscation techniques
                 on the obscurity (difficulty of reverse engineering)
                 and performance (execution time) of obfuscated
                 programs. In this article, we propose a Genetic
                 Algorithm (GA)-based framework that not only optimizes
                 obscurity and performance of obfuscated cryptographic
                 programs, but it also ensures very low timing
                 side-channel leakage. Our proposed Timing Side Channel
                 Sensitive Program Obfuscation Optimization Framework
                 (TSC-SPOOF) determines the combination of obfuscation
                 transformation functions that produce optimized
                 obfuscated programs with preferred optimization
                 parameters. In particular, TSC-SPOOF employs normalized
                 compression distance (NCD) and channel capacity to
                 measure obscurity and timing side-channel leakage,
                 respectively. We also use RISC-V rocket core running on
                 a Xilinx Zynq FPGA device as part of our framework to
                 obtain realistic results. The experimental results
                 clearly show that our proposed solution leads to
                 cryptographic programs with lower execution time,
                 higher obscurity, and lower timing side-channel leakage
                 than unguided obfuscation.",
  acknowledgement = ack-nhfb,
  articleno =    "20",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "https://dl.acm.org/loi/taco",
}

@Article{Bora:2021:HPC,
  author =       "Satyajit Bora and Roy Paily",
  title =        "A High-Performance Core Micro-Architecture Based on
                 {RISC-V ISA} for Low Power Applications",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "68",
  number =       "6",
  pages =        "2132--2136",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/TCSII.2020.3043204",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
}

@InProceedings{Boubakri:2021:OPT,
  author =       "Marouene Boubakri and Fausto Chiatante and Belhassen
                 Zouari",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 19th International Conference on Embedded
                 and Ubiquitous Computing (EUC)}",
  title =        "Open Portable Trusted Execution Environment framework
                 for {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/EUC53437.2021.00015",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Boubakri:2021:TFT,
  author =       "Marouene Boubakri and Fausto Chiatante and Belhassen
                 Zouari",
  editor =       "{IEEE}",
  booktitle =    "{2021 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Towards a firmware {TPM} on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "647--650",
  year =         "2021",
  DOI =          "https://doi.org/10.23919/DATE51398.2021.9474152",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Bruns:2021:TRV,
  author =       "Niklas Bruns and Vladimir Herdt and Daniel Gro{\ss}e
                 and Rolf Drechsler",
  title =        "Toward {RISC-V CSR} Compliance Testing",
  journal =      "IEEE Embedded Systems Letters",
  volume =       "13",
  number =       "4",
  pages =        "202--205",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/LES.2021.3077368",
  ISSN =         "1943-0663 (print), 1943-0671 (electronic)",
  ISSN-L =       "1943-0663",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Bruschi:2021:GHC,
  author =       "Nazareno Bruschi and Germain Haugou and Giuseppe
                 Tagliavini and Francesco Conti and Luca Benini and
                 Davide Rossi",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 39th International Conference on Computer
                 Design (ICCD)}",
  title =        "{GVSoC}: a Highly Configurable, Fast and Accurate
                 Full-Platform Simulator for {RISC-V} based {IoT}
                 Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "409--416",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICCD53106.2021.00071",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Caforio:2021:VMC,
  author =       "Flavia Caforio and Pierpaolo Iannicelli and Michele
                 Paolino and Daniel Raho",
  editor =       "{IEEE}",
  booktitle =    "{2021 10th Mediterranean Conference on Embedded
                 Computing (MECO)}",
  title =        "{VOSySmonitoRV}: a mixed-criticality solution on
                 {Linux}-capable {RISC-V} platforms",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/MECO52532.2021.9460246",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Cannizzaro:2021:RVB,
  author =       "Michael J. Cannizzaro and Evan W. Gretok and Alan D.
                 George",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE Space Computing Conference (SCC)}",
  title =        "{RISC-V} Benchmarking for Onboard Sensor Processing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "46--59",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/SCC49971.2021.00013",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Castro:2021:EDP,
  author =       "Jairo Walber Abdala Castro and Aurelio
                 Morales-Villanueva",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE XXVIII International Conference on
                 Electronics, Electrical Engineering and Computing
                 (INTERCON)}",
  title =        "Exploring Dynamic Partial Reconfiguration in a
                 Tightly-coupled Coprocessor Attached to a {RISC-V}
                 Soft-processor on a {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/INTERCON52678.2021.9532810",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Charaf:2021:RCE,
  author =       "Najdet Charaf and Ahmed Kamaleldin and Martin
                 Th{\"u}mmler and Diana G{\"o}hringer",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Parallel and Distributed
                 Processing Symposium Workshops (IPDPSW)}",
  title =        "{RV-CAP}: Enabling Dynamic Partial Reconfiguration for
                 {FPGA-Based RISC-V System-on-Chip}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "172--179",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/IPDPSW52791.2021.00033",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Cheikh:2021:KDV,
  author =       "A. Cheikh and S. Sordillo and A. Mastrandrea and F.
                 Menichelli and G. Scotti and M. Olivieri",
  title =        "{Klessydra-T}: Designing Vector Coprocessors for
                 Multithreaded Edge-Computing Cores",
  journal =      j-IEEE-MICRO,
  volume =       "41",
  number =       "2",
  pages =        "64--71",
  month =        mar # "\slash " # apr,
  year =         "2021",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2021.3050962",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu Apr 1 10:32:23 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
}

@InProceedings{Chen:2021:DVR,
  author =       "Jiarong Chen and Zixin Wang and Yingfeng Ding and
                 Haopeng Feng and Dihu Chen",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Conference on Computer
                 Science, Electronic Information Engineering and
                 Intelligent Control Technology (CEI)}",
  title =        "Design and verification of {RISC-V CPU} based on {HLS}
                 and {UVM}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "659--664",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/CEI52496.2021.9574575",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Chen:2021:SEE,
  author =       "Quanxiu Chen and Yi Liu and Zhenyu Wu and Jian Liao",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 15th International Conference on
                 Anti-counterfeiting, Security, and Identification
                 (ASID)}",
  title =        "A Single Event Effect Simulation Method for {RISC-V}
                 Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "106--110",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ASID52932.2021.9651696",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Cilardo:2021:MES,
  author =       "Alessandro Cilardo",
  editor =       "{IEEE}",
  booktitle =    "{2021 16th International Conference on Design \&
                 Technology of Integrated Systems in Nanoscale Era
                 (DTIS)}",
  title =        "Memory Encryption Support for an {FPGA}-based {RISC-V}
                 Implementation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/DTIS53253.2021.9505064",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Ciocirlan:2021:AEPa,
  author =       "Stefan Dan Ciocirlan and Dumitrel Loghin and Lavanya
                 Ramapantulu and Nicolae Tapus and Yong Meng Teo",
  title =        "The Accuracy and Efficiency of Posit Arithmetic",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  day =          "16",
  month =        sep,
  year =         "2021",
  bibdate =      "Sat Dec 16 15:13:00 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  abstract =     "Motivated by the increasing interest in the posit
                 numeric format, in this paper we evaluate the accuracy
                 and efficiency of posit arithmetic in contrast to the
                 traditional IEEE 754 32-bit floating-point (FP32)
                 arithmetic. We first design and implement a Posit
                 Arithmetic Unit (PAU), called POSAR, with flexible
                 bit-sized arithmetic suitable for applications that can
                 trade accuracy for savings in chip area. Next, we
                 analyze the accuracy and efficiency of POSAR with a
                 series of benchmarks including mathematical
                 computations, ML kernels, NAS Parallel Benchmarks
                 (NPB), and Cifar-10 CNN. This analysis is done on our
                 implementation of POSAR integrated into a RISC-V Rocket
                 Chip core in comparison with the IEEE 754-based
                 Floating Point Unit (FPU) of Rocket Chip. Our analysis
                 shows that POSAR can outperform the FPU, but the
                 results are not spectacular. For NPB, 32-bit posit
                 achieves better accuracy than FP32 and improves the
                 execution by up to 2\%. However, POSAR with 32-bit
                 posit needs 30\% more FPGA resources compared to the
                 FPU. For classic ML algorithms, we find that 8-bit
                 posits are not suitable to replace FP32 because they
                 exhibit low accuracy leading to wrong results. Instead,
                 16-bit posit offers the best option in terms of
                 accuracy and efficiency. For example, 16-bit posit
                 achieves the same Top-1 accuracy as FP32 on a Cifar-10
                 CNN with a speedup of 18\%.",
  acknowledgement = ack-nhfb,
  archiveprefix = "arXiv",
  eprint =       "2109.08225",
  primaryclass = "cs.AR",
}

@InProceedings{Ciocirlan:2021:AEPb,
  author =       "Stefan Dan Ciocirlan and Dumitrel Loghin and Lavanya
                 Ramapantulu and Nicolae {pu } and Yong Meng Teo",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 39th International Conference on Computer
                 Design (ICCD)}",
  title =        "The Accuracy and Efficiency of Posit Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "83--87",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICCD53106.2021.00024",
  bibdate =      "Fri Dec 15 09:21:55 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic; RISC-V",
}

@Article{Cococcioni:2021:VPO,
  author =       "Marco Cococcioni and Federico Rossi and Emanuele
                 Ruffaldi and Sergio Saponara",
  title =        "Vectorizing posit operations on {RISC-V} for faster
                 deep neural networks: experiments and comparison with
                 {ARM SVE}",
  journal =      "Neural Computing and Applications",
  volume =       "33",
  number =       "16",
  publisher =    pub-SV,
  address =      pub-SV:adr,
  pages =        "10575--10585",
  month =        feb,
  year =         "2021",
  DOI =          "https://doi.org/10.1007/s00521-021-05814-0",
  ISSN =         "1433-3058",
  ISSN-L =       "0941-0643",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}

@Article{Dao:2021:CPA,
  author =       "Ba-Anh Dao and Trong-Thuc Hoang and Anh-Tien Le and
                 Akira Tsukamoto and Kuniyasu Suzaki and Cong-Kha Pham",
  title =        "Correlation Power Analysis Attack Resisted
                 Cryptographic {RISC-V SoC} With Random Dynamic
                 Frequency Scaling Countermeasure",
  journal =      j-IEEE-ACCESS,
  volume =       "9",
  number =       "",
  pages =        "151993--152014",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ACCESS.2021.3126703",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Dave:2021:CLA,
  author =       "Avani Dave and Nilanjan Banerjee and Chintan Patel",
  editor =       "{IEEE}",
  booktitle =    "{2021 22nd International Symposium on Quality
                 Electronic Design (ISQED)}",
  title =        "{CARE}: Lightweight Attack Resilient Secure Boot
                 Architecture with Onboard Recovery for {RISC-V} based
                 {SOC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "516--521",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISQED51717.2021.9424322",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Delshadtehrani:2021:SSP,
  author =       "Leila Delshadtehrani and Sadullah Canakci and Manuel
                 Egele and Ajay Joshi",
  editor =       "{IEEE}",
  booktitle =    "{2021 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "{SealPK}: Sealable Protection Keys for {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1278--1281",
  year =         "2021",
  DOI =          "https://doi.org/10.23919/DATE51398.2021.9473932",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{DeSio:2021:SEH,
  author =       "Corrado {De Sio} and Sarah Azimi and Andrea Portaluri
                 and Luca Sterpone",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "{SEU} Evaluation of Hardened-by-Replication Software
                 in {RISC-V} Soft Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/DFT52944.2021.9568342",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{DiGirolamo:2021:RVN,
  author =       "Salvatore {Di Girolamo} and Andreas Kurth and
                 Alexandru Calotoiu and Thomas Benz and Timo Schneider
                 and Jakub Ber{\'a}nek and Luca Benini and Torsten
                 Hoefler",
  editor =       "{IEEE}",
  booktitle =    "{2021 ACM\slash IEEE 48th Annual International
                 Symposium on Computer Architecture (ISCA)}",
  title =        "A {RISC-V} in-network accelerator for flexible
                 high-performance low-power packet processing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "958--971",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISCA52012.2021.00079",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ditzel:2021:AMR,
  author =       "Dave Ditzel and Roger Espasa and Nivard Aymerich and
                 Allen Baum and Tom Berg and Jim Burr and Eric Hao and
                 Jayesh Iyer and Miquel Izquierdo and Shankar Jayaratnam
                 and Darren Jones and Chris Klingner and Jin Kim and
                 Stephen Lee and Marc Lupon and Grigorios Magklis and
                 Bojan Maric and Rajib Nath and Mike Neilly and Duane
                 Northcutt and Bill Orner and Jose Renau and Gerard
                 Reves and Xavier Reves and Tom Riordan and Pedro
                 Sanchez and Sri Samudrala and Guillem Sole and Raymond
                 Tang and Tommy Thorn and Francisco Torres and Sebastia
                 Tortella and Daniel Yau",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE Hot Chips 33 Symposium (HCS)}",
  title =        "Accelerating {ML} Recommendation with over a Thousand
                 {RISC-V\slash Tensor} Processors on {Esperanto}'s
                 {ET-SoC-1} Chip",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--23",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/HCS52781.2021.9566904",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Dorflinger:2021:CSO,
  author =       "A. D{\"o}rflinger and M. Albers and B. Kleinbeck and
                 Y. Guan and H. Michalik and R. Klink and C. Blochwitz
                 and A. Nechi and M. Berekovic",
  editor =       "{ACM}",
  booktitle =    "{CF '21: Proceedings of the 18th ACM International
                 Conference on Computing Frontiers, May 2021}",
  title =        "A comparative survey of open-source application-class
                 {RISC-V} processor implementations",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "12--20",
  year =         "2021",
  DOI =          "https://doi.org/10.1145/3457388.3458657",
  ISBN =         "1-4503-8404-8",
  ISBN-13 =      "978-1-4503-8404-9",
  bibdate =      "Tue Dec 19 07:49:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3457388.3458657",
  abstract =     "The numerous emerging implementations of RISC-V
                 processors and frameworks underline the success of this
                 Instruction Set Architecture (ISA) specification. The
                 free and open source character of many implementations
                 facilitates their adoption in academic and commercial
                 projects. As yet it is not easy to say which
                 implementation fits best for a system with given
                 requirements such as processing performance or power
                 consumption. With varying backgrounds and histories,
                 the developed RISC-V processors are very different from
                 each other. Comparisons are difficult, because results
                 are reported for arbitrary technologies and
                 configuration settings. Scaling factors are used to
                 draw comparisons, but this gives only rough estimates.
                 In order to give more substantiated results, this paper
                 compares the most prominent open-source
                 application-class RISC-V projects by running identical
                 benchmarks on identical platforms with defined
                 configuration settings. The Rocket, BOOM, CVA6, and
                 SHAKTI C-Class implementations are evaluated for
                 processing performance, area and resource utilization,
                 power consumption as well as efficiency. Results are
                 presented for the Xilinx Virtex UltraScale+ family and
                 GlobalFoundries 22FDX ASIC technology.",
  acknowledgement = ack-nhfb,
}

@InProceedings{Dow:2021:SHS,
  author =       "Hsu-Kang Dow and Tuo Li and William Miles and Sri
                 Parameswaran",
  editor =       "{IEEE}",
  booktitle =    "{2021 58th {ACM\slash IEEE} Design Automation
                 Conference (DAC)}",
  title =        "{SHORE}: Hardware\slash Software Method for Memory
                 Safety Acceleration on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "289--294",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/DAC18074.2021.9586293",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Eliahu:2021:MME,
  author =       "Adi Eliahu and Ronny Ronen and Pierre-Emmanuel
                 Gaillardon and Shahar Kvatinsky",
  title =        "{multiPULPly}: a Multiplication Engine for
                 Accelerating Neural Networks on Ultra-low-power
                 Architectures",
  journal =      j-JETC,
  volume =       "17",
  number =       "2",
  pages =        "24:1--24:27",
  month =        apr,
  year =         "2021",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3432815",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Apr 30 06:39:29 MDT 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jetc.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3432815",
  abstract =     "Computationally intensive neural network applications
                 often need to run on resource-limited low-power
                 devices. Numerous hardware accelerators have been
                 developed to speed up the performance of neural network
                 applications and reduce power consumption; however,
                 most focus on data centers and full-fledged systems.
                 Acceleration in ultra-low-power systems has been only
                 partially addressed. In this article, we present
                 multiPULPly, an accelerator that integrates memristive
                 technologies within standard low-power CMOS technology,
                 to accelerate multiplication in neural network
                 inference on ultra-low-power systems. This accelerator
                 was designated for PULP, an open-source microcontroller
                 system that uses low-power RISC-V processors.
                 Memristors were integrated into the accelerator to
                 enable power consumption only when the memory is
                 active, to continue the task with no context-restoring
                 overhead, and to enable highly parallel analog
                 multiplication. To reduce the energy consumption, we
                 propose novel dataflows that handle common
                 multiplication scenarios and are tailored for our
                 architecture. The accelerator was tested on FPGA and
                 achieved a peak energy efficiency of 19.5 TOPS/W,
                 outperforming state-of-the-art accelerators by $ 1.5
                 \times $ to $ 4.5 \times $.",
  acknowledgement = ack-nhfb,
  articleno =    "24",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "https://dl.acm.org/loi/jetc",
}

@InProceedings{Elkhatib:2021:ARV,
  author =       "Rami Elkhatib and Reza Azarderakhsh and Mehran
                 Mozaffari-Kermani",
  title =        "Accelerated {RISC-V} for {SIKE}",
  crossref =     "IEEE:2021:ISC",
  pages =        "131--138",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00035",
  bibdate =      "Thu Sep 21 10:36:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-28",
}

@InProceedings{Elsadek:2021:RVR,
  author =       "Islam Elsadek and Eslam Yahya Tawfik",
  editor =       "{IEEE}",
  booktitle =    "{2021 19th IEEE International New Circuits and Systems
                 Conference (NEWCAS)}",
  title =        "{RISC-V} Resource-Constrained Cores: a Survey and
                 Energy Comparison",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/NEWCAS50681.2021.9462781",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Faller:2021:TSB,
  author =       "Tobias Faller and Philipp Scholl and Tobias Paxian and
                 Bernd Becker",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 22nd Latin American Test Symposium
                 (LATS)}",
  title =        "Towards {SAT}-Based {SBST} Generation for {RISC-V}
                 Cores",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--2",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/LATS53581.2021.9651819",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Forno:2021:CEN,
  author =       "Evelina Forno and Andrea Spitale and Enrico Macii and
                 Gianvito Urgese",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 14th International Symposium on Embedded
                 {Multicore\slash Many-core} Systems-on-Chip (MCSoC)}",
  title =        "Configuring an Embedded Neuromorphic Coprocessor Using
                 a {RISC-V} Chip for Enabling Edge Computing
                 Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "328--332",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/MCSoC51149.2021.00055",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gao:2021:EEF,
  author =       "Dapeng Gao and Tom Melham",
  editor =       "{IEEE}",
  booktitle =    "{2021 Formal Methods in Computer Aided Design
                 (FMCAD)}",
  title =        "End-to-End Formal Verification of a {RISC-V} Processor
                 Extended with Capability Pointers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "24--33",
  year =         "2021",
  DOI =          "https://doi.org/10.34727/2021/isbn.978-3-85448-046-4_10",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Garofalo:2021:XEEa,
  author =       "Angelo Garofalo and Giuseppe Tagliavini and Francesco
                 Conti and Luca Benini and Davide Rossi",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 28th Symposium on Computer Arithmetic
                 (ARITH)}",
  title =        "{XpulpNN}: Enabling Energy Efficient and Flexible
                 Inference of Quantized Neural Networks on {RISC-V}
                 based {IoT} End Nodes",
  crossref =     "IEEE:2021:ISC",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "53--53",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021.00020",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  note =         "See \cite{Garofalo:2021:XEEb}.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-28",
  remark =       "Published in IEEE Transactions on Emerging Topics in
                 Computing, Volume: 9, Issue: 3, July--September 2021,
                 and orally presented at ARITH 2021.",
}

@Article{Garofalo:2021:XEEb,
  author =       "Angelo Garofalo and Giuseppe Tagliavini and Francesco
                 Conti and Luca Benini and Davide Rossi",
  title =        "{XpulpNN}: Enabling Energy Efficient and Flexible
                 Inference of Quantized Neural Networks on {RISC-V}
                 Based {IoT} End Nodes",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "9",
  number =       "3",
  pages =        "1489--1505",
  month =        jul # "\slash " # sep,
  year =         "2021",
  DOI =          "https://doi.org/10.1109/TETC.2021.3072337",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  note =         "See \cite{Garofalo:2021:XEEb}.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}

@InProceedings{Gaurav:2021:DIL,
  author =       "Tanya Gaurav and Amit Bhatt and Rutu Parekh",
  editor =       "{IEEE}",
  booktitle =    "{2021 Second International Conference on Electronics
                 and Sustainable Communication Systems (ICESC)}",
  title =        "Design and implementation of low power {RISC V ISA}
                 based coprocessor design for matrix multiplication",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "189--195",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICESC51422.2021.9532933",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gholizadehazari:2021:FIR,
  author =       "Erfan Gholizadehazari and Tuba Ayhan and Berna Ors",
  editor =       "{IEEE}",
  booktitle =    "{2021 29th Signal Processing and Communications
                 Applications Conference (SIU)}",
  title =        "An {FPGA} Implementation of a {RISC-V} Based {SoC}
                 System for Image Processing Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/SIU53274.2021.9477998",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gonzalez-Gomez:2021:TGA,
  author =       "Jeferson Gonz{\'a}lez-G{\'o}mez and Steven
                 {\'A}vila-Ard{\'o}n and Jonathan Rojas-Gonz{\'a}lez and
                 Andres Stephen-Cantillano and Jorge Castro-God{\'\i}nez
                 and Carlos Salazar-Garc{\'\i}a and Muhammad Shafique
                 and J{\"o}rg Henkel",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 12th Latin America Symposium on Circuits
                 and System (LASCAS)}",
  title =        "{TailoredCore}: Generating Application-Specific
                 {RISC-V}-based Cores",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/LASCAS51355.2021.9459152",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gonzalez:2021:GWH,
  author =       "Abraham Gonzalez and Jerry Zhao and Ben Korpan and
                 Hasan Genc and Colin Schmidt and John Wright and Ayan
                 Biswas and Alon Amid and Farhana Sheikh and Anton
                 Sorokin and Sirisha Kale and Mani Yalamanchi and Ramya
                 Yarlagadda and Mark Flannigan and Larry Abramowitz and
                 Elad Alon and Yakun Sophia Shao and Krste Asanovi{\'c}
                 and Borivoje Nikoli{\'c}",
  editor =       "{IEEE}",
  booktitle =    "{ESSCIRC 2021 --- IEEE 47th European Solid State
                 Circuits Conference (ESSCIRC)}",
  title =        "A 16mm2 106.1 {GOPS\slash W} Heterogeneous {RISC-V}
                 Multi-Core Multi-Accelerator {SoC} in Low-Power 22nm
                 {FinFET}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "259--262",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ESSCIRC53450.2021.9567768",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Goud:2021:GAD,
  author =       "B. Mahesh Goud and Dilip Lilaramani and Mahendra
                 Swain",
  editor =       "{IEEE}",
  booktitle =    "{2021 International Conference on Computational
                 Performance Evaluation (ComPE)}",
  title =        "Generation and Authentication of Digital Certificates
                 using {Ethereum} based Decentralized Mechanism for
                 Mitigating Data Fraud on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "905--909",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ComPE53109.2021.9752130",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/bitcoin.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Green:2021:TTI,
  author =       "Brad Green and Dillon Todd and Jon C. Calhoun and
                 Melissa C. Smith",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Conference on Cluster
                 Computing (CLUSTER)}",
  title =        "{TIGRA}: a Tightly Integrated Generic {RISC-V}
                 Accelerator Interface",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "779--782",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/Cluster48925.2021.00115",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gruin:2021:SET,
  author =       "Alban Gruin and Thomas Carle and Hugues Cass{\'e} and
                 Christine Rochange",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE Real-Time Systems Symposium (RTSS)}",
  title =        "Speculative Execution and Timing Predictability in an
                 Open Source {RISC-V} Core",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "393--404",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/RTSS52674.2021.00043",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Harris:2021:DDR,
  author =       "Sarah L. Harris and David Harris",
  editor =       "{IEEE}",
  booktitle =    "{2021 {ACM\slash IEEE} Workshop on Computer
                 Architecture Education (WCAE)}",
  title =        "Digital Design and {RISC-V} Computer Architecture
                 Textbook",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/WCAE53984.2021.9707615",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Harris:2021:MIR,
  author =       "Austin Harris and Tarunesh Verma and Shijia Wei and
                 Lauren Biernacki and Alex Kisil and Misiker Tadesse Aga
                 and Valeria Bertacco and Baris Kasikci and Mohit Tiwari
                 and Todd Austin",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Symposium on Hardware
                 Oriented Security and Trust (HOST)}",
  title =        "{Morpheus II}: a {RISC-V} Security Extension for
                 Protecting Vulnerable Software and Hardware",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "226--238",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/HOST49136.2021.9702275",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Harris:2021:RUR,
  author =       "Sarah L. Harris and Daniel Chaver and Luis Pi{\~n}uel
                 and J. I. Gomez-Perez and M. Hamza Liaqat and Zubair L.
                 Kakakhel and Olof Kindgren and Robert Owen",
  editor =       "{IEEE}",
  booktitle =    "{2021 31st International Conference on
                 Field-Programmable Logic and Applications (FPL)}",
  title =        "{RVfpga}: Using a {RISC-V} Core Targeted to an {FPGA}
                 in Computer Architecture Education",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "145--150",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/FPL53798.2021.00032",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Herdt:2021:MBC,
  author =       "Vladimir Herdt and S{\"o}ren Tempel and Daniel
                 Gro{\ss}e and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2021 26th Asia and South Pacific Design Automation
                 Conference (ASP-DAC)}",
  title =        "Mutation-based Compliance Testing for {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "55--60",
  year =         "2021",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Hesham:2021:DAI,
  author =       "Sarah Hesham and Mohamed Shalan and M. Watheq
                 El-Kharashi and Mohamed Dessouky",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Midwest Symposium on Circuits
                 and Systems (MWSCAS)}",
  title =        "Digital {ASIC} Implementation of {RISC-V}: {OpenLane}
                 and Commercial Approaches in Comparison",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "498--502",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/MWSCAS47672.2021.9531753",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ho:2021:IDC,
  author =       "Van-Ninh Ho and Khai-Minh Ma and Hong-Hai Thai and
                 Duc-Hung Le",
  editor =       "{IEEE}",
  booktitle =    "{2021 International Conference on Advanced
                 Technologies for Communications (ATC)}",
  title =        "Implementation of a Dual-core 64-bit {RISC-V} on 7nm
                 {FinFET} Process",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "28--32",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ATC52653.2021.9598283",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Misc{Horne:2021:RQ,
  author =       "Mitchell Horne",
  title =        "{riscv\slash QEMU}",
  howpublished = "Web site",
  day =          "8",
  month =        jun,
  year =         "2021",
  bibdate =      "Fri Dec 23 12:03:37 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  note =         "See also \cite{Horne:2020:GSF}.",
  URL =          "https://wiki.freebsd.org/riscv/QEMU",
  acknowledgement = ack-nhfb,
}

@Misc{Horne:2021:S,
  author =       "Mitchell Horne",
  title =        "Spike",
  howpublished = "Web site",
  day =          "8",
  month =        jun,
  year =         "2021",
  bibdate =      "Fri Dec 23 12:03:37 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://wiki.freebsd.org/riscv/Spike",
  abstract =     "Spike is the canonical RISC-V ISA simulator. It
                 supports several ISA extensions, including some that
                 are not yet ratified. See the README on GitHub for more
                 information.",
  acknowledgement = ack-nhfb,
}

@InProceedings{Hu:2021:AIS,
  author =       "Bowen Hu and Yun Chen and Xiaoyang Zeng",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 4th International Conference on Electronics
                 Technology (ICET)}",
  title =        "An Agile Instruction Set Extension Method Based on the
                 {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "342--346",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICET51757.2021.9450911",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Hung:2021:EEP,
  author =       "Yi-Wen Hung and Yao-Tse Chang and Shuenn-Yuh Lee and
                 Chou-Ching Lin and Gia-Shing Shieh",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Conference on Consumer
                 Electronics --- Taiwan (ICCE-TW)}",
  title =        "An Energy-efficient and Programmable {RISC-V CNN}
                 Coprocessor for Real-time Epilepsy Detection and
                 Identification on Wearable Devices",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--2",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICCE-TW52618.2021.9602978",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Hussein:2021:AFG,
  author =       "Abdelrahman S. Hussein and Hassan Mostafa",
  editor =       "{IEEE}",
  booktitle =    "{2021 3rd Novel Intelligent and Leading Emerging
                 Sciences Conference (NILES)}",
  title =        "{ASIC-FPGA} Gap for a {RISC-V} Core Implementation for
                 {DNN} Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "385--388",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/NILES53778.2021.9600503",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Im:2021:CAB,
  author =       "Jaekyung Im and Seokhyeong Kang",
  editor =       "{IEEE}",
  booktitle =    "{2021 18th International SoC Design Conference
                 (ISOCC)}",
  title =        "Comparative Analysis between {Verilog} and {Chisel} in
                 {RISC-V} Core Design and Verification",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "59--60",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISOCC53507.2021.9614007",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Islam:2021:ERS,
  author =       "Md Ashraful Islam and Kenji Kise",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 14th International Symposium on Embedded
                 {Multicore\slash Many-core} Systems-on-Chip (MCSoC)}",
  title =        "Efficient Resource Shared {RISC-V} Multicore
                 Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "366--372",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/MCSoC51149.2021.00061",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Jang:2021:DMP,
  author =       "Hyeonguk Jang and Kyuseung Han and Sukho Lee and
                 Jae-Jin Lee and Seung-Yeong Lee and Jae-Hyoung Lee and
                 Woojoo Lee",
  title =        "Developing a Multicore Platform Utilizing Open
                 {RISC-V} Cores",
  journal =      j-IEEE-ACCESS,
  volume =       "9",
  number =       "",
  pages =        "120010--120023",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ACCESS.2021.3108475",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Jiao:2021:RVR,
  author =       "Qiang Jiao and Wei Hu and Fang Liu and Yong Dong",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Conference on Systems, Man,
                 and Cybernetics (SMC)}",
  title =        "{RISC-VTF}: {RISC-V} Based Extended Instruction Set
                 for {Transformer}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1565--1570",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/SMC52423.2021.9658643",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{K:2021:CAD,
  author =       "Shalini K and Abhishek Kumar Srivastava and Surendra
                 Allam and Dilip Lilaramani",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE Mysore Sub Section International Conference
                 (MysuruCon)}",
  title =        "Comparative analysis on Deep Convolution Neural
                 Network models using {Pytorch} and {OpenCV DNN}
                 frameworks for identifying optimum fruit detection
                 solution on {RISC-V} architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "738--743",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/MysuruCon52639.2021.9641594",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/python.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kanamori:2021:ROR,
  author =       "Takuto Kanamori and Kenji Kise",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 14th International Symposium on Embedded
                 {Multicore\slash Many-core} Systems-on-Chip (MCSoC)}",
  title =        "{RVCoreP-32IC}: an optimized {RISC-V} soft processor
                 supporting the compressed instructions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "38--45",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/MCSoC51149.2021.00014",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kanase:2021:ADB,
  author =       "Gopal Kanase and Nithin M",
  editor =       "{IEEE}",
  booktitle =    "{2021 6th International Conference on Communication
                 and Electronics Systems (ICCES)}",
  title =        "{ASIC} Design of a 32-bit Low Power {RISC-V} based
                 System Core for Medical Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICCES51350.2021.9489067",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kazemi:2021:DVA,
  author =       "Zahra Kazemi and Amin Norollah and Afef Kchaou and
                 Mahdi Fazeli and David Hely and Vincent Beroulle",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "An In-Depth Vulnerability Analysis of {RISC-V}
                 Micro-Architecture Against Fault Injection Attack",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/DFT52944.2021.9568318",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Koca:2021:MLP,
  author =       "Nazim Altar Koca and Berkay Yildiz and Yusuf Caner
                 Demirkol and Berna {\"O}rs",
  editor =       "{IEEE}",
  booktitle =    "{2021 13th International Conference on Electrical and
                 Electronics Engineering (ELECO)}",
  title =        "Multi-Layer Perceptron Hardware Accelerator on
                 {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "465--469",
  year =         "2021",
  DOI =          "https://doi.org/10.23919/ELECO54474.2021.9677758",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lai:2021:IBR,
  author =       "Jin-Yang Lai and Chiung-An Chen and Shih-Lun Chen and
                 Chun-Yu Su",
  editor =       "{IEEE}",
  booktitle =    "{2021 International Symposium on Intelligent Signal
                 Processing and Communication Systems (ISPACS)}",
  title =        "Implement 32-bit {RISC-V} Architecture Processor using
                 {Verilog HDL}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--2",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISPACS51563.2021.9651130",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lamberti:2021:LPL,
  author =       "Lorenzo Lamberti and Manuele Rusci and Marco Fariselli
                 and Francesco Paci and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Low-Power License Plate Detection and Recognition on a
                 {RISC-V} Multi-Core {MCU}-Based Vision System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISCAS51556.2021.9401730",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Le:2021:RTC,
  author =       "Anh-Tien Le and Trong-Thuc Hoang and Ba-Anh Dao and
                 Akira Tsukamoto and Kuniyasu Suzaki and Cong-Kha Pham",
  title =        "A Real-Time Cache Side-Channel Attack Detection System
                 on {RISC-V} Out-of-Order Processor",
  journal =      j-IEEE-ACCESS,
  volume =       "9",
  number =       "",
  pages =        "164597--164612",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ACCESS.2021.3134256",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Lee:2021:MCS,
  author =       "Wooyoung Lee and Jina Park and Changjun Byun and
                 Eunjin Choi and Jae-Hyoung Lee and Woojoo Lee and Kyung
                 Jin Byun and Kyuseung Han",
  editor =       "{IEEE}",
  booktitle =    "{2021 18th International SoC Design Conference
                 (ISOCC)}",
  title =        "{$K$}-means Clustering-specific Lightweight {RISC-V}
                 processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "391--392",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISOCC53507.2021.9613863",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Lee:2021:RVC,
  author =       "Shuenn-Yuh Lee and Yi-Wen Hung and Yao-Tse Chang and
                 Chou-Ching Lin and Gia-Shing Shieh",
  title =        "{RISC-V CNN} Coprocessor for Real-Time Epilepsy
                 Detection in Wearable Application",
  journal =      "IEEE Transactions on Biomedical Circuits and Systems",
  volume =       "15",
  number =       "4",
  pages =        "679--691",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/TBCAS.2021.3092744",
  ISSN =         "1932-4545 (print), 1940-9990 (electronic)",
  ISSN-L =       "1932-4545",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Li:2021:LPA,
  author =       "Zhiyu Li and Yuhao Huang and Longfeng Tian and Ruimin
                 Zhu and Shanlin Xiao and Zhiyi Yu",
  title =        "A Low-Power Asynchronous {RISC-V} Processor With
                 Propagated Timing Constraints Method",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "68",
  number =       "9",
  pages =        "3153--3157",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/TCSII.2021.3100524",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
}

@InProceedings{Ling:2021:OSF,
  author =       "Xiaoyi Ling and Takahiro Notsu and Jason Anderson",
  editor =       "{IEEE}",
  booktitle =    "{2021 24th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "An Open-Source Framework for the Generation of
                 {RISC-V} Processor + {CGRA} Accelerator Systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "35--42",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/DSD53832.2021.00015",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Liu:2021:WPR,
  author =       "Meng Liu",
  editor =       "{IEEE}",
  booktitle =    "{2021 International Conference on {Hardware\slash
                 Software} Codesign and System Synthesis (CODES+ISSS)}",
  title =        "Work-in-Progress: The {RISC-V} Instruction Set
                 Architecture Optimization and Fixed-point Math Library
                 Co-design",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "23--24",
  year =         "2021",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lu:2021:DAI,
  author =       "Yuan Lu and Yangmeng Liu and Yongbo Liao and Yuting
                 Liu and Lu Xu",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 4th International Conference on Electronics
                 Technology (ICET)}",
  title =        "Design of Adjacent Interconnect Processor Based on
                 {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "427--431",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICET51757.2021.9451102",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lu:2021:ESD,
  author =       "Tao Lu",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Conference on Networking,
                 Architecture and Storage (NAS)}",
  title =        "Exploring Storage Device Characteristics of a {RISC-V}
                 little-core {SoC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/NAS51552.2021.9605430",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Lu:2021:SRV,
  author =       "T. Lu",
  title =        "A survey on {RISC-V} security: Hardware and
                 architecture",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "30",
  day =          "9",
  month =        jul,
  year =         "2021",
  DOI =          "https://doi.org/10.48550/arXiv.2107.04175",
  bibdate =      "Tue Dec 19 07:47:28 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://arxiv.org/abs/2107.04175",
  abstract =     "The Internet of Things (IoT) is an ongoing
                 technological revolution. Embedded processors are the
                 processing engines of smart IoT devices. For decades,
                 these processors were mainly based on the Arm
                 instruction set architecture (ISA). In recent years,
                 the free and open RISC-V ISA standard has attracted the
                 attention of industry and academia and is becoming the
                 mainstream. Data security and user privacy protection
                 are common challenges faced by all IoT devices. In
                 order to deal with foreseeable security threats, the
                 RISC-V community is studying security solutions aimed
                 at achieving a root of trust (RoT) and ensuring that
                 sensitive information on RISC-V devices is not tampered
                 with or leaked. Many RISC-V security research projects
                 are underway, but the academic community has not yet
                 conducted a comprehensive survey of RISC-V security
                 solutions. In order to fill this research gap, this
                 paper presents an in-depth survey on RISC-V security
                 technologies. This paper summarizes the representative
                 security mechanisms of RISC-V hardware and
                 architecture. Based on our survey, we predict the
                 future research and development directions of RISC-V
                 security. We hope that our research can inspire RISC-V
                 researchers and developers.",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ma:2021:CRV,
  author =       "Jun Ma and Ting Chong and Lei Li and Hao Liu and Xige
                 Zhang and Liang Liu and Yidong Yuan",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Conference on Power,
                 Intelligent Computing and Systems (ICPICS)}",
  title =        "Construction of {RISC-V} Lightweight Trusted Execution
                 Environment Based on Hardware Extension",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "237--242",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICPICS52425.2021.9524261",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Mao:2021:CEB,
  author =       "Binjie Mao and Nianxiong Tan and Ting Chong and Lei
                 Li",
  editor =       "{IEEE}",
  booktitle =    "{2021 6th International Conference on Integrated
                 Circuits and Microsystems (ICICM)}",
  title =        "A {CLIC} Extension Based Fast Interrupt System for
                 Embedded {RISC-V} Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "109--113",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICICM54364.2021.9660345",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Marshall:2021:LIC,
  author =       "Ben Marshall and Daniel Page and Thinh Hung Pham",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 32nd International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP)}",
  title =        "A lightweight {ISE} for {ChaCha} on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "25--32",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ASAP52443.2021.00011",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Matsuno:2021:RWE,
  author =       "Shota Matsuno and Masashi Tawada and Nozomu Togawa",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Conference on Consumer
                 Electronics (ICCE)}",
  title =        "Reducing Writing Energy Consumption for Non-Volatile
                 Registers Utilizing Frequent Patterns of Sequential
                 Bits on {RISC-V} Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICCE50685.2021.9427727",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Merchant:2021:AFB,
  author =       "Farhad Merchant and Dominik Sisejkovic and Lennart M.
                 Reimann and Kirthihan Yasotharan and Thomas Grass and
                 Rainer Leupers",
  editor =       "{IEEE}",
  booktitle =    "{2021 34th International Conference on VLSI Design and
                 2021 20th International Conference on Embedded Systems
                 (VLSID)}",
  title =        "{ANDROMEDA}: an {FPGA} Based {RISC-V MPSoC}
                 Exploration Framework",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "270--275",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/VLSID51830.2021.00051",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Molina-Robles:2021:APS,
  author =       "Roberto Molina-Robles and Ronny
                 Garc{\'\i}a-Ram{\'\i}rez and Alfonso
                 Chac{\'o}n-Rodr{\'\i}guez and Renato Rimolo-Donadio and
                 Alfredo Arnaud",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE Latin America Electron Devices Conference
                 (LAEDC)}",
  title =        "An affordable post-silicon testing framework applied
                 to a {RISC-V} based microcontroller",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/LAEDC51812.2021.9437939",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Molina-Robles:2021:LLA,
  author =       "Roberto Molina-Robles and Ronny
                 Garc{\'\i}a-Ram{\'\i}rez and Alfonso
                 Chac{\'o}n-Rodr{\'\i}guez and Renato Rimolo-Donadio and
                 Alfredo Arnaud",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE URUCON}",
  title =        "Low-level algorithm for a software-emulated {I$^2$C
                 I/O} module in general purpose {RISC-V} based
                 microcontrollers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "90--94",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/URUCON53396.2021.9647309",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Mueller:2021:RVB,
  author =       "Kai-Uwe Mueller and Alexander Stanitzki and Tatjana
                 Fedtschenko and Rainer Kokozinski",
  editor =       "{IEEE}",
  booktitle =    "{MikroSystemTechnik Congress 2021; Congress}",
  title =        "{RISC-V} based {SoC} with integrated
                 switched-capacitor {PUF} in 180 nm",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--3",
  year =         "2021",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Nannipieri:2021:RVP,
  author =       "Pietro Nannipieri and Stefano {Di Matteo} and Luca
                 Zulberti and Francesco Albicocchi and Sergio Saponara
                 and Luca Fanucci",
  title =        "A {RISC-V} Post Quantum Cryptography Instruction Set
                 Extension for Number Theoretic Transform to Speed-Up
                 {CRYSTALS} Algorithms",
  journal =      j-IEEE-ACCESS,
  volume =       "9",
  number =       "",
  pages =        "150798--150808",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ACCESS.2021.3126208",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Nguyen:2021:CBT,
  author =       "Khai-Duy Nguyen and Dang Tuan Kiet and Trong-Thuc
                 Hoang and Nguyen Quang Nhu Quynh and Cong-Kha Pham",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE Hot Chips 33 Symposium (HCS)}",
  title =        "A {CORDIC}-based Trigonometric Hardware Accelerator
                 with Custom Instruction in 32-bit {RISC-V}
                 {System-on-Chip}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--13",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/HCS52781.2021.9567158",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Papaphilippou:2021:DCS,
  author =       "Philippos Papaphilippou and Paul H. J. Kelly and Wayne
                 Luk",
  editor =       "{IEEE}",
  booktitle =    "{2021 31st International Conference on
                 Field-Programmable Logic and Applications (FPL)}",
  title =        "Demonstrating custom {SIMD} instruction development
                 for a {RISC-V} softcore",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "139--139",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/FPL53798.2021.00030",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Papaphilippou:2021:SRV,
  author =       "Philippos Papaphilippou and Kelly Paul H. J. and Wayne
                 Luk",
  editor =       "{IEEE}",
  booktitle =    "{2021 31st International Conference on
                 Field-Programmable Logic and Applications (FPL)}",
  title =        "{Simodense}: a {RISC-V} softcore optimised for
                 exploring custom {SIMD} instructions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "391--397",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/FPL53798.2021.00082",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Paulin:2021:RBR,
  author =       "Gianna Paulin and Renzo Andri and Francesco Conti and
                 Luca Benini",
  title =        "{RNN}-Based Radio Resource Management on Multicore
                 {RISC-V} Accelerator Architectures",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "29",
  number =       "9",
  pages =        "1624--1637",
  year =         "2021",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2021.3093242",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}

@InProceedings{Perez:2021:COS,
  author =       "Boria Perez and Alexander Fell and John D. Davis",
  editor =       "{IEEE}",
  booktitle =    "{2021 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "{Coyote}: an Open Source Simulation Tool to Enable
                 {RISC-V} in {HPC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "130--135",
  year =         "2021",
  DOI =          "https://doi.org/10.23919/DATE51398.2021.9474080",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Pircher:2021:ERV,
  author =       "S. Pircher and J. Geier and A. Zeh and D.
                 Mueller-Gritschneder",
  editor =       "{IEEE}",
  booktitle =    "{2021 22nd International Symposium on Quality
                 Electronic Design (ISQED)}",
  title =        "Exploring the {RISC-V} Vector Extension for the
                 Classic {McEliece} Post-Quantum Cryptosystem",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "401--407",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISQED51717.2021.9424273",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Poli:2021:DIR,
  author =       "Ludovico Poli and Sangeet Saha and Xiaojun Zhai and
                 Klaus D. Mcdonald-Maier",
  editor =       "{IEEE}",
  booktitle =    "{2021 17th International Conference on Mobility,
                 Sensing and Networking (MSN)}",
  title =        "Design and Implementation of a {RISC V} Processor on
                 {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "161--166",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/MSN53354.2021.00037",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Qin:2021:CHA,
  author =       "Xinyu Qin and Xudong Liu and Jun Han",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 14th International Conference on ASIC
                 (ASICON)}",
  title =        "A {CNN} Hardware Accelerator Designed for {YOLO}
                 Algorithm Based on {RISC-V SoC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ASICON52560.2021.9620500",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Qiu:2021:AVP,
  author =       "Jing Qiu and Fei Ye and Hua Zhou",
  editor =       "{IEEE}",
  booktitle =    "{2021 International Conference on Networking Systems
                 of AI (INSAI)}",
  title =        "Automatic Verification Platform Based on {RISC-V}
                 Architecture Microprocessor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "157--160",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/INSAI54028.2021.00037",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Rajabalipanah:2021:ARV,
  author =       "Maryam Rajabalipanah and Mahboobe Sadeghipour Roodsari
                 and Zahra Jahanpeima and Gianluca Roascio and Paolo
                 Prinetto and Zainalabedin Navabi",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE East--West Design \& Test Symposium
                 (EWDTS)}",
  title =        "{AFTAB}: a {RISC-V} Implementation with Configurable
                 Gateways for Security",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/EWDTS52692.2021.9580979",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Rajagopal:2021:EQE,
  author =       "S. Rajagopal",
  editor =       "{IEEE}",
  booktitle =    "Proceedings of the {IEEE Hot Chips 33 Symposium (HCS),
                 August 2021}",
  title =        "{EDGE Q 5G} with an {EDGE}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--13.",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/HCS52781.2021.9567324",
  bibdate =      "Tue Dec 19 07:46:00 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Reichenbach:2021:RVR,
  author =       "Marc Reichenbach and Johannes Kn{\"o}dtel and
                 Sebastian Rachuj and Dietmar Fey",
  title =        "{RISC-V3}: a {RISC-V} Compatible {CPU} With a Data
                 Path Based on Redundant Number Systems",
  journal =      j-IEEE-ACCESS,
  volume =       "9",
  number =       "",
  pages =        "43684--43700",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ACCESS.2021.3063238",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Richter:2021:RVB,
  author =       "Mike Richter and Andre Luedecke and Yoon-Cue Lee and
                 Alexander Stanitzki and Alexander Utz and Guenter Grau
                 and Holger Kappert and Rainer Kokozinski",
  editor =       "{IEEE}",
  booktitle =    "{SMACD \slash PRIME 2021; International Conference on
                 SMACD and 16th Conference on PRIME}",
  title =        "A {RISC-V}-based System on Chip for High-Speed Control
                 in Safety-Critical 650 {V GaN-Applications}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2021",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Riedel:2021:BFL,
  author =       "Samuel Riedel and Fabian Schuiki and Paul Scheffler
                 and Florian Zaruba and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2021 {IEEE\slash ACM} International Conference On
                 Computer Aided Design (ICCAD)}",
  title =        "{Banshee}: a Fast {LLVM}-Based {RISC-V} Binary
                 Translator",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--9",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICCAD51958.2021.9643546",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Riese:2021:MTP,
  author =       "Frank Riese and Vladimir Herdt and Daniel Gro{\ss}e
                 and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2021 IFIP\slash IEEE 29th International Conference on
                 Very Large Scale Integration (VLSI-SoC)}",
  title =        "Metamorphic Testing for Processor Verification: a
                 {RISC-V} Case Study at the Instruction Level",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/VLSI-SoC53125.2021.9606997",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{RK:2021:VBP,
  author =       "Risikesh RK and Sharad Sinha and Nanditha Rao",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 14th International Symposium on Embedded
                 {Multicore\slash Many-core} Systems-on-Chip (MCSoC)}",
  title =        "Variable Bit-Precision Vector Extension for {RISC-V}
                 Based Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "114--121",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/MCSoC51149.2021.00024",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Rojas:2021:LCB,
  author =       "Camilo Rojas and Hanssel Morales and Elkim Roa",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "A Low-Cost Bug Hunting Verification Methodology for
                 {RISC-V}-Based Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISCAS51556.2021.9401510",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Santos:2021:CRV,
  author =       "Douglas A. Santos and Lucas M. Luza and Maria
                 Kastriotou and Carlo Cazzaniga and Cesar A. Zeferino
                 and Douglas R. Melo and Luigi Dilillo",
  editor =       "{IEEE}",
  booktitle =    "{2021 16th International Conference on Design \&
                 Technology of Integrated Systems in Nanoscale Era
                 (DTIS)}",
  title =        "Characterization of a {RISC-V System-on-Chip} under
                 Neutron Radiation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/DTIS53253.2021.9505054",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Savas:2021:GHS,
  author =       "S{\"u}leyman Savas and Endri Bezati and J{\"o}rn W.
                 Janneck",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 34th International System-on-Chip
                 Conference (SOCC)}",
  title =        "Generating hardware and software for {RISC-V} cores
                 generated with {Rocket Chip} generator",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "89--94",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/SOCC52499.2021.9739411",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Schiavone:2021:AEA,
  author =       "Pasquale Davide Schiavone and Davide Rossi and Alfio
                 {Di Mauro} and Frank K. G{\"u}rkaynak and Timothy Saxe
                 and Mao Wang and Ket Chong Yap and Luca Benini",
  title =        "{Arnold}: an {eFPGA}-Augmented {RISC-V SoC} for
                 Flexible and Low-Power {IoT} End Nodes",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "29",
  number =       "4",
  pages =        "677--690",
  year =         "2021",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2021.3058162",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}

@InProceedings{Schmidt:2021:ECR,
  author =       "Colin Schmidt and John Wright and Zhongkai Wang and
                 Eric Chang and Albert Ou and Woorham Bae and Sean Huang
                 and Anita Flynn and Brian Richards and Krste
                 Asanovi{\'c} and Elad Alon and Borivoje Nikoli{\'c}",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Solid-State Circuits
                 Conference (ISSCC)}",
  title =        "4.3 An Eight-Core {1.44GHz RISC-V} Vector Machine in
                 16nm {FinFET}",
  volume =       "64",
  number =       "",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "58--60",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISSCC42613.2021.9365789",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Schuiki:2021:SSR,
  author =       "Fabian Schuiki and Florian Zaruba and Torsten Hoefler
                 and Luca Benini",
  title =        "Stream Semantic Registers: a Lightweight {RISC-V ISA}
                 Extension Achieving Full Compute Utilization in
                 Single-Issue Cores",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "70",
  number =       "2",
  pages =        "212--227",
  month =        feb,
  year =         "2021",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2020.2987314",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}

@InProceedings{Serrano:2021:LPL,
  author =       "Ronaldo Serrano and Marco Sarmiento and Ckristian
                 Duran and Khai-Duy Nguyen and Trong-Thuc Hoang and
                 Koichiro Ishibashi and Cong-Kha Pham",
  editor =       "{IEEE}",
  booktitle =    "{2021 18th International SoC Design Conference
                 (ISOCC)}",
  title =        "A Low-Power Low-Area {SoC} based in {RISC-V} Processor
                 for {IoT} Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "375--376",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISOCC53507.2021.9613880",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Sewell:2021:EFS,
  author =       "Peter Sewell",
  editor =       "{IEEE}",
  booktitle =    "{2021 Formal Methods in Computer Aided Design
                 (FMCAD)}",
  title =        "Engineering with Full-scale Formal Architecture:
                 {Morello}, {CHERI}, {Armv8-A}, and {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "12--12",
  year =         "2021",
  DOI =          "https://doi.org/10.34727/2021/isbn.978-3-85448-046-4_7",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Shepherd:2021:LVL,
  author =       "Carlton Shepherd and Konstantinos Markantonakis and
                 Georges-Axel Jaloyan",
  editor =       "{IEEE}",
  booktitle =    "{2021 {\booktitle{IEEE Security and Privacy}}
                 Workshops (SPW)}",
  title =        "{LIRA-V}: Lightweight Remote Attestation for
                 Constrained {RISC-V} Devices",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "221--227",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/SPW53761.2021.00036",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Sordillo:2021:CVA,
  author =       "Stefano Sordillo and Abdallah Cheikh and Antonio
                 Mastrandrea and Francesco Menichelli and Mauro
                 Olivieri",
  title =        "Customizable vector acceleration in extreme-edge
                 computing: a {RISC-V} software\slash hardware
                 architecture study on {VGG-16} implementation",
  journal =      j-ELECTRONICS,
  volume =       "10",
  number =       "4",
  pages =        "518--538",
  month =        feb,
  year =         "2021",
  DOI =          "https://doi.org/10.3390/electronics10040518",
  ISSN =         "2079-9292",
  ISSN-L =       "2079-9292",
  bibdate =      "Tue Dec 19 07:52:17 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronics",
  journal-URL =  "https://www.mdpi.com/journal/electronics",
}

@InProceedings{Srivastava:2021:OSS,
  author =       "Abhishek Kumar Srivastava and Kirana CS and Dilip
                 Lilaramani and Rakshitha R and Kavya Sree",
  editor =       "{IEEE}",
  booktitle =    "{2021 2nd International Conference on Communication,
                 Computing and Industry 4.0 (C2I4)}",
  title =        "An open-source {SWUpdate} and {Hawkbit} framework for
                 {OTA} Updates of {RISC-V} based resource constrained
                 devices",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/C2I454156.2021.9689433",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Stapf:2021:HWT,
  author =       "Emmanuel Stapf and Patrick Jauernig and Ferdinand
                 Brasser and Ahmad-Reza Sadeghi",
  editor =       "{IEEE}",
  booktitle =    "{2021 IFIP\slash IEEE 29th International Conference on
                 Very Large Scale Integration (VLSI-SoC)}",
  title =        "In Hardware We Trust? {From TPM} to Enclave Computing
                 on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/VLSI-SoC53125.2021.9606968",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Su:2021:FAD,
  author =       "Charlie Hong-Men Su",
  editor =       "{IEEE}",
  booktitle =    "{2021 International Symposium on VLSI Design,
                 Automation and Test (VLSI-DAT)}",
  title =        "Flexible Acceleration of Data Processing with {RISC-V
                 DSP}, Vector and Custom Extensions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "i--i",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/VLSI-DAT52063.2021.9427339",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Sun:2021:LPB,
  author =       "Mingjian Sun and Yuan Li and Song Chen and Yi Kang",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 32nd International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP)}",
  title =        "A Low Power Branch Prediction for Deep Learning on
                 {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "203--206",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ASAP52443.2021.00037",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Suvorova:2021:ADR,
  author =       "E. A. Suvorova",
  editor =       "{IEEE}",
  booktitle =    "{2021 Wave Electronics and its Application in
                 Information and Telecommunication Systems (WECONF)}",
  title =        "An Approach for Development of {RISC-V} Based
                 Transport Layer Controller",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--9",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/WECONF51603.2021.9470646",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Suvorova:2021:RVB,
  author =       "Elena Suvorova",
  editor =       "{IEEE}",
  booktitle =    "{2021 29th Conference of Open Innovations Association
                 (FRUCT)}",
  title =        "{RISC V} Based Reconfigurable Manager for Event
                 Transmission in {SpaceFibre} Networks",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "356--365",
  year =         "2021",
  DOI =          "https://doi.org/10.23919/FRUCT52173.2021.9435599",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Suzaki:2021:TPG,
  author =       "Kuniyasu Suzaki and Kenta Nakajima and Tsukasa Oi and
                 Akira Tsukamoto",
  title =        "{TS-Perf}: General Performance Measurement of Trusted
                 Execution Environment and Rich Execution Environment on
                 {Intel SGX}, {Arm TrustZone}, and {RISC-V Keystone}",
  journal =      j-IEEE-ACCESS,
  volume =       "9",
  number =       "",
  pages =        "133520--133530",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ACCESS.2021.3112202",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Swain:2021:DNS,
  author =       "Mahendra Swain and Dilip Lilaramani and G. Mahesh and
                 A. K. Srivastva",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 2nd International Conference on Applied
                 Electromagnetics, Signal Processing, \& Communication
                 (AESPC)}",
  title =        "A Decentralized Network to Secure Smart Grid
                 Transactions Using {Ethereum} on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/AESPC52704.2021.9708533",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/bitcoin.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Szkandera:2021:BYO,
  author =       "Filip Szkandera",
  title =        "Build Your Own {RISC-V CPU}: Even Home-Brew Processors
                 Can use Hot New Tech",
  journal =      j-IEEE-SPECTRUM,
  volume =       "58",
  number =       "6",
  pages =        "16--18",
  month =        jun,
  year =         "2021",
  CODEN =        "IEESAM",
  DOI =          "https://doi.org/10.1109/MSPEC.2021.9444942",
  ISSN =         "0018-9235 (print), 1939-9340 (electronic)",
  ISSN-L =       "0018-9235",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeespectrum2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Spectrum",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6",
}

@InProceedings{Talaki:2021:EDV,
  author =       "E. Bertrand Talaki and Mathieu {Bouvier Des Noes} and
                 Olivier Savry and David Hely and Simone Bacles-Min and
                 Romain Lemaire",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE Physical Assurance and Inspection of
                 Electronics (PAINE)}",
  title =        "Exposing Data Value On a {RISC-V} Based {SoC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/PAINE54418.2021.9707710",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Tan:2021:POS,
  author =       "Zhangxi Tan and Lin Zhang and David Patterson and Yi
                 Li",
  title =        "{PicoRio}: an open-source, {RISC-V} small-board
                 computer to elevate the {RISC-V} software ecosystem",
  journal =      "Tsinghua Science and Technology",
  volume =       "26",
  number =       "3",
  pages =        "384--386",
  year =         "2021",
  CODEN =        "TSTEF7",
  DOI =          "https://doi.org/10.26599/TST.2020.9010037",
  ISSN =         "1007-0214 (print), 1878-7606 (electronic)",
  ISSN-L =       "1007-0214",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tang:2021:CPT,
  author =       "Junlong Tang and Jun Zhang and Qiang Song and Shenbo
                 Liu and Zhiwen Yu and Wanghui Zou",
  editor =       "{IEEE}",
  booktitle =    "{2021 9th International Symposium on Next Generation
                 Electronics (ISNE)}",
  title =        "The Compilation Performance Tests and Analysis of
                 {RISC-V} Compilation Toolchain On the {SPEC CPU{\reg}
                 2017}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ISNE48910.2021.9493648",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tehrani:2021:RPP,
  author =       "Etienne Tehrani and Tarik Graba and Abdelmalek Si
                 Merabet and Jean-Luc Danger",
  editor =       "{IEEE}",
  booktitle =    "{2021 24th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "{RSM} Protection of the {PRESENT} Lightweight Cipher
                 as a {RISC-V} Extension",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "325--332",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/DSD53832.2021.00056",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Thomet:2021:FFR,
  author =       "S{\'e}bastien Thomet and Serge De-Paoli and Jean-Marc
                 Daveau and Val{\'e}rie Bertin and Fady Abouzeid and
                 Philippe Roche and Fakhreddine Ghaffari and Olivier
                 Romain",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "{FIRECAP}: Fail-Reason Capturing hardware module for a
                 {RISC-V} based System on a Chip",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/DFT52944.2021.9568317",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Tine:2021:VERa,
  author =       "Blaise Tine and Fares Elsabbagh and Krishna Yalamarthy
                 and Hyesoon Kim",
  title =        "{Vortex}: Extending the {RISC-V ISA} for {GPGPU} and
                 {3D}-Graphics Research",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--13",
  day =          "21",
  month =        oct,
  year =         "2021",
  DOI =          "https://doi.org/10.48550/arXiv.2110.10857",
  bibdate =      "Tue Dec 19 09:23:08 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://arxiv.org/abs/2110.10857",
  abstract =     "The importance of open-source hardware and software
                 has been increasing. However, despite GPUs being one of
                 the more popular accelerators across various
                 applications, there is very little open-source GPU
                 infrastructure in the public domain. We argue that one
                 of the reasons for the lack of open-source
                 infrastructure for GPUs is rooted in the complexity of
                 their ISA and software this http URL this work, we
                 first propose an ISA extension to RISC-V that supports
                 GPGPUs and graphics. The main goal of the ISA extension
                 proposal is to minimize the ISA changes so that the
                 corresponding changes to the open-source ecosystem are
                 also minimal, which makes for a sustainable development
                 ecosystem. To demonstrate the feasibility of the
                 minimally extended RISC-V ISA, we implemented the
                 complete software and hardware stacks of Vortex on
                 FPGA. Vortex is a PCIe-based soft GPU that supports
                 OpenCL and OpenGL. Vortex can be used in a variety of
                 applications, including machine learning, graph
                 analytics, and graphics rendering. Vortex can scale up
                 to 32 cores on an Altera Stratix 10 FPGA, delivering a
                 peak performance of 25.6 GFlops at 200 Mhz",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tine:2021:VERb,
  author =       "Blaise Tine and Krishna P. Yalamarthy and Fares
                 Elsabbagh and Hyesoon Kim",
  editor =       "ACM",
  booktitle =    "{MICRO '21: The 54th Annual IEEE\slash ACM
                 International Symposium on Microarchitecture
                 Proceedings. October 18--22, 2021, Virtual from Athens,
                 Greece}",
  title =        "{Vortex}: Extending the {RISC-V ISA} for {GPGPU} and
                 {3D}-graphics",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "754--766",
  year =         "2021",
  DOI =          "https://doi.org/10.1145/3466752.3480128",
  ISBN =         "1-4503-8557-5",
  ISBN-13 =      "978-1-4503-8557-2",
  bibdate =      "Tue Dec 19 08:26:06 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  abstract =     "The importance of open-source hardware and software
                 has been increasing. However, despite GPUs being one of
                 the more popular accelerators across various
                 applications, there is very little open-source GPU
                 infrastructure in the public domain. We argue that one
                 of the reasons for the lack of open-source
                 infrastructure for GPUs is rooted in the complexity of
                 their ISA and software stacks. In this work, we first
                 propose an ISA extension to RISC-V that supports GPGPUs
                 and graphics. The main goal of the ISA extension
                 proposal is to minimize the ISA changes so that the
                 corresponding changes to the open-source ecosystem are
                 also minimal, which makes for a sustainable development
                 ecosystem. To demonstrate the feasibility of the
                 minimally extended RISC-V ISA, we implemented the
                 complete software and hardware stacks of Vortex on
                 FPGA. Vortex is a PCIe-based soft GPU that supports
                 OpenCL and OpenGL. Vortex can be used in a variety of
                 applications, including machine learning, graph
                 analytics, and graphics rendering. Vortex can scale up
                 to 32 cores on an Altera Stratix 10 FPGA, delivering a
                 peak performance of 25.6 GFlops at 200 Mhz.",
  acknowledgement = ack-nhfb,
}

@Article{Tiwari:2021:PCP,
  author =       "Sugandha Tiwari and Neel Gala and Chester Rebeiro and
                 V. Kamakoti",
  title =        "{PERI}: a Configurable Posit Enabled {RISC-V} Core",
  journal =      j-TACO,
  volume =       "18",
  number =       "3",
  pages =        "25:1--25:26",
  month =        jun,
  year =         "2021",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3446210",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Tue Jun 29 08:21:11 MDT 2021",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3446210",
  abstract =     "Owing to the failure of Dennard's scaling, the past
                 decade has seen a steep growth of prominent new
                 paradigms leveraging opportunities in computer
                 architecture. Two technologies of interest are Posit
                 and RISC-V. Posit was introduced in mid-2017 as a
                 \ldots{}",
  acknowledgement = ack-nhfb,
  articleno =    "25",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "https://dl.acm.org/loi/taco",
}

@InProceedings{Tourres:2021:ERV,
  author =       "Ma{\"e}l Tourres and Cyrille Chavet and Bertrand {Le
                 Gal} and J{\'e}r{\'e}mie Crenne and Philippe Coussy",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 4th 5G World Forum (5GWF)}",
  title =        "Extended {RISC-V} hardware architecture for future
                 digital communication systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "224--229",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/5GWF52925.2021.00046",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tran:2021:RVR,
  author =       "Dai Duong Tran and Thi Giang Truong and Truong Giang
                 Do and The Duc Do",
  editor =       "{IEEE}",
  booktitle =    "{2021 15th International Conference on Advanced
                 Computing and Applications (ACOMP)}",
  title =        "{RISC-V} Random Test Generator",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "150--155",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ACOMP53746.2021.00027",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wang:2021:CIR,
  author =       "Shihang Wang and Jianghan Zhu and Qi Wang and Can He
                 and Terry Tao Ye",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 32nd International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP)}",
  title =        "Customized Instruction on {RISC-V} for
                 {Winograd}-Based Convolution Acceleration",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "65--68",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ASAP52443.2021.00018",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wang:2021:XGA,
  author =       "Xi Wang and John D. Leidel and Brody Williams and Alan
                 Ehret and Miguel Mark and Michel A. Kinsy and Yong
                 Chen",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Parallel and Distributed
                 Processing Symposium (IPDPS)}",
  title =        "{xBGAS}: a Global Address Space Extension on {RISC-V}
                 for High Performance Computing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "454--463",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/IPDPS49936.2021.00054",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Watanabe:2021:IWG,
  author =       "Rei Watanabe and Jubee Tada and Keiichi Sato",
  editor =       "{IEEE}",
  booktitle =    "{2021 Ninth International Symposium on Computing and
                 Networking Workshops (CANDARW)}",
  title =        "An Implementation of a World Grid Square Codes
                 Generator on a {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "309--312",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/CANDARW53999.2021.00059",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Book{Waterman:2021:RVIa,
  author =       "Andrew Waterman and Krste Asanovi{\'c}",
  title =        "The {RISC-V} Instruction Set Manual. {Volume I}:
                 Unprivileged {ISA}",
  publisher =    "RISC-V International",
  address =      "????",
  pages =        "xvi + 220",
  year =         "2021",
  bibdate =      "Mon Dec 18 14:01:43 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  note =         "Document Version 20211213.",
  URL =          "https://drive.google.com/file/d/1s0lZxUZaa7eV_O0_WsZzaurFLLww7ou5/view",
  acknowledgement = ack-nhfb,
}

@Book{Waterman:2021:RVIb,
  author =       "Andrew Waterman and Krste Asanovi{\'c} and John
                 Hauser",
  title =        "The {RISC-V} Instruction Set Manual. {Volume II}:
                 Privileged Architecture",
  publisher =    "RISC-V International",
  address =      "????",
  pages =        "xii + 141",
  day =          "4",
  month =        dec,
  year =         "2021",
  bibdate =      "Mon Dec 18 13:56:16 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  note =         "Document Version 20211203.",
  URL =          "https://drive.google.com/file/d/1EMip5dZlnypTk7pt4WWUKmtjUKTOkBqh/view",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wei:2021:SIC,
  author =       "Mengmeng Wei and Guoqiang Yang and Fanyu Kong",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE International Conference on Information
                 Communication and Software Engineering (ICICSE)}",
  title =        "Software Implementation and Comparison of {ZUC-256},
                 {SNOW-V}, and {AES-256} on {RISC-V} Platform",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "56--60",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ICICSE52190.2021.9404134",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wessman:2021:RFR,
  author =       "Nils-Johan Wessman and Fabio Malatesta and Jan
                 Andersson and Paco Gomez and Miguel Masmano and Vicente
                 Nicolau and Jimmy {Le Rhun} and Guillem Cabo and
                 Francisco Bas and Ruben Lorenzo and Oriol Sala and
                 David Trilla and Jaume Abella",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE Space Computing Conference (SCC)}",
  title =        "{De-RISC}: the First {RISC-V} Space-Grade Platform for
                 Safety-Critical Systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "17--26",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/SCC49971.2021.00010",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wilson:2021:FIT,
  author =       "Andrew E. Wilson and Michael Wirthlin",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE Space Computing Conference (SCC)}",
  title =        "Fault Injection of {TMR} Open Source {RISC-V}
                 Processors using Dynamic Partial Reconfiguration on
                 {SRAM}-based {FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/SCC49971.2021.00008",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wistoff:2021:MTC,
  author =       "Nils Wistoff and Moritz Schneider and Frank K.
                 G{\"u}rkaynak and Luca Benini and Gernot Heiser",
  editor =       "{IEEE}",
  booktitle =    "{2021 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Microarchitectural Timing Channels and their
                 Prevention on an Open-Source 64-bit {RISC-V} Core",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "627--632",
  year =         "2021",
  DOI =          "https://doi.org/10.23919/DATE51398.2021.9474214",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Yang:2021:ATF,
  author =       "Dun-An Yang and Jing-Jia Liou and Harry H. Chen",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 30th Asian Test Symposium (ATS)}",
  title =        "Analyzing Transient Faults and Functional Error Rates
                 of a {RISC-V} Core: a Case Study",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "133--138",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ATS52891.2021.00035",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Yildiz:2021:CAR,
  author =       "Recep Onur Y{\i}ld{\i}z and Ayse Yilmazer-Metin",
  editor =       "{IEEE}",
  booktitle =    "{2021 29th Telecommunications Forum (TELFOR)}",
  title =        "{CORDIC} Accelerator for {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/TELFOR52709.2021.9653439",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Yilmaz:2021:DIB,
  author =       "Yasin Y{\i}lmaz and Yavuz Selim Tozlu and Berna
                 {\"O}rs",
  editor =       "{IEEE}",
  booktitle =    "{2021 13th International Conference on Electrical and
                 Electronics Engineering (ELECO)}",
  title =        "Design and Implementation of a 32-bit {RISC-V} Core",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "460--464",
  year =         "2021",
  DOI =          "https://doi.org/10.23919/ELECO54474.2021.9677678",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Zaruba:2021:MCR,
  author =       "Florian Zaruba and Fabian Schuiki and Luca Benini",
  title =        "{Manticore}: a 4096-Core {RISC-V} Chiplet Architecture
                 for Ultraefficient Floating-Point Computing",
  journal =      j-IEEE-MICRO,
  volume =       "41",
  number =       "2",
  pages =        "36--42",
  month =        mar # "\slash " # apr,
  year =         "2021",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2020.3045564",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
}

@InProceedings{Zekany:2021:TOP,
  author =       "Stephen A. Zekany and Jielun Tan and James A.
                 Connolly",
  editor =       "{IEEE}",
  booktitle =    "{2021 {ACM\slash IEEE} Workshop on Computer
                 Architecture Education (WCAE)}",
  title =        "Teaching Out-of-Order Processor Design with the
                 {RISC-V ISA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/WCAE53984.2021.9707143",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zgheib:2021:ERV,
  author =       "Anthony Zgheib and Olivier Potin and Jean-Baptiste
                 Rigaud and Jean-Max Dutertre",
  editor =       "{IEEE}",
  booktitle =    "{SMACD \slash PRIME 2021; International Conference on
                 SMACD and 16th Conference on PRIME}",
  title =        "Extending a {RISC-V} core with an {AES} hardware
                 accelerator to meet {IOT} constraints",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2021",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhang:2021:ARV,
  author =       "Yunrui Zhang and Zichao Guo and Jian Li and Fan Cai
                 and Jianyang Zhou",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 15th International Conference on
                 Anti-counterfeiting, Security, and Identification
                 (ASID)}",
  title =        "{AnnikaCore}: {RISC-V} Architecture Processor Design
                 and Implementation for {IoT}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "200--203",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ASID52932.2021.9651690",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhang:2021:CAE,
  author =       "Li Zhang and Xian Zhou and Chuliang Guo",
  editor =       "{IEEE}",
  booktitle =    "{2021 China Semiconductor Technology International
                 Conference (CSTIC)}",
  title =        "A {CNN} Accelerator with Embedded {RISC-V}
                 Controllers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--3",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/CSTIC52283.2021.9461576",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhang:2021:DVT,
  author =       "Wendi Zhang and Yonghui Zhang and Kun Zhao",
  editor =       "{IEEE}",
  booktitle =    "{2021 5th Asian Conference on Artificial Intelligence
                 Technology (ACAIT)}",
  title =        "Design and Verification of Three-stage Pipeline {CPU}
                 Based on {RISC-V} Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "697--703",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ACAIT53529.2021.9731161",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zheng:2021:DIA,
  author =       "Zhenhong Zheng and Xiangyu Zhu and Hui Qian",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 5th Advanced Information Technology,
                 Electronic and Automation Control Conference (IAEAC)}",
  title =        "Design and Implementation of Arbitrary Point {FFT}
                 Based on {RISC-V SoC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1216--1219",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/IAEAC50856.2021.9390787",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhong:2021:HIR,
  author =       "Xinchao Zhong and Chiu-Wing Sham and Longyu Ma",
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 10th Global Conference on Consumer
                 Electronics (GCCE)}",
  title =        "A Highly Integrated {RISC-V} Based {SoC} for On-Board
                 Unit in {ETC} System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "302--303",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/GCCE53005.2021.9622039",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zulberti:2021:SBC,
  author =       "Luca Zulberti and Pietro Nannipieri and Luca Fanucci",
  editor =       "{IEEE}",
  booktitle =    "{2021 16th International Conference on Design \&
                 Technology of Integrated Systems in Nanoscale Era
                 (DTIS)}",
  title =        "A Script-Based Cycle-True Verification Framework to
                 Speed-Up Hardware and Software Co-Design of
                 {System-on-Chip} exploiting {RISC-V} Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/DTIS53253.2021.9505139",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Adit:2022:PLT,
  author =       "Neil Adit and Adrian Sampson",
  title =        "Performance Left on the Table: an Evaluation of
                 Compiler Autovectorization for {RISC-V}",
  journal =      j-IEEE-MICRO,
  volume =       "42",
  number =       "5",
  pages =        "41--48",
  month =        sep # "\slash " # oct,
  year =         "2022",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2022.3184867",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
}

@InProceedings{Ahmadi-Pour:2022:TMS,
  author =       "Sallar Ahmadi-Pour and Sangeet Saha and Vladimir Herdt
                 and Rolf Drechsler and Klaus McDonald-Maier",
  editor =       "{IEEE}",
  booktitle =    "{2022 25th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "Task Mapping and Scheduling in {FPGA}-based
                 Heterogeneous Real-time Systems: a {RISC-V}
                 Case-Study",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "134--141",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DSD57027.2022.00027",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Alder:2022:FPU,
  author =       "Fritz Alder and Jo {Van Bulck} and Jesse Spielman and
                 David Oswald and Frank Piessens",
  title =        "Faulty Point Unit: {ABI} Poisoning Attacks on Trusted
                 Execution Environments",
  journal =      j-DTRAP,
  volume =       "3",
  number =       "2",
  pages =        "13:1--13:26",
  month =        jun,
  year =         "2022",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3491264",
  ISSN =         "2692-1626 (print), 2576-5337 (electronic)",
  ISSN-L =       "2576-5337",
  bibdate =      "Sat Jul 30 07:34:14 MDT 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/dtrap.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3491264",
  abstract =     "This article analyzes a previously overlooked attack
                 surface that allows unprivileged adversaries to impact
                 floating-point computations in enclaves through the
                 Application Binary Interface (ABI). In a comprehensive
                 study across 7 industry-standard and esearch enclave
                 shielding runtimes for Intel Software Guard Extensions
                 (SGX), we show that control and state registers of the
                 x87 Floating-Point Unit (FPU) and Intel Streaming SIMD
                 Extensions are not always properly sanitized on enclave
                 entry. We furthermore show that this attack goes beyond
                 the x86 architecture and can also affect RISC-V
                 enclaves. Focusing on SGX, we abuse the adversary's
                 control over precision and rounding modes as an ABI
                 fault injection primitive to corrupt enclaved
                 floating-point operations. Our analysis reveals that
                 this is especially relevant for applications that use
                 the older x87 FPU, which is still under certain
                 conditions used by modern compilers. We exemplify the
                 potential impact of ABI quality-degradation attacks for
                 enclaved machine learning and for the SPEC benchmarks.
                 We then explore the impact on confidentiality, showing
                 that control over exception masks can be abused as a
                 controlled channel to recover enclaved multiplication
                 operands. Our findings, affecting 5 of 7 studied SGX
                 runtimes and one RISC-V runtime, demonstrate the
                 challenges of implementing high-assurance trusted
                 execution across computing architectures.",
  acknowledgement = ack-nhfb,
  articleno =    "13",
  fjournal =     "Digital Threats: Research and Practice (DTRAP)",
  journal-URL =  "https://dl.acm.org/loi/dtrap",
}

@Article{Amor:2022:RVI,
  author =       "Hela Belhadj Amor and Carolynn Bernier and
                 Zden{\v{e}}k P{\v{r}}ikryl",
  title =        "A {RISC-V ISA} Extension for Ultra-Low Power {IoT}
                 Wireless Signal Processing",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "71",
  number =       "4",
  pages =        "766--778",
  month =        apr,
  year =         "2022",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2021.3063027",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}

@InProceedings{Annink:2022:PSE,
  author =       "Edian B. Annink and Gerard Rauwerda and Edwin
                 Hakkennes and Alessandra Menicucci and Stefano {Di
                 Mascio} and Gianluca Furano and Marco Ottavi",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "Preventing Soft Errors and Hardware Trojans in
                 {RISC-V} Cores",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DFT56152.2022.9962340",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Anonymous:2022:TRV,
  author =       "Anonymous",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Conference on IC Design and
                 Technology (ICICDT)}",
  title =        "Tutorial \#1: {RISC-V} Computer System Designed for
                 Cyber-Security",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "xxxi--xxxi",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICICDT56182.2022.9933100",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Antonov:2022:SOR,
  author =       "Alexander Antonov",
  editor =       "{IEEE}",
  booktitle =    "{2022 11th Mediterranean Conference on Embedded
                 Computing (MECO)}",
  title =        "Superscalar Out-of-Order {RISC-V ASIP} Based on
                 Programmable Hardware Generator with Decoupled
                 Computations and Flow Control",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/MECO55406.2022.9797182",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{B:2022:MMT,
  author =       "Karunatharaka B and Sakshi Kamal and Sharvani G S",
  editor =       "{IEEE}",
  booktitle =    "{2022 4th International Conference on Advances in
                 Computing, Communication Control and Networking
                 (ICAC3N)}",
  title =        "Minimal Multi-tasking Operating System for {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2267--2270",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICAC3N56670.2022.10073988",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Bartolini:2022:MCP,
  author =       "Andrea Bartolini and Federico Ficarelli and Emanuele
                 Parisi and Francesco Beneventi and Francesco Barchi and
                 Daniele Gregori and Fabrizio Magugliani and Marco
                 Cicala and Cosimo Gianfreda and Daniele Cesarini and
                 Andrea Acquaviva and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 35th International System-on-Chip
                 Conference (SOCC)}",
  title =        "{Monte Cimone}: Paving the Road for the First
                 Generation of {RISC-V} High-Performance Computers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/SOCC56010.2022.9908096",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Bertaccini:2022:MNE,
  author =       "Luca Bertaccini and Gianna Paulin and Tim Fischer and
                 Stefan Mach and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 29th Symposium on Computer Arithmetic
                 (ARITH)}",
  title =        "{MiniFloat-NN} and {ExSdotp}: an {ISA} Extension and a
                 Modular Open Hardware Unit for Low-Precision Training
                 on {RISC-V} Cores",
  crossref =     "IEEE:2022:ISC",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ARITH54963.2022.00010",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-29",
}

@InProceedings{Boseler:2022:CVP,
  author =       "Felix B{\"o}seler and J{\"o}rg Walter and Behnam Razi
                 Perjikolaei",
  editor =       "{IEEE}",
  booktitle =    "{2022 Forum on Specification \& Design Languages
                 (FDL)}",
  title =        "A Comparison of Virtual Platform Simulation Solutions
                 for Timing Prediction of Small {RISC-V} Based {SoCs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/FDL56239.2022.9925667",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Cabo:2022:DRV,
  author =       "Guillem Cabo and Gerard Cand{\'o}n and Xavier Carril
                 and Max Doblas and Marc Dom{\'\i}nguez and Alberto
                 Gonz{\'a}lez and C{\'e}sar Hern{\'a}ndez and
                 V{\'\i}ctor Jim{\'e}nez and Vatistas Kostalampros and
                 Rub{\'e}n Langarita and Nei{\'e}l Leyva and Guillem
                 L{\'o}pez-Parad{\'\i}s and Jonnatan Mendoza and
                 Francesco Minervini and Juli{\'a}n Pav{\'o}n and
                 Crist{\'o}bal Ram{\'\i}rez and Narc{\'\i}s Rodas and
                 Enrico Reggiani and Mario Rodr{\'\i}guez and Carlos
                 Rojas and Abraham Ruiz and V{\'\i}ctor Soria and
                 Alejandro Suanes and Iv{\'a}n Vargas and Roger Figueras
                 and Pau Fontova and Joan Marimon and V{\'\i}ctor
                 Montabes and Adri{\'a}n Cristal and Carles
                 Hern{\'a}ndez and Ricardo Mart{\'\i}nez and Miquel
                 Moret{\'o} and Francesc Moll and Oscar Palomar and
                 Marco A. Ram{\'\i}rez and Antonio Rubio and Jordi
                 Sacrist{\'a}n and Francesc Serra-Graells and Nehir
                 Sonmez and Llu{\'\i}s Ter{\'e}s and Osman Unsal and
                 Mateo Valero and Lu{\'\i}s Villa",
  editor =       "{IEEE}",
  booktitle =    "{2022 37th Conference on Design of Circuits and
                 Integrated Circuits (DCIS)}",
  title =        "{DVINO}: a {RISC-V} Vector Processor Implemented in
                 65nm Technology",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DCIS55711.2022.9970128",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Cai:2022:RPT,
  author =       "Boyang Cai and Shaobin Xie and Quanyi Liang and
                 Wanying Lu",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Symposium on Advances in
                 Informatics, Electronics and Education (ISAIEE)}",
  title =        "Research on Penetration Testing of {IoT} Gateway Based
                 on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "422--425",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISAIEE57420.2022.00093",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Cassano:2022:RVR,
  author =       "Luca Cassano and Stefano {Di Mascio} and Alessandro
                 Palumbo and Alessandra Menicucci and Gianluca Furano
                 and Giuseppe Bianchi and Marco Ottavi",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "Is {RISC-V} ready for Space? {A} Security
                 Perspective",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DFT56152.2022.9962352",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Chander:2022:SRV,
  author =       "V. Naveen Chander and Kuruvilla Varghese",
  editor =       "{IEEE}",
  booktitle =    "{2022 35th International Conference on VLSI Design and
                 2022 21st International Conference on Embedded Systems
                 (VLSID)}",
  title =        "A Soft {RISC-V} Vector Processor for {Edge-AI}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "263--268",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/VLSID2022.2022.00058",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Chen:2022:CRV,
  author =       "Gregory K. Chen and Phil C. Knag and Carlos Tokunaga
                 and Ram K. Krishnamurthy",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE Symposium on VLSI Technology and Circuits
                 (VLSI Technology and Circuits)}",
  title =        "An 8-core {RISC-V} Processor with Compute near Last
                 Level Cache in {Intel 4 CMOS}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "68--69",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830518",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Chen:2022:DUL,
  author =       "Jiahao Chen and Dingji Li and Zeyu Mi and Yuxuan Liu
                 and Binyu Zang and Haibing Guan and Haibo Chen",
  title =        "{DuVisor}: A user-level hypervisor through delegated
                 virtualization,",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--17",
  day =          "22",
  month =        jan,
  year =         "2022",
  DOI =          "https://doi.org/10.48550/arXiv.2201.09652",
  bibdate =      "Tue Dec 19 08:16:51 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/virtual-machines.bib",
  URL =          "https://arxiv.org/abs/2201.09652",
  abstract =     "Today's mainstream virtualization systems comprise of
                 two cooperative components: a kernel-resident driver
                 that accesses virtualization hardware and a user-level
                 helper process that provides VM management and I/O
                 virtualization. However, this virtualization
                 architecture has intrinsic issues in both security (a
                 large attack surface) and performance. While there is a
                 long thread of work trying to minimize the
                 kernel-resident driver by offloading functions to user
                 mode, they face a fundamental tradeoff between security
                 and performance: more offloading may reduce the kernel
                 attack surface, yet increase the runtime ring crossings
                 between the helper process and the driver, and thus
                 more performance cost.\par This paper explores a new
                 design called delegated virtualization, which
                 completely separates the control plane (the kernel
                 driver) from the data plane (the helper process) and
                 thus eliminates the kernel driver from runtime
                 intervention. The resulting user-level hypervisor,
                 called DuVisor, can handle all VM operations without
                 trapping into the kernel once the kernel driver has
                 done the initialization. DuVisor retrofits existing
                 hardware virtualization support with a new delegated
                 virtualization extension to directly handle VM exits,
                 configure virtualization registers, manage the stage-2
                 page table and virtual devices in user mode. We have
                 implemented the hardware extension on an open-source
                 RISC-V CPU and built a Rust-based hypervisor atop the
                 hardware. Evaluation on FireSim shows that DuVisor
                 outperforms KVM by up to 47.96\% in a variety of
                 real-world applications and significantly reduces the
                 attack surface.",
  acknowledgement = ack-nhfb,
}

@InProceedings{Chen:2022:RVS,
  author =       "Chen Chen and Qimin Yuan and Xiaowen Jiang and Kai
                 Huang and Peng Li and Wei Xi",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 6th Conference on Energy Internet and
                 Energy System Integration (EI2)}",
  title =        "A {RISC-V System-on-Chip} Based on Dual-core Isolation
                 for Smart Grid Security",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1278--1283",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/EI256261.2022.10116661",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Choudhury:2022:ORV,
  author =       "Ananya Choudhury and Saroja V. Siddamal and Jayashree
                 Mallidue",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Conference on Distributed
                 Computing, VLSI, Electrical Circuits and Robotics
                 (DISCOVER)}",
  title =        "An optimized {RISC-V} processor with five stage
                 pipelining using {Tournament Branch Predictor} for
                 efficient performance",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "57--60",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DISCOVER55800.2022.9974891",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Cococcioni:2022:LPP,
  author =       "Marco Cococcioni and Federico Rossi and Emanuele
                 Ruffaldi and Sergio Saponara",
  title =        "A Lightweight Posit Processing Unit for {RISC-V}
                 Processors in Deep Neural Network Applications",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "10",
  number =       "4",
  pages =        "1898--1908",
  month =        oct # "\slash " # dec,
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TETC.2021.3120538",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}

@InProceedings{Cosimi:2022:AHS,
  author =       "Francesco Cosimi and Fabrizio Tronci and Sergio
                 Saponara and Paolo Gai",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Conference on Smart Computing
                 (SMARTCOMP)}",
  title =        "Analysis, Hardware Specification and Design of a
                 Programmable Performance Monitoring Unit {(PPMU)} for
                 {RISC-V ECUs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "213--218",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/SMARTCOMP55677.2022.00056",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{De:2022:HSU,
  author =       "Asmit De and Swaroop Ghosh",
  editor =       "{IEEE}",
  booktitle =    "{2022 35th International Conference on VLSI Design and
                 2022 21st International Conference on Embedded Systems
                 (VLSID)}",
  title =        "{HeapSafe}: Securing Unprotected Heaps in {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "120--125",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/VLSID2022.2022.00034",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Deng:2022:DSH,
  author =       "Junyong Deng and Zekun Ye and Kai Zhou and Xiaoliang
                 Fu and Baoxiang Zhang and Xiaoyan Xie",
  editor =       "{IEEE}",
  booktitle =    "{2022 7th International Conference on Integrated
                 Circuits and Microsystems (ICICM)}",
  title =        "Design of Software--Hardware Collaborative Graph
                 Computing Accelerator Based on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "404--410",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICICM56102.2022.10011254",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Dharsni:2022:OHF,
  author =       "I Thanga Dharsni and Kirti S. Pande and Manoj Kumar
                 Panda",
  editor =       "{IEEE}",
  booktitle =    "{2022 3rd International Conference on Smart
                 Electronics and Communication (ICOSEC)}",
  title =        "Optimized Hazard Free Pipelined Architecture Block for
                 {RV32I RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "739--746",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICOSEC54921.2022.9952122",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Ditzel:2022:AMR,
  author =       "David R. Ditzel and the Esperanto team",
  title =        "Accelerating {ML} Recommendation With Over 1,000
                 {RISC-V\slash Tensor} Processors on {Esperanto}'s
                 {ET-SoC-1} Chip",
  journal =      j-IEEE-MICRO,
  volume =       "42",
  number =       "3",
  pages =        "31--38",
  month =        may # "\slash " # jun,
  year =         "2022",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2022.3140674",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
}

@InProceedings{Dorflinger:2022:FFT,
  author =       "Alexander D{\"o}rflinger and Benedikt Kleinbeck and
                 Mark Albers and Harald Michalik and Martin Moya",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE Intl Conf on Dependable, Autonomic and
                 Secure Computing, Intl Conf on Pervasive Intelligence
                 and Computing, Intl Conf on Cloud and Big Data
                 Computing, Intl Conf on Cyber Science and Technology
                 Congress {(DASC\slash PiCom\slash CBDCom\slash
                 CyberSciTech)}}",
  title =        "A Framework for Fault Tolerance in {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DASC/PiCom/CBDCom/Cy55231.2022.9927800",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ecker:2022:SRV,
  author =       "Wolfgang Ecker and Peer Adelt and Wolfgang Mueller and
                 Reinhold Heckmann and Milos Krstic and Vladimir Herdt
                 and Rolf Drechsler and Gerhard Angst and Ralf Wimmer
                 and Andreas Mauderer and Rafael Stahl and Karsten
                 Emrich and Daniel Mueller-Gritschneder and Bernd Becker
                 and Philipp Scholl and Eyck Jentzsch and Jan
                 Schlamelcher and Kim Gr{\"u}ttner and Paul Palomero
                 Bernardo and Oliver Bringmann and Mihaela Damian and
                 Julian Oppermann and Andreas Koch and J{\"o}rg Bormann
                 and Johannes Partzsch and Christian Mayr and Wolfgang
                 Kunz",
  editor =       "{IEEE}",
  booktitle =    "{2022 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "The {Scale4Edge RISC-V} Ecosystem",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "808--813",
  year =         "2022",
  DOI =          "https://doi.org/10.23919/DATE54114.2022.9774593",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Elkhatib:2022:ARV,
  author =       "Rami Elkhatib and Brian Koziel and Reza Azarderakhsh
                 and Mehran Mozaffari Kermani",
  title =        "Accelerated {RISC-V} for Post-Quantum {SIKE}",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-1,
  volume =       "69",
  number =       "6",
  pages =        "2490--2501",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TCSI.2022.3162626",
  ISSN =         "1549-8328 (print), 1558-0806 (electronic)",
  ISSN-L =       "1549-8328",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I: Regular
                 Papers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919",
}

@Article{Eni:2022:EHB,
  author =       "Yossi Eni and Shlomo Greenberg and Yehuda Ben-Shimol",
  title =        "Efficient Hint-Based Event {(EHE)} Issue Scheduling
                 for Hardware Multithreaded {RISC-V} Pipeline",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-1,
  volume =       "69",
  number =       "2",
  pages =        "735--745",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TCSI.2021.3117490",
  ISSN =         "1549-8328 (print), 1558-0806 (electronic)",
  ISSN-L =       "1549-8328",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I: Regular
                 Papers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919",
}

@Article{Feng:2022:RRV,
  author =       "Lang Feng and Jiayi Huang and Luyi Li and Haochen
                 Zhang and Zhongfeng Wang",
  title =        "{RvDfi}: a {RISC-V} Architecture With Security
                 Enforcement by High Performance Complete Data-Flow
                 Integrity",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "71",
  number =       "10",
  pages =        "2499--2512",
  month =        oct,
  year =         "2022",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2021.3133701",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}

@InProceedings{FernandesDosSantos:2022:EEN,
  author =       "Fernando {Fernandes Dos Santos} and Angeliki
                 Kritikakou and Olivier Sentieys",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 28th International Symposium on On-Line
                 Testing and Robust System Design (IOLTS)}",
  title =        "Experimental evaluation of neutron-induced errors on a
                 multicore {RISC-V} platform",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/IOLTS56730.2022.9897448",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Funck:2022:VPD,
  author =       "Milan Funck and Vladimir Herdt and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2022 25th International Symposium on Design and
                 Diagnostics of Electronic Circuits and Systems
                 (DDECS)}",
  title =        "Virtual Prototype driven Design, Implementation and
                 Evaluation of {RISC-V} Instruction Set Extensions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "14--19",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DDECS54261.2022.9770108",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Furano:2022:ERL,
  author =       "Gianluca Furano and Stefano {Di Mascio} and Alessandra
                 Menicucci and Claudio Monteleone",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE Aerospace Conference (AERO)}",
  title =        "A {European} Roadmap to Leverage {RISC-V} in Space
                 Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/AERO53065.2022.9843361",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gao:2022:RDR,
  author =       "Jie Gao and Jun Zhang",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 16th International Conference on
                 Solid-State \& Integrated Circuit Technology
                 (ICSICT)}",
  title =        "Research and Design of {RISC-V} Four-Stage
                 Out-of-Order Execution Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--3",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICSICT55466.2022.9963329",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gao:2022:TFI,
  author =       "Zhanyuan Gao and Laiping Zhao and Haonan Chen",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE\slash ACIS 22nd International Conference on
                 Computer and Information Science (ICIS)}",
  title =        "A Trigonometric Function Instruction Set Extension
                 Method Based on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "119--126",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICIS54925.2022.9882453",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Garofalo:2022:DHRa,
  author =       "Angelo Garofalo and Matteo Perotti and Luca Valente
                 and Yvan Tortorella and Alessandro Nadalini and Luca
                 Benini and Davide Rossi and Francesco Conti",
  editor =       "{IEEE}",
  booktitle =    "{ESSCIRC 2022- IEEE 48th European Solid State Circuits
                 Conference (ESSCIRC)}",
  title =        "{Darkside}: {2.6GFLOPS, 8.7mW} Heterogeneous {RISC-V}
                 Cluster for Extreme-Edge On-Chip {DNN} Inference and
                 Training",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "273--276",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ESSCIRC55480.2022.9911384",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Garofalo:2022:DHRb,
  author =       "Angelo Garofalo and Yvan Tortorella and Matteo Perotti
                 and Luca Valente and Alessandro Nadalini and Luca
                 Benini and Davide Rossi and Francesco Conti",
  title =        "{DARKSIDE}: a Heterogeneous {RISC-V} Compute Cluster
                 for Extreme-Edge On-Chip {DNN} Inference and Training",
  journal =      "IEEE Open Journal of the Solid-State Circuits
                 Society",
  volume =       "2",
  number =       "",
  pages =        "231--243",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/OJSSCS.2022.3210082",
  ISSN =         "2644-1349",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Open J. Solid-State Circuits Soc.",
}

@InProceedings{Garzon:2022:RVB,
  author =       "Esteban Garz{\'o}n and Roman Golman and Odem Harel and
                 Tzachi Noy and Yehuda Kra and Asaf Pollock and Slava
                 Yuzhaninov and Yonatan Shoshan and Yehuda Rudin and
                 Yoav Weitzman and Marco Lanuzza and Adam Teman",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "A {RISC-V}-based Research Platform for Rapid Design
                 Cycle",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2614--2615",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISCAS48785.2022.9937866",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gava:2022:SEA,
  author =       "Jonas Gava and Guilherme Dorneles and Ricardo Reis and
                 Rafael Garibotti and Luciano Ost",
  editor =       "{IEEE}",
  booktitle =    "{2022 29th IEEE International Conference on
                 Electronics, Circuits and Systems (ICECS)}",
  title =        "Soft Error Assessment of {CNN} Inference Models
                 Running on a {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICECS202256217.2022.9970958",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ge:2022:SDI,
  author =       "Zhilai Ge and Penghao Xiao and Mengxue Li and Haipeng
                 Wang",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Conference on Automation, Robotics
                 and Computer Engineering (ICARCE)}",
  title =        "{SoC} Design of Intelligent Recognition Based on
                 {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICARCE55724.2022.10046614",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gerlin:2022:DTC,
  author =       "Nicolas Gerlin and Endri Kaja and Monideep Bora and
                 Keerthikumara Devarajegowda and Dominik Stoffel and
                 Wolfgang Kunz and Wolfgang Ecker",
  editor =       "{IEEE}",
  booktitle =    "{2022 IFIP\slash IEEE 30th International Conference on
                 Very Large Scale Integration (VLSI-SoC)}",
  title =        "Design of a Tightly-Coupled {RISC-V} Physical Memory
                 Protection Unit for Online Error Detection",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/VLSI-SoC54400.2022.9939622",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gordon:2022:PKL,
  author =       "Nicholas Gordon and Kevin Pedretti and John R. Lange",
  editor =       "{IEEE}",
  booktitle =    "{2022 {IEEE\slash ACM} International Workshop on
                 Runtime and Operating Systems for Supercomputers
                 (ROSS)}",
  title =        "Porting the {Kitten} Lightweight Kernel Operating
                 System to {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ROSS56639.2022.00008",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gorius:2022:DER,
  author =       "Jean-Michel Gorius and Simon Rokicki and Steven
                 Derrien",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Conference on Field-Programmable
                 Technology (ICFPT)}",
  title =        "Design Exploration of {RISC-V} Soft-Cores through
                 Speculative High-Level Synthesis",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICFPT56656.2022.9974478",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gracia:2022:PTT,
  author =       "Dar{\'\i}o Su{\'a}rez Gracia and Alejandro Valero and
                 Rub{\'e}n Gran Tejero and Mar{\'\i}a Villarroya and
                 V{\'\i}ctor Vi{\~n}als",
  editor =       "{IEEE}",
  booktitle =    "{2022 37th Conference on Design of Circuits and
                 Integrated Circuits (DCIS)}",
  title =        "{peRISCVcope}: a Tiny Teaching-Oriented {RISC-V}
                 Interpreter",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "01--06",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DCIS55711.2022.9970050",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Hadayeghparast:2022:HSP,
  author =       "Shahriar Hadayeghparast and Siavash Bayat-Sarmadi and
                 Shahriar Ebrahimi",
  title =        "High-Speed Post-Quantum Cryptoprocessor Based on
                 {RISC-V} Architecture for {IoT}",
  journal =      "IEEE Internet of Things Journal",
  volume =       "9",
  number =       "17",
  pages =        "15839--15846",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/JIOT.2022.3152850",
  ISSN =         "2327-4662",
  ISSN-L =       "2327-4662",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Internet Things J.",
}

@Book{Harris:2022:DDC,
  author =       "Sarah Harris and David Money Harris",
  title =        "Digital Design and Computer Architecture: {RISC-V}
                 Edition",
  publisher =    "Morgan Kaufmann (Elsevier)",
  address =      "Cambridge, MA, USA",
  pages =        "xxv + 564",
  year =         "2022",
  ISBN =         "0-12-820064-2 (paperback)",
  ISBN-13 =      "978-0-12-820064-3 (paperback)",
  LCCN =         "TK7868.D5 H35 2022",
  bibdate =      "Thu Dec 28 10:22:32 MST 2023",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  abstract =     "The newest addition to the Harris and Harris family of
                 \booktitle{Digital Design and Computer Architecture}
                 books, this RISC-V Edition covers the fundamentals of
                 digital logic design and reinforces logic concepts
                 through the design of a RISC-V microprocessor.
                 Combining an engaging and humorous writing style with
                 an updated and hands-on approach to digital design,
                 this book takes the reader from the fundamentals of
                 digital logic to the actual design of a processor. By
                 the end of this book, readers will be able to build
                 their own RISC-V microprocessor and will have a
                 top-to-bottom understanding of how it works. Beginning
                 with digital logic gates and progressing to the design
                 of combinational and sequential circuits, this book
                 uses these fundamental building blocks as the basis for
                 designing a RISC-V processor. SystemVerilog and VHDL
                 are integrated throughout the text in examples
                 illustrating the methods and techniques for CAD-based
                 circuit design. The companion website includes a
                 chapter on I/O systems with practical examples that
                 show how to use the RED-V RedBoard, which has a RISC-V
                 microcontroller, to communicate with peripheral devices
                 such as LCDs, Bluetooth radios, and motors. This book
                 will be a valuable resource for students taking a
                 course that combines digital logic and computer
                 architecture or students taking a two-semester sequence
                 in digital logic and computer
                 organization/architecture.",
  acknowledgement = ack-nhfb,
  subject =      "RISC microprocessors; Digital electronics; Logic
                 design; Computer architecture; RISC (Microprocesseurs);
                 {\'E}lectronique num{\'e}rique; Structure logique;
                 Ordinateurs; Architecture; Computer architecture;
                 Digital electronics; Logic design; RISC
                 microprocessors",
  tableofcontents = "1: From Zero to One / 1 \\
                 2: Combinational Logic Design / 53 \\
                 3: Sequential Logic Design / 107 \\
                 4: Hardware Description Languages / 171 \\
                 5: Digital Building Blocks / 237 \\
                 6: Architecture / 299 \\
                 7: Microarchitecture / 393 \\
                 8: Memory Systems / 499 \\
                 9: Embedded I/O Systems / 542 [online supplement] \\
                 Appendix A. Digital System Implementation / 543 [online
                 supplement] \\
                 Appendix B. RISC-V Instruction Set Summary / 544
                 [online supplement] \\
                 Appendix C. C Programming / 545 [online supplement] \\
                 Further Reading / 547 \\
                 Index / 549",
}

@InProceedings{He:2022:DCG,
  author =       "Bin He and Ning-Mei Yu and Meng Xu and Xing-Jia Wang",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 16th International Conference on
                 Solid-State \& Integrated Circuit Technology
                 (ICSICT)}",
  title =        "Design of computing granularity configurable processor
                 based on {RISC-V} extended instruction",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--3",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICSICT55466.2022.9963166",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Hepola:2022:OCD,
  author =       "Kari Hepola and Joonas Multanen and Pekka
                 J{\"a}{\"a}skel{\"a}inen",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 33rd International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP)}",
  title =        "{OpenASIP 2.0}: Co-Design Toolset for {RISC-V}
                 Application-Specific Instruction-Set Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "161--165",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ASAP54787.2022.00034",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Hoyer:2022:DAF,
  author =       "Ingo Hoyer and Alexander Utz and Andr{\'e} L{\"u}decke
                 and Mike Richter and Felix Wichum and Pierre Gembaczka
                 and Kerstin K{\"o}hler and Maurice Rohr and Christoph
                 Hoog Antink and Karsten Seidl",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Symposium on Medical
                 Measurements and Applications (MeMeA)}",
  title =        "Detection of atrial fibrillation with an optimized
                 neural network on a {RISC-V}-based microcontroller for
                 efficient integration into {ECG} patches",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/MeMeA54994.2022.9856502",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Hu:2022:WPR,
  author =       "Xiao Hu and Yaohua Wang and Xuan Gao",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Conference on Compilers,
                 Architecture, and Synthesis for Embedded Systems
                 (CASES)}",
  title =        "Work-in-Progress: {RISC-V} Based Low-cost Embedded
                 Trace Processing System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "31--32",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/CASES55004.2022.00022",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Iuga:2022:CET,
  author =       "Nicolai Iuga and Ionel Zagan and Vasile Gheorghita
                 Gaitan",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Conference on Development and
                 Application Systems (DAS)}",
  title =        "{CPU} Execution Time Analysis based on {RISC-V ISA}
                 Simulators: a Survey",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "12--18",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DAS54948.2022.9786163",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kadomoto:2022:EDM,
  author =       "Junichiro Kadomoto and Hidetsugu Irie and Shuichi
                 Sakai",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 15th International Symposium on Embedded
                 {Multicore\slash Many-core} Systems-on-Chip (MCSoC)}",
  title =        "Evaluation of Different Microarchitectures for
                 Energy-Efficient {RISC-V} Cores",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "78--84",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/MCSoC57363.2022.00022",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Kamaleldin:2022:AAH,
  author =       "Ahmed Kamaleldin and Diana G{\"o}hringer",
  title =        "{AGILER}: an Adaptive Heterogeneous Tile-Based
                 Many-Core Architecture for {RISC-V} Processors",
  journal =      j-IEEE-ACCESS,
  volume =       "10",
  number =       "",
  pages =        "43895--43913",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ACCESS.2022.3168686",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Kamaleldin:2022:HMA,
  author =       "Ahmed Kamaleldin and Diana G{\"o}hringer",
  editor =       "{IEEE}",
  booktitle =    "{2022 32nd International Conference on
                 Field-Programmable Logic and Applications (FPL)}",
  title =        "A Hybrid Memory\slash Accelerator Tile Architecture
                 for {FPGA}-based {RISC-V} Manycore Systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "300--306",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/FPL57034.2022.00053",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Karl:2022:HAF,
  author =       "Patrick Karl and Tim Fritzmann and Georg Sigl",
  editor =       "{IEEE}",
  booktitle =    "{2022 25th International Symposium on Design and
                 Diagnostics of Electronic Circuits and Systems
                 (DDECS)}",
  title =        "Hardware Accelerated {FrodoKEM} on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "154--159",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DDECS54261.2022.9770148",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Kim:2022:OIP,
  author =       "Youngbeom Kim and Seog Chung Seo",
  title =        "Optimized Implementation of {PIPO} Block Cipher on
                 32-Bit {ARM} and {RISC-V} Processors",
  journal =      j-IEEE-ACCESS,
  volume =       "10",
  number =       "",
  pages =        "97298--97309",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ACCESS.2022.3205617",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Klemmer:2022:EPM,
  author =       "Lucas Klemmer and Daniel Gro{\ss}e",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE Computer Society Annual Symposium on VLSI
                 (ISVLSI)}",
  title =        "An Exploration Platform for Microcoded {RISC-V} Cores
                 leveraging the One Instruction Set Computer Principle",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "38--43",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISVLSI54635.2022.00020",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Knodtel:2022:SID,
  author =       "Johannes Kn{\"o}dtel and Sebastian Rachuj and Marc
                 Reichenbach",
  editor =       "{IEEE}",
  booktitle =    "{2022 25th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "Suitability of {ISAs} for Data Paths Based on
                 Redundant Number Systems: Is {RISC-V} the best?",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "247--253",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DSD57027.2022.00041",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kong:2022:HPR,
  author =       "Xinjie Kong and Weiliang He and Jun Han",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 16th International Conference on
                 Solid-State \& Integrated Circuit Technology
                 (ICSICT)}",
  title =        "A high-performance {RISC-V} co-processor architecture
                 for fast {IP} processing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--3",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICSICT55466.2022.9963438",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Koranek:2022:IRO,
  author =       "Daniel F. Koranek and Scott R. Graham and Brett J.
                 Borghetti and Wayne C. Henry",
  title =        "Identification of Return-Oriented Programming Attacks
                 Using {RISC-V} Instruction Trace Data",
  journal =      j-IEEE-ACCESS,
  volume =       "10",
  number =       "",
  pages =        "45347--45364",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ACCESS.2022.3170479",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Kovacevic:2022:RVV,
  author =       "Nikola Kova{\v{c}}evi{\'c} and {\Dbar}or{\dbar}e
                 Mi{\v{s}}elji{\'c} and Aleksa Stojkovi{\'c}",
  editor =       "{IEEE}",
  booktitle =    "{2022 30th Telecommunications Forum (TELFOR)}",
  title =        "{RISC-V} vector processor for acceleration of machine
                 learning algorithms",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TELFOR56187.2022.9983779",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kuang:2022:HSN,
  author =       "Honglin Kuang and Yifan Zhao and Jun Han",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE Asia Pacific Conference on Circuits and
                 Systems (APCCAS)}",
  title =        "A High-Speed {NTT}-Based Polynomial Multiplication
                 Accelerator with Vector Extension of {RISC-V} for
                 {Saber} Algorithm",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "592--595",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/APCCAS55924.2022.10090293",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kuhne:2022:POF,
  author =       "Jonas K{\"u}hne and Michele Magno and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Parallelizing Optical Flow Estimation on an Ultra-Low
                 Power {RISC-V} Cluster for {Nano-UAV} Navigation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "301--305",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISCAS48785.2022.9937215",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Kukner:2022:RVP,
  author =       "Halil K{\"u}kner and G{\"o}khan Kaplayan and Ahmet Efe
                 and Mehmet Ali G{\"u}lden",
  editor =       "{IEEE}",
  booktitle =    "{2022 IFIP\slash IEEE 30th International Conference on
                 Very Large Scale Integration (VLSI-SoC)}",
  title =        "{RISC-V} Processor Trace Encoder with Multiple
                 Instructions Retirement Support",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/VLSI-SoC54400.2022.9939596",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Kwon:2022:OIS,
  author =       "Hyeokdong Kwon and Hyunjun Kim and Siwoo Eum and
                 Minjoo Sim and Hyunji Kim and Wai-Kong Lee and Zhi Hu
                 and Hwajeong Seo",
  title =        "Optimized Implementation of {SM4} on {AVR}
                 Microcontrollers, {RISC-V} Processors, and {ARM}
                 Processors",
  journal =      j-IEEE-ACCESS,
  volume =       "10",
  number =       "",
  pages =        "80225--80233",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ACCESS.2022.3195217",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Le:2022:SAD,
  author =       "Anh-Tien Le and Trong-Thuc Hoang and Ba-Anh Dao and
                 Akira Tsukamoto and Kuniyasu Suzaki and Cong-Kha Pham",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "{Spectre} attack detection with Neutral Network on
                 {RISC-V} processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2467--2471",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISCAS48785.2022.9937212",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Book{Ledin:2022:MCA,
  author =       "Jim Ledin and Dave Farley",
  title =        "Modern Computer Architecture and Organization: Learn
                 x86, {ARM}, and {RISC-V} architectures and the design
                 of smartphones, {PCs}, and cloud servers",
  publisher =    "Packt Publishing",
  address =      "Birmingham, UK",
  edition =      "Second",
  pages =        "xxxvi + 628",
  year =         "2022",
  ISBN =         "1-80323-451-2 (paperback), 1-80323-823-2 (e-book)",
  ISBN-13 =      "978-1-80323-451-9 (paperback), 978-1-80323-823-4
                 (e-book)",
  LCCN =         "QA76.9.A73 L43 2022",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  abstract =     "Are you a software developer, systems designer, or
                 computer architecture student looking for a methodical
                 introduction to digital device architectures, but are
                 overwhelmed by the complexity of modern systems? This
                 step-by-step guide will teach you how modern computer
                 systems work with the help of practical examples and
                 exercises. You'll gain insights into the internal
                 behavior of processors down to the circuit level and
                 will understand how the hardware executes code
                 developed in high-level languages. This book will teach
                 you the fundamentals of computer systems including
                 transistors, logic gates, sequential logic, and
                 instruction pipelines. You will learn details of modern
                 processor architectures and instruction sets including
                 x86, x64, ARM, and RISC-V. You will see how to
                 implement a RISC-V processor in a low-cost FPGA board
                 and write a quantum computing program and run it on an
                 actual quantum computer. This edition has been updated
                 to cover the architecture and design principles
                 underlying the important domains of cybersecurity,
                 blockchain and bitcoin mining, and self-driving
                 vehicles. By the end of this book, you will have a
                 thorough understanding of modern processors and
                 computer architecture and the future directions these
                 technologies are likely to take.",
  acknowledgement = ack-nhfb,
  tableofcontents = "Introducing Computer Architecture \\
                 Digital Logic \\
                 Processor Elements \\
                 Computer System Components \\
                 Hardware--Software Interface \\
                 Specialized Computing Domains \\
                 Processor and Memory Architectures \\
                 Performance-Enhancing Techniques \\
                 Specialized Processor Extensions \\
                 Modern Processor Architectures and Instruction Sets \\
                 The RISC-V Architecture and Instruction Set \\
                 Processor Virtualization \\
                 Domain-Specific Computer Architectures \\
                 Cybersecurity and Confidential Computing Architectures
                 \\
                 Blockchain and Bitcoin Mining Architectures \\
                 Self-Driving Vehicle Architectures \\
                 Quantim Computing and Other Future Directions in
                 Computer Architectures",
}

@InProceedings{Lee:2022:PQC,
  author =       "Jihye Lee and Whijin Kim and Sohyeon Kim and Ji-Hoon
                 Kim",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Conference on Electronics,
                 Information, and Communication (ICEIC)}",
  title =        "Post-Quantum Cryptography Coprocessor for {RISC-V CPU}
                 Core",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--2",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICEIC54506.2022.9748834",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Leplus:2022:IRD,
  author =       "Ga{\"e}tan Leplus and Olivier Savry and Lilian
                 Bossuet",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Symposium on Hardware
                 Oriented Security and Trust (HOST)}",
  title =        "Insertion of random delay with context-aware dummy
                 instructions generator in a {RISC-V} processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "81--84",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/HOST54066.2022.9840060",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Liu:2022:RVS,
  author =       "Youyao Liu and Yuchen Pan and Longyi Li",
  editor =       "{IEEE}",
  booktitle =    "{2022 14th International Conference on Measuring
                 Technology and Mechatronics Automation (ICMTMA)}",
  title =        "Research on Vector Structure of Neural Network
                 Algorithm Based on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "134--139",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICMTMA54903.2022.00034",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Lodea:2022:ESE,
  author =       "Nicolas Lod{\'e}a and Willian Nunes and Vitor Zanini
                 and Marcos Sartori and Luciano Ost and Ney Calazans and
                 Rafael Garibotti and C{\'e}sar Marcon",
  title =        "Early Soft Error Reliability Analysis on {RISC-V}",
  journal =      "IEEE Latin America Transactions",
  volume =       "20",
  number =       "9",
  pages =        "2139--2145",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TLA.2022.9878169",
  ISSN =         "1548-0992",
  ISSN-L =       "1548-0992",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Loh:2022:VDC,
  author =       "Siu Hong Loh and You Hong Liew and Jia Jia Sim",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 12th International Conference on Control
                 System, Computing and Engineering (ICCSCE)}",
  title =        "{VLSI} Design Course with Verification of {RISC-V}
                 Design using Universal Verification Methodology
                 {(UVM)}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "7--12",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICCSCE54767.2022.9935582",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lu:2022:DPP,
  author =       "Liu Lu",
  editor =       "{IEEE}",
  booktitle =    "{2022 6th International Symposium on Computer Science
                 and Intelligent Control (ISCSIC)}",
  title =        "Design of A Programmable {PCI-E} Encryption System
                 Based on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "368--373",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISCSIC57216.2022.00082",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ma:2022:DSB,
  author =       "Khai-Minh Ma and Tran-Bao-Thuong Cao and Duc-Hung Le",
  editor =       "{IEEE}",
  booktitle =    "{2022 9th NAFOSTED Conference on Information and
                 Computer Science (NICS)}",
  title =        "Design of an {SoC} Based on 32-bit {RISC-V CPU} and
                 Lightweight Block Cipher {PRINCE} on {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "25--29",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/NICS56915.2022.10013427",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Maisto:2022:PVU,
  author =       "Vincenzo Maisto and Alessandro Cilardo",
  editor =       "{IEEE}",
  booktitle =    "{2022 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "A Pluggable Vector Unit for {RISC-V} Vector
                 Extension",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1143--1148",
  year =         "2022",
  DOI =          "https://doi.org/10.23919/DATE54114.2022.9774501",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Mallasen:2022:CCR,
  author =       "David Mallas{\'e}n and Raul Murillo and Alberto A.
                 {Del Barrio} and Guillermo Botella and Luis Pi{\~n}uel
                 and Manuel Prieto-Matias",
  editor =       "{IEEE}",
  booktitle =    "{2022 37th Conference on Design of Circuits and
                 Integrated Circuits (DCIS)}",
  title =        "Customizing the {CVA6 RISC-V} Core to Integrate Posit
                 and Quire Instructions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "01--06",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DCIS55711.2022.9970026",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Mallasen:2022:POSa,
  author =       "David Mallas{\'e}n and Raul Murillo and Alberto A.
                 {Del Barrio} and Guillermo Botella and Luis Pi{\~n}uel
                 and Manuel Prieto-Matias",
  title =        "{PERCIVAL}: Open-Source Posit {RISC-V} Core With Quire
                 Capability",
  journal =      j-IEEE-TRANS-EMERG-TOP-COMPUT,
  volume =       "10",
  number =       "3",
  pages =        "1241--1252",
  month =        jul # "\slash " # sep,
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TETC.2022.3187199",
  ISSN =         "2168-6750 (print), 2376-4562 (electronic)",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Emerging Topics in Computing",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516",
}

@InProceedings{Mallasen:2022:POSb,
  author =       "David Mallas{\'e}n and Raul Murillo and Alberto A.
                 {Del Barrio} and Guillermo Botella and Luis Pi{\~n}uel
                 and Manuel Prieto-Matias",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 29th Symposium on Computer Arithmetic
                 (ARITH)}",
  title =        "{PERCIVAL}: Open-Source Posit {RISC-V} Core With Quire
                 Capability",
  crossref =     "IEEE:2022:ISC",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "66--66",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ARITH54963.2022.00019",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  note =         "Authors and title only. See
                 \cite{Mallasen:2022:POSa}.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-29",
}

@Article{Mariotti:2022:WVB,
  author =       "Gianfranco Mariotti and Roberto Giorgi",
  title =        "\pkg{WebRISC-V}: a 32\slash 64-bit {RISC-V} pipeline
                 simulation tool",
  journal =      j-SOFTWAREX,
  volume =       "18",
  number =       "??",
  pages =        "??--??",
  month =        jun,
  year =         "2022",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1016/j.softx.2022.101105",
  ISSN =         "2352-7110",
  ISSN-L =       "2352-7110",
  bibdate =      "Thu Jun 2 09:45:22 MDT 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/softwarex.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S235271102200070X",
  acknowledgement = ack-nhfb,
  articleno =    "101105",
  fjournal =     "SoftwareX",
  journal-URL =  "https://www.sciencedirect.com/journal/softwarex/issues",
}

@InProceedings{Markov:2022:IRV,
  author =       "D. Markov and A. Romanov",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Ural Conference on Electrical
                 Power Engineering (UralCon)}",
  title =        "Implementation of the {RISC-V} Architecture with the
                 Extended {Zbb} Instruction Set",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "180--184",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/UralCon54942.2022.9906776",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "FPGA; ISA; microarchitecture; RARS; RISC-V; RTL; Zbb",
}

@InProceedings{Martinoli:2022:RIC,
  author =       "Valentin Martinoli and Yannick Teglia and Bouagoun
                 Abdellah and R{\'e}gis Leveugle",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 28th International Symposium on On-Line
                 Testing and Robust System Design (IOLTS)}",
  title =        "Recovering Information on the {CVA6 RISC-V CPU} with a
                 Baremetal Micro-Architectural Covert Channel",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/IOLTS56730.2022.9897297",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Meng:2022:DBH,
  author =       "Ziqin Meng and Yunrui Zhang and Jianyang Zhou and
                 Zichao Guo",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 16th International Conference on
                 Anti-counterfeiting, Security, and Identification
                 (ASID)}",
  title =        "Design of 64-Bit High-Performance Embedded Processor
                 Supporting {RISC-V B}-Extension",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "28--32",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ASID56930.2022.9995771",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Mezger:2022:SRV,
  author =       "Benjamin W. Mezger and Douglas A. Santos and Luigi
                 Dilillo and Cesar A. Zeferino and Douglas R. Melo",
  title =        "A Survey of the {RISC-V} Architecture Software
                 Support",
  journal =      j-IEEE-ACCESS,
  volume =       "10",
  number =       "",
  pages =        "51394--51411",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ACCESS.2022.3174125",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Moratelli:2022:MRV,
  author =       "Carlos Moratelli and Ram{\~a}o Tiburski and S{\'e}rgio
                 F. Johann and Emanuel Moura and Everton {De Matos} and
                 Fabiano Hessel",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 8th World Forum on Internet of Things
                 (WF-IoT)}",
  title =        "{MIPS} and {RISC-V}: Evaluating Virtualization
                 Trade-off for Edge Devices",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/WF-IoT54382.2022.10152084",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/virtual-machines.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Mumcu:2022:PEL,
  author =       "Muhammet Cihat Mumcu and {\.I}hsan {\c{C}}i{\c{c}}ek
                 and Salih Bayar",
  editor =       "{IEEE}",
  booktitle =    "{2022 30th Signal Processing and Communications
                 Applications Conference (SIU)}",
  title =        "Performance Evaluation of Lightweight Cryptographic
                 Algorithms on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/SIU55565.2022.9864856",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Nair:2022:HIN,
  author =       "M. K. Aparna Nair and Police Manoj Kumar Reddy and Y.
                 L. Abijith and Venkatesh Rajagopalan and J. Soumya",
  editor =       "{IEEE}",
  booktitle =    "{2022 35th International Conference on VLSI Design and
                 2022 21st International Conference on Embedded Systems
                 (VLSID)}",
  title =        "Hardware Implementation of Network Interface
                 Architecture for {RISC-V} based {NoC-MPSoC} Framework",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "86--91",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/VLSID2022.2022.00028",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ng:2022:RIP,
  author =       "Jien Hau Ng and Chee Hong Ang and Hwa Chaw Law",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 15th International Symposium on Embedded
                 {Multicore\slash Many-core} Systems-on-Chip (MCSoC)}",
  title =        "A Realization of {IO} Physical Memory Protection for
                 {RISC-V} Systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "375--380",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/MCSoC57363.2022.00066",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Nguyen-Hoang:2022:IBR,
  author =       "Duc-Thinh Nguyen-Hoang and Khai-Minh Ma and Duy-Linh
                 Le and Hong-Hai Thai and Tran-Bao-Thuong Cao and
                 Duc-Hung Le",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE Ninth International Conference on
                 Communications and Electronics (ICCE)}",
  title =        "Implementation of a 32-Bit {RISC-V} Processor with
                 Cryptography Accelerators on {FPGA} and {ASIC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "219--224",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICCE55644.2022.9852060",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Nguyen:2022:TNN,
  author =       "Ngo-Doanh Nguyen and Duy-Hieu Bui and Xuan-Tu Tran",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Conference on Advanced
                 Technologies for Communications (ATC)}",
  title =        "Tiny Neuron Network System based on {RISC-V}
                 Processor: a Decentralized Approach for {IoT}
                 Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "98--103",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ATC55345.2022.9942990",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Nurmi:2022:RSD,
  author =       "Antti Nurmi and Antti Rautakoura and Henri Lunnikivi
                 and Timo D. H{\"a}m{\"a}l{\"a}inen",
  editor =       "{IEEE}",
  booktitle =    "{2022 25th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "A Resilient System Design to Boot a {RISC-V MPSoC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "232--238",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DSD57027.2022.00039",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Paludo:2022:NAL,
  author =       "Rog{\'e}rio Paludo and Leonel Sousa",
  title =        "{NTT} Architecture for a {Linux}-Ready {RISC-V}
                 Fully-Homomorphic Encryption Accelerator",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-1,
  volume =       "69",
  number =       "7",
  pages =        "2669--2682",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TCSI.2022.3166550",
  ISSN =         "1549-8328 (print), 1558-0806 (electronic)",
  ISSN-L =       "1549-8328",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/linux.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/unix.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I: Regular
                 Papers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919",
}

@InProceedings{Pan:2022:PCA,
  author =       "Sing-Yu Pan and Shuenn-Yuh Lee and Yi-Wen Hung and
                 Chou-Ching Lin and Gia-Shing Shieh",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Conference on Recent Advances
                 in Systems Science and Engineering (RASSE)}",
  title =        "A Programmable {CNN} Accelerator with {RISC-V} Core in
                 Real-Time Wearable Application",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/RASSE54974.2022.9989732",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Park:2022:BIS,
  author =       "Seonghwan Park and Dongwook Kang and Jeonghwan Kang
                 and Donghyun Kwon",
  title =        "{Bratter}: An instruction set extension for forward
                 control-flow integrity in {RISC-V}",
  journal =      j-SENSORS-BASEL,
  volume =       "27",
  number =       "4",
  pages =        "1392--1405",
  month =        feb,
  year =         "2022",
  CODEN =        "SENSC9",
  DOI =          "https://doi.org/10.3390/s22041392",
  ISSN =         "1424-8220",
  ISSN-L =       "1424-8220",
  bibdate =      "Tue Dec 19 08:21:10 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Sensors (Basel)",
  journal-URL =  "https://www.mdpi.com/journal/sensors",
}

@InProceedings{Perotti:2022:NAV,
  author =       "Matteo Perotti and Matheus Cavalcante and Nils Wistoff
                 and Renzo Andri and Lukas Cavigelli and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 33rd International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP)}",
  title =        "A {``New Ara''} for Vector Computing: an Open Source
                 Highly Efficient {RISC-V V 1.0} Vector Processor
                 Design",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "43--51",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ASAP54787.2022.00017",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Phangestu:2022:FSP,
  author =       "Aaron Elson Phangestu and Ir. Totok Mujiono and M. I.
                 Kom and St Ahmad Zaini",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Seminar on Intelligent Technology
                 and Its Applications (ISITIA)}",
  title =        "Five-Stage Pipelined 32-Bit {RISC-V} Base Integer
                 Instruction Set Architecture Soft Microprocessor Core
                 in {VHDL}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "304--309",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISITIA56226.2022.9855292",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Plusquellic:2022:ILA,
  author =       "Jim Plusquellic and Donald E. Owen and Tom J. Mannos
                 and Brian Dziki",
  title =        "Information Leakage Analysis Using a Co-Design-Based
                 Fault Injection Technique on a {RISC-V}
                 Microprocessor",
  journal =      j-IEEE-TRANS-CAD-ICS,
  volume =       "41",
  number =       "3",
  pages =        "438--451",
  year =         "2022",
  CODEN =        "ITCSDI",
  DOI =          "https://doi.org/10.1109/TCAD.2021.3065915",
  ISSN =         "0278-0070 (print), 1937-4151 (electronic)",
  ISSN-L =       "0278-0070",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computer-Aided Design of
                 Integrated Circuits and Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43",
}

@InProceedings{Popovici:2022:ERV,
  author =       "Cosmin-Andrei Popovici and Andrei Stan",
  editor =       "{IEEE}",
  booktitle =    "{2022 26th International Conference on System Theory,
                 Control and Computing (ICSTCC)}",
  title =        "Extending a {RISC-V} Core with a {CAN-FD}
                 Communication Unit",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "31--36",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICSTCC55426.2022.9931880",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Prabhakaran:2022:DAM,
  author =       "Sandeep Prabhakaran and Mathan N and V.
                 Vedanarayanan",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Conference on Communication,
                 Computing and Internet of Things (IC3IoT)}",
  title =        "Design and Analysis of a Multi Clocked Pipelined
                 Processor Based on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/IC3IOT53935.2022.9767960",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ramsauer:2022:SHP,
  author =       "Ralf Ramsauer and Stefan Huber and Konrad Schwarz and
                 Jan Kiszka and Wolfgang Mauerer",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 8th World Forum on Internet of Things
                 (WF-IoT)}",
  title =        "Static Hardware Partitioning on {RISC-V}:
                 Shortcomings, Limitations, and Prospects",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/WF-IoT54382.2022.10152063",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Razilov:2022:CSP,
  author =       "Viktor Razilov and Emil Mat{\'u}{\v{s}} and Gerhard
                 Fettweis",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Wireless Communications and Mobile
                 Computing (IWCMC)}",
  title =        "Communications Signal Processing Using {RISC-V} Vector
                 Extension",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "690--695",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/IWCMC55113.2022.9824961",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Rotar:2022:RVB,
  author =       "Danut Rotar and Teodor Petri{\c{t}}a and Florin
                 Alexa",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Symposium on Electronics and
                 Telecommunications (ISETC)}",
  title =        "{RISC-V} based {HW} accelerator",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISETC56213.2022.10010137",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Sa:2022:FLR,
  author =       "Bruno S{\'a} and Jos{\'e} Martins and Sandro Pinto",
  title =        "A First Look at {RISC-V} Virtualization From an
                 Embedded Systems Perspective",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "71",
  number =       "9",
  pages =        "2177--2190",
  month =        sep,
  year =         "2022",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2021.3124320",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/virtual-machines.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}

@Article{Saarinen:2022:DRV,
  author =       "Markku-Juhani O. Saarinen and G. Richard Newell and
                 Ben Marshall",
  title =        "Development of the {RISC-V} entropy source interface",
  journal =      j-J-CRYPTO-ENG,
  volume =       "12",
  number =       "4",
  pages =        "371--386",
  month =        nov,
  year =         "2022",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1007/s13389-021-00275-6",
  ISSN =         "2190-8508 (print), 2190-8516 (electronic)",
  ISSN-L =       "2190-8508",
  bibdate =      "Fri Jun 2 12:32:09 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/jcryptoeng.bib;
                 https://www.math.utah.edu/pub/tex/bib/linux.bib;
                 https://www.math.utah.edu/pub/tex/bib/prng.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/unix.bib",
  URL =          "https://link.springer.com/article/10.1007/s13389-021-00275-6",
  abstract =     "The RISC-V true random number generator (TRNG)
                 architecture breaks with previous ISA TRNG practice by
                 splitting the entropy source (ES) component away from
                 cryptographic DRBGs into a separate privileged
                 interface, and in its use of polling. The modular
                 approach is suitable for the RISC-V hardware IP
                 ecosystem, allows a significantly smaller
                 implementation footprint on platforms that need it,
                 while directly supporting current standards compliance
                 testing methods. We describe the interface, its use in
                 cryptography, and offer additional discussion,
                 background, and rationale for various aspects of it.
                 The design was informed by lessons learned from earlier
                 mainstream ISAs, recently introduced SP 800-90B and
                 FIPS 140-3 entropy audit requirements, AIS 31 and
                 common criteria, current and emerging cryptographic
                 needs such as post-quantum cryptography, and the goal
                 of supporting a wide variety of RISC-V implementations
                 and applications. Many of the architectural choices
                 result from quantitative observations about random
                 number generators in secure microcontrollers, the Linux
                 kernel, and cryptographic libraries.",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Crypto. Eng.",
  fjournal =     "Journal of Cryptographic Engineering",
  journal-URL =  "http://link.springer.com/journal/13389",
}

@InProceedings{Sakamoto:2022:EEN,
  author =       "Keisuke Sakamoto and Masanori Natsui and Takahiro
                 Hanyu",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 65th International Midwest Symposium on
                 Circuits and Systems (MWSCAS)}",
  title =        "Energy-Efficient Nonvolatile {RISC-V CPU} with a
                 Custom Instruction-Controlled Accelerator",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/MWSCAS54063.2022.9859466",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Salomo:2022:ACA,
  author =       "Yahwista Salomo and Infall Syafalni and Nana Sutisna
                 and Rahmat Mulyawan and Trio Adiono",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Symposium on Electronics and Smart
                 Devices (ISESD)}",
  title =        "Analysis of Cache Associativity and Replacement Policy
                 on Matrix Multiplication Performance in {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISESD56103.2022.9980712",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Sanchez-Flores:2022:RCA,
  author =       "Alejandra Sanchez-Flores and Lluc Alvarez and Bartomeu
                 Alorda-Ladaria",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Conference on Omni-layer
                 Intelligent Systems (COINS)}",
  title =        "A review of {CNN} accelerators for embedded systems
                 based on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/COINS54846.2022.9855006",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Santos:2022:NIT,
  author =       "Douglas A. Santos and Andr{\'e} M. P. Mattos and Lucas
                 M. Luza and Carlo Cazzaniga and Maria Kastriotou and
                 Douglas R. Melo and Luigi Dilillo",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "Neutron Irradiation Testing and Analysis of a
                 Fault-Tolerant {RISC-V System-on-Chip}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DFT56152.2022.9962335",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Sarihi:2022:PEO,
  author =       "Amin Sarihi and Michael A. Schoenfelder and
                 Abdel-Hameed A. Badawy",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Performance, Computing, and
                 Communications Conference (IPCCC)}",
  title =        "Performance Evaluation of an Out-of-Order {RISC-V
                 CPU}: a {SPEC INT 2017} Study",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "418--419",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/IPCCC55026.2022.9894297",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Scheipel:2022:MRR,
  author =       "Tobias Scheipel and Florian Angermair and Marcel
                 Baunach",
  editor =       "{IEEE}",
  booktitle =    "{2022 25th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "{moreMCU}: a Runtime-reconfigurable {RISC-V} Platform
                 for Sustainable Embedded Systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "24--31",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DSD57027.2022.00013",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Schmidt:2022:ECG,
  author =       "Colin Schmidt and John Wright and Zhongkai Wang and
                 Eric Chang and Albert Ou and Woorham Bae and Sean Huang
                 and Vladimir Milovanovi{\'c} and Anita Flynn and Brian
                 Richards and Krste Asanovi{\'c} and Elad Alon and
                 Borivoje Nikoli{\'c}",
  title =        "An Eight-Core {1.44-GHz RISC-V} Vector Processor in
                 16-nm {FinFET}",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "57",
  number =       "1",
  pages =        "140--152",
  year =         "2022",
  CODEN =        "IJSCBC",
  DOI =          "https://doi.org/10.1109/JSSC.2021.3118046",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
}

@InProceedings{Sharif:2022:CCA,
  author =       "Uzair Sharif and Daniel Mueller-Gritschneder and Ulf
                 Schlichtmann",
  editor =       "{IEEE}",
  booktitle =    "{2022 11th Mediterranean Conference on Embedded
                 Computing (MECO)}",
  title =        "{COMPAS}: Compiler-assisted Software-implemented
                 Hardware Fault Tolerance for {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/MECO55406.2022.9797144",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Shukla:2022:LOR,
  author =       "Satyam Shukla and Kailash Chandra Ray",
  title =        "A Low-Overhead Reconfigurable {RISC-V} Quad-Core
                 Processor Architecture for Fault-Tolerant
                 Applications",
  journal =      j-IEEE-ACCESS,
  volume =       "10",
  number =       "",
  pages =        "44136--44146",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ACCESS.2022.3169495",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Silveira:2022:PRV,
  author =       "Jonathas Silveira and Lucas Castro and Victor
                 Ara{\'u}jo and Rodrigo Zeli and Daniel Lazari and
                 Marcelo Guedes and Rodolfo Azevedo and Lucas Wanner",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 34th International Symposium on Computer
                 Architecture and High Performance Computing
                 (SBAC-PAD)}",
  title =        "{Prof5}: a {RISC-V} profiler tool",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "201--210",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/SBAC-PAD55451.2022.00031",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Song:2022:HER,
  author =       "Yifan Song and Bowen Jia and Boyuan Yang and Pei
                 Zhang",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Conference on Advances in
                 Electrical Engineering and Computer Applications
                 (AEECA)}",
  title =        "{Hummingbird E203 RISC-V} processor core-based traffic
                 flow detection system design",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "823--826",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/AEECA55500.2022.9919100",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Soria-Pardos:2022:SGO,
  author =       "V{\'\i}ctor Soria-Pardos and Max Doblas and Guillem
                 L{\'o}pez--Parad{\'\i}s and Gerard Cand{\'o}n and
                 Narc{\'\i}s Rodas and Xavier Carril and Pau
                 Fontova--Must{\'e} and Neiel Leyva and Santiago
                 Marco-Sola and Miquel Moret{\'o}",
  editor =       "{IEEE}",
  booktitle =    "{2022 25th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "{Sargantana}: a 1 {GHz+} In-Order {RISC-V} Processor
                 with {SIMD} Vector Extensions in 22nm {FD-SOI}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "254--261",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DSD57027.2022.00042",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Soulard:2022:RVB,
  author =       "Guillaume Soulard and Gabriel P. Lachance and
                 {\'E}lodie Boisselier and Mounir Boukadoum and Amine
                 Miled",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE Canadian Conference on Electrical and
                 Computer Engineering (CCECE)}",
  title =        "{RISC-V} Based Processor Architecture for an Embedded
                 Visible Light Spectrophotometer",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "360--363",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/CCECE49351.2022.9918259",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Stangherlin:2022:DIS,
  author =       "Kleber Stangherlin and Manoj Sachdev",
  title =        "Design and Implementation of a Secure {RISC-V}
                 Microprocessor",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "30",
  number =       "11",
  pages =        "1705--1715",
  year =         "2022",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2022.3203307",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}

@InProceedings{Sud:2022:ECE,
  author =       "Parangat Sud and Shekoufeh Neisarian and Elif Bilge
                 Kavun",
  editor =       "{IEEE}",
  booktitle =    "{2022 25th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "Evaluating Cryptographic Extensions On A {RISC-V}
                 Simulation Environment",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "548--555",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DSD57027.2022.00079",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Swakath:2022:DPE,
  author =       "S. U. Swakath and Abhijit Kshirsagar and Koteswararao
                 Kondepu and Satish Naik Banavath and Andrii Chub and
                 Dmitri Vinnikov",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 63th International Scientific Conference on
                 Power and Electrical Engineering of Riga Technical
                 University (RTUCON)}",
  title =        "Development of a Power Electronics Controller with
                 {RISC-V} based Core for Security-Critical
                 Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/RTUCON56726.2022.9978737",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Syafalni:2022:RVL,
  author =       "Infall Syafalni and Yahwista Salomo and Chyndi Oktavia
                 Devi and Muhammad Ali Novandhika and Nana Sutisna and
                 Rahmat Mulyawan and Trio Adiono",
  editor =       "{IEEE}",
  booktitle =    "{2022 8th International Conference on Wireless and
                 Telematics (ICWT)}",
  title =        "{RISC-V} Learning Framework using {PYNQ FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICWT55831.2022.9935365",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Tabanelli:2022:ORF,
  author =       "Enrico Tabanelli and Giuseppe Tagliavini and Luca
                 Benini",
  title =        "Optimizing Random Forest-Based Inference on {RISC-V
                 MCUs} at the Extreme Edge",
  journal =      j-IEEE-TRANS-CAD-ICS,
  volume =       "41",
  number =       "11",
  pages =        "4516--4526",
  year =         "2022",
  CODEN =        "ITCSDI",
  DOI =          "https://doi.org/10.1109/TCAD.2022.3199903",
  ISSN =         "0278-0070 (print), 1937-4151 (electronic)",
  ISSN-L =       "0278-0070",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computer-Aided Design of
                 Integrated Circuits and Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43",
}

@Article{Taheri:2022:RHL,
  author =       "Farhad Taheri and Siavash Bayat-Sarmadi and Shahriar
                 Hadayeghparast",
  title =        "{RISC-HD}: Lightweight {RISC-V} Processor for
                 Efficient Hyperdimensional Computing Inference",
  journal =      "IEEE Internet of Things Journal",
  volume =       "9",
  number =       "23",
  pages =        "24030--24037",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/JIOT.2022.3191717",
  ISSN =         "2327-4662",
  ISSN-L =       "2327-4662",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Internet Things J.",
}

@InProceedings{Taka:2022:IPR,
  author =       "Endri Taka and George Lentaris and Dimitrios Soudris",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "Improving the performance of {RISC-V} softcores on
                 {FPGA} by exploiting {PVT} variability and {DVFS}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1595--1599",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISCAS48785.2022.9937320",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Takayama:2022:IPM,
  author =       "Riku Takayama and Jubee Tada",
  editor =       "{IEEE}",
  booktitle =    "{2022 Tenth International Symposium on Computing and
                 Networking Workshops (CANDARW)}",
  title =        "An Implementation of a Pattern Matching Accelerator on
                 a {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "273--275",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/CANDARW57323.2022.00059",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/string-matching.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tan:2022:SPS,
  author =       "Sih Pin Tan and Yung It Ho",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 15th International Symposium on Embedded
                 {Multicore\slash Many-core} Systems-on-Chip (MCSoC)}",
  title =        "Scalability of Post-Silicon Test Generation for
                 Multi-core {RISC-V SOC} Validation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "14--17",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/MCSoC57363.2022.00012",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Tang:2022:GGP,
  author =       "Wenkai Tang and Peiyong Zhang",
  title =        "{GPGCN}: A general-purpose graph convolution neural
                 network accelerator based on {RISC-V ISA} extension",
  journal =      j-ELECTRONICS,
  volume =       "11",
  number =       "22",
  pages =        "3833--3854",
  month =        nov,
  year =         "2022",
  DOI =          "https://doi.org/10.3390/electronics11223833",
  ISSN =         "2079-9292",
  bibdate =      "Tue Dec 19 08:10:50 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://www.mdpi.com/2079-9292/11/22/3833",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronics",
  journal-URL =  "https://www.mdpi.com/journal/electronics",
}

@InProceedings{Tine:2022:AGR,
  author =       "Blaise Tine and Varun Saxena and Santosh Srivatsan and
                 Joshua R. Simpson and Fadi Alzammar and Liam Paul
                 Cooper and Sam Jijina and Swetha Rajagoplan and
                 Tejaswini Anand Kumar and Jeff Young and Hyesoon Kim",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE Hot Chips 34 Symposium (HCS)}",
  title =        "Accelerating Graphic Rendering on Programmable {RISC-V
                 GPUs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--15",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/HCS55958.2022.9895607",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tollec:2022:EFE,
  author =       "Simon Tollec and Mihail Asavoae and Damien
                 Courouss{\'e} and Karine Heydemann and Mathieu Jan",
  editor =       "{IEEE}",
  booktitle =    "{2022 Workshop on Fault Detection and Tolerance in
                 Cryptography (FDTC)}",
  title =        "Exploration of Fault Effects on Formal {RISC-V}
                 Microarchitecture Models",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "73--83",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/FDTC57191.2022.00017",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tortorella:2022:RCF,
  author =       "Yvan Tortorella and Luca Bertaccini and Davide Rossi
                 and Luca Benini and Francesco Conti",
  editor =       "{IEEE}",
  booktitle =    "{2022 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "{RedMulE}: a Compact {FP16} Matrix-Multiplication
                 Accelerator for Adaptive Deep Learning on
                 {RISC-V}-Based Ultra-Low-Power {SoCs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1099--1102",
  year =         "2022",
  DOI =          "https://doi.org/10.23919/DATE54114.2022.9774759",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Truesdell:2022:NSP,
  author =       "Daniel S. Truesdell and Xinjian Liu and Jacob Breiholz
                 and Shourya Gupta and Shuo Li and Benton H. Calhoun",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE Symposium on VLSI Technology and Circuits
                 (VLSI Technology and Circuits)}",
  title =        "{NanoWattch}: a Self-Powered {3-nW RISC-V SoC}
                 Operable from {160mV} Photovoltaic Input with
                 Integrated Temperature Sensing and Adaptive Performance
                 Scaling",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "210--211",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830206",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tsai:2022:ETI,
  author =       "Chun-Jen Tsai and Yi-De Lee",
  editor =       "{IEEE}",
  booktitle =    "{2022 IFIP\slash IEEE 30th International Conference on
                 Very Large Scale Integration (VLSI-SoC)}",
  title =        "Embedded {TCP\slash IP} Controller for a {RISC-V
                 SoC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/VLSI-SoC54400.2022.9939600",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tsuchiya:2022:ACT,
  author =       "Tatsuya Tsuchiya and Kanemitsu Ootsu and Takashi
                 Yokota and Shun Kojima",
  editor =       "{IEEE}",
  booktitle =    "{2022 23rd ACIS International Summer Virtual
                 Conference on Software Engineering, Artificial
                 Intelligence, Networking and {Parallel\slash
                 Distributed} Computing (SNPD-Summer)}",
  title =        "Assembly code translation from {ARM64} to {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "68--73",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/SNPD-Summer57817.2022.00020",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tulemez:2022:ICI,
  author =       "{\c{S}}afak T{\"u}lemez and Deniz Turgay Altilar",
  editor =       "{IEEE}",
  booktitle =    "{2022 International Conference on Theoretical and
                 Applied Computer Science and Engineering (ICTASCE)}",
  title =        "Implementation of Code Integrity Check Module for
                 {RISC-V} Architecture with {AES}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "148--152",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICTACSE50438.2022.10009686",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ushakov:2022:THM,
  author =       "V. Ushakov and S. Sovio and Q. Qi and V. Nayani and V.
                 Manea and P. Ginzboorg and J. E. Ekberg",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Conference on Trust, Security
                 and Privacy in Computing and Communications
                 (TrustCom)}",
  title =        "{Trusted Hart} for Mobile {RISC-V} Security",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1587--1596",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TrustCom56396.2022.00228",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Vasudev:2022:ITR,
  author =       "Srikrishna Vasudev and Kartickraj K and Anuj Grover",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE Asia Pacific Conference on Circuits and
                 Systems (APCCAS)}",
  title =        "Up to 13.7\% Increase in Throughput of {RISC V SoC}
                 Using Timing Speculative Razor {SRAM}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "222--225",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/APCCAS55924.2022.10090381",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Vazquez:2022:ERV,
  author =       "Daniel V{\'a}zquez and Alfonso Rodr{\'\i}guez and
                 Andr{\'e}s Otero and Eduardo de la Torre",
  editor =       "{IEEE}",
  booktitle =    "{2022 37th Conference on Design of Circuits and
                 Integrated Circuits (DCIS)}",
  title =        "Extending {RISC-V} Processor Datapaths with
                 Multi-Grain Reconfigurable Overlays",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "01--06",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DCIS55711.2022.9970069",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Venkateswarlu:2022:TPA,
  author =       "Sankatali Venkateswarlu and Subrat Mishra and Herman
                 Oprins and Bjorn Vermeersch and Moritz Brunion and
                 Jun-Han Han and Mircea R. Stan and Pieter Weckx and
                 Francky Catthoor",
  title =        "Thermal Performance Analysis of {Mempool RISC-V}
                 Multicore {SoC}",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "30",
  number =       "11",
  pages =        "1668--1676",
  year =         "2022",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2022.3207553",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}

@InProceedings{Verma:2022:RVC,
  author =       "Anu Verma and Priyamvada Sharma and Bishnu Prasad
                 Das",
  editor =       "{IEEE}",
  booktitle =    "{2022 25th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "{RISC-V} Core with Approximate Multiplier for
                 Error-Tolerant Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "239--246",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DSD57027.2022.00040",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Vijaykumar:2022:MPO,
  author =       "Nandita Vijaykumar and Ataberk Olgun and Konstantinos
                 Kanellopoulos and F. Nisa Bostanci and Hasan Hassan and
                 Mehrshad Lotfi and Phillip B. Gibbons and Onur Mutlu",
  title =        "\pkg{MetaSys}: a Practical Open-source Metadata
                 Management System to Implement and Evaluate Cross-layer
                 Optimizations",
  journal =      j-TACO,
  volume =       "19",
  number =       "2",
  pages =        "26:1--26:29",
  month =        jun,
  year =         "2022",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3505250",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Fri Mar 25 07:03:00 MDT 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/gnu.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3505250",
  abstract =     "This article introduces the first open-source
                 FPGA-based infrastructure, MetaSys, with a prototype in
                 a RISC-V system, to enable the rapid implementation and
                 evaluation of a wide range of cross-layer techniques in
                 real hardware. Hardware-software \ldots{}",
  acknowledgement = ack-nhfb,
  articleno =    "26",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "https://dl.acm.org/loi/taco",
}

@InProceedings{Wang:2022:DBO,
  author =       "Wenzhu Wang and Xiaodong Liu and Jie Yu and Jianfeng
                 Li and Zhou Mao and Zhuoheng Li and Chenguang Ding and
                 Chao Zhang",
  editor =       "{IEEE}",
  booktitle =    "{2022 15th International Conference on Advanced
                 Computer Theory and Engineering (ICACTE)}",
  title =        "The Design and Building of {openKylin} on {RISC-V}
                 Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "88--91",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICACTE55855.2022.9943636",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "openKylin operating system; UKUI (Ultimate Kylin User
                 Interface) package compilation",
}

@InProceedings{Wang:2022:RSP,
  author =       "Hui Wang and Yuyuan Du and Xiangcheng Mu",
  editor =       "{IEEE}",
  booktitle =    "{2022 2nd International Conference on Algorithms, High
                 Performance Computing and Artificial Intelligence
                 (AHPCAI)}",
  title =        "Research on In-System Programming {IP} of {RISC-V}
                 Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "264--269",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/AHPCAI57455.2022.10087608",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wessman:2022:RCR,
  author =       "Nils-Johan Wessman and Fabio Malatesta and Stefano
                 Ribes and Jan Andersson and Antonio
                 Garc{\'\i}a-Vilanova and Miguel Masmano and Vicente
                 Nicolau and Paco Gomez and Jimmy {Le Rhun} and Sergi
                 Alcaide and Guillem Cabo and Francisco Bas and Pedro
                 Benedicte and Fabio Mazzocchetti and Jaume Abella",
  editor =       "{IEEE}",
  booktitle =    "{2022 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "{De-RISC}: a Complete {RISC-V} Based Space-Grade
                 Platform",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "802--807",
  year =         "2022",
  DOI =          "https://doi.org/10.23919/DATE54114.2022.9774557",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wu:2022:ACR,
  author =       "Zheng Wu and Wuzhen Xie and Xiaoling Yi and Haitao
                 Yang and Ruiyao Pu and Xiankui Xiong and Haidong Yao
                 and Chixiao Chen and Jun Tao and Fan Yang",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "An Automated Compiler for {RISC-V} Based {DNN}
                 Accelerator",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "3097--3101",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISCAS48785.2022.9937645",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wu:2022:FIP,
  author =       "Zhongpan Wu and Karim Hammad and Abel Beyene and Yunus
                 Dawji and Ebrahim Ghafar-Zadeh and Sebastian
                 Magierowski",
  editor =       "{IEEE}",
  booktitle =    "{2022 20th IEEE Interregional NEWCAS Conference
                 (NEWCAS)}",
  title =        "An {FPGA} Implementation of a Portable {DNA}
                 Sequencing Device Based on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "417--420",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/NEWCAS52662.2022.9842014",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wu:2022:ICH,
  author =       "Hailong Wu and Jindong Li and Xiang Chen",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Conference on Integrated
                 Circuits, Technologies and Applications (ICTA)}",
  title =        "Implementation of {CNN} Heterogeneous Scheme Based on
                 Domestic {FPGA} with {RISC-V} Soft Core {CPU}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "158--159",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICTA56932.2022.9963056",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Xi:2022:HRV,
  author =       "Yuhao Xi and Zhendong Zhang and Yuze Wang and Wen Wang
                 and Xiaoxia Han and Weidong Wang and Peng Liu",
  editor =       "{IEEE}",
  booktitle =    "{2022 7th International Conference on Integrated
                 Circuits and Microsystems (ICICM)}",
  title =        "A Heterogeneous {RISC-V SoC} for Confidential
                 Computing and Password Recovery",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "500--504",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICICM56102.2022.10011247",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Xu:2022:TDH,
  author =       "Yinan Xu and Zihao Yu and Dan Tang and Guokai Chen and
                 Lu Chen and Lingrui Gou and Yue Jin and Qianruo Li and
                 Xin Li and Zuojun Li and Jiawei Lin and Tong Liu and
                 Zhigang Liu and Jiazhan Tan and Huaqiang Wang and
                 Huizhe Wang and Kaifan Wang and Chuanqi Zhang and
                 Fawang Zhang and Linjuan Zhang and Zifei Zhang and
                 Yangyang Zhao and Yaoyang Zhou and Yike Zhou and
                 Jiangrui Zou and Ye Cai and Dandan Huan and Zusong Li
                 and Jiye Zhao and Zihao Chen and Wei He and Qiyuan Quan
                 and Xingwu Liu and Sa Wang and Kan Shi and Ninghui Sun
                 and Yungang Bao",
  editor =       "{IEEE}",
  booktitle =    "{2022 55th {IEEE\slash ACM} International Symposium on
                 Microarchitecture (MICRO)}",
  title =        "Towards Developing High Performance {RISC-V}
                 Processors Using Agile Methodology",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1178--1199",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/MICRO56248.2022.00080",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Yong:2022:SLI,
  author =       "Kin Fei Yong and Chin Theng Lim and Wei Khoon Teng",
  editor =       "{IEEE}",
  booktitle =    "{2022 17th International Microsystems, Packaging,
                 Assembly and Circuits Technology Conference (IMPACT)}",
  title =        "System Level {IR} Drop Impact on Chip Power
                 Performance Signoff for {RISC-V} System on Chip",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/IMPACT56280.2022.9966707",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{You:2022:RVP,
  author =       "Chao-Xing You and Qi-Tong Wang and Han Zhong and Cheng
                 Liu",
  editor =       "{IEEE}",
  booktitle =    "{2022 4th International Academic Exchange Conference
                 on Science and Technology Innovation (IAECST)}",
  title =        "{RISC-V} processor-based automatic access
                 floating-point computing accelerated dataflow
                 co-processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "647--650",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/IAECST57965.2022.10061878",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Yu:2022:CSI,
  author =       "Xiang Yu and Zhijie Yang and Linghui Peng and Bo Lin
                 and Wenjing Yang and Lei Wang",
  editor =       "{IEEE}",
  booktitle =    "{2022 5th International Conference on Circuits,
                 Systems and Simulation (ICCSS)}",
  title =        "{CNN} Specific {ISA} Extensions Based on {RISC-V}
                 Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "116--120",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICCSS55260.2022.9802445",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Misc{Zeeb:2022:RV,
  author =       "Bjoern Zeeb",
  title =        "{RISC-V}",
  howpublished = "Web site",
  day =          "26",
  month =        jun,
  year =         "2022",
  bibdate =      "Fri Dec 23 12:05:46 2022",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://wiki.freebsd.org/riscv",
  abstract =     "FreeBSD/RISC-V is a architecture port for FreeBSD to
                 run on the RISC-V Instruction-Set Architecture (ISA),
                 able to boot to multi-user mode on the QEMU emulator,
                 Spike simulator and real hardware.",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zgheib:2022:CVS,
  author =       "Anthony Zgheib and Olivier Potin and Jean-Baptiste
                 Rigaud and Jean-Max Dutertre",
  editor =       "{IEEE}",
  booktitle =    "{2022 25th Euromicro Conference on Digital System
                 Design (DSD)}",
  title =        "A {CFI} Verification System based on the {RISC-V}
                 Instruction Trace Encoder",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "456--463",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DSD57027.2022.00067",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhang:2022:ABP,
  author =       "Weiyan Zhang and Mehran Goli and Alireza Mahzoon and
                 Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Workshop on Rapid System
                 Prototyping (RSP)}",
  title =        "{ANN}-based Performance Estimation of Embedded
                 Software for {RISC-V} Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "22--28",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/RSP57251.2022.10039004",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhang:2022:EPE,
  author =       "Weiyan Zhang and Mehran Goli and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2022 25th International Symposium on Design and
                 Diagnostics of Electronic Circuits and Systems
                 (DDECS)}",
  title =        "Early Performance Estimation of Embedded Software on
                 {RISC-V} Processor using Linear Regression",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "20--25",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/DDECS54261.2022.9770144",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhang:2022:POR,
  author =       "Luming Zhang",
  editor =       "{IEEE}",
  booktitle =    "{2022 7th International Conference on Intelligent
                 Computing and Signal Processing (ICSP)}",
  title =        "The Porting and Optimization of {RISC-V UEFI} Boot",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "840--843",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICSP54964.2022.9778600",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhang:2022:RTI,
  author =       "Zhun Zhang and Qiang Hao and Dongdong Xu and Jiqing
                 Wang and Jinhui Ma and Jinlei Zhang and Jiakang Liu and
                 Xiang Wang",
  editor =       "{IEEE}",
  booktitle =    "{2022 8th Annual International Conference on Network
                 and Information Systems for Computers (ICNISC)}",
  title =        "Real-Time Instruction Execution Monitoring with
                 Hardware-Assisted Security Monitoring Unit in {RISC-V}
                 Embedded Systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "192--196",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICNISC57059.2022.00048",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Zhang:2022:TMT,
  author =       "Jipeng Zhang and Junhao Huang and Zhe Liu and Sujoy
                 Sinha Roy",
  title =        "Time-Memory Trade-Offs for {Saber+} on
                 Memory-Constrained {RISC-V} Platform",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "71",
  number =       "11",
  pages =        "2996--3007",
  month =        nov,
  year =         "2022",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2022.3143441",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}

@Article{Zhao:2022:HPD,
  author =       "Yifan Zhao and Ruiqi Xie and Guozhu Xin and Jun Han",
  title =        "A High-Performance Domain-Specific Processor With
                 Matrix Extension of {RISC-V} for {Module-LWE}
                 Applications",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-1,
  volume =       "69",
  number =       "7",
  pages =        "2871--2884",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/TCSI.2022.3162593",
  ISSN =         "1549-8328 (print), 1558-0806 (electronic)",
  ISSN-L =       "1549-8328",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I: Regular
                 Papers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919",
}

@InProceedings{Zheng:2022:SRV,
  author =       "Tian Zheng and Gang Cai and Zhihong Huang",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "A Soft {RISC-V} Processor {IP} with High-performance
                 and Low-resource consumption for {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2538--2541",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ISCAS48785.2022.9937742",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zuo:2022:HBR,
  author =       "Sheng Zuo and Junjie Zhuang and Yao Liu and Mingyu
                 Wang and Zhiyi Yu",
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE International Conference on Integrated
                 Circuits, Technologies and Applications (ICTA)}",
  title =        "Hardware Based {RISC-V} Instruction Set
                 Randomization",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "96--97",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ICTA56932.2022.9963094",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Alonso:2023:VVT,
  author =       "Mart{\'\i} Alonso and David Andreu and Ramon Canal and
                 Stefano {Di Carlo} and Cristiano Chenet and Juanjo
                 Costa and Andreu Girones and Dimitris Gizopoulos and
                 Vasileios Karakostas and Beatriz Otero and George
                 Papadimitriou and Eva Rodr{\'\i}guez and Alessandro
                 Savino",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE European Test Symposium (ETS)}",
  title =        "Validation, Verification, and Testing {(VVT)} of
                 future {RISC-V} powered cloud infrastructures: the
                 {Vitamin-V Horizon Europe Project} perspective",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ETS56758.2023.10174216",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Anders:2023:SRD,
  author =       "Jens Anders and Pablo Andreu and Bernd Becker and
                 Steffen Becker and Riccardo Cantoro and Nikolaos I.
                 Deligiannis and Nourhan Elhamawy and Tobias Faller and
                 Carles Hernandez and Nele Mentens and Mahnaz Namazi
                 Rizi and Ilia Polian and Abolfazl Sajadi and Mathias
                 Sauer and Denis Schwachhofer and Matteo Sonza Reorda
                 and Todor Stefanov and Ilya Tuzov and Stefan Wagner and
                 Nu{\v{s}}a Zidari{\v{c}}",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE European Test Symposium (ETS)}",
  title =        "A Survey of Recent Developments in Testability, Safety
                 and Security of {RISC-V} Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--10",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ETS56758.2023.10174099",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Angioli:2023:AHA,
  author =       "Marco Angioli and Marcello Barbirotta and Antonio
                 Mastrandrea and Saeid Jamili and Mauro Olivieri",
  editor =       "{IEEE}",
  booktitle =    "{2023 18th Conference on Ph.D Research in
                 Microelectronics and Electronics (PRIME)}",
  title =        "Automatic Hardware Accelerators Reconfiguration
                 through {LinearUCB} Algorithms on a {RISC-V}
                 Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "169--172",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/PRIME58259.2023.10161944",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Misc{Anonymous:2023:BBO,
  author =       "Anonymous",
  title =        "{BOOM}: The {Berkeley} Out-of-Order {RISC-V}
                 Processor",
  howpublished = "Web site.",
  year =         "2023",
  bibdate =      "Tue Dec 19 08:01:27 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://github.com/riscv-boom",
  acknowledgement = ack-nhfb,
}

@Misc{Anonymous:2023:CRV,
  author =       "Anonymous",
  title =        "{China RISC-V Alliance}",
  howpublished = "Chinese-language Web site",
  year =         "2023",
  bibdate =      "Tue Dec 19 07:37:27 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "http://crva.ict.ac.cn/",
  acknowledgement = ack-nhfb,
}

@Misc{Anonymous:2023:OSH,
  author =       "Anonymous",
  title =        "Open-Source High-Performance {RISC-V} Processor",
  howpublished = "Web site.",
  year =         "2023",
  bibdate =      "Tue Dec 19 08:02:21 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://github.com/OpenXiangShan/XiangShan",
  acknowledgement = ack-nhfb,
}

@InProceedings{Anonymous:2023:PHP,
  author =       "Anonymous",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE Hot Chips 35 Symposium (HCS)}",
  title =        "{P870} High-Performance {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--19",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/HCS59251.2023.10254712",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Misc{Anonymous:2023:RCG,
  author =       "Anonymous",
  title =        "{Rocket Chip} Generator",
  year =         "2023",
  bibdate =      "Tue Dec 19 07:54:05 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://github.com/chipsalliance/rocket-chip",
  acknowledgement = ack-nhfb,
}

@Misc{Anonymous:2023:SRV,
  author =       "Anonymous",
  title =        "{SweRV RISC-V} Core{\TM} 1.1 From {Western Digital}",
  howpublished = "Web site.",
  year =         "2023",
  bibdate =      "Tue Dec 19 07:56:30 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://github.com/chipsalliance/Cores-VeeR-EH1;
                 https://github.com/westerndigitalcorporation/swerv_eh1",
  acknowledgement = ack-nhfb,
}

@InProceedings{Anonymous:2023:VVD,
  author =       "Anonymous",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE Hot Chips 35 Symposium (HCS)}",
  title =        "{Veyron V1} Data Center-Class {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--16",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/HCS59251.2023.10254710",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{AskariHemmat:2023:BAP,
  author =       "MohammadHossein AskariHemmat and Sean Wagner and Olexa
                 Bilaniuk and Yassine Hariri and Yvon Savaria and
                 Jean-Pierre David",
  editor =       "{IEEE}",
  booktitle =    "{2023 28th Asia and South Pacific Design Automation
                 Conference (ASP-DAC)}",
  title =        "{BARVINN}: Arbitrary Precision {DNN} Accelerator
                 Controlled by a {RISC-V CPU}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "483--489",
  year =         "2023",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{AskariHemmat:2023:QIR,
  author =       "MohammadHossein AskariHemmat and Th{\'e}o Dupuis and
                 Yoan Fournier and Nizar {El Zarif} and Matheus
                 Cavalcante and Matteo Perotti and Frank G{\"u}rkaynak
                 and Luca Benini and Fran{\c{c}}ois Leduc-Primeau and
                 Yvon Savaria and Jean-Pierre David",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "{Quark}: an Integer {RISC-V} Vector Processor for
                 Sub-Byte Quantized {DNN} Inference",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISCAS46773.2023.10181985",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Azad:2023:RRV,
  author =       "Zahra Azad and Guowei Yang and Rashmi Agrawal and
                 Daniel Petrisko and Michael Taylor and Ajay Joshi",
  title =        "{RISE}: {RISC-V SoC} for {En\slash Decryption}
                 Acceleration on the Edge for Homomorphic Encryption",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "31",
  number =       "10",
  pages =        "1523--1536",
  year =         "2023",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2023.3288754",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}

@InProceedings{B:2023:HPS,
  author =       "Anil Kumar D B and Bansilal Bairwa and Bhadriraju
                 Vamsidath and Ujwal V and Tharun P and Tushaar Rao",
  editor =       "{IEEE}",
  booktitle =    "{2023 International Conference on Smart Systems for
                 applications in Electrical Sciences (ICSSES)}",
  title =        "{HDL} Programming and Sequential Circuitry for
                 Multi-Core {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICSSES58299.2023.10201166",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Barral:2023:ESR,
  author =       "Hadrien Barral and Georges-Axel Jaloyan and David
                 Naccache",
  editor =       "{IEEE}",
  booktitle =    "{2023 {\booktitle{IEEE Security and Privacy}}
                 Workshops (SPW)}",
  title =        "Emoji shellcoding in {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "255--263",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/SPW59333.2023.00028",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Benini:2023:NDC,
  author =       "Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2023 9th International Workshop on Advances in
                 Sensors and Interfaces (IWASI)}",
  title =        "From Nano-Drones to Cars --- a {RISC-V} Open Platform
                 for next-generation vehicles",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "8--8",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/IWASI58316.2023.10164418",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Bertuletti:2023:EPP,
  author =       "Marco Bertuletti and Yichao Zhang and Alessandro
                 Vanelli-Coralli and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{2023 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Efficient Parallelization of {5G-PUSCH} on a Scalable
                 {RISC-V} Many-Core Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.23919/DATE56975.2023.10137247",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Bohmer:2023:NRT,
  author =       "Kevin B{\"o}hmer and Bruno Forlin and Carlo Cazzaniga
                 and Paolo Rech and Gianluca Furano and Nikolaos
                 Alachiotis and Marco Ottavi",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "Neutron Radiation Tests of the {NEORV32 RISC-V SoC} on
                 Flash-Based {FPGAs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DFT59622.2023.10313556",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Borowski:2023:ABT,
  author =       "Michal Borowski and Chandrajit Pal and Sangeet Saha
                 and Ludovico Poli and Xiaojun Zhai and Klaus D.
                 McDonald-Maier",
  editor =       "{IEEE}",
  booktitle =    "{2023 21st IEEE Interregional NEWCAS Conference
                 (NEWCAS)}",
  title =        "Anomaly Behaviour tracing of {CHERI-RISC V} using
                 Hardware--Software Co-design",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/NEWCAS57931.2023.10198103",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Bove:2023:BSS,
  author =       "Davide Bove and Julian Funk",
  title =        "Basic secure services for standard {RISC-V}
                 architectures",
  journal =      j-COMPUT-SECUR,
  volume =       "133",
  number =       "??",
  pages =        "??--??",
  month =        oct,
  year =         "2023",
  CODEN =        "CPSEDU",
  DOI =          "https://doi.org/10.1016/j.cose.2023.103415",
  ISSN =         "0167-4048 (print), 1872-6208 (electronic)",
  ISSN-L =       "0167-4048",
  bibdate =      "Wed Aug 23 06:09:54 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computsecur2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0167404823003255",
  acknowledgement = ack-nhfb,
  articleno =    "103415",
  fjournal =     "Computers \& Security",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01674048",
}

@InProceedings{Bruns:2023:PVU,
  author =       "Niklas Bruns and Vladimir Herdt and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2023 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Processor Verification using Symbolic Execution: a
                 {RISC-V} Case-Study",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.23919/DATE56975.2023.10137202",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Cannizzaro:2023:ERV,
  author =       "Michael J. Cannizzaro and Alan D. George",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE Aerospace Conference}",
  title =        "Evaluation of {RISC-V} Silicon Under Neutron
                 Radiation",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--9",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/AERO55745.2023.10115689",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Castells-Rufas:2023:EEP,
  author =       "David Castells-Rufas and Xavier Martorell and Aleix
                 Roca and Alexander Kropotov and Xavier Teruel and
                 Teresa Cervero and John D. Davis",
  editor =       "{IEEE}",
  booktitle =    "{2023 38th Conference on Design of Circuits and
                 Integrated Systems (DCIS)}",
  title =        "{Ethernet} Emulation over {PCIe} for {RISC-V} Software
                 Development Vehicles",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DCIS58620.2023.10335994",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Chatzopoulos:2023:EEO,
  author =       "Odysseas Chatzopoulos and George Papadimitriou and
                 Wing Shek Wong and Dimitris Gizopoulos",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Workload
                 Characterization (IISWC)}",
  title =        "Energy Efficiency of Out-of-Order {CPUs}: Comparative
                 Study and Microarchitectural Hotspot Characterization
                 of {RISC-V} Designs",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "216--220",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/IISWC59245.2023.00032",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Chen:2023:ECR,
  author =       "Gregory K. Chen and Phil C. Knag and Carlos Tokunaga
                 and Ram K. Krishnamurthy",
  title =        "An Eight-Core {RISC-V} Processor With Compute Near
                 Last Level Cache in {Intel 4 CMOS}",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "58",
  number =       "4",
  pages =        "1117--1128",
  year =         "2023",
  CODEN =        "IJSCBC",
  DOI =          "https://doi.org/10.1109/JSSC.2022.3228765",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
}

@InProceedings{Chen:2023:PMZ,
  author =       "Yulong Chen and YanJie Pei and Xiang Lu and Mengyao
                 Shi",
  editor =       "{IEEE}",
  booktitle =    "{ICC 2023 --- IEEE International Conference on
                 Communications}",
  title =        "Point Multiplication {ZigZag}: an Optimized
                 Co-Processor Architecture Design for {SM2/3} Based on
                 {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "3793--3798",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICC45041.2023.10279122",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Chen:2023:RVC,
  author =       "Yuxing Chen and Xinrui Wang and Suwen Song and Lang
                 Feng and Zhongfeng Wang",
  title =        "{RISC-V} Custom Instructions of Elementary Functions
                 for {IoT} Endpoint Devices",
  journal =      j-IEEE-TRANS-COMPUT,
  pages =        "1--13",
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3336174",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}

@InProceedings{Chuah:2023:FVS,
  author =       "Czea Sie Chuah and Christian Appold and Tim
                 Leinmueller",
  editor =       "{IEEE}",
  booktitle =    "{2023 21st ACM-IEEE International Symposium on Formal
                 Methods and Models for System Design (MEMOCODE)}",
  title =        "Formal Verification of Security Properties on {RISC-V}
                 Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "159--168",
  year =         "2023",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Conti:2023:MHR,
  author =       "Francesco Conti and Gianna Paulin and Angelo Garofalo
                 and Davide Rossi and Alfio {Di Mauro} and Georg
                 Rutishauser and Gianmarco Ottavi and Manuel Eggimann
                 and Hayate Okuhara and Luca Benini",
  title =        "{Marsellus}: a Heterogeneous {RISC-V AI-IoT} End-Node
                 {SoC} With 2--8 b {DNN} Acceleration and 30\%-Boost
                 Adaptive Body Biasing",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  pages =        "1--15",
  year =         "2023",
  CODEN =        "IJSCBC",
  DOI =          "https://doi.org/10.1109/JSSC.2023.3318301",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
}

@InProceedings{Conti:2023:WAI,
  author =       "Francesco Conti and Davide Rossi and Gianna Paulin and
                 Angelo Garofalo and Alfio {Di Mauro} and Georg
                 Rutishauser and Gianmarco Ottavi and Manuel Eggimann
                 and Hayate Okuhara and Vincent Huard and Olivier
                 Montfort and Lionel Jure and Nils Exibard and Pascal
                 Gouedo and Mathieu Louvat and Emmanuel Botte and Luca
                 Benini",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Solid-State Circuits
                 Conference (ISSCC)}",
  title =        "{22.1 A 12.4TOPS\slash W @ 136GOPS AI-IoT}
                 {System-on-Chip} with 16 {RISC-V}, {2-to-8b}
                 Precision-Scalable {DNN} Acceleration and 30\%-Boost
                 Adaptive Body Biasing",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "21--23",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISSCC42615.2023.10067643",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Cui:2023:RVI,
  author =       "Enfang Cui and Tianzheng Li and Qian Wei",
  title =        "{RISC-V} Instruction Set Architecture Extensions: a
                 Survey",
  journal =      j-IEEE-ACCESS,
  volume =       "11",
  number =       "",
  pages =        "24696--24711",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ACCESS.2023.3246491",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Cuomo:2023:TRV,
  author =       "Luca Cuomo and Claudio Scordino and Alessandro
                 Ottaviano and Nils Wistoff and Robert Balas and Luca
                 Benini and Errico Guidieri and Ida Maria Savino",
  editor =       "{IEEE}",
  booktitle =    "{2023 12th Mediterranean Conference on Embedded
                 Computing (MECO)}",
  title =        "Towards a {RISC-V} Open Platform for Next-generation
                 Automotive {ECUs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/MECO58584.2023.10154913",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Dao:2023:HTC,
  author =       "Ba-Anh Dao and Ngoc-Quynh Nguyen and Chung-Tien
                 Nguyen",
  editor =       "{IEEE}",
  booktitle =    "{2023 15th International Conference on Knowledge and
                 Systems Engineering (KSE)}",
  title =        "A High-Throughput and Compact {GOST-28147-89}
                 Accelerator for {RISC-V System-on-Chip}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/KSE59128.2023.10299520",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Deb:2023:RVS,
  author =       "Suman Deb and Anupam Chattopadhyay and Avi Mendelson",
  editor =       "{IEEE}",
  booktitle =    "{2023 IFIP\slash IEEE 31st International Conference on
                 Very Large Scale Integration (VLSI-SoC)}",
  title =        "A {RISC-V SoC} with Hardware Trojans: Case Study on
                 Trojan-ing the On-Chip Protocol Conversion",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/VLSI-SoC57769.2023.10321883",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{deOliveira:2023:EFT,
  author =       "{\'A}dria Barros de Oliveira and Fernanda Lima
                 Kastensmidt",
  title =        "Evaluating Fault-Tolerant Techniques on {COTS RISC-V
                 NOEL-V} Processor in {Zynq UltraScale+ FPGA} Under
                 Proton Testing",
  journal =      j-IEEE-TRANS-NUCL-SCI,
  volume =       "70",
  number =       "8",
  pages =        "1708--1715",
  year =         "2023",
  CODEN =        "IRNSAM",
  DOI =          "https://doi.org/10.1109/TNS.2023.3281396",
  ISSN =         "0018-9499 (print), 1558-1578 (electronic)",
  ISSN-L =       "0018-9499",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Nuclear Science",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=23",
}

@InProceedings{Dimitrakopoulos:2023:MAB,
  author =       "G. Dimitrakopoulos and E. Kallitsounakis and Z.
                 Takakis and A. Stefanidis and C. Nicopoulos",
  editor =       "{IEEE}",
  booktitle =    "{2023 12th International Conference on Modern Circuits
                 and Systems Technologies (MOCAST)}",
  title =        "Multi-Armed Bandits for Autonomous Test Application in
                 {RISC-V} Processor Verification",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/MOCAST57943.2023.10176659",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ding:2023:DIS,
  author =       "Can Ding and Yunfei Zhu and Rongcai Zhao and Xiao
                 Zhang",
  editor =       "{IEEE}",
  booktitle =    "{2023 8th International Conference on Intelligent
                 Computing and Signal Processing (ICSP)}",
  title =        "Design and implementation of a speech recognition
                 module based on {RISC-V} embedded processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "20--27",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICSP58490.2023.10248542",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Doblas:2023:SAS,
  author =       "Max Doblas and Gerard Cand{\'o}n and Xavier Carril and
                 Marc Dom{\'\i}nguez and Enric Erra and Alberto
                 Gonz{\'a}lez and C{\'e}sar Hern{\'a}ndez and
                 V{\'\i}ctor Jim{\'e}nez and Vatistas Kostalampros and
                 Rub{\'e}n Langarita and Neiel Leyva and Guillem
                 L{\'o}pez-Parad{\'\i}s and Jonnatan Mendoza and Josep
                 Oltra and Juli{\'a}n Pav{\'o}n and Crist{\'o}bal
                 Ram{\'\i}rez and Narc{\'\i}s Rodas and Enrico Reggiani
                 and Mario Rodr{\'\i}guez and Carlos Rojas and Abraham
                 Ruiz and Hugo Safadi and V{\'\i}ctor Soria and
                 Alejandro Suanes and Iv{\'a}n Vargas and Fernando
                 Arreza and Roger Figueras and Pau Fontova-Must{\'e} and
                 Joan Marimon and Ricardo Mart{\'\i}nez and Sergio
                 Moreno and Jordi Sacrist{\'a}n and Oscar Alonso and
                 Xavier Aragon{\'e}s and Adri{\'a}n Cristal and
                 {\'A}ngel Di{\'e}guez and Manuel L{\'o}pez and Diego
                 Mateo and Francesc Moll and Miquel Moret{\'o} and Oscar
                 Palomar and Marco A. Ram{\'\i}rez and Francesc
                 Serra-Graells and Nehir Sonmez and Llu{\'\i}s Ter{\'e}s
                 and Osman Unsal and Mateo Valero and Luis Villa",
  editor =       "{IEEE}",
  booktitle =    "{2023 38th Conference on Design of Circuits and
                 Integrated Systems (DCIS)}",
  title =        "{Sargantana}: an Academic {SoC RISC-V} Processor in
                 22nm {FDSOI} Technology",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DCIS58620.2023.10335976",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Domingos:2023:SRV,
  author =       "Joao Mario Domingos and Tiago Rocha and Nuno Neves and
                 Nuno Roma and Pedro Tom{\'a}s and Leonel Sousa",
  editor =       "{IEEE}",
  booktitle =    "2023 {IEEE 34th International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP): ASAP 2023, 19--21 July 2023, Porto,
                 Portugal}",
  title =        "Supporting {RISC-V} Performance Counters Through
                 {Linux} Performance Analysis Tools",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "94--101",
  month =        jul,
  year =         "2023",
  DOI =          "https://doi.org/10.1109/asap57973.2023.00027",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/linux.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/unix.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Doran:2023:EVR,
  author =       "Michael A. Doran and Nabeeh Kandalaft",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 14th Annual Ubiquitous Computing,
                 Electronics \& Mobile Communication Conference
                 (UEMCON)}",
  title =        "Embedded Virtualization on {RISC-V} with {seL4}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "0736--0740",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/UEMCON59035.2023.10316016",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/virtual-machines.bib",
  acknowledgement = ack-nhfb,
  keywords =     "formally proven seL4 microkernel",
}

@InProceedings{Ducasse:2023:JCS,
  author =       "Quentin Ducasse and Pascal Cotret and Lo{\"\i}c
                 Lagadec",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Parallel and Distributed
                 Processing Symposium Workshops (IPDPSW)}",
  title =        "{JIT} Compiler Security through Low-Cost {RISC-V}
                 Extension",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "125--128",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/IPDPSW59300.2023.00032",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Dupuis:2023:SCR,
  author =       "Th{\'e}o Dupuis and Yoan Fournier and MohammadHossein
                 AskariHemmat and Nizar {El Zarif} and Fran{\c{c}}ois
                 Leduc-Primeau and Jean Pierre David and Yvon Savaria",
  editor =       "{IEEE}",
  booktitle =    "{2023 21st IEEE Interregional NEWCAS Conference
                 (NEWCAS)}",
  title =        "{Sparq}: a Custom {RISC-V} Vector Processor for
                 Efficient Sub-Byte Quantized Inference",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/NEWCAS57931.2023.10198172",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Emil:2023:DEA,
  author =       "Demyana Emil and Mohammed Hamdy and Gihan Nagib",
  title =        "Development an efficient {AXI}-interconnect unit
                 between set of customized peripheral devices and an
                 implemented dual-core {RISC-V} processor",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "79",
  number =       "15",
  pages =        "17000--17019",
  month =        oct,
  year =         "2023",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-023-05304-1",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Fri Sep 1 07:21:16 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/jsuper2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://link.springer.com/article/10.1007/s11227-023-05304-1",
  acknowledgement = ack-nhfb,
  ajournal =     "J. Supercomputing",
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}

@InProceedings{Faller:2023:CBA,
  author =       "Tobias Faller and Nikolaos I. Deligiannis and Markus
                 Schw{\"o}rer and Matteo Sonza Reorda and Bernd Becker",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE European Test Symposium (ETS)}",
  title =        "Constraint-Based Automatic {SBST} Generation for
                 {RISC-V} Processor Families",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ETS56758.2023.10174156",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Fernandes:2023:EAS,
  author =       "Jo{\~a}o Cassiano V. Fernandes and Helbert da Rocha
                 and Ant{\'o}nio Esp{\'\i}rito-Santo",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Conference on Industrial
                 Technology (ICIT)}",
  title =        "Encryption and Authentication in Smart Transducers
                 Implemented in {RISC-V} Softcore Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICIT58465.2023.10143043",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Forlin:2023:URV,
  author =       "Bruno Endres Forlin and Wouter van Huffelen and Carlo
                 Cazzaniga and Paolo Rech and Nikolaos Alachiotis and
                 Marco Ottavi",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE European Test Symposium (ETS)}",
  title =        "An unprotected {RISC-V} Soft-core processor on an
                 {SRAM FPGA}: Is it as bad as it sounds?",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ETS56758.2023.10174076",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Funck:2023:IIL,
  author =       "Milan Funck and Sallar Ahmadi-Pour and Vladimir Herdt
                 and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2023 Forum on Specification \& Design Languages
                 (FDL)}",
  title =        "Identification of {ISA}-Level Mutation-Classes for
                 Qualification of {RISC-V} Formal Verification",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/FDL59689.2023.10272202",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gao:2023:DGC,
  author =       "Fei Gao and Ting-Jung Chang and Ang Li and Marcelo
                 Orenes-Vera and Davide Giri and Paul J. Jackson and
                 August Ning and Georgios Tziantzioulis and Joseph
                 Zuckerman and Jinzheng Tu and Kaifeng Xu and Grigory
                 Chirkov and Gabriele Tombesi and Jonathan Balkind and
                 Margaret Martonosi and Luca Carloni and David
                 Wentzlaff",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE Custom Integrated Circuits Conference
                 (CICC)}",
  title =        "{DECADES}: a 67mm2, {1.46TOPS, 55} Giga Cache-Coherent
                 64-bit {RISC-V} Instructions per second, Heterogeneous
                 Manycore {SoC} with 109 Tiles including Accelerators,
                 Intelligent Storage, and {eFPGA} in 12nm {FinFET}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--2",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/CICC57935.2023.10121257",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gao:2023:LSL,
  author =       "Yimin Gao and Sergiu Mosanu and Mohammad Nazmus Sakib
                 and Vaibhav Verma and Xinfei Guo and Mircea Stan",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 36th International System-on-Chip
                 Conference (SOCC)}",
  title =        "{LiteAIR5}: a System-Level Framework for the Design
                 and Modeling of {AI}-extended {RISC-V} Cores",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/SOCC58585.2023.10257058",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Geier:2023:CCA,
  author =       "Johannes Geier and Lukas Auer and Daniel
                 Mueller-Gritschneder and Uzair Sharif and Ulf
                 Schlichtmann",
  editor =       "{IEEE}",
  booktitle =    "{2023 28th Asia and South Pacific Design Automation
                 Conference (ASP-DAC)}",
  title =        "{CompaSeC}: a Compiler-assisted Security
                 Countermeasure to Address Instruction Skip Fault
                 Attacks on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2023",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gerlach:2023:SRM,
  author =       "Lukas Gerlach and Daniel Weber and Ruiyi Zhang and
                 Michael Schwarz",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE Symposium on Security and Privacy (SP)}",
  title =        "A Security {RISC}: Microarchitectural Attacks on
                 Hardware {RISC-V CPUs}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "2321--2338",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/SP46215.2023.10179399",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gewehr:2023:IEC,
  author =       "Carlos Gabriel de Araujo Gewehr and Fernando Gehm
                 Moraes",
  editor =       "{IEEE}",
  booktitle =    "{2023 36th {SBC\slash SBMicro\slash IEEE\slash ACM}
                 Symposium on Integrated Circuits and Systems Design
                 (SBCCI)}",
  title =        "Improving the Efficiency of Cryptography Algorithms on
                 Resource-Constrained Embedded Systems via {RISC-V}
                 Instruction Set Extensions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/SBCCI60457.2023.10261964",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Ghasemi:2023:SIH,
  author =       "S. Maryam Ghasemi and Sergej Meschkov and Jonas
                 Krautter and Dennis R. E. Gnad and Mehdi B. Tahoori",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 29th International Symposium on On-Line
                 Testing and Robust System Design (IOLTS)}",
  title =        "{SLM ISA} and Hardware Extensions for {RISC-V}
                 Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/IOLTS59296.2023.10224880",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Gobieski:2023:MMM,
  author =       "Graham Gobieski and Oguz Atli and Cagri Erbagci and
                 Ken Mai and Nathan Beckmann and Brandon Lucia",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "{MANIC}: a $ 19 \mu \mathrm {W} $ @ {4MHz, 256
                 MOPS\slash mW}, {RISC-V} microcontroller with embedded
                 {MRAM} main memory and vector-dataflow co-processor in
                 22nm bulk {finFET CMOS}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISCAS46773.2023.10181809",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Gomez:2023:HLV,
  author =       "Constantino G{\'o}mez and Filippo Mantovani and Erich
                 Focht and Marc Casas",
  title =        "{HPCG} on long-vector architectures: Evaluation and
                 optimization on {NEC SX-Aurora} and {RISC-V}",
  journal =      j-FUT-GEN-COMP-SYS,
  volume =       "143",
  number =       "??",
  pages =        "152--162",
  month =        jun,
  year =         "2023",
  CODEN =        "FGSEVI",
  DOI =          "https://doi.org/10.1016/j.future.2023.01.015",
  ISSN =         "0167-739X (print), 1872-7115 (electronic)",
  ISSN-L =       "0167-739X",
  bibdate =      "Mon Mar 13 08:24:01 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/futgencompsys2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0167739X23000225",
  abstract =     "Accelerators are becoming a key component to improve
                 efficiency in High-Performance Computing systems (HPC).
                 While GPU based systems are widely used to accelerate
                 HPC workloads, new systems based on long-vector
                 architectures are rapidly gaining popularity. The
                 development of optimized math libraries becomes
                 fundamental to achieve high performance in those
                 emerging vector architectures. This paper focuses on
                 the optimization of the HPCG benchmark, which comprises
                 four fundamental kernels found in many numerical
                 applications. We target two relevant long-vector
                 architectures like the NEC Vector Engine and the RISC-V
                 `V' vector extension. Compared to the well-tuned
                 proprietary solution, our open HPCG implementation
                 achieves a 1.6\% improvement in performance on the NEC
                 Vector Engine and achieves near maximum memory
                 bandwidth utilization in the two evaluated RISC-V
                 vector accelerator designs.",
  acknowledgement = ack-nhfb,
  fjournal =     "Future Generation Computer Systems",
  journal-URL =  "http://www.sciencedirect.com/science/journal/0167739X",
}

@InProceedings{Gousselot:2023:LCA,
  author =       "Th{\'e}ophile Gousselot and Olivier Thomas and
                 Jean-Max Dutertre and Olivier Potin and Jean-Baptiste
                 Rigaud",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Hardware
                 Oriented Security and Trust (HOST)}",
  title =        "Lightweight Countermeasures Against Original Linear
                 Code Extraction Attacks on a {RISC-V} Core",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "89--99",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/HOST55118.2023.10133316",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Gruin:2023:MTP,
  author =       "Alban Gruin and Thomas Carle and Christine Rochange
                 and Hugues Cass{\'e} and Pascal Sainrat",
  title =        "{MINOTAuR}: a Timing Predictable {RISC-V} Core
                 Featuring Speculative Execution",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "1",
  pages =        "183--195",
  month =        jan,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2022.3200000",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}

@Article{Guo:2023:TMS,
  author =       "Pengfei Guo and Yingjian Yan and Junjie Wang and
                 Jingxin Zhong and Yanjiang Liu and Jinsong Xu",
  title =        "Towards a metrics suite for evaluating cache
                 side-channel vulnerability: Case studies on an
                 open-source {RISC-V} processor",
  journal =      j-COMPUT-SECUR,
  volume =       "135",
  number =       "??",
  pages =        "??--??",
  month =        dec,
  year =         "2023",
  CODEN =        "CPSEDU",
  DOI =          "https://doi.org/10.1016/j.cose.2023.103480",
  ISSN =         "0167-4048 (print), 1872-6208 (electronic)",
  ISSN-L =       "0167-4048",
  bibdate =      "Fri Nov 10 11:02:45 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computsecur2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/gnu.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0167404823003905",
  acknowledgement = ack-nhfb,
  articleno =    "103480",
  fjournal =     "Computers \& Security",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01674048",
}

@InProceedings{Gupta:2023:CDR,
  author =       "Naina Gupta and Arpan Jati and Anupam Chattopadhyay",
  editor =       "{IEEE}",
  booktitle =    "{2023 {IEEE\slash ACM} International Conference on
                 Computer Aided Design (ICCAD)}",
  title =        "{CRYSTALS-Dilithium} on {RISC-V} Processor:
                 Lightweight Secure Boot Using Post-Quantum Digital
                 Signature",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICCAD57390.2023.10323688",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Ha:2023:KCI,
  author =       "Seon Ha and Minsang Yu and Hyungon Moon and Jongeun
                 Lee",
  title =        "Kernel Code Integrity Protection at the Physical
                 Address Level on {RISC-V}",
  journal =      j-IEEE-ACCESS,
  volume =       "11",
  number =       "",
  pages =        "62358--62367",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ACCESS.2023.3285876",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@Article{Han:2023:MBC,
  author =       "Shaopu Han and Qiguang Wang and Yanfeng Jiang",
  title =        "{MRAM}-Based Cache System Design and Policy
                 Optimization for {RISC-V} Multi-Core {CPUs}",
  journal =      j-IEEE-TRANS-MAGNETICS,
  volume =       "59",
  number =       "6",
  pages =        "1--14",
  year =         "2023",
  CODEN =        "IEMGAQ",
  DOI =          "https://doi.org/10.1109/TMAG.2023.3267467",
  ISSN =         "0018-9464 (print), 1941-0069 (electronic)",
  ISSN-L =       "0018-9464",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Magnetics",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=20",
}

@Article{Han:2023:RVB,
  author =       "Shaopu Han and Yanfeng Jiang",
  title =        "{RISC-V}-Based Evaluation and Strategy Exploration of
                 {MRAM} Triple-Level Hybrid Cache Systems",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "31",
  number =       "7",
  pages =        "980--992",
  year =         "2023",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2023.3268108",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}

@InProceedings{Haribabu:2023:RVC,
  author =       "P Haribabu and Gvk Sasirekha and Madhav Rao and
                 Jyotsna Bapat and Debabrata Das",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE\slash ACM 23rd International Symposium on
                 Cluster, Cloud and Internet Computing Workshops
                 (CCGridW)}",
  title =        "{RISC-V} Core for Ethical Intelligent {IoT} Edge:
                 Analysis \& Design Choice",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "110--117",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/CCGridW59191.2023.00031",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Harmina:2023:DIC,
  author =       "Tomislav Harmina and Daniel Hofman and Jakov Benjak",
  editor =       "{IEEE}",
  booktitle =    "{2023 International Symposium ELMAR}",
  title =        "{DCT} Implementation on a Custom {FPGA RISC-V}
                 Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "163--167",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ELMAR59410.2023.10253892",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Misc{Harris:2023:CVW,
  author =       "Sarah Harris and David Harris and Rose Thompson and
                 {45 others}",
  title =        "{CORE-V Wally}",
  howpublished = "Web source code archive",
  year =         "2023",
  bibdate =      "Thu Dec 28 10:17:09 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://github.com/openhwgroup/cvw",
  acknowledgement = ack-nhfb,
  remark =       "From the Web site: ``CORE-V Wally is a configurable
                 RISC-V Processor associated with \booktitle{RISC-V
                 System-on-Chip Design} textbook. Contains a 5-stage
                 pipeline, support for A, B, C, D, F, M and Q
                 extensions, and optional caches, BP, FPU, VM/MMU, AHB,
                 RAMs, and peripherals.'' From the README file: ``Wally
                 is described in an upcoming textbook, \booktitle{RISC-V
                 System-on-Chip Design}, by Harris, Stine, Thompson, and
                 Harris.''  See also earlier book \cite{Harris:2022:DDC}.",
}

@InProceedings{He:2023:AHS,
  author =       "Zicheng He and Ao Sheri and Qiufeng Li and Quan Cheng
                 and Hao Yu",
  editor =       "{IEEE}",
  booktitle =    "{2023 28th Asia and South Pacific Design Automation
                 Conference (ASP-DAC)}",
  title =        "Agile Hardware and Software Co-design for
                 {RISC-V}-based Multi-precision Deep Learning
                 Microprocessor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "490--495",
  year =         "2023",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{He:2023:DIR,
  author =       "Jiangwei He and Weiwei Shi and Chaoyuan Wu and Zhihong
                 Mo",
  editor =       "{IEEE}",
  booktitle =    "{2023 6th International Conference on Electronics
                 Technology (ICET)}",
  title =        "Design and Implementation of a {RISC-V SoC} for
                 Real-Time Epilepsy Detection on {FPGA}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "127--132",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICET58434.2023.10211684",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{He:2023:ROS,
  author =       "Tianchen He and Xiangning Chen and Guokang Wang",
  editor =       "{IEEE}",
  booktitle =    "{2023 8th International Conference on Computer and
                 Communication Systems (ICCCS)}",
  title =        "Research on Open Source Processor and Analysis of
                 Current Development Dilemma Based on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "768--774",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICCCS57501.2023.10151171",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Hepola:2023:EEE,
  author =       "Kari Hepola and Joonas Multanen and Pekka
                 J{\"a}{\"a}skel{\"a}inen",
  title =        "Energy-Efficient Exposed Datapath Architecture With a
                 {RISC-V} Instruction Set Mode",
  journal =      j-IEEE-TRANS-COMPUT,
  pages =        "1--13",
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3337313",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}

@InProceedings{Hubert:2023:MOO,
  author =       "Bastien Hubert and Omar Hammami",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Conference on Design, Test
                 and Technology of Integrated Systems (DTTIS)}",
  title =        "Multi-objective Optimisation of {RISC-V CV32A6} for
                 {ML} application",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DTTIS59576.2023.10348379",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Imianosky:2023:IRE,
  author =       "Carolina Imianosky and Douglas A. Santos and Douglas
                 R. Melo and Felipe VieE and Luigi Dilillo",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "Implementation and Reliability Evaluation of a
                 {RISC-V} Vector Extension Unit",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DFT59622.2023.10313569",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Jahnke:2023:PEP,
  author =       "Marek Jahnke and Lucas Bublitz and Ulf Kulau",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE Nordic Circuits and Systems Conference
                 (NorCAS)}",
  title =        "Performance Evaluation of {PicoRV32 RISC-V} Softcore
                 for Resource-Constrained Devices",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/NorCAS58970.2023.10305479",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Jiang:2023:FAU,
  author =       "Shijie Jiang and Yi Zou and Hao Wang and Wanwan Li",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 34th International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP)}",
  title =        "An {FFT} Accelerator Using Deeply-coupled {RISC-V}
                 Instruction Set Extension for Arbitrary Number of
                 Points",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "165--171",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ASAP57973.2023.00036",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Jimenez:2023:FVR,
  author =       "Victor Jimenez and Mario Rodriguez and Marc Dominguez
                 and Josep Sans and Ivan Diaz and Luca Valente and Vito
                 Luca Guglielmi and Josue V. Quiroga and R. Ignacio
                 Genovese and Nehir Sonmez and Oscar Palomar and Miquel
                 Moreto",
  title =        "Functional Verification of a {RISC-V} Vector
                 Accelerator",
  journal =      "IEEE Design \& Test",
  volume =       "40",
  number =       "3",
  pages =        "36--44",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/MDAT.2022.3226709",
  ISSN =         "2168-2356 (print), 2168-2364 (electronic)",
  ISSN-L =       "2168-2356",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Jin:2023:SBS,
  author =       "Hai Jin and Zhuo He and Weizhong Qiang",
  title =        "{SpecTerminator}: Blocking Speculative Side Channels
                 Based on Instruction Classes on {RISC-V}",
  journal =      j-TACO,
  volume =       "20",
  number =       "1",
  pages =        "15:1--15:??",
  month =        mar,
  year =         "2023",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3566053",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Fri Feb 17 06:54:21 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3566053",
  abstract =     "In modern processors, speculative execution has
                 significantly improved the performance of processors,
                 but it has also introduced speculative execution
                 vulnerabilities. Recent defenses are based on the
                 delayed execution to block various speculative side
                 channels, but we show that several of the current
                 state-of-the-art defenses fail to block some of the
                 available speculative side channels, and the current
                 most secure defense introduces a performance overhead
                 of up to 24.5\%.\par

                 We propose SpecTerminator, the first defense framework
                 based on instruction classes that can comprehensively
                 and precisely block all existing speculative side
                 channels. In SpecTerminator, a novel speculative side
                 channel classification scheme based on the features of
                 secret transmission is proposed, and the sensitive
                 instructions in the speculative window are classified
                 and identified using optimized hardware taint tracking
                 and instruction masking techniques to accurately
                 determine the scope of leakage. Then, according to the
                 execution characteristics of these instructions,
                 dedicated delayed execution strategies, such as TLB
                 request ignoring, selective issue, and extended
                 delay-on-miss, are designed for each type of sensitive
                 instruction to precisely control that these
                 instructions are delayed only in pipeline stages that
                 are at risk of leakage. In contrast to previous
                 defenses based on the Gem5 simulator, we have
                 innovatively implemented defenses against Spectre
                 attacks based on the open-source instruction set RISC-V
                 on an FPGA-accelerated simulation platform that is more
                 similar to real hardware. To evaluate the security of
                 SpecTerminator, we have replicated various existing
                 x86-based Spectre variants on RISC-V. On SPEC 2006,
                 SpecTerminator defends against Spectre attacks based on
                 memory hierarchy side channels with a performance
                 overhead of 2.6\% and against all existing Spectre
                 attacks with a performance overhead of 6.0\%.",
  acknowledgement = ack-nhfb,
  articleno =    "15",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "https://dl.acm.org/loi/taco",
}

@Article{Joannou:2023:RTR,
  author =       "Alexandre Joannou and Peter Rugg and Jonathan Woodruff
                 and Franz A. Fuchs and Marno {Van der Maas} and Matthew
                 Naylor and Michael Roe and Robert N. M. Watson and
                 Peter G. Neumann and Simon W. Moore",
  title =        "Randomized Testing of {RISC-V CPUs} using Direct
                 Instruction Injection",
  journal =      "IEEE Design \& Test",
  pages =        "1--1",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/MDAT.2023.3262741",
  ISSN =         "2168-2356 (print), 2168-2364 (electronic)",
  ISSN-L =       "2168-2356",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Jose:2023:SME,
  author =       "Tom Jose and Deepak Shankar",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE Space Computing Conference (SCC)}",
  title =        "System Model Evaluation of {RISC-V} Cores for improved
                 performance and fault tolerance",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "86--91",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/SCC57168.2023.00022",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Karmakar:2023:HSI,
  author =       "Apurba Karmakar and Santiago S{\'a}nchez-Solano and
                 Macarena C. Mart{\'\i}nez-Rodr{\'\i}guez and Piedad
                 Brox",
  editor =       "{IEEE}",
  booktitle =    "{2023 38th Conference on Design of Circuits and
                 Integrated Systems (DCIS)}",
  title =        "{HW\slash SW} implementation of {RSA} digital
                 signature on a {RISC-V}-based {System-on-Chip}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DCIS58620.2023.10335970",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Korsman:2023:EEM,
  author =       "Aleksi Korsman and Verneri Hirvonen and Otto Simola
                 and Antti Tarkka and Marko Kosunen and Jussi
                 Ryyn{\"a}nen",
  editor =       "{IEEE}",
  booktitle =    "{2023 19th International Conference on Synthesis,
                 Modeling, Analysis and Simulation Methods and
                 Applications to Circuit Design (SMACD)}",
  title =        "End-to-End Multi-Target Verification Environment for a
                 {RISC-V} Microprocessor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/SMACD58065.2023.10192249",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Kra:2023:HLP,
  author =       "Yehuda Kra and Yonatan Shoshan and Yehuda Rudin and
                 Adam Teman",
  title =        "{HAMSA-DI}: a Low-Power Dual-Issue {RISC-V} Core
                 Targeting Energy-Efficient Embedded Systems",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-1,
  pages =        "1--14",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TCSI.2023.3323425",
  ISSN =         "1549-8328 (print), 1558-0806 (electronic)",
  ISSN-L =       "1549-8328",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I: Regular
                 Papers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919",
}

@InProceedings{Kressel:2023:EIO,
  author =       "John Alistair Kressel and Guillermo Callaghan and
                 Cosmin Gorgovan and Mikel Luj{\'a}n",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Performance
                 Analysis of Systems and Software (ISPASS)}",
  title =        "Evaluating the Impact of Optimizations for Dynamic
                 Binary Modification on 64-bit {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "81--91",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISPASS57527.2023.00017",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Kuo:2023:IRT,
  author =       "Yao-Ming Kuo and Mark F. Flanagan and Francisco
                 Garcia-Herrero and {\'O}scar Ruano and Juan Antonio
                 Maestro",
  title =        "Integration of a Real-Time {CCSDS 410.0-B-32}
                 Error-Correction Decoder on {FPGA-Based RISC-V SoCs}
                 Using {RISC-V} Vector Extension",
  journal =      j-IEEE-TRANS-AEROSP-ELECTRON-SYST,
  volume =       "59",
  number =       "5",
  pages =        "5835--5846",
  year =         "2023",
  CODEN =        "IEARAX",
  DOI =          "https://doi.org/10.1109/TAES.2023.3266314",
  ISSN =         "0018-9251 (print), 1557-9603 (electronic)",
  ISSN-L =       "0018-9251",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Aerospace and Electronic
                 Systems",
}

@Article{Kuo:2023:RVG,
  author =       "Yao-Ming Kuo and Francisco Garc{\'\i}a-Herrero and
                 Oscar Ruano and Juan Antonio Maestro",
  title =        "{RISC-V Galois Field ISA} Extension for Non-Binary
                 Error-Correction Codes and Classical and Post-Quantum
                 Cryptography",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "3",
  pages =        "682--692",
  month =        mar,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2022.3174587",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}

@InProceedings{Kurian:2023:PER,
  author =       "Ashley Kurian and M. Ramesh Kini",
  booktitle =    "Lecture Notes in Networks and Systems",
  title =        "Posit Extended {RISC-V} Processor and Its Enhancement
                 Using Data Type Casting",
  publisher =    "Springer Nature",
  address =      "Singapore",
  pages =        "571--586",
  year =         "2023",
  DOI =          "https://doi.org/10.1007/978-981-19-6634-7_40",
  ISBN =         "981-19663-4-6",
  ISBN-13 =      "978-981-19663-4-7",
  ISSN =         "2367-3389",
  bibdate =      "Fri Dec 15 11:31:31 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "posit arithmetic",
}

@InProceedings{Lee:2023:DDB,
  author =       "Seunghyun Lee and Jeik Choi and Seockhwan Noh and
                 Jahyun Koo and Jaeha Kung",
  editor =       "{IEEE}",
  booktitle =    "{2023 60th {ACM\slash IEEE} Design Automation
                 Conference (DAC)}",
  title =        "{DBPS}: Dynamic Block Size and Precision Scaling for
                 Efficient {DNN} Training Supported by {RISC-V ISA}
                 Extensions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DAC56929.2023.10248013",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lee:2023:SDD,
  author =       "Jimin Lee and Jae Min Kim and Junho Huh and Jungwoo
                 Kim",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Conference on Consumer
                 Electronics (ICCE)}",
  title =        "Software-driven Debug Framework for Embedded {RISC-V},
                 that Transparently Emulates the Industry Standard Debug
                 Framework",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICCE56470.2023.10043490",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Li:2023:CCC,
  author =       "Ang Li and Ting-Jung Chang and Fei Gao and Tuan Ta and
                 Georgios Tziantzioulis and Yanghui Ou and Moyang Wang
                 and Jinzheng Tu and Kaifeng Xu and Paul Jackson and
                 August Ning and Grigory Chirkov and Marcelo Orenes-Vera
                 and Shady Agwa and Xiaoyu Yan and Eric Tang and
                 Jonathan Balkind and Christopher Batten and David
                 Wentzlaff",
  title =        "{CIFER}: a Cache-Coherent 12-nm 16-mm2 {SoC} With Four
                 64-Bit {RISC-V} Application Cores, 18 32-Bit {RISC-V}
                 Compute Cores, and a 1541 {LUT6\slash mm2}
                 Synthesizable {eFPGA}",
  journal =      "IEEE Solid-State Circuits Letters",
  volume =       "6",
  number =       "",
  pages =        "229--232",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/LSSC.2023.3303111",
  ISSN =         "2573-9603",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Li:2023:EAA,
  author =       "Jia-Yu Li and Yi-Kai Chen and Wai-Chi Fang",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 12th Global Conference on Consumer
                 Electronics (GCCE)}",
  title =        "An Edge {AI} Accelerator Design Based on {LRCN} Model
                 for Real-time {EEG}-based Emotion Detection System on
                 the {RISC-V FPGA} Platform",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "89--90",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/GCCE59613.2023.10315393",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Li:2023:MPC,
  author =       "Huimin Li and Nele Mentens and Stjepan Picek",
  editor =       "{IEEE}",
  booktitle =    "{2023 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Maximizing the Potential of Custom {RISC-V} Vector
                 Extensions for Speeding up {SHA-3} Hash Functions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.23919/DATE56975.2023.10137009",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/hash.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Li:2023:PDC,
  author =       "Kai Li and Wei Yin and Qiang Liu",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "A Portable {DSP} Coprocessor Design Using {RISC-V}
                 Packed-{SIMD} Instructions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISCAS46773.2023.10181681",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Li:2023:SCE,
  author =       "Wenxin Li and Weike Wang and Senyang Li and Zhenliang
                 An",
  editor =       "{IEEE}",
  booktitle =    "{2023 9th International Symposium on System Security,
                 Safety, and Reliability (ISSSR)}",
  title =        "A Static {CFG} Extraction Scheme for {RISC-V} Runtime
                 {CFI}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "444--445",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISSSR58837.2023.00073",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Liang:2023:IHI,
  author =       "Quanyi Liang and Shaobin Xie and Boyang Cai",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 3rd International Conference on Power,
                 Electronics and Computer Applications (ICPECA)}",
  title =        "Intelligent Home {IoT} Intrusion Detection System
                 Based on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "296--300",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICPECA56706.2023.10076248",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Liu:2023:BPA,
  author =       "Yen-Fu Liu and Chou-Ying Hsieh and Sy-Yen Kuo",
  editor =       "{IEEE}",
  booktitle =    "2023 {IEEE 34th International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP): ASAP 2023, 19--21 July 2023, Porto,
                 Portugal}",
  title =        "{Boomerang}: Physical-Aware Design Space Exploration
                 Framework on {RISC-V SonicBOOM} Microarchitecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "85--93",
  month =        jul,
  year =         "2023",
  DOI =          "https://doi.org/10.1109/asap57973.2023.00026",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Lopez-Villellas:2023:RVG,
  author =       "Lori{\'e}n L{\'o}pez-Villellas and Esteve
                 Pineda-S{\'a}nchez and Asaf Badouh and Santiago
                 Marco-Sola and Pablo Ib{\'a}{\~n}ez and Jes{\'u}s
                 Alastruey-Bened{\'e} and Miquel Moret{\'o}",
  editor =       "{IEEE}",
  booktitle =    "{2023 38th Conference on Design of Circuits and
                 Integrated Systems (DCIS)}",
  title =        "{RISC-V} for Genome Data Analysis: Opportunities and
                 Challenges",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DCIS58620.2023.10335997",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Luchterhandt:2023:TRC,
  author =       "Lars Luchterhandt and Tom Nellius and Robert Beck and
                 Rainer Doemer and Pascal Kneuper and Wolfgang Mueller
                 and Babak Sadiye",
  editor =       "{IEEE}",
  booktitle =    "{MBMV 2023; 26th Workshop}",
  title =        "Towards a {Rocket Chip} Based Implementation of the
                 {RISC-V GPC} Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2023",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Ma:2023:DSB,
  author =       "Khai-Minh Ma and Duc-Hung Le and Cong-Kha Pham and
                 Trong-Thuc Hoang",
  title =        "Design of an {SoC} Based on 32-Bit {RISC-V} Processor
                 with Low-Latency Lightweight Cryptographic Cores in
                 {FPGA}",
  journal =      j-FUTURE-INTERNET,
  volume =       "15",
  number =       "5",
  pages =        "186",
  day =          "19",
  month =        may,
  year =         "2023",
  CODEN =        "????",
  DOI =          "https://doi.org/10.3390/fi15050186",
  ISSN =         "1999-5903",
  bibdate =      "Thu Jun 1 07:41:25 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/future-internet.bib;
                 https://www.math.utah.edu/pub/tex/bib/hash.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://www.mdpi.com/1999-5903/15/5/186",
  abstract =     "The security of Internet of Things (IoTs) devices in
                 recent years has created interest in developing
                 implementations of lightweight cryptographic algorithms
                 for such systems. Additionally, open-source hardware
                 and field-programable gate arrays (FPGAs) are gaining
                 traction via newly developed tools, frameworks, and
                 HDLs. This enables new methods of creating hardware and
                 systems faster, more simply, and more efficiently. In
                 this paper, the implementation of a system-on-chip
                 (SoC) based on a 32-bit RISC-V processor with
                 lightweight cryptographic accelerator cores in FPGA and
                 an open-source integrating framework is presented. The
                 system consists of a 32-bit VexRiscv processor, written
                 in SpinalHDL, and lightweight cryptographic accelerator
                 cores for the PRINCE block cipher, the PRESENT-80 block
                 cipher, the ChaCha stream cipher, and the SHA3-512 hash
                 function, written in Verilog HDL and optimized for low
                 latency with fewer clock cycles. The primary aim of
                 this work was to develop a customized SoC platform with
                 a register-controlled bus suitable for integrating
                 lightweight cryptographic cores to become compact
                 embedded systems that require encryption
                 functionalities. Additionally, custom firmware was
                 developed to verify the functionality of the SoC with
                 all integrated accelerator cores, and to evaluate the
                 speed of cryptographic processing. The proposed system
                 was successfully implemented in a Xilinx Nexys4 DDR
                 FPGA development board. The resources of the system in
                 the FPGA were low with 11,830 LUTs and 9552 FFs. The
                 proposed system can be applicable to enhancing the
                 security of Internet of Things systems.",
  acknowledgement = ack-nhfb,
  fjournal =     "Future Internet",
  journal-URL =  "https://www.mdpi.com/journal/futureinternet",
}

@InProceedings{Mach:2023:NRV,
  author =       "J{\'a}n Mach and Luk{\'a}{\v{s}} Koh{\'u}tka and Pavel
                 {\v{C}}i{\v{c}}{\'a}k",
  editor =       "{IEEE}",
  booktitle =    "{2023 12th Mediterranean Conference on Embedded
                 Computing (MECO)}",
  title =        "A New {RISC-V CPU} for Safety-Critical Systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/MECO58584.2023.10155108",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Malathi:2023:DRV,
  author =       "D. Malathi and R. Sneha and M. Shanmugapriya and S.
                 Sethurajan",
  editor =       "{IEEE}",
  booktitle =    "{2023 4th International Conference on Signal
                 Processing and Communication (ICSPC)}",
  title =        "Design of {RISC-V} Processing Unit Using Posit Number
                 System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "427--431",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICSPC57692.2023.10125646",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Malone:2023:RVP,
  author =       "Steven Malone and Patrick Saenz and Patrick Phelan",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE Aerospace Conference}",
  title =        "{RISC-V} Processors for Spaceflight Embedded
                 Platforms",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--11",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/AERO55745.2023.10115850",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Mao:2023:RIR,
  author =       "Gaoyu Mao and Yao Liu and Wangchen Dai and Guangyan Li
                 and Zhewen Zhang and Alan H. F. Lam and Ray C. C.
                 Cheung",
  title =        "{REALISE-IoT}: {RISC-V} Based Efficient and
                 Lightweight Public-Key System for {IoT} Applications",
  journal =      "IEEE Internet of Things Journal",
  pages =        "1--1",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/JIOT.2023.3296135",
  ISSN =         "2327-4662",
  ISSN-L =       "2327-4662",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Internet Things J.",
}

@InProceedings{Mendat:2023:RVN,
  author =       "Daniel R. Mendat and Jonah P. Sengupta and Gaspar
                 Tognetti and Martin Villemur and Philippe O. Pouliquen
                 and Sergio Montano and Kayode Sanni and Jamal L. Molin
                 and Nishant Zachariah and Isidoros Doxas and Andreas G.
                 Andreou",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "A {RISC-V} Neuromorphic Micro-Controller Unit {(vMCU)}
                 with Event-Based Physical Interface and Computational
                 Memory for Low-Latency Machine Perception and
                 Intelligence at the Edge",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISCAS46773.2023.10181861",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Mezger:2023:HRT,
  author =       "Benjamin W. Mezger and Douglas A. Santos and Luigi
                 Dilillo and Douglas R. Melo",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "Hardening a Real-Time Operating System for a
                 Dependable {RISC-V System-on-Chip}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DFT59622.2023.10313566",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Min:2023:EER,
  author =       "Jung Gyu Min and Dongyun Kam and Younghoon Byun and
                 Gunho Park and Youngjoo Lee",
  editor =       "{IEEE}",
  booktitle =    "{2023 {IEEE\slash ACM} International Symposium on Low
                 Power Electronics and Design (ISLPED)}",
  title =        "Energy-Efficient {RISC-V}-Based Vector Processor for
                 Cache-Aware Structurally-Pruned Transformers",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISLPED58423.2023.10244508",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Minervini:2023:VAE,
  author =       "Francesco Minervini and Oscar Palomar and Osman Unsal
                 and Enrico Reggiani and Josue Quiroga and Joan Marimon
                 and Carlos Rojas and Roger Figueras and Abraham Ruiz
                 and Alberto Gonzalez and Jonnatan Mendoza and Ivan
                 Vargas and C{\'e}sar Hernandez and Joan Cabre and Lina
                 Khoirunisya and Mustapha Bouhali and Julian Pavon and
                 Francesc Moll and Mauro Olivieri and Mario Kovac and
                 Mate Kovac and Leon Dragic and Mateo Valero and Adrian
                 Cristal",
  title =        "{Vitruvius+}: an Area-Efficient {RISC-V} Decoupled
                 Vector Coprocessor for High Performance Computing
                 Applications",
  journal =      j-TACO,
  volume =       "20",
  number =       "2",
  pages =        "28:1--28:??",
  month =        jun,
  year =         "2023",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3575861",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Sat Jun 10 08:08:06 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3575861",
  abstract =     "The maturity level of RISC-V and the availability of
                 domain-specific instruction set extensions, like vector
                 processing, make RISC-V a good candidate for supporting
                 the integration of specialized hardware in processor
                 cores for the High Performance \ldots{}",
  acknowledgement = ack-nhfb,
  articleno =    "28",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "https://dl.acm.org/loi/taco",
}

@InProceedings{Minev:2023:PCA,
  author =       "Petar Minev and Valentina Kukenska and Ilian Varbov
                 and Matyo Dinev",
  editor =       "{IEEE}",
  booktitle =    "{2023 XXXII International Scientific Conference
                 Electronics (ET)}",
  title =        "A Practical Computer Architecture Education with
                 {RISC-V} and {TL-Verilog}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ET59121.2023.10279744",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Moallemi:2023:SSI,
  author =       "Amirhossein Moallemi and Riccardo Gaspari and Federica
                 Zonzini and Luca {De Marchi} and Davide Brunelli and
                 Luca Benini",
  title =        "Speeding up System Identification Algorithms on a
                 Parallel {RISC-V MCU} for Fast Near-Sensor Vibration
                 Diagnostic",
  journal =      "IEEE Sensors Letters",
  volume =       "7",
  number =       "9",
  pages =        "1--4",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/LSENS.2023.3303074",
  ISSN =         "2475-1472",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Sens. Lett.",
}

@Article{Molina-Robles:2023:ECB,
  author =       "Roberto Molina-Robles and Alfredo Arnaud and
                 Mat{\'\i}as Miguez and Joel Gak and Alfonso
                 Chac{\'o}n-Rodr{\'\i}guez and Ronny
                 Garc{\'\i}a-Ram{\'\i}rez",
  title =        "An Energy Consumption Benchmark for a Low-Power
                 {RISC-V} Core Aimed at Implantable Medical Devices",
  journal =      "IEEE Embedded Systems Letters",
  volume =       "15",
  number =       "2",
  pages =        "57--60",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/LES.2022.3190063",
  ISSN =         "1943-0663 (print), 1943-0671 (electronic)",
  ISSN-L =       "1943-0663",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Morris:2023:EDA,
  author =       "Jordan Morris and Ashur Rafiev and Graeme M. Bragg and
                 Mark L. Vousden and David B. Thomas and Alex Yakovlev
                 and Andrew D. Brown",
  title =        "An Event-Driven Approach to Genotype Imputation on a
                 Custom {RISC-V} Cluster",
  journal =      j-TCBB,
  pages =        "1--10",
  year =         "2023",
  CODEN =        "ITCBCY",
  DOI =          "https://doi.org/10.1109/TCBB.2023.3328714",
  ISSN =         "1545-5963 (print), 1557-9964 (electronic)",
  ISSN-L =       "1545-5963",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE\slash ACM Transactions on Computational Biology
                 and Bioinformatics",
  journal-URL =  "https://dl.acm.org/loi/tcbb",
}

@InProceedings{Nadalini:2023:TWR,
  author =       "Alessandro Nadalini and Georg Rutishauser and Alessio
                 Burrello and Nazareno Bruschi and Angelo Garofalo and
                 Luca Benini and Francesco Conti and Davide Rossi",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE Computer Society Annual Symposium on VLSI
                 (ISVLSI)}",
  title =        "A 3 {TOPS\slash W RISC-V} Parallel Cluster for
                 Inference of Fine-Grain Mixed-Precision Quantized
                 Neural Networks",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISVLSI59464.2023.10238679",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Nanjundaswamy:2023:RVT,
  author =       "Nithin Ravani Nanjundaswamy and Gregor Nitsche and
                 Frank Poppen and Kim Gr{\"u}ttner",
  editor =       "{IEEE}",
  booktitle =    "{2023 53rd Annual {IEEE\slash IFIP} International
                 Conference on Dependable Systems and Networks Workshops
                 (DSN-W)}",
  title =        "{RISC-V} Timing-Instructions for Open Time-Triggered
                 Architectures",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "211--214",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DSN-W58399.2023.00058",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Nascimento:2023:RVS,
  author =       "Felipe F. Nascimento and Rodrigo N. Wuerdig and
                 Andr{\'e} F. Ponchet and Bruno Sanches and Denis S.
                 Loubach and Roberto D'Amore and Marcus H. Victor Junior
                 and Walter S. Oliveira and Vitor O. Kuribara and Luiz
                 C. Moreira",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE Seventh Ecuador Technical Chapters Meeting
                 (ECTM)}",
  title =        "{RISC-V SoC} Physical Implementation in 180 nm {CMOS}
                 with a {Quark} Core Based on {FemtoRV32}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ETCM58927.2023.10309011",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Nikiema:2023:DLC,
  author =       "Pegdwende Romaric Nikiema and Angeliki Kritikakou and
                 Marcello Traiola and Olivier Sentieys",
  editor =       "{IEEE}",
  booktitle =    "{2023 53rd Annual {IEEE\slash IFIP} International
                 Conference on Dependable Systems and Networks ---
                 Supplemental Volume (DSN-S)}",
  title =        "Design with low complexity fine-grained {Dual Core
                 Lock-Step (DCLS) RISC-V} processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "224--229",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DSN-S58398.2023.00062",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Nikiema:2023:TDR,
  author =       "Pegdwende Romaric Nikiema and Alessandro Palumbo and
                 Allan Aasma and Luca Cassano and Angeliki Kritikakou
                 and Ari Kulmala and Jari Lukkarila and Marco Ottavi and
                 Rafail Psiakis and Marcello Traiola",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 29th International Symposium on On-Line
                 Testing and Robust System Design (IOLTS)}",
  title =        "Towards Dependable {RISC-V} Cores for Edge Computing
                 Devices",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/IOLTS59296.2023.10224862",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Nunes:2023:VAA,
  author =       "Willian Analdo Nunes and Marcos Luiggi Lemos Sartori
                 and Matheus Trevisan Moreira and Fernando Gehm Moraes
                 and Ney Laert Vilar Calazans",
  editor =       "{IEEE}",
  booktitle =    "{2023 36th {SBC\slash SBMicro\slash IEEE\slash ACM}
                 Symposium on Integrated Circuits and Systems Design
                 (SBCCI)}",
  title =        "Validating an Automated Asynchronous Synthesis
                 Environment with a Challenging Design: {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/SBCCI60457.2023.10261656",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Ottaviano:2023:CLL,
  author =       "Alessandro Ottaviano and Thomas Benz and Paul
                 Scheffler and Luca Benini",
  title =        "{Cheshire}: a Lightweight, {Linux}-Capable {RISC-V}
                 Host Platform for Domain-Specific Accelerator Plug-In",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "70",
  number =       "10",
  pages =        "3777--3781",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TCSII.2023.3289186",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/linux.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/unix.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
}

@InProceedings{P:2023:AOF,
  author =       "Gayathri G P and Jaya S and Krishnakumar Rao S",
  editor =       "{IEEE}",
  booktitle =    "{2023 International Conference on Control,
                 Communication and Computing (ICCC)}",
  title =        "An Area Optimized Floating-Point Coprocessor for
                 {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICCC57789.2023.10165397",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Park:2023:DUL,
  author =       "Jina Park and Eunjin Choi and Kyungwon Lee and Jae-Jin
                 Lee and Kyuseung Han and Woojoo Lee",
  editor =       "{IEEE}",
  booktitle =    "{2023 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Developing an Ultra-low Power {RISC-V} Processor for
                 Anomaly Detection",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--2",
  year =         "2023",
  DOI =          "https://doi.org/10.23919/DATE56975.2023.10137003",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Park:2023:FDL,
  author =       "Jina Park and Kyuseung Han and Eunjin Choi and Sukho
                 Lee and Jae-Jin Lee and Woojoo Lee and Massoud Pedram",
  editor =       "{IEEE}",
  booktitle =    "{2023 {IEEE\slash ACM} International Symposium on Low
                 Power Electronics and Design (ISLPED)}",
  title =        "{Florian}: Developing a Low-Power {RISC-V} Multicore
                 Processor with a Shared Lightweight {FPU}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISLPED58423.2023.10244431",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Parvin:2023:RDL,
  author =       "Sajjad Parvin and Sallar Ahmadi-Pour and Chandan Kumar
                 Jha and Frank Sill Torres and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Conference on Omni-layer
                 Intelligent Systems (COINS)}",
  title =        "{Lo-RISK}: Design of a Low Optical Leakage and High
                 Performance {RISC-V} Core",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/COINS57856.2023.10189332",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Parvin:2023:TDP,
  author =       "Sajjad Parvin and Mehran Goli and Frank Sill Torres
                 and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2023 28th Asia and South Pacific Design Automation
                 Conference (ASP-DAC)}",
  title =        "{Trojan-D2}: Post-Layout Design and Detection of
                 Stealthy Hardware Trojans --- a {RISC-V} Case Study",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "683--689",
  year =         "2023",
  DOI =          "",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Perotti:2023:YOS,
  author =       "Matteo Perotti and Matheus Cavalcante and Alessandro
                 Ottaviano and Jiantao Liu and Luca Benini",
  title =        "{Yun}: an Open-Source, 64-Bit {RISC-V}-Based Vector
                 Processor With Multi-Precision Integer and
                 Floating-Point Support in 65-nm {CMOS}",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "70",
  number =       "10",
  pages =        "3732--3736",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TCSII.2023.3292579",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
}

@Article{Philip:2023:ICE,
  author =       "Sebin Shaji Philip and Roberto Passerone and Kasim
                 Sinan Yildirim and Davide Brunelli",
  title =        "Intermittent Computing Emulation of Ultralow-Power
                 Processors: Evaluation of Backup Strategies for
                 {RISC-V}",
  journal =      j-IEEE-TRANS-CAD-ICS,
  volume =       "42",
  number =       "1",
  pages =        "82--94",
  year =         "2023",
  CODEN =        "ITCSDI",
  DOI =          "https://doi.org/10.1109/TCAD.2022.3169108",
  ISSN =         "0278-0070 (print), 1937-4151 (electronic)",
  ISSN-L =       "0278-0070",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computer-Aided Design of
                 Integrated Circuits and Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43",
}

@InProceedings{Pillement:2023:SRV,
  author =       "S. Pillement and M. M{\'e}ndez Real and J. Pottier and
                 T. Nieddu and B. {Le Gal} and S. Faucou and J. L.
                 B{\'e}chennec and M. Briday and S. Girbal and J. {Le
                 Rhun} and O. Gilles and D. Gracia P{\'e}rez and A.
                 Sintzoff and J. R. Coulon",
  editor =       "{IEEE}",
  booktitle =    "{2023 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "Securing a {RISC-V} architecture: a dynamic approach",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.23919/DATE56975.2023.10136972",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Popovici:2023:RVE,
  author =       "Cosmin-Andrei Popovici and Andrei Stan and Vasile-Ion
                 Manta",
  editor =       "{IEEE}",
  booktitle =    "{2023 27th International Conference on System Theory,
                 Control and Computing (ICSTCC)}",
  title =        "{RISC-V} Extension for Optimized {PWM} Control",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "404--409",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICSTCC59206.2023.10308510",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Qi:2023:DPF,
  author =       "Yu Qi and Mengxue Chen and Guilan Li and Gaosheng Li
                 and Meisheng He and Bangjian Xu",
  editor =       "{IEEE}",
  booktitle =    "{2023 2nd International Conference on Computing,
                 Communication, Perception and Quantum Technology
                 (CCPQT)}",
  title =        "A Deeply Pipelined {FMA} Unit for High Performance
                 {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "53--59",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/CCPQT60491.2023.00015",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Rao:2023:GBC,
  author =       "Ambika S. Rao and Arjun Kudtarkar and Lakshmi Harakuni
                 and G. Nagendra Rao and Kumar K. Sudeendra",
  editor =       "{IEEE}",
  booktitle =    "{2023 2nd International Conference on Vision Towards
                 Emerging Trends in Communication and Networking
                 Technologies (ViTECoN)}",
  title =        "A Generic On-Board Computer based on {RISC-V}
                 Architecture Processor for Low Cost Nanosatellite
                 Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ViTECoN58111.2023.10157686",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Rao:2023:IRE,
  author =       "Ambika S. Rao and Rahul Anilkumar and K. Padmapriya
                 and K. Sudeendra Kumar",
  editor =       "{IEEE}",
  booktitle =    "{2023 International Conference on Networking and
                 Communications (ICNWC)}",
  title =        "Improving Reliability of Embedded {RISC-V SoC} for
                 Low-cost Space Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICNWC57852.2023.10127244",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Raza:2023:ODI,
  author =       "Muhammad Ali Raza and Iraj Shahzad and Hafsa Anwar and
                 Muhammad Ali Qureshi and Farhan Hassan Malik and
                 Muhammad Usman Ali Khan",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Conference on Emerging Trends
                 in Engineering, Sciences and Technology {(ICES\&T)}}",
  title =        "An Optimum Design and Implementation of a 16-bit {ALU}
                 on {CADENCE} Using {RISC-V} Architecture",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICEST56843.2023.10138869",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Rogan:2023:RVI,
  author =       "Sam Rogan and Yoshihito Kondo",
  editor =       "{IEEE}",
  booktitle =    "{2023 International Conference on IC Design and
                 Technology (ICICDT)}",
  title =        "{RISC-V} Is Inevitable",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "xxxvi--xxxvi",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICICDT59917.2023.10332314",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Roodsari:2023:LCL,
  author =       "Mahboobe Sadeghipour Roodsari and Fatemeh Sheikhshoaei
                 and Nicolo Maunero and Paolo Prinetto and Zain Navabi",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Conference on Design, Test
                 and Technology of Integrated Systems (DTTIS)}",
  title =        "{LiFi-CFI}: Light-weight Fine-grained Hardware {CFI}
                 Protection for {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DTTIS59576.2023.10348176",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Rutishauser:2023:CMR,
  author =       "Georg Rutishauser and Robin Hunziker and Alfio {Di
                 Mauro} and Sizhen Bian and Luca Benini and Michele
                 Magno",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "{ColibriES}: a Milliwatts {RISC-V} Based Embedded
                 System Leveraging Neuromorphic and Neural Networks
                 Hardware Accelerators for Low-Latency Closed-loop
                 Control Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISCAS46773.2023.10181726",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{S:2023:DMC,
  author =       "Sajin S and Shubham Sunil Garag and Anuj Phegade and
                 Deepshikha Gusain and Kuruvilla Varghese",
  editor =       "{IEEE}",
  booktitle =    "{2023 36th International Conference on VLSI Design and
                 2023 22nd International Conference on Embedded Systems
                 (VLSID)}",
  title =        "Design of a Multi-Core Compatible {Linux} Bootable
                 64-bit Out-of-Order {RISC-V} Processor Core",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "42--47",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/VLSID57277.2023.00023",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/linux.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/unix.bib",
  acknowledgement = ack-nhfb,
}

@Article{Sa:2023:CRV,
  author =       "Bruno S{\'a} and Luca Valente and Jos{\'e} Martins and
                 Davide Rossi and Luca Benini and Sandro Pinto",
  title =        "{CVA6 RISC-V} Virtualization: Architecture,
                 Microarchitecture, and Design Space Exploration",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "31",
  number =       "11",
  pages =        "1713--1726",
  year =         "2023",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2023.3302837",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/virtual-machines.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}

@InProceedings{Sadrabadi:2023:ESE,
  author =       "Bahareh Ebrahimi Sadrabadi and Catherine H. Gebotys",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE Physical Assurance and Inspection of
                 Electronics (PAINE)}",
  title =        "Exploring Security of Embedded {SRAM} in {PIC} and
                 {RISC-V} Chips: Insights from Image Processing of
                 Low-Cost Photon Emission Microscopy",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/PAINE58317.2023.10317997",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Safari:2023:HHP,
  author =       "Negin Safari and Amirmahdi Joudi and Maryam
                 Rajabalipanah and Zahra Jahanpeima and Hasan
                 Sadeghzadeh and Zainalabedin Navabi",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE East--West Design \& Test Symposium
                 (EWDTS)}",
  title =        "{HIRMA}: High-Performance Implementation for {RISC-V}
                 Microcontroller Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/EWDTS59469.2023.10297033",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Saif:2023:FIE,
  author =       "Md. Hasanul Banna Saif and Nahin {Ul Sadad} and Md.
                 Nazrul Islam Mondal",
  editor =       "{IEEE}",
  booktitle =    "{2023 International Conference on Electrical, Computer
                 and Communication Engineering (ECCE)}",
  title =        "{FPGA} Implementation of Educational {RISC-V}
                 Processor Suitable for Embedded Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ECCE57851.2023.10101508",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Santos:2023:CFT,
  author =       "Douglas A. Santos and Andr{\'e} M. P. Mattos and
                 Douglas R. Melo and Luigi Dilillo",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Defect and Fault
                 Tolerance in VLSI and Nanotechnology Systems (DFT)}",
  title =        "Characterization of a Fault-Tolerant {RISC-V}
                 {System-on-Chip} for Space Environments",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/DFT59622.2023.10313549",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Sarraseca:2023:SOS,
  author =       "Marcel Sarraseca and Sergi Alcaide and Francisco
                 Fuentes and Juan Carlos Rodriguez and Feng Chang and
                 Ilham Lasfar and Ramon Canal and Francisco J. Cazorla
                 and Jaume Abella",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 29th International Symposium on On-Line
                 Testing and Robust System Design (IOLTS)}",
  title =        "{SafeLS}: an Open Source Implementation of a Lockstep
                 {NOEL-V RISC-V} Core",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/IOLTS59296.2023.10224867",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Saussereau:2023:ASO,
  author =       "Jonathan Saussereau and Camille Leroux and
                 Jean-Baptiste Begueret and Christophe Jego",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Circuits and
                 Systems (ISCAS)}",
  title =        "{AsteRISC}: a Size-Optimized {RISC-V} Core for Design
                 Space Exploration",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISCAS46773.2023.10181330",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Scherer:2023:SLP,
  author =       "Moritz Scherer and Manuel Eggimann and Alfio {Di
                 Mauro} and Arpan Suravi Prasad and Francesco Conti and
                 Davide Rossi and Jorge Tom{\'a}s G{\'o}mez and Ziyun Li
                 and Syed Shakib Sarwar and Zhao Wang and Barbara {De
                 Salvo} and Luca Benini",
  editor =       "{IEEE}",
  booktitle =    "{ESSCIRC 2023- IEEE 49th European Solid State Circuits
                 Conference (ESSCIRC)}",
  title =        "{Siracusa}: a Low-Power On-Sensor {RISC-V SoC} for
                 Extended Reality Visual Processing in 16nm {CMOS}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "217--220",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ESSCIRC59616.2023.10268718",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Selg:2023:MBO,
  author =       "Hardi Selg and Maksim Jenihhin and Peeter Ellervee and
                 Jaan Raik",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 29th International Symposium on On-Line
                 Testing and Robust System Design (IOLTS)}",
  title =        "{ML}-Based Online Design Error Localization for
                 {RISC-V} Implementations",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/IOLTS59296.2023.10224864",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Shu:2023:HDS,
  author =       "Yuqiao Shu and Zhenjiang Wang and Lei Wang and
                 Chengzhuo Li",
  editor =       "{IEEE}",
  booktitle =    "{2023 3rd International Symposium on Computer
                 Technology and Information Science (ISCTIS)}",
  title =        "Hardware Design of {SM2} Coprocessor Based on
                 {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1099--1104",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISCTIS58954.2023.10213122",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Shukla:2023:EFT,
  author =       "Satyam Shukla and Utkarsh and Md Azam and Kailash
                 Chandra Ray",
  title =        "An Efficient Fault-Tolerant Instruction Decoder for
                 {RISC-V} Based Dual-Core Soft-Processors",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-1,
  pages =        "1--10",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TCSI.2023.3315604",
  ISSN =         "1549-8328 (print), 1558-0806 (electronic)",
  ISSN-L =       "1549-8328",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems I: Regular
                 Papers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919",
}

@Article{Snelgrove:2023:SPT,
  author =       "Martin Snelgrove and Robert Beachler",
  title =        "{speedAI240}: a 2-Petaflop, {30-Teraflops\slash W}
                 At-Memory Inference Acceleration Device With 1456
                 {RISC-V} Cores",
  journal =      j-IEEE-MICRO,
  volume =       "43",
  number =       "3",
  pages =        "58--63",
  month =        may # "\slash " # jun,
  year =         "2023",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2023.3255864",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
}

@Article{Talpes:2023:MDT,
  author =       "Emil Talpes and Debjit Das Sarma and Doug Williams and
                 Sahil Arora and Thomas Kunjan and Benjamin Floering and
                 Ankit Jalote and Christopher Hsiong and Chandrasekhar
                 Poorna and Vaidehi Samant and John Sicilia and Anantha
                 Kumar Nivarti and Raghuvir Ramachandran and Tim Fischer
                 and Ben Herzberg and Bill McGee and Ganesh
                 Venkataramanan and Pete Banon",
  title =        "The Microarchitecture of {DOJO}, {Tesla}'s Exa-Scale
                 Computer",
  journal =      j-IEEE-MICRO,
  volume =       "43",
  number =       "3",
  pages =        "31--39",
  month =        may # "\slash " # jun,
  year =         "2023",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2023.3258906",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Thu May 18 07:38:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/hot-chips.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
  remark =       "DOJO is based on RISC-V64 with instruction set
                 extensions. Its arithmetic supports 8-, 16-, 32-, and
                 64-bit integers, and IEEE 754 FP32 (1/8/23), plus FP16
                 (1/5/10), BFP16 (1/8/7), CFP8 (1/4/3), CFP8 (1/5/2),
                 and CFP16 (1/5/10) floating-point formats. The latter
                 is unusual having an external register that records the
                 exponent bias (0, 31, or 63), so that it supports three
                 different ranges of numbers. There is no support for
                 FP64 or longer formats. There is support for stochastic
                 rounding.",
}

@InProceedings{Tang:2023:VRV,
  author =       "Shibo Tang and Jiacheng Zhu and Yifei Gao and Jing
                 Zhou and Dejun Mu and Wei Hu",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 32nd Asian Test Symposium (ATS)}",
  title =        "Verifying {RISC-V} Privilege Transition Integrity
                 Through Symbolic Execution",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ATS59501.2023.10317946",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tempel:2023:MIG,
  author =       "S{\"o}ren Tempel and Tobias Brandt and Christoph
                 L{\"u}th and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2023 Forum on Specification \& Design Languages
                 (FDL)}",
  title =        "Minimally Invasive Generation of {RISC-V} Instruction
                 Set Simulators from Formal {ISA} Models",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--8",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/FDL59689.2023.10272224",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Tiwari:2023:IDI,
  author =       "Ankita Tiwari and Prithwijit Guha and Gaurav Trivedi
                 and Nitesh Gupta and Navneeth Jayaraj and Jan Pidanic",
  editor =       "{IEEE}",
  booktitle =    "{2023 33rd International Conference Radioelektronika
                 (RADIOELEKTRONIKA)}",
  title =        "{IndiRA}: Design and Implementation of a Pipelined
                 {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/RADIOELEKTRONIKA57919.2023.10109058",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Tran:2023:TFP,
  author =       "Thai-Ha Tran and Ba-Anh Dao and Trong-Thuc Hoang and
                 Van-Phuc Hoang and Cong-Kha Pham",
  title =        "Transition Factors of Power Consumption Models for
                 {CPA} Attacks on Cryptographic {RISC-V SoC}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "72",
  number =       "9",
  pages =        "2689--2700",
  month =        sep,
  year =         "2023",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3262926",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}

@InProceedings{Tsai:2023:IDM,
  author =       "Chun-Jen Tsai and Chun Wei Chao and Sheng-Di Hong",
  editor =       "{IEEE}",
  booktitle =    "{2023 IFIP\slash IEEE 31st International Conference on
                 Very Large Scale Integration (VLSI-SoC)}",
  title =        "Integrated Dynamic Memory Manager for a {RISC-V}
                 Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/VLSI-SoC57769.2023.10321894",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Valente:2023:HVH,
  author =       "Luca Valente and Yvan Tortorella and Mattia Sinigaglia
                 and Giuseppe Tagliavini and Alessandro Capotondi and
                 Luca Benini and Davide Rossi",
  editor =       "{IEEE}",
  booktitle =    "{2023 Design, Automation \& Test in Europe Conference
                 \& Exhibition (DATE)}",
  title =        "{HULK-V}: a Heterogeneous Ultra-low-power {Linux}
                 capable {RISC-V SoC}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.23919/DATE56975.2023.10137252",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/linux.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/unix.bib",
  acknowledgement = ack-nhfb,
}

@Article{Venkateswarlu:2023:IDI,
  author =       "Sankatali Venkateswarlu and Subrat Mishra and Herman
                 Oprins and Bjorn Vermeersch and Moritz Brunion and
                 Jun-Han Han and Mircea R. Stan and Dwaipayan Biswas and
                 Pieter Weckx and Francky Catthoor",
  title =        "Impact of {3-D} Integration on Thermal Performance of
                 {RISC-V MemPool} Multicore {SOC}",
  journal =      j-IEEE-TRANS-VLSI-SYST,
  volume =       "31",
  number =       "12",
  pages =        "1896--1904",
  year =         "2023",
  CODEN =        "IEVSE9",
  DOI =          "https://doi.org/10.1109/TVLSI.2023.3314135",
  ISSN =         "1063-8210 (print), 1557-9999 (electronic)",
  ISSN-L =       "1063-8210",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Very Large Scale Integration
                 (VLSI) Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=92",
}

@Article{Vizcaino:2023:ALV,
  author =       "Pablo Vizcaino and Filippo Mantovani and Roger Ferrer
                 and Jesus Labarta",
  title =        "Acceleration with long vector architectures:
                 Implementation and evaluation of the {FFT} kernel on
                 {NEC SX-Aurora} and {RISC-V} vector extension",
  journal =      j-CCPE,
  volume =       "35",
  number =       "20",
  pages =        "e7424:1--e7424:??",
  day =          "10",
  month =        sep,
  year =         "2023",
  CODEN =        "CCPEBO",
  DOI =          "https://doi.org/10.1002/cpe.7424",
  ISSN =         "1532-0626 (print), 1532-0634 (electronic)",
  ISSN-L =       "1532-0626",
  bibdate =      "Wed Sep 27 08:16:49 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ccpe2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "Concurr. Comput.",
  fjournal =     "Concurrency and Computation: Practice and Experience",
  journal-URL =  "http://www.interscience.wiley.com/jpages/1532-0626",
  onlinedate =   "02 November 2022",
}

@InProceedings{Wang:2023:DIS,
  author =       "Shangshou Wang and Lei Wang and Huaili Guo and
                 Zhengjiang Wang",
  editor =       "{IEEE}",
  booktitle =    "{2023 3rd International Symposium on Computer
                 Technology and Information Science (ISCTIS)}",
  title =        "Design and Implementation of {SM4} Coprocessor Based
                 on {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1052--1057",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISCTIS58954.2023.10213118",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "SM4 cryptographic standard algorithm",
}

@Article{Wang:2023:LRV,
  author =       "Peng Wang and Zhi-Bin Yu",
  title =        "{LLVM RISC-V RV32X} Graphics Extension Support and
                 Characteristics Analysis of Graphics Programs",
  journal =      j-IEEE-ACCESS,
  volume =       "11",
  number =       "",
  pages =        "67285--67297",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ACCESS.2023.3291920",
  ISSN =         "2169-3536",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Access",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639",
}

@InProceedings{Wang:2023:OXE,
  author =       "Jiaolong Wang and Lei Wang and Peixin Wang",
  editor =       "{IEEE}",
  booktitle =    "{2023 3rd International Symposium on Computer
                 Technology and Information Science (ISCTIS)}",
  title =        "Optimisation of x264 encoder acceleration based on
                 {RISC-V} vector instructions",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1128--1133",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISCTIS58954.2023.10213200",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wang:2023:RCA,
  author =       "Hansen Wang and Dongju Li and Tsuyoshi Isshiki",
  editor =       "{IEEE}",
  booktitle =    "{2023 6th International Conference on Electronics
                 Technology (ICET)}",
  title =        "Reconfigurable {CNN} Accelerator Embedded in
                 Instruction Extended {RISC-V} Core",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "945--954",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICET58434.2023.10211513",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Wei:2023:REI,
  author =       "Qian Wei and Enfang Cui and Yue Gao and Tianzheng Li",
  editor =       "{IEEE}",
  booktitle =    "{2023 2nd International Conference on Computing,
                 Communication, Perception and Quantum Technology
                 (CCPQT)}",
  title =        "A Review of Edge Intelligence Applications Based on
                 {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "115--119",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/CCPQT60491.2023.00025",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Weingarten:2023:PFV,
  author =       "Lennart Weingarten and Alireza Mahzoon and Mehran Goli
                 and Rolf Drechsler",
  editor =       "{IEEE}",
  booktitle =    "{2023 24th International Symposium on Quality
                 Electronic Design (ISQED)}",
  title =        "Polynomial Formal Verification of a Processor: a
                 {RISC-V} Case Study",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--7",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISQED57927.2023.10129397",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Wen:2023:WCP,
  author =       "Elliott Wen and Gerald Weber and Suranga Nanayakkara",
  title =        "{WasmAndroid}: a Cross-Platform Runtime for Native
                 Programming Languages on {Android}",
  journal =      j-TECS,
  volume =       "22",
  number =       "1",
  pages =        "4:1--4:??",
  month =        jan,
  year =         "2023",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/3530286",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Sat Mar 11 08:39:25 MST 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/tecs.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3530286",
  abstract =     "Open source hardware such as RISC-V has been gaining
                 substantial momentum. Recently, they have begun to
                 embrace Google's Android operating system to leverage
                 its software ecosystem. Despite the encouraging
                 progress, a challenging issue arises: a majority
                 \ldots{}",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "https://dl.acm.org/loi/tecs",
}

@Article{Wilson:2023:NRT,
  author =       "Andrew E. Wilson and Michael Wirthlin and Nathan G.
                 Baker",
  title =        "Neutron Radiation Testing of {RISC-V TMR} Soft
                 Processors on {SRAM}-Based {FPGAs}",
  journal =      j-IEEE-TRANS-NUCL-SCI,
  volume =       "70",
  number =       "4",
  pages =        "603--610",
  year =         "2023",
  CODEN =        "IRNSAM",
  DOI =          "https://doi.org/10.1109/TNS.2023.3235582",
  ISSN =         "0018-9499 (print), 1558-1578 (electronic)",
  ISSN-L =       "0018-9499",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Nuclear Science",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=23",
}

@InProceedings{Wu:2023:DRV,
  author =       "Fan Wu and Junyang Tian and Guoyan Yang and Haitao Gui
                 and Yuteng Luo",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 6th Information
                 Technology,Networking,Electronic and Automation Control
                 Conference (ITNEC)}",
  title =        "Design of {RISC-V} heterogeneous multi-core {SOC}
                 architecture for edge computing for power
                 applications",
  volume =       "6",
  number =       "",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "701--708",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ITNEC56291.2023.10082372",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Wu:2023:ERR,
  author =       "Bing-Chen Wu and Wei-Ting Chen and Tsung-Te Liu",
  title =        "An Error-Resilient {RISC-V} Microprocessor With a
                 Fully Integrated {DC--DC} Voltage Regulator for
                 Near-Threshold Operation in 28-nm {CMOS}",
  journal =      j-IEEE-J-SOLID-STATE-CIRCUITS,
  volume =       "58",
  number =       "11",
  pages =        "3275--3285",
  year =         "2023",
  CODEN =        "IJSCBC",
  DOI =          "https://doi.org/10.1109/JSSC.2023.3287360",
  ISSN =         "0018-9200 (print), 1558-173X (electronic)",
  ISSN-L =       "0018-9200",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Journal of Solid-State Circuits",
}

@InProceedings{Wu:2023:SVR,
  author =       "Lingjuan Wu and Yifei Gao and Jiacheng Zhu and Yu Tai
                 and Wei Hu",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 32nd Asian Test Symposium (ATS)}",
  title =        "Security Verification of {RISC-V} System Based on
                 {ISA} Level Information Flow Tracking",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ATS59501.2023.10317944",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Xiang:2023:RRV,
  author =       "Mufan Xiang and Yongjian Li and Yongxin Zhao",
  editor =       "{IEEE}",
  booktitle =    "{2023 International Symposium of Electronics Design
                 Automation (ISEDA)}",
  title =        "{RVFC}: {RISC-V} Formal in {Chisel}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "162--167",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ISEDA59274.2023.10218484",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Xu:2023:TDH,
  author =       "Yinan Xu and Zihao Yu and Dan Tang and Ye Cai and
                 Dandan Huan and Wei He and Ninghui Sun and Yungang
                 Bao",
  title =        "Toward Developing High-Performance {RISC-V} Processors
                 Using Agile Methodology",
  journal =      j-IEEE-MICRO,
  volume =       "43",
  number =       "4",
  pages =        "98--106",
  month =        jul # "\slash " # aug,
  year =         "2023",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2023.3273562",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeemicro.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40",
}

@InProceedings{Yandrapati:2023:DIRa,
  author =       "Amar Babu Yandrapati and Reshma Sri Bhuma and Siva
                 Koteswara Rao Ragineedu and Khamar Alfaz Shaik and
                 Bannu Gudise",
  editor =       "{IEEE}",
  booktitle =    "{2023 8th International Conference on Communication
                 and Electronics Systems (ICCES)}",
  title =        "Design and Implementation of {RISC-V} based Smart
                 Insulin Pump",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "133--138",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICCES57224.2023.10192663",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Yandrapati:2023:DIRb,
  author =       "Amar Babu Yandrapati and Susanka Nilagiri and Hari
                 Krishna Yakkanti and Pallavi Domathoti",
  editor =       "{IEEE}",
  booktitle =    "{2023 8th International Conference on Communication
                 and Electronics Systems (ICCES)}",
  title =        "Design and Implementation of {RISC-V} based
                 Pacemaker",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "123--127",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICCES57224.2023.10192752",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Yang:2023:ATF,
  author =       "Chun-Chieh Yang and Yi-Ru Chen and Hui-Hsin Liao and
                 Yuan-Ming Chang and Jenq-Kuen Lee",
  title =        "Auto-tuning Fixed-point Precision with {TVM} on
                 {RISC-V} Packed {SIMD} Extension",
  journal =      j-TODAES,
  volume =       "28",
  number =       "3",
  pages =        "33:1--33:??",
  month =        may,
  year =         "2023",
  CODEN =        "ATASFO",
  DOI =          "https://doi.org/10.1145/3569939",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Wed May 17 08:06:20 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/todaes.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3569939",
  abstract =     "Today, as deep learning (DL) is applied more often in
                 daily life, dedicated processors such as CPUs and GPUs
                 have become very important for accelerating model
                 executions. With the growth of technology, people are
                 becoming accustomed to using edge devices, such as
                 mobile phones, smart watches, and VR devices in their
                 daily lives. A variety of technologies using DL are
                 gradually being applied to these edge devices. However,
                 there is a large number of computations in DL. It faces
                 a challenging problem how to provide solutions in the
                 edge devices. In this article, the proposed method
                 enables a flow with the RISC-V Packed extension (P
                 extension) in TVM. TVM, an open deep learning compiler
                 for neural network models, is growing as a key
                 infrastructure for DL computing. RISC-V is an open
                 instruction set architecture (ISA) with customized and
                 flexible features. The Packed-SIMD extension is a
                 RISC-V extension that enables subword
                 single-instruction multiple-data (SIMD) computations in
                 RISC-V architectures to support fallback engines in AI
                 computing. In the proposed flow, a fixed-point type
                 that is supported by an integer of 16-bit type and
                 saturation instructions is added to replace the
                 original 32-bit float type. In addition, an auto-tuning
                 method is proposed to use a uniform selector mechanism
                 (USM) to find the binary point position for fixed-point
                 type use. The tensorization feature of TVM can be used
                 to optimize specific hardware such as subword SIMD
                 instructions with RISC-V P extension. With our
                 experiment on the Spike simulator, the proposed method
                 with the USM can improve performance by approximately
                 2.54 to 6.15$ \times $ in terms of instruction counts
                 with little accuracy loss.",
  acknowledgement = ack-nhfb,
  articleno =    "33",
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems",
  journal-URL =  "https://dl.acm.org/loi/todaes",
}

@InProceedings{Yen:2023:FDR,
  author =       "Mao-Hsu Yen and Tzu-Feng Lin and Cheng-Hao Tsou and
                 Yan-Wei Yu and Yih-Hsia Lin and Yuan-Fu Ku and
                 Chien-Ting Kao",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 6th International Conference on Knowledge
                 Innovation and Invention (ICKII)}",
  title =        "{FPGA} Design of {RISC-V MCU} Collaborative Industrial
                 Printer Control System",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "142--146",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICKII58656.2023.10332790",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Yen:2023:VIR,
  author =       "Mao-Hsu Yen and Cheng-Hao Tsou and Tzu-Feng Lin and
                 Yih-Hsia Lin and Yuan-Fu Ku and Chien-Ting Kao",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 6th International Conference on Knowledge
                 Innovation and Invention (ICKII)}",
  title =        "{VLSI} Implementation of {RISC-V MCU} with a variable
                 stage pipeline",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "161--165",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICKII58656.2023.10332786",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zgheib:2023:CCI,
  author =       "Anthony Zgheib and Olivier Potin and Jean-Baptiste
                 Rigaud and Jean-Max Dutertre",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Symposium on Hardware
                 Oriented Security and Trust (HOST)}",
  title =        "{CIFER}: Code Integrity and control Flow verification
                 for programs Executed on a {RISC-V} core",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "100--110",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/HOST55118.2023.10133542",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Zhai:2023:MCR,
  author =       "Jianwang Zhai and Chen Bai and Binwu Zhu and Yici Cai
                 and Qiang Zhou and Bei Yu",
  title =        "{McPAT-Calib}: a {RISC-V BOOM} Microarchitecture Power
                 Modeling Framework",
  journal =      j-IEEE-TRANS-CAD-ICS,
  volume =       "42",
  number =       "1",
  pages =        "243--256",
  year =         "2023",
  CODEN =        "ITCSDI",
  DOI =          "https://doi.org/10.1109/TCAD.2022.3169464",
  ISSN =         "0278-0070 (print), 1937-4151 (electronic)",
  ISSN-L =       "0278-0070",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Computer-Aided Design of
                 Integrated Circuits and Systems",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43",
}

@InProceedings{Zhang:2023:DMC,
  author =       "Zheng Zhang and Bo Gao and Min Gong",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 5th International Conference on Civil
                 Aviation Safety and Information Technology (ICCASIT)}",
  title =        "Design of the Main Control {RISC-V} Processor in
                 Chiplet Applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1419--1424",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICCASIT58768.2023.10351511",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Zhang:2023:ESH,
  author =       "Chengbo Zhang and Peiyong Zhang and Shengrui Zheng and
                 Zhao Yang and Rui Liu and Kaitian Huang",
  title =        "An Efficient Self-Healing Architecture for Improving
                 the {RAS} Characteristics of {RISC-V} Server and Its
                 Quantitative Evaluation Method",
  journal =      "IEEE Embedded Systems Letters",
  volume =       "15",
  number =       "1",
  pages =        "41--44",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/LES.2022.3194031",
  ISSN =         "1943-0663 (print), 1943-0671 (electronic)",
  ISSN-L =       "1943-0663",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhang:2023:SDD,
  author =       "Bin Zhang and Ye Cai and Zhiheng He and Sen Liang and
                 Wei He",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE International Test Conference in Asia
                 (ITC-Asia)}",
  title =        "Structured {DFT} Development Approach for
                 {Chisel}-Based High Performance {RISC-V} Processors",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ITC-Asia58802.2023.10301174",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhao:2023:ERV,
  author =       "Yifan Zhao and Honglin Kuang and Yi Sun and Zhen Yang
                 and Chen Chen and Jianyi Meng and Jun Han",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 34th International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP)}",
  title =        "Enhancing {RISC-V} Vector Extension for Efficient
                 Application of Post-Quantum Cryptography",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "10--17",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ASAP57973.2023.00014",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Zhao:2023:NTF,
  author =       "Yuankang Zhao and Salim Ullah and Siva Satyendra Sahoo
                 and Akash Kumar",
  title =        "{NvMISC}: Toward an {FPGA}-Based Emulation Platform
                 for {RISC-V} and Nonvolatile Memories",
  journal =      "IEEE Embedded Systems Letters",
  volume =       "15",
  number =       "4",
  pages =        "170--173",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/LES.2023.3299202",
  ISSN =         "1943-0663 (print), 1943-0671 (electronic)",
  ISSN-L =       "1943-0663",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Zheng:2023:HSC,
  author =       "Xin Zheng and Junwei Wu and Xian Lin and Huaien Gao
                 and Suting Cai and Xiaoming Xiong",
  title =        "Hardware\slash Software Co-Design of Cryptographic
                 {SoC} Based on {RISC-V} Virtual Prototype",
  journal =      j-IEEE-TRANS-CIRCUITS-SYST-II-EXPRESS-BRIEFS,
  volume =       "70",
  number =       "9",
  pages =        "3624--3628",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/TCSII.2023.3267186",
  ISSN =         "1549-7747 (print), 1558-3791 (electronic)",
  ISSN-L =       "1549-7747",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Circuits and Systems II: Express
                 Briefs",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/issues?punumber=8920",
}

@InProceedings{Zhong:2023:RVB,
  author =       "Xinchao Zhong and Chiu-Wing Sham",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 12th Global Conference on Consumer
                 Electronics (GCCE)}",
  title =        "A {RISC-V} Based {SoC} with Configurable {CPK} Sensor
                 Interface for {ECU} on Motorcycle",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "321--322",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/GCCE59613.2023.10315543",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zhou:2023:RVB,
  author =       "Haoxiang Zhou and Haiqiao Hong and Dingbang Liu and
                 Hang Liu and Yu Xia and Kai Li and Jun Liu and Shaobo
                 Luo and Wei Mao and Hao Yu",
  editor =       "{IEEE}",
  booktitle =    "{2023 IEEE 5th International Conference on Artificial
                 Intelligence Circuits and Systems (AICAS)}",
  title =        "{RISC-V} based Fully-Parallel {SRAM}
                 Computing-in-Memory Accelerator with High Hardware
                 Utilization and Data Reuse Rate",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--5",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/AICAS57966.2023.10168630",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@InProceedings{Zou:2023:ABR,
  author =       "Xiaofeng Zou and Yuanxi Peng and Tuo Li and Lingjun
                 Kong and Zhaochun Pang and Lu Zhang",
  editor =       "{IEEE}",
  booktitle =    "{2023 2nd International Conference on Computing,
                 Communication, Perception and Quantum Technology
                 (CCPQT)}",
  title =        "Accelerating {Blake3} in {RISC-V}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "296--301",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/CCPQT60491.2023.00057",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/hash.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Blake3 hash algorithm",
}

@InProceedings{Zuo:2023:FBM,
  author =       "Sheng Zuo and Huan Chang",
  editor =       "{IEEE}",
  booktitle =    "{2023 3rd International Conference on Frontiers of
                 Electronics, Information and Computation Technologies
                 (ICFEICT)}",
  title =        "{FPGA} Based Memory Security and Error Correction
                 System for {RISC-V} Processor",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "253--259",
  year =         "2023",
  DOI =          "https://doi.org/10.1109/ICFEICT59519.2023.00051",
  bibdate =      "Sat Dec 16 15:51:40 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
}

@Article{Bai:2024:BER,
  author =       "Chen Bai and Qi Sun and Jianwang Zhai and Yuzhe Ma and
                 Bei Yu and Martin D. F. Wong",
  title =        "{BOOM-Explorer}: {RISC-V} {BOOM} Microarchitecture
                 Design Space Exploration",
  journal =      j-TODAES,
  volume =       "29",
  number =       "1",
  pages =        "20:1--20:??",
  month =        jan,
  year =         "2024",
  CODEN =        "ATASFO",
  DOI =          "https://doi.org/10.1145/3630013",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Mon Jan 15 11:14:18 MST 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/risc-v.bib;
                 https://www.math.utah.edu/pub/tex/bib/todaes.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3630013",
  abstract =     "Microarchitecture parameters tuning is critical in the
                 microprocessor design cycle. It is a non-trivial design
                 space exploration (DSE) problem due to the large
                 solution space, cycle-accurate simulators' modeling
                 inaccuracy, and high simulation runtime for performance
                 evaluations. Previous methods require massive expert
                 efforts to construct interpretable equations or high
                 computing resource demands to train black-box
                 prediction models. This article follows the black-box
                 methods due to better solution qualities than
                 analytical methods in general. We summarize two learned
                 lessons and propose BOOM-Explorer accordingly. First,
                 embedding microarchitecture domain knowledge in the DSE
                 improves the solution quality. Second, BOOM-Explorer
                 makes the microarchitecture DSE for
                 register-transfer-level designs within the limited time
                 budget feasible. We enhance BOOM-Explorer with the
                 diversity-guidance, further improving the algorithm
                 performance. Experimental results with RISC-V
                 Berkeley-Out-of-Order Machine under 7-nm technology
                 show that our proposed methodology achieves an average
                 of 18.75\% higher Pareto hypervolume, 35.47\% less
                 average distance to reference set, and 65.38\% less
                 overall running time compared to previous approaches.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Transact. Des. Automat. Electron. Syst.",
  articleno =    "20",
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems",
  journal-URL =  "https://dl.acm.org/loi/todaes",
}

@Article{Brohet:2024:STM,
  author =       "Marco Brohet and Francesco Regazzoni",
  title =        "A Survey on Thwarting Memory Corruption in {RISC-V}",
  journal =      j-COMP-SURV,
  volume =       "56",
  number =       "2",
  pages =        "28:1--28:??",
  month =        feb,
  year =         "2024",
  CODEN =        "CMSVAN",
  DOI =          "https://doi.org/10.1145/3604906",
  ISSN =         "0360-0300 (print), 1557-7341 (electronic)",
  ISSN-L =       "0360-0300",
  bibdate =      "Wed Oct 4 09:27:39 MDT 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compsurv.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "https://dl.acm.org/doi/10.1145/3604906",
  abstract =     "With embedded devices becoming more pervasive and
                 entrenched in society, it is paramount to keep these
                 systems secure. A threat plaguing these systems
                 consists of software vulnerabilities that cause memory
                 corruption, potentially allowing an attacker to breach
                 the device. Software-based countermeasures exist, but
                 suffer from high overhead. In this survey, we
                 investigate whether this could be mitigated using
                 dedicated hardware. Driven by the advancements of open
                 hardware, we focus on implementations for RISC-V, a
                 novel and open architecture tailored for customization.
                 We distinguish between methods validating memory
                 accesses beforehand, obfuscating information necessary
                 for an attack, and detecting memory values corrupted
                 earlier. We compare on qualitative metrics, such as the
                 security coverage and level of transparency, and
                 performance in both software and hardware. Although
                 current implementations do not easily allow for a fair
                 comparison as their evaluation methodologies vary
                 widely, we show that current implementations are
                 suitable to minimize the runtime overhead with a
                 relatively small area overhead. Nevertheless, we
                 identified that further research is still required to
                 mitigate more fine-grained attacks such as intra-object
                 overflows, to integrate into more sophisticated
                 protected execution environments towards resilient
                 systems that are automatically recoverable, and to move
                 towards more harmonized evaluation.",
  acknowledgement = ack-nhfb,
  ajournal =     "ACM Comput. Surv.",
  articleno =    "28",
  fjournal =     "ACM Computing Surveys",
  journal-URL =  "https://dl.acm.org/loi/csur",
}

@Article{Chen:2024:RVC,
  author =       "Yuxing Chen and Xinrui Wang and Suwen Song and Lang
                 Feng and Zhongfeng Wang",
  title =        "{RISC-V} Custom Instructions of Elementary Functions
                 for {IoT} Endpoint Devices",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "73",
  number =       "2",
  pages =        "523--535",
  month =        feb,
  year =         "2024",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3336174",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Feb 16 07:37:44 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "custom instructions; elementary function; Hardware;
                 Internet of Things; IP networks; ISA; Mathematical
                 models; RISC-V; Robot kinematics; Task analysis;
                 versatility; Wearable computers",
}

@Article{Harris:2024:UDS,
  author =       "David Harris and James Stine and Milo Ercegovac and
                 Alberto Nannarelli and Katherine Parry and Cedar
                 Turek",
  title =        "Unified Digit Selection for Radix-4 Recurrence
                 Division and Square Root",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "73",
  number =       "1",
  pages =        "292--300",
  month =        jan,
  year =         "2024",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3305760",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Dec 27 15:37:27 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "division; square root; SRT; minimally-redundant radix-4; RISC-V",
}

@Article{Hepola:2024:EEE,
  author =       "Kari Hepola and Joonas Multanen and Pekka
                 J{\"a}{\"a}skel{\"a}inen",
  title =        "Energy-Efficient Exposed Datapath Architecture With a
                 {RISC-V} Instruction Set Mode",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "73",
  number =       "2",
  pages =        "560--573",
  month =        feb,
  year =         "2024",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2023.3337313",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Feb 16 07:37:44 2024",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2020.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Codes; Computer architecture; Exposed datapath;
                 instruction level parallelism; Instruction sets;
                 multi-instruction-set architecture; Programming;
                 Reduced instruction set computing; Registers; transport
                 triggered architecture; VLIW",
}

%%% ====================================================================
%%% Cross-referenced entries must come last:
@Proceedings{Burgess:2017:ISC,
  editor =       "Neil Burgess and Javier Bruguera and Florent de
                 Dinechin",
  booktitle =    "{24th IEEE Symposium on Computer Arithmetic (ARITH
                 24), London, UK, 24--26 July 2017}",
  title =        "{2017 IEEE 24th Symposium on Computer Arithmetic
                 (ARITH 24), London, UK, 24--26 July 2017}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "xii + 198",
  year =         "2017",
  ISBN =         "1-5386-1966-0 (print), 1-5386-1965-2, 1-5386-1964-4",
  ISBN-13 =      "978-1-5386-1966-7 (print), 978-1-5386-1965-0,
                 978-1-5386-1964-3",
  ISSN =         "1063-6889",
  LCCN =         "QA76.9.C62 S95 2017",
  bibdate =      "Fri Nov 17 10:14:11 2017",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/gnu.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  URL =          "http://ieeexplore.ieee.org/servlet/opac?punumber=8019911",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-24; computer arithmetic units; correctness
                 proofs; cryptography; domain specific designs; error
                 analysis; exascale computing; floating point
                 arithmetic; floating-point error analysis; formal
                 verification; function approximation; modular
                 arithmetic; theorem proving; verification",
}

@Proceedings{Gustafson:2019:PCN,
  editor =       "John Gustafson and Vassil Dimitrov",
  booktitle =    "{Proceedings of the Conference for Next Generation
                 Arithmetic 2019, Singapore, March 2019}",
  title =        "{Proceedings of the Conference for Next Generation
                 Arithmetic 2019, Singapore, March 2019}",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "66",
  year =         "2019",
  ISBN =         "1-4503-7139-6",
  ISBN-13 =      "978-1-4503-7139-1",
  LCCN =         "????",
  bibdate =      "Mon Feb 10 12:06:51 MST 2020",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  series =       "ICPS",
  acknowledgement = ack-nhfb,
  meetingname =  "Conference for Next Generation Arithmetic (2019:
                 Singapore)",
  subject =      "Computer arithmetic; Congresses; Computer algorithms;
                 Computer algorithms.; Computer arithmetic.",
}

@Proceedings{Takagi:2019:ISC,
  editor =       "Naofumi Takagi and Sylvie Boldo and Martin
                 Langhammer",
  booktitle =    "{2019 IEEE 26th Symposium on Computer Arithmetic
                 ARITH-26 (2019), Kyoto, Japan, 10--12 June 2019}",
  title =        "{2019 IEEE 26th Symposium on Computer Arithmetic
                 ARITH-26 (2019), Kyoto, Japan, 10--12 June 2019}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "15 + 220",
  month =        jun,
  year =         "2019",
  DOI =          "https://doi.org/10.1109/ARITH.2019.00001",
  ISBN =         "1-72813-366-1",
  ISBN-13 =      "978-1-72813-366-9",
  ISSN =         "1063-6889",
  ISSN-L =       "1063-6889",
  bibdate =      "Fri Jan 31 08:18:07 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  abstract =     "Presents the title page of the proceedings record.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-26",
}

@Proceedings{IEEE:2021:ISC,
  editor =       "{IEEE}",
  booktitle =    "{2021 IEEE 28th Symposium on Computer Arithmetic:
                 ARITH 2021: virtual conference, 14--16 June 2021:
                 proceedings}",
  title =        "{2021 IEEE 28th Symposium on Computer Arithmetic:
                 ARITH 2021: virtual conference, 14--16 June 2021:
                 proceedings}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "????",
  year =         "2021",
  DOI =          "https://doi.org/10.1109/ARITH51176.2021",
  ISBN =         "1-66542-293-9 (print), 1-66544-648-X (e-book)",
  ISBN-13 =      "978-1-66542-293-2 (print), 978-1-66544-648-8
                 (e-book)",
  LCCN =         "????",
  bibdate =      "Thu Sep 21 10:36:52 MDT 2023",
  bibsource =    "fsz3950.oclc.org:210/WorldCat;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransemergtopcomput.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-28",
  meetingname =  "IEEE International Symposium on Computer Arithmetic
                 28. 2021",
  remark =       "The 28th IEEE Symposium on Computer Arithmetic ---
                 ARITH 2021 --- originally scheduled in Turin, Italy, is
                 held in June 2021 as a virtual conference due to the
                 uncertainty of the world health and travel situation.",
}

@Proceedings{IEEE:2022:ISC,
  editor =       "{IEEE}",
  booktitle =    "{2022 IEEE 29th Symposium on Computer Arithmetic:
                 ARITH 2022: virtual conference, 12--14 September 2022:
                 proceedings}",
  title =        "{2022 IEEE 29th Symposium on Computer Arithmetic:
                 ARITH 2022: virtual conference, 12--14 September 2022:
                 proceedings}",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "????",
  year =         "2022",
  DOI =          "https://doi.org/10.1109/ARITH54963.2022",
  ISBN =         "1-66547-827-6, 1-66547-828-4",
  ISBN-13 =      "978-1-66547-827-4, 978-1-66547-828-1",
  LCCN =         "????",
  bibdate =      "Thu Sep 21 10:14:25 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/risc-v.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-29",
  meetingname =  "IEEE Symposium on Computer Arithmetic 29. 2022",
}