%%% -*-BibTeX-*-
%%% ====================================================================
%%%  BibTeX-file{
%%%     author          = "Nelson H. F. Beebe",
%%%     version         = "1.56",
%%%     date            = "03 January 2024",
%%%     time            = "10:05:03 MST",
%%%     filename        = "sigarch.bib",
%%%     address         = "University of Utah
%%%                        Department of Mathematics, 110 LCB
%%%                        155 S 1400 E RM 233
%%%                        Salt Lake City, UT 84112-0090
%%%                        USA",
%%%     telephone       = "+1 801 581 5254",
%%%     FAX             = "+1 801 581 4148",
%%%     URL             = "https://www.math.utah.edu/~beebe",
%%%     checksum        = "40163 99934 479202 4536439",
%%%     email           = "beebe at math.utah.edu, beebe at acm.org,
%%%                        beebe at computer.org (Internet)",
%%%     codetable       = "ISO/ASCII",
%%%     keywords        = "bibliography; BibTeX; Computer Architecture
%%%                        News; International Symposium on Computer
%%%                        Architecture (ISCA); SIGARCH",
%%%     license         = "public domain",
%%%     supported       = "yes",
%%%     docstring       = "This is an almost complete BibTeX
%%%                        bibliography for ACM SIGARCH Computer
%%%                        Architecture News (CODEN CANED2, ISSN
%%%                        0163-5964 (print), 1943-5851 (electronic)),
%%%                        which began publishing with volume 1, issue
%%%                        1, in January 1972.  The journal appears four
%%%                        to nine times a year, with five annual issues
%%%                        in recent years.  Publication ceased with
%%%                        volume 45, number 2, in May 2017.
%%%
%%%                        The incompleteness is due to holes in the ACM
%%%                        Portal Database: there are at least 8 issues
%%%                        for which no entry at all is present, or
%%%                        there is an issue Web page, but its contents
%%%                        are empty.  The missing issues are:
%%%
%%%                            Volume  1 number 1 1972
%%%                            Volume  1 number 3 1972
%%%                            Volume  2 number 2 1973
%%%                            Volume  5 number 3 1976
%%%                            Volume  5 number 5 1976
%%%                            Volume  8 number 1 1980
%%%                            Volume  9 number 3 1981
%%%                            Volume 36 number 6 2008
%%%
%%%                        The journal has World-Wide Web sites at
%%%
%%%                            https://dl.acm.org/newsletter/sigarch
%%%                            http://www.acm.org/sigarch/
%%%                            http://www.cs.wisc.edu/~arch/www/
%%%
%%%                        with tables of contents at
%%%
%%%                            https://dl.acm.org/loi/sigarch
%%%
%%%                        Some of the ISCA Conferences are jointly
%%%                        sponsored by the ACM and the IEEE, and also
%%%                        appear as an issue of Computer Architecture
%%%                        News. The first ISCA Conference was held in
%%%                        1973.  Tables of contents of the proceedings
%%%                        volumes, and pointers to online article text,
%%%                        may be available at
%%%
%%%                            http://portal.acm.org/browse_dl.cfm?idx=SERIES416
%%%                            http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=30879&isYear=YYYY
%%%
%%%                        where YYYY is a four-digit year.
%%%
%%%                        At version 1.56, the year coverage looked
%%%                        like this:
%%%
%%%                             1972 (   8)    1988 ( 103)    2004 (  77)
%%%                             1973 (  35)    1989 ( 116)    2005 ( 115)
%%%                             1974 (  44)    1990 ( 114)    2006 (  99)
%%%                             1975 (   9)    1991 ( 119)    2007 (  97)
%%%                             1976 (  53)    1992 (  87)    2008 (  90)
%%%                             1977 (  56)    1993 (  64)    2009 (  91)
%%%                             1978 (  33)    1994 (  70)    2010 ( 104)
%%%                             1979 (  16)    1995 (  59)    2011 ( 108)
%%%                             1980 (  67)    1996 (  51)    2012 ( 113)
%%%                             1981 (  18)    1997 (  51)    2013 ( 132)
%%%                             1982 (  81)    1998 ( 129)    2014 ( 120)
%%%                             1983 (  74)    1999 (  54)    2015 (  69)
%%%                             1984 (  60)    2000 (  69)    2016 ( 135)
%%%                             1985 (  67)    2001 (  56)    2017 ( 112)
%%%                             1986 (  66)    2002 (  69)
%%%                             1987 (  87)    2003 (  63)
%%%
%%%                             Article:       3395
%%%                             Book:             1
%%%                             InProceedings:   82
%%%                             Proceedings:     32
%%%
%%%                             Total entries: 3510
%%%
%%%                        This bibliography was constructed primarily
%%%                        from data in the ACM Portal database, and
%%%                        from several on-line library catalogs. The
%%%                        ACM Portal database lacks data for these
%%%                        volume(issue number) pairs: 1(1), 1(3), 2(2),
%%%                        5(3), 5(5), 8(1), 9(3), 36(6), 37(1), and
%%%                        41(1).
%%%
%%%                        Numerous errors in the sources noted above
%%%                        have been corrected.  Spelling has been
%%%                        verified with the UNIX spell and GNU ispell
%%%                        programs using the exception dictionary
%%%                        stored in the companion file with extension
%%%                        .sok.
%%%
%%%                        BibTeX citation tags are uniformly chosen as
%%%                        name:year:abbrev, where name is the family
%%%                        name of the first author or editor, year is a
%%%                        4-digit number, and abbrev is a 3-letter
%%%                        condensation of important title words.
%%%                        Citation labels were automatically generated
%%%                        by software developed for the BibNet Project.
%%%
%%%                        In this bibliography, entries are sorted in
%%%                        publication order, with the help of
%%%                        ``bibsort -byvolume''.  The bibsort utility
%%%                        is available from
%%%
%%%                            https://www.math.utah.edu/pub/bibsort
%%%                            ftp://ftp.math.utah.edu/pub/bibsort
%%%
%%%                        The checksum field above contains a CRC-16
%%%                        checksum as the first value, followed by the
%%%                        equivalent of the standard UNIX wc (word
%%%                        count) utility output of lines, words, and
%%%                        characters.  This is produced by Robert
%%%                        Solovay's checksum utility.",
%%%  }
%%% ====================================================================

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%%% ====================================================================
%%% Acknowledgement abbreviations:

@String{ack-nhfb = "Nelson H. F. Beebe,
                    University of Utah,
                    Department of Mathematics, 110 LCB,
                    155 S 1400 E RM 233,
                    Salt Lake City, UT 84112-0090, USA,
                    Tel: +1 801 581 5254,
                    FAX: +1 801 581 4148,
                    e-mail: \path|beebe@math.utah.edu|,
                            \path|beebe@acm.org|,
                            \path|beebe@computer.org| (Internet),
                    URL: \path|https://www.math.utah.edu/~beebe/|"}

%%% ====================================================================
%%% Journal abbreviations:

@String{j-COMP-ARCH-NEWS = "ACM SIGARCH Computer Architecture News"}

%%% ====================================================================
%%% Publishers and their addresses:

@String{pub-ACM                 = "ACM Press"}
@String{pub-ACM:adr             = "New York, NY 10036, USA"}

@String{pub-IEEE                = "IEEE Computer Society Press"}
@String{pub-IEEE:adr            = "1109 Spring Street, Suite 300,
                                  Silver Spring, MD 20910, USA"}

@String{pub-MORGAN-KAUFMANN     = "Morgan Kaufmann Publishers"}
@String{pub-MORGAN-KAUFMANN:adrsf = "San Francisco, CA, USA"}

%%% ====================================================================
%%% Bibliography entries, in publication order:

%%% TO DO: [04-Sep-2014] Volume 1 number 1: no data yet in ACM Portal database

@Article{Foster:1972:RDM,
  author =       "Caxton C. Foster",
  title =        "A review of dynamic memories with enhanced data access
                 by {Harold S. Stone. IEEETC Vol. C-21, \#4, p 359--386,
                 April 1972}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "1",
  number =       "2",
  pages =        "3--7",
  month =        apr,
  year =         "1972",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:38 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bataille:1972:SOG,
  author =       "M. Bataille",
  title =        "Something old: the {Gamma 60} the computer that was
                 ahead of its time",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "1",
  number =       "2",
  pages =        "10--15",
  month =        apr,
  year =         "1972",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:38 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Foster:1972:SNI,
  author =       "Caxton C. Foster",
  title =        "Something new: the {Intel MCS-4} micro computer set",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "1",
  number =       "2",
  pages =        "16--17",
  month =        apr,
  year =         "1972",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:38 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1972:MNC,
  author =       "J. A. N. Lee",
  title =        "My next compiler",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "1",
  number =       "2",
  pages =        "17--19",
  month =        apr,
  year =         "1972",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:38 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Flynn:1972:CAJ,
  author =       "Michael J. Flynn and Mrs. Carol Rogers",
  title =        "Computer architecture at {Johns Hopkins}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "1",
  number =       "2",
  pages =        "21--33",
  month =        apr,
  year =         "1972",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:38 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

%%% TO DO: [04-Sep-2014] Volume 1 number 3: no data yet in ACM Portal database

@Article{Vaughan:1972:CAS,
  author =       "R. F. Vaughan and R. A. Collins",
  title =        "On computer architecture, software portability \&
                 microprogramming",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "1",
  number =       "4",
  pages =        "14--15",
  month =        oct,
  year =         "1972",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Brakefield:1972:OFP,
  author =       "James C. Brakefield",
  title =        "An optimal floating point format",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "1",
  number =       "4",
  pages =        "16--17",
  month =        oct,
  year =         "1972",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Brewer:1972:RDD,
  author =       "J. E. Brewer",
  title =        "Recent doctoral dissertations of interest to
                 {SIGARCH}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "1",
  number =       "4",
  pages =        "18--20",
  month =        oct,
  year =         "1972",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bettcher:1973:TSR,
  author =       "C. W. Bettcher",
  title =        "Thread standardization and relative cost",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "1",
  pages =        "9--9",
  month =        jan,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:28 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "This is a reprint of an article published in the {\em
                 Journal of the Society of Automotive Engineers}, Volume
                 XVIII, Number 2, p. 131, February 1926, about the cost
                 of the lack of standardization of screw threads. {\em
                 Computer Architecture News\/} Editor-in-Chief Caxton C.
                 Foster has added a hand-written note ``of course, there
                 is no message here for {\em us}.''",
}

@Article{Sites:1973:FPS,
  author =       "Richard L. Sites",
  title =        "Floating point significance interrupt proposal",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "1",
  pages =        "10--12",
  month =        jan,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:28 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The purpose of this proposal is to aid numerical
                 analysts in observing the significance of results in
                 floating-point calculations. This proposal is not a
                 cure-all, but it does attempt to a first, high-payoff
                 step in understanding and analyzing floating-point
                 algorithms. This proposal is specifically for IBM
                 360/370 architecture, but the ideas are applicable to
                 all machines.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "The author observes that register clearing by
                 subtraction is common, and is one of the reasons that
                 ``all IBM language processors execute with significance
                 masked off.'' He proposes suppressing the significance
                 interrupt in subtractions when both operands are
                 equal.",
}

@Article{Foster:1973:CA,
  author =       "Caxton Foster",
  title =        "Computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "1",
  pages =        "13--18",
  month =        jan,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:28 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

%%% TO DO: [04-Sep-2014] Volume 2 number 2: no data yet in ACM Portal database

@Article{Adler:1973:MCC,
  author =       "Louis S. Adler",
  title =        "A mini-computer configuration for {CAI}: a systems
                 engineering view",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "3",
  pages =        "10--19",
  month =        oct,
  year =         "1973",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1216456.1216457",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jul 6 14:31:17 MDT 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Computer assisted instruction (CAI) has not impacted
                 the educational world with the degree of success which
                 early proponents predicted. Although CAI has proven to
                 be a more efficient learning tool than common
                 traditional methods in specific instances, the overall
                 success of such systems has been sporadic. There is no
                 question that a well-designed and correctly implemented
                 CAI system can be highly effective; however, several
                 important factors must be overcome to guarantee a
                 reasonable amount of success. These are:\par

                 * Overcoming the present high cost of hardware while
                 still providing a reliable system having acceptable
                 display capability.\par

                 * Developing a software real-time operating system
                 which guarantees fast response times.\par

                 * Authoring high quality courseware.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gentleman:1973:TC,
  author =       "W. M. Gentleman and B. A. Wichmann",
  title =        "Timing on computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "3",
  pages =        "20--23",
  month =        oct,
  year =         "1973",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1216456.1216458",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jul 6 14:31:17 MDT 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  URL =          "ftp://ftp.math.utah.edu/pub/mirrors/ftp.ira.uka.de/bibliography/Misc/monitor.bib",
  abstract =     "Most computers today provide some form of clock which
                 can be read by software. The purpose of this note is to
                 illustrate why in many existing systems, the facilities
                 offered are inadequate for ordinary programmers.
                 Proposals are made for changes in both hardware and
                 software to remedy these deficiencies.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schank:1973:AAS,
  author =       "Karl Schank",
  title =        "Architectural assistance to software debugging aids",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "3",
  pages =        "37--38",
  month =        oct,
  year =         "1973",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1216456.1216459",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jul 6 14:31:17 MDT 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "It has been observed [1] that 45 to 50\% of
                 programming effort is spent in debugging, checkout and
                 testing, yet the architecture of most modern computer
                 systems does little if anything to facilitate ease of
                 debugging. In most batch systems the programmer is
                 sufficiently removed from the execution of his program
                 as to be severely handicapped in diagnosing errors.
                 There is only so much information that can be easily
                 obtained from a voluminous core dump, for instance.
                 Even programmers on large timesharing systems have
                 available at most an interactive software debugging
                 package which operates through a combination of
                 insertions and replacements of object code and
                 interpretation (rather than execution) of machine code.
                 This can get to be quite inefficient when carried to
                 the extreme and often is useful only if the program has
                 been processed by a special compiler.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bhandarkar:1973:MCM,
  author =       "Dileep P. Bhandarkar and Samuel H. Fuller",
  title =        "{Markov} chain models for analyzing memory
                 interference in multiprocessor computer systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "1--6",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anderson:1973:IDP,
  author =       "George A. Anderson",
  title =        "Interconnecting a distributed processor system for
                 avionics",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "11--16",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goke:1973:BNP,
  author =       "L. Rodney Goke and G. J. Lipovski",
  title =        "{Banyan} networks for partitioning multiprocessor
                 systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "21--28",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jordan:1973:SDS,
  author =       "Harry F. Jordan and Burton J. Smith",
  title =        "Structure of digital system description languages",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "31--34",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1973:VDS,
  author =       "John A. N. Lee",
  title =        "{VDL}---a definition system for all levels",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "41--48",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Radoy:1973:MPP,
  author =       "Charles H. Radoy and George P. {Copeland, Jr.} and G.
                 J. Lipovski",
  title =        "A methodology for parallel processing design
                 tradeoffs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "51--56",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reddaway:1973:DDA,
  author =       "S. F. Reddaway",
  title =        "{DAP}---a distributed array processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "61--65",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kogge:1973:MRP,
  author =       "Peter M. Kogge",
  title =        "Maximal rate pipelined solutions to recurrence
                 problems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "71--76",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Agerwala:1973:CCL,
  author =       "Tilak Agerwala and Mike Flynn",
  title =        "Comments on capabilities, limitations and
                 ``correctness'' of {Petri} nets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "81--86",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Omohundro:1973:FFC,
  author =       "Wayne E. Omohundro and James H. Tracey",
  title =        "{Flowware}---a flow charting procedure to describe
                 digital networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "91--97",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Barbacci:1973:AED,
  author =       "Mario R. Barbacci and Daniel P. Siewiorek",
  title =        "Automated exploration of the design space for register
                 transfer {(RT)} systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "101--106",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Laliotis:1973:IAS,
  author =       "T. A. Laliotis",
  title =        "Implementation aspects of the symbol hardware
                 compiler",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "111--115",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Copeland:1973:ACC,
  author =       "George P. {Copeland, Jr.} and G. J. Lipovski and
                 Stanley Y. W. Su",
  title =        "The architecture of {CASSM}: a cellular system for
                 non-numeric processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "121--128",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hemphill:1973:DDG,
  author =       "John M. Hemphill and S. A. Szygenda",
  title =        "Deriving design guidelines for diagnosable computer
                 systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "131--135",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Parhami:1973:DFT,
  author =       "Behrooz Parhami and Algirdas Avizienis",
  title =        "Design of fault-tolerant associative processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "141--145",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fischler:1973:FTM,
  author =       "M. A. Fischler and O. Firschein",
  title =        "A fault tolerant multiprocessor architecture for
                 real-time control applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "151--157",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lipovski:1973:VFS,
  author =       "G. J. Lipovski",
  title =        "A varistructured fail-soft cellular computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "161--165",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vaucher:1973:HLC,
  author =       "Jean Vaucher and Christian Rey",
  title =        "A hardware laboratory for computer architecture
                 research",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "171--175",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Knoke:1973:SEC,
  author =       "P. J. Knoke",
  title =        "Simulation exercises for computer architecture
                 education",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "181--185",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sloan:1973:CAC,
  author =       "M. E. Sloan",
  title =        "Computer architecture courses in electrical
                 engineering departments",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "191--195",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hartenstein:1973:IHC,
  author =       "R. Hartenstein",
  title =        "Increasing hardware complexity---a challenge to
                 computer architecture education",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "201--206",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rossmann:1973:RWC,
  author =       "George Rossmann",
  title =        "Review of the {{\em Workshop on Computer Architecture
                 Education}}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "211--214",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cooper:1973:MMB,
  author =       "Richard G. Cooper",
  title =        "{Micromodules}: Microprogrammable building blocks for
                 hardware development",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "221--226",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fuller:1973:CMA,
  author =       "S. H. Fuller and D. P. Siewiorek and R. J. Swan",
  title =        "Computer Modules: an architecture for large digital
                 modules",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "231--237",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zaks:1973:MAF,
  author =       "Rodnay Zaks",
  title =        "A microprogrammed architecture for front end
                 processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "241--246",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vranesic:1973:DFV,
  author =       "Z. G. Vranesic and V. C. Hamacher and Y. Y. Leung",
  title =        "Design of a fully variable-length structured
                 minicomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "251--255",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Marvel:1973:HHA,
  author =       "Orin E. Marvel",
  title =        "Happe {Honeywell Associative Parallel Processing
                 Ensemble}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "261--267",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schaffner:1973:CAP,
  author =       "Mario R. Schaffner",
  title =        "A computer architecture and its programming language",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "2",
  number =       "4",
  pages =        "271--277",
  month =        dec,
  year =         "1973",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shore:1974:CCa,
  author =       "John Shore",
  title =        "Conjecture corner",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "1",
  pages =        "3--6",
  month =        mar,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McKeeman:1974:CDE,
  author =       "W. M. McKeeman",
  title =        "Computer design evaluation using programming language
                 primitives",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "1",
  pages =        "7--18",
  month =        mar,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hartenstein:1974:LMI,
  author =       "Reiner W. Hartenstein",
  title =        "Letter to membership from incoming chairman {(CAN,
                 Oct. 73)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "1",
  pages =        "19--22",
  month =        mar,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stryker:1974:SSA,
  author =       "David Stryker and David Weiss",
  title =        "Secure system architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "2",
  pages =        "37--38",
  month =        jun,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Su:1974:BRL,
  author =       "Stephen Y. H. Su",
  title =        "Book review of {{\em Logic and Logic Design\/}} by {B.
                 Girling and H. G. Morning. International Textbook
                 Company Limited 1973}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "3",
  pages =        "2--3",
  month =        sep,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:02 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shore:1974:CCb,
  author =       "John Shore",
  title =        "Conjecture corner",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "3",
  pages =        "4--9",
  month =        sep,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:02 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nisnevich:1974:DPC,
  author =       "L. Nisnevich and E. Strasbourger",
  title =        "Decentralized priority control in data communication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "1--6",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reames:1974:LNS,
  author =       "Cecil C. Reames and Ming T. Liu",
  title =        "A loop network for simultaneous transmission of
                 variable-length messages",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "7--12",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Callan:1974:APS,
  author =       "James F. Callan",
  title =        "The architecture of the {Picture System}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "13--16",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "Evans \& Sutherland Picture System",
}

@Article{Staudhammer:1974:FDO,
  author =       "John Staudhammer and Jeffrey F. Eastman and James N.
                 England",
  title =        "A fast display-oriented processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "17--22",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Eastman:1974:CDC,
  author =       "Jeffrey F. Eastman and John Staudhammer",
  title =        "Computer display of colored three-dimensional
                 objects",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "23--27",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kerr:1974:MPI,
  author =       "Henry D. Kerr",
  title =        "A microprogrammed processor for interactive computer
                 graphics",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "28--33",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Armstrong:1974:FMT,
  author =       "C. V. W. Armstrong",
  title =        "Functional memory techniques applied to the
                 microprogrammed control of an associative processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "34--40",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wade:1974:IDM,
  author =       "James F. Wade and Paul D. Stigall",
  title =        "Instruction design to minimize program size",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "41--44",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bondi:1974:HHM,
  author =       "James O. Bondi and Paul D. Stigall",
  title =        "{HMO}, a hardware microcode optimizer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "45--51",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Peskin:1974:CAD,
  author =       "A. M. Peskin",
  title =        "The computer aided design of processor architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "51--55",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Huen:1974:IPR,
  author =       "W. H. Huen and D. P. Siewiorek",
  title =        "Intermodule protocol for register transfer level
                 modules: representation and analytic tools",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "56--62",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Isaacson:1974:PSP,
  author =       "Portia Isaacson",
  title =        "Picture systems, {PS}, and the design of a
                 channel-to-channel computer interface",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "63--70",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lofgren:1974:RCT,
  author =       "Lennart L{\"o}fgren",
  title =        "Reference concepts in a tree structured address
                 space",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "71--79",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anderson:1974:VMM,
  author =       "Judith A. Anderson and G. J. Lipovski",
  title =        "A virtual memory for microprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "80--84",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Brundage:1974:PED,
  author =       "R. E. Brundage and A. P. Batson",
  title =        "The performance enhancement of descriptor-based
                 virtual memory systems through the use of associative
                 registers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "85--90",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Marvel:1974:SSP,
  author =       "Orin E. Marvel",
  title =        "{SPEAC}: special purpose electronic area correlator",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "91--94",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Satterfield:1974:AAS,
  author =       "James M. Satterfield",
  title =        "Architectural advances of the space shuttle orbiter
                 avionics computer system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "95--98",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kodres:1974:DSA,
  author =       "Uno R. Kodres and William L. McCracken",
  title =        "Design study of an avionics navigation microcomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "99--105",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kane:1974:ISI,
  author =       "Gerald R. Kane",
  title =        "An iteratively structured information processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "106--112",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Richards:1974:HSI,
  author =       "H. {Richards, Jr.} and A. E. Oldehoeft",
  title =        "Hardware-software interactions in {SYMBOL-2R}'s
                 operating system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "113--118",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sylvain:1974:DEA,
  author =       "Pierre Sylvain and Maniel Vineberg",
  title =        "The design and evaluation of the array machine: a
                 high-level language processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "119--125",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dennis:1974:PAB,
  author =       "Jack B. Dennis and David P. Misunas",
  title =        "A preliminary architecture for a basic data-flow
                 processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "126--132",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Berkling:1974:RLR,
  author =       "K. J. Berkling",
  title =        "Reduction languages for reduction machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "133--140",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{King:1974:ODS,
  author =       "Willis K. King and Fulvio Carbonaro",
  title =        "Output devices sharing by minicomputers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "141--145",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rannem:1974:RSC,
  author =       "S. Rannem and V. C. Hamacher and S. G. Zaky and P.
                 Connolly",
  title =        "On relating small computer performance to design
                 parameters",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "146--151",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lawson:1974:ASH,
  author =       "Harold W. {Lawson, Jr.} and Bengt Magnhagen",
  title =        "Advantages of structured hardware",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "152--158",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kornerup:1974:CMS,
  author =       "Peter Kornerup",
  title =        "Concepts of the {MATHILDA} system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "159--164",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Foster:1974:S,
  author =       "Caxton C. Foster",
  title =        "{SOCRATES}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "165--169",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wann:1974:CCS,
  author =       "Donald F. Wann and Robert A. Ellis",
  title =        "Conjoined computer systems: an architecture for
                 laboratory data processing and instrument control",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "170--175",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jensen:1974:DFC,
  author =       "E. Douglas Jensen",
  title =        "A distributed function computer for real-time
                 control",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "176--182",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Radoy:1974:SMI,
  author =       "C. H. Radoy and G. J. Lipovski",
  title =        "Switched multiple instruction, multiple data stream
                 processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "183--187",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lechner:1974:SED,
  author =       "Robert J. Lechner",
  title =        "Sequentially encoded data structures that support
                 bidirectional scanning",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "188--194",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Freeman:1974:ICE,
  author =       "Martin Freeman",
  title =        "An instruction class for an extensible interpreter",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "195--200",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Giloi:1974:SCC,
  author =       "W. K. Giloi and H. Berg",
  title =        "{STARLET}: a computer concept based on ordered sets as
                 primitive data types",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "201--206",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cornell:1974:CGP,
  author =       "R. G. Cornell and H. C. Torng",
  title =        "A cellular general purpose computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "207--213",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goldstein:1974:MOR,
  author =       "Barry C. Goldstein and Thomas W. Scrutchin",
  title =        "A machine-oriented resource management architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "214--219",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sloan:1974:DOC,
  author =       "M. E. Sloan",
  title =        "A design-oriented computer engineering program",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "220--224",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Baron:1974:ELC,
  author =       "Janis Beitch Baron and D. E. Atkins",
  title =        "An educational laboratory in contemporary digital
                 design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "3",
  number =       "4",
  pages =        "225--231",
  month =        dec,
  year =         "1974",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:04 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1975:ACFa,
  author =       "W. R. Smith",
  title =        "{AADC} computer family architecture program",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "1",
  pages =        "4--8",
  month =        mar,
  year =         "1975",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lunde:1975:MDW,
  author =       "{\AA}mund Lunde",
  title =        "More data on the {O/W} ratios: a note on a paper by
                 {Flynn}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "1",
  pages =        "9--13",
  month =        mar,
  year =         "1975",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lipovski:1975:NNA,
  author =       "G. Jack Lipovski and Stanley Y. W. and Sr",
  title =        "On non-numeric architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "1",
  pages =        "14--29",
  month =        mar,
  year =         "1975",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Boulaye:1975:SDS,
  author =       "Guy. G. Boulaye",
  title =        "Structured design for structured computer
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "2",
  pages =        "8--17",
  month =        jun,
  year =         "1975",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:42 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Parnas:1975:ECA,
  author =       "D. L. Parnas",
  title =        "Evaluation criteria for abstract machines with unknown
                 applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "3",
  pages =        "2--9",
  month =        sep,
  year =         "1975",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:02 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Special issue: The AADC computer family architecture
                 project",
}

@Article{Smith:1975:ACFb,
  author =       "William R. Smith",
  title =        "{AADC} computer family architecture questions and
                 answers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "3",
  pages =        "15--21",
  month =        sep,
  year =         "1975",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:02 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Special issue: The AADC computer family architecture
                 project",
}

@Article{Su:1975:ICC,
  author =       "Stephen Y. H. Su",
  title =        "An introduction to {CHDL} (computer hardware
                 description languages)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "3",
  pages =        "22--23",
  month =        sep,
  year =         "1975",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:02 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Doran:1975:ICL,
  author =       "R. W. Doran",
  title =        "The {International Computers Ltd. ICL2900} computer
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "3",
  pages =        "24--47",
  month =        sep,
  year =         "1975",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:02 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bell:1976:CSW,
  author =       "Gordon Bell and William D. Strecker",
  title =        "Computer structures: {What} have we learned from the
                 {PDP-11}?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "1--14",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kerner:1976:PLL,
  author =       "Helmut Kerner and Werner Beyerle",
  title =        "A {PMS} level language for performance evaluation
                 modelling {(V-PMS)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "15--19",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Moalla:1976:DTM,
  author =       "M. Moalla and G. Saucier and J. Sifakis and M.
                 Zachariades",
  title =        "A design tool for the multilevel description and
                 simulation of systems of interconnected modules",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "20--27",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Allen:1976:CCS,
  author =       "Jonathan Allen",
  title =        "A course in computer structures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "28--32",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rossmann:1976:ICS,
  author =       "George E. Rossmann",
  title =        "The {IEEE Computer Society} task force on computer
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "33--33",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Widdoes:1976:MMM,
  author =       "Lawrence C. {Widdoes, Jr.}",
  title =        "The {Minerva} multi-microprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "34--39",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Arnold:1976:HRM,
  author =       "R. G. Arnold and E. W. Page",
  title =        "A hierarchical, restructurable multi-microprocessor
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "40--45",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McGill:1976:MAN,
  author =       "Robert McGill and John Steinhoff",
  title =        "A multimicroprocessor approach to numerical analysis:
                 {An} application to gaming problems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "46--51",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jensen:1976:MIS,
  author =       "John E. Jensen and Jean-Loup Baer",
  title =        "A model of interference in a shared resource
                 multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "52--57",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Leung:1976:CSF,
  author =       "Clement K. C. Leung and David P. Misunas and Andrij
                 Neczwid and Jack B. Dennis",
  title =        "A computer simulation facility for packet
                 communication architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "58--63",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rege:1976:CPS,
  author =       "S. L. Rege",
  title =        "Cost, performance and size tradeoffs for different
                 levels in a memory hierarchy",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "64--67",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dworak:1976:IIR,
  author =       "Paul E. Dworak and Alice C. Parker",
  title =        "An input interface for a real-time digital sound
                 generation system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "68--73",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mulder:1976:MOD,
  author =       "Michael C. Mulder and Patrick P. Fasang",
  title =        "A microprocessor oriented data acquisition and control
                 system for power system control",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "74--78",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gladney:1976:MRT,
  author =       "H. M. Gladney and G. Hochweller",
  title =        "Multiprogramming for real-time applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "79--85",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kehl:1976:BAH,
  author =       "Theodore H. Kehl",
  title =        "{Basil} architecture --- an {HLL} minicomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "86--92",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lawson:1976:FDC,
  author =       "Harold W. {Lawson, Jr.}",
  title =        "Function distribution in computer system
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "93--97",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vissers:1976:IDA,
  author =       "Chris A. Vissers",
  title =        "Interface, a dispersed architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "98--104",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thomasian:1976:DSS,
  author =       "A. Thomasian and A. Avizienis",
  title =        "A design study of a shared resource computing system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "105--112",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ford:1976:HSI,
  author =       "W. S. Ford and V. C. Hamacher",
  title =        "Hardware support for inter-process communication and
                 processor sharing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "113--118",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Trambacz:1976:TDP,
  author =       "Ulrich Trambacz and Georg Hyla",
  title =        "A taxonomy of display processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "119--120",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kluge:1976:TBT,
  author =       "W. E. Kluge",
  title =        "Traversing binary tree structures with shift register
                 memories (recent results)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "121.1--121.1",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fernandez:1976:ASS,
  author =       "Eduardo B. Fernandez and Rita C. Summers and Charles
                 D. Coleman",
  title =        "Architectural support for system protection (recent
                 results)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "121.2--121.2",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gault:1976:DUP,
  author =       "James W. Gault and Alice C. Parker",
  title =        "The design of a user-programmable digital interface
                 (recent results)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "121.3--121.3",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fournier:1976:SDG,
  author =       "Serge Fournier and Ming T. Liu",
  title =        "System design of a grammar-programmable high-level
                 language machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "122.4--122.4",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kuznia:1976:SSM,
  author =       "Ch. Kuznia and R. Kober and H. Kopp",
  title =        "{SMS 101} --- a structured multi microprocessor
                 system with deadlock-free operation scheme",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "122.5--122.5",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Liu:1976:SSD,
  author =       "Philip S. Liu and Frederic J. Mowle",
  title =        "Selection schemes for dynamically microcoding
                 {Fortran} programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "122.6--122.6",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fuller:1976:DMM,
  author =       "S. H. Fuller and D. P. Siewiorek and R. J. Swan",
  title =        "The design of a multi-micro-computer system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "123--123",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reames:1976:DSD,
  author =       "Cecil C. Reames and Ming T. Liu",
  title =        "Design and simulation of the distributed loop computer
                 network {(DLCN)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "124--129",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Franchi:1976:DFC,
  author =       "Paolo Franchi",
  title =        "Distribution of functions and control in {RPCNET}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "130--135",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wittie:1976:EMR,
  author =       "Larry D. Wittie",
  title =        "Efficient message routing in {Mega-Micro-Computer}
                 networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "136--140",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Welch:1976:IDO,
  author =       "Terry A. Welch",
  title =        "An investigation of descriptor oriented architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "141--146",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Feustel:1976:TAS,
  author =       "E. A. Feustel",
  title =        "Tagged architecture and the semantics of programming
                 languages: {Extensible} types",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "147--150",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Batson:1976:DDA,
  author =       "A. P. Batson and R. E. Brundage and J. P. Kearns",
  title =        "Design data for {Algol-60} machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "151--154",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Strecker:1976:CMP,
  author =       "William D. Strecker",
  title =        "Cache memories for {PDP-11} family computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "155--158",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Patel:1976:ITP,
  author =       "Janak H. Patel and Edward S. Davidson",
  title =        "Improving the throughput of a pipeline by insertion of
                 delays",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "159--164",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Abd-Alla:1976:LAT,
  author =       "A. M. Abd-Alla and Laird H. Moffett",
  title =        "On-line architecture tuning using microcapture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "165--171",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Healy:1976:COC,
  author =       "Leonard D. Healy",
  title =        "A character-oriented context-addressed
                 segment-sequential storage",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "172--177",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bush:1976:SIS,
  author =       "J. A. Bush and G. J. Lipovski and S. Y. W. su and J.
                 K. Watson and S. J. Ackerman",
  title =        "Some implementations of segment sequential functions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "178--185",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{DeMartinis:1976:SMS,
  author =       "Manlio DeMartinis and G. Jack Lipovski and Stanley Y.
                 W. Su and J. K. Watson",
  title =        "A {Self Managing Secondary Memory} system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "186--194",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fuller:1976:PPC,
  author =       "Samuel H. Fuller",
  title =        "Price\slash performance comparison of {C.mmp} and the
                 {PDP-10}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "4",
  number =       "4",
  pages =        "195--202",
  month =        jan,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorelli:1976:RAC,
  author =       "Lars-Erik Thorelli",
  title =        "Representation of arrays in computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "1",
  pages =        "6--9",
  month =        apr,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Berndt:1976:ECA,
  author =       "Helmut Berndt",
  title =        "Evolutionary computer architecture: the {Unidata
                 7.000} series",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "1",
  pages =        "10--16",
  month =        apr,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dennis:1976:CAC,
  author =       "Jack B. Dennis",
  title =        "Computer architecture and the cost of software",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "1",
  pages =        "17--21",
  month =        apr,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lindamood:1976:NCA,
  author =       "George Lindamood",
  title =        "On navel contemplation and the art of computer
                 maintenance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "1",
  pages =        "22--23",
  month =        apr,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fuller:1976:IMS,
  author =       "S. H. Fuller and G. A. Mathew",
  title =        "Implementing microprogram storage with {PLA}'s",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "2",
  pages =        "6--11",
  month =        jun,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:42 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hicks:1976:GQS,
  author =       "D. R. Hicks",
  title =        "A generalized queue scheme for process synchronization
                 and communication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "2",
  pages =        "12--14",
  month =        jun,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:42 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Langdon:1976:BRR,
  author =       "Glen G. Langdon",
  title =        "Book reviews: Review of {{\em Introduction to Computer
                 Architecture\/}} by {Harold S. Stone}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "2",
  pages =        "17--19",
  month =        jun,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:42 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

%%% TO DO: [04-Sep-2014] Volume 5 number 3: no data yet in ACM Portal database

@Article{Thurber:1976:ANR,
  author =       "Kenneth J. Thurber",
  title =        "{ARPS}: a new real-time computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "4",
  pages =        "6--16",
  month =        oct,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:09 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Salisbury:1976:MMC,
  author =       "Alan B. Salisbury",
  title =        "{MCF}: a military computer family for computer-based
                 systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "4",
  pages =        "17--20",
  month =        oct,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:09 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ris:1976:UDF,
  author =       "Frederic N. Ris",
  title =        "A unified decimal floating-point architecture for the
                 support of high-level languages",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "4",
  pages =        "21--31",
  month =        oct,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:09 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lipovski:1976:QS,
  author =       "G. Jack Lipovski",
  title =        "A question of style",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "4",
  pages =        "32--38",
  month =        oct,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:09 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chroust:1976:DIV,
  author =       "G. Chroust",
  title =        "Data interfaces versus control interfaces: a
                 half-baked conjecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "4",
  pages =        "39--40",
  month =        oct,
  year =         "1976",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:09 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

%%% TO DO: [04-Sep-2014] Volume 5 number 5: no data yet in ACM Portal database

@Article{Langdon:1977:CFM,
  author =       "Glen G. Langdon",
  title =        "Considerations on the ``figure of merit'' technique
                 for storage hierarchy design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "6",
  pages =        "25--28",
  month =        feb,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:28 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Miller:1977:BRRb,
  author =       "Edward F. Miller",
  title =        "Book Reviews: Review of {{\em High-Level Language
                 Computer Architecture\/}} by {Yaohan Chu. Academic
                 Press, New York, 1975}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "6",
  pages =        "29--29",
  month =        feb,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:28 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chu:1977:AHD,
  author =       "Yaohan Chu",
  title =        "Architecture of a hardware data interpreter",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "1--9",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dasgupta:1977:DSL,
  author =       "Subrata Dasgupta",
  title =        "The design of some language constructs for horizontal
                 microprogramming",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "10--16",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jensen:1977:HMM,
  author =       "E. Douglas Jensen and Richard Y. Kain",
  title =        "The {Honeywell Modular Microprogram Machine}: {M3}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "17--28",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ramseyer:1977:MMI,
  author =       "Richard R. Ramseyer and Andries van Dam",
  title =        "A multi-microprocessor implementation of a general
                 purpose pipelined {CPU}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "29--34",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ravi:1977:HMS,
  author =       "C. V. Ravi and Torben Moller",
  title =        "A hierarchical microcomputer system for hardware and
                 software development",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "35--40",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Harris:1977:HMO,
  author =       "J. Archer Harris and David R. Smith",
  title =        "Hierarchical multiprocessor organizations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "41--48",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hurakami:1977:PPS,
  author =       "K. Hurakami and S. Nishikawa and M. Sato",
  title =        "Poly-Processor {System} analysis and design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "49--56",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mazare:1977:FEH,
  author =       "Guy Mazare",
  title =        "A few examples of how to use a symmetrical
                 multi-micro-processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "57--62",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kogge:1977:MPP,
  author =       "Peter M. Kogge",
  title =        "The microprogramming of pipelined processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "63--69",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Siegel:1977:UVT,
  author =       "Howard Jay Siegel",
  title =        "The universality of various types of {SIMD} machine
                 interconnection networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "70--79",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rau:1977:EIF,
  author =       "Ramakrishna B. Rau and George E. Rossmann",
  title =        "The effect of instruction fetch strategies upon the
                 performance of pipelined instruction units",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "80--89",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ahuja:1977:MMS,
  author =       "S. R. Ahuja and J. R. Jump",
  title =        "A modular memory scheme for array processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "90--94",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Haynes:1977:AAC,
  author =       "Leonard S. Haynes",
  title =        "The architecture of an {ALGOL 60} computer implemented
                 with distributed processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "95--104",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sullivan:1977:LSHa,
  author =       "Herbert Sullivan and T. R. Bashkow",
  title =        "A large scale, homogeneous, fully distributed parallel
                 machine, {I}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "105--117",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sullivan:1977:LSHb,
  author =       "Herbert Sullivan and Theodore R. Bashkow and David
                 Klappholz",
  title =        "A Large Scale, Homogeneous, Fully Distributed Parallel
                 Machine, {II}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "118--124",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lipovski:1977:VMM,
  author =       "G. Jack Lipovski",
  title =        "On virtual memories and micronetworks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "125--134",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Strauss:1977:CNT,
  author =       "Jon C. Strauss and Kenneth J. Thurber",
  title =        "Considerations for new tactical computer systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "135--140",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thurber:1977:ATC,
  author =       "Kenneth J. Thurber and Peter C. Patton and Robert C.
                 Deward and Jon C. Strauss and Thomas W. Petschauer",
  title =        "An advanced tactical computer concept",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "141--146",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nutt:1977:MIP,
  author =       "Gary J. Nutt",
  title =        "Microprocessor implementation of a parallel
                 processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "147--152",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dworak:1977:DIR,
  author =       "Paul Dworak and Alice C. Parker and Richard Blum",
  title =        "The design and implementation of a real-time sound
                 generation system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "153--158",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Parker:1977:HST,
  author =       "A. C. Parker and A. W. Nagle",
  title =        "Hardware\slash software tradeoffs in a variable word
                 width, variable queue length buffer memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "159--164",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Peuto:1977:ITM,
  author =       "Bernard L. Peuto and Leonard J. Shustek",
  title =        "An instruction timing model of {CPU} performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "165--178",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hoogendoorn:1977:RMI,
  author =       "Cornelis H. Hoogendoorn",
  title =        "Reduction of memory interference in multiprocessor
                 systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "179--183",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hammerstrom:1977:ICC,
  author =       "D. W. Hammerstrom and E. S. Davidson",
  title =        "Information content of {CPU} memory referencing
                 behavior",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "184--192",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Liu:1977:MCP,
  author =       "Ming T. Liu and Cecil C. Reames",
  title =        "Message communication protocol and operating system
                 design for the {Distributed Loop Computer Network
                 (DLCN)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "193--200",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Poujoulat:1977:ACB,
  author =       "G. H. Poujoulat",
  title =        "Architecture of the {CORAIL} building block system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "201--204",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tredennick:1977:HSB,
  author =       "H. L. Tredennick and T. A. Welch",
  title =        "High-speed buffering for variable length operands",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "7",
  pages =        "205--210",
  month =        mar,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Steel:1977:AGP,
  author =       "Rod Steel",
  title =        "Another general purpose computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "8",
  pages =        "5--11",
  month =        apr,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lindamood:1977:WN,
  author =       "George E. Lindamood",
  title =        "What's in a name?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "8",
  pages =        "12--14",
  month =        apr,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schneiker:1977:MF,
  author =       "Conrad Schneiker",
  title =        "The microprocessors of the future",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "8",
  pages =        "15--16",
  month =        apr,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Miller:1977:BRR,
  author =       "Edward F. {Miller, Jr.}",
  title =        "Book review: Review of {{\em Large-Scale Computer
                 Architecture: Parallel and Associative Processors\/}}
                 by {Kenneth J. Thurber, Hayden Book Company, Rochelle
                 Park, New Jersey 1976}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "5",
  number =       "8",
  pages =        "17--17",
  month =        apr,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Conner:1977:IOC,
  author =       "William M. Conner and Edward R. Dirling",
  title =        "Input\slash Output considerations in look-ahead
                 processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "1",
  pages =        "7--12",
  month =        jun,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rosin:1977:SM,
  author =       "Robert F. Rosin",
  title =        "The significance of microprogramming",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "1",
  pages =        "14--19",
  month =        jun,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gonzalez:1977:BRR,
  author =       "Mario J. Gonzalez",
  title =        "Book review: Review of {{\em Microprogramming
                 Primer\/}} by {Harry Katzan, Jr., McGraw-Hill 1977}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "1",
  pages =        "29--30",
  month =        jun,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vineberg:1977:ICS,
  author =       "Maniel Vineberg",
  title =        "Implementation of character string pattern matching on
                 a multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "2",
  pages =        "1--7",
  month =        may,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bird:1977:APP,
  author =       "R. M. Bird and J. C. Tu and R. M. Worthy",
  title =        "Associative\slash parallel processors for searching
                 very large textual data bases",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "2",
  pages =        "8--9",
  month =        may,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lipovski:1977:IFT,
  author =       "G. J. Lipovski",
  title =        "On imaginary fields, token transfers and floating
                 codes in intelligent secondary memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "2",
  pages =        "17--22",
  month =        may,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zaky:1977:MNN,
  author =       "S. G. Zaky",
  title =        "Microprocessors for non-numeric processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "2",
  pages =        "23--30",
  month =        may,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hsiao:1977:ADC,
  author =       "David K. Hsiao and Krishnamurthi Kannan",
  title =        "The architecture of a database computer --- a
                 summary",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "2",
  pages =        "31--33",
  month =        may,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rosenthal:1977:DMM,
  author =       "Robert S. Rosenthal",
  title =        "The data management machine, a classification",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "2",
  pages =        "35--39",
  month =        may,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McDonell:1977:TNS,
  author =       "Ken J. McDonell",
  title =        "Trends in non-software support for input-output
                 functions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "2",
  pages =        "40--47",
  month =        may,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cerretti:1977:UIP,
  author =       "R. Cerretti and D. Jasilli and D. R. Matteucci",
  title =        "{Ulisse}: {An Italian} project for a multifunctional
                 terminal system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "2",
  pages =        "48--50",
  month =        may,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bray:1977:DMR,
  author =       "Olin H. Bray",
  title =        "Data management requirements: {The} similarity of
                 memory management, database systems, and message
                 processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "2",
  pages =        "68--76",
  month =        may,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Landson:1977:CSA,
  author =       "Barry M. Landson and Robert G. Sargent",
  title =        "A comparison of sequential and associate computing of
                 priority queues",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "2",
  pages =        "77--78",
  month =        may,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Myers:1977:CAS,
  author =       "Glenford J. Myers",
  title =        "The case against stack-oriented instruction sets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "3",
  pages =        "7--10",
  month =        aug,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tanenbaum:1977:AMA,
  author =       "Andrew S. Tanenbaum",
  title =        "Ambiguous machine architecture and program
                 efficiency",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "3",
  pages =        "11--13",
  month =        aug,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hicks:1977:MCA,
  author =       "D. R. Hicks",
  title =        "Microprogramming with a content-addressable
                 read-only-memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "3",
  pages =        "14--15",
  month =        aug,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hicks:1977:MPS,
  author =       "D. R. Hicks",
  title =        "Multitasking as a program structuring primitive",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "3",
  pages =        "16--18",
  month =        aug,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chroust:1977:BRR,
  author =       "G. Chroust",
  title =        "Book reviews: Review of {{\em Digital System
                 Implementation\/}} by {Gerrit A. Blaauw, Prentice Hall,
                 Series in Automatic Computation 1976}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "4",
  pages =        "27--28",
  month =        oct,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:09 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hagan:1977:VMS,
  author =       "R. A. Hagan and C. S. Wallace",
  title =        "A virtual memory system for the {Hewlett Packard
                 2100A}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "5",
  pages =        "5--13",
  month =        dec,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:17 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Baskett:1977:MMF,
  author =       "Forest Baskett",
  title =        "More on microprocessors of the future",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "5",
  pages =        "14--17",
  month =        dec,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:17 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chu:1977:DEC,
  author =       "Yaohan Chu",
  title =        "Direct-execution computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "5",
  pages =        "18--23",
  month =        dec,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:17 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schulthess:1977:RCA,
  author =       "Peter U. Schulthess and Eduard P. Mumprecht",
  title =        "Reply to the case against stack-oriented instruction
                 sets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "5",
  pages =        "24--27",
  month =        dec,
  year =         "1977",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:17 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mountain:1978:AMC,
  author =       "John B. Mountain and Philip H. Enslow",
  title =        "Application of the military computer family
                 architecture selection criteria to the {PR1ME P400}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "6",
  pages =        "3--17",
  month =        feb,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:28 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lipovski:1978:JFM,
  author =       "G. Jack Lipovski",
  title =        "Just a few more words on microprocessors of the
                 future",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "6",
  pages =        "18--21",
  month =        feb,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:28 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Keedy:1978:USE,
  author =       "J. L. Keedy",
  title =        "On the use of stacks in the evaluation of
                 expressions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "6",
  pages =        "22--28",
  month =        feb,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:28 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tanenbaum:1978:RPA,
  author =       "Andrew S. Tanenbaum",
  title =        "Review of {{\em Processor Architecture\/}} by {S. H.
                 Lavington, NCC Publications, Manchester 1976}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "6",
  pages =        "31--31",
  month =        feb,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:28 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Whiteside:1978:BRR,
  author =       "A. E. Whiteside",
  title =        "Book reviews: Review of {{\em The Architecture of
                 Concurrent Programs\/}} by {Per Brinch Hansen,
                 Prentice-Hall 1977}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "6",
  number =       "6",
  pages =        "32--32",
  month =        feb,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:28 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bhandarkar:1978:STT,
  author =       "Dileep P. Bhandarkar and J. Egil Juliussen",
  title =        "Semiconductor technology: trends and implications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "1",
  pages =        "4--14",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Payne:1978:CCD,
  author =       "A. J. Payne",
  title =        "A computer console design to help the operator",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "1",
  pages =        "15--22",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McGlynn:1978:RCA,
  author =       "Daniel R. McGlynn",
  title =        "Review of {{\em Content Addressable Parallel
                 Processors\/}} by {Caxton C. Foster. Van Nostrand
                 Reinhold Co. 1976}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "1",
  pages =        "23--23",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ramamoorthy:1978:RSC,
  author =       "C. V. Ramamoorthy",
  title =        "Review of {{\em Structured Computer Organization\/}}
                 by {Andrew S. Tanenbaum, Prentice-Hall 1976}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "1",
  pages =        "23--23",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Buchholz:1978:RCS,
  author =       "W. Buchholz",
  title =        "Review of {{\em Computer System Architecture\/}} by
                 {M. Morris Mano, Prentice-Hall 1976}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "1",
  pages =        "24--24",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vranesic:1978:BRR,
  author =       "Z. G. Vranesic",
  title =        "Book reviews: Review of {{\em Content Addressable
                 Parallel Processors\/}} by {Caxton C. Foster, Van
                 Nostrand Reinhold Co. 1976}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "1",
  pages =        "24--24",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Korfhage:1978:DPU,
  author =       "R. R. Korfhage and W. H. E. Day and L. L. Beck and W.
                 F. Appelbe",
  title =        "Data physics: an unorthodox view of data and its
                 implications in data processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "1--7",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Copeland:1978:SSS,
  author =       "George P. Copeland",
  title =        "String storage and searching for data base
                 applications: implementation on the {INDY} backend
                 kernel",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "8--17",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Otis:1978:ERD,
  author =       "Allen J. Otis and George P. Copeland",
  title =        "Editing requirements for data base applications and
                 their implementation on the {INDY} backend kernel",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "18--29",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lipovski:1978:SPI,
  author =       "G. Jack Lipovski",
  title =        "Semantic paging on intelligent discs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "30--34",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Williams:1978:MSD,
  author =       "Rhon Williams",
  title =        "A multiprocessing system for the direct execution of
                 {LISP}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "35--41",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bird:1978:TFI,
  author =       "R. M. Bird and J. B. Newsbaum and J. L. Trefftzs",
  title =        "Text file inversion: an evaluation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "42--50",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Roberts:1978:SCA,
  author =       "David C. Roberts",
  title =        "A specialized computer architecture for text
                 retrieval",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "51--59",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stucki:1978:CCA,
  author =       "M. J. Stucki and J. R. Cox and G. C. Roman and P. N.
                 Turcu",
  title =        "Coordinating concurrent access in a distributed
                 database architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "60--64",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gouda:1978:HCC,
  author =       "Mohamed G. Gouda",
  title =        "A hierarchical controller for concurrent accessing of
                 distributed databases",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "65--70",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gavish:1978:EAD,
  author =       "Bezalel Gavish and Harvey Koch",
  title =        "An extensible architecture for data flow processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "71--76",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Harvill:1978:FPO,
  author =       "J. B. Harvill",
  title =        "Functional parallelism in an operand state saving
                 computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "77--84",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hutchison:1978:MM,
  author =       "J. S. Hutchison and W. G. Roman",
  title =        "Madman machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "85--90",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Banerjee:1978:UDM,
  author =       "Jayanta Banerjee and David K. Hsiao",
  title =        "The use of a database machine for supporting
                 relational databases",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "91--98",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sadowski:1978:EPR,
  author =       "Paul J. Sadowski and S. A. Schuster",
  title =        "Exploiting parallelism in a {Relational Associative
                 Processor}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "99--109",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chang:1978:BRD,
  author =       "Hsu Chang",
  title =        "Bubbles for relational database",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "110--116",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{ElMasri:1978:MIR,
  author =       "A. {El Masri} and J. Rohmer and D. Tusera",
  title =        "A machine for information retrieval",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "117--120",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Matteucci:1978:DSA,
  author =       "Dante R. Matteucci",
  title =        "A distributed structure for the automization of the
                 {Catalog of the National Cultural Heritage}:
                 experiences and proposals",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "2",
  pages =        "121--133",
  month =        aug,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:41 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thurber:1978:CCT,
  author =       "Kenneth J. Thurber",
  title =        "Computer communication techniques",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "3",
  pages =        "7--16",
  month =        oct,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:02 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jennings:1978:VP,
  author =       "Hal W. Jennings",
  title =        "A variation on the {PDP 11}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "3",
  pages =        "17--26",
  month =        oct,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:02 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hansen:1978:MAC,
  author =       "Per Brinch Hansen",
  title =        "Multiprocessor architectures for concurrent programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "4",
  pages =        "4--23",
  month =        dec,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Keedy:1978:EEU,
  author =       "J. L. Keedy",
  title =        "On the evaluation of expressions using accumulators,
                 stacks and store-to-store instructions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "4",
  pages =        "24--27",
  month =        dec,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chattergy:1978:CL,
  author =       "Rahul Chattergy",
  title =        "In the current literature",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "4",
  pages =        "30--30",
  month =        dec,
  year =         "1978",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cragon:1979:ECS,
  author =       "Harvey G. Cragon",
  title =        "An evaluation of code space requirements and
                 performance of various architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "5",
  pages =        "5--21",
  month =        feb,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thurber:1979:BLC,
  author =       "Kenneth J. Thurber and Harvey A. Freeman",
  title =        "A bibliography of local computer network
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "5",
  pages =        "22--27",
  month =        feb,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cox:1979:NCA,
  author =       "Lyle A. {Cox, Jr.}",
  title =        "The nature of ``computer architecture''",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "7",
  pages =        "8--12",
  month =        apr,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{vandeSnepscheut:1979:INP,
  author =       "Jan L. A. van de Snepscheut and Gert A. Slavenburg",
  title =        "Introducing the notion of processes to hardware",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "7",
  pages =        "13--23",
  month =        apr,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Atkins:1979:RAC,
  author =       "D. E. Atkins",
  title =        "Review of {{\em Advances in Computer Architecture\/}}
                 by {Glenford J. Myers. Wiley-Interscience Division of
                 John Wiley and Sons 1978}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "7",
  pages =        "25--26",
  month =        apr,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bowyer:1979:BRS,
  author =       "Kevin W. Bowyer",
  title =        "Book review of {{\em The Structure of Computers and
                 Computations: Volume One\/}} by {David J. Kuck. John
                 Wiley \& Sons 1978}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "7",
  pages =        "27--30",
  month =        apr,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gibson:1979:TOR,
  author =       "Randall Gibson and Paul Anderson",
  title =        "Technical overview of the {Renaissance Octobus}
                 system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "8",
  pages =        "2--9",
  month =        jun,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stevenson:1979:EEM,
  author =       "Johan W. Stevenson and Andrew S. Tanenbaum",
  title =        "Efficient encoding of machine instructions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "8",
  pages =        "10--17",
  month =        jun,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Keedy:1979:MUS,
  author =       "J. L. Keedy",
  title =        "More on the use of stacks in the evaluation of
                 expressions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "8",
  pages =        "18--22",
  month =        jun,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Quick:1979:IMP,
  author =       "G. E. Quick",
  title =        "Intelligent memory: ``a parallel processing
                 concept''",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "8",
  pages =        "23--28",
  month =        jun,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rivest:1979:BCA,
  author =       "Ronald L. Rivest",
  title =        "The {BLIZZARD} computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "9",
  pages =        "2--10",
  month =        aug,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Keedy:1979:TPR,
  author =       "J. L. Keedy",
  title =        "A technique for passing reference parameters in an
                 information-hiding architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "9",
  pages =        "11--15",
  month =        aug,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kavipurapu:1979:QAU,
  author =       "Krishna M. Kavipurapu and Dennis J. Frailey",
  title =        "Quantification of architectures using software
                 science",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "10",
  pages =        "2--6",
  month =        oct,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Turton:1979:PHS,
  author =       "Trevor Turton",
  title =        "A proposed high-speed computer design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "10",
  pages =        "7--21",
  month =        oct,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Staff:1979:CL,
  author =       "{Computer Architecture News} staff",
  title =        "In the current literature",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "7",
  number =       "10",
  pages =        "22--22",
  month =        oct,
  year =         "1979",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

%%% TO DO: [04-Sep-2014] Volume 8 number 1: no data yet in ACM Portal database

@Article{Richards:1980:CE,
  author =       "Dana Richards",
  title =        "On a {``Counter--Example''}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "2",
  pages =        "2--3",
  month =        apr,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Denning:1980:WIC,
  author =       "Peter J. Denning",
  title =        "Why not innovations in computer architecture?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "2",
  pages =        "4--7",
  month =        apr,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gerrity:1980:HDU,
  author =       "G. W. Gerrity",
  title =        "Hardware detection of undefined references",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "2",
  pages =        "8--11",
  month =        apr,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Denning:1980:MCS,
  author =       "Peter J. Denning and T. Don Dennis",
  title =        "On minimizing contention at semaphores",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "2",
  pages =        "12--19",
  month =        apr,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dennis:1980:BBD,
  author =       "Jack B. Dennis and G. Andrew Boughton and Clement K.
                 C. Leung",
  title =        "Building blocks for data flow prototypes",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "1--8",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Davidson:1980:MSM,
  author =       "Edward S. Davidson",
  title =        "A multiple stream microprocessor prototype system:
                 {AMP-1}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "9--16",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Andre:1980:KAO,
  author =       "F. Andre and J. P. Ban{\^a}tre and H. Leroy and G.
                 Paget and F. Ployette and J. P. Routeau",
  title =        "{KENSUR}: An architecture oriented towards programming
                 languages translation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "17--22",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kuhl:1980:DFT,
  author =       "J. G. Kuhl and S. M. Reddy",
  title =        "Distributed fault-tolerance for large multiprocessor
                 systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "23--30",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Malek:1980:CCA,
  author =       "Miroslaw Malek",
  title =        "A comparison connection assignment for diagnosis of
                 multiprocessor systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "31--36",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Grosspietsch:1980:CTR,
  author =       "K. E. Grosspietsch and J. Kaiser and E. Nett",
  title =        "A concept for test and reconfiguration of a
                 fault-tolerant {VLSI} processor system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "37--43",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Brassard:1980:PBC,
  author =       "Jean-Paul Brassard and Jan Gecsei",
  title =        "Path building in cellular partitioning networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "44--50",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McMillen:1980:MMC,
  author =       "Robert J. McMillen and Howard Jay Siegel",
  title =        "{MIMD} machine communication using the augmented data
                 manipulator network",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "51--60",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shen:1980:FTC,
  author =       "John P. Shen and John P. Hayes",
  title =        "Fault tolerance of a class of connecting networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "61--71",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Coffman:1980:CBS,
  author =       "E. G. {Coffman, Jr.} and Kimming So",
  title =        "On the comparison between single and multiple
                 processor systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "72--79",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hamacher:1980:PCF,
  author =       "V. Carl Hamacher and Gerald S. Shedler",
  title =        "Performance of a collision-free local bus network
                 having asynchronous distributed control",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "80--87",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zuberek:1980:TPN,
  author =       "W. M. Zuberek",
  title =        "Timed {Petri} nets and preliminary performance
                 evaluation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "88--96",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ditzel:1980:RHL,
  author =       "David R. Ditzel and David A. Patterson",
  title =        "Retrospective on high-level language computer
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "97--104",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sansonnet:1980:MLD,
  author =       "J. P. Sansonnet and M. Castan and C. Percebois",
  title =        "{M3L}: a list-directed architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "105--112",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hibino:1980:PPG,
  author =       "Yasushi Hibino",
  title =        "A Practical Parallel Garbage Collection Algorithm and
                 Its Implementation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "113--120",
  month =        may,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  URL =          "ftp://ftp.math.utah.edu/pub/mirrors/ftp.ira.uka.de/bibliography/Compiler/garbage.collection.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "Hardware assisted GC",
}

@Article{Treleaven:1980:MPR,
  author =       "Philip C. Treleaven and Geoffrey F. Mole",
  title =        "A multi-processor reduction machine for user-defined
                 reduction languages",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "121--130",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tobias:1980:SUM,
  author =       "Jeffrey M. Tobias",
  title =        "A single user multiprocessor incorporating processor
                 manipulation facilities",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "131--138",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Halstead:1980:MSD,
  author =       "Robert H. {Halstead, Jr.} and Stephen A. Ward",
  title =        "The {MuNet}: a scalable decentralized architecture for
                 parallel computation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "139--145",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lampson:1980:PHP,
  author =       "Butler W. Lampson and Kenneth A. Pier",
  title =        "A processor for a high-performance personal computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "146--160",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Edwards:1980:MGN,
  author =       "D. B. G. Edwards and A. E. Knowles and J. V. Woods",
  title =        "{MU6-G}: a new design to achieve mainframe performance
                 from a mini-sized computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "161--167",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Batcher:1980:AMP,
  author =       "Kenneth E. Batcher",
  title =        "Architecture of a massively parallel processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "168--173",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Palmer:1980:IND,
  author =       "John Palmer",
  title =        "The {Intel 8087} numeric data processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "174--181",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kuhn:1980:EMA,
  author =       "Robert H. Kuhn",
  title =        "Efficient mapping of algorithms to single-stage
                 interconnections",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "182--189",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nassimi:1980:SRB,
  author =       "David Nassimi and Sartaj Sahni",
  title =        "A self routing {Benes} network",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "190--195",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{vonIssendorff:1980:ANF,
  author =       "H. von Issendorff and W. Gr{\"u}newald",
  title =        "An adaptable network for functional distributed
                 systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "196--201",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Riad:1980:CFC,
  author =       "Mokhtar Boshra Riad",
  title =        "A combination of field and current access techniques
                 for efficient and cost-effective bubble memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "202--210",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Trivedi:1980:DLS,
  author =       "K. S. Trivedi",
  title =        "Designing linear storage hierarchies so as to maximize
                 reliability subject to cost and performance
                 constraints",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "211--217",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ahuja:1980:APP,
  author =       "Sudhir R. Ahuja and Charles S. Roberts",
  title =        "An associative\slash parallel processor for partial
                 match retrieval using superimposed codes",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "218--227",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ruggiero:1980:MBV,
  author =       "M. D. Ruggiero and S. G. Zaky",
  title =        "A microprocessor-based virtual memory system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "228--235",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jagannathan:1980:TAI,
  author =       "Anand Jagannathan",
  title =        "A technique for the architectural implementation of
                 software subsystems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "236--244",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Berstis:1980:SPD,
  author =       "Viktors Berstis",
  title =        "Security and protection of data in the {IBM
                 System\slash 38}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "245--252",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hoffmann:1980:HIC,
  author =       "Miguel Garc{\'\i}a Hoffmann",
  title =        "Hardware implementation of communication protocols:
                 a formal approach",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "253--263",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Guillier:1980:ACF,
  author =       "P. Guillier and D. Slosberg",
  title =        "An architecture with comprehensive facilities of
                 inter-process synchronization and communication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "264--270",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lougheed:1980:CPP,
  author =       "Robert M. Lougheed and David L. McCubbrey",
  title =        "The cytocomputer: a practical pipelined image
                 processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "271--277",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Halatsis:1980:ACM,
  author =       "C. Halatsis and A. van Dam and J. Joosten and M.
                 Letheren",
  title =        "Architectural considerations for a microprogrammable
                 emulating engine using bit-slices",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "278--291",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Irwin:1980:OPS,
  author =       "Mary Jane Irwin and Don Heller",
  title =        "Online pipeline systems for recursive numeric
                 computations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "292--299",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Foster:1980:DSP,
  author =       "M. J. Foster and H. T. Kung",
  title =        "Design of special-purpose {VLSI} chips: Example and
                 opinions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "300--307",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kumar:1980:SLC,
  author =       "Anshul Kumar and P. C. P. Bhatt",
  title =        "A structured language for {CAD} of digital systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "308--316",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hercksen:1980:HMS,
  author =       "Uwe Hercksen and Rainer Klar and Wolfgang
                 Klein{\"o}der",
  title =        "Hardware-measurements of storage access conflicts in
                 the processor array {EGPA(1)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "317--324",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tokoro:1980:HLM,
  author =       "Mario Tokoro and Kiichiro Tamaru and Masaaki Mizuno
                 and Masao Hori",
  title =        "A high level multi-lingual multiprocessor {KMP\slash
                 II}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "3",
  pages =        "325--333",
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:54:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Aupperle:1980:RIC,
  author =       "Ken Aupperle",
  title =        "A real innovation in computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "4",
  pages =        "6--7",
  month =        jun,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Galloway:1980:AIR,
  author =       "John R. {Galloway, Jr.}",
  title =        "Architectural innovation round: round \#3",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "4",
  pages =        "8--10",
  month =        jun,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sharp:1980:STD,
  author =       "John A. Sharp",
  title =        "Some thoughts on data flow architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "4",
  pages =        "11--21",
  month =        jun,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Payne:1980:VFP,
  author =       "Mary Payne and Dileep Bhandarkar",
  title =        "{VAX} floating point: a solid foundation for numerical
                 computation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "4",
  pages =        "22--33",
  month =        jun,
  year =         "1980",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/641845.641849",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Sat Jun 24 12:02:21 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dickman:1980:TR,
  author =       "Lloyd Dickman",
  title =        "Treasurer's report",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "4",
  pages =        "37--38",
  month =        jun,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Staff:1980:CLAa,
  author =       "{Computer Architecture News} staff",
  title =        "Current literature: abstracts of articles of
                 interest\ldots{}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "4",
  pages =        "48--48",
  month =        jun,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Davies:1980:CAM,
  author =       "Julian Davies",
  title =        "Clock architecture and management",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "5",
  pages =        "3--6",
  month =        aug,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:16 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chroust:1980:RMO,
  author =       "G. Chroust and J. R. M{\"u}hlbacher",
  title =        "Rivalling multiprocessor organization: a
                 hardware\slash speed trade-off",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "5",
  pages =        "7--10",
  month =        aug,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:16 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stevenson:1980:RPI,
  author =       "David Stevenson",
  title =        "A report on the proposed {IEEE Floating Point Standard
                 (IEEE Task p754)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "5",
  pages =        "11--12",
  month =        aug,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:16 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rattner:1980:OBC,
  author =       "Justin Rattner and George Cox",
  title =        "Object-based computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "6",
  pages =        "4--11",
  month =        oct,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Myers:1980:HIC,
  author =       "G. J. Myers and B. R. S. Buckingham",
  title =        "A hardware implementation of capability-based
                 addressing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "6",
  pages =        "12--24",
  month =        oct,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Patterson:1980:CRI,
  author =       "David A. Patterson and David R. Ditzel",
  title =        "The case for the reduced instruction set computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "6",
  pages =        "25--33",
  month =        oct,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Clark:1980:CCR,
  author =       "Douglas W. Clark and William D. Strecker",
  title =        "Comments on {``The Case for the Reduced Instruction
                 Set Computer,''} by {Patterson} and {Ditzel}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "6",
  pages =        "34--38",
  month =        oct,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Brakefield:1980:BAT,
  author =       "James C. Brakefield",
  title =        "Is 32 bits of address too much?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "6",
  pages =        "39--40",
  month =        oct,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Brakefield:1980:PB,
  author =       "James C. Brakefield",
  title =        "The peripheral bus",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "6",
  pages =        "41--43",
  month =        oct,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mudge:1980:BRR,
  author =       "Trevor Mudge",
  title =        "Book reviews: Review of {{\em The Structure of
                 Computers and Computation, Vol. I\/}} by {David J.
                 Kuck, John Wiley \& and Sons 1978}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "6",
  pages =        "44--45",
  month =        oct,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Staff:1980:CLAb,
  author =       "Computer Architecture News Staff",
  title =        "Current literature: abstracts of articles of
                 interest\ldots{}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "6",
  pages =        "46--46",
  month =        oct,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reed:1980:WFC,
  author =       "Karl Reed",
  title =        "The way forward in computer architecture research",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "7",
  pages =        "3--7",
  month =        oct,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gilmore:1980:SEM,
  author =       "John Gilmore",
  title =        "Suggested enhancements to the {Motorola MC68000}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "7",
  pages =        "8--14",
  month =        oct,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wakerly:1980:PED,
  author =       "John F. Wakerly",
  title =        "{Pascal} extensions for describing computer
                 instruction sets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "7",
  pages =        "15--23",
  month =        oct,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kavi:1980:SA,
  author =       "Krishna M. Kavi",
  title =        "Semantics of an algorithm",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "7",
  pages =        "24--26",
  month =        oct,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Treleaven:1980:VMA,
  author =       "Philip C. Treleaven",
  title =        "{VLSI}: machine architecture and very high level
                 languages",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "8",
  number =       "7",
  pages =        "27--38",
  month =        oct,
  year =         "1980",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dickman:1981:SB,
  author =       "Lloyd Dickman",
  title =        "{SIGARCH} business",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "1",
  pages =        "7--8",
  month =        feb,
  year =         "1981",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:28 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{DePrycker:1981:NIM,
  author =       "Martin L. {De Prycker}",
  title =        "A new index mode for the {VAX-11}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "2",
  pages =        "10--11",
  month =        apr,
  year =         "1981",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1296940.1296941",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:58:05 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "One advantage of most high level languages over
                 machine languages consists of the availability of
                 concepts which are frequently used by most programmers.
                 One of these concepts is the array mechanism, where the
                 high level language generally provides three operations
                 associated with array manipulations: type-checking,
                 bounds-checking and address calculation.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stevenson:1981:PP,
  author =       "David Stevenson",
  title =        "The {Phoenix Project}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "2",
  pages =        "12--15",
  month =        apr,
  year =         "1981",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1296940.1296942",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:58:05 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The Phoenix Project was an exploration of the issues
                 surrounding large scale scientific computing. It was
                 conducted at the Institute for Advanced Computation,
                 NASA-Ames Research Center at Moffett Field, California
                 from 1975 to 1979. The primary results of the project
                 were a sizing of the likely needs of large scale
                 scientific computing during the 1980s, what computing
                 technology could be available to meet those needs, a
                 conceptual design of a processor that could meet those
                 needs, and a programming, language suitable for use by
                 this community on a parallel processor such as the one
                 proposed.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{VanOost:1981:MPS,
  author =       "E. M. J. C. {Van Oost}",
  title =        "Multi-processor system description and simulation
                 using structured multi-programming languages",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "2",
  pages =        "16--32",
  month =        apr,
  year =         "1981",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1296940.1296943",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:58:05 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Most of the multi-processor systems designed for real
                 time control demand a high efficiency, compromising the
                 simplicity of the system. If this requirement imposes a
                 hardware implementation of most of the primitives of
                 the system, a complicated hardware will result. In
                 order to retain to some extent the ease of using
                 structured multi-programming languages, e.g. Concurrent
                 Pascal [1], we have used these languages for the
                 description and simulation of the complex hardware,
                 instead of using them for software implementation of
                 parallelism.\par

                 This approach is explained with examples taken from an
                 existing multi-processor system [2] developed at the
                 Brussels Free University (V.U.B.).",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wakerly:1981:BRR,
  author =       "John Wakerly",
  title =        "Book review: Review of {'The Computers that Saved
                 Metropolis, by DC Comics and Radio Shack', July 1980}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "2",
  pages =        "33--34",
  month =        apr,
  year =         "1981",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1296940.1296945",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:58:05 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

%%% TO DO: [04-Sep-2014] Volume 9 number 3: no data yet in ACM Portal database

@Article{Arvind:1981:MPD,
  author =       "Arvind and V. Kathail",
  title =        "A Multiple Processor Data Flow Machine that Supports
                 Generalized Procedures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "3",
  pages =        "??--??",
  year =         "1981",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibsource =    "ftp://ftp.math.utah.edu/pub/mirrors/ftp.ira.uka.de/bibliography/Compiler/Functional.bib;
                 http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  note =         "Proceedings of the 8th Annual Symposium on Computer
                 Architecture.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "functional dataflow",
}

@Article{Gerrity:1981:PI,
  author =       "G. W. Gerrity",
  title =        "On processes and interrupts",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "4",
  pages =        "4--14",
  month =        jun,
  year =         "1981",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hill:1981:HMS,
  author =       "Dwight D. Hill",
  title =        "A hardware mechanism for supporting range checks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "4",
  pages =        "15--21",
  month =        jun,
  year =         "1981",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cherniavsky:1981:CMA,
  author =       "Vladimir S. Cherniavsky",
  title =        "The computing memory another distributed computer
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "4",
  pages =        "22--24",
  month =        jun,
  year =         "1981",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thornton:1981:ASC,
  author =       "James E. Thornton",
  title =        "{8th Annual Symposium on Computer Architecture:
                 Heterogeneous Computer Architecture}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "4",
  pages =        "25--33",
  month =        jun,
  year =         "1981",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Staff:1981:ETP,
  author =       "Computer Architecture News Staff",
  title =        "Errata for two publications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "4",
  pages =        "34--34",
  month =        jun,
  year =         "1981",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lindsay:1981:CMM,
  author =       "Donald C. Lindsay",
  title =        "Cache memory for microprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "5",
  pages =        "6--13",
  month =        aug,
  year =         "1981",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1296947.1296948",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:16 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "A growth path for current microprocessors is suggested
                 which includes bus enhancements and cache memories. The
                 implications are examined, and several differences from
                 the mainframe world are pointed out.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kavi:1981:IAC,
  author =       "Krishna M. Kavi",
  title =        "Innovative architectures and commercial computers: a
                 summary of the panel discussion at {NCC 1981}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "5",
  pages =        "14--16",
  month =        aug,
  year =         "1981",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1296947.1296949",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:16 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The session was held on May 4, 1981 in Chicago at NCC
                 1981. The panelists were Harvey Cragon, Pat Goldberg,
                 Dave Patterson, Justin Rattner, Dean Earnest and Peter
                 Denning. Krishna Kavi was the moderator. A complete
                 report of the session is available and can be obtained
                 by writing to the Computer Science Department, P. O.
                 Box 44330, U.S.L., Lafayette, LA 70504.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jenevein:1981:EHS,
  author =       "R. M. Jenevein and ?. DeGroot and G. Jack Lipovski",
  title =        "Errata: ``{A} hardware support mechanism for
                 scheduling resources in parallel machine environment'':
                 (from {Proceedings of the 8th Annual Symposium on
                 Computer Architecture}, p. 57)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "5",
  pages =        "17--17",
  month =        aug,
  year =         "1981",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1296947.1296950",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:16 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yuen:1981:EPS,
  author =       "C. K. Yuen",
  title =        "Extending the power of short-wordlength processors by
                 means of context-dependent machine instructions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "6",
  pages =        "9--15",
  month =        oct,
  year =         "1981",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gottlieb:1981:CPP,
  author =       "Allan Gottlieb and Clyde P. Kruskal",
  title =        "Coordinating parallel processors: a partial
                 unification",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "6",
  pages =        "16--24",
  month =        oct,
  year =         "1981",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:1981:ESM,
  author =       "Anonymous",
  title =        "Errata: Structured machine design: an ongoing
                 experiment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "9",
  number =       "6",
  pages =        "25--25",
  month =        oct,
  year =         "1981",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McDowell:1982:PML,
  author =       "Charlie McDowell",
  title =        "Protection at the micromachine level",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "1",
  pages =        "4--8",
  month =        jan,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Feustel:1982:PPC,
  author =       "Edward A. Feustel",
  title =        "Protected procedure call on the {PRIME(TM)} machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "1",
  pages =        "9--22",
  month =        jan,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{El-Halabi:1982:SRD,
  author =       "Hossam El-Halabi and Dharma P. Agrawal",
  title =        "Some remarks on direct execution computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "1",
  pages =        "23--27",
  month =        jan,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fitzpatrick:1982:RAV,
  author =       "Daniel T. Fitzpatrick and John K. Foderaro and Manolis
                 G. H. Katevenis and Howard A. Landman and David
                 A. Patterson and James B. Peek and Zvi Peshkess and
                 Carlo H. S{\'e}quin and Robert W. Sherburne and Korbin
                 S. {Van Dyke}",
  title =        "A {RISCy} approach to {VLSI}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "1",
  pages =        "28--32",
  month =        jan,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rattner:1982:HSC,
  author =       "Justin Rattner",
  title =        "Hardware\slash software cooperation in the
                 {iAPX-432}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "1--1",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hennessy:1982:HST,
  author =       "John Hennessy and Norman Jouppi and Forest Baskett and
                 Thomas Gross and John Gill",
  title =        "Hardware\slash software tradeoffs for increased
                 performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "2--11",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rymarczyk:1982:CGP,
  author =       "James W. Rymarczyk",
  title =        "Coding guidelines for pipelined processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "12--19",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Johnsson:1982:OMP,
  author =       "Richard K. Johnsson and John D. Wick",
  title =        "An overview of the mesa processor architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "20--29",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Berenbaum:1982:OSL,
  author =       "Alan D. Berenbaum and Michael W. Condry and Priscilla
                 M. Lu",
  title =        "The operating system and language support features of
                 the {BELLMACTM-32} microprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "30--38",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Radin:1982:M,
  author =       "George Radin",
  title =        "The 801 minicomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "39--47",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ditzel:1982:RAF,
  author =       "David R. Ditzel and H. R. McLellan",
  title =        "Register allocation for free: {The C} machine stack
                 cache",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "48--56",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Harbison:1982:AAO,
  author =       "Samuel P. Harbison",
  title =        "An architectural alternative to optimizing compilers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "57--65",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lampson:1982:FPC,
  author =       "Butler W. Lampson",
  title =        "Fast procedure calls",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "66--76",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jones:1982:SPM,
  author =       "Douglas W. Jones",
  title =        "Systematic protection mechanism design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "77--80",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reed:1982:GPM,
  author =       "Karl Reed",
  title =        "On a general property of memory mapping tables",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "81--86",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cook:1982:EIO,
  author =       "Robert P. Cook and Nitin Donde",
  title =        "An experiment to improve operand addressing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "87--91",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fusaoka:1982:CCH,
  author =       "Akira Fusaoka and Masaharu Hirayama",
  title =        "Compiler chip: a hardware implementation of compiler",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "92--95",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rau:1982:ASE,
  author =       "B. R. Rau and C. D. Glaeser and E. M. Greenawalt",
  title =        "Architectural support for the efficient generation of
                 code for horizontal architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "96--99",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McLear:1982:GCD,
  author =       "R. E. McLear and D. M. Scheibelhut and E. Tammaru",
  title =        "Guidelines for creating a debuggable processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "100--106",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wilkes:1982:HSM,
  author =       "M. V. Wilkes",
  title =        "Hardware support for memory protection: {Capability}
                 implementations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "107--116",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pollack:1982:SAM,
  author =       "Fred J. Pollack and George W. Cox and Dan W.
                 Hammerstrom and Kevin C. Kahn and Konrad K. Lai and
                 Justin R. Rattner",
  title =        "Supporting {Ada} memory management in the {iAPX-432}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "117--131",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sansonnet:1982:DEL,
  author =       "J. P. Sansonnet and M. Castan and C. Percebois and D.
                 Botella and J. Perez",
  title =        "Direct execution of {Lisp} on a list-directed
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "132--139",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Johnson:1982:SRA,
  author =       "Mark Scott Johnson",
  title =        "Some requirements for architectural support of
                 software debugging",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "140--148",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Middelburg:1982:EPA,
  author =       "C. A. Middelburg",
  title =        "The effect of the {PDP-11} architecture on code
                 generation for chill",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "149--157",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sweet:1982:EAM,
  author =       "Richard E. Sweet and James G. {Sandman, Jr.}",
  title =        "Empirical analysis of the mesa instruction set",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "158--166",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McDaniel:1982:AMI,
  author =       "Gene McDaniel",
  title =        "An analysis of a mesa instruction set using dynamic
                 instruction frequencies",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "167--176",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wiecek:1982:CSV,
  author =       "Cheryl A. Wiecek",
  title =        "A case study of {VAX-11} instruction set usage for
                 compiler execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "177--184",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Maekawa:1982:FSA,
  author =       "Mamoru Maekawa and Ken Sakamura and Chiaki Ishikawa",
  title =        "Firmware structure and architectural support for
                 monitors, vertical migration and user
                 microprogramming",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "185--194",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kamibayashi:1982:HOS,
  author =       "N. Kamibayashi and H. Ogawana and K. Nagayama and H.
                 Aiso",
  title =        "{Heart}: an operating system nucleus machine
                 implemented by firmware",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "195--204",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ahuja:1982:MMA,
  author =       "Sudhir R. Ahuja and Abhaya Asthana",
  title =        "A multi-microprocessor architecture with hardware
                 support for communication and scheduling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "2",
  pages =        "205--209",
  month =        mar,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:44 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Patterson:1982:RAH,
  author =       "David A. Patterson and Richard S. Piepho",
  title =        "{RISC} assessment: a high-level language experiment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "3--8",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Clark:1982:MAI,
  author =       "Douglas W. Clark and Henry M. Levy",
  title =        "Measurement and analysis of instruction use in the
                 {VAX-11\slash 780}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "9--17",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kavi:1982:HAP,
  author =       "Krishna Kavi and Boumediene Belkhouche and Evelyn
                 Bullard and Lois Delcambre and Stephen Nemecek",
  title =        "{HLL} architectures: {Pitfalls} and predilections",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "18--23",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gottlieb:1982:NUD,
  author =       "Allan Gottlieb and Ralph Grishman and Clyde P. Kruskal
                 and Kevin P. McAuliffe and Larry Rudolph and Marc
                 Snir",
  title =        "The {NYU Ultracomputer}---designing a {MIMD},
                 shared-memory parallel machine (extended abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "27--42",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chu:1982:VAH,
  author =       "King-Hang Chu and King-Sun Fu",
  title =        "{VLSI} architectures for high speed recognition of
                 context-free languages and finite-state languages",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "43--49",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Franklin:1982:ACC,
  author =       "Mark A. Franklin and Donald F. Wann",
  title =        "Asynchronous and clocked control structures for {VLSI}
                 based interconnection networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "50--59",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McMillen:1982:PFT,
  author =       "Robert J. McMillen and Howard Jay Siegel",
  title =        "Performance and fault tolerance improvements in the
                 {Inverse Augmented Data Manipulator} network",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "63--72",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Parker:1982:GNM,
  author =       "D. S. Parker and C. S. Raghavendra",
  title =        "The {Gamma} network: a multiprocessor interconnection
                 network with redundant paths",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "73--80",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jenevein:1982:CPR,
  author =       "R. M. Jenevein and J. C. Browne",
  title =        "A control processor for a reconfigurable array
                 computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "81--89",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bhuyan:1982:GCP,
  author =       "Laxmi N. Bhuyan and Dharma P. Agrawal",
  title =        "A general class of processor interconnection
                 strategies",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "90--98",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Burkowski:1982:ISD,
  author =       "F. J. Burkowski",
  title =        "Instruction set design issues relating to a static
                 dataflow computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "101--111",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1982:DAE,
  author =       "James E. Smith",
  title =        "Decoupled access\slash execute computer
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "112--119",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Caluwaerts:1982:DFA,
  author =       "L. J. Caluwaerts and J. Debacker and J. A.
                 Peperstraete",
  title =        "A data flow architecture with a paged memory system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "120--127",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rau:1982:ECG,
  author =       "B. Ramakrishna Rau and Christopher D. Glaeser and
                 Raymond L. Picard",
  title =        "Efficient code generation for horizontal
                 architectures: {Compiler} techniques and architectural
                 support",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "131--139",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Barton:1982:SNH,
  author =       "Gene C. Barton",
  title =        "{Sentry}: a novel hardware implementation of classic
                 operating system mechanisms",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "140--147",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Abramovici:1982:LSM,
  author =       "M. Abramovici and Y. H. Levendel and P. R. Menon",
  title =        "A logic simulation machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "148--157",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dasgupta:1982:TFL,
  author =       "Subrata Dasgupta and Marius Olafsson",
  title =        "Towards a family of languages for the design and
                 implementation of machine architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "158--167",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1982:RPD,
  author =       "Yann-Hang Lee and Kang G. Shin",
  title =        "Rollback propagation detection and performance
                 evaluation of {FTMR2M}---a fault-tolerant
                 multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "171--180",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lin:1982:DFT,
  author =       "Woei Lin and Chuan-lin Wu",
  title =        "Design of a $ 2 \times 2 $ fault-tolerant switching
                 element",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "181--189",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fussell:1982:FTW,
  author =       "Donald Fussell and Peter Varman",
  title =        "Fault-tolerant wafer-scale architectures for {VLSI}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "190--198",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pramanik:1982:DF,
  author =       "Sakti Pramanik",
  title =        "Database filters",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "201--210",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tokoro:1982:SSI,
  author =       "Mario Tokoro and Takashi Takizuka",
  title =        "On the semantic structure of information --- a
                 proposal of the abstract storage architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "211--217",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dohi:1982:HSA,
  author =       "Yasunori Dohi and Akira Suzuki and Noriyuki Matsui",
  title =        "Hardware sorter and its application to data base
                 machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "218--225",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Treleaven:1982:RCA,
  author =       "Philip C. Treleaven and Richard P. Hopkins",
  title =        "A recursive computer architecture for {VLSI}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "229--238",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Castan:1982:HRP,
  author =       "M. Castan and E. I. Organick",
  title =        "{$ \mu $3L}: an {HLL-RISC} processor for parallel
                 execution of {FP}-language programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "239--247",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hommes:1982:HSC,
  author =       "F. Hommes",
  title =        "The heap\slash substitution concept --- an
                 implementation of functional operations on data
                 structures for a reduction machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "248--256",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reynolds:1982:SRA,
  author =       "Paul F. {Reynolds, Jr.}",
  title =        "A shared resource algorithm for distributed
                 simulation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "259--266",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jain:1982:DPT,
  author =       "Bijendra N. Jain",
  title =        "Duplication of packets and their detection in {X.25}
                 communication protocols",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "267--273",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Markenscoff:1982:MPS,
  author =       "Pauline Markenscoff",
  title =        "A multiple processor system for real time control
                 tasks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "274--280",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Miller:1982:HMD,
  author =       "Leslie Jill Miller",
  title =        "A heterogeneous multiprocessor design and the
                 distributed scheduling of its task group workload",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "283--290",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goble:1982:DPV,
  author =       "George H. Goble and Michael H. Marsh",
  title =        "A dual processor {VAX 11\slash 780}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "291--298",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dubois:1982:ECC,
  author =       "Michel Dubois and Fay{\.e} A. Briggs",
  title =        "Effects of cache coherency in multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "299--308",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mudge:1982:PAC,
  author =       "T. N. Mudge and B. A. Makrucki",
  title =        "Probabilistic analysis of a crossbar switch",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "311--320",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Levitan:1982:FEN,
  author =       "Steven P. Levitan and Caxton C. Foster",
  title =        "Finding an extremum in a network",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "321--325",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Premkumar:1982:RAR,
  author =       "U. V. Premkumar and J. C. Browne",
  title =        "Resource allocation in rectangular {SW} banyans",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "326--333",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:1982:LA,
  author =       "Anonymous",
  title =        "List of authors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "3",
  pages =        "335--335",
  month =        apr,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:52 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mayer:1982:ABB,
  author =       "Alastair J. W. Mayer",
  title =        "The architecture of the {Burroughs B5000}: 20 years
                 later and still ahead of the times?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "4",
  pages =        "3--10",
  month =        jun,
  year =         "1982",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/641542.641543",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Brakefield:1982:OSA,
  author =       "James C. Brakefield",
  title =        "From the other side of the {Atlantic}: how to improve
                 upon the {MU5} design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "4",
  pages =        "11--16",
  month =        jun,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hansen:1982:PEI,
  author =       "Paul M. Hansen and Mark A. Linton and Robert N. Mayo
                 and Marguerite Murphy and David A. Patterson",
  title =        "A performance evaluation of the {Intel iAPX 432}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "4",
  pages =        "17--26",
  month =        jun,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Huguet:1982:PPS,
  author =       "Miquel Huguet",
  title =        "The protection of the processor status word of the
                 {PDP-11\slash 60}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "4",
  pages =        "27--30",
  month =        jun,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Brakefield:1982:JWO,
  author =       "James Brakefield",
  title =        "Just what is an op-code?: or a universal computer
                 design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "4",
  pages =        "31--34",
  month =        jun,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:07 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Knott:1982:FDA,
  author =       "J. D. Knott and T. W. Crockett",
  title =        "Fair dynamic arbitration for a multiprocessor
                 communications bus",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "5",
  pages =        "4--9",
  month =        sep,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Larus:1982:CMA,
  author =       "James R. Larus",
  title =        "A comparison of microcode, assembly code, and
                 high-level languages on the {VAX-11} and {RISC I}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "5",
  pages =        "10--15",
  month =        sep,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Patterson:1982:PEI,
  author =       "David A. Patterson",
  title =        "A performance evaluation of the {Intel 80286}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "5",
  pages =        "16--18",
  month =        sep,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Egan:1982:EVC,
  author =       "Rod Egan",
  title =        "The effect of {VLSI} on computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "5",
  pages =        "19--22",
  month =        sep,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Benzie:1982:BRR,
  author =       "Thomas Benzie",
  title =        "Book reviews: Review of {{\em Microcomputer
                 Architecture and Programming\/}} by {John F. Wakerly,
                 John Wiley \& Sons, Inc., 1981}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "5",
  pages =        "23--23",
  month =        sep,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Levy:1982:UBM,
  author =       "Henry M. Levy and Douglas W. Clark",
  title =        "On the use of benchmarks for measuring system
                 performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "6",
  pages =        "5--8",
  month =        dec,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schulthess:1982:ONA,
  author =       "Peter Schulthess and Fritz Vonaesch",
  title =        "{OPA}: a new architecture for {Pascal-like}
                 languages",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "6",
  pages =        "9--20",
  month =        dec,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Brakefield:1982:TI,
  author =       "James C. Brakefield",
  title =        "Talk on interpreters",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "6",
  pages =        "21--28",
  month =        dec,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Doran:1982:MFC,
  author =       "D. W. Doran",
  title =        "Main frame computer trends",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "10",
  number =       "6",
  pages =        "29--44",
  month =        dec,
  year =         "1982",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gajski:1983:CLS,
  author =       "Daniel Gajski and David Kuck and Duncan Lawrie and
                 Ahmed Sameh",
  title =        "{CEDAR}: a large scale multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "1",
  pages =        "7--11",
  month =        mar,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{French:1983:TDF,
  author =       "Elaine French and Hugh Glaser",
  title =        "{TUKI}: a data flow processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "1",
  pages =        "12--18",
  month =        mar,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Marovac:1983:SAD,
  author =       "Nenad Marovac",
  title =        "A systematic approach to the design and implementation
                 of a computer instruction set",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "1",
  pages =        "19--24",
  month =        mar,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cragon:1983:EIS,
  author =       "Harvey Cragon",
  title =        "Executable instruction set specification",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "1",
  pages =        "25--43",
  month =        mar,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Colwell:1983:PTR,
  author =       "Robert P. Colwell and Charles Y. Hitchcock and E.
                 Douglas Jensen",
  title =        "Peering through the {RISC\slash CISC} fog: an outline
                 of research",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "1",
  pages =        "44--50",
  month =        mar,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gorsline:1983:RAC,
  author =       "G. W. Gorsline",
  title =        "Review of {{\em Advances in Computer Architecture\/}}
                 by {Glenford J. Myers, John Wiley \& Sons, Inc. 1982}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "1",
  pages =        "55--55",
  month =        mar,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sachs:1983:BRR,
  author =       "M. W. Sachs",
  title =        "Book reviews: Review of {{\em Microcomputer
                 Interfacing\/}} by {G. Jack Lipovski, Lexington Books
                 1980}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "1",
  pages =        "55--55",
  month =        mar,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Abramson:1983:HSP,
  author =       "David Abramson and John Rosenberg",
  title =        "Hardware support for program debuggers in a paged
                 virtual memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "2",
  pages =        "8--19",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:42 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Frailey:1983:WLC,
  author =       "Dennis J. Frailey",
  title =        "Word length of a computer architecture definitions and
                 applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "2",
  pages =        "20--26",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:42 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hollaar:1983:BRR,
  author =       "Lee A. Hollaar",
  title =        "Book reviews: Review of {{\em Computer Design\/}} by
                 {Glen G. Langdon, Computeach Press}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "2",
  pages =        "27--28",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:42 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wilkes:1983:SPS,
  author =       "Maurice V. Wilkes",
  title =        "Size, power, and speed (keynote address)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "2--4",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Giloi:1983:TTC,
  author =       "W. K. Giloi",
  title =        "Towards a taxonomy of computer architecture based on
                 the machine data type view",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "6--15",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Avizienis:1983:FTF,
  author =       "Algirdas Avi{\v{z}}ienis",
  title =        "Framework for a taxonomy of fault-tolerance attributes
                 in computer systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "16--21",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pehrson:1983:CID,
  author =       "Bj{\"o}rn Pehrson and Joachim Parrow",
  title =        "Caddie an interactive design environment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "24--31",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dasgupta:1983:VCA,
  author =       "Subrata Dasgupta",
  title =        "On the verification of computer architectures using an
                 architecture description language",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "32--38",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{King:1983:RSC,
  author =       "Richard M. King",
  title =        "Research on synthesis of concurrent computing systems
                 (extended abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "39--46",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fisher:1983:APP,
  author =       "Allan L. Fisher and H. T. Kung and Louis M. Monier and
                 Yasunori Dohi",
  title =        "Architecture of the {PSC}---a programmable systolic
                 chip",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "48--53",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fisher:1983:SLV,
  author =       "Allan L. Fisher and H. T. Kung",
  title =        "Synchronizing large {VLSI} processor arrays",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "54--58",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wagner:1983:BVM,
  author =       "Robert A. Wagner",
  title =        "The {Boolean Vector Machine [BVM]}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "59--66",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bonuccelli:1983:VTM,
  author =       "M. A. Bonuccelli and E. Lodi and F. Luccio and P.
                 Maestrini and L. Pagli",
  title =        "A {VLSI} tree machine for relational data bases",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "67--73",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Caluwaerts:1983:ISD,
  author =       "L. J. Caluwaerts and J. Debacker and J. A.
                 Peperstraete",
  title =        "Implementing streams on a data flow computer system
                 with paged memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "76--83",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Requa:1983:PDF,
  author =       "Joseph E. Requa",
  title =        "The {Piecewise Data Flow} architecture control flow
                 and register management",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "84--89",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tokoro:1983:WSC,
  author =       "Mario Tokoro and J. R. Jagannathan and Hideki
                 Sunahara",
  title =        "On the working set concept for data-flow machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "90--97",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Marczynski:1983:DDS,
  author =       "R. W. Marczy{\'n}ski and J. Milewski",
  title =        "A data driven system based on a microprogrammed
                 processor module",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "98--106",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Patterson:1983:AVI,
  author =       "David A. Patterson and Phil Garrison and Mark Hill and
                 Dimitris Lioupis and Chris Nyberg and Tim Sippel and
                 Korbin {Van Dyke}",
  title =        "Architecture of a {VLSI} instruction cache for a
                 {RISC}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "108--116",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yeh:1983:PSC,
  author =       "Phil C. C. Yeh and Janak H. Patel and Edward S.
                 Davidson",
  title =        "Performance of shared cache for parallel-pipelined
                 computer systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "117--123",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goodman:1983:UCM,
  author =       "James R. Goodman",
  title =        "Using cache memory to reduce processor-memory
                 traffic",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "124--131",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1983:SIC,
  author =       "James E. Smith and James R. Goodman",
  title =        "A study of instruction cache organizations and
                 replacement policies",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "132--137",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fisher:1983:VLI,
  author =       "Joseph A. Fisher",
  title =        "{Very Long Instruction Word} architectures and the
                 {ELI-512}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "140--150",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tomita:1983:UML,
  author =       "Shinji Tomita and Kiyoshi Shibayama and Toshiaki
                 Kitamura and Toshiyuki Nakata and Hiroshi Hagiwara",
  title =        "A user-microprogrammable, local host computer with
                 low-level parallelism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "151--157",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gumpertz:1983:CTE,
  author =       "Richard H. Gumpertz",
  title =        "Combining tags with error codes",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "160--165",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Park:1983:FDB,
  author =       "Young Gil Park and Jung Wan Cho",
  title =        "Fault diagnosis of bit-slice processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "166--172",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fiol:1983:LDI,
  author =       "M. A. Fiol and I. Alegre and J. L. A. Yebra",
  title =        "Line digraph iterations and the (d,k) problem for
                 directed graphs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "174--177",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Opper:1983:RAR,
  author =       "Eli Opper and Miroslaw Malek and G. Jack Lipovski",
  title =        "Resource allocation in rectangular {CC}-banyans",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "178--184",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sovis:1983:UTS,
  author =       "Franti{\v{s}}ek Sovi{\v{s}}",
  title =        "Uniform theory of the shuffle-exchange type
                 permutation networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "185--191",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Srini:1983:ACA,
  author =       "Vason P. Srini and Jorge F. Asenjo",
  title =        "Analysis of {Cray-1S} architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "194--206",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jordan:1983:PMH,
  author =       "Harry F. Jordan",
  title =        "Performance measurements on {HEP} --- a pipelined
                 {MIMD} computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "207--212",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Amano:1983:SSM,
  author =       "Hideharu Amano and Takaichi Yoshida and Hideo Aiso",
  title =        "{(SM)2-Sparse Matrix Solving Machine}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "213--220",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Krishnan:1983:ESC,
  author =       "R. Kalyana Krishnan and A. K. Rajasekar and C. S.
                 Moghe",
  title =        "An experimental system for {Computer Science}
                 instruction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "222--227",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kronlof:1983:ECM,
  author =       "Klaus Kronl{\"o}f",
  title =        "Execution control and memory management of a {Data
                 Flow Signal Processor}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "230--235",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kishi:1983:DDD,
  author =       "Masasuke Kishi and Hiroshi Yasuhara and Yasusuke
                 Kawamura",
  title =        "{DDDP}---a {Distributed Data Driven Processor}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "236--242",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Takahashi:1983:DFP,
  author =       "Naohisa Takahashi and Makoto Amamiya",
  title =        "A data flow processor array system: {Design} and
                 analysis",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "243--250",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pier:1983:RDH,
  author =       "Kenneth A. Pier",
  title =        "A retrospective on the {Dorado}, a high-performance
                 personal computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "252--269",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dugan:1983:SEA,
  author =       "Robert J. Dugan",
  title =        "{System\slash 370} extended architecture: a program
                 view of the channel subsystem",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "270--276",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Norton:1983:AIM,
  author =       "Richard L. Norton and Jacob A. Abraham",
  title =        "Adaptive interpretation as a means of exploiting
                 complex instruction sets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "277--282",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kumar:1983:SSC,
  author =       "Manoj Kumar and Daniel M. Dias and J. R. Jump",
  title =        "Switching strategies in a class of packet switching
                 networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "284--300",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wah:1983:CSD,
  author =       "Benjamin W. Wah",
  title =        "A comparative study of distributed resource sharing on
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "301--308",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fuchs:1983:CED,
  author =       "W. Kent Fuchs and Jacob A. Abraham and Kuang-Hua
                 Huang",
  title =        "Concurrent error detection in {VLSI} interconnection
                 networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "309--315",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Giloi:1983:HFD,
  author =       "W. K. Giloi and P. Behr",
  title =        "Hierarchical function distribution --- a design
                 principle for advanced multicomputer architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "318--325",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stringa:1983:EIE,
  author =       "Luigi Stringa",
  title =        "{EMMA}-an industrial experience on large
                 multiprocessing architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "326--333",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Philipson:1983:CSM,
  author =       "Lars Philipson and Bo Nilsson and Bjorn Breidegard",
  title =        "A communication structure for a multiprocessor
                 computer with distributed global memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "334--340",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hayashi:1983:AHP,
  author =       "Hiromu Hayashi and Akira Hattori and Haruo Akimoto",
  title =        "{ALPHA}---a high-performance {LISP} machine equipped
                 with a new stack structure and garbage collection
                 system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "342--348",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Umeyama:1983:PEM,
  author =       "Shinji Umeyama and Koichiro Tamura",
  title =        "A parallel execution model of logic programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "349--355",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schmittgen:1983:SAC,
  author =       "Claudia Schmittgen and Werner Kluge",
  title =        "A system architecture for the concurrent evaluation of
                 applicative program expressions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "356--362",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yamaguchi:1983:PEL,
  author =       "Yoshinori Yamaguchi and Kenji Toda and Toshitsugu
                 Yuba",
  title =        "A performance evaluation of a {Lisp}-based data-driven
                 machine {(EM-3)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "363--369",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tanimoto:1983:PAP,
  author =       "Steven L. Tanimoto",
  title =        "A pyramidal approach to parallel processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "372--378",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gaillat:1983:DPP,
  author =       "G{\'e}rard Gaillat",
  title =        "The design of a parallel processor for image
                 processing on-board satellites: an application oriented
                 approach",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "379--386",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nishimura:1983:LPP,
  author =       "Hitoshi Nishimura and Hiroshi Ohno and Toru Kawata and
                 Isao Shirakawa and Koichi Omura",
  title =        "{Links-1} --- a parallel pipelined multimicrocomputer
                 system for image creation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "387--394",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ericsson:1983:LSM,
  author =       "T. Ericsson and P. E. Danielsson",
  title =        "{LIPP} --- a {SIMD} multiprocessor architecture for
                 image processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "395--400",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Treleaven:1983:NGC,
  author =       "Philip C. Treleaven",
  title =        "The new generation of computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "402--409",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Uchida:1983:IMS,
  author =       "Shunichi Uchida",
  title =        "Inference machine: {From} sequential to parallel",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "410--416",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Moto-oka:1983:OFG,
  author =       "Tohru Moto-oka",
  title =        "Overview to the {Fifth Generation Computer System}
                 project",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "417--422",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Murakami:1983:RDB,
  author =       "Kunio Murakami and Takeo Kakuta and Nobuyoshi Miyazaki
                 and Shigeki Shibayama and Haruo Yokota",
  title =        "A relational data base machine: {First} step to
                 knowledge base machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "423--425",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Arvind:1983:CMN,
  author =       "Arvind and Robert A. Iannucci",
  title =        "A critique of multiprocessing {von Neumann} style",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "3",
  pages =        "426--436",
  month =        jun,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hill:1983:ACM,
  author =       "Dwight D. Hill",
  title =        "An analysis of {C} machine support for other
                 block-structured languages",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "4",
  pages =        "6--16",
  month =        sep,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:10 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Marovac:1983:IID,
  author =       "Nenad Marovac",
  title =        "On interprocess interaction in distributed
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "4",
  pages =        "17--22",
  month =        sep,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:10 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schalkoff:1983:TED,
  author =       "Robert J. Schalkoff",
  title =        "Towards an efficient, dedicated architecture for a
                 {Digital Geometric Image Transformer (DGIT)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "4",
  pages =        "23--29",
  month =        sep,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:10 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Plotkin:1983:TSA,
  author =       "Arieh Plotkin and Daniel Tabak",
  title =        "A {Tree Structured Architecture} for semantic gap
                 reduction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "4",
  pages =        "30--44",
  month =        sep,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:10 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wilkes:1983:KJI,
  author =       "Maurice V. Wilkes",
  title =        "Keeping jump instructions out of the pipeline of a
                 {RISC}-like computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "5",
  pages =        "5--7",
  month =        dec,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:17 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jones:1983:PM,
  author =       "Jeremy Jones",
  title =        "Puzzling with microcode",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "5",
  pages =        "8--12",
  month =        dec,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:17 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Amsbury:1983:CSA,
  author =       "Wayne Amsbury",
  title =        "A code-splitting algorithm",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "5",
  pages =        "13--21",
  month =        dec,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:17 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dongarra:1983:PVC,
  author =       "Jack J. Dongarra",
  title =        "Performance of various computers using standard linear
                 equations software in a {Fortran} environment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "5",
  pages =        "22--27",
  month =        dec,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:17 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bhujade:1983:DAC,
  author =       "M. R. Bhujade",
  title =        "On the design of {Always Compatible Instruction Set
                 Architecture(ACISA)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "11",
  number =       "5",
  pages =        "28--30",
  month =        dec,
  year =         "1983",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:17 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Heath:1984:RER,
  author =       "J. L. Heath",
  title =        "Re-evaluation of the {RISC I}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "1",
  pages =        "3--10",
  month =        mar,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Patterson:1984:RW,
  author =       "David A. Patterson",
  title =        "{RISC} watch",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "1",
  pages =        "11--19",
  month =        mar,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Beeler:1984:BBB,
  author =       "Michael Beeler",
  title =        "Beyond the {Baskett} benchmark",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "1",
  pages =        "20--31",
  month =        mar,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Feustel:1984:PEP,
  author =       "Edward A. Feustel",
  title =        "Process exchange on the {PR1ME} family of computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "1",
  pages =        "32--43",
  month =        mar,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fenwick:1984:AOA,
  author =       "P. M. Fenwick",
  title =        "Addressing operations for automatic data structure
                 accessing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "1",
  pages =        "44--57",
  month =        mar,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yuen:1984:SAI,
  author =       "C. K. Yuen",
  title =        "Some applications of the implicit register reference",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "1",
  pages =        "58--63",
  month =        mar,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kavi:1984:AQ,
  author =       "Krishna M. Kavi and K. Krishnamohan",
  title =        "Architecture quality",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "1",
  pages =        "64--72",
  month =        mar,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Agrawal:1984:BHH,
  author =       "Dharma P. Agrawal and Winser E. Alexander",
  title =        "{B-HIVE}: a heterogeneous, interconnected, versatile
                 and expandable multicomputer system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "2",
  pages =        "7--13",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Burkowski:1984:VAM,
  author =       "F. J. Burkowski",
  title =        "A vector and array multiprocessor extension of the
                 sylvan architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "4--11",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kapauan:1984:PPC,
  author =       "Alejandro Kapauan and J. Timothy Field and Dennis B.
                 Gannon and Lawrence Snyder",
  title =        "The {Pringle} parallel computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "12--20",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yasrebi:1984:SAS,
  author =       "Mehrad Yasrebi and G. J. Lipovski",
  title =        "A state-of-the-art {SIMD} two-dimensional {FFT} array
                 processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "21--27",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ma:1984:ARS,
  author =       "Y. W. Ma and R. Krishnamurti",
  title =        "The architecture of {Replica}: a special-purpose
                 computer system for active multi-sensory perception of
                 $3$-dimensional objects",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "30--37",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goldwasser:1984:GOD,
  author =       "Samuel M. Goldwasser",
  title =        "A generalized object display processor architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "38--47",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kawakami:1984:SPL,
  author =       "Katsura Kawakami and Shigeo Shimazaki",
  title =        "A special purpose {LSI} processor using the {DDA}
                 algorithm for image transformation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "48--54",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wah:1984:SMM,
  author =       "Benjamin W. Wah and Guo-Jie Li and Chee-Fen Yu",
  title =        "The status of {MANIP} --- a multicomputer architecture
                 for solving, combinatorial extremum-search problems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "56--63",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gonzalez-Rubio:1984:SFP,
  author =       "R. Gonzalez-Rubio and J. Rohmer and D. Terral",
  title =        "The {SCHUSS} filter: a processor for non-numerical
                 data processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "64--73",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ebeling:1984:DIV,
  author =       "Carl Ebeling and Andrew Palay",
  title =        "The design and implementation of a {VLSI} chess move
                 generator",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "74--80",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1984:PAC,
  author =       "Manjai Lee and Chuan-lin Wu",
  title =        "Performance analysis of circuit switching, baseline
                 interconnection networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "82--90",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kruskal:1984:IBS,
  author =       "Clyde P. Kruskal and Marc Snir",
  title =        "The importance of being square",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "91--98",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chin:1984:CPM,
  author =       "Chi-Yuan Chin and Kai Hwang",
  title =        "Connection principles for multipath, packet switching
                 networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "99--108",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Weiss:1984:IIL,
  author =       "Shlomo Weiss and James E. Smith",
  title =        "Instruction issue logic for pipelined supercomputers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "110--118",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wedig:1984:RBI,
  author =       "Robert G. Wedig and Marc A. Rose",
  title =        "The reduction of branch instruction execution overhead
                 using structured control flow",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "119--125",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Banerjee:1984:FEL,
  author =       "Utpal Banerjee and Daniel D. Gajski",
  title =        "Fast execution of loops with if statements",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "126--132",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gajski:1984:PPR,
  author =       "Daniel Gajski and Won Kim and Shinya Fushimi",
  title =        "A parallel pipelined relational query processor: an
                 architectural overview",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "134--141",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Somani:1984:EVD,
  author =       "Arun K. Somani and Vinod K. Agarwal",
  title =        "An efficient {VLSI} dictionary machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "142--150",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fisher:1984:DMS,
  author =       "Allan L. Fisher",
  title =        "Dictionary machines with a small number of
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "151--156",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hill:1984:EEC,
  author =       "Mark D. Hill and Alan Jay Smith",
  title =        "Experimental evaluation of on-chip microprocessor
                 cache memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "158--166",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goodman:1984:USC,
  author =       "James R. Goodman and Men-chow Chiang",
  title =        "The use of static column {RAM} as a memory hierarchy",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "167--173",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Haikala:1984:CHRa,
  author =       "I. J. Haikala",
  title =        "Cache hit ratios with geometric task switch
                 intervals",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "175--175",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ishikawa:1984:DOO,
  author =       "Yutaka Ishikawa and Mario Tokoro",
  title =        "The design of an object oriented architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "178--187",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ungar:1984:ASS,
  author =       "David Ungar and Ricki Blau and Peter Foley and Dain
                 Samples and David Patterson",
  title =        "Architecture of {SOAR}: {Smalltalk} on a {RISC}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "188--197",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bose:1984:DIS,
  author =       "Pradip Bose and Edward S. Davidson",
  title =        "Design of instruction set architectures for support of
                 high-level languages",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "198--206",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Quinton:1984:ASS,
  author =       "Patrice Quinton",
  title =        "Automatic synthesis of systolic arrays from uniform
                 recurrent equations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "208--214",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhang:1984:MDS,
  author =       "Chang nian Zhang and David Y. Y. Yun",
  title =        "Multi-dimensional systolic networks, for {Discrete
                 Fourier Transform}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "215--222",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fortes:1984:DBL,
  author =       "J. A. B. Fortes and D. I. Moldovan",
  title =        "Data broadcasting in linearly scheduled array
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "224--231",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ramakrishnan:1984:MMM,
  author =       "I. V. Ramakrishnan and P. J. Varman",
  title =        "Modular matrix multiplication on a linear array",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "232--238",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rao:1984:JEE,
  author =       "T. R. N. Rao",
  title =        "Joint encryption and error correction schemes",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "240--241",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bose:1984:UEC,
  author =       "Bella Bose",
  title =        "Unidirectional error correction\slash detection for
                 {VLSI} memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "242--244",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chen:1984:ECC,
  author =       "C. L. Chen",
  title =        "Error-correcting codes for semiconductor memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "245--247",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ghaffar:1984:SEC,
  author =       "Khaled Abdel Ghaffar and Robert J. McEliece",
  title =        "Soft error correction for increased densities in
                 {VLSI} memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "248--250",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{King:1984:CSA,
  author =       "Richard M. King and Robert A. Wagner",
  title =        "Combining speed with alpha-particle induced memory,
                 error tolerance in a large {Boolean} vector machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "251--253",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bhuyan:1984:PLC,
  author =       "Laxmi N. Bhuyan",
  title =        "On the performance of loosely coupled
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "256--262",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mehrotra:1984:STD,
  author =       "Ravi Mehrotra and Sarosh N. Talukdar",
  title =        "Scheduling of tasks for distributed processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "263--270",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kavi:1984:MRD,
  author =       "Krishna M. Kavi and Edward W. Banios and Bruce D.
                 Shriver",
  title =        "Message repository definitional facility: an
                 architectural model for interprocess communication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "271--278",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Banerjee:1984:FSA,
  author =       "Prithviraj Banerjee and Jacob A. Abraham",
  title =        "Fault-secure algorithms for multiple-processor
                 systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "279--287",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bic:1984:ELP,
  author =       "Lubomir Bic",
  title =        "Execution of logic programs on a dataflow
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "290--296",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rudd:1984:HPF,
  author =       "W. G. Rudd and Duncan A. Buell and Donald M.
                 Chiarulli",
  title =        "A high performance factoring machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "297--300",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Emer:1984:CPP,
  author =       "Joel S. Emer and Douglas W. Clark",
  title =        "A characterization of processor performance in the
                 {VAX-11\slash 780}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "301--310",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Moeller:1984:PPP,
  author =       "W. D. Moeller and G. Sandweg",
  title =        "The peripheral processor {PP4}, a highly regular
                 {VLSI} processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "312--318",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Philipson:1984:VBD,
  author =       "Lars Philipson",
  title =        "{VLSI} based design principles for {MIMD}
                 multiprocessor computers with distributed memory
                 management",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "319--327",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Samatham:1984:MNS,
  author =       "M. R. Samatham and D. K. Pradhan",
  title =        "A multiprocessor network suitable for single-chip
                 {VLSI} implementation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "328--339",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rudolph:1984:DDC,
  author =       "Larry Rudolph and Zary Segall",
  title =        "Dynamic decentralized cache schemes for {MIMD}
                 parallel processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "340--347",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Papamarcos:1984:LOC,
  author =       "Mark S. Papamarcos and Janak H. Patel",
  title =        "A low-overhead coherence solution for multiprocessors
                 with private cache memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "348--354",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Archibald:1984:ESC,
  author =       "James Archibald and Jean Loup Baer",
  title =        "An economical solution to the cache coherence
                 problem",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "355--362",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Haikala:1984:CHRb,
  author =       "Ilkka J. Haikala",
  title =        "Cache hit ratios with geometric task switch
                 intervals",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "3",
  pages =        "364--371",
  month =        jun,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chesley:1984:WM,
  author =       "Gilman D. Chesley",
  title =        "A wafer microcomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "4",
  pages =        "4--6",
  month =        sep,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:10 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Siegel:1984:PRP,
  author =       "Howard Jay Siegel and Thomas Schwederski and Nathaniel
                 J. {Davis IV} and James T. Kuehn",
  title =        "{PASM}: a reconfigurable parallel system for image
                 processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "4",
  pages =        "7--19",
  month =        sep,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:10 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Aslam:1984:MDC,
  author =       "Javaid Aslam",
  title =        "Methodology for designing a computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "5",
  pages =        "4--11",
  month =        dec,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:18 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Graham:1984:PAS,
  author =       "Peter C. J. Graham",
  title =        "Providing architectural support for expert systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "12",
  number =       "5",
  pages =        "12--18",
  month =        dec,
  year =         "1984",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:18 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dongarra:1985:PVC,
  author =       "Jack J. Dongarra",
  title =        "Performance of various computers using standard linear
                 equations software in a {Fortran} environment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "1",
  pages =        "3--11",
  month =        mar,
  year =         "1985",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1296930.1296931",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:22 MDT 2008",
  bibsource =    "ftp://ftp.math.utah.edu/pub/bibnet/authors/d/dongarra-jack-j.bib;
                 http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This note compares the performance of different
                 computer systems while solving dense systems of linear
                 equations using the LINPACK software in a Fortran
                 environment. About 100 computers, ranging from a CRAY
                 X-MP to the 68000 based systems such as the Apollo and
                 SUN Workstations to IBM PC's, are compared.",
  acknowledgement = ack-nhfb,
  classcodes =   "C4140 (Linear algebra); C5470 (Performance evaluation
                 and testing); C7310 (Mathematics computing)",
  corpsource =   "Div. of Math. and Comput. Sci., Argonne Nat. Lab., IL,
                 USA",
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "68000 based; Apollo workstations; Cray X-MP; dense
                 systems; evaluation; FORTRAN environment; IBM PCs;
                 linear algebra; linear equations; LINPACK; performance;
                 performance comparison; performance evaluation;
                 software; Sun Workstations; systems",
  treatment =    "X Experimental",
}

@Article{Hor:1985:DPP,
  author =       "T. M. Hor and C. K. Yuen",
  title =        "The design and programming of a powerful short
                 wordlength processor using context-dependent machine
                 instructions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "1",
  pages =        "12--26",
  month =        mar,
  year =         "1985",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1296930.1296932",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:22 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Context-dependent machine instructions were used to
                 extend the capability of instruction set of a short
                 wordlength processor. By freeing instruction bits for
                 other purposes, a more powerful machine instruction set
                 can be designed. Programming examples were given to
                 illustrate the benefit obtained from the design. Less
                 CPU time and memory space were required as compared
                 with popular 8-bit CPUs.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Miya:1985:MDP,
  author =       "E. N. Miya",
  title =        "Multiprocessor\slash distributed processing
                 bibliography (in machine-readable form)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "1",
  pages =        "27--29",
  month =        mar,
  year =         "1985",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1296930.1296933",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:22 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "There is a lot of renewed interest in parallel
                 processing. People parallel process, too. Human
                 parallel processing tends to be cooperative rather than
                 competitive. To this end, research literature uses
                 bibliographies like road-maps to the field.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "annotated bibliography; cellular automata; computer
                 system architecture; fault-tolerant computers;
                 multicomputers; multiprocessor software; networks;
                 operating systems; parallel algorithms; parallel
                 processing; programming languages; supercomputers;
                 vector processing",
}

@Article{Hu:1985:DAE,
  author =       "Weiming Hu",
  title =        "Dataflow architecture for {EEG} patient monitor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "2",
  pages =        "3--10",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1296935.1296936",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Much work is currently directed towards dataflow
                 architectures. Most of the proposed architectures
                 attempt to exploit fine grained parallelism. This paper
                 describes an application specific dataflow architecture
                 which exploits coarse grained parallelism. The
                 application is that of a real-time patient monitor used
                 to display patient data.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tagg:1985:SEA,
  author =       "A. G. Tagg",
  title =        "Speculations on the evolution of an architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "2",
  pages =        "11--18",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1296935.1296937",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "PRIME computers was formed in the early 1970s by a
                 splinter group of hardware and software engineers from
                 Honeywell. With them, they brought their ideas on
                 minicomputers, based on their experience of Honeywell
                 minis, and their experience of the MULTICS operating
                 system.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Randell:1985:HST,
  author =       "Brian Randell",
  title =        "Hardware\slash software tradeoffs: a general design
                 principle?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "2",
  pages =        "19--21",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1296935.1296938",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Hardware and software are logically equivalent. Any
                 operation performed by software can also be built
                 directly into the hardware and any instruction executed
                 by the hardware can also be simulated in software. The
                 decision to put certain features in hardware and others
                 in software is based on such factors as cost, speed,
                 reliability and frequency of change. There are no hard
                 and fast rules to the effect that X must go into the
                 hardware and Y must be programmed explicitly. Designers
                 with different goals may, and often do, make different
                 decisions\ldots{} the boundary between hardware and
                 software is arbitrary and constantly changing. Today's
                 software is tomorrow's hardware, and vice versa. [1]",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kumar:1985:APM,
  author =       "V. K. Prasanna Kumar and C. S. Raghavendra",
  title =        "Array processor with multiple broadcasting",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "2--10",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wolf:1985:MMI,
  author =       "G. Wolf and J. R. Jump",
  title =        "Matrix multiplication in an interleaved array
                 processing architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "11--17",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goodman:1985:PVD,
  author =       "J. R. Goodman and Jian-tu Hsieh and Koujuch Liou and
                 Andrew R. Pleszkun and P. B. Schechter and Honesty C.
                 Young",
  title =        "{PIPE}: a {VLSI} decoupled architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "20--27",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hsu:1985:TST,
  author =       "Peter Y. T. Hsu and Joseph T. Rahmeh and Edward S.
                 Davidson and Jacob A. Abraham",
  title =        "{TIDBITS}: speedup via time-delay bit-slicing in {ALU}
                 design for {VLSI} technology",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "29--35",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1985:IPI,
  author =       "James E. Smith and Andrew R. Pleszkun",
  title =        "Implementation of precise interrupts in pipelined
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "36--44",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schwetman:1985:CPP,
  author =       "Herb Schwetman and Daniel Gajski and Dennis Gannon and
                 Daniel Hills and Jacob Schwartz and James Browne",
  title =        "Classification of parallel processor architectures
                 (invited tutorial session)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "45--45",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hasegawa:1985:HST,
  author =       "Makoto Hasegawa and Yoshiharu Shigei",
  title =        "High-speed top-of-stack scheme for {VLSI} processor: a
                 management algorithm and its analysis",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "48--54",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hitchcock:1985:AMR,
  author =       "Charles Y. {Hitchcock III} and H. M. Brinkley Sprunt",
  title =        "Analyzing multiple register sets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "55--63",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1985:CEI,
  author =       "Alan Jay Smith",
  title =        "Cache evaluation and the impact of workload choice",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "64--73",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Moon:1985:AS,
  author =       "David A. Moon",
  title =        "Architecture of the {Symbolics 3600}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "76--83",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ram:1985:PGC,
  author =       "Ashwin Ram and Janak H. Patel",
  title =        "Parallel garbage collection without synchronization
                 overhead",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "84--90",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sohi:1985:ELE,
  author =       "Gurindar S. Sohi and Edward S. Davidson and Janak H.
                 Patel",
  title =        "An efficient {LISP}-execution architecture with a new
                 representation for list structures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "91--98",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Amano:1985:SIN,
  author =       "Hideharu Amano and Taisuke Boku and Tomohiro Kudoh and
                 Hideo Aiso",
  title =        "{(SM)2-II}: a new version of the sparse matrix solving
                 machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "100--107",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Beetem:1985:GS,
  author =       "John Beetem and Monty Denneau and Don Weingarten",
  title =        "The {GF11} supercomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "108--115",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1985:MUD,
  author =       "Bradley Warren Smith and Howard Jay Siegel",
  title =        "Models for use in the design of macro-pipelined
                 parallel processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "116--123",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Edler:1985:IRM,
  author =       "Jan Edler and Allan Gottlieb and Clyde P. Kruskal and
                 Kevin P. McAuliffe and Larry Rudolph and Marc Snir and
                 Patricia J. Teller and James Wilson",
  title =        "Issues related to {MIMD} shared-memory computers: the
                 {NYU Ultracomputer} approach",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "126--135",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ibbett:1985:MPV,
  author =       "R. N. Ibbett and P. C. Capon and N. P. Topham",
  title =        "{MU6V}: a parallel vector processing system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "136--144",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lundstrom:1985:DCH,
  author =       "Stephen F. Lundstrom",
  title =        "A decentralized control, highly concurrent
                 multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "145--151",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dally:1985:OOA,
  author =       "William J. Dally and James T. Kajiya",
  title =        "An object oriented architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "154--161",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gehringer:1985:TAH,
  author =       "Edward F. Gehringer and J. Leslie Keedy",
  title =        "Tagged architecture: how compelling are its
                 advantages?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "162--170",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nanba:1985:VAV,
  author =       "S. Nanba and N. Ohno and H. Kubo and H. Morisue and T.
                 Ohshima and H. Yamagishi",
  title =        "{VM\slash 4}: {ACOS-4} virtual machine architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "171--178",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dobry:1985:PSP,
  author =       "T. P. Dobry and A. M. Despain and Y. N. Patt",
  title =        "Performance studies of a {Prolog} machine
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "180--190",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nakazaki:1985:DHS,
  author =       "Ryosei Nakazaki and Akihiko Konagaya and Shin'ichi
                 Habata and Hideo Shimazu and Mamoru Umemutra and
                 Masahiro Yamamoto and Minoru Yokota and Takashi
                 Chikayama",
  title =        "Design of a high-speed {Prolog} machine {(HPM)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "191--197",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Woo:1985:HUU,
  author =       "Nam Sung Woo",
  title =        "A hardware unification unit: design and analysis",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "198--205",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Matelan:1985:FM,
  author =       "Nicholas Matelan",
  title =        "The {FLEX\slash 32} multicomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "209--213",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rattner:1985:CMT,
  author =       "J. Rattner",
  title =        "Commercial multiprocessors (title only)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "214--214",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Naedel:1985:CCA,
  author =       "Dick Naedel",
  title =        "Closely coupled asynchronous hierarchical and parallel
                 processing in an open architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "215--220",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Savage:1985:PPL,
  author =       "Jim Savage",
  title =        "Parallel processing as a language design problem",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "221--224",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rodgers:1985:IMS,
  author =       "David P. Rodgers",
  title =        "Improvements in multiprocessor system design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "225--231",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mark:1985:SCF,
  author =       "Peter B. Mark",
  title =        "The {Sequoia} computer: a fault-tolerant
                 tightly-coupled multiprocessor architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "232--232",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nestle:1985:SNS,
  author =       "Elliot Nestle and Armond Inselberg",
  title =        "The {SYNAPSE N+1 System}: architectural
                 characteristics and performance data of a
                 tightly-coupled multiprocessor system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "233--239",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Horst:1985:AHV,
  author =       "Robert W. Horst and Timothy C. K. Chou",
  title =        "An architecture for high volume transaction
                 processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "240--245",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stone:1985:FGC,
  author =       "Harold Stone and Eric Manning and Harriet Rigas and
                 Philip Treleaven",
  title =        "The fifth generation computer systems projects
                 (invited session)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "247--247",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kamiya:1985:HPA,
  author =       "Shigeo Kamiya and Susumu Matsuda and Kazuhide Iwata
                 and Shigeki Shibayama and Hiroshi Sakai and Kunio
                 Murakami",
  title =        "A hardware pipeline algorithm for relational database
                 operation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "250--257",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1985:DMR,
  author =       "Dik Lun Lee",
  title =        "A distributed multiple-response resolver for
                 value-order retrieval",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "258--265",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Feo:1985:DDR,
  author =       "John Feo and Roy Jenevein and J. C. Browne",
  title =        "Dynamic, distributed resource configuration on
                 {SW}-banyans",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "268--275",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Katz:1985:ICC,
  author =       "R. H. Katz and S. J. Eggers and D. A. Wood and C. L.
                 Perkins and R. G. Sheldon",
  title =        "Implementing a cache consistency protocol",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "276--283",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Li:1985:TRS,
  author =       "Zhiyuan Li and Walid Abu-Sufah",
  title =        "A technique for reducing synchronization overhead in
                 large scale multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "284--291",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Whitby-Strevens:1985:T,
  author =       "Colin Whitby-Strevens",
  title =        "The transputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "292--300",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hurson:1985:SMU,
  author =       "A. R. Hurson and B. Shirazi",
  title =        "A systolic multiplier unit and its {VLSI} design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "302--309",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Melhem:1985:LSS,
  author =       "Rami Melhem",
  title =        "A language for the simulation of systolic
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "310--314",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chuang:1985:VSA,
  author =       "Henry Y. H. Chuang and Guo He",
  title =        "A versatile systolic array for matrix computations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "315--322",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vedder:1985:HDF,
  author =       "Rex Vedder and Dennis Finn",
  title =        "The {Hughes Data Flow Multiprocessor}: architecture
                 for efficient signal and data processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "324--332",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Traub:1985:APG,
  author =       "Kenneth R. Traub",
  title =        "An abstract parallel graph reduction machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "333--341",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Preiss:1985:DFQ,
  author =       "Bruno R. Preiss and V. C. Hamacher",
  title =        "Data flow on a queue machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "342--351",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gaudiot:1985:MHS,
  author =       "J. L. Gaudiot",
  title =        "Methods for handling structures in data-flow systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "352--358",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Samatham:1985:BMN,
  author =       "M. R. Samatham and D. K. Pradhan",
  title =        "The {de Bruijn} multiprocessor network: a versatile
                 sorting network",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "360--367",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tzeng:1985:FTS,
  author =       "Nian-Feng Tzeng and Pen-Chung Yew and Chun-Qi Zhu",
  title =        "A fault-tolerant scheme for multistage interconnection
                 networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "368--375",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kumar:1985:DAF,
  author =       "V. P. Kumar and S. M. Reddy",
  title =        "Design and analysis of fault-tolerant multistage
                 interconnection networks with low link complexity",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "376--386",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Davis:1985:PAP,
  author =       "Nathaniel J. {Davis IV} and Howard Jay Siegel",
  title =        "The performance analysis of partitioned circuit
                 switched multistage interconnection networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "387--394",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vrsalovic:1985:IPD,
  author =       "Dalibor Vrsalovic and Edward F. Gehringer and Zary Z.
                 Segall and Daniel P. Siewiorek",
  title =        "The influence of parallel decomposition strategies on
                 the performance of multiprocessor systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "396--405",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Abu-Sufah:1985:PPT,
  author =       "Walid Abu-Sufah and Alex Y. Kwok",
  title =        "Performance prediction tools for {Cedar}: a
                 multiprocessor supercomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "406--413",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Grino:1985:ASM,
  author =       "Jos{\'e} M. Llaber{\'\i}a Gri{\~n}{\'o} and Mateo
                 Valero Cort{\'e}s and Enrique Herrada Lillo and
                 Jes{\'u}s Labarta Mancho",
  title =        "Analysis and simulation of multiplexed single-bus
                 networks with and without buffering",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "414--421",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sanguinetti:1985:PMB,
  author =       "J. Sanguinetti and B. Kumar",
  title =        "Performance of a message-based multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "3",
  pages =        "424--425",
  month =        jun,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:54 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hake:1985:PDP,
  author =       "J.-Fr. Hake",
  title =        "{PDOC} --- a database on parallel processing
                 literature",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "4",
  pages =        "2--7",
  month =        sep,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:10 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rockey:1985:DAS,
  author =       "Mark Rockey",
  title =        "The dataflow architecture: a suitable base for the
                 implementation of expert systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "4",
  pages =        "8--14",
  month =        sep,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:10 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cragon:1985:ADS,
  author =       "Harvey G. Cragon",
  title =        "An architecture design system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "4",
  pages =        "15--21",
  month =        sep,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:10 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Huguet:1985:RRF,
  author =       "Miquel Huguet and Tom{\'a}s Lang",
  title =        "A reduced register file for {RISC} architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "4",
  pages =        "22--31",
  month =        sep,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:10 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Alexander:1985:TBP,
  author =       "Cedell A. Alexander and William M. Keshlear and Faye
                 Briggs",
  title =        "Translation buffer performance in a {UNIX}
                 environment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "5",
  pages =        "2--14",
  month =        dec,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:18 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1985:HSC,
  author =       "Rosanna Lee",
  title =        "On ``hot spot'' contention",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "13",
  number =       "5",
  pages =        "15--20",
  month =        dec,
  year =         "1985",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:18 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Woo:1986:CHU,
  author =       "Nam Sung Woo and Richard O'Keefe",
  title =        "A comment on {``A hardware unification unit: design
                 and analysis''}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "1",
  pages =        "2--3",
  month =        jan,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ruighaver:1986:DAD,
  author =       "A. B. Ruighaver",
  title =        "Design aspects of the {Delft Parallel Processor DPP84}
                 and its programming system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "1",
  pages =        "4--8",
  month =        jan,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hammerstrom:1986:CAP,
  author =       "Dan Hammerstrom and David Maier and Shreekant
                 Thakkar",
  title =        "The {Cognitive Architecture Project}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "1",
  pages =        "9--21",
  month =        jan,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1986:BRC,
  author =       "Alan Jay Smith",
  title =        "Bibliography and reading on {CPU} cache memories and
                 related topics",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "1",
  pages =        "22--42",
  month =        jan,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:29 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yokota:1986:MAR,
  author =       "H. Yokota and H. Itoh",
  title =        "A model and an architecture for a relational knowledge
                 base",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "2--9",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Amamiya:1986:IEL,
  author =       "M. Amamiya and M. Takesue and R. Hasegawa and H.
                 Mikami",
  title =        "Implementation and evaluation of a
                 list-processing-oriented data flow machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "10--19",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Takahashi:1986:NSS,
  author =       "K. Takahashi and H. Yamada and H. Nagai and K.
                 Matsumi",
  title =        "A new string search hardware architecture for {VLSI}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "20--27",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gupta:1986:PAA,
  author =       "A. Gupta and C. Forgy and A. Newell and R. Wedig",
  title =        "Parallel algorithms and architectures for rule-based
                 systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "28--37",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Halstead:1986:CDM,
  author =       "R. R. {Halstead, Jr.} and T. L. Anderson and R. B.
                 Osborne and T. L. Sterling",
  title =        "{Concert}: design of a multiprocessor development
                 system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "40--48",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kung:1986:MRB,
  author =       "H. T. Kung",
  title =        "Memory requirements for balanced computer
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "49--54",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hong:1986:GAS,
  author =       "Y. C. Hong and T. H. Payne and L. B. O. Ferguson",
  title =        "Graph allocation in static dataflow systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "55--64",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Agrawal:1986:SIR,
  author =       "P. Agrawal and R. Agrawal",
  title =        "Software implementation of a recursive fault tolerance
                 algorithm on a network of computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "65--72",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nojiri:1986:MPO,
  author =       "T. Nojiri and S. Kawasaki and K. Sakoda",
  title =        "Microprogrammable processor for object-oriented
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "74--81",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thakkar:1986:IFU,
  author =       "S. S. Thakkar and W. E. Hostmann",
  title =        "An instruction fetch unit for a graph reduction
                 machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "82--91",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gehringer:1986:FOO,
  author =       "E. F. Gehringer and R. P. Colwell",
  title =        "Fast object-oriented procedure calls: lessons from the
                 {Intel 432}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "92--101",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dias:1986:CMS,
  author =       "D. M. Dias and B. R. Iyer and P. S. Yu",
  title =        "On coupling many small systems for transaction
                 processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "104--110",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Malkawi:1986:PMP,
  author =       "M. I. Malkawi and J. H. Patel",
  title =        "Performance measurement of paging behavior in
                 multiprogramming systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "111--118",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Agarwal:1986:ANT,
  author =       "A. Agarwal and R. L. Sites and M. Horowitz",
  title =        "{ATUM}: a new technique for capturing address traces
                 using microcode",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "119--127",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wise:1986:EES,
  author =       "M. J. Wise",
  title =        "Experimenting with {EPILOG}: some results and
                 preliminary conclusions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "119--127",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shobatake:1986:UPB,
  author =       "Y. Shobatake and H. Aiso",
  title =        "A unification processor based on a uniformly
                 structured cellular hardware",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "128--139",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ito:1986:APE,
  author =       "N. Ito and M. Sato and E. Kuno and K. Rokusawa",
  title =        "The architecture and preliminary evaluation results of
                 the experimental parallel inference machine {PIM-D}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "149--156",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seznec:1986:ERC,
  author =       "A. Seznec",
  title =        "An efficient routing control for the {SIGMA} network
                 {$ \Sigma (4) $}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "158--168",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nicoud:1986:RHP,
  author =       "J. D. Nicoud and K. Skala",
  title =        "{REYSM}, a high performance, low power multi-processor
                 bus",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "169--174",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1986:ESG,
  author =       "K. Y. Lee and W. Hegazy",
  title =        "The extra stage gamma network",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "175--182",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yuhara:1986:EFA,
  author =       "M. Yuhara and A. Hattori and M. Niwa and M. Kishimoto
                 and H. Hayashi",
  title =        "Evaluation of the {FACOM ALPHA Lisp} machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "184--190",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pleszkun:1986:AEL,
  author =       "A. R. Pleszkun and M. J. Thazhuthaveetil",
  title =        "An architecture for efficient {Lisp} list access",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "191--198",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nakata:1986:FLS,
  author =       "T. Nakata and N. Koike",
  title =        "A functional level simulation engine of {MAN-YO}: a
                 special purpose parallel machine for logic design
                 automation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "202--208",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Frank:1986:EPS,
  author =       "E. H. Frank",
  title =        "Exploiting parallelism in a switch-level simulation
                 machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "209--215",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anantharaman:1986:HAS,
  author =       "T. S. Anantharaman and R. Bisiani",
  title =        "A hardware accelerator for speech recognition
                 algorithms",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "216--223",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shimada:1986:EPD,
  author =       "T. Shimada and K. Hiraki and K. Nishida and S.
                 Sekiguchi",
  title =        "Evaluation of a prototype data flow processor of the
                 {SIGMA-1} for scientific computations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "226--234",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sargeant:1986:SDS,
  author =       "J. Sargeant and C. C. Kirkham",
  title =        "Stored data structures on the {Manchester} dataflow
                 machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "235--242",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hawakami:1986:SDS,
  author =       "K. Hawakami and J. R. Gurd",
  title =        "A scalable dataflow structure store",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "243--250",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hasegawa:1986:FFT,
  author =       "M. Hasegawa and Y. Shigei",
  title =        "{$ A T^2 = O(N \log^4 N), T = O(\log N) $} {Fast
                 Fourier Transform} in a light connected $3$-dimensional
                 {VLSI}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "252--260",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sapiecha:1986:MAH,
  author =       "K. Sapiecha and R. Jarocki",
  title =        "Modular architecture for high performance
                 implementation of {FFT} algorithm",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "261--270",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Navarro:1986:CSI,
  author =       "J. J. Navarro and J. M. Llaberia and M. Valero",
  title =        "Computing size-independent matrix problems on systolic
                 array processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "271--278",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tomita:1986:CLL,
  author =       "S. Tomita and K. Shibayama and T. Nakata and S. Yuasa
                 and H. Hagiwara",
  title =        "A computer with low-level parallelism {QA-2}: its
                 applications to {$3$-D} graphics and {Prolog\slash
                 Lisp} machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "280--289",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hirayama:1986:VOA,
  author =       "M. Hirayama",
  title =        "{VLSI} oriented asynchronous architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "290--296",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hwu:1986:HHP,
  author =       "W. Hwu and Y. N. Patt",
  title =        "{HPSm}, a high performance restricted data flow
                 architecture having minimal functionality",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "297--306",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Onaga:1986:DRA,
  author =       "K. Onaga and T. Takechi",
  title =        "On design of rotary array communication and
                 wavefront-driven algorithms for solving large-scale
                 band-limited matrix equations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "308--315",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Napolitano:1986:CAD,
  author =       "L. M. {Napolitano, Jr.}",
  title =        "A computer architecture for dynamic finite element
                 analysis",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "316--323",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Harper:1986:PEV,
  author =       "D. T. {Harper III} and J. R. Jump",
  title =        "Performance evaluation of vector accesses in parallel
                 memories using a skewed storage scheme",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "324--328",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kondo:1986:PMA,
  author =       "T. Kondo and T. Tsuchiya and T. Kitamura and Y.
                 Sugiyama and T. Kimura",
  title =        "Pseudo {MIMD} array processor---{AAP2}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "330--337",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fisher:1986:SLA,
  author =       "A. L. Fisher",
  title =        "Scan line array processors for image computation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "338--345",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Annaratone:1986:WAI,
  author =       "M. Annaratone and E. Arnould and T. Gross and H. T.
                 Kung and M. S. Lam",
  title =        "{Warp} architecture and implementation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "346--356",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wood:1986:CAT,
  author =       "D. A. Wood and S. J. Eggers and G. Gibson and M. D.
                 Hill and J. M. Pendleton",
  title =        "An in-cache address translation mechanism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "358--365",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cheriton:1986:SCC,
  author =       "D. R. Cheriton and G. A. Slavenburg and P. D. Boyle",
  title =        "Software-controlled caches in the {VMP}
                 multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "366--374",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goodman:1986:URV,
  author =       "J. R. Goodman and W. C. Hsu",
  title =        "On the use of registers vs. cache to minimize memory
                 traffic",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "375--383",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hsu:1986:HCS,
  author =       "P. Y. T. Hsu and E. S. Davidson",
  title =        "Highly concurrent scalar processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "386--395",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McFarling:1986:RCB,
  author =       "S. McFarling and J. Hennesey",
  title =        "Reducing the cost of branches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "396--403",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kunkel:1986:OPS,
  author =       "S. R. Kunkel and J. E. Smith",
  title =        "Optimal pipelining in supercomputers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "404--411",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sweazey:1986:CCC,
  author =       "P. Sweazey and A. J. Smith",
  title =        "A class of compatible cache consistency protocols and
                 their support by the {IEEE Futurebus}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "414--423",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bitar:1986:MCS,
  author =       "P. Bitar and A. M. Despain",
  title =        "Multiprocessor cache synchronization: issues,
                 innovations, evolution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "424--433",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dubois:1986:MAB,
  author =       "M. Dubois and C. Scheurich and F. Briggs",
  title =        "Memory access buffering in multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "434--442",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Taylor:1986:ESL,
  author =       "G. S. Taylor and P. N. Hilfinger and J. R. Larus and
                 D. A. Patterson and B. G. Zorn",
  title =        "Evaluation of the {SPUR Lisp} architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "2",
  pages =        "444--452",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Woo:1986:RCC,
  author =       "Nam Sung Woo",
  title =        "A reply to comments {``A Comment on 'A Hardware
                 Unification Unit: Design and Analysis''\,'}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "3",
  pages =        "2--4",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{DuBose:1986:MR,
  author =       "D. K. DuBose and D. K. Fotakis and D. Tabak",
  title =        "A microcoded {RISC}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "3",
  pages =        "5--16",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lang:1986:RRS,
  author =       "Tom{\'a}s Lang and Miquel Huguet",
  title =        "Reduced register saving\slash restoring in
                 single-window register files",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "3",
  pages =        "17--26",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rouse:1986:TDH,
  author =       "Larry O'Neal Rouse",
  title =        "The twisted double helix: a minimum distance
                 architecture for 5th generation computing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "3",
  pages =        "27--33",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Harland:1986:RMT,
  author =       "David M. Harland",
  title =        "A recursively microcodable tagged architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "3",
  pages =        "34--40",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Alexander:1986:CMP,
  author =       "Cedell Alexander and William Keshlear and Furrokh
                 Cooper and Faye Briggs",
  title =        "Cache memory performance in a {Unix} environment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "3",
  pages =        "41--61",
  month =        jun,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stokes:1986:THV,
  author =       "Roger Stokes",
  title =        "Traces for hardware verification",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "4",
  pages =        "7--14",
  month =        sep,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kirner:1986:DDS,
  author =       "Claudio Kirner and Eduardo Marques",
  title =        "Design of a distributed system support based on a
                 centralized parallel bus",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "4",
  pages =        "15--26",
  month =        sep,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Irwin:1986:STR,
  author =       "Mary Jane Irwin",
  title =        "Secretary\slash Treasurer's {Report}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "4",
  pages =        "28--28",
  month =        sep,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Harland:1986:MOO,
  author =       "David M. Harland and Bruno Beloff",
  title =        "Microcoding an object-oriented instruction set",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "5",
  pages =        "3--12",
  month =        dec,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:18 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stallings:1986:ABR,
  author =       "William Stallings",
  title =        "An annotated bibliography on reduced instruction set
                 computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "14",
  number =       "5",
  pages =        "13--19",
  month =        dec,
  year =         "1986",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:18 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Halstead:1987:OCM,
  author =       "Robert H. {Halstead, Jr.}",
  title =        "Overview of {Concert MultiLisp}: a multiprocessor
                 symbolic computing system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "1",
  pages =        "5--14",
  month =        mar,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Patterson:1987:PRS,
  author =       "Dave Patterson",
  title =        "A progress report on {SPUR}: {February 1, 1987}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "1",
  pages =        "15--21",
  month =        mar,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Despain:1987:A,
  author =       "A. Despain and Y. Patt and V. Srini and P. Bitar and
                 W. Bush and C. Chien and W. Citrin and B. Fagin and W.
                 Hwu and S. Melvin and R. McGeer and A. Singhal and M.
                 Shebanow and P. {Van Roy}",
  title =        "Aquarius",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "1",
  pages =        "22--34",
  month =        mar,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kohli:1987:OPP,
  author =       "Madhur Kohli and Mark E. Giuliano and Jack Minker",
  title =        "An overview of the {PRISM} project",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "1",
  pages =        "35--42",
  month =        mar,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hermenegildo:1987:DHP,
  author =       "M. V. Hermenegildo and R. A. Warren",
  title =        "Designing a high performance parallel logic
                 programming system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "1",
  pages =        "43--52",
  month =        mar,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mills:1987:CGR,
  author =       "Jonathan W. Mills",
  title =        "Coming to grips with a {RISC}: a report of the
                 progress of the {LOW RISC} design group",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "1",
  pages =        "53--62",
  month =        mar,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Short:1987:UIS,
  author =       "Brian Short",
  title =        "Use of instruction set simulators to evaluate the {LOW
                 RISC}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "1",
  pages =        "63--67",
  month =        mar,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gutzmann:1987:ODH,
  author =       "Kurt M. Gutzmann",
  title =        "Optimal dimension of hypercubes for sorting",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "1",
  pages =        "68--72",
  month =        mar,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chesley:1987:AWN,
  author =       "Gilman Chesley",
  title =        "Addressable {WSI}: a non-redundant approach",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "1",
  pages =        "73--80",
  month =        mar,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Biswas:1987:CCS,
  author =       "Nripendra N. Biswas and S. Srinivas and Trishala
                 Dharanendra",
  title =        "A centrally controlled shuffle network for
                 reconfigurable and fault-tolerant architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "1",
  pages =        "81--87",
  month =        mar,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ditzel:1987:BFC,
  author =       "D. R. Ditzel and H. R. McLellan",
  title =        "Branch folding in the {CRISP} microprocessor: reducing
                 branch delay to zero",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "2--8",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{DeRosa:1987:EBA,
  author =       "J. A. DeRosa and H. M. Levy",
  title =        "An evaluation of branch architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "10--16",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hwu:1987:CRO,
  author =       "W. W. Hwu and Y. N. Patt",
  title =        "Checkpoint repair for out-of-order execution
                 machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "18--26",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sohi:1987:IIL,
  author =       "G. S. Sohi and S. Vajapeyam",
  title =        "Instruction issue logic for high-performance,
                 interruptible pipelined processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "27--34",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Swensen:1987:FTS,
  author =       "J. Swensen and Y. Patt",
  title =        "Fast temporary storage for serial and parallel
                 execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "35--43",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wong:1987:PAD,
  author =       "K. Wong and M. A. Franklin",
  title =        "Performance analysis and design of a logic simulation
                 machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "46--55",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Doshi:1987:MSA,
  author =       "K. Doshi and P. Varman",
  title =        "A modular systolic architecture for image
                 convolutions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "56--63",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fujita:1987:TMA,
  author =       "S. Fujita and R. Aibara and M. Yamashita and T. Ae",
  title =        "A template matching algorithm using
                 optically-connected {$3$-D} {VLSI} architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "64--70",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mendelson:1987:MDF,
  author =       "B. Mendelson and G. M. Silberman",
  title =        "Mapping data flow programs on a {VLSI} array of
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "72--80",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ghosal:1987:AMA,
  author =       "D. Ghosal and L. N. Bhuyan",
  title =        "Analytical modeling and architectural modifications of
                 a dataflow computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "81--89",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Takesue:1987:URM,
  author =       "M. Takesue",
  title =        "A unified resource management and execution control
                 mechanism for data flow machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "90--97",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Abe:1987:HPI,
  author =       "S. Abe and T. Bandoh and S. Yamaguchi and K. Kurosawa
                 and K. Kiriyama",
  title =        "High performance integrated {Prolog} processor {IPP}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "100--107",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fagin:1987:PSP,
  author =       "B. S. Fagin and A. M. Despain",
  title =        "Performance studies of a parallel {Prolog}
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "108--116",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Civera:1987:EVP,
  author =       "P. L. Civera and F. Maddaleno and G. L. Piccinini and
                 M. Zamboni",
  title =        "An experimental {VLSI} {Prolog} interpreter:
                 preliminary measurements and results",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "117--126",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ridoux:1987:DSM,
  author =       "O. Ridoux",
  title =        "Deterministic and stochastic modeling of parallel
                 garbage collection: towards real-time criteria",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "128--136",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sun:1987:SEP,
  author =       "C. Sun and Y. Tsu",
  title =        "The sharing of environment in {AND--OR}-parallel
                 execution of logic programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "137--144",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Guha:1987:AID,
  author =       "A. Guha and R. Ramnarayan and M. Derstine",
  title =        "Architectural issues in designing symbolic processors
                 in optics",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "145--151",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Varma:1987:RMS,
  author =       "A. Varma and C. S. Raghavendra",
  title =        "Rearrangeability of multistage shuffle\slash exchange
                 networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "154--162",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Beivide:1987:OMC,
  author =       "R. Beivide and E. Herrada and J. L. Balcazar and J.
                 Labarta",
  title =        "Optimized mesh-connected networks for {SIMD} and
                 {MIMD} architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "163--170",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Harper:1987:PER,
  author =       "D. T. {Harper III} and J. R. Jump",
  title =        "Performance evaluation of reduced bandwidth multistage
                 interconnection networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "171--175",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ramachandran:1987:HSI,
  author =       "U. Ramachandran and M. Solomon and M. Vernon",
  title =        "Hardware support for interprocess communication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "178--188",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dally:1987:AMD,
  author =       "W. J. Dally and L. Chao and A. Chien and S. Hassoun
                 and W. Horwat and J. Kaplan and P. Song and B. Totty
                 and S. Wills",
  title =        "Architecture of a message-driven processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "189--196",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kumar:1987:ESA,
  author =       "M. Kumar",
  title =        "Effect of storage allocation\slash reclamation methods
                 on parallelism and storage requirements",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "197--205",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chang:1987:CDS,
  author =       "J. H. Chang and H. Chao and K. So",
  title =        "Cache design of a sub-micron {CMOS} {System\slash
                 370}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "208--213",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Freeman:1987:APM,
  author =       "M. Freeman",
  title =        "An architectural perspective on a memory access
                 controller",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "214--223",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cheung:1987:OAG,
  author =       "K. Cheung and G. Sohi and K. Saluja and D. Pradhan",
  title =        "Organization and analysis of a gracefully-degrading
                 interleaved memory system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "224--231",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Scheurich:1987:CMO,
  author =       "C. Scheurich and M. Dubois",
  title =        "Correct memory operation of cache-based
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "234--243",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wilson:1987:HCB,
  author =       "A. W. {Wilson, Jr.}",
  title =        "Hierarchical cache\slash bus architecture for shared
                 memory multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "244--252",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1987:MCD,
  author =       "R. L. Lee and P. C. Yew and D. H. Lawrie",
  title =        "Multiprocessor cache design considerations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "253--262",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Eickemeyer:1987:PEM,
  author =       "R. J. Eickemeyer and J. H. Patel",
  title =        "Performance evaluation of multiple register sets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "264--271",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stanley:1987:PAA,
  author =       "T. J. Stanley and R. G. Wedig",
  title =        "A performance analysis of automatically managed top of
                 stack buffers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "272--281",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Moore:1987:CSV,
  author =       "B. Moore and A. Padegs and R. Smith and W. Buchholz",
  title =        "Concepts of the {System\slash 370} vector
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "282--288",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pleszkun:1987:WRA,
  author =       "A. R. Pleszkun and J. R. Goodman and W. C. Hsu and R.
                 T. Joersz and G. Bier and P. Woest and P. B.
                 Schechter",
  title =        "{WISQ}: a restartable architecture using queues",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "290--299",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chow:1987:ATD,
  author =       "P. Chow and M. Horowitz",
  title =        "Architectural tradeoffs in the design of {MIPS-X}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "300--308",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ditzel:1987:HAC,
  author =       "D. R. Ditzel and H. R. McLellan and A. D. Berenbaum",
  title =        "The hardware architecture of the {CRISP}
                 microprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "2",
  pages =        "309--319",
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 16:49:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Moore:1987:BDN,
  author =       "Matthew Moore and Charles McDowell",
  title =        "Bi-directional networks for large parallel
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "3",
  pages =        "3--4",
  month =        jun,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kaplan:1987:LLG,
  author =       "Ian Kaplan",
  title =        "The {LDF 100}: a large grain dataflow parallel
                 processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "3",
  pages =        "5--12",
  month =        jun,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lass:1987:WCC,
  author =       "Stanley Lass",
  title =        "Wide channel computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "3",
  pages =        "13--16",
  month =        jun,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bril:1987:IIA,
  author =       "Reinder J. Bril",
  title =        "An implementation independent approach to cache
                 memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "3",
  pages =        "17--24",
  month =        jun,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bril:1987:CLV,
  author =       "Reinder J. Bril",
  title =        "On cacheability of lock-variables in tightly coupled
                 multiprocessor systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "3",
  pages =        "25--32",
  month =        jun,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:53 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Iliffe:1987:FLM,
  author =       "J. K. Iliffe",
  title =        "A forward-looking method of {Cache} memory control",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "4",
  pages =        "4--10",
  month =        sep,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bandyopadhyay:1987:CBM,
  author =       "Amitava Bandyopadhyay and Yuan F. Zheng",
  title =        "Combining both microcode and hardwired control in
                 {RISC}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "4",
  pages =        "11--15",
  month =        sep,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dowd:1987:ERV,
  author =       "Martin Dowd",
  title =        "An example {RISC} vector machine architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "4",
  pages =        "16--22",
  month =        sep,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bhatia:1987:MIN,
  author =       "Sanjiv K. Bhatia and A. G. Starling",
  title =        "Multilayered {Illiac} network scheme",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "4",
  pages =        "23--31",
  month =        sep,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nowak:1987:SGP,
  author =       "Lothar Nowak",
  title =        "{SAMP:a} general purpose processor based on a
                 self-timed {VLIW} structure",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "4",
  pages =        "32--39",
  month =        sep,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ashenden:1987:LWP,
  author =       "Peter J. Ashenden and Chris J. Barter and Chris D.
                 Marlin",
  title =        "The {Leopard} workstation project",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "4",
  pages =        "40--51",
  month =        sep,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chiang:1987:DEL,
  author =       "Y. P. Chiang and M. L. Manwaring",
  title =        "Direct execution {Lisp} and cell memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "4",
  pages =        "52--57",
  month =        sep,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Terry:1987:FCM,
  author =       "J. M. Terry",
  title =        "Flow-control machines:the structured execution
                 architecture {(SXA)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "4",
  pages =        "58--69",
  month =        sep,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wirth:1987:HAP,
  author =       "Niklaus Wirth",
  title =        "Hardware architectures for programming languages and
                 programming languages for hardware architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "2--8",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Beck:1987:VAM,
  author =       "Bob Beck and Bob Kasten and Shreekant Thakkar",
  title =        "{VLSI} assist for a multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "10--20",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bisiani:1987:ASM,
  author =       "Roberto Bisiani and Alessandro Forin",
  title =        "Architectural support for multilanguage parallel
                 programming on heterogeneous systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "21--30",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rashid:1987:MIV,
  author =       "Richard Rashid and Avadis Tevanian and Michael Young
                 and David Golub and Robert Baron",
  title =        "Machine-independent virtual memory management for
                 paged uniprocessor and multiprocessor architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "31--39",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hayes:1987:ADE,
  author =       "John R. Hayes and Martin E. Fraeman and Robert L.
                 Williams and Thomas Zaremba",
  title =        "An architecture for the direct execution of the
                 {Forth} programming language",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "42--49",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Steenkiste:1987:TTC,
  author =       "Peter Steenkiste and John Hennessy",
  title =        "Tags and type checking in {LISP}: hardware and
                 software approaches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "50--59",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Davidson:1987:EIS,
  author =       "Jack W. Davidson and Richard A. Vaughan",
  title =        "The effect of instruction set complexity on program
                 size and memory performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "60--64",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Atkinson:1987:DP,
  author =       "Russell R. Atkinson and Edward M. McCreight",
  title =        "The dragon processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "65--69",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goodman:1987:CMV,
  author =       "James R. Goodman",
  title =        "Coherency for multiprocessor virtual address caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "72--81",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cargill:1987:CHS,
  author =       "T. A. Cargill and B. N. Locanthi",
  title =        "Cheap hardware support for software debugging and
                 profiling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "82--83",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Georgiou:1987:ECI,
  author =       "C. J. Georgiou and S. L. Palmer and P. L. Rosenfeld",
  title =        "An experimental coprocessor for implementing
                 persistent objects on an {IBM 4381}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "84--87",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Magenheimer:1987:IMD,
  author =       "Daniel J. Magenheimer and Liz Peters and Karl Pettis
                 and Dan Zuras",
  title =        "Integer multiplication and division on the {HP}
                 precision architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "90--99",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wall:1987:MEU,
  author =       "David W. Wall and Michael L. Powell",
  title =        "The {Mahler} experience: using an intermediate
                 language as the machine description",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "100--104",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Weiss:1987:SSC,
  author =       "Shlomo Weiss and James E. Smith",
  title =        "A study of scalar compilation techniques for pipelined
                 supercomputers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "105--109",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bush:1987:CSR,
  author =       "William R. Bush and A. Dain Samples and David Ungar
                 and Paul N. Hilfinger",
  title =        "Compiling {Smalltalk-80} to a {RISC}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "112--116",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chow:1987:HMA,
  author =       "F. Chow and S. Correll and M. Himelstein and E.
                 Killian and L. Weber",
  title =        "How many addressing modes are enough?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "117--121",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Massalin:1987:SLS,
  author =       "Henry Massalin",
  title =        "{Superoptimizer}: a look at the smallest program",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "122--126",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Taki:1987:PAE,
  author =       "Kazuo Taki and Katzuto Nakajima and Hiroshi Nakashima
                 and Morihiro Ikeda",
  title =        "Performance and architectural evaluation of the {PSI}
                 machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "128--135",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Borriello:1987:RVC,
  author =       "Gaetano Borriello and Andrew R. Cherenson and Peter B.
                 Danzig and Michael N. Nelson",
  title =        "{RISCs} vs. {CISCs} for {Prolog}: a case study",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "136--145",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kieburtz:1987:RAS,
  author =       "Richard B. Kieburtz",
  title =        "A {RISC} architecture for symbolic computation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "146--155",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ditzel:1987:DTS,
  author =       "David R. Ditzel and Hubert R. McLellan and Alan D.
                 Berenbaum",
  title =        "Design tradeoffs to support the {C} programming
                 language in the {CRISP} microprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "158--163",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thacker:1987:FMW,
  author =       "Charles P. Thacker and Lawrence C. Stewart",
  title =        "{Firefly}: a multiprocessor workstation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "164--172",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Clark:1987:PPV,
  author =       "Douglas W. Clark",
  title =        "Pipelining and performance in the {VAX 8800}
                 processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "173--177",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Colwell:1987:VAT,
  author =       "Robert P. Colwell and Robert P. Nix and John J.
                 O'Donnell and David B. Papworth and Paul K. Rodman",
  title =        "A {VLIW} architecture for a trace scheduling
                 compiler",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "180--192",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Levinthal:1987:PCG,
  author =       "Adam Levinthal and Pat Hanrahan and Mike Paquette and
                 Jim Lawson",
  title =        "Parallel computers for graphics applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "193--198",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1987:ZCP,
  author =       "J. E. Smith and G. E. Dermer and B. D. Vanderwarn and
                 S. D. Klinger and C. M. Rozewski",
  title =        "The {ZS-1} central processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "5",
  pages =        "199--204",
  month =        oct,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:25 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Frietman:1987:EOD,
  author =       "E. E. E. Frietman and A. B. Ruighaver",
  title =        "An electro-optic data communication system for the
                 {Delft} parallel processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "6",
  pages =        "2--8",
  month =        dec,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:28 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shippen:1987:TTD,
  author =       "G. B. Shippen and J. K. Archibald",
  title =        "A tagged token dataflow machine for computing small,
                 iterative algorithms",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "15",
  number =       "6",
  pages =        "9--18",
  month =        dec,
  year =         "1987",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:28 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Penn:1988:PSI,
  author =       "Clif Penn",
  title =        "Preface to the {Special} issue on {Neural Networks}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "1",
  pages =        "6--6",
  month =        mar,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lippmann:1988:ICN,
  author =       "Richard P. Lippmann",
  title =        "An introduction to computing with neural nets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "1",
  pages =        "7--25",
  month =        mar,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anderson:1988:SNN,
  author =       "James A. Anderson and Edward J. Wisniewski and Susan
                 R. Viscuso",
  title =        "Software for neural networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "1",
  pages =        "26--36",
  month =        mar,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Garth:1988:ISN,
  author =       "Simon Garth and Danny Pike",
  title =        "An integrated system for neural network simulations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "1",
  pages =        "37--44",
  month =        mar,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Maren:1988:CRI,
  author =       "A. Jean Maren",
  title =        "Conference report: {IEEE First International
                 Conference on Neural Networks}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "1",
  pages =        "45--46",
  month =        mar,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dongarra:1988:PVC,
  author =       "Jack J. Dongarra",
  title =        "Performance of various computers using standard linear
                 equations software in a {FORTRAN} environment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "1",
  pages =        "47--69",
  month =        mar,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wulf:1988:WCA,
  author =       "Wm. A. Wulf",
  title =        "The {WM} computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "1",
  pages =        "70--84",
  month =        mar,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tabak:1988:LIM,
  author =       "Daniel Tabak",
  title =        "Logarithmic indices for multiprocessor evaluation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "1",
  pages =        "85--90",
  month =        mar,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dowd:1988:ERV,
  author =       "Martin Dowd",
  title =        "An example {RISC} vector machine architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "1",
  pages =        "91--99",
  month =        mar,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dowd:1988:RVC,
  author =       "Martin Dowd",
  title =        "{RISC} vector {CPU}'s and crossbars in desktops",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "1",
  pages =        "100--102",
  month =        mar,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lass:1988:MIO,
  author =       "Stanley Lass",
  title =        "Multiple instructions\slash operands per access to
                 cache memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "1",
  pages =        "103--103",
  month =        mar,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gass:1988:WRS,
  author =       "Wanda Gass",
  title =        "Workshop report: synthesis of foo bars",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "1",
  pages =        "104--108",
  month =        mar,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ferguson:1988:BRL,
  author =       "F. Joel Ferguson",
  title =        "Book Review: {{\em Logic Design Principles\/}} by
                 {Edward J. McCluskey, Prentice-Hall Publishers,
                 Englewood Cliffs, New Jersey, 549 pp., \$39.95}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "1",
  pages =        "109--109",
  month =        mar,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:31 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ghosh:1988:CIM,
  author =       "J. Ghosh and K. Hwang",
  title =        "Critical issues in mapping neural networks on
                 message-passing multicomputers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "3--11",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Takefuji:1988:MCS,
  author =       "Y. Takefuji and R. Jannarone and Y. B. Cho and T.
                 Chen",
  title =        "Multinomial conjunctoid statistical learning
                 machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "12--17",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Louri:1988:BPA,
  author =       "A. Louri and K. Hwang",
  title =        "A bit-plane architecture for optical computing with
                 two-dimensional symbolic substitution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "18--27",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fiske:1988:RAP,
  author =       "S. Fiske and W. J. Dally",
  title =        "The reconfigurable arithmetic processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "30--36",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pleszkun:1988:PPM,
  author =       "A. R. Pleszkun and G. S. Sohi",
  title =        "The performance potential of multiple functional unit
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "37--44",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hwu:1988:EPM,
  author =       "W. W. Hwu and P. P. Chang",
  title =        "Exploiting parallel microprocessor microarchitectures
                 with a compiler code generator",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "45--53",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McNiven:1988:AMR,
  author =       "G. D. McNiven and E. S. Davidson",
  title =        "Analysis of memory referencing behavior for design of
                 local memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "56--63",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Eickenmeyer:1988:PEC,
  author =       "R. J. Eickenmeyer and J. H. Patel",
  title =        "Performance evaluation of on-chip register and cache
                 organizations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "64--72",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Baer:1988:IPM,
  author =       "J.-L. Baer and W.-H. Wang",
  title =        "On the inclusion properties for multi-level cache
                 hierarchies",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "73--80",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Short:1988:SST,
  author =       "R. T. Short and H. M. Levy",
  title =        "A simulation study of two-level caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "81--88",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chow:1988:HNH,
  author =       "E. Chow and H. Madan and J. Peterson and D. Grunwald
                 and D. Reed",
  title =        "Hyperswitch network for the hypercube computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "90--99",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Winsor:1988:ABH,
  author =       "D. C. Winsor and T. N. Mudge",
  title =        "Analysis of bus hierarchies for multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "100--107",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wei:1988:EGN,
  author =       "S. Wei and G. Lee",
  title =        "Extra group network: a cost-effective fault-tolerant
                 multistage interconnection network",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "108--115",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jiang:1988:PMB,
  author =       "H. Jiang and K. C. Smith",
  title =        "A partial-multiple-bus computer structure with
                 improved cost effectiveness",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "116--122",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Watson:1988:FPA,
  author =       "I. Watson and V. Woods and P. Watson and R. Banach and
                 M. Greenberg and J. Sargeant",
  title =        "{Flagship}: a parallel architecture for declarative
                 programming",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "124--130",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Iannucci:1988:TDN,
  author =       "R. A. Iannucci",
  title =        "Toward a dataflow\slash {von Neumann} hybrid
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "131--140",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Culler:1988:RRD,
  author =       "D. E. Culler and Arvind",
  title =        "Resource requirements of dataflow programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "141--150",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sprunt:1988:PDP,
  author =       "B. Sprunt and D. Kirk and L. Sha",
  title =        "Priority-driven, preemptive {I/O} controllers for
                 real-time systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "152--159",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shukla:1988:KIP,
  author =       "S. B. Shukla and D. P. Agrawal",
  title =        "A kernel-independent, pipelined architecture for
                 real-time {$2$-D} convolution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "160--166",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Liu:1988:EBL,
  author =       "W. Liu and T.-F. Yeh and W. E. Batchelor and R.
                 Cavin",
  title =        "Exploiting bit level concurrency in real-time
                 geometric feature extractions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "167--174",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Clark:1988:MVP,
  author =       "D. W. Clark and P. J. Bannon and J. B. Keller",
  title =        "Measuring {VAX 8800} performance with a histogram
                 hardware monitor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "176--185",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sites:1988:MCA,
  author =       "R. L. Sites and A. Agarwal",
  title =        "Multiprocessor cache analysis using {ATUM}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "186--195",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ng:1988:TOB,
  author =       "S. Ng and D. Lang and R. Selinger",
  title =        "Trade-offs between devices and paths in achieving disk
                 interleaving",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "196--201",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jainandunsing:1988:DCC,
  author =       "K. Jainandunsing and E. F. Deprettere",
  title =        "Design of a concurrent computer for solving systems of
                 linear equations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "204--211",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wolfe:1988:WDH,
  author =       "A. Wolfe and M. {Breternitz, Jr.} and C. Stephens and
                 A. L. Ting and D. B. Kirk and R. P. {Bianchini, Jr.}
                 and J. P. Shen",
  title =        "The white dwarf: a high-performance
                 application-specific processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "212--222",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gaudiot:1988:SPD,
  author =       "J. L. Gaudiot and C. M. Lin and M. Hosseiniyar",
  title =        "Solving partial differential equations in a
                 data-driven multiprocessor environment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "223--230",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1988:SSP,
  author =       "D. Lee",
  title =        "Scrambled storage for parallel memory systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "232--239",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Krishnaswamy:1988:ALC,
  author =       "V. Krishnaswamy and S. Ahuja and N. Carriero and D.
                 Gelernter",
  title =        "The architecture of a {Linda} coprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "240--249",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kung:1988:DAS,
  author =       "H. T. Kung",
  title =        "Deadlock avoidance for systolic communication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "252--260",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{So:1988:CPV,
  author =       "K. So and V. Zecca",
  title =        "Cache performance of vector processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "261--268",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vernon:1988:DRR,
  author =       "M. K. Vernon and U. Manber",
  title =        "Distributed round-robin and first-come first-serve
                 protocols and their applications to multiprocessor bus
                 arbitration",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "269--279",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Agarwal:1988:EDS,
  author =       "A. Agarwal and R. Simoni and J. Hennessy and M.
                 Horowitz",
  title =        "An evaluation of directory schemes for cache
                 coherence",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "280--298",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Prybylski:1988:PTC,
  author =       "S. Prybylski and M. Horowitz and J. Hennessy",
  title =        "Performance tradeoffs in cache design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "290--298",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cheong:1988:CCS,
  author =       "H. Cheong and A. V. Vaidenbaum",
  title =        "A cache coherence scheme with fast selective
                 invalidation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "299--307",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vernon:1988:AEP,
  author =       "M. K. Vernon and E. D. Lazowska and J. Zahorjan",
  title =        "An accurate and efficient performance analysis
                 technique for multiprocessor snooping cache-consistency
                 protocols",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "308--315",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rau:1988:DTR,
  author =       "D. Rau and J. A. B. Fortes and H. J. Siegel",
  title =        "Destination tag routing techniques based on a state
                 model for the {LADM} network",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "318--324",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kim:1988:RCB,
  author =       "D. W. Kim and G. J. Lipovski and A. Hartmann and R.
                 Jenevein",
  title =        "Regular {CC}-banyan networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "325--332",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jenevein:1988:TAR,
  author =       "R. M. Jenevein and T. Mookken",
  title =        "Traffic analysis of rectangular {SW}-banyan networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "333--342",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tamir:1988:HPM,
  author =       "Y. Tamir and G. L. Frazier",
  title =        "High-performance multi-queue buffers for {VLSI}
                 communications switches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "343--354",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Preiss:1988:CBM,
  author =       "B. R. Preiss and V. C. Hamacher",
  title =        "A cache-based message passing scheme for a shared-bus
                 multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "358--364",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Boku:1988:IHP,
  author =       "T. Boku and S. Nomura and H. Amano",
  title =        "{IMPULSE}: a high performance processing unit for
                 multiprocessors for scientific calculation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "365--372",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Eggers:1988:CSP,
  author =       "S. J. Eggers and R. H. Katz",
  title =        "A characterization of sharing in parallel programs and
                 its application to coherency protocol evaluation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "373--382",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lipovski:1988:FOI,
  author =       "G. J. Lipovski and P. Vaughan",
  title =        "A fetch-and-op implementation for parallel computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "384--392",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seznec:1988:SPT,
  author =       "A. Seznec and Y. J{\'e}gou",
  title =        "Synchronizing processors through memory requests in a
                 tightly coupled multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "393--400",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fujimoto:1988:DPS,
  author =       "R. M. Fujimoto and J.-J. Tsai and G. Gopalakrishnan",
  title =        "Design and performance of special purpose hardware for
                 time warp",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "401--409",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cheriton:1988:VMI,
  author =       "D. R. Cheriton and A. Gupta and P. D. Boyle and H. A.
                 Goosen",
  title =        "The {VMP} multiprocessor: initial experience,
                 refinements, and performance evaluation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "410--421",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goodman:1988:WMN,
  author =       "J. R. Goodman and P. J. Woest",
  title =        "The {Wisconsin} multicube: a new large-scale
                 cache-coherent multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "422--431",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tick:1988:DBP,
  author =       "E. Tick",
  title =        "Data buffer performance for sequential {Prolog}
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "434--442",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Halstead:1988:MMP,
  author =       "R. H. {Halstead, Jr.} and T. Fujita",
  title =        "{MASA}: a multithreaded processor architecture for
                 parallel symbolic computing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "443--451",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Butler:1988:PAO,
  author =       "P. L. Butler and J. D. {Allen, Jr.} and D. W.
                 Bouldin",
  title =        "Parallel architecture for {OPS5}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "2",
  pages =        "452--457",
  month =        may,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cheriton:1988:CCM,
  author =       "David R. Cheriton and Pat Boyle and Gert A.
                 Slavenburg",
  title =        "Comments on {``Coherency for multiprocessor virtual
                 addresses caches''} by {James R. Goodman}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "3",
  pages =        "3--6",
  month =        jun,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goodman:1988:RDR,
  author =       "James R. Goodman",
  title =        "Reply to {David R. Cheriton's, Pat Boyle's, and Gert
                 A. Slavenburg's ``Comments on 'Coherency for
                 multiprocessor virtual addressed caches''\,' by James
                 R. Goodman}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "3",
  pages =        "7--7",
  month =        jun,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rabbat:1988:TDC,
  author =       "Guy Rabbat and Borko Furht and Ron Kibler",
  title =        "Three-dimensional computers and measuring their
                 performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "3",
  pages =        "9--16",
  month =        jun,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Castan:1988:MPG,
  author =       "M. Castan and A. Contessa and E. Cousin and C. Coustet
                 and B. Lecussan",
  title =        "{MaRs}: a parallel graph reduction multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "3",
  pages =        "17--24",
  month =        jun,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Contessa:1988:AFT,
  author =       "Alessandro Contessa",
  title =        "An approach to fault tolerance and error recovery in a
                 parallel graph reduction machine: {MaRS}---a case
                 study",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "3",
  pages =        "25--32",
  month =        jun,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Crawford:1988:EHH,
  author =       "Chuck Crawford",
  title =        "Evolution of the {Harris H-series} computers and
                 speculations on their future",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "3",
  pages =        "33--39",
  month =        jun,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Good:1988:SIC,
  author =       "Philip L. Good",
  title =        "Structuring an instruction cache",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "3",
  pages =        "40--43",
  month =        jun,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Johnson:1988:CMM,
  author =       "Eric E. Johnson",
  title =        "Completing an {MIMD} multiprocessor taxonomy",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "3",
  pages =        "44--47",
  month =        jun,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jones:1988:UR,
  author =       "Douglas W. Jones",
  title =        "The ultimate {RISC}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "3",
  pages =        "48--55",
  month =        jun,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jones:1988:MC,
  author =       "Douglas W. Jones",
  title =        "A minimal {CISC}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "3",
  pages =        "56--63",
  month =        jun,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lass:1988:SCM,
  author =       "Stanley Lass",
  title =        "Shared cache multiprocessing with pack computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "3",
  pages =        "64--70",
  month =        jun,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jouppi:1988:SVS,
  author =       "Norman P. Jouppi",
  title =        "Superscalar vs. superpipelined machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "3",
  pages =        "71--80",
  month =        jun,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schachter:1988:BRH,
  author =       "Lorne H. Schachter",
  title =        "Book review of {{\em High-Performance Computer
                 Architecture\/}} by {Harold S. Stone. Addison-Wesley
                 1987}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "3",
  pages =        "81--84",
  month =        jun,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:55 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ramachandran:1988:PSI,
  author =       "Umakishore Ramachandran",
  title =        "Preface to the {Special Issue on Architectural Support
                 for Operating Systems}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "11--11",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Asthana:1988:IMS,
  author =       "A. Asthana and H. V. Jagadish and J. A. Chandross and
                 D. Lin and S. C. Knauer",
  title =        "An intelligent memory system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "12--20",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Beltrametti:1988:CMM,
  author =       "Monica Beltrametti and Kenneth Bobey and John R.
                 Zorbas",
  title =        "The control mechanism for the {Myrias} parallel
                 computer system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "21--30",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Finkel:1988:YSM,
  author =       "Raphael Finkel and Debra Hengsen",
  title =        "{YACKOS} on a shared-memory multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "31--36",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pucci:1988:OCE,
  author =       "Marc F. Pucci and J. L. Alberi",
  title =        "Optimized communication in an extended remote
                 procedure call model",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "37--46",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cortadella:1988:DRC,
  author =       "Jordi Cortadella and Teodor Jov{\'e}",
  title =        "Dynamic {RAM} for on-chip instruction caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "45--50",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Naderi:1988:MPEa,
  author =       "M. Naderi",
  title =        "Modelling and performance evaluation of
                 multiprocessors organization with shared memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "51--74",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gehringer:1988:SCP,
  author =       "Edward Gehringer and Janne Abullarade and Michael H.
                 Gulyn",
  title =        "A survey of commercial parallel processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "75--107",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lease:1988:CPS,
  author =       "Mark Lease and Mac Lively",
  title =        "Comparing production system architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "108--116",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Page:1988:FAH,
  author =       "Ivor Page and Jeff Niehaus",
  title =        "The {Flex} architecture, a high speed graphics
                 processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "117--129",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Murakami:1988:OKU,
  author =       "Kazuaki Murakami and Akira Fukuda and Toshinori
                 Sueyoshi and Shinji Tomita",
  title =        "An overview of the {Kyushu University} reconfigurable
                 parallel processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "130--137",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Percus:1988:SRC,
  author =       "Ora E. Percus and J. K. Percus",
  title =        "Some results concerning clock-regulated queues",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "138--144",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Williams:1988:SSS,
  author =       "Fleur Liane Williams",
  title =        "Should {SCC} set condition codes?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "145--149",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Steven:1988:NEA,
  author =       "Gordon B. Steven",
  title =        "A novel effective address calculation mechanism for
                 {RISC} microprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "150--156",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Parhami:1988:DFV,
  author =       "Behrooz Parhami",
  title =        "From defects to failures: a view of dependable
                 computing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "157--168",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Patterson:1988:RP,
  author =       "David A. Patterson",
  title =        "{RISCY} patents",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "169--191",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Takacs:1988:BRV,
  author =       "Helen C. Takacs",
  title =        "Book review: {{\em A VLSI Architecture for Concurrent
                 Data Structures\/}} by {William J. Dally (Kluwer
                 1988)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "192--193",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Colwell:1988:BRC,
  author =       "Robert P. Colwell",
  title =        "Book review: {{\em Computer Architecture and
                 Organization}}, 2nd ed. by {John P. Hayes (McGraw Hill,
                 1988)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "193--195",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McDowell:1988:BRS,
  author =       "Charles E. McDowell",
  title =        "Book review: {{\em Supercomputer Architectures\/}} by
                 {Paul B. Schneck (Kluwer Academic Publishers)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "4",
  pages =        "195--196",
  month =        sep,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:11 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hum:1988:SWF,
  author =       "Herbert H. J. Hum and Guang R. Gao",
  title =        "Summary of the workshop on frontiers in functional
                 programming and dataflow architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "5",
  pages =        "12--19",
  month =        dec,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{vanTilborg:1988:IDC,
  author =       "Andre M. van Tilborg",
  title =        "Instrumentation for distributed computing systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "5",
  pages =        "20--25",
  month =        dec,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Griffin:1988:UUR,
  author =       "Glenn W. Griffin",
  title =        "The ultimate ultimate {RISC}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "5",
  pages =        "26--32",
  month =        dec,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jones:1988:RCR,
  author =       "Douglas W. Jones",
  title =        "Risks of comparing {RISCs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "5",
  pages =        "33--34",
  month =        dec,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Naderi:1988:MPEb,
  author =       "M. Naderi",
  title =        "Modelling and performance evaluation of
                 multiprocessors, organizations with multi-memory
                 units",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "5",
  pages =        "35--51",
  month =        dec,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kogge:1988:VRB,
  author =       "Peter Kogge and John Oldfield and Mark Brule and
                 Charles Stormon",
  title =        "{VLSI} and rule-based systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "5",
  pages =        "52--65",
  month =        dec,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Parhami:1988:BRM,
  author =       "Behrooz Parhami",
  title =        "Book review: {{\em Memory Storage Patterns in Parallel
                 Processing\/}} by {Mary A. Mace (Kluwer Academic
                 Publishers, Boston, 1987, 139 pp.)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "16",
  number =       "5",
  pages =        "76--76",
  month =        dec,
  year =         "1988",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Moskowitz:1989:AMM,
  author =       "J. P. Moskowitz and C. Jousselin",
  title =        "An algebraic memory model",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "1",
  pages =        "55--62",
  month =        mar,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wong:1989:SAS,
  author =       "W. F. Wong",
  title =        "A stack addressing scheme based on windowing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "1",
  pages =        "63--69",
  month =        mar,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:1989:PTD,
  author =       "Anonymous",
  title =        "Pipelining through {Dynamic Control ROM}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "1",
  pages =        "70--72",
  month =        mar,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lass:1989:SIC,
  author =       "Stanley E. Lass",
  title =        "Some innovations in computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "1",
  pages =        "73--77",
  month =        mar,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bitar:1989:BRR,
  author =       "Philip Bitar",
  title =        "Book reviews: Review of {{\em Parallel Execution of
                 Logic Programs\/}} by {John Conery. Kluwer Academic
                 Publishers 1987}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "1",
  pages =        "81--82",
  month =        mar,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cohn:1989:ACT,
  author =       "Robert Cohn and Thomas Gross and Monica Lam",
  title =        "Architecture and compiler tradeoffs for a long
                 instruction word processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "2--14",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sohi:1989:TIF,
  author =       "Gurindar S. Sohi and Sriram Vajapeyam",
  title =        "Tradeoffs in instruction format design for horizontal
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "15--25",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dehnert:1989:OLS,
  author =       "James C. Dehnert and Peter Y.-T. Hsu and Joseph P.
                 Bratt",
  title =        "Overlapped loop support in the {Cydra 5}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "26--38",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Burkowski:1989:ASS,
  author =       "F. J. Burkowski and G. V. Cormack and G. D. P. Dueck",
  title =        "Architectural support for synchronous task
                 communication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "40--53",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gupta:1989:FBM,
  author =       "Rajiv Gupta",
  title =        "The fuzzy barrier: a mechanism for high speed
                 synchronization of processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "54--63",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goodman:1989:ESP,
  author =       "James R. Goodman and Mary K. Vernon and Philip J.
                 Woest",
  title =        "Efficient synchronization primitives for large-scale
                 cache-coherent multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "64--75",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mellor-Crummey:1989:SIC,
  author =       "J. M. Mellor-Crummey and T. J. LeBlanc",
  title =        "A software instruction counter",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "78--86",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Aral:1989:EDP,
  author =       "Z. Aral and I. Gerther and G. Schaffer",
  title =        "Efficient debugging primitives for multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "87--95",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Staknis:1989:SMA,
  author =       "M. E. Staknis",
  title =        "Sheaved memory: architectural support for state saving
                 and restoration in pages systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "96--102",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Holliday:1989:RHP,
  author =       "M. A. Holliday",
  title =        "Reference history, page size, and migration daemons in
                 local\slash remote architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "104--112",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Black:1989:TLB,
  author =       "D. L. Black and R. F. Rashid and D. B. Golub and C. R.
                 Hill",
  title =        "Translation lookaside buffer consistency: a software
                 approach",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "113--122",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gibson:1989:FCT,
  author =       "G. A. Gibson and L. Hellerstein and R. M. Karp and D.
                 A. Patterson",
  title =        "Failure correction techniques for large disk arrays",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "123--132",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jouppi:1989:UVS,
  author =       "N. P. Jouppi and J. Bertoni and D. W. Wall",
  title =        "A unified vector\slash scalar floating-point
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "134--143",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mulder:1989:DBR,
  author =       "H. Mulder",
  title =        "Data buffering: run-time versus compile-time support",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "144--151",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Adams:1989:AIS,
  author =       "T. L. Adams and R. E. Zimmerman",
  title =        "An analysis of 8086 instruction set usage in {MS DOS}
                 programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "152--160",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Roos:1989:RTS,
  author =       "J. Roos",
  title =        "A real-time support processor for {Ada} tasking",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "162--171",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vegdahl:1989:RES,
  author =       "Steven R. Vegdahl and Uwe F. Pleban",
  title =        "The runtime environment for {Scheme}, a {Scheme}
                 implementation on the 88000",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "172--182",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McFarling:1989:POI,
  author =       "S. McFarling",
  title =        "Program optimization for instruction caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "183--191",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Karger:1989:URO,
  author =       "Paul A. Karger",
  title =        "Using registers to optimize cross-domain call
                 performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "194--204",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Arnould:1989:DNN,
  author =       "Emmanuel Arnould and H. T. Kung and Fran{\c{c}}ois
                 Bitz and Robert D. Sansom and Eric C. Cooperm",
  title =        "The design of nectar: a network backplane for
                 heterogeneous multicomputers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "205--216",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Delgado-Rannauro:1989:MDP,
  author =       "S. A. Delgado-Rannauro and T. J. Reynolds",
  title =        "A message driven {OR}-parallel machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "217--228",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Owicki:1989:EPS,
  author =       "S. Owicki and A. Agarwal",
  title =        "Evaluating the performance of software cache
                 coherence",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "230--242",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Weber:1989:ACI,
  author =       "W. Weber and A. Gupta",
  title =        "Analysis of cache invalidation patterns in
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "243--256",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Eggers:1989:ESC,
  author =       "S. J. Eggers and R. H. Katz",
  title =        "The effect of sharing on the cache and bus performance
                 of parallel programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "257--270",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jouppi:1989:AIL,
  author =       "N. P. Jouppi and D. W. Wall",
  title =        "Available instruction-level parallelism for
                 superscalar and superpipelined machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "272--282",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dally:1989:MOF,
  author =       "W. J. Dally",
  title =        "Micro-optimization of floating-point operations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "283--289",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1989:LMI,
  author =       "M. D. Smith and M. Johnson and M. A. Horowitz",
  title =        "Limits on multiple instruction issue",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "2",
  pages =        "290--302",
  month =        apr,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:39 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Eggers:1989:EPF,
  author =       "S. J. Eggers and R. H. Katz",
  title =        "Evaluating the performance of four snooping cache
                 coherency protocols",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "2--15",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cheriton:1989:MLS,
  author =       "D. R. Cheriton and H. A. Goosen and P. D. Boyle",
  title =        "Multi-level shared caching techniques for scalability
                 in {VMP-M/C}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "16--24",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goto:1989:DPC,
  author =       "A. Goto and A. Matsumoto and E. Tick",
  title =        "Design and performance of a coherent cache for
                 parallel logic programming architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "25--33",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Grafe:1989:EDP,
  author =       "V. G. Grafe and G. S. Davidson and J. E. Hoch and V.
                 P. Holmes",
  title =        "The {Epsilon} dataflow processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "36--45",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sakai:1989:ADS,
  author =       "S. Sakai and y. Yamaguchi and K. Hiraki and Y. Kodama
                 and T. Yuba",
  title =        "An architecture of a dataflow single chip processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "46--53",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nitezki:1989:EDP,
  author =       "P. Nitezki",
  title =        "Exploiting data parallelism in signal processing on a
                 dataflow machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "54--61",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ibbett:1989:AMS,
  author =       "R. N. Ibbett and T. M. Hopkins and K. I. M. McKinnon",
  title =        "Architectural mechanisms to support sparse vector
                 processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "64--71",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Harper:1989:DSS,
  author =       "D. T. Harper and D. A. Linebarger",
  title =        "A dynamic storage scheme for conflict-free vector
                 access",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "72--77",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Murakami:1989:SSI,
  author =       "K. Murakami and N. Irie and S. Tomita",
  title =        "{SIMP} (Single Instruction stream\slash Multiple
                 instruction Pipelining): a novel high-speed
                 single-processor architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "78--85",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ben-Asher:1989:DSA,
  author =       "Y. Ben-Asher and D. Egozi and A. Schuster",
  title =        "{$2$-D SIMD} algorithms in the perfect shuffle
                 networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "88--95",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Valero-Garcia:1989:SHA,
  author =       "M. Valero-Garcia and J. J. Navarro and J. M. Llaberia
                 and M. Valero",
  title =        "Systematic hardware adaptation of systolic
                 algorithms",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "96--104",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chen:1989:TMH,
  author =       "M.-S. Chen and K. G. Shin",
  title =        "Task migration in hypercube multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "105--111",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Przybylski:1989:CPO,
  author =       "S. Przybylski and M. Horowitz and J. Hennessy",
  title =        "Characteristics of performance-optimal multi-level
                 cache hierarchies",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "114--121",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wood:1989:SRD,
  author =       "D. A. Wood and R. H. Katz",
  title =        "Supporting reference and dirty bits in {SPUR}'s
                 virtual address cache",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "122--130",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kessler:1989:IIS,
  author =       "R. E. Kessler and R. Jooss and A. Lebeck and M. D.
                 Hill",
  title =        "Inexpensive implementations of set-associativity",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "131--139",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wang:1989:OPT,
  author =       "W. H. Wang and J.-L. Baer and H. M. Levy",
  title =        "Organization and performance of a two-level
                 virtual-real cache hierarchy",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "140--148",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jesshope:1989:HPC,
  author =       "C. R. Jesshope and P. R. Miller and J. T. Yantchev",
  title =        "High performance communications in processor
                 networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "150--157",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mizrahi:1989:IMS,
  author =       "H. E. Mizrahi and J. L. Baer and E. D. Lazowska and J.
                 Zahorjan",
  title =        "Introducing memory into the switch elements of
                 multiprocessor interconnection networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "158--166",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Scott:1989:UFC,
  author =       "S. L. Scott and G. S. Sohi",
  title =        "Using feedback to control tree saturation in
                 multistage interconnection networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "167--176",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ezhilchelvan:1989:CRS,
  author =       "P. D. Ezhilchelvan and S. K. Shrivastava and A.
                 Tully",
  title =        "Constructing replicated systems using processors with
                 point-to-point communication links",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "177--184",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Benker:1989:KKC,
  author =       "H. Benker and J. M. Beacco and M. Dorochevsky and Th.
                 Jeffr{\'e} and A. P{\"o}hlmann and J. Noy{\'e} and B.
                 Poterie and J. C. Syre and O. Thibault and G.
                 Watzlawik",
  title =        "{KCM}: a knowledge crunching machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "186--194",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Singhal:1989:HPP,
  author =       "A. Singhal and Y. N. Patt",
  title =        "A high performance {Prolog} processor with multiple
                 function units",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "195--202",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Morioka:1989:EMS,
  author =       "M. Morioka and S. Yamaguchi and T. Bandoh",
  title =        "Evaluation of memory system for integrated {Prolog}
                 processor {IPP}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "203--210",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wong:1989:TDH,
  author =       "K.-F. Wong and M. H. Williams",
  title =        "A type driven hardware engine for {Prolog} clause
                 retrieval over a large knowledge base",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "211--222",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hwu:1989:CSH,
  author =       "W. W. Hwu and T. M. Conte and P. P. Chang",
  title =        "Comparing software and hardware schemes for reducing
                 the cost of branches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "224--233",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Farrens:1989:IPS,
  author =       "M. K. Farrens and a. R. Pleszkun",
  title =        "Improving performance of small on-chip instruction
                 caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "234--241",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hwu:1989:AHI,
  author =       "W. W. Hwu and P. P. Chang",
  title =        "Achieving high instruction cache performance with an
                 optimizing compiler",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "242--251",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Steenkiste:1989:ICD,
  author =       "P. Steenkiste",
  title =        "The impact of code density on instruction cache
                 performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "252--259",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nikhil:1989:CDS,
  author =       "R. S. Nikhil",
  title =        "Can dataflow subsume {von Neumann} computing?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "262--272",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Weber:1989:EBM,
  author =       "W.-D. Weber and A. Gupta",
  title =        "Exploring the benefits of multiple hardware contexts
                 in a multiprocessor architecture: preliminary results",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "273--280",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jouppi:1989:AOT,
  author =       "N. P. Jouppi",
  title =        "Architectural and organizational tradeoffs in the
                 design of the {MultiTitan CPU}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "281--289",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sato:1989:RTC,
  author =       "M. Sato and S. Ichikawa and E. Goto",
  title =        "Run-time checking in {Lisp} by integrating memory
                 addressing and range checking",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "290--297",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hopper:1989:MVW,
  author =       "A. Hopper and A. Jones and D. Lioupis",
  title =        "Multiple vs. wide shared bus multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "300--306",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Annaratone:1989:PMC,
  author =       "M. Annaratone and R. R{\"u}hl",
  title =        "Performance measurements on a commercial
                 multiprocessor running parallel code",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "307--314",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Annaratone:1989:ICS,
  author =       "M. Annaratone and C. Pommerell and R. R{\"u}hl",
  title =        "Interprocessor communication speed and performance in
                 distributed-memory parallel processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "315--324",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ghosal:1989:ACC,
  author =       "D. S. Ghosal and S. K. Tripathi and L. N. Bhuyan and
                 H. Jiang",
  title =        "Analysis of computation-communication issues in
                 dynamic dataflow architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "325--333",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kravitz:1989:LSM,
  author =       "S. Kravitz and R. E. Bryant and R. Rutenbar",
  title =        "Logic simulation on massively parallel architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "336--343",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fukazawa:1989:RRP,
  author =       "T. Fukazawa and T. Kimura and M. Tomizawa and K.
                 Takeda and Y. Itoh",
  title =        "{R256}: a research parallel processor for scientific
                 computation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "344--351",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anido:1989:TPT,
  author =       "M. L. Anido and D. J. Allerton and E. J. Zaluska",
  title =        "A three-port\slash three-access register file for
                 concurrent processing and {I/O} communication in a
                 {RISC}-like graphics engine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "354--361",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mulder:1989:AFA,
  author =       "J. M. Mulder and R. J. Portier and A. Srivastava and
                 R. in't Velt",
  title =        "An architecture framework for application-specific and
                 scalable architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "362--369",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kim:1989:PLS,
  author =       "K. Kim and V. K. Prasanna-Kumar",
  title =        "Perfect {Latin} squares and parallel array access",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "372--379",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Weiss:1989:ASS,
  author =       "S. Weiss",
  title =        "An aperiodic storage scheme to reduce memory conflicts
                 in vector processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "380--386",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chen:1989:AVA,
  author =       "C.-L. Chen and C.-K. Liao",
  title =        "Analysis of vector access performance on skewed
                 interleaved memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "387--394",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Agarwal:1989:ABS,
  author =       "A. Agarwal and M. Cherian",
  title =        "Adaptive backoff synchronization techniques",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "396--406",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stenstrom:1989:CCP,
  author =       "P. Stenstr{\"o}m",
  title =        "A cache consistency protocol for multiprocessors with
                 multistage networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "407--415",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Su:1989:DSM,
  author =       "H.-M. Su and P.-C. Yew",
  title =        "On data synchronization for multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "3",
  pages =        "416--423",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{vanTilborg:1989:PFD,
  author =       "A. M. van Tilborg",
  title =        "Panel on future directions in parallel computer
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "4",
  pages =        "3--53",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gunther:1989:PBS,
  author =       "N. J. Gunther and M. T. Noga",
  title =        "{ParcBench}: a benchmark for shared-memory
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "4",
  pages =        "54--61",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Elkateeb:1989:PSR,
  author =       "A. Elkateeb and T. Le-Ngoc",
  title =        "A priority strategy on {RISC} for real-time
                 multitasking software applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "4",
  pages =        "62--68",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Oyang:1989:MCA,
  author =       "Y.-J. Oyang",
  title =        "A multiprocessor configuration in accordance with the
                 aspects of physical and systems design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "4",
  pages =        "69--73",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seebauer:1989:MCEa,
  author =       "H. Seebauer",
  title =        "A memory controller executing segment operations in
                 time {$ O(1) $}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "4",
  pages =        "74--81",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schwartz:1989:DDD,
  author =       "R. J. Schwartz",
  title =        "The design and development of a dynamic program
                 behavior measurement tool for the {Intel 8086\slash
                 88}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "4",
  pages =        "82--94",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Martin:1989:FAM,
  author =       "A. J. Martin and S. M. Burns and T. K. Lee and D.
                 Borkovic and P. J. Hazewindus",
  title =        "The first asynchronous microprocessor: the test
                 results",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "4",
  pages =        "95--110",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cornett:1989:UMS,
  author =       "F. Cornett",
  title =        "The {UT1000} microprogramming simulator: an
                 educational tool",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "4",
  pages =        "111--118",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yuen:1989:BDD,
  author =       "C. K. Yuen and W. F. Wong",
  title =        "A bidirectional data driven {Lisp} engine for the
                 direct execution of {Lisp} in parallel",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "4",
  pages =        "119--130",
  month =        jun,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smotherman:1989:SBT,
  author =       "M. Smotherman",
  title =        "A sequencing-based taxonomy of {I/O} systems and
                 review of historical machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "5--15",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cousins:1989:DCR,
  author =       "R. Cousins",
  title =        "{DMA} considerations on {RISC} workstations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "16--23",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Katz:1989:PHP,
  author =       "R. H. Katz",
  title =        "A project on high performance {I/O} subsystems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "24--31",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dibble:1989:BSB,
  author =       "P. C. Dibble and M. L. Scott",
  title =        "Beyond striping: the bridge multiprocessor file
                 system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "32--39",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reddy:1989:SPD,
  author =       "A. L. N. Reddy and P. Banerjee",
  title =        "A study parallel disk organizations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "40--47",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1989:MRT,
  author =       "J. M. Smith and G. Q. {Maguire, Jr.}",
  title =        "Measured response times for page-sized fetches on a
                 network",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "48--54",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wolman:1989:ISI,
  author =       "B. Wolman and T. M. Olson",
  title =        "{IOBENCH}: a system independent {IO} benchmark",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "55--70",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Oslon:1989:DAP,
  author =       "T. M. Oslon",
  title =        "Disk array performance in a random {IO} environment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "71--77",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wolman:1989:ASB,
  author =       "B. L. Wolman",
  title =        "An analysis of server-based locking",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "78--82",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Debaere:1989:IPC,
  author =       "E. H. Debaere",
  title =        "Instruction-path coprocessing to solve some {RISC}
                 problems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "83--94",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seebauer:1989:MCEb,
  author =       "H. Seebauer",
  title =        "A memory controller executing segment operations in
                 time {$ O(1) $}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "95--102",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chiu:1989:RLF,
  author =       "P. K. Chiu",
  title =        "Representation of logic functions by {\tt if--then}
                 clauses",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "103--107",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Baleanu:1989:ECC,
  author =       "C. Baleanu and D. Tomescu",
  title =        "Embedding computers in a cellular array",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "108--115",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lass:1989:HES,
  author =       "S. Lass",
  title =        "On hardware enhanced 80386 software emulation,
                 compiled emulation, a program distribution language,
                 and pack computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "5",
  pages =        "116--118",
  month =        sep,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Litaize:1989:MSM,
  author =       "Daniel Litaize and Omar Hammami and Mustapha Lalam and
                 Adelaziz Mzoughi and Pascl Sinrat",
  title =        "Multiprocessors with a serial multiport memory and a
                 pseudo crossbar of serial links used as a
                 processor-memory switch",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "8--21",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fritsch:1989:DSM,
  author =       "G. Fritsch and W. Henning and H. Hesenuer and R. Klar
                 and C. U. Linster and C. w. Oehlrich and P. Schlenk and
                 J. Vokert",
  title =        "Distributed shared memory multiprocessor architecture
                 {MEMSY} for high performance parallel computations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "22--35",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mendelson:1989:SCC,
  author =       "A. Mendelson and D. K. Pradhan and A. D. Singh",
  title =        "A single cached copy data coherence scheme for
                 multiprocessor systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "36--49",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Feitelson:1989:AMU,
  author =       "Dror G. Feitelson and Larry Rudolph",
  title =        "Architecture for a multi-user general-purpose parallel
                 system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "50--56",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Quammen:1989:RWA,
  author =       "D. Quammen and D. R. Miller and D. Tabak",
  title =        "Register window architecture for multitasking
                 applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "57--66",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rosenberg:1989:EEI,
  author =       "Arnold Rosenberg",
  title =        "Efficient emulations of interconnection networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "67--79",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Scherson:1989:DPC,
  author =       "Isaac D. Scherson and Peter F. Corbett",
  title =        "Description and performance of a class of orthogonal
                 multiprocessor networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "80--90",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{David:1989:EIB,
  author =       "Llana David and Ran Ginosar and Michael Yoeli",
  title =        "An efficient implementation of {Boolean} functions and
                 finite state machine as self-timed circuit",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "91--104",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dollan:1989:CSP,
  author =       "Apostolos Dollan and Robert F. Krick",
  title =        "The case for the sustained performance computer
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "129--136",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Johnson:1989:WSP,
  author =       "Eric E. Johnson",
  title =        "Working set prefetching for cache memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "137--141",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1989:MPC,
  author =       "K. e H. Lee and C. H. Lam",
  title =        "Massage-passing controller for a shared-memory
                 multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "142--149",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hsu:1989:LCF,
  author =       "Tsong-Chih Hsu and Ling-Yang Kung",
  title =        "Logic and conflict-free vector addresses",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "150--153",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hsu:1989:AGU,
  author =       "Tsong-Chih Hsu and Ling-Yang Kung",
  title =        "An address generation unit for array accessing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "154--160",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hsu:1989:HMP,
  author =       "Tsong-Chih Hsu and Ling-Yang Kung",
  title =        "A hardware mechanism for priority queue",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "17",
  number =       "6",
  pages =        "162--169",
  month =        dec,
  year =         "1989",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dvorak:1990:MAS,
  author =       "V. Dvorak",
  title =        "Microsequencer architecture supporting arbitrary
                 branching up to 2m targets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "1",
  pages =        "9--9",
  month =        mar,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dongarra:1990:PVC,
  author =       "Jack J. Dongarra",
  title =        "Performance of various computers using standard linear
                 equations software",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "1",
  pages =        "17--17",
  month =        mar,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hsu:1990:CFO,
  author =       "Tsong---Chih Hsu and Ling---Yang Kung",
  title =        "A comment on {``A Fetch-and-Op Implementation for
                 Parallel Computers''}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "1",
  pages =        "32--32",
  month =        mar,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cousins:1990:NAC,
  author =       "Robert Cousins",
  title =        "A novel approach to character interfaces",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "1",
  pages =        "35--35",
  month =        mar,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cousins:1990:RPI,
  author =       "Robert Cousins",
  title =        "A reentrant peripheral interface",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "1",
  pages =        "43--43",
  month =        mar,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anderson:1990:ACS,
  author =       "Noel W. Anderson",
  title =        "Amorphous computer system architecture: a preliminary
                 look",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "1",
  pages =        "51--51",
  month =        mar,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Oyang:1990:CEA,
  author =       "Yen-Jen Oyang and Bor-Ting Chang and Shu-May Lin",
  title =        "A cost-effective approach to implement a long
                 instruction word microprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "1",
  pages =        "59--59",
  month =        mar,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fritsch:1990:PBA,
  author =       "C. Fritsch and T. S{\'a}nchez and J. Anaya",
  title =        "Primitive based architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "1",
  pages =        "73--73",
  month =        mar,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lorin:1990:MRC,
  author =       "Harold Lorin",
  title =        "A model for recentralization of computing:
                 (distributed processing comes home)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "1",
  pages =        "81--81",
  month =        mar,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Teodosiu:1990:CTD,
  author =       "Dan Teodosiu",
  title =        "Computing in three dimensions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "1",
  pages =        "99--99",
  month =        mar,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Frazier:1990:ASM,
  author =       "Gary Frazier",
  title =        "{Ariel}: a scalable multiprocessor for the simulation
                 of neural networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "1",
  pages =        "107--107",
  month =        mar,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Colwell:1990:BRH,
  author =       "Robert P. Colwell",
  title =        "Book review: {{\em High-Level Language Computer
                 Architecture\/}} edited by {Veljko Milutinovic
                 (Computer Science Press, 1989)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "1",
  pages =        "120--122",
  month =        mar,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Parhami:1990:BRA,
  author =       "Behrooz Parhami",
  title =        "Book review: {{\em Advanced Research in VLSI}}, edited
                 by {Charles L. Seitz (The MIT Press, Cambridge, MA,
                 1989, 373 pp.)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "1",
  pages =        "122--123",
  month =        mar,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:32 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Matthes:1990:HRG,
  author =       "Wolfgang Matthes",
  title =        "Hardware {Resources}: a generalizing view on computer
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "2",
  pages =        "7--14",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rauchwerger:1990:MFP,
  author =       "Lawrence Rauchwerger and Michael P. Farmwald",
  title =        "A multiple floating point coprocessor architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "2",
  pages =        "15--24",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Glew:1990:SCT,
  author =       "Andy Glew and Wen-Mei Hwu",
  title =        "Snoopy cache test-and-test-and-set without excessive
                 bus contention",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "2",
  pages =        "25--32",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Higbee:1990:QEC,
  author =       "Lee Higbee",
  title =        "Quick and easy cache performance analysis",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "2",
  pages =        "33--44",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Park:1990:ISF,
  author =       "Arvin Park and Jeffrey C. Becker and Richard J.
                 Lipton",
  title =        "{IOStone}: a synthetic file system benchmark",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "2",
  pages =        "45--52",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pnevmatikatos:1990:CPI,
  author =       "Dionisios N. Pnevmatikatos and Mark D. Hill",
  title =        "Cache performance of the integer {SPEC} benchmarks on
                 a {RISC}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "2",
  pages =        "53--68",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ruighaver:1990:MND,
  author =       "A. B. Ruighaver",
  title =        "A modular network for dense optical interconnection of
                 processing elements",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "2",
  pages =        "69--75",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{DeGloria:1990:VVI,
  author =       "Alessandro {De Gloria}",
  title =        "{VISA}: a variable instruction set architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "2",
  pages =        "76--84",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Williams:1990:ADR,
  author =       "Fleur L. Williams and Gordon B. Steven",
  title =        "Address and data register separation on the {M68000}
                 family",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "2",
  pages =        "85--89",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Adve:1990:WON,
  author =       "Sarita V. Adve and Mark D. Hill",
  title =        "Weak ordering---a new definition",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "2--14",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gharachorloo:1990:MCE,
  author =       "Kourosh Gharachorloo and Daniel Lenoski and James
                 Laudon and Phillip Gibbons and Anoop Gupta and John
                 Hennessy",
  title =        "Memory consistency and event ordering in scalable
                 shared-memory multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "15--26",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1990:SMC,
  author =       "Joonwon Lee and Umakishore Ramachandran",
  title =        "Synchronization with multiprocessor caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "27--37",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chuang:1990:DPA,
  author =       "Po-Jen Chuang and Nian-Feng Tzeng",
  title =        "Dynamic processor allocation in hypercube computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "40--49",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Youssef:1990:NAF,
  author =       "Abdou Youssef and Bruce Arden",
  title =        "A new approach to fast control of $ r_2 \times r_2 $
                 $3$-stage {Benes} networks of $ r \times r$ crossbar
                 switches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "50--59",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dally:1990:VCF,
  author =       "William J. Dally",
  title =        "Virtual-channel flow control",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "60--68",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Borkar:1990:SSM,
  author =       "Shekhar Borkar and Robert Cohn and George Cox and
                 Thomas Gross and H. T. Kung and Monica Lam and Margie
                 Levine and Brian Moore and Wire Moore and Craig
                 Peterson and Jim Susman and Jim Sutton and John
                 Urbanski and Jon Webb",
  title =        "Supporting systolic and memory communication in
                 {iWarp}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "70--81",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Papadopoulos:1990:MET,
  author =       "Gregory M. Papadopoulos and David E. Culler",
  title =        "{Monsoon}: an explicit token-store architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "82--91",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Annaratone:1990:KPP,
  author =       "Marco Annaratone and Marco Fillo and Kiyoshi
                 Nakabayashi and Marc Viredaz",
  title =        "The {K2} parallel processor: architecture and hardware
                 implementation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "92--101",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Agarwal:1990:APA,
  author =       "Anant Agarwal and Beng-Hong Lim and David Kranz and
                 John Kubiatowicz",
  title =        "{APRIL}: a processor architecture for
                 multiprocessing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "104--114",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bisiani:1990:PDS,
  author =       "Roberto Bisiani and Mosur Ravishankar",
  title =        "{PLUS}: a distributed shared-memory system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "115--124",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bennett:1990:ASC,
  author =       "John K. Bennett and John B. Carter and Willy
                 Zwaenepoel",
  title =        "Adaptive software cache management for distributed
                 shared memory architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "125--134",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ditzel:1990:BSV,
  author =       "David R. Ditzel and John L. Hennessy and Bernie Rudin
                 and Alan Jay Smith and Stephen L. Squires and Zeke
                 Zalcstein",
  title =        "Big science versus little science---do you have to
                 build it? (panel session)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "136--136",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{OKrafka:1990:EET,
  author =       "Brian W. O'Krafka and A. Richard Newton",
  title =        "An empirical evaluation of two memory-efficient
                 directory methods",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "138--147",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lenoski:1990:DBC,
  author =       "Daniel Lenoski and James Laudon and Kourosh
                 Gharachorloo and Anoop Gupta and John Hennessy",
  title =        "The directory-based cache coherence protocol for the
                 {DASH} multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "148--159",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Przybylski:1990:PIB,
  author =       "Steven Przybylski",
  title =        "The performance impact of block sizes and fetch
                 strategies",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "160--169",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Alpert:1990:PCL,
  author =       "D. Alpert and A. Averbuch and O. Danieli",
  title =        "Performance comparison of load\slash store and
                 symmetric instruction set architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "172--181",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Davidson:1990:RCB,
  author =       "Jack W. Davidson and David B. Whalley",
  title =        "Reducing the cost of branches by using registers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "182--191",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Love:1990:ISV,
  author =       "Carl E. Love and Harry F. Jordan",
  title =        "An investigation of static versus dynamic scheduling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "192--201",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bhandarkar:1990:VVA,
  author =       "Dileep Bhandarkar and Richard Brunner",
  title =        "{VAX} vector architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "204--215",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Horst:1990:MII,
  author =       "Robert W. Horst and Richard L. Harris and Robert L.
                 Jardine",
  title =        "Multiple instruction issue in the {NonStop Cyclone}
                 processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "216--226",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thakkar:1990:POA,
  author =       "Shreekant S. Thakkar and Mark Sweiger",
  title =        "Performance of an {OLTP} application on symmetry
                 multiprocessor system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "228--238",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chen:1990:ISG,
  author =       "Ding-Kai Chen and Hong-Men Su and Pen-Chung Yew",
  title =        "The impact of synchronization and granularity on
                 parallel systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "239--248",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bugge:1990:TDS,
  author =       "H{\aa}kon O. Bugge and Ernst H. Kristiansen and
                 Bj{\o}rn O. Bakka",
  title =        "Trace-driven simulations for a two-level cache design
                 in open bus systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "250--259",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hsu:1990:PMT,
  author =       "Jiun-Ming Hsu and Prithviraj Banerjee",
  title =        "Performance measurement and trace driven simulation of
                 parallel {CAD} and numeric applications on a hypercube
                 multicomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "260--269",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Borg:1990:GAV,
  author =       "Anita Borg and R. E. Kessler and David W. Wall",
  title =        "Generation and analysis of very long address traces",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "270--279",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Holmer:1990:FPE,
  author =       "Bruce K. Holmer and Barton Sano and Michael Carlton
                 and Peter {Van Roy} and Ralph Haygood and William R. Bush
                 and Alvin M. Despain and Joan M. Pendleton and Tep
                 Dobry",
  title =        "Fast {Prolog} with an extended general purpose
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "282--291",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Alkalaj:1990:ASM,
  author =       "Leon Alkalaj and Tom{\'a}s Lang and Milo{\v{s}}
                 Ercegovac",
  title =        "Architectural support for the management of
                 tightly-coupled fine-grain goals in flat concurrent
                 {Prolog}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "292--301",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ho:1990:BAD,
  author =       "Samuel Ho and Lawrence Snyder",
  title =        "Balance in architectural design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "302--310",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reddy:1990:SBP,
  author =       "A. L. Narasimha Reddy and Prithviraj Banerjee",
  title =        "A study of {I/O} behavior of perfect benchmarks on a
                 multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "312--321",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chen:1990:MPS,
  author =       "Peter M. Chen and David A. Patterson",
  title =        "Maximizing performance in a striped disk array",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "322--331",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shin:1990:DAH,
  author =       "Kang G. Shin and Greg Dykema",
  title =        "A distributed {I/O} architecture for {HARTS}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "332--342",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1990:BBS,
  author =       "Michael D. Smith and Monica S. Lam and Mark A.
                 Horowitz",
  title =        "Boosting beyond static scheduling in a superscalar
                 processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "344--354",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Taylor:1990:TSL,
  author =       "George Taylor and Peter Davies and Michael Farmwald",
  title =        "The {TLB} slice---a low-cost high-speed address
                 translation mechanism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "355--363",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jouppi:1990:IDM,
  author =       "Norman P. Jouppi",
  title =        "Improving direct-mapped cache performance by the
                 addition of a small fully-associative cache and
                 prefetch buffers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "364--373",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Davidson:1990:BTO,
  author =       "Edward S. Davidson and Gurindar S. Sohl and Joseph A.
                 Fisher and Greg Grohoski and Yale Pratt and J. E. Smith
                 and David R. Stiles",
  title =        "Better than one operation per clock (panel): vectors,
                 {VLIW}, and superscalar",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3a",
  pages =        "376--376",
  month =        jun,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Alverson:1990:TCS,
  author =       "Robert Alverson and David Callahan and Daniel Cummings
                 and Brian Koblenz and Allan Porterfield and Burton
                 Smith",
  title =        "The {Tera} computer system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "1--6",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hwang:1990:ORB,
  author =       "K. Hwang and M. Dubois and D. K. Panda and S. Rao and
                 S. Shang and A. Uresin and W. Mao and H. Nair and M.
                 Lytwyn and F. Hsieh and J. Liu and S. Mehrotra and C.
                 M. Cheng",
  title =        "{OMP}: a {RISC}-based multiprocessor using
                 orthogonal-access memories and multiple spanning
                 buses",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "7--22",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dai:1990:BAS,
  author =       "Kechang Dai and Wolfgang K. Giloi",
  title =        "A basic architecture supporting {LGDG} computation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "23--33",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Min:1990:ECS,
  author =       "Sang Lyul Min and Jean-Loup Baer and Hyoung-Joo Kim",
  title =        "An efficient caching support for critical sections in
                 large-scale shared-memory multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "34--47",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nagashima:1990:IFA,
  author =       "Umpei Nagashima and Fumio Nishimoto and Takashi
                 Shibata and Hiroshi Itoh and Minoru Gotoh",
  title =        "An improvement of {I/O} function for auxiliary
                 storage: parallel {I/O} for a large scale
                 supercomputing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "48--59",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tzeng:1990:AVH,
  author =       "Nian-Feng Tzeng",
  title =        "Analysis of a variant hypercube topology",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "60--70",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{vanderHouwen:1990:POS,
  author =       "P. J. van der Houwen and B. P. Sommeijer",
  title =        "Parallel {ODE} solvers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "71--81",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dayde:1990:UPL,
  author =       "M. J. Dayd{\'e} and I. S. Duff",
  title =        "Use of parallel level 3 {BLAS} in {LU} factorization
                 on three vector multiprocessors the {ALLIANT FX/80},
                 the {CRAY-2}, and the {IBM 3090 VF}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "82--95",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Houstis:1990:ENS,
  author =       "E. N. Houstis and J. R. Rice and N. P. Chrisochoides
                 and H. C. Karathanasis and P. N. Papachiou and M. K.
                 Samartzis and E. A. Vavalis and Ko Yang Wang and S.
                 Weerawarana",
  title =        "{//ELLPACK}: a numerical simulation programming
                 environment for parallel {MIMD} machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "96--107",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Christara:1990:SCP,
  author =       "Christina C. Christara",
  title =        "{Schur} complement preconditioned conjugate gradient
                 methods for spline collocation equations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "108--120",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chung:1990:COP,
  author =       "Kuo-Liang Chung and Ferng-Ching Lin and Wen-Chin
                 Chen",
  title =        "Cost-optimal parallel {B}-spline interpolations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "121--131",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gallivan:1990:SGS,
  author =       "K. Gallivan and A. Sameh and Z. Zlatev",
  title =        "Solving general sparse linear systems using conjugate
                 gradient-type methods",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "132--139",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yuba:1990:DCD,
  author =       "Toshitsugu Yuba and Toshio Shimada and Yoshinori
                 Yamaguchi and Kei Hiraki and Shuichi Sakai",
  title =        "Dataflow computer development in {Japan}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "140--147",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sarkar:1990:PPO,
  author =       "Vivek Sarkar and David Cann",
  title =        "{POSC}---a partitioning and optimizing {SISAL}
                 compiler",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "148--164",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bodin:1990:LOH,
  author =       "Fran{\c{c}}ois Bodin and Fran{\c{c}}ois Charot",
  title =        "Loop optimization for horizontal microcoded machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "164--176",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tang:1990:CTD,
  author =       "Peiyi Tang and Pen-Chung Yew and Chuan-Qi Zhu",
  title =        "Compiler techniques for data synchronization in nested
                 parallel loops",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "177--186",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hudak:1990:CTD,
  author =       "David E. Hudak and Santosh G. Abraham",
  title =        "Compiler techniques for data partitioning of
                 sequentially iterated parallel loops",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "187--200",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Klappholz:1990:PAA,
  author =       "David Klappholz and Kleanthis Psarris and Xiangyun
                 Kong",
  title =        "On the perfect accuracy of an approximate subscript
                 analysis test",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "201--212",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Malony:1990:HBP,
  author =       "Allen D. Malony and Daniel A. Reed",
  title =        "A hardware-based performance monitor for the {Intel
                 iPSC/2} hypercube",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "213--226",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dimpsey:1990:PDD,
  author =       "R. T. Dimpsey and R. K. Iyer",
  title =        "Performance degradation due to multiprogramming and
                 system overheads in real workloads: case study on a
                 shared memory multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "227--238",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Saad:1990:SBP,
  author =       "Youcef Saad and Harry A. G. Wijshoff",
  title =        "{SPARK}: a benchmark package for sparse computations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "239--253",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cybenko:1990:SPE,
  author =       "George Cybenko and Lyle Kipp and Lynn Pointer and
                 David Kuck",
  title =        "Supercomputer performance evaluation and the {Perfect
                 Benchmarks}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "254--266",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Noor:1990:SLS,
  author =       "Ahmed K. Noor and Jeanne M. Peters",
  title =        "Strategies for large-scale structural problems on
                 high-performance computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "267--280",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zecca:1990:ECV,
  author =       "V. Zecca and A. Kamel",
  title =        "Elastodynamics on clustered vector multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "281--290",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Eijkhout:1990:IPP,
  author =       "Victor Eijkhout",
  title =        "Implementation of $5$-point\slash $9$-point
                 multi-level methods on hypercube architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "291--295",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chen:1990:SBV,
  author =       "Philip C. Chen",
  title =        "Supercomputer-based visualization systems used for
                 analyzing output data of a numerical weather prediction
                 model",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "296--309",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Takahashi:1990:PAW,
  author =       "Yoshizo Takahashi and Shigetaka Sasaki",
  title =        "Parallel automated wire-routing with a number of
                 competing processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "310--317",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chan:1990:HAA,
  author =       "Tony F. Chan",
  title =        "Hierarchical algorithms and architectures for parallel
                 scientific computing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "318--329",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1990:IDA,
  author =       "Kevin Smith and Bill Appelbe and Kurt Stirewalt",
  title =        "Incremental dependence analysis for interactive
                 parallelization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "330--341",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ruhl:1990:PFC,
  author =       "Roland R{\"u}hl and Marco Annaratone",
  title =        "Parallelization of {FORTRAN} code on
                 distributed-memory parallel processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "342--353",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gornish:1990:CDD,
  author =       "Edward H. Gornish and Elana D. Granston and Alexander
                 V. Veidenbaum",
  title =        "Compiler-directed data prefetching in multiprocessors
                 with memory hierarchies",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "354--368",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gao:1990:TEF,
  author =       "Guang R. Gao and Herbert H. J. Hum and Yue-Bong Wong",
  title =        "Towards efficient fine-grain software pipelining",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "369--379",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Andre:1990:PSM,
  author =       "Fran{\c{c}}oise Andr{\'e} and Jean-Louis Pazat and
                 Henry Thomas",
  title =        "{Pandore}: a system to manage data distribution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "380--388",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fatoohi:1990:VPA,
  author =       "Rod A. Fatoohi",
  title =        "Vector performance analysis of the {NEC SX-2}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "389--400",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bodin:1990:PEP,
  author =       "Fran{\c{c}}ois Bodin and Daniel Windheiser and William
                 Jalby and Daya Atapattu and Mannho Lee and Dennis
                 Gannon",
  title =        "Performance evaluation and prediction for parallel
                 algorithms on the {BBN GP1000}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "401--413",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Brochard:1990:DAH,
  author =       "Luigi Brochard and Alex Freau",
  title =        "Designing algorithms on hierarchical memory
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "414--427",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bucher:1990:ACM,
  author =       "Ingrid Y. Bucher and Donald A. Calahan",
  title =        "Access conflicts in multiprocessor memories queueing
                 models and simulation studies",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "428--438",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Luque:1990:ITD,
  author =       "Emilio Luque and Ana Ripoll and Porfidio Hern{\'a}ndez
                 and Tom{\'a}s Margalef",
  title =        "Impact of task duplication on static-scheduling
                 performance in multiprocessor systems with variable
                 execution-time tasks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "439--446",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gerasoulis:1990:CTG,
  author =       "Apostolos Gerasoulis and Sesh Venugopal and Tao Yang",
  title =        "Clustering task graphs for message passing
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "447--456",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Paalvast:1990:MPP,
  author =       "Edwin M. Paalvast and Arjan J. van Gemund and Henk J.
                 Sips",
  title =        "A method for parallel program generation with an
                 application to the {Booster} language",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "457--469",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tsoukarellas:1990:RTS,
  author =       "M. A. Tsoukarellas and T. S. Papatheodorou",
  title =        "A run time support system for multiprocessor
                 machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "470--478",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hey:1990:STP,
  author =       "Anthony J. G. Hey",
  title =        "Supercomputing with transputers---past, present and
                 future",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "3b",
  pages =        "479--489",
  month =        sep,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:03 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1990:EA,
  author =       "Burton Smith",
  title =        "The end of architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "4",
  pages =        "10--17",
  month =        dec,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hill:1990:WS,
  author =       "Mark D. Hill",
  title =        "What is scalability?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "4",
  pages =        "18--21",
  month =        dec,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Laplante:1990:NSI,
  author =       "P. A. Laplante",
  title =        "A novel single instruction computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "4",
  pages =        "22--26",
  month =        dec,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ginosar:1990:PAP,
  author =       "Ran Ginosar and Nick Michell",
  title =        "On the potential of asynchronous pipelined
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "4",
  pages =        "27--34",
  month =        dec,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Oyang:1990:EEA,
  author =       "Yen-Jen Oyang and Chun-Hung Wen and Yu-Fen Chen and
                 Shu-May Lin",
  title =        "The effect of employing advanced branching mechanisms
                 in superscalar processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "4",
  pages =        "35--52",
  month =        dec,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Deville:1990:LCU,
  author =       "Yannick Deville",
  title =        "A low-cost usage-based replacement algorithm for cache
                 memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "4",
  pages =        "52--58",
  month =        dec,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gunther:1990:HSM,
  author =       "Bernard K. Gunther",
  title =        "A high speed mechanism for short branches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "4",
  pages =        "59--61",
  month =        dec,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McLaughlin:1990:DFD,
  author =       "Robert McLaughlin",
  title =        "Design for fast {DSP} machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "4",
  pages =        "62--66",
  month =        dec,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Joerg:1990:SPN,
  author =       "Werner B. Joerg",
  title =        "A subclass of {Petri Nets} as design abstraction for
                 parallel architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "4",
  pages =        "67--77",
  month =        dec,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1990:UN,
  author =       "Mark Thorson",
  title =        "{Usenet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "4",
  pages =        "80--89",
  month =        dec,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Langdon:1990:BRH,
  author =       "Glen G. {Langdon, Jr.}",
  title =        "Book review: {{\em Highly Parallel Computing\/}} by
                 {George Almasi and Allan Gotlieb (Benjamin\slash
                 Cummings, 1989)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "4",
  pages =        "90--90",
  month =        dec,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Langdon:1990:BRS,
  author =       "Glen G. {Langdon, Jr.}",
  title =        "Book review: {{\em Solving Problems on Concurrent
                 Processors, Vol II: Software for Concurrent
                 Processors\/}} by {I. Angus, G. Fox, J. Kim, and D.
                 Walker (Prentice-Hall, 1990)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "4",
  pages =        "90--91",
  month =        dec,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dikotter:1990:BRD,
  author =       "Marc Dikotter",
  title =        "Book review: {{\em The Definition of Standard ML\/}}
                 by {R. Milner, M. Torte, R. Harper}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "18",
  number =       "4",
  pages =        "91--91",
  month =        dec,
  year =         "1990",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Leighton:1991:SPS,
  author =       "F. T. Leighton",
  title =        "Selected Papers from the {Symposium on Parallel
                 Algorithms and Architectures}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "5--5",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ngai:1991:FAR,
  author =       "John Y. Ngai and Charles L. Seitz",
  title =        "A framework for adaptive routing in multicomputer
                 networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "6--14",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Beigel:1991:PNI,
  author =       "Richard Beigel and Clydel P. Kruskal",
  title =        "Processor networks and interconnection networks
                 without long wires (extended abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "15--24",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Annexstein:1991:FTH,
  author =       "Fred Annexstein",
  title =        "Fault tolerance in hypercube-derivative networks
                 (preliminary version)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "25--34",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fujimoto:1991:VTM,
  author =       "Richard M. Fujimoto",
  title =        "The {Virtual Time Machine}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "35--44",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bilardi:1991:OVA,
  author =       "Ginfranco Bilardi and Scot W. Hornick and Majid
                 Sarrafzadeh",
  title =        "Optimal {VLSI} architectures for multidimensional
                 {DFT} (preliminary version)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "45--52",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thomborson:1991:SIM,
  author =       "Clark D. Thomborson and Belle W.-Y. Wei",
  title =        "Systolic implementations of a move-to-front text
                 compressor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "53--60",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Knight:1991:TLL,
  author =       "Thomas F. {Knight, Jr.}",
  title =        "Technologies for low latency interconnection
                 switches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "61--68",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Herbordt:1991:MPA,
  author =       "Martin C. Herbordt and Charles C. Weems and James C.
                 Corbett",
  title =        "Message-passing algorithms for a {SIMD} torus with
                 coteries",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "69--78",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Konstantinidou:1991:CRP,
  author =       "S. Konstantinidou and L. Snyder",
  title =        "The chaos router: a practical application of
                 randomization in network routing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "79--88",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bruck:1991:RAE,
  author =       "Jehoshua Bruck and Robert Cypher and Danny Soroker",
  title =        "Running algorithms efficiently on faulty hypercubes
                 (extended abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "89--96",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nishimura:1991:ASM,
  author =       "Naomi Nishimura",
  title =        "Asynchronous shared memory parallel computation
                 (preliminary version)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "97--105",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shand:1991:HSL,
  author =       "M. Shand and P. Bertin and J. Vuillemin",
  title =        "Hardware speedups in long integer multiplication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "106--113",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thapar:1991:CCL,
  author =       "Manu Thapar and Bruce Delagi",
  title =        "Cache coherence for large scale shared memory
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "114--119",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Grabienski:1991:FFS,
  author =       "Peter Grabienski",
  title =        "{FLIP-FLOP}: a stack-oriented multiprocessing system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "120--127",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Price:1991:TAD,
  author =       "Camille C. Price",
  title =        "Task allocation in data flow multiprocessors: an
                 annotated bibliography",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "128--134",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Adams:1991:PPP,
  author =       "Rod Adams and Gordon Steven",
  title =        "A parallel pipelined processor with conditional
                 instruction execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "135--142",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1991:UNa,
  author =       "Mark Thorson",
  title =        "{Usenet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "146--150",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hilton:1991:BRS,
  author =       "Michael L. Hilton",
  title =        "Book review: {{\em Systems Programming in Parallel
                 Logic Languages\/}} by {Ian Foster (Prentice Hall,
                 1990)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "151--151",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anthony:1991:BRT,
  author =       "Keith Anthony",
  title =        "Book review: {{\em Technology Projection Modeling of
                 Future Computer Systems\/}} by {Al Cutaia
                 (Prentice-Hall, 1990)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "152--153",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schneck:1991:BRO,
  author =       "Paul B. Schneck",
  title =        "Book review: {{\em Optimizing FORTRAN Programs\/}} by
                 {C. F. Schofield (Halstead Press, 1989)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "153--154",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bernecky:1991:BRMa,
  author =       "Robert Bernecky",
  title =        "Book review: {{\em Multiprocessors\/}} by {Daniel
                 Tabak (Prentice Hall, Englewood Cliffs, NJ)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "154--156",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bernecky:1991:BRMb,
  author =       "Robert Bernecky",
  title =        "Book review: {{\em Multiprocessor Performance\/}} by
                 {Erol Gelenbe (J. Wiley \& Sons, Chichester,
                 England)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "156--157",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fulcher:1991:BRN,
  author =       "John Fulcher",
  title =        "Book review: {{\em Neural Net Applications and
                 Products\/}} by {Richard K. Miller, Terri C. Walker,
                 and Anne M. Ryan (SEAl Technical Publications, 1990)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "1",
  pages =        "157--158",
  month =        mar,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wolfe:1991:VIS,
  author =       "Andrew Wolfe and John P. Shen",
  title =        "A variable instruction stream extension to the {VLIW}
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "2--14",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Katevenis:1991:RBP,
  author =       "Manolis Katevenis and Nestoras Tzartzanis",
  title =        "Reducing the branch penalty by rearranging
                 instructions in a double-width memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "15--27",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1991:FPP,
  author =       "Roland L. Lee and Alex Y. Kwok and Fay{\'e} A.
                 Briggs",
  title =        "The floating point performance of a superscalar
                 {SPARC} processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "28--37",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Callahan:1991:SP,
  author =       "David Callahan and Ken Kennedy and Allan Porterfield",
  title =        "Software prefetching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "40--52",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sohi:1991:HBD,
  author =       "Gurindar S. Sohi and Manoj Franklin",
  title =        "High-bandwidth data memory systems for superscalar
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "53--62",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lam:1991:CPO,
  author =       "Monica D. Lam and Edward E. Rothberg and Michael E.
                 Wolf",
  title =        "The cache performance and optimizations of blocked
                 algorithms",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "63--74",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mogul:1991:ECS,
  author =       "Jeffrey C. Mogul and Anita Borg",
  title =        "The effect of context switches on cache performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "75--84",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Keppel:1991:PIF,
  author =       "David Keppel",
  title =        "A portable interface for on-the-fly instruction space
                 modification",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "86--95",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Appel:1991:VMP,
  author =       "Andrew W. Appel and Kai Li",
  title =        "Virtual memory primitives for user programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "96--107",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anderson:1991:IAO,
  author =       "Thomas E. Anderson and Henry M. Levy and Brian N.
                 Bershad and Edward D. Lazowska",
  title =        "The interaction of architecture and operating system
                 design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "108--120",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bradlee:1991:IRA,
  author =       "David G. Bradlee and Susan J. Eggers and Robert R.
                 Henry",
  title =        "Integrating register allocation and instruction
                 scheduling for {RISCs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "122--131",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Benitez:1991:CGS,
  author =       "Manuel E. Benitez and Jack W. Davidson",
  title =        "Code generation for streaming: an access\slash execute
                 mechanism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "132--141",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bagrodia:1991:EIH,
  author =       "Rajive Bagrodia and Sharad Mathur",
  title =        "Efficient {Implementation} of high-level parallel
                 programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "142--151",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mangione-Smith:1991:VRD,
  author =       "William Mangione-Smith and Santosh G. Abraham and
                 Edward S. Davidson",
  title =        "Vector register design for polycyclic vector
                 scheduling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "154--163",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Culler:1991:FGP,
  author =       "David E. Culler and Anurag Sah and Klaus E. Schauser
                 and Thorsten von Eicken and John Wawrzynek",
  title =        "Fine-grain parallelism with minimal hardware support:
                 a compiler-controlled threaded abstract machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "164--175",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wall:1991:LIL,
  author =       "David W. Wall",
  title =        "Limits of instruction-level parallelism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "176--188",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1991:PCP,
  author =       "Edward K. Lee and Randy H. Katz",
  title =        "Performance consequences of parity placement in disk
                 arrays",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "190--199",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cate:1991:CCC,
  author =       "Vincent Cate and Thomas Gross",
  title =        "Combining the concepts of compression and caching for
                 a two-level filesystem",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "200--211",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bolosky:1991:NPT,
  author =       "William J. Bolosky and Michael L. Scott and Robert P.
                 Fitzgerald and Robert J. Fowler and Alan L. Cox",
  title =        "{NUMA} policies and their relation to memory
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "212--221",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chaiken:1991:LDS,
  author =       "David Chaiken and John Kubiatowicz and Anant Agarwal",
  title =        "{LimitLESS} directories: a scalable cache coherence
                 scheme",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "224--234",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Min:1991:ECB,
  author =       "Sang L. Min and Jong-Deok Choi",
  title =        "An efficient cache-based access anomaly detection
                 scheme",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "235--244",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gharachorloo:1991:PEM,
  author =       "Kourosh Gharachorloo and Anoop Gupta and John
                 Hennessy",
  title =        "Performance evaluation of memory consistency models
                 for shared-memory multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "245--257",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Freudenthal:1991:PCF,
  author =       "Eric Freudenthal and Allan Gottlieb",
  title =        "Process coordination with fetch-and-increment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "260--268",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mellor-Crummey:1991:SC,
  author =       "John M. Mellor-Crummey and Michael L. Scott",
  title =        "Synchronization without contention",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "269--278",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Johnson:1991:CRB,
  author =       "Douglas Johnson",
  title =        "The case for a read barrier",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "279--287",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cmelik:1991:AMS,
  author =       "Robert F. Cmelik and Shing I. Kong and David R. Ditzel
                 and Edmund J. Kelly",
  title =        "An analysis of {MIPS} and {SPARC} instruction set
                 utilization on the {SPEC} benchmarks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "290--302",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hall:1991:PCA,
  author =       "C. Brian Hall and Kevin O'Brien",
  title =        "Performance characteristics of architectural features
                 of the {IBM RISC System\slash 6000}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "303--309",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bhandarkar:1991:PAC,
  author =       "Dileep Bhandarkar and Douglas W. Clark",
  title =        "Performance from architecture: comparing a {RISC} and
                 a {CISC} with similar hardware organization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "2",
  pages =        "310--319",
  month =        apr,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{DeMara:1991:SPA,
  author =       "R. F. DeMara and D. I. Moldovan",
  title =        "The {SNAP-1} parallel {AI} prototype",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "2--11",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tan:1991:GEN,
  author =       "Wei Siong Tan and H. Russ and Cecil O. Alford",
  title =        "{GT-EP}: a novel high-performance real-time
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "13--21",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Higuchi:1991:IPA,
  author =       "Tetsuya Higuchi and Tatsumi Furuya and Kenichi Handa
                 and Naoto Takahashi and Hiroyasu Nishiyama and Akio
                 Kokubu",
  title =        "{IXM2}: a parallel associative processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "22--31",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kaeli:1991:BHT,
  author =       "David R. Kaeli and Philip G. Emma",
  title =        "Branch history table prediction of moving target
                 branches due to subroutine returns",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "34--42",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Klaiber:1991:ASC,
  author =       "Alexander C. Klaiber and Henry M. Levy",
  title =        "An architecture for software-controlled data
                 prefetching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "43--53",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fu:1991:DPM,
  author =       "John W. C. Fu and Janak H. Patel",
  title =        "Data prefetching in multiprocessor vector cache
                 memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "54--63",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Harper:1991:RMC,
  author =       "D. T. {Harper III}",
  title =        "Reducing memory contention in shared memory
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "66--73",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rau:1991:PRI,
  author =       "B. Ramakrishna Rau",
  title =        "Pseudo-randomly interleaved memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "74--83",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Li:1991:EMS,
  author =       "Kai Li and Karin Petersen",
  title =        "Evaluation of memory system extensions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "84--93",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dowd:1991:HPI,
  author =       "Patrick W. Dowd",
  title =        "High performance interprocessor communication through
                 optical wavelength division multiple access channels",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "96--105",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Landin:1991:RFI,
  author =       "Anders Landin and Erik Hagersten and Seif Haridi",
  title =        "Race-free interconnection networks and multiprocessor
                 consistency",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "106--115",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lin:1991:DFM,
  author =       "Xiaola Lin and Lionel M. Ni",
  title =        "Deadlock-free multicast wormhole routing in
                 multicomputer networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "116--125",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Farrens:1991:DBR,
  author =       "Matthew Farrens and Arvin Park",
  title =        "Dynamic base register caching: a technique for
                 reducing address bus width",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "128--137",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Olukotun:1991:ICH,
  author =       "O. A. Olukotun and T. N. Mudge and R. B. Brown",
  title =        "Implementing a cache for a high-performance {GaAs}
                 microprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "138--147",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kurian:1991:CPE,
  author =       "Lizyamma Kurian and Paul T. Hulina and Lee D. Coraor
                 and Dhamir N. Mannai",
  title =        "Classification and performance evaluation of
                 instruction buffering techniques",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "150--159",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nakajima:1991:OVS,
  author =       "Masaitsu Nakajima and Hiraku Nakano and Yasuhiro
                 Nakakura and Tadahiro Yoshida and Yoshiyuki Goi and
                 Yuji Nakai and Reiji Segawa and Takeshi Kishida and
                 Hiroshi Kadota",
  title =        "{OHMEGA}: a {VLSI} superscalar processor architecture
                 for numerical applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "160--168",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vajapeyam:1991:ESC,
  author =       "Sriram Vajapeyam and Gurindar S. Sohi and Wei-Chung
                 Hsu",
  title =        "An empirical study of the {CRAY Y-MP} processor using
                 the {Perfect Club} benchmarks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "170--179",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stephens:1991:ILP,
  author =       "Chriss Stephens and Bryce Cogswell and John Heinlein
                 and Gregory Palmer and John P. Shen",
  title =        "Instruction level profiling and evaluation of the
                 {IBM\slash 6000}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "180--189",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dimpsey:1991:PPT,
  author =       "R. T. Dimpsey and R. K. Iyer",
  title =        "Performance prediction and tuning on a
                 multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "190--199",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Oehlrich:1991:PEC,
  author =       "C. W. Oehlrich and A. Quick",
  title =        "Performance evaluation of a communication system for
                 transputer-networks based on monitored event traces",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "202--211",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Konstantinidou:1991:CRA,
  author =       "S. Konstantinidou and L. Snyder",
  title =        "Chaos router: architecture and performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "212--221",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shukla:1991:SPC,
  author =       "Shridhar B. Shukla and Dharma P. Agrawal",
  title =        "Scheduling pipelined communication in distributed
                 memory multiprocessors for real-time applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "222--231",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Adve:1991:DDR,
  author =       "Sarita V. Adve and Mark D. Hill and Barton P. Miller
                 and Robert H. B. Netzer",
  title =        "Detecting data races on weak memory systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "234--243",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Koldinger:1991:VTD,
  author =       "Eric J. Koldinger and Susan J. Eggers and Henry M.
                 Levy",
  title =        "On the validity of trace-driven simulation for
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "244--253",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gupta:1991:CEL,
  author =       "Anoop Gupta and John Hennessy and Kourosh Gharachorloo
                 and Todd Mowry and Wolf-Dietrich Weber",
  title =        "Comparative evaluation of latency reducing and
                 tolerating techniques",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "254--263",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chang:1991:IAF,
  author =       "Pohua P. Chang and Scott A. Mahlke and William Y. Chen
                 and Nancy J. Warter and Wen-mei W. Hwu",
  title =        "{IMPACT}: an architectural framework for
                 multiple-instruction-issue processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "266--275",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Butler:1991:SIS,
  author =       "Michael Butler and Tse-Yu Yeh and Yale Patt and Mitch
                 Alsup and Hunter Scales and Michael Shebanow",
  title =        "Single instruction stream parallelism is greater than
                 two",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "276--286",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Melvin:1991:EFG,
  author =       "Stephen Melvin and Yale Patt",
  title =        "Exploiting fine-grained parallelism through a
                 combination of hardware and software techniques",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "287--296",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Adve:1991:CHS,
  author =       "Sarita V. Adve and Vikram S. Adve and Mark D. Hill and
                 Mary K. Vernon",
  title =        "Comparison of hardware and software cache coherence
                 schemes",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "298--308",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Simoni:1991:MPL,
  author =       "Richard Simoni and Mark Horowitz",
  title =        "Modeling the performance of limited pointers
                 directories for cache coherence",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "309--319",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Quammen:1991:FRM,
  author =       "Donna J. Quammen and D. Richard Miller",
  title =        "Flexible register management for sequential programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "320--329",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bradlee:1991:ERP,
  author =       "David G. Bradlee and Susan J. Eggers and Robert R.
                 Henry",
  title =        "The effect on {RISC} performance of register set size
                 and structure versus code generation strategy",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "330--339",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Papadopoulos:1991:MRV,
  author =       "Gregory M. Papadopoulos and Kenneth R. Traub",
  title =        "Multithreading: a revisionist view of dataflow
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "342--351",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chiueh:1991:MTV,
  author =       "Tzi-cker Chiueh",
  title =        "Multi-threaded vectorization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "352--361",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Farrens:1991:SAI,
  author =       "Matthew K. Farrens and Andrew R. Pleszkun",
  title =        "Strategies for achieving improved processor
                 throughput",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "362--369",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kagimasa:1991:ASM,
  author =       "Toyohiko Kagimasa and Kikuo Takahashi and Toshiaki
                 Mori and Seiichi Yoshizumi",
  title =        "Adaptive storage management for very large
                 virtual\slash real storage systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "372--379",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hall:1991:VVA,
  author =       "Judith S. Hall and Paul T. Robinson",
  title =        "Virtualizing the {VAX} architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "380--389",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Akella:1991:MMI,
  author =       "Janaki Akella and Daniel P. Siewiorek",
  title =        "Modeling and measurement of the impact of {Input\slash
                 Output} on system performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "3",
  pages =        "390--399",
  month =        may,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wilson:1991:PSP,
  author =       "Paul R. Wilson",
  title =        "Pointer swizzling at page fault time: efficiently
                 supporting huge address spaces on standard hardware",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "6--13",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kuga:1991:DDH,
  author =       "Morihiro Kuga and Kazuaki Murakami and Shinji Tomita",
  title =        "{DSNS} (dynamically-hazard-resolved
                 statically-code-scheduled, nonuniform superscalar): yet
                 another superscalar processor architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "14--29",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ponder:1991:PVA,
  author =       "Carl Ponder",
  title =        "Performance variation across benchmark suites",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "30--36",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Conte:1991:BSB,
  author =       "Thomas M. Conte and Wen-mei W. Hwu",
  title =        "A brief survey of benchmark usage in the architecture
                 community",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "37--44",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Morris:1991:CER,
  author =       "Todd D. Morris and Edward F. Gehringer",
  title =        "A cost-effective reliable multipath interconnection
                 network",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "45--65",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Laplante:1991:ICB,
  author =       "P. A. Laplante",
  title =        "An improved conditional branching scheme for a single
                 instruction computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "66--68",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{DuBois:1991:DED,
  author =       "Andrew J. DuBois and John Rasure",
  title =        "Design and evaluation of a distributed asynchronous
                 {VLSI} crossbar switch controller for a packet switched
                 supercomputer network",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "69--79",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lass:1991:CCP,
  author =       "Stanley E. Lass",
  title =        "The compiler controlled pack cache and messaging",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "80--85",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ungerer:1991:MLP,
  author =       "Theo Ungerer and Eberhard Zehendner",
  title =        "A multi-level parallelism architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "86--93",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Matthes:1991:HMO,
  author =       "Wolfgang Matthes",
  title =        "How many operation units are adequate?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "94--108",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cunha:1991:AMM,
  author =       "Alberto R. Cunha and Carlos N. Ribeiro and Jos{\'e} A.
                 Marques",
  title =        "The architecture of a memory management unit for
                 object-oriented systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "109--116",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Matloff:1991:AAS,
  author =       "Norman Matloff",
  title =        "An argument against scalable cache coherency",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "117--123",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rodohan:1991:OAO,
  author =       "D. P. Rodohan and R. J. Glover",
  title =        "An overview of the {A} architecture for optimisation
                 problems in a logic programming environment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "124--131",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wray:1991:TSD,
  author =       "Stuart C. Wray",
  title =        "Time-sequenced {DMA} for multimedia computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "132--137",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ramamoorthy:1991:BMC,
  author =       "Ganesh Ramamoorthy and Alok N. Choudhary",
  title =        "A bibliography for multiprocessor cache memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "138--153",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:1991:SBC,
  author =       "Alan Jay Smith",
  title =        "Second bibliography on {Cache} memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "154--182",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1991:UNb,
  author =       "Mark Thorson",
  title =        "{Usenet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "4",
  pages =        "185--191",
  month =        jun,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:06 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Patterson:1991:TGS,
  author =       "David A. Patterson",
  title =        "Towards guidelines for {SIGARCH} sponsored
                 conferences",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "5",
  pages =        "7--7",
  month =        sep,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Maa:1991:TED,
  author =       "Yeong-Chang Maa and Dhiraj K. Pradhan and Dominique
                 Thi{\'e}baut",
  title =        "Two economical directory schemes for large-scale cache
                 coherent multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "5",
  pages =        "10--10",
  month =        sep,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1991:UNc,
  author =       "Mark Thorson",
  title =        "{Usenet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "5",
  pages =        "21--26",
  month =        sep,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ivanovic:1991:BRC,
  author =       "Vladimir G. Ivanovic",
  title =        "Book review: {{\em Computation Structures\/}} by
                 {Stephen A Ward and Robert H. Halstead, Jr. (MIT Press
                 or McGraw-Hill, 1990)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "5",
  pages =        "27--29",
  month =        sep,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Krieger:1991:BRM,
  author =       "Moshe Krieger",
  title =        "Book review: {{\em Multiprocessors\/}} by {D. Tabak
                 (Prentice-Hall, 1990)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "5",
  pages =        "27--29",
  month =        sep,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fulcher:1991:BRM,
  author =       "John Fulcher",
  title =        "Book review: {{\em The 68000 and 68020
                 Microprocessors: Hardware, Software and Interfacing
                 Techniques\/}} by {W. Triebel and A. Singh (Prentice
                 Hall, 1991)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "5",
  pages =        "29--30",
  month =        sep,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:26 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Baker:1991:PIS,
  author =       "Henry G. Baker",
  title =        "Precise instruction scheduling without a precise
                 machine model",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "6",
  pages =        "4--8",
  month =        dec,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McLaughlin:1991:LAB,
  author =       "Robert McLaughlin",
  title =        "Look-ahead branching hardware",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "6",
  pages =        "9--11",
  month =        dec,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Beth:1991:RCI,
  author =       "Thomas Beth and Volker Hatz",
  title =        "A restricted crossbar implementation and its
                 applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "6",
  pages =        "12--16",
  month =        dec,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1991:UNd,
  author =       "Mark Thorson",
  title =        "{Usenet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "6",
  pages =        "19--23",
  month =        dec,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bernecky:1991:BRP,
  author =       "Robert Bernecky",
  title =        "Book review: {{\em Past, Present, Parallel: A Survey
                 of Available Parallel Computing Systems\/}} by {Arthur
                 Trew \& Greg Wilson (Eds.), (Springer-Verlag 1991)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "19",
  number =       "6",
  pages =        "24--25",
  month =        dec,
  year =         "1991",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:27 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Singh:1992:SSP,
  author =       "Jaswinder Pal Singh and Wolf-Dietrich Weber and Anoop
                 Gupta",
  title =        "{SPLASH}: {Stanford} parallel applications for
                 shared-memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "1",
  pages =        "5--44",
  month =        mar,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wajda:1992:SSP,
  author =       "Eligiusz Wajda",
  title =        "{SPIRE}: streaming processing with instructions
                 release element",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "1",
  pages =        "45--54",
  month =        mar,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Deville:1992:CRP,
  author =       "Yannick Deville and Jean Gobert",
  title =        "A class of replacement policies for medium and
                 high-associativity structures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "1",
  pages =        "55--64",
  month =        mar,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zucker:1992:PSM,
  author =       "Richard N. Zucker and Jean-Loup Baer",
  title =        "A performance study of memory consistency models",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "2--12",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Keleher:1992:LRC,
  author =       "Pete Keleher and Alan L. Cox and Willy Zwaenepoel",
  title =        "Lazy release consistency for software distributed
                 shared memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "13--21",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gharachorloo:1992:HML,
  author =       "Kourosh Gharachorloo and Anoop Gupta and John
                 Hennessy",
  title =        "Hiding memory latency using dynamic scheduling in
                 shared-memory multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "22--33",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fernandes:1992:EBB,
  author =       "Edil S. T. Fernandes and Fernando M. B. Barbosa",
  title =        "Effects of building blocks on the performance of
                 super-scalar architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "36--45",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lam:1992:LCF,
  author =       "Monica S. Lam and Robert P. Wilson",
  title =        "Limits of control flow on parallelism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "46--57",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Franklin:1992:ESW,
  author =       "Manoj Franklin and Gurindar S. Sohi",
  title =        "The expandable split window paradigm for exploiting
                 fine-grain parallelism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "58--67",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Litaize:1992:TSM,
  author =       "Daniel Litaize and Abdelaziz Mzoughi and Christine
                 Rochange and Pascal Sainrat",
  title =        "Towards a shared-memory massively parallel
                 multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "70--79",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stenstrom:1992:CPE,
  author =       "Per Stenstr{\"o}m and Truman Joe and Anoop Gupta",
  title =        "Comparative performance evaluation of cache-coherent
                 {NUMA} and {COMA} architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "80--91",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lenoski:1992:DPI,
  author =       "Daniel Lenoski and James Laudon and Truman Joe and
                 David Nakahira and Luis Stevens and Anoop Gupta and
                 John Hennessy",
  title =        "The {DASH} prototype: implementation and performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "92--103",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Intrater:1992:PED,
  author =       "Gideon Intrater and Ilan Spillinger",
  title =        "Performance evaluation of a decoded instruction cache
                 for variable instruction-length computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "106--113",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chen:1992:SBS,
  author =       "J. Bradley Chen and Anita Borg and Norman P. Jouppi",
  title =        "A simulation based study of {TLB} performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "114--123",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yeh:1992:AIT,
  author =       "Tse-Yu Yeh and Yale N. Patt",
  title =        "Alternative implementations of two-level adaptive
                 branch prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "124--134",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hirata:1992:EPA,
  author =       "Hiroaki Hirata and Kozo Kimura and Satoshi Nagamine
                 and Yoshiyuki Mochizuki and Akio Nishimura and
                 Yoshimori Nakase and Teiji Nishizawa",
  title =        "An elementary processor architecture with simultaneous
                 instruction issuing from multiple threads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "136--145",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sato:1992:TBP,
  author =       "Mitsuhisa Sato and Yuetsu Kodama and Shuichi Sakai and
                 Yoshinori Yamaguchi and Yasuhito Koumura",
  title =        "Thread-based programming for the {EM-4} hybrid
                 dataflow machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "146--155",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nikhil:1992:MMP,
  author =       "R. S. Nikhil and G. M. Papadopoulos and Arvind",
  title =        "{T}: a multithreaded massively parallel architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "156--167",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dubnicki:1992:ABS,
  author =       "Czarek Dubnicki and Thomas J. LeBlanc",
  title =        "Adjustable block size coherent caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "170--180",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Olukotun:1992:POP,
  author =       "Kunle Olukotun and Trevor Mudge and Richard Brown",
  title =        "Performance optimization of pipelined primary cache",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "181--190",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McFarling:1992:CRD,
  author =       "Scott McFarling",
  title =        "Cache replacement with dynamic exclusion",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "191--200",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Keckler:1992:PCI,
  author =       "Stephem W. Keckler and William J. Dally",
  title =        "Processor coupling: integrating compile time and
                 runtime scheduling for parallelism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "202--213",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Boothe:1992:IMT,
  author =       "Bob Boothe and Abhiram Ranade",
  title =        "Improved multithreading techniques for hiding
                 communication latency in multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "214--223",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{DeGloria:1992:ILP,
  author =       "Alessandro {De Gloria} and Paolo Faraboschi",
  title =        "Instruction-level parallelism in {Prolog}: analysis
                 and architectural support",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "224--233",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kurian:1992:MLE,
  author =       "Lizyamma Kurian and Paul T. Hulina and Lee D. Coraor",
  title =        "Memory latency effects in decoupled architectures with
                 a single data memory module",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "236--245",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seznec:1992:IPS,
  author =       "Andr{\'e} Seznec and Jacques Lenfant",
  title =        "Interleaved parallel schemes: improving memory
                 throughput on supercomputers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "246--255",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{vonEicken:1992:AMM,
  author =       "Thorsten von Eicken and David E. Culler and Seth Copen
                 Goldstein and Klaus Erik Schauser",
  title =        "Active messages: a mechanism for integrated
                 communication and computation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "256--266",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chien:1992:PAR,
  author =       "Andrew A. Chien and Jae H. Kim",
  title =        "Planar-adaptive routing: low-cost adaptive networks
                 for multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "268--277",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Glass:1992:TMA,
  author =       "Christopher J. Glass and Lionel M. Ni",
  title =        "The turn model for adaptive routing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "278--287",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shimizu:1992:LLM,
  author =       "Toshiyuki Shimizu and Takeshi Horie and Hiroaki
                 Ishihata",
  title =        "Low-latency message communication support for the
                 {AP1000}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "288--297",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Aichinger:1992:FBP,
  author =       "Barbara P. Aichinger",
  title =        "{Futurebus+} as an {I/O} bus: profile {B}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "300--307",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reddy:1992:SSO,
  author =       "A. L. Narasimha Reddy",
  title =        "A study of {I/O} system organizations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "308--317",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Menon:1992:CSA,
  author =       "Jai Menon and Dick Mattson",
  title =        "Comparison of sparing alternatives for disk arrays",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "318--329",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Siegle:1992:MPB,
  author =       "Markus Siegle and Richard Hofmann",
  title =        "Monitoring program behaviour on {SUPRENUM}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "332--341",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Austin:1992:DDA,
  author =       "Todd M. Austin and Gurindar S. Sohi",
  title =        "Dynamic dependency analysis of ordinary programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "342--351",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Najjar:1992:ALL,
  author =       "Walid A. Najjar and W. Marcus Miller and A. P. Wim
                 B{\"o}hm",
  title =        "An analysis of loop latency in dataflow execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "352--360",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yang:1992:NCD,
  author =       "Qing Yang and Liping Wu Yang",
  title =        "A novel cache design for vector processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "362--371",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Valero:1992:INS,
  author =       "Mateo Valero and Tom{\'a}s Lang and Jos{\'e} M.
                 Llaber{\'\i}a and Montse Peiron and Eduard Ayguad{\'e}
                 and Juan J. Navarra",
  title =        "Increasing the number of strides for conflict-free
                 vector access",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "372--381",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wulf:1992:EWA,
  author =       "Wm. A. Wulf",
  title =        "Evaluation of the {WM} architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "382--390",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Johnson:1992:ICL,
  author =       "Kirk L. Johnson",
  title =        "The impact of communication locality on large-scale
                 multiprocessor performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "392--402",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Scott:1992:PSR,
  author =       "Steven L. Scott and James R. Goodman and Mary K.
                 Vernon",
  title =        "Performance of the {SCI} ring",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "403--414",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Talluri:1992:TST,
  author =       "Madhusudhan Talluri and Shing Kong and Mark D. Hill
                 and David A. Patterson",
  title =        "Tradeoffs in supporting two page sizes",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "415--424",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Louri:1992:PEO,
  author =       "Ahmed Louri and Jongwhoa Na",
  title =        "Parallel electro-optical rule-based system for fast
                 execution of expert systems (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "427--427",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seznec:1992:OAF,
  author =       "Andr{\'e} Seznec and Karl Courtel",
  title =        "{OPAC} (abstract): a floating-point coprocessor
                 dedicated to compute-bound kernels",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "427--427",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cheng:1992:TCB,
  author =       "Der-Chung Cheng and Kanad Ghose",
  title =        "The time-constrained barrier synchronizer and its
                 applications in parallel systems (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "428--428",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Louri:1992:NCD,
  author =       "Ahmed Louri and Hongki Sung",
  title =        "A new compiler-directed cache coherence scheme for
                 shared memory multiprocessors with fast and parallel
                 explicit invalidation (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "428--428",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Singh:1992:AGP,
  author =       "Gautam B. Singh",
  title =        "Architecture of a graphics processor (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "429--429",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yomtov:1992:PED,
  author =       "Ruben Yomtov",
  title =        "Performance evaluation of disk subsystems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "429--429",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lai:1992:EBS,
  author =       "Feipei Lai and Meng-chou Chang",
  title =        "Enhancing boosting with semantic register in a
                 superscalar processor (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "430--430",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sklenar:1992:PUVa,
  author =       "Ivan Sklenar",
  title =        "Prefetch unit for vector operations on scalar
                 computers (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "430--430",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Newman:1992:MMSa,
  author =       "Gary Newman",
  title =        "Memory management support for tiled array organization
                 (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "431--431",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Uht:1992:DPI,
  author =       "Augustus K. Uht and Darin B. Johnson",
  title =        "Data path issues in a highly concurrent machine
                 (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "431--431",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fineberg:1992:SLT,
  author =       "Samuel A. Fineberg and Thomas L. Casavant and Brent H.
                 Pease",
  title =        "Seamless --- a latency-tolerant {RISC}-based
                 multiprocessor architecture (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "432--432",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sayeed:1992:PMB,
  author =       "M. A. Sayeed and M. Atiquzzaman",
  title =        "Performance of multiple-bus multiprocessor under
                 non-uniform memory reference model (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "432--432",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kechadi:1992:PIV,
  author =       "M. Tahar Kechadi and J-L. Dekeyser and Ph. Marquet and
                 Ph. Preux",
  title =        "Performance improvement for vector pipeline
                 multiprocessor systems using a disordered execution
                 model(abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "433--433",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Varma:1992:CPS,
  author =       "Anujan Varma and Gunjan Sinha",
  title =        "A class of prefetch schemes for on-chip data caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "433--433",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Abnous:1992:PBV,
  author =       "Arthur Abnous and Nader Bagherzadeh",
  title =        "Pipelining and bypassing in a {VLIW} processor
                 (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "434--434",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Prakash:1992:SAS,
  author =       "Shiv Prakash and Alice C. Parker",
  title =        "Synthesis of application-specific heterogeneous
                 multiprocessor systems (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "434--434",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Farrens:1992:PTL,
  author =       "Matthew Farrens and Arvin Park and Rob Fanfelle and
                 Pius Ng and Gary Tyson",
  title =        "A partitioned translation lookaside buffer approach to
                 reducing address bandwidth (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "435--435",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Laudon:1992:AIT,
  author =       "James Laudon and Anoop Gupta and Mark Horowitz",
  title =        "Architectural and implementation tradeoffs in the
                 design of multiple-context processors (abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "435--435",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Alleyne:1992:EDN,
  author =       "Brian D. Alleyne and Isaac D. Scherson",
  title =        "Expanded delta networks for very large parallel
                 computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "436--436",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Singh:1992:IHB,
  author =       "Jaswinder Pal Singh",
  title =        "Implications of hierarchical {N-body} methods for
                 multiprocessor architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "436--436",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Michael:1992:DBC,
  author =       "Wisam Michael",
  title =        "Directory-based cache coherency protocol for a
                 ring-connected multiprocessor-array",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "437--437",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wang:1992:RCD,
  author =       "Wen-Hann Wang and Jim Quinlan and Konrad Lai",
  title =        "Revisit the case for direct-mapped chaches: a case for
                 two-way set-associative level-two caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "437--437",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Culler:1992:AMM,
  author =       "David E. Culler and Michial Gunter and James C. Lee",
  title =        "Analysis of multithreaded microprocessors under
                 multiprogramming",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "438--438",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wittenbrink:1992:CWG,
  author =       "C. M. Wittenbrink and A. K. Somani and C. H. Chen",
  title =        "Cache write generate for high performance parallel
                 processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "438--438",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Burkhardt:1992:ICA,
  author =       "Walter H. Burkhardt and Stefan Rust",
  title =        "Integrated computer architecture development system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "2",
  pages =        "439--439",
  month =        may,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:43 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chevance:1992:EMM,
  author =       "R. J. Chevance",
  title =        "An evaluation methodology for microprocessor and
                 system architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "3",
  pages =        "4--13",
  month =        jun,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Laird:1992:CTC,
  author =       "Michael Laird",
  title =        "A comparison of three current superscalar designs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "3",
  pages =        "14--21",
  month =        jun,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dongarra:1992:PVC,
  author =       "Jack J. Dongarra",
  title =        "Performance of various computers using standard linear
                 equations software",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "3",
  pages =        "22--44",
  month =        jun,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Keown:1992:PHR,
  author =       "William F. {Keown, Jr.} and Philip {Koopman, Jr.} and
                 Aaron Collins",
  title =        "Performance of the {HARRIS RTX 2000} stack
                 architecture versus the {Sun 4 SPARC} and the {Sun 3
                 M68020} Architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "3",
  pages =        "45--52",
  month =        jun,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1992:UNa,
  author =       "Mark Thorson",
  title =        "{Usenet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "3",
  pages =        "56--62",
  month =        jun,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chalterjee:1992:BRI,
  author =       "Siddhartha Chalterjee",
  title =        "Book review: {{\em The Impact of Vector and Parallel
                 Architectures on the Gaussian Elimination Algorithm\/}}
                 by {Yves Robert (Manchester University Press and
                 Halsted Press, 1991)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "3",
  pages =        "63--64",
  month =        jun,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Esponda:1992:GCR,
  author =       "Margarita Esponda and Ra{\'u}l Rojas",
  title =        "A graphical comparison of {RISC} processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "4",
  pages =        "2--8",
  month =        sep,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Matsui:1992:DRM,
  author =       "Shogo Matsui",
  title =        "Dynamic refresh method for dynamic {RAMs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "4",
  pages =        "9--16",
  month =        sep,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Park:1992:CRS,
  author =       "Arvin Park and Ron Maeder",
  title =        "Codes to reduce switching transients across {VLSI I/O}
                 pins",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "4",
  pages =        "17--21",
  month =        sep,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Newman:1992:MMSb,
  author =       "Gary Newman",
  title =        "Memory management support for tiled array
                 organization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "4",
  pages =        "22--30",
  month =        sep,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sklenar:1992:PUVb,
  author =       "Ivan Sklen{\'a}{\v{r}}",
  title =        "Prefetch unit for vector operations on scalar
                 computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "4",
  pages =        "31--37",
  month =        sep,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Malik:1992:ILP,
  author =       "Nadeem Malik and Richard J. Eickemeyer and Stamatis
                 Vassiliadis",
  title =        "Instruction-level parallelism from execution interlock
                 collapsing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "4",
  pages =        "38--43",
  month =        sep,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vassiliadis:1992:ASO,
  author =       "Stamatis Vassiliadis and Bart Blaner and Richard J.
                 Eickemeyer",
  title =        "On the attributes of the {SCISM} organization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "4",
  pages =        "44--53",
  month =        sep,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1992:UNb,
  author =       "Mark Thorson",
  title =        "{Usenet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "4",
  pages =        "56--64",
  month =        sep,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Allen:1992:BRC,
  author =       "Ken Allen",
  title =        "Book review: {{\em Computing with Parallel
                 Architectures: T.Node\/}}, edited by {D. Gassilloud and
                 J. C. Grossetie (Kluwer Academic Publishers 1991)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "4",
  pages =        "65--66",
  month =        sep,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Michael:1992:FMB,
  author =       "Gavin Michael and Andrew Chien",
  title =        "Future multicomputers: beyond minimalist
                 multiprocessors?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "5",
  pages =        "6--12",
  month =        dec,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kaushal:1992:CHH,
  author =       "R. P. Kaushal and J. S. Bedi",
  title =        "Comparison of hypercube, hypernet, and symmetric
                 hypernet architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "5",
  pages =        "13--25",
  month =        dec,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1992:UNc,
  author =       "Mark Thorson",
  title =        "{Usenet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "5",
  pages =        "28--33",
  month =        dec,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Levy:1992:BRN,
  author =       "David Levy",
  title =        "Book review: {{\em Neural Networks and Fuzzy Systems:
                 A Dynamical Systems Approach to Machine
                 Intelligence\/}} by {Bart Kosko (Prentice Hall 1992)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "20",
  number =       "5",
  pages =        "34--34",
  month =        dec,
  year =         "1992",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Inoue:1993:PEV,
  author =       "Atsushi Inoue and Kenji Takeda",
  title =        "Performance evaluation for various configuration of
                 superscalar processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "1",
  pages =        "4--11",
  month =        mar,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Uht:1993:EMIa,
  author =       "Augustus K. Uht",
  title =        "Extraction of massive instruction level parallelism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "1",
  pages =        "12--14",
  month =        mar,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ullah:1993:MIP,
  author =       "Nasr Ullah and Matt Holle",
  title =        "The {MC88110} implementation of precise exceptions in
                 a superscalar architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "1",
  pages =        "15--25",
  month =        mar,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Deville:1993:PDP,
  author =       "Yannick Deville",
  title =        "A process-dependent partitioning strategy for cache
                 memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "1",
  pages =        "26--33",
  month =        mar,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1993:UNa,
  author =       "Mark Thorson",
  title =        "{Usenet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "1",
  pages =        "36--38",
  month =        mar,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Staff:1993:BR,
  author =       "{ACM SIGARCH Computer Architecture News Staff}",
  title =        "Book reviews",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "1",
  pages =        "39--39",
  month =        mar,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:33 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cypher:1993:ARP,
  author =       "R. Cypher and A. Ho and S. Konstantinidou and P.
                 Messina",
  title =        "Architectural requirements of parallel scientific
                 applications with explicit communication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "2--13",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rothberg:1993:WSC,
  author =       "Edward Rothberg and Jaswinder Pal Singh and Anoop
                 Gupta",
  title =        "Working sets, cache sizes, and node granularity issues
                 for large-scale multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "14--26",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nagle:1993:DTS,
  author =       "David Nagle and Richard Uhlig and Tim Stanley and
                 Stuart Sechrest and Trevor Mudge and Richard Brown",
  title =        "Design tradeoffs for software-managed {TLBs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "27--38",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Huck:1993:AST,
  author =       "Jerry Huck and Jim Hays",
  title =        "Architectural support for translation table management
                 in large address space machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "39--50",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cao:1993:TPR,
  author =       "Pei Cao and Swee Boon Lim and Shivakumar Venkataraman
                 and John Wilkes",
  title =        "The {TickerTAIP} parallel {RAID} architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "52--63",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stodolsky:1993:PLO,
  author =       "Daniel Stodolsky and Garth Gibson and Mark Holland",
  title =        "Parity logging overcoming the small write problem in
                 redundant disk arrays",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "64--75",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Menon:1993:AFT,
  author =       "Jai Menon and Jim Cortney",
  title =        "The architecture of a fault-tolerant cached {RAID}
                 controller",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "76--87",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dubois:1993:DEU,
  author =       "Michel Dubois and Jonas Skeppstedt and Livio Ricciulli
                 and Krishnan Ramamurthy and Per Stenstr{\"o}m",
  title =        "The detection and elimination of useless misses in
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "88--97",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cox:1993:ACC,
  author =       "Alan L. Cox and Robert J. Fowler",
  title =        "Adaptive cache coherency for detecting migratory
                 shared data",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "98--108",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stenstrom:1993:ACC,
  author =       "Per Stenstr{\"o}m and Mats Brorsson and Lars
                 Sandberg",
  title =        "An adaptive cache coherence protocol optimized for
                 migratory sharing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "109--118",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Waldspurger:1993:RRF,
  author =       "Carl A. Waldspurger and William E. Weihl",
  title =        "Register relocation: flexible contexts for
                 multithreading",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "120--130",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hidaka:1993:MTC,
  author =       "Yasuo Hidaka and Hanpei Koike and Hidehiko Tanaka",
  title =        "Multiple threads in cyclic register windows",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "131--142",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dwarkadas:1993:ERC,
  author =       "Sandhya Dwarkadas and Peter Keleher and Alan L. Cox
                 and Willy Zwaenepoel",
  title =        "Evaluation of release consistent software distributed
                 shared memory on emerging network technology",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "144--155",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wood:1993:MCS,
  author =       "David A. Wood and Satish Chandra and Babak Falsafi and
                 Mark D. Hill and James R. Larus and Alvin R. Lebeck and
                 James C. Lewis and Shubhendu S. Mukherjee and Subbarao
                 Palacharla and Steven K. Reinhardt",
  title =        "Mechanisms for cooperative shared memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "156--167",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seznec:1993:CTW,
  author =       "Andr{\'e} Seznec",
  title =        "A case for two-way skewed-associative caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "169--178",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Agarwal:1993:CAC,
  author =       "Anant Agarwal and Stephen D. Pudar",
  title =        "Column-associative caches: a technique for reducing
                 the miss rate of direct-mapped caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "179--190",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jouppi:1993:CWP,
  author =       "Norman P. Jouppi",
  title =        "Cache write policies and performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "191--201",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Boyd:1993:HPM,
  author =       "Eric L. Boyd and Edward S. Davidson",
  title =        "Hierarchical performance modeling with {MACS}: a case
                 study of the {Convex C-240}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "203--210",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kuck:1993:CSI,
  author =       "D. Kuck and E. Davidson and D. Lawrie and A. Sameh and
                 C. Q. Zhu and A. Veidenbaum and J. Konicek and P. Yew
                 and K. Gallivan and W. Jalby and H. Wijshoff and R.
                 Bramley and U. M. Yang and P. Emrath and D. Padua and
                 R. Eigenmann and J. Hoeflinger and G. Jaxon and Z. Li
                 and T. Murphy and J. Andrews",
  title =        "The cedar system and an initial performance study",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "213--223",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Noakes:1993:JMM,
  author =       "Michael D. Noakes and Deborah A. Wallach and William
                 J. Dally",
  title =        "The {J-machine} multicomputer: an architectural
                 evaluation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "224--235",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bunda:1993:BVB,
  author =       "John Bunda and Don Fussell and W. C. Athas and Roy
                 Jenevein",
  title =        "16-bit vs. 32-bit instructions for pipelined
                 microprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "237--246",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kiyohara:1993:RCN,
  author =       "Tokuzo Kiyohara and Scott Mahlke and William Chen and
                 Roger Bringmann and Richard Hank and Sadun Anik and
                 Wen-Mei Hwu",
  title =        "Register connection: a new approach to adding
                 registers into instruction set architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "247--256",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yeh:1993:CDB,
  author =       "Tse-Yu Yeh and Yale N. Patt",
  title =        "A comparison of dynamic branch predictors that use two
                 levels of branch history",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "257--266",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Barroso:1993:PCC,
  author =       "Luis Andr{\'e} Barroso and Michel Dubois",
  title =        "The performance of cache-coherent ring-based
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "268--277",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tullsen:1993:LCP,
  author =       "Dean M. Tullsen and Susan J. Eggers",
  title =        "Limitations of cache prefetching on a bus-based
                 multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "278--288",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Herlihy:1993:TMA,
  author =       "Maurice Herlihy and J. Eliot B. Moss",
  title =        "Transactional memory: architectural support for
                 lock-free data structures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "289--300",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Spertus:1993:EMF,
  author =       "Ellen Spertus and Seth Copen Goldstein and Klaus Erik
                 Schauser and Thorsten von Eicken and David E. Culler
                 and William J. Dally",
  title =        "Evaluation of mechanisms for fine-grained parallel
                 programs in the {J-machine} and the {CM-5}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "302--313",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Horie:1993:IAP,
  author =       "Takeshi Horie and Kenichi Hayashi and Toshiyuki
                 Shimizu and Hiroaki Ishihata",
  title =        "Improving {AP1000} parallel computer performance with
                 message communication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "314--325",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hsu:1993:PCD,
  author =       "W.-C. Hsu and J. E. Smith",
  title =        "Performance of cached {DRAM} organizations in vector
                 supercomputers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "327--336",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gao:1993:CRT,
  author =       "Q. S. Gao",
  title =        "The {Chinese} remainder theorem and the prime memory
                 system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "337--340",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seznec:1993:OMS,
  author =       "Andr{\'e} Seznec and Jacques Lenfant",
  title =        "Odd memory systems may be quite interesting",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "341--350",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Boppana:1993:CAW,
  author =       "Rajendra V. Boppana and Suresh Chalasani",
  title =        "A comparison of adaptive wormhole routing algorithms",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "2",
  pages =        "351--360",
  month =        may,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:46 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Uht:1993:EMIb,
  author =       "Augustus K. Uht",
  title =        "Extraction of massive instruction level parallelism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "3",
  pages =        "5--12",
  month =        jun,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ramanathan:1993:SCP,
  author =       "Gowri Ramanathan and Joel Oren",
  title =        "Survey of commercial parallel machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "3",
  pages =        "13--33",
  month =        jun,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ewy:1993:SCP,
  author =       "Benjamin J. Ewy and Joseph B. Evans",
  title =        "Secondary cache performance in {RISC} architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "3",
  pages =        "34--37",
  month =        jun,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Danesh:1993:PLC,
  author =       "Iraj Danesh",
  title =        "Physical limitations of a computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "3",
  pages =        "40--45",
  month =        jun,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1993:UNb,
  author =       "Mark Thorson",
  title =        "{Usenet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "3",
  pages =        "46--49",
  month =        jun,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fostel:1993:BRP,
  author =       "Gary Fostel",
  title =        "Book Reviews: {{\em Principles of Computer Systems\/}}
                 by {Gerald M. Karam \& John C. Bryant (Prentice Hall
                 1992)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "3",
  pages =        "50--51",
  month =        jun,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fostel:1993:BRC,
  author =       "Gary Fostel",
  title =        "Book Review: {{\em Computer Architecture\/}} by {Mario
                 De Blasi (Addison-Wesley Publishing Company, 1990)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "3",
  pages =        "51--53",
  month =        jun,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fulcher:1993:BRP,
  author =       "John Fulcher",
  title =        "Book Review: {{\em Practical Parallel Computing\/}} by
                 {Paul Messina and Almerico Murli, Editors (John Wiley
                 and Sons, 1992)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "3",
  pages =        "53--54",
  month =        jun,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:56 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hill:1993:WAR,
  author =       "Mark D. Hill and James R. Larus and Alvin R. Lebeck
                 and Madhusudhan Talluri and David A. Wood",
  title =        "{Wisconsin Architectural Research Tool Set}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "4",
  pages =        "8--10",
  month =        sep,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hyatt:1993:HPO,
  author =       "Craig Hyatt",
  title =        "A high-performance object-oriented memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "4",
  pages =        "11--19",
  month =        sep,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dewan:1993:CUM,
  author =       "Gautam Dewan and V. S. S. Nair",
  title =        "A case for uniform memory access multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "4",
  pages =        "20--26",
  month =        sep,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1993:UNc,
  author =       "Mark Thorson",
  title =        "{Usenet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "4",
  pages =        "27--28",
  month =        sep,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Langdon:1993:BR,
  author =       "Glen Langdon",
  title =        "Book Reviews",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "4",
  pages =        "29--29",
  month =        sep,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jain:1993:ISI,
  author =       "Ravi Jain and John Werth and J. C. Browne",
  title =        "Introduction to the {Special Issue on Input\slash
                 Output in Parallel Computer Systems}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "5",
  pages =        "5--6",
  month =        dec,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Corbett:1993:OVP,
  author =       "Peter F. Corbett and Sandra Johnson Baylor and Dror G.
                 Feitelson",
  title =        "Overview of the {Vesta} parallel file system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "5",
  pages =        "7--14",
  month =        dec,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lin:1993:PIA,
  author =       "Z. Lin and S. Zhou",
  title =        "Parallelizing {I/O} intensive applications for a
                 workstation cluster: a case study",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "5",
  pages =        "15--22",
  month =        dec,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fineberg:1993:INA,
  author =       "Samuel A. Fineberg",
  title =        "Implementing the {NHT-1} application {I/O} benchmark",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "5",
  pages =        "23--30",
  month =        dec,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{delRosario:1993:IPT,
  author =       "Juan Miguel del Rosario and Rajesh Bordawekar and Alok
                 Choudhary",
  title =        "Improved parallel {I/O} via a two-phase run-time
                 access strategy",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "5",
  pages =        "31--38",
  month =        dec,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ghandeharizadeh:1993:OTS,
  author =       "Shahram Ghandeharizadeh and Cyrus Shahabi and Luis
                 Ramos",
  title =        "An overview of techniques to support continuous
                 retrieval of multimedia objects",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "5",
  pages =        "39--46",
  month =        dec,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jain:1993:SPO,
  author =       "Ravi Jain and Kiran Somalwar and John Werth and J. C.
                 Browne",
  title =        "Scheduling parallel {I/O} operations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "5",
  pages =        "47--54",
  month =        dec,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Li:1993:TTF,
  author =       "Qiang Li and Naphtali Rishe",
  title =        "A transputer {T9000} family based architecture for
                 parallel database machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "5",
  pages =        "55--62",
  month =        dec,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Assmann:1993:RPA,
  author =       "Claus A{\ss}mann",
  title =        "A {RISC} processor architecture with a versatile stack
                 system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "5",
  pages =        "63--70",
  month =        dec,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wang:1993:NDH,
  author =       "Dajin Wang",
  title =        "A note on {``Diagnosabilities of hypercubes under the
                 pessimistic one-step diagnosis strategy''}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "5",
  pages =        "71--78",
  month =        dec,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1993:UNd,
  author =       "Mark Thorson",
  title =        "{Usenet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "5",
  pages =        "79--85",
  month =        dec,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Alverson:1993:BRH,
  author =       "Bob Alverson",
  title =        "Book Review: {{\em High-Speed Digital Design: A
                 Handbook of Black Magic\/}} by {Howard W. Johnson and
                 Martin Graham (Prentice-Hall, 1993)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "21",
  number =       "5",
  pages =        "85--86",
  month =        dec,
  year =         "1993",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:19 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Iannucci:1994:AII,
  author =       "Robert Iannucci and Anant Agarwal and Bill Dally and
                 Anoop Gupta and Greg Papadopoulos and Burton Smith",
  title =        "Architectural and implementation issues for
                 multithreading (panel session {I})",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "1",
  pages =        "3--18",
  month =        mar,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Halstead:1994:PCR,
  author =       "Burt Halstead and David Callahan and Jack Dennis and
                 R. S. Nikhil and Vivek Sarkar",
  title =        "Programming, compilation, and resource management
                 issues for multithreading (panel session {II})",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "1",
  pages =        "19--33",
  month =        mar,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Baker:1994:LLP,
  author =       "Henry G. Baker",
  title =        "Linear logic and permutation stacks---the {Forth}
                 shall be first",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "1",
  pages =        "34--43",
  month =        mar,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mendlson:1994:CTI,
  author =       "Abraham Mendlson and Shlomit S. Pinter and Ruth
                 Shtokhamer",
  title =        "Compile time instruction cache optimizations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "1",
  pages =        "44--51",
  month =        mar,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Barach:1994:HVF,
  author =       "David Barach and Jaspal Kohli and John Slice and Marc
                 Spaulding and Rajeev Bharadhwaj and Don Hudson and
                 Cliff Neighbors and Nirmal Saxena and Rolland Crunk",
  title =        "{HALSIM}---a very fast {SPARC V9} behavioral model",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "1",
  pages =        "52--58",
  month =        mar,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1994:UNa,
  author =       "Mark Thorson",
  title =        "{Usenet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "1",
  pages =        "59--60",
  month =        mar,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Madruga:1994:BRS,
  author =       "Ewerton Longoni Madruga",
  title =        "Book Review: {{\em SNMP, SNMPv2, and CMIP: The
                 Practical Guide to Network Management Standards\/}} by
                 {William Stallings (Addison-Wesley Publishing Company
                 Inc. 1993)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "1",
  pages =        "60--61",
  month =        mar,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Calder:1994:FAI,
  author =       "B. Calder and D. Grunwald",
  title =        "Fast and accurate instruction fetch and branch
                 prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "2--11",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Talcott:1994:IUB,
  author =       "A. R. Talcott and W. Yamamoto and M. J. Serrano and R.
                 C. Wood and M. Nemirovsky",
  title =        "The impact of unresolved branches on branch prediction
                 scheme performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "12--21",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Palacharla:1994:ESB,
  author =       "S. Palacharla and R. E. Kessler",
  title =        "Evaluating stream buffers as a secondary cache
                 replacement",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "24--33",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jouppi:1994:TTL,
  author =       "N. P. Jouppi and S. J. E. Wilton",
  title =        "Tradeoffs in two-level on-chip caching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "34--45",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Singhal:1994:ASP,
  author =       "A. Singhal and A. J. Goldberg",
  title =        "Architectural support for performance tuning: a case
                 study on the {SPARCcenter 2000}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "48--59",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cvetanovic:1994:CAA,
  author =       "Z. Cvetanovic and D. Bhandarkar",
  title =        "Characterization of {Alpha AXP} performance using {TP}
                 and {SPEC} workloads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "60--70",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Natarajan:1994:MBC,
  author =       "C. Natarajan and S. Sharma and R. K. Iyer",
  title =        "Measurement-based characterization of global memory
                 and network contention, operating system and
                 parallelization overheads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "71--80",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Joe:1994:EMO,
  author =       "T. Joe and J. L. Hennessy",
  title =        "Evaluating the memory overhead required for {COMA}
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "82--93",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Klaiber:1994:CMP,
  author =       "A. C. Klaiber and H. M. Levy",
  title =        "A comparison of message passing and shared memory
                 architectures for data parallel programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "94--105",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cox:1994:SVH,
  author =       "A. L. Cox and S. Dwarkadas and P. Keleher and H. Lu
                 and R. Rajamony and W. Zwaenepoel",
  title =        "Software versus hardware shared-memory implementation:
                 a case study",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "106--117",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pnevmatikatos:1994:GEB,
  author =       "D. N. Pnevmatikatos and G. S. Sohi",
  title =        "Guarded execution and branch prediction in dynamic
                 {ILP} processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "120--129",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Su:1994:BMS,
  author =       "C.-L Su and A. M. Despain",
  title =        "Branch with masked squashing in superpipelined
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "130--140",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Blumrich:1994:VMM,
  author =       "M. A. Blumrich and K. Li and R. Alpert and C. Dubnicki
                 and E. W. Felten and J. Sandberg",
  title =        "Virtual memory mapped network interface for the
                 {SHRIMP} multicomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "142--153",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Steenkiste:1994:AEH,
  author =       "P. Steenkiste and M. Hemy and T. Mummert and B. Zill",
  title =        "Architecture and evaluation of a high-speed networking
                 subsystem for distributed-memory systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "154--163",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nayfeh:1994:EDS,
  author =       "B. A. Nayfeh and K. Olukotun",
  title =        "Exploring the design space for a shared-cache
                 multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "166--175",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thekkath:1994:ISB,
  author =       "R. Thekkath and S. J. Eggers",
  title =        "Impact of sharing-based thread placement on
                 multithreaded architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "176--186",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dahlgren:1994:CPG,
  author =       "F. Dahlgren and M. Dubois and P. Stenstr{\"o}m",
  title =        "Combined performance gains of simple cache protocol
                 extensions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "187--197",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Huang:1994:SDC,
  author =       "A. S. Huang and G. Slavenburg and J. P. Shen",
  title =        "Speculative disambiguation: a compilation technique
                 for dynamic memory disambiguation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "200--210",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Farkas:1994:CPT,
  author =       "K. I. Farkas and N. P. Jouppi",
  title =        "Complexity\slash performance tradeoffs with
                 non-blocking loads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "211--222",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chen:1994:PSS,
  author =       "T.-F. Chen and J.-L. Baer",
  title =        "A performance study of software and hardware data
                 prefetching schemes",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "223--232",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Drapeau:1994:RIH,
  author =       "A. L. Drapeau and K. W. Shirriff and J. H. Hartman and
                 E. L. Miller and S. Seshan and R. H. Katz and K. Lutz
                 and D. A. Patterson and E. K. Lee and P. M. Chen and G.
                 A. Gibson",
  title =        "{RAID-II}: a high-bandwidth network file server",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "234--244",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Blaum:1994:EOS,
  author =       "M. Blaum and J. Brady and J. Bruck and J. Menon",
  title =        "{EVENODD}: an optimal scheme for tolerating double
                 disk failures in {RAID} architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "245--254",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ng:1994:CDA,
  author =       "S. W. Ng",
  title =        "Crosshatch disk array for improved reliability and
                 performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "255--264",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{DeHon:1994:MRA,
  author =       "A. DeHon and F. Chong and M. Becker and E. Egozy and
                 H. Minsky and S. Peretz and T. F. {Knight, Jr.}",
  title =        "{METRO}: a router architecture for high-performance,
                 short-haul routing networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "266--277",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Allen:1994:AAR,
  author =       "J. D. Allen and P. T. Gaughan and D. E. Schimmel and
                 S. Yalamanchili",
  title =        "{Ariadne}---an adaptive router for fault-tolerant
                 multicomputers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "278--288",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kim:1994:CRF,
  author =       "J. H. Kim and Z. Liu and A. A. Chien",
  title =        "Compressionless routing: a framework for adaptive and
                 fault-tolerant routing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "289--300",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kuskin:1994:SFM,
  author =       "J. Kuskin and D. Ofelt and M. Heinrich and J. Heinlein
                 and R. Simoni and K. Gharachorloo and J. Chapin and D.
                 Nakahira and J. Baxter and M. Horowitz and A. Gupta and
                 M. Rosenblum and J. Hennessy",
  title =        "The {Stanford FLASH} multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "302--313",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chaiken:1994:SEC,
  author =       "D. Chaiken and A. Agarwal",
  title =        "Software-extended coherent shared memory: performance
                 and cost",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "314--324",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reinhardt:1994:TTU,
  author =       "S. K. Reinhardt and J. R. Larus and D. A. Wood",
  title =        "{Tempest} and {Typhoon}: user-level shared memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "325--336",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Farrens:1994:SSC,
  author =       "M. Farrens and G. Tyson and A. R. Pleszkun",
  title =        "A study of single-chip processor\slash cache
                 organizations for large numbers of transistors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "338--347",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chen:1994:UAT,
  author =       "C.-H. Chen and A. K. Somani",
  title =        "A unified architectural tradeoff methodology",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "348--357",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nagle:1994:OAC,
  author =       "D. Nagle and R. Uhlig and T. Mudge and S. Sechrest",
  title =        "Optimal allocation of on-chip memory for
                 multiple-{API} operating systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "358--369",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Quong:1994:ECM,
  author =       "R. W. Quong",
  title =        "Expected {I-cache} miss rates via the gap model",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "372--383",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seznec:1994:DSC,
  author =       "A. Seznec",
  title =        "Decoupled sectored caches: conciliating low tag
                 implementation cost",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "2",
  pages =        "384--393",
  month =        apr,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:40 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gurd:1994:SBB,
  author =       "J. R. Gurd",
  title =        "Supercomputing: big bang or steady state growth?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "3",
  pages =        "3--13",
  month =        jun,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Litchfield:1994:IES,
  author =       "Kay P. Litchfield",
  title =        "Instruction execution sequence confirmation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "3",
  pages =        "14--18",
  month =        jun,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Allen:1994:RWR,
  author =       "Phil Allen and Franc Brglez and Hal Carter and Robert
                 Caverly and Jerry Dillion and Albert Lo and Ron Lomax
                 and John Oldfield and Cesar Pina and T. J. Wilkinson",
  title =        "Report of the {1993 Workshop on Rapid Prototyping of
                 Microelectronic Systems for Universities}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "3",
  pages =        "19--26",
  month =        jun,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1994:UNb,
  author =       "Mark Thorson",
  title =        "{Usenet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "3",
  pages =        "27--28",
  month =        jun,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Madruga:1994:BRI,
  author =       "Ewerton Longoni Madruga",
  title =        "Book Review: {{\em Internetworking with TCP/IP, vol.
                 III: Client-Server programming and applications (BSD
                 Sockets version)\/}} by {Douglas E. Comer and David L.
                 Stevens (Prentice-Hall, 1993)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "3",
  pages =        "29--30",
  month =        jun,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jain:1994:SII,
  author =       "Ravi Jain and John Werth and J. C. Browne",
  title =        "{Special Issue on Input\slash Output in Parallel
                 Computer Systems}: {Introduction}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "4",
  pages =        "3--4",
  month =        sep,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Baylor:1994:PEM,
  author =       "Sandra Johnson Baylor and Caroline Benveniste and
                 Yarsun Hsu",
  title =        "Performance evaluation of a massively parallel {I/O}
                 subsystem",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "4",
  pages =        "5--10",
  month =        sep,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sinclair:1994:IPS,
  author =       "James B. Sinclair and Jay Tang and Peter J. Varman",
  title =        "Instability in parallel {I/O} systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "4",
  pages =        "11--16",
  month =        sep,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vanderleest:1994:MBC,
  author =       "Steven H. Vanderleest and Ravishankar K. Iyer",
  title =        "Measurement of {I/O} bus contention and correlation
                 among heterogeneous device types in a single-bus
                 multiprocessor system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "4",
  pages =        "17--22",
  month =        sep,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thakur:1994:CCD,
  author =       "Rajeev Thakur and Rajesh Bordawekar and Alok
                 Choudhary",
  title =        "Compilation of out-of-core data parallel programs for
                 distributed memory machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "4",
  pages =        "23--28",
  month =        sep,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Asthana:1994:EAM,
  author =       "Abhaya Asthana and Mark Cravatts and Paul
                 Krzyzanowski",
  title =        "An experimental active memory based {I/O} subsystem",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "4",
  pages =        "29--34",
  month =        sep,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Durand:1994:DSA,
  author =       "Dannie Durand and Ravi Jain and David Tseytlin",
  title =        "Distributed scheduling algorithms to improve the
                 performance of parallel data transfers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "4",
  pages =        "35--40",
  month =        sep,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yokota:1994:DND,
  author =       "Haruo Yokota",
  title =        "{DR-nets}: data-reconstruction networks for highly
                 reliable parallel-disk systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "4",
  pages =        "41--46",
  month =        sep,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Forsell:1994:MMPa,
  author =       "Martti J. Forsell",
  title =        "Are multiport memories physically feasible?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "4",
  pages =        "47--54",
  month =        sep,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chaudhry:1994:CMP,
  author =       "Ghulam Chaudhry and Xuechang Li",
  title =        "A case for the multithreaded processor architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "4",
  pages =        "55--59",
  month =        sep,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chan:1994:ECF,
  author =       "Yin Chan and Ashok Sudarsanam and Andrew Wolfe",
  title =        "The effect of compiler-flag tuning on {SPEC} benchmark
                 performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "4",
  pages =        "60--70",
  month =        sep,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1994:RCC,
  author =       "Jin-Ho Lee and Min-Young Lee and Seong-Uk Choi and
                 Myong-Soon Park",
  title =        "Reducing cache conflicts in data cache prefetching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "4",
  pages =        "71--77",
  month =        sep,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1994:UNc,
  author =       "Mark Thorson",
  title =        "{Usenet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "4",
  pages =        "78--81",
  month =        sep,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:12 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Forsell:1994:MMPb,
  author =       "Martti J. Forsell",
  title =        "Are multiport memories physically feasible?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "5",
  pages =        "3--10",
  month =        dec,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sosic:1994:HCH,
  author =       "Rok Sosi{\v{c}}",
  title =        "History cache: hardware support for reverse
                 execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "5",
  pages =        "11--18",
  month =        dec,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hill:1994:WWT,
  author =       "Mark D. Hill and James R. Larus and David A. Wood",
  title =        "The {Wisconsin Wind Tunnel} project: an annotated
                 bibliography",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "5",
  pages =        "19--26",
  month =        dec,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Saha:1994:DDT,
  author =       "Avijit Saha and Nadeem Malik",
  title =        "Distributed directory tags",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "5",
  pages =        "27--29",
  month =        dec,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Unwala:1994:SMP,
  author =       "Ishaq H. Unwala and Harvey G. Cragon",
  title =        "A study of {MIPS} programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "5",
  pages =        "30--40",
  month =        dec,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1994:IN,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "5",
  pages =        "41--46",
  month =        dec,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ohnemus:1994:BIL,
  author =       "Kenneth R. Ohnemus and Diana F. Mallin",
  title =        "Benefits of implementing on-line methods and
                 procedures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "5",
  pages =        "49--55",
  month =        dec,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cunningham:1994:LDT,
  author =       "Daniel K. Cunningham and Steven J. Reilly",
  title =        "Leading the design team---the evolution of the
                 technical writer from a support role to a design role",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "5",
  pages =        "56--60",
  month =        dec,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rockley:1994:MTE,
  author =       "Ann Rockley",
  title =        "Multimedia: towards an electronic performance support
                 system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "5",
  pages =        "61--65",
  month =        dec,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Drew:1994:TTM,
  author =       "Katherine E. Drew",
  title =        "Telecommunicators and telecommuters: making
                 multiple-site documentation projects work",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "22",
  number =       "5",
  pages =        "66--75",
  month =        dec,
  year =         "1994",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Severson:1995:TCP,
  author =       "Aimee Severson and Brent Nelson",
  title =        "Throughput in a counterflow pipeline processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "1",
  pages =        "5--12",
  month =        mar,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hsu:1995:SAC,
  author =       "Tsong-Chih Hsu and Sheng-De Wang",
  title =        "A simple architecture for constant time sorting
                 machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "1",
  pages =        "13--19",
  month =        mar,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wulf:1995:HMW,
  author =       "Wm. A. Wulf and Sally A. McKee",
  title =        "Hitting the memory wall: implications of the obvious",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "1",
  pages =        "20--24",
  month =        mar,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1995:INa,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "1",
  pages =        "25--28",
  month =        mar,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Agarwal:1995:AMA,
  author =       "Anant Agarwal and Ricardo Bianchini and David Chaiken
                 and Kirk L. Johnson and David Kranz and John
                 Kubiatowicz and Beng-Hong Lim and Kenneth Mackenzie and
                 Donald Yeung",
  title =        "The {MIT Alewife} machine: architecture and
                 performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "2--13",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kodama:1995:EXP,
  author =       "Yuetsu Kodama and Hirohumi Sakane and Mitsuhisa Sato
                 and Hayato Yamana and Shuichi Sakai and Yoshinori
                 Yamaguchi",
  title =        "The {EM-X} parallel computer: architecture and basic
                 performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "14--23",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Woo:1995:SPC,
  author =       "Steven Cameron Woo and Moriyoshi Ohara and Evan Torrie
                 and Jaswinder Pal Singh and Anoop Gupta",
  title =        "The {SPLASH-2} programs: characterization and
                 methodological considerations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "24--36",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Grahn:1995:ESS,
  author =       "H{\aa}kan Grahn and Per Stenstr{\"o}m",
  title =        "Efficient strategies for software-only protocols in
                 shared-memory multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "38--47",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lebeck:1995:DSI,
  author =       "Alvin R. Lebeck and David A. Wood",
  title =        "Dynamic self-invalidation: reducing coherence overhead
                 in shared-memory multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "48--59",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dahlgren:1995:BPH,
  author =       "Fredrik Dahlgren",
  title =        "Boosting the performance of hybrid snooping cache
                 protocols",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "60--69",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nowatzyk:1995:CNW,
  author =       "Andreas G. Nowatzyk and Michael C. Browne and Edmund
                 J. Kelly and Michael Parkin",
  title =        "{S}-connect: from networks of workstations to
                 supercomputer performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "71--82",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Varma:1995:DAD,
  author =       "Anujan Varma and Quinn Jacobson",
  title =        "Destage algorithms for disk arrays with non-volatile
                 caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "83--95",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stoll:1995:EMP,
  author =       "Gordon Stoll and Bin Wei and Douglas Clark and Edward
                 W. Felten and Kai Li and Patrick Hanrahan",
  title =        "Evaluating multi-port frame buffer designs for a
                 mesh-connected multicomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "96--105",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nowatzyk:1995:CRD,
  author =       "Andreas G. Nowatzyk and Paul R. Prucnal",
  title =        "Are crossbars really dead?: the case for optical
                 multiprocessor interconnect systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "106--115",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jourdan:1995:ECF,
  author =       "St{\'e}phan Jourdan and Pascal Sainrat and Daniel
                 Litaize",
  title =        "Exploring configurations of functional units in an
                 out-of-order superscalar processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "117--125",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ando:1995:USE,
  author =       "Hideki Ando and Chikako Nakanishi and Tetsuya Hara and
                 Masao Nakaya",
  title =        "Unconstrained speculative execution with predicated
                 state buffering",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "126--137",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mahlke:1995:CFP,
  author =       "Scott A. Mahlke and Richard E. Hank and James E.
                 McCormick and David I. August and Wen-Mei W. Hwu",
  title =        "A comparison of full and partial predicated execution
                 support for {ILP} processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "138--150",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Simone:1995:ITO,
  author =       "M. Simone and A. Essen and A. Ike and A.
                 Krishnamoorthy and T. Maruyama and N. Patkar and M.
                 Ramaswami and M. Shebanow and V. Thirumalaiswamy and D.
                 Tovey",
  title =        "Implementation trade-offs in using a restricted data
                 flow architecture in a high performance {RISC}
                 microprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "151--162",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Diep:1995:PEP,
  author =       "Trung A. Diep and Christopher Nelson and John Paul
                 Shen",
  title =        "Performance evaluation of the {PowerPC 620}
                 microarchitecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "163--174",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Romer:1995:RTM,
  author =       "Theodore H. Romer and Wayne H. Ohlrich and Anna R.
                 Karlin and Brian N. Bershad",
  title =        "Reducing {TLB} and memory overhead using online
                 superpage promotion",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "176--187",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhang:1995:SIA,
  author =       "Zheng Zhang and Josep Torrellas",
  title =        "Speeding up irregular applications in shared-memory
                 multiprocessors: memory binding and group prefetching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "188--199",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anjan:1995:EFA,
  author =       "K. V. Anjan and Timothy Mark Pinkston",
  title =        "An efficient, fully adaptive deadlock recovery scheme:
                 {DISHA}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "201--210",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shin:1995:AIH,
  author =       "Kang G. Shin and Stuart W. Daniel",
  title =        "Analysis and implementation of hybrid switching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "211--219",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dao:1995:CFC,
  author =       "Binh Vien Dao and Jose Duato and Sudhakar
                 Yalamanchili",
  title =        "Configurable flow control mechanisms for
                 fault-tolerant routing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "220--229",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Callahan:1995:NLO,
  author =       "Timothy Callahan and Seth Copen Goldstein",
  title =        "{NIFDY}: a low overhead, high throughput network
                 interface",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "230--241",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Peiron:1995:VMA,
  author =       "Montse Peiron and Mateo Valero and Eduard Ayguad{\'e}
                 and Tom{\'a}s Lang",
  title =        "Vector multiprocessors with arbitrated memory access",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "243--252",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kavi:1995:DCM,
  author =       "Krishna M. Kavi and A. R. Hurson and Phenil Patadia
                 and Elizabeth Abraham and Ponnarasu Shanmugam",
  title =        "Design of cache memories for multi-threaded dataflow
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "253--264",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bodin:1995:SAE,
  author =       "Fran{\c{c}}ois Bodin and Andr{\'e} Seznec",
  title =        "Skewed associativity enhances performance
                 predictability",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "265--274",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Young:1995:CAS,
  author =       "Cliff Young and Nicolas Gloy and Michael D. Smith",
  title =        "A comparative analysis of schemes for correlated
                 branch prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "276--286",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Calder:1995:NCL,
  author =       "Brad Calder and Dirk Grunwald",
  title =        "Next cache line and set prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "287--296",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Karamcheti:1995:CAS,
  author =       "Vijay Karamcheti and Andrew A. Chien",
  title =        "A comparison of architectural support for messaging in
                 the {TMC CM-5} and the {Cray T3D}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "298--307",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stricker:1995:OMS,
  author =       "T. Stricker and T. Gross",
  title =        "Optimizing memory system performance for communication
                 in parallel computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "308--319",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Arpaci:1995:EEC,
  author =       "Remzi H. Arpaci and David E. Culler and Arvind
                 Krishnamurthy and Steve G. Steinberg and Katherine
                 Yelick",
  title =        "Empirical evaluation of the {CRAY-T$3$D}: a compiler
                 perspective",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "320--331",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Conte:1995:OIF,
  author =       "Thomas M. Conte and Kishore N. Menezes and Patrick M.
                 Mills and Burzin A. Patel",
  title =        "Optimization of instruction fetch mechanisms for high
                 issue rates",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "333--344",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Uhlig:1995:IFC,
  author =       "Richard Uhlig and David Nagle and Trevor Mudge and
                 Stuart Sechrest and Joel Emer",
  title =        "Instruction fetching: coping with code bloat",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "345--356",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1995:ICF,
  author =       "Dennis Lee and Jean-Loup Baer and Brad Calder and Dirk
                 Grunwald",
  title =        "Instruction cache fetch policies for speculative
                 execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "357--367",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Austin:1995:SDC,
  author =       "Todd M. Austin and Dionisios N. Pnevmatikatos and
                 Gurindar S. Sohi",
  title =        "Streamlining data cache access with fast address
                 calculation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "369--380",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wang:1995:CCA,
  author =       "Hong Wang and Tong Sun and Qing Yang",
  title =        "{CAT}---caching address tags: a technique for reducing
                 area cost of on-chip caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "381--390",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tullsen:1995:SMM,
  author =       "Dean M. Tullsen and Susan J. Eggers and Henry M.
                 Levy",
  title =        "Simultaneous multithreading: maximizing on-chip
                 parallelism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "392--403",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ho:1995:AVP,
  author =       "Richard C. Ho and C. Han Yang and Mark A. Horowitz and
                 David L. Dill",
  title =        "Architecture validation for processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "404--413",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sohi:1995:MP,
  author =       "Gurindar S. Sohi and Scott E. Breach and T. N.
                 Vijaykumar",
  title =        "Multiscalar processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "2",
  pages =        "414--425",
  month =        may,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Beckmann:1995:HPM,
  author =       "Carl J. Beckmann",
  title =        "{HTGL}: a program modelling language",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "3",
  pages =        "3--10",
  month =        jun,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lafitte:1995:SDH,
  author =       "Jean-Louis Lafitte",
  title =        "On structured data handling in parallel processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "3",
  pages =        "11--18",
  month =        jun,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ulmann:1995:ESB,
  author =       "B. Ulmann",
  title =        "{o$ \mu $-EP-1}: a simple 32-bit architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "3",
  pages =        "19--24",
  month =        jun,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1995:INb,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "3",
  pages =        "25--27",
  month =        jun,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tabak:1995:CMH,
  author =       "Daniel Tabak",
  title =        "{{\em Cache and Memory Hierarchy Design: A
                 Performance-Directed Approach\/}} by {Steven A.
                 Przybylski}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "3",
  pages =        "28--28",
  month =        jun,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:57 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wilkes:1995:MWC,
  author =       "Maurice V. Wilkes",
  title =        "The memory wall and the {CMOS} end-point",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "4",
  pages =        "4--6",
  month =        sep,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Johnson:1995:GMW,
  author =       "Eric E. Johnson",
  title =        "Graffiti on ``the memory wall''",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "4",
  pages =        "7--8",
  month =        sep,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Afzal:1995:PMU,
  author =       "Tariq Afzal",
  title =        "Performance modeling using the {Motorola PowerPC}
                 timing simulator",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "4",
  pages =        "9--18",
  month =        sep,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Parhami:1995:SMD,
  author =       "Behrooz Parhami",
  title =        "{SIMD} machines: do they have a significant future?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "4",
  pages =        "19--22",
  month =        sep,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jain:1995:AAE,
  author =       "Ravi Jain and John Werth",
  title =        "Airdisks and {airRAID} (expanded extract): modeling
                 and scheduling periodic wireless data broadcast",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "4",
  pages =        "23--28",
  month =        sep,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kontothanassis:1995:ESM,
  author =       "Leonidas I. Kontothanassis and Michael L. Scott",
  title =        "Efficient shared memory with minimal hardware
                 support",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "4",
  pages =        "29--35",
  month =        sep,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gschwind:1995:VP,
  author =       "Michael K. Gschwind and Thomas J. Pietsch",
  title =        "Vector prefetching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "5",
  pages =        "1--7",
  month =        dec,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Karne:1995:OOC,
  author =       "Ramesh K. Karne",
  title =        "Object-oriented computer architectures for new
                 generation of applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "5",
  pages =        "8--19",
  month =        dec,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Khalid:1995:URA,
  author =       "Humayun Khalid",
  title =        "The unconventional replacement algorithms",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "5",
  pages =        "20--26",
  month =        dec,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Khalid:1995:TDS,
  author =       "Humayun Khalid",
  title =        "A trace-driven simulation methodology",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "5",
  pages =        "27--33",
  month =        dec,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mirghafori:1995:TSB,
  author =       "Nikki Mirghafori and Margret Jacoby and David
                 Patterson",
  title =        "Truth in {SPEC} benchmarks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "5",
  pages =        "34--42",
  month =        dec,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1995:INc,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "23",
  number =       "5",
  pages =        "43--44",
  month =        dec,
  year =         "1995",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mudge:1996:RPH,
  author =       "Trevor Mudge",
  title =        "Report on the panel: {``How Can Computer Architecture
                 Researchers Avoid Becoming the Society for
                 Irreproducible Results?''}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "1",
  pages =        "1--5",
  month =        mar,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kwon:1996:COR,
  author =       "Oh-Young Kwon and Gi-Ho Park and Tack-Don Han",
  title =        "A compiler optimization to reduce execution time of
                 loop nest",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "1",
  pages =        "6--11",
  month =        mar,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1996:INa,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "1",
  pages =        "12--16",
  month =        mar,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tabak:1996:BRA,
  author =       "Daniel Tabak",
  title =        "Book Review: {{\em Alpha Implementations and
                 Architecture\/}} by {Dileep P. Bhandarkar}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "1",
  pages =        "17--18",
  month =        mar,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:34 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Evers:1996:UHB,
  author =       "Marius Evers and Po-Yung Chang and Yale N. Patt",
  title =        "Using hybrid branch predictors to improve branch
                 prediction accuracy in the presence of context
                 switches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "3--11",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gloy:1996:ADB,
  author =       "Nicolas Gloy and Cliff Young and J. Bradley Chen and
                 Michael D. Smith",
  title =        "An analysis of dynamic branch prediction schemes on
                 system workloads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "12--21",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sechrest:1996:CAD,
  author =       "Stuart Sechrest and Chih-Chieh Lee and Trevor Mudge",
  title =        "Correlation and aliasing in dynamic branch
                 predictors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "22--32",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reinhardt:1996:DHS,
  author =       "Steven K. Reinhardt and Robert W. Pfile and David A.
                 Wood",
  title =        "Decoupled hardware support for distributed shared
                 memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "34--43",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yeung:1996:MMS,
  author =       "Donald Yeung and John Kubiatowicz and Anant Agarwal",
  title =        "{MGS}: a multigrain shared memory system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "44--55",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Morin:1996:COB,
  author =       "Christine Morin and Alain Gefflaut and Michel
                 Ban{\^a}tre and Anne-Marie Kermarrec",
  title =        "{COMA}: an opportunity for building fault-tolerant
                 scalable shared memory multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "56--65",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nayfeh:1996:EDA,
  author =       "Basem A. Nayfeh and Lance Hammond and Kunle Olukotun",
  title =        "Evaluation of design alternatives for a multiprocessor
                 microprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "67--77",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Burger:1996:MBL,
  author =       "Doug Burger and James R. Goodman and Alain K{\"a}gi",
  title =        "Memory bandwidth limitations of future
                 microprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "78--89",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Saulsbury:1996:MMW,
  author =       "Ashley Saulsbury and Fong Pong and Andreas Nowatzyk",
  title =        "Missing the memory wall: the case for processor\slash
                 memory integration",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "90--101",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seznec:1996:DUP,
  author =       "Andr{\'e} Seznec",
  title =        "Don't use the page number, but a pointer to it",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "104--113",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Juan:1996:DBC,
  author =       "Toni Juan and Tom{\'a}s Lang and Juan J. Navarro",
  title =        "The difference-bit cache",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "114--120",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Iftode:1996:UAP,
  author =       "Liviu Iftode and Jaswinder Pal Singh and Kai Li",
  title =        "Understanding application performance on shared
                 virtual memory systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "122--133",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Holt:1996:AAB,
  author =       "Chris Holt and Jaswinder Pal Singh and John Hennessy",
  title =        "Application and architectural bottlenecks in large
                 scale distributed shared memory machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "134--145",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wilson:1996:ICP,
  author =       "Kenneth M. Wilson and Kunle Olukotun and Mendel
                 Rosenblum",
  title =        "Increasing cache port efficiency for dynamic
                 superscalar microprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "147--157",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Austin:1996:HBA,
  author =       "Todd M. Austin and Gurindar S. Sohi",
  title =        "High-bandwidth address translation for multiple-issue
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "158--167",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hu:1996:DDC,
  author =       "Yiming Hu and Qing Yang",
  title =        "{DCD}---disk caching disk: a new approach for boosting
                 {I/O} performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "169--178",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Maquelin:1996:PWC,
  author =       "Olivier Maquelin and Guang R. Gao and Herbert H. J.
                 Hum and Kevin B. Theobald and Xin-Min Tian",
  title =        "Polling watchdog: combining polling and interrupts for
                 efficient message handling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "179--188",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tullsen:1996:ECI,
  author =       "Dean M. Tullsen and Susan J. Eggers and Joel S. Emer
                 and Henry M. Levy and Jack L. Lo and Rebecca L. Stamm",
  title =        "Exploiting choice: instruction fetch and issue on an
                 implementable simultaneous multithreading processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "191--202",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Eickemeyer:1996:EMU,
  author =       "Richard J. Eickemeyer and Ross E. Johnson and Steven
                 R. Kunkel and Mark S. Squillante and Shiafun Liu",
  title =        "Evaluation of multithreaded uniprocessors for
                 commercial application environments",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "203--212",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hara:1996:PCI,
  author =       "Tetsuya Hara and Hideki Ando and Chikako Nakanishi and
                 Masao Nakaya",
  title =        "Performance comparison of {ILP} machines with cycle
                 time evaluation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "213--224",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kim:1996:RCQ,
  author =       "Jae H. Kim and Andrew A. Chien",
  title =        "Rotating combined queueing {(RCQ)}: bandwidth and
                 latency guarantees in low-cost, high-performance
                 networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "226--236",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rexford:1996:RAR,
  author =       "Jennifer Rexford and John Hall and Kang G. Shin",
  title =        "A router architecture for real-time point-to-point
                 networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "237--246",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mukherjee:1996:CNI,
  author =       "Shubhendu S. Mukherjee and Babak Falsafi and Mark D.
                 Hill and David A. Wood",
  title =        "Coherent network interfaces for fine-grain
                 communication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "247--258",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Horowitz:1996:IMO,
  author =       "Mark Horowitz and Margaret Martonosi and Todd C. Mowry
                 and Michael D. Smith",
  title =        "Informing memory operations: providing memory
                 performance feedback in modern processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "260--270",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Xia:1996:IPS,
  author =       "Chun Xia and Josep Torrellas",
  title =        "Instruction prefetching of systems codes with layout
                 optimized for reduced cache misses",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "271--282",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Choi:1996:CHS,
  author =       "Lynn Choi and Pen-Chung Yew",
  title =        "Compiler and hardware support for cache coherence in
                 large-scale multiprocessors: design considerations and
                 performance study",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "283--294",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Felten:1996:EEM,
  author =       "Edward W. Felten and Richard D. Alpert and Angelos
                 Bilas and Matthias A. Blumrich and Douglas W. Clark and
                 Stefanos N. Damianakis and Cezary Dubnicki and Liviu
                 Iftode and Kai Li",
  title =        "Early experience with message-passing on the {SHRIMP}
                 multicomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "296--307",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lovett:1996:SCN,
  author =       "Tom Lovett and Russell Clapp",
  title =        "{STiNG}: a {CC-NUMA} computer system for the
                 commercial marketplace",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "2",
  pages =        "308--317",
  month =        may,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:47 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Carretero:1996:MPD,
  author =       "J. Carretero and F. P{\'e}rez and P. de Miguel and F.
                 Garc{\'\i}a and L. Alonso",
  title =        "A massively parallel and distributed {I/O} subsystem",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "3",
  pages =        "1--8",
  month =        jun,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ligon:1996:DLB,
  author =       "W. B. {Ligon III} and Daniel C. {Stanzione, Jr.}",
  title =        "Distributing and load-balancing for loops in
                 scientific applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "3",
  pages =        "9--17",
  month =        jun,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Belayneh:1996:DNBa,
  author =       "Samson Belayneh and David R. Kaeli",
  title =        "A discussion on non-blocking\slash lockup-free
                 caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "3",
  pages =        "18--25",
  month =        jun,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1996:INb,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "3",
  pages =        "26--32",
  month =        jun,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Paez-Monzon:1996:RPD,
  author =       "Gerard P{\'a}ez-Monz{\'o}n and Charles
                 P{\'a}ez-Monz{\'o}n",
  title =        "The {RISC} processor {DMN-6}: a unified data-control
                 flow architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "4",
  pages =        "3--10",
  month =        sep,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pulido:1996:ETT,
  author =       "J. A. G{\'o}mez Pulido and J. M. S{\'a}nchez P{\'e}rez
                 and J. A. Moreno Zamora",
  title =        "An educational tool for testing hierarchical
                 multilevel caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "4",
  pages =        "11--15",
  month =        sep,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Belayneh:1996:DNBb,
  author =       "Samson Belayneh and David R. Kaeli",
  title =        "A discussion on non-blocking\slash lockup-free
                 caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "4",
  pages =        "16--16",
  month =        sep,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rosenbaum:1996:AP,
  author =       "Mark Rosenbaum",
  title =        "Architectural potholes",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "4",
  pages =        "17--18",
  month =        sep,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mashey:1996:AP,
  author =       "John Mashey",
  title =        "Architectural potholes",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "4",
  pages =        "18--18",
  month =        sep,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cockcroft:1996:P,
  author =       "Adrian Cockcroft",
  title =        "{I/O} potholes",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "4",
  pages =        "18--19",
  month =        sep,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ebrahim:1996:P,
  author =       "Zahir Ebrahim",
  title =        "{I/O} potholes",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "4",
  pages =        "19--20",
  month =        sep,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Carlile:1996:IB,
  author =       "Brad Carlile",
  title =        "Interpreting benchmarks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "4",
  pages =        "20--21",
  month =        sep,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chase:1996:RW,
  author =       "David Chase",
  title =        "Register windows",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "4",
  pages =        "21--21",
  month =        sep,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{DeMone:1996:RWD,
  author =       "Paul W. DeMone",
  title =        "Register windows and delay slots",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "4",
  pages =        "21--22",
  month =        sep,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:13 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rose:1996:CIT,
  author =       "Charlton D. Rose and J. Kelly Flanagan",
  title =        "Constructing instruction traces from cache-filtered
                 address traces {(CITCAT)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "5",
  pages =        "1--8",
  month =        dec,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hummel:1996:EDS,
  author =       "Susan Flynn Hummel",
  title =        "Efficient data sharing with conditional remote memory
                 transfers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "5",
  pages =        "9--17",
  month =        dec,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Widigen:1996:EOR,
  author =       "Larry Widigen and Elliot Sowadsky and Kevin McGrath",
  title =        "Eliminating operand read latency",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "5",
  pages =        "18--22",
  month =        dec,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Machanick:1996:CSM,
  author =       "Philip Machanick",
  title =        "The case for {SRAM} main memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "24",
  number =       "5",
  pages =        "23--30",
  month =        dec,
  year =         "1996",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:20 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bhandarkar:1997:RVC,
  author =       "Dileep Bhandarkar",
  title =        "{RISC} versus {CISC}: a tale of two chips",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "1",
  pages =        "1--12",
  month =        mar,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Martin:1997:SCM,
  author =       "I. Mart{\'\i}n and F. Tirado",
  title =        "A {SIMD} computer for multigrid methods",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "1",
  pages =        "13--18",
  month =        mar,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Weicker:1997:USB,
  author =       "Reinhold Weicker",
  title =        "On the use of {SPEC} benchmarks in computer
                 architecture research",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "1",
  pages =        "19--22",
  month =        mar,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mukherjee:1997:WSG,
  author =       "Shubhendu S. Mukherjee",
  title =        "What should graduate students know before joining a
                 large computer architecture project?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "1",
  pages =        "23--26",
  month =        mar,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Khalid:1997:NCR,
  author =       "Humayun Khalid",
  title =        "A new cache replacement scheme based on
                 backpropagation neural networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "1",
  pages =        "27--33",
  month =        mar,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1997:INa,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "1",
  pages =        "34--36",
  month =        mar,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vajapeyam:1997:ISI,
  author =       "Sriram Vajapeyam and Tulika Mitra",
  title =        "Improving superscalar instruction dispatch and issue
                 by exploiting dynamic code sequences",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "1--12",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nair:1997:EIL,
  author =       "Ravi Nair and Martin E. Hopkins",
  title =        "Exploiting instruction level parallelism in processors
                 by caching scheduled groups",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "13--25",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ebcioglu:1997:DDC,
  author =       "Kemal Ebcio{\u{g}}lu and Erik R. Altman",
  title =        "{DAISY}: dynamic compilation for 100\% architectural
                 compatibility",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "26--37",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pinkston:1997:DIN,
  author =       "Timothy Mark Pinkston and Sugath Warnakulasuriya",
  title =        "On deadlocks in interconnection networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "38--49",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Stunkel:1997:IMW,
  author =       "Craig B. Stunkel and Rajeev Sivaram and Dhabaleswar K.
                 Panda",
  title =        "Implementing multidestination worms in switch-based
                 parallel systems: architectural alternatives and their
                 impact",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "50--61",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Alvarez:1997:TMF,
  author =       "Guillermo A. Alvarez and Walter A. Burkhard and Flaviu
                 Cristian",
  title =        "Tolerating multiple failures in {RAID} architectures
                 with optimal storage and uniform declustering",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "62--72",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Teodosiu:1997:HFC,
  author =       "Dan Teodosiu and Joel Baxter and Kinshuk Govil and
                 John Chapin and Mendel Rosenblum and Mark Horowitz",
  title =        "Hardware fault containment in scalable shared-memory
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "73--84",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Martin:1997:ECL,
  author =       "Richard P. Martin and Amin M. Vahdat and David E.
                 Culler and Thomas E. Anderson",
  title =        "Effects of communication latency, overhead, and
                 bandwidth in a cluster architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "85--97",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Weber:1997:MIA,
  author =       "Wolf-Dietrich Weber and Stephen Gold and Pat Helland
                 and Takeshi Shimizu and Thomas Wicki and Winfried
                 Wilcke",
  title =        "The {Mercury Interconnect Architecture}: a
                 cost-effective infrastructure for high-performance
                 servers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "98--107",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hakura:1997:DAC,
  author =       "Ziyad S. Hakura and Anoop Gupta",
  title =        "The design and analysis of a cache architecture for
                 texture mapping",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "108--120",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wilson:1997:DHB,
  author =       "Kenneth M. Wilson and Kunle Olukotun",
  title =        "Designing high bandwidth on-chip caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "121--132",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Farkas:1997:MSD,
  author =       "Keith I. Farkas and Paul Chow and Norman P. Jouppi and
                 Zvonko Vranesic",
  title =        "Memory-system design considerations for
                 dynamically-scheduled processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "133--143",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ranganathan:1997:ISP,
  author =       "Parthasarathy Ranganathan and Vijay S. Pai and Hazim
                 Abdel-Shafi and Sarita V. Adve",
  title =        "The interaction of software prefetching with {ILP}
                 processors in shared-memory systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "144--156",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kontothanassis:1997:VBS,
  author =       "Leonidas Kontothanassis and Galen Hunt and Robert
                 Stets and Nikolaos Hardavellas and Micha{\l} Cierniak
                 and Srinivasan Parthasarathy and Wagner {Meira, Jr.}
                 and Sandhya Dwarkadas and Michael Scott",
  title =        "{VM}-based shared memory on low-latency,
                 remote-memory-access networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "157--169",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kagi:1997:ESL,
  author =       "Alain K{\"a}gi and Doug Burger and James R. Goodman",
  title =        "Efficient synchronization: let them eat {QOLB}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "170--180",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Moshovos:1997:DSS,
  author =       "Andreas Moshovos and Scott E. Breach and T. N.
                 Vijaykumar and Gurindar S. Sohi",
  title =        "Dynamic speculation and synchronization of data
                 dependences",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "181--193",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sodani:1997:DIR,
  author =       "Avinash Sodani and Gurindar S. Sohi",
  title =        "Dynamic instruction reuse",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "194--205",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Palacharla:1997:CES,
  author =       "Subbarao Palacharla and Norman P. Jouppi and J. E.
                 Smith",
  title =        "Complexity-effective superscalar processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "206--218",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Michael:1997:CCA,
  author =       "Maged M. Michael and Ashwini K. Nanda and Beng-Hong
                 Lim and Michael L. Scott",
  title =        "Coherence controller architectures for {SMP}-based
                 {CC-NUMA} multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "219--228",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Falsafi:1997:RND,
  author =       "Babak Falsafi and David A. Wood",
  title =        "Reactive {NUMA}: a design for unifying {S-COMA} and
                 {CC-NUMA}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "229--240",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Laudon:1997:SOC,
  author =       "James Laudon and Daniel Lenoski",
  title =        "The {SGI Origin}: a {ccNUMA} highly scalable server",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "241--251",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Joseph:1997:PUM,
  author =       "Doug Joseph and Dirk Grunwald",
  title =        "Prefetching using {Markov} predictors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "252--263",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Santhanam:1997:DPH,
  author =       "Vatsa Santhanam and Edward H. Gornish and Wei-Chung
                 Hsu",
  title =        "Data prefetching on the {HP PA-8000}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "264--273",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chang:1997:TPI,
  author =       "Po-Yung Chang and Eric Hao and Yale N. Patt",
  title =        "Target prediction for indirect jumps",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "274--283",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sprangle:1997:APM,
  author =       "Eric Sprangle and Robert S. Chappell and Mitch Alsup
                 and Yale N. Patt",
  title =        "The agree predictor: a mechanism for reducing negative
                 branch history interference",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "284--291",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Michaud:1997:TCC,
  author =       "Pierre Michaud and Andr{\'e} Seznec and Richard
                 Uhlig",
  title =        "Trading conflict and capacity aliasing in conditional
                 branch predictors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "292--303",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Emer:1997:LDP,
  author =       "Joel Emer and Nikolas Gloy",
  title =        "A language for describing predictors and its
                 application to automatic synthesis",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "304--314",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Johnson:1997:RTA,
  author =       "Teresa L. Johnson and Wen-mei W. Hwu",
  title =        "Run-time adaptive cache hierarchy management via
                 reference analysis",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "315--326",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fromm:1997:EEI,
  author =       "Richard Fromm and Stylianos Perissakis and Neal
                 Cardwell and Christoforos Kozyrakis and Bruce McGaughy
                 and David Patterson and Tom Anderson and Katherine
                 Yelick",
  title =        "The energy efficiency of {IRAM} architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "327--337",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Burger:1997:DA,
  author =       "Doug Burger and Stefanos Kaxiras and James R.
                 Goodman",
  title =        "{DataScalar} architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "2",
  pages =        "338--349",
  month =        may,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wilkes:1997:CLS,
  author =       "Maurice Wilkes and Andrew Hopper",
  title =        "The collapsed {LAN}: a solution to a bandwidth
                 problem?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "3",
  pages =        "1--5",
  month =        jun,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jokinen:1997:CDP,
  author =       "Tommi Jokinen and Chia-Jiu Wang",
  title =        "Cache design with path balancing table, skewing and
                 indirect tags",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "3",
  pages =        "6--12",
  month =        jun,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Burger:1997:STS,
  author =       "Doug Burger and Todd M. Austin",
  title =        "The {SimpleScalar} tool set, version 2.0",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "3",
  pages =        "13--25",
  month =        jun,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1997:INb,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "3",
  pages =        "26--27",
  month =        jun,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{VanMeter:1997:RCL,
  author =       "Rodney {Van Meter} and Greg Finn and Steve Hotz and
                 Dave Dyer",
  title =        "Response to the collapsed {LAN}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "4",
  pages =        "1--12",
  month =        sep,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:14 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hu:1997:OES,
  author =       "Weiwu Hu and Peisu Xia",
  title =        "Out-of-order execution in sequentially consistent
                 shared-memory systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "4",
  pages =        "3--10",
  month =        sep,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:14 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Khalid:1997:NTS,
  author =       "Humayun Khalid",
  title =        "A novel trace sampling technique",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "4",
  pages =        "11--16",
  month =        sep,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:14 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Khalid:1997:PKC,
  author =       "Humayun Khalid",
  title =        "Performance of the {KORA-2} cache replacement scheme",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "4",
  pages =        "17--21",
  month =        sep,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:14 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jutla:1997:IAP,
  author =       "D. N. Jutla and P. Bodorik",
  title =        "Improving applications performance: a memory model and
                 cache architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "4",
  pages =        "22--29",
  month =        sep,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:14 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ulmann:1997:NEP,
  author =       "B. Ulmann",
  title =        "{NICE}: an elegant and powerful 32-bit architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "4",
  pages =        "30--35",
  month =        sep,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:14 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1997:INc,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "4",
  pages =        "36--41",
  month =        sep,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:14 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pai:1997:RRS,
  author =       "Vijay S. Pai and Parthasarathy Ranganathan and Sarita
                 V. Adve",
  title =        "{RSIM}: {Rice} simulator for {ILP} multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "5",
  pages =        "1--1",
  month =        dec,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:21 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shi:1997:IID,
  author =       "Weisong Shi and Weiwu Hu and Ming Zhu",
  title =        "An innovative implementation for directory-based cache
                 coherence in shared memory multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "5",
  pages =        "2--9",
  month =        dec,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:21 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1997:INd,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "25",
  number =       "5",
  pages =        "10--14",
  month =        dec,
  year =         "1997",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:21 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ulmann:1998:ILE,
  author =       "B. Ulmann",
  title =        "Instruction looping, an extension to conditional
                 execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "1",
  pages =        "3--4",
  month =        mar,
  year =         "1998",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1216461.1216462",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:32 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The following article describes an easy to implement
                 but very powerful extension to simple conditional
                 execution based program flow control as used for
                 example in the ARM RISC processors and others.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Haring:1998:IWP,
  author =       "G{\"u}nter Haring and Christoph Lindemann and Martin
                 Reiser",
  title =        "International workshop performance evaluation ---
                 origins and directions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "1",
  pages =        "5--6",
  month =        mar,
  year =         "1998",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1216461.1216463",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:32 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Performance Evaluation is a discipline of Computer
                 Science for some thirty years. It seems time to take
                 stock of what we were doing. That is, provide answers
                 to the following questions:{\bullet} What are its
                 scientific contributions?{\bullet} What is its
                 relevance in industry and business?{\bullet} What is
                 its standing in academia?{\bullet} Where is the field
                 headed?{\bullet} What are its success stories and
                 failures?{\bullet} What are its current burning
                 questions?",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Munsil:1998:RSU,
  author =       "Wes Munsil and Chia-Jiu Wang",
  title =        "Reducing stack usage in {Java} bytecode execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "1",
  pages =        "7--11",
  month =        mar,
  year =         "1998",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1216461.1216464",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:32 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "For many years, the Tomasulo method of dynamically
                 scheduling instructions for execution in a load/store
                 processor has been known and used. This paper presents
                 an adaptation of the Tomasulo method to a stack-based
                 processor architecture, and illustrates its use in a
                 software simulator of a subset of the Java Virtual
                 Machine. Experimental results show that the adapted
                 Tomasulo method reduces stack usage, in some cases
                 eliminating it altogether. This method should be of
                 interest to computer architects and those involved in
                 the implementation and use of the Java programming
                 language.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1998:INaa,
  author =       "Mark Thorson",
  title =        "{Internet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "1",
  pages =        "12--17",
  month =        mar,
  year =         "1998",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1216461.1216465",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:32 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This column consists of selected traffic from the
                 comp.arch newsgroup, a forum for discussion of computer
                 architecture on Internet --- an international computer
                 network. As always, the opinions expressed in this
                 column are the personal views of the authors, and do
                 not necessarily represent the institutions to which
                 they are affiliated. Text which sets the context of a
                 message appears in italics; this is usually text the
                 author has quoted from earlier messages. The code-like
                 expressions below the authors' names are their
                 addresses on Internet.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Moudgill:1998:TFS,
  author =       "Mayan Moudgill",
  title =        "Techniques for fast simulation of associative cache
                 directories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "2",
  pages =        "1--8",
  month =        may,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chung:1998:LBC,
  author =       "Byung-Kwon Chung and Jih-Kwon Peir",
  title =        "{LRU}-based column-associative caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "2",
  pages =        "9--17",
  month =        may,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1998:INb,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "2",
  pages =        "18--22",
  month =        may,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:48 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Barroso:1998:MSC,
  author =       "Luiz Andr{\'e} Barroso and Kourosh Gharachorloo and
                 Edouard Bugnion",
  title =        "Memory system characterization of commercial
                 workloads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "3--14",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Keeton:1998:PCQ,
  author =       "Kimberly Keeton and David A. Patterson and Yong Qiang
                 He and Roger C. Raphael and Walter E. Baker",
  title =        "Performance characterization of a {Quad Pentium Pro
                 SMP} using {OLTP} workloads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "15--26",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:1998:ECD,
  author =       "Dennis C. Lee and Patrick J. Crowley and Jean-Loup
                 Baer and Thomas E. Anderson and Brian N. Bershad",
  title =        "Execution characteristics of desktop applications on
                 {Windows NT}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "27--38",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lo:1998:ADW,
  author =       "Jack L. Lo and Luiz Andr{\'e} Barroso and Susan J.
                 Eggers and Kourosh Gharachorloo and Henry M. Levy and
                 Sujay S. Parekh",
  title =        "An analysis of database workload performance on
                 simultaneous multithreaded processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "39--50",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Evers:1998:ACP,
  author =       "Marius Evers and Sanjay J. Patel and Robert S.
                 Chappell and Yale N. Patt",
  title =        "An analysis of correlation and predictability: what
                 makes two-level branch predictors work",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "52--61",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Federovsky:1998:BPB,
  author =       "Eitan Federovsky and Meir Feder and Sholomo Weiss",
  title =        "Branch prediction based on universal data compression
                 algorithms",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "62--72",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sazeides:1998:MPP,
  author =       "Yiannakis Sazeides and James E. Smith",
  title =        "Modeling program predictability",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "73--84",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cox:1998:MLT,
  author =       "Michael Cox and Narendra Bhandari and Michael Shantz",
  title =        "Multi-level texture caching for {$3$D} graphics
                 hardware",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "86--97",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Eberle:1998:SQC,
  author =       "Hans Eberle and Erwin Oertli",
  title =        "{Switcherland}: a {QoS} communication architecture for
                 workstation clusters",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "98--108",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Alvarez:1998:DDA,
  author =       "Guillermo A. Alvarez and Walter A. Burkhard and Larry
                 J. Stockmeyer and Flaviu Cristian",
  title =        "Declustered disk array architectures with optimal and
                 near-optimal parallelism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "109--120",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Grunwald:1998:CES,
  author =       "Dirk Grunwald and Artur Klauser and Srilatha Manne and
                 Andrew Pleszkun",
  title =        "Confidence estimation for speculation control",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "122--131",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Manne:1998:PGS,
  author =       "Srilatha Manne and Artur Klauser and Dirk Grunwald",
  title =        "Pipeline gating: speculation control for energy
                 reduction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "132--141",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chrysos:1998:MDP,
  author =       "George Z. Chrysos and Joel S. Emer",
  title =        "Memory dependence prediction using store sets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "142--153",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Juan:1998:DHL,
  author =       "Toni Juan and Sanji Sanjeevan and Juan J. Navarro",
  title =        "Dynamic history-length fitting: a third level of
                 adaptivity for branch prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "155--166",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Driesen:1998:AIB,
  author =       "Karel Driesen and Urs H{\"o}lzle",
  title =        "Accurate indirect branch prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "167--178",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mukherjee:1998:UPA,
  author =       "Shubhendu S. Mukherjee and Mark D. Hill",
  title =        "Using prediction to accelerate coherence protocols",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "179--190",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Oskin:1998:APC,
  author =       "Mark Oskin and Frederic T. Chong and Timothy
                 Sherwood",
  title =        "Active pages: a computation model for intelligent
                 memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "192--203",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Swanson:1998:ITR,
  author =       "Mark Swanson and Leigh Stoller and John Carter",
  title =        "Increasing {TLB} reach using superpages backed by
                 shadow memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "204--213",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Qiu:1998:ODA,
  author =       "Xiaogang Qiu and Michel Dubois",
  title =        "Options for dynamic address translation in {COMAs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "214--225",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{August:1998:IPS,
  author =       "David I. August and Daniel A. Connors and Scott A.
                 Mahlke and John W. Sias and Kevin M. Crozier and
                 Ben-Chung Cheng and Patrick R. Eaton and Qudus B.
                 Olaniran and Wen-mei W. Hwu",
  title =        "Integrated predicated and speculative execution in the
                 {IMPACT EPIC} architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "227--237",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wallace:1998:TMP,
  author =       "Steven Wallace and Brad Calder and Dean M. Tullsen",
  title =        "Threaded multiple path execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "238--249",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Klauser:1998:SEE,
  author =       "Artur Klauser and Abhijit Paithankar and Dirk
                 Grunwald",
  title =        "Selective eager execution on the {PolyPath}
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "250--259",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Patel:1998:ITC,
  author =       "Sanjay Jeram Patel and Marius Evers and Yale N. Patt",
  title =        "Improving trace cache effectiveness with branch
                 promotion and trace packing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "262--271",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gabbay:1998:EIF,
  author =       "Freddy Gabbay and Avi Mendelson",
  title =        "The effect of instruction fetch bandwidth on value
                 prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "272--281",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Albonesi:1998:DIC,
  author =       "David H. Albonesi",
  title =        "Dynamic {IPC\slash clock} rate optimization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "282--292",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhang:1998:PMC,
  author =       "Yinong Zhang and George B. {Adams III}",
  title =        "Performance modeling and code partitioning for the
                 {DS} architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "293--304",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Keckler:1998:EFG,
  author =       "Stephen W. Keckler and William J. Dally and Daniel
                 Maskit and Nicholas P. Carter and Andrew Chang and Whay
                 S. Lee",
  title =        "Exploiting fine-grain thread level parallelism on the
                 {MIT} multi-{ALU} processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "306--317",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Abandah:1998:EAT,
  author =       "Gheith A. Abandah and Edward S. Davidson",
  title =        "Effects of architectural and technological advances on
                 the {HP\slash Convex Exemplar}'s memory and
                 communication performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "318--329",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Blumrich:1998:DCS,
  author =       "Matthias A. Blumrich and Richard D. Alpert and Yuqun
                 Chen and Douglas W. Clark and Stefanos N. Damianakis
                 and Cezary Dubnicki and Edward W. Felten and Liviu
                 Iftode and Kai Li and Margaret Martonosi and Robert A.
                 Shillner",
  title =        "Design choices in the {SHRIMP} system: an empirical
                 study",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "330--341",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Soundararajan:1998:FUM,
  author =       "Vijayaraghavan Soundararajan and Mark Heinrich and Ben
                 Verghese and Kourosh Gharachorloo and Anoop Gupta and
                 John Hennessy",
  title =        "Flexible use of memory for replication\slash migration
                 in cache-coherent {DSM} multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "342--355",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kumar:1998:ESL,
  author =       "Sanjeev Kumar and Christopher Wilkerson",
  title =        "Exploiting spatial locality in data caches using
                 spatial footprints",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "357--368",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lynch:1998:LLL,
  author =       "William L. Lynch and Gary Lauterbach and Joseph I.
                 Chamdani",
  title =        "Low load latency through sum-addressed memory
                 {(SAM)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "369--379",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sorin:1998:AES,
  author =       "Daniel J. Sorin and Vijay S. Pai and Sarita V. Adve
                 and Mary K. Vernon and David A. Wood",
  title =        "Analytic evaluation of shared-memory systems with
                 {ILP} processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "3",
  pages =        "380--391",
  month =        jun,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:58 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Golla:1998:CEB,
  author =       "Prasad N. Golla and Eric C. Lin",
  title =        "A comparison of the effect of branch prediction on
                 multithreaded and scalar architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "4",
  pages =        "3--11",
  month =        sep,
  year =         "1998",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1216475.1216476",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:40 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Speculative instructions execution requires dynamic
                 branch predictors to increase the performance of a
                 processor by executing from predicted branch target
                 routines. Conventional Scalar architectures such as the
                 Superscalar or Multiscalar architecture executes from a
                 single stream, while a Multithreaded architecture
                 executes from multiple streams at a time. Several
                 aggressive branch predictors have been proposed with
                 high prediction accuracies. Unfortunately, none of the
                 branch predictors can provide 100\% accuracy.
                 Therefore, there is an inherent limitation on
                 speculative execution in real implementation. In this
                 paper, we show that Multithreaded architecture is a
                 better candidate for utilizing speculative execution
                 than Scalar architectures. Generally the branch
                 prediction performance degradation is compounded for
                 larger window sizes on Scalar architectures, while for
                 a Multithreaded architecture, by increasing the number
                 of executing threads, we could sustain a higher
                 performance for a large aggregated speculative window
                 size. Hence, heavier workloads may increase performance
                 and utilization for Multithreaded architectures. We
                 present analytical and simulation results to support
                 our argument.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1998:INc,
  author =       "Mark Thorson",
  title =        "{Internet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "4",
  pages =        "12--16",
  month =        sep,
  year =         "1998",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1216475.1216477",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:40 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This column consists of selected traffic from the
                 comp.arch newsgroup, a forum for discussion of computer
                 architecture on Internet---an international computer
                 network. As always, the opinions expressed in this
                 column are the personal views of the authors, and do
                 not necessarily represent the institutions to which
                 they are affiliated. Text which sets the context of a
                 message appears in italics; this is usually text the
                 author has quoted from earlier messages. The code-like
                 expressions below the authors' names are their
                 addresses on Internet.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Machanick:1998:SVL,
  author =       "Philip Machanick",
  title =        "Streaming vs. latency in information mass-transit",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "5",
  pages =        "4--6",
  month =        dec,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:21 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lafitte:1998:GMD,
  author =       "Jean-Louis Lafitte",
  title =        "A generalized mapping device to help memory latency",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "5",
  pages =        "7--13",
  month =        dec,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:21 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ashraf:1998:IRM,
  author =       "Farooq Ashraf and Mostafa Abd-El-Barr and Khalid
                 Al-Tawil",
  title =        "Introduction to routing in multicomputer networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "5",
  pages =        "14--21",
  month =        dec,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:21 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wilmot:1998:DTM,
  author =       "Dick Wilmot",
  title =        "Data threaded microarchitecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "26",
  number =       "5",
  pages =        "22--32",
  month =        dec,
  year =         "1998",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:21 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yuen:1999:SR,
  author =       "C. K. Yuen",
  title =        "Stack and {RISC}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "1",
  pages =        "3--9",
  month =        mar,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Baylor:1999:USS,
  author =       "Sandra Johnson Baylor",
  title =        "Unified scalable shared memory architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "1",
  pages =        "10--21",
  month =        mar,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{DeWitt:1999:PTL,
  author =       "Anthony DeWitt and Thomas Gross",
  title =        "The potential of thread-level speculation based on
                 value profiling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "1",
  pages =        "22--22",
  month =        mar,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kalamatianos:1999:IAI,
  author =       "John Kalamatianos and David R. Kaeli",
  title =        "Improving the accuracy of indirect branch prediction
                 via branch classification",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "1",
  pages =        "23--26",
  month =        mar,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ju:1999:PMD,
  author =       "Roy Dz-ching Ju and Jean-Fran{\c{c}}ois Collard and
                 Karim Oukbir",
  title =        "Probabilistic memory disambiguation and its
                 application to data speculation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "1",
  pages =        "27--30",
  month =        mar,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Postiff:1999:LIL,
  author =       "Matthew A. Postiff and David A. Greene and Gary S.
                 Tyson and Trevor N. Mudge",
  title =        "The limits of instruction level parallelism in
                 {SPEC95} applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "1",
  pages =        "31--34",
  month =        mar,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yang:1999:LMJ,
  author =       "Byung-Sun Yang and Junpyo Lee and Jinpyo Park and
                 Soo-Mook Moon and Kemal Ebcio{\u{g}}lu and Erik
                 Altman",
  title =        "Lightweight monitor for {Java VM}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "1",
  pages =        "35--38",
  month =        mar,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rao:1999:SAU,
  author =       "Amit Rao and Santosh Pande",
  title =        "Storage assignment using expression tree
                 transformations to generate compact and efficient {DSP}
                 code",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "1",
  pages =        "39--42",
  month =        mar,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Flautner:1999:HLS,
  author =       "Kriszti{\'a}n Flautner and Gary S. Tyson and Trevor
                 Mudge",
  title =        "A high level simulator integrated with the {Mirv}
                 compiler",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "1",
  pages =        "43--46",
  month =        mar,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Casse:1999:UAI,
  author =       "H. Cass{\'e} and L. F{\'e}raud and C. Rochange and P.
                 Sainrat",
  title =        "Using the abstract interpretation technique for static
                 pointer analysis",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "1",
  pages =        "47--50",
  month =        mar,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bahar:1999:CSC,
  author =       "Iris Bahar and Brad Calder and Dirk Grunwald",
  title =        "A comparison of software code reordering and victim
                 buffers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "1",
  pages =        "51--54",
  month =        mar,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Carr:1999:ISP,
  author =       "Steve Carr and Philip Sweany",
  title =        "Improving software pipelining with hardware support
                 for self-spatial loads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "1",
  pages =        "55--58",
  month =        mar,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:35 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Barua:1999:MCM,
  author =       "Rajeev Barua and Walter Lee and Saman Amarasinghe and
                 Anant Agarwal",
  title =        "{Maps}: a compiler-managed memory system for raw
                 machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "4--15",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vajapeyam:1999:DVM,
  author =       "Sriram Vajapeyam and P. J. Joseph and Tulika Mitra",
  title =        "Dynamic vectorization: a mechanism for exploiting
                 far-flung {ILP} in ordinary programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "16--27",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goldstein:1999:PCP,
  author =       "Seth Copen Goldstein and Herman Schmit and Matthew Moe
                 and Mihai Budiu and Srihari Cadambi and R. Reed Taylor
                 and Ronald Laufer",
  title =        "{PipeRench}: a co\slash processor for streaming
                 multimedia acceleration",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "28--39",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yoaz:1999:STI,
  author =       "Adi Yoaz and Mattan Erez and Ronny Ronen and Stephan
                 Jourdan",
  title =        "Speculation techniques for improving load related
                 instruction scheduling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "42--53",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bekerman:1999:CLA,
  author =       "Michael Bekerman and Stephan Jourdan and Ronny Ronen
                 and Gilad Kirshenboim and Lihu Rappoport and Adi Yoaz
                 and Uri Weiser",
  title =        "Correlated load-address predictors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "54--63",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Calder:1999:SVP,
  author =       "Brad Calder and Glenn Reinman and Dean M. Tullsen",
  title =        "Selective value prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "64--74",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Qiu:1999:TLM,
  author =       "Xiaogang Qiu and Michel Dubois",
  title =        "Tolerating late memory traps in {ILP} processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "76--87",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Luk:1999:MFE,
  author =       "Chi-Keung Luk and Todd C. Mowry",
  title =        "Memory forwarding: enabling aggressive layout
                 optimizations by guaranteeing the safety of data
                 relocation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "88--99",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cho:1999:DLV,
  author =       "Sangyeun Cho and Pen-Chung Yew and Gyungho Lee",
  title =        "Decoupling local variable accesses in a wide-issue
                 superscalar processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "100--110",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Roth:1999:EJP,
  author =       "Amir Roth and Gurindar S. Sohi",
  title =        "Effective jump-pointer prefetching for linked data
                 structures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "111--121",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ranganathan:1999:PIV,
  author =       "Parthasarathy Ranganathan and Sarita Adve and Norman
                 P. Jouppi",
  title =        "Performance of image and video processing with
                 general-purpose processors and media {ISA} extensions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "124--135",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Merten:1999:HDP,
  author =       "Matthew C. Merten and Andrew R. Trick and Christopher
                 N. George and John C. Gyllenhaal and Wen-mei W. Hwu",
  title =        "A hardware-driven profiling scheme for identifying
                 program hot spots to support runtime optimization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "136--147",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shen:1999:CRF,
  author =       "Xiaowei Shen and Arvind and Larry Rudolph",
  title =        "Commit-reconcile \& fences {(CRF)}: a new memory
                 model for architects and compiler writers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "150--161",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gniady:1999:SIR,
  author =       "Chris Gniady and Babak Falsafi and T. N. Vijaykumar",
  title =        "Is {SC + ILP = RC}?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "162--171",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "Instruction level parallelism (ILP); release
                 consistency (RC); sequential consistency (SC)",
}

@Article{Lai:1999:MSP,
  author =       "An-Chow Lai and Babak Falsafi",
  title =        "Memory sharing predictor: the key to a speculative
                 coherent {DSM}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "172--183",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chappell:1999:SSM,
  author =       "Robert S. Chappell and Jared Stark and Sangwook P. Kim
                 and Steven K. Reinhardt and Yale N. Patt",
  title =        "Simultaneous subordinate microthreading {(SSMT)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "186--195",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Black:1999:BBT,
  author =       "Bryan Black and Bohuslav Rychlik and John Paul Shen",
  title =        "The block-based trace cache",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "196--207",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{August:1999:PDL,
  author =       "David I. August and John W. Sias and Jean-Michel
                 Puiatti and Scott A. Mahlke and Daniel A. Connors and
                 Kevin M. Crozier and Wen-mei W. Hwu",
  title =        "The program decision logic approach to predicated
                 execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "208--219",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cuppu:1999:PCC,
  author =       "Vinodh Cuppu and Bruce Jacob and Brian Davis and
                 Trevor Mudge",
  title =        "A performance comparison of contemporary {DRAM}
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "222--233",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reinman:1999:SFE,
  author =       "Glenn Reinman and Todd Austin and Brad Calder",
  title =        "A scalable front-end architecture for fast instruction
                 delivery",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "234--245",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kim:1999:AEA,
  author =       "Seongwoo Kim and Arun K. Somani",
  title =        "Area efficient architectures for information integrity
                 in cache memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "246--255",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nakra:1999:VPV,
  author =       "Tarun Nakra and Rajiv Gupta and Mary Lou Soffa",
  title =        "Value prediction in {VLIW} machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "258--269",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tullsen:1999:SVP,
  author =       "Dean M. Tullsen and John S. Seng",
  title =        "Storageless value prediction using prior register
                 values",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "270--279",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bilas:1999:UNI,
  author =       "Angelos Bilas and Cheng Liao and Jaswinder Pal Singh",
  title =        "Using network interface support to avoid asynchronous
                 protocol processing in shared virtual memory systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "282--293",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bilir:1999:MSN,
  author =       "E. Ender Bilir and Ross M. Dickson and Ying Hu and
                 Manoj Plakal and Daniel J. Sorin and Mark D. Hill and
                 David A. Wood",
  title =        "Multicast snooping: a new coherence method using a
                 multicast address network",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "294--304",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jiang:1999:SAP,
  author =       "Dongming Jiang and Jaswinder Pal Singh",
  title =        "Scaling application performance on a cache-coherent
                 multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "2",
  pages =        "305--316",
  month =        may,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:1999:MSF,
  author =       "Anonymous",
  title =        "In memoriam---{SIGARCH} founder: {Caxton C. Foster}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "3",
  pages =        "1--3",
  month =        jun,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:59 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hwang:1999:SSI,
  author =       "Seung H. Hwang and Gwan S. Choi",
  title =        "Selective-set-invalidation {(SSI)} for
                 soft-error-resilient cache architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "3",
  pages =        "4--9",
  month =        jun,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:59 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cheng:1999:DHP,
  author =       "Peng Cheng and Hai Jin and Jiangling Zhang",
  title =        "Design of high performance {RAID} in real-time
                 system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "3",
  pages =        "10--17",
  month =        jun,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:59 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yuen:1999:ASC,
  author =       "C. K. Yuen",
  title =        "Architectural support for the cache based vector
                 computation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "3",
  pages =        "18--23",
  month =        jun,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:59 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Driker:1999:DCC,
  author =       "Benjamin Driker",
  title =        "Disbursed control computer architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "3",
  pages =        "24--31",
  month =        jun,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:59 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Khalid:1999:PEM,
  author =       "Humayun Khalid",
  title =        "Performance evaluation of multimedia systems with
                 {MPEG-2} bitstreams",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "3",
  pages =        "32--37",
  month =        jun,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:59 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Khalid:1999:MPE,
  author =       "Humayun Khalid",
  title =        "A methodology for performance evaluation of systems
                 with large emulation code",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "3",
  pages =        "38--42",
  month =        jun,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:59 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Khalid:1999:TMB,
  author =       "Humayun Khalid",
  title =        "Tracing multimedia benchmarks with five degrees of
                 validation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "3",
  pages =        "43--48",
  month =        jun,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:59 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Khalid:1999:PET,
  author =       "Humayun Khalid",
  title =        "Performance evaluation of two operating systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "3",
  pages =        "49--52",
  month =        jun,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:59 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1999:INa,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "3",
  pages =        "53--60",
  month =        jun,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:59 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Machanick:1999:CRA,
  author =       "Phillip Machanick",
  title =        "Correction to {RAMpage ASPOLOS} paper",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "4",
  pages =        "2--5",
  month =        sep,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:14 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shahhoseini:1999:ABP,
  author =       "H. S. Shahhoseini and M. Naderi and S. Nemati",
  title =        "Achieving the best performance on superscalar
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "4",
  pages =        "6--11",
  month =        sep,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:14 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1999:INb,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "4",
  pages =        "12--14",
  month =        sep,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:14 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Torrant:1999:SMS,
  author =       "Marc Torrant and Muhammad Shaaban and Roy Czernikowski
                 and Ken Hsu",
  title =        "A simultaneous multithreading simulator",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "5",
  pages =        "1--5",
  month =        dec,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:1999:INc,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "27",
  number =       "5",
  pages =        "6--10",
  month =        dec,
  year =         "1999",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dai:2000:LSO,
  author =       "Min Dai and Christine Eisenbeis and Sid-Ahmed-Ali
                 Touati",
  title =        "Load-store optimization for software pipelining",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "1",
  pages =        "3--10",
  month =        mar,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Clauss:2000:AML,
  author =       "Philippe Clauss and Beno{\^\i}t Meister",
  title =        "Automatic memory layout transformations to optimize
                 spatial locality in parameterized loop nests",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "1",
  pages =        "11--19",
  month =        mar,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kreaseck:2000:LTB,
  author =       "Barbara Kreaseck and Dean Tullsen and Brad Calder",
  title =        "Limits of task-based parallelism in irregular
                 applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "1",
  pages =        "20--20",
  month =        mar,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:2000:RVC,
  author =       "Junpyo Lee and Byung-Sun Yang and Suhyun Kim and Kemal
                 Ebcio{\u{g}}lu and Erik Altman and Seungil Lee and Yoo
                 C. Chung and Heungbok Lee and Je Hyung Lee and Soo-Mook
                 Moon",
  title =        "Reducing virtual call overheads in a {Java VM}
                 just-in-time compiler",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "1",
  pages =        "21--33",
  month =        mar,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sadler:2000:APE,
  author =       "Chris Sadler and Sandeep K. S. Gupta and Rohit
                 Bhatia",
  title =        "Applying predication to efficiently handle runtime
                 class testing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "1",
  pages =        "34--42",
  month =        mar,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bermudo:2000:OCM,
  author =       "Nerina Bermudo and Xavier Vera and Antonio
                 Gonz{\'a}lez and Josep Llosa",
  title =        "Optimizing cache miss equations polyhedra",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "1",
  pages =        "43--52",
  month =        mar,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Unger:2000:CCA,
  author =       "A. Unger and E. Zehendner and Th. Ungerer",
  title =        "A combined compiler and architecture technique to
                 control multithreaded execution of branches and loop
                 iterations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "1",
  pages =        "53--61",
  month =        mar,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Aydin:2000:UCL,
  author =       "Hakan Aydin and David Kaeli",
  title =        "Using cache line coloring to perform aggressive
                 procedure inlining",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "1",
  pages =        "62--71",
  month =        mar,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tyagi:2000:COP,
  author =       "Akhilesh Tyagi and Gyungho Lee",
  title =        "A compiler optimization paradigm for dynamic energy
                 management",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "1",
  pages =        "72--76",
  month =        mar,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2000:INa,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "1",
  pages =        "77--78",
  month =        mar,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Steffan:2000:SAT,
  author =       "J. Greggory Steffan and Christopher B. Colohan and
                 Antonia Zhai and Todd C. Mowry",
  title =        "A scalable approach to thread-level speculation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "1--12",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cintra:2000:ASS,
  author =       "Marcelo Cintra and Jos{\'e} F. Mart{\'\i}nez and Josep
                 Torrellas",
  title =        "Architectural support for scalable speculative
                 parallelization in shared-memory multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "13--24",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reinhardt:2000:TFD,
  author =       "Steven K. Reinhardt and Shubhendu S. Mukherjee",
  title =        "Transient fault detection via simultaneous
                 multithreading",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "25--36",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jacobson:2000:TP,
  author =       "Quinn Jacobson and James E. Smith",
  title =        "Trace preconstruction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "37--46",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rakvic:2000:CTM,
  author =       "Ryan Rakvic and Bryan Black and John Paul Shen",
  title =        "Completion time multiple branch prediction for
                 enhancing trace cache performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "47--58",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Merten:2000:HMD,
  author =       "Matthew C. Merten and Andrew R. Trick and Erik M.
                 Nystrom and Ronald D. Barnes and Wen-mei W. Hmu",
  title =        "A hardware mechanism for dynamic extraction and
                 relayout of program hot spots",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "59--70",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Oskin:2000:HCS,
  author =       "Mark Oskin and Frederic T. Chong and Matthew Farrens",
  title =        "{HLS}: combining statistical and symbolic simulation
                 to guide microprocessor designs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "71--82",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Brooks:2000:WFA,
  author =       "David Brooks and Vivek Tiwari and Margaret Martonosi",
  title =        "{Wattch}: a framework for architectural-level power
                 analysis and optimizations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "83--94",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vijaykrishnan:2000:EDI,
  author =       "N. Vijaykrishnan and M. Kandemir and M. J. Irwin and
                 H. S. Kim and W. Ye",
  title =        "Energy-driven integrated hardware-software
                 optimizations using {SimplePower}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "95--106",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hallnor:2000:FAS,
  author =       "Erik G. Hallnor and Steven K. Reinhardt",
  title =        "A fully associative software-managed cache design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "107--116",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Saulsbury:2000:RBT,
  author =       "Ashley Saulsbury and Fredrik Dahlgren and Per
                 Stenstr{\"o}m",
  title =        "Recency-based {TLB} preloading",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "117--127",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rixner:2000:MAS,
  author =       "Scott Rixner and William J. Dally and Ujval J. Kapasi
                 and Peter Mattson and John D. Owens",
  title =        "Memory access scheduling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "128--138",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lai:2000:SAT,
  author =       "An-Chow Lai and Babak Falsafi",
  title =        "Selective, accurate, and timely self-invalidation
                 using last-touch prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "139--148",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Margolus:2000:EDA,
  author =       "Norman Margolus",
  title =        "An embedded {DRAM} architecture for large-scale
                 spatial-lattice computations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "149--160",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mai:2000:SMM,
  author =       "Ken Mai and Tim Paaske and Nuwan Jayasena and Ron Ho
                 and William J. Dally and Mark Horowitz",
  title =        "Smart {Memories}: a modular reconfigurable
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "161--171",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zilles:2000:UBS,
  author =       "Craig B. Zilles and Gurindar S. Sohi",
  title =        "Understanding the backward slices of performance
                 degrading instructions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "172--181",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lepak:2000:VLS,
  author =       "Kevin M. Lepak and Mikko H. Lipasti",
  title =        "On the value locality of store instructions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "182--191",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cvetanovic:2000:PAA,
  author =       "Zarka Cvetanovic and R. E. Kessler",
  title =        "Performance analysis of the {Alpha 21264}-based
                 {Compaq ES40} system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "192--202",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Faraboschi:2000:LTP,
  author =       "Paolo Faraboschi and Geoffrey Brown and Joseph A.
                 Fisher and Giuseppe Desoli and Fred Homewood",
  title =        "{Lx}: a technology platform for customizable {VLIW}
                 embedded processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "203--213",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ranganathan:2000:RCT,
  author =       "Parthasarathy Ranganathan and Sarita Adve and Norman
                 P. Jouppi",
  title =        "Reconfigurable caches and their application to media
                 processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "214--224",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ye:2000:CHP,
  author =       "Zhi Alex Ye and Andreas Moshovos and Scott Hauck and
                 Prithviraj Banerjee",
  title =        "{CHIMAERA}: a high-performance architecture with a
                 tightly-coupled reconfigurable functional unit",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "225--235",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Henry:2000:CWW,
  author =       "Dana S. Henry and Bradley C. Kuszmaul and Gabriel H.
                 Loh and Rahul Sami",
  title =        "Circuits for wide-window superscalar processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "236--247",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Agarwal:2000:CRV,
  author =       "Vikas Agarwal and M. S. Hrishikesh and Stephen W.
                 Keckler and Doug Burger",
  title =        "Clock rate versus {IPC}: the end of the road for
                 conventional microarchitectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "248--259",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smith:2000:VIS,
  author =       "J. E. Smith and Greg Faanes and Rabin Sugumar",
  title =        "Vector instruction set support for conditional
                 operations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "260--269",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chou:2000:IPC,
  author =       "Yuan Chou and John Paul Shen",
  title =        "Instruction path coprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "270--281",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Barroso:2000:PSA,
  author =       "Luiz Andr{\'e} Barroso and Kourosh Gharachorloo and
                 Robert McNamara and Andreas Nowatzyk and Shaz Qadeer
                 and Barton Sano and Scott Smith and Robert Stets and
                 Ben Verghese",
  title =        "{Piranha}: a scalable architecture based on
                 single-chip multiprocessing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "282--293",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Radhakrishnan:2000:AIE,
  author =       "Ramesh Radhakrishnan and Deependra Talla and Lizy
                 Kurian John",
  title =        "Allowing for {ILP} in an embedded {Java} processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "294--305",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bekerman:2000:ELA,
  author =       "Michael Bekerman and Adi Yoaz and Freddy Gabbay and
                 Stephan Jourdan and Maxim Kalaev and Ronny Ronen",
  title =        "Early load address resolution via register tracking",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "306--315",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cruz:2000:MBR,
  author =       "Jos{\'e}-Lorenzo Cruz and Antonio Gonz{\'a}lez and
                 Mateo Valero and Nigel P. Topham",
  title =        "Multiple-banked register file architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "2",
  pages =        "316--325",
  month =        may,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:49 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fernandez:2000:EPN,
  author =       "Benjam{\'\i}n Sahelices Fern{\'a}ndez and Diego R.
                 Llanos Ferraris and Agust{\'\i}n de Dios
                 Hern{\'a}ndez",
  title =        "Exploiting parallelism in a network of workstations
                 using {COMA-BC}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "3",
  pages =        "1--8",
  month =        jun,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:59 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2000:INb,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "3",
  pages =        "9--13",
  month =        jun,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:59 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lafitte:2000:RDH,
  author =       "Jean-Louis Lafitte",
  title =        "Regarding a device to help battering the {RAM} wall",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "4",
  pages =        "4--10",
  month =        sep,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:14 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Petit:2000:LSE,
  author =       "S. Petit and J. A. Gil and J. Sahuquillo and A. Pont",
  title =        "{LIDE}: a simulation environment for shared virtual
                 memory systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "4",
  pages =        "11--18",
  month =        sep,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:14 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schlosser:2000:DCS,
  author =       "Steven W. Schlosser and John Linwood Griffin and David
                 F. Nagle and Gregory R. Ganger",
  title =        "Designing computer systems with {MEMS}-based storage",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "1--12",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gharachorloo:2000:ADA,
  author =       "Kourosh Gharachorloo and Madhu Sharma and Simon Steely
                 and Stephen {Van Doren}",
  title =        "Architecture and design of {AlphaServer GS320}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "13--24",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Martin:2000:TSA,
  author =       "Milo M. K. Martin and Daniel J. Sorin and Anastassia
                 Ailamaki and Alaa R. Alameldeen and Ross M. Dickson and
                 Carl J. Mauer and Kevin E. Moore and Manoj Plakal and
                 Mark D. Hill and David A. Wood",
  title =        "Timestamp snooping: an approach for extending {SMPs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "25--36",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nanda:2000:MPR,
  author =       "Ashwini Nanda and Kwok-Ken Mak and Krishnan Sugarvanam
                 and Ramendra K. Sahoo and Vijayaraghavan Soundararajan
                 and T. Basil Smith",
  title =        "{MemorIES3}: a programmable, real-time hardware
                 emulation tool for multiprocessor server design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "37--48",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gibson:2000:FVS,
  author =       "Jeff Gibson and Robert Kunz and David Ofelt and Mark
                 Horowitz and John Hennessy and Mark Heinrich",
  title =        "{FLASH} vs. {(Simulated) FLASH}: closing the
                 simulation loop",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "49--58",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chou:2000:UML,
  author =       "Andy Chou and Benjamin Chelf and Dawson Engler and
                 Mark Heinrich",
  title =        "Using meta-level compilation to check {FLASH} protocol
                 code",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "59--70",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bhoedjang:2000:EDA,
  author =       "Raoul A. F. Bhoedjang and Kees Verstoep and Tim
                 R{\"u}hl and Henri E. Bal and Rutger F. H. Hofman",
  title =        "Evaluating design alternatives for reliable
                 communication on high-speed networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "71--81",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mattson:2000:CS,
  author =       "Peter Mattson and William J. Dally and Scott Rixner
                 and Ujval J. Kapasi and John D. Owens",
  title =        "Communication scheduling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "82--92",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hill:2000:SAD,
  author =       "Jason Hill and Robert Szewczyk and Alec Woo and Seth
                 Hollar and David Culler and Kristofer Pister",
  title =        "System architecture directions for networked sensors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "93--104",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lebeck:2000:PAP,
  author =       "Alvin R. Lebeck and Xiaobo Fan and Heng Zeng and Carla
                 Ellis",
  title =        "Power aware page allocation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "105--116",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Berger:2000:HSM,
  author =       "Emery D. Berger and Kathryn S. McKinley and Robert D.
                 Blumofe and Paul R. Wilson",
  title =        "{Hoard}: a scalable memory allocator for multithreaded
                 applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "117--128",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Flautner:2000:TLP,
  author =       "Kristi{\'a}n Flautner and Rich Uhlig and Steve
                 Reinhardt and Trevor Mudge",
  title =        "Thread-level parallelism and interactive performance
                 of desktop applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "129--138",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kawahito:2000:ENP,
  author =       "Motohiro Kawahito and Hideaki Komatsu and Toshio
                 Nakatani",
  title =        "Effective null pointer check elimination utilizing
                 hardware trap",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "139--149",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhang:2000:FVL,
  author =       "Youtao Zhang and Jun Yang and Rajiv Gupta",
  title =        "Frequent value locality and value-centric data cache
                 design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "150--159",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Burrows:2000:EFV,
  author =       "M. Burrows and U. Erlingson and S-T. A. Leung and M.
                 T. Vandevoorde and C. A. Waldspurger and K. Walker and
                 W. E. Weihl",
  title =        "Efficient and flexible value sampling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "160--167",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thekkath:2000:ASC,
  author =       "David Lie Chandramohan Thekkath and Mark Mitchell and
                 Patrick Lincoln and Dan Boneh and John Mitchell and
                 Mark Horowitz",
  title =        "Architectural support for copy and tamper resistant
                 software",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "168--177",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Burke:2000:ASF,
  author =       "Jerome Burke and John McDonald and Todd Austin",
  title =        "Architectural support for fast symmetric-key
                 cryptography",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "178--189",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kubiatowicz:2000:OAG,
  author =       "John Kubiatowicz and David Bindel and Yan Chen and
                 Steven Czerwinski and Patrick Eaton and Dennis Geels
                 and Ramakrishna Gummadi and Sean Rhea and Hakim
                 Weatherspoon and Chris Wells and Ben Zhao",
  title =        "{OceanStore}: an architecture for global-scale
                 persistent storage",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "190--201",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Duesterwald:2000:SPH,
  author =       "Evelyn Duesterwald and Vasanth Bala",
  title =        "Software profiling for hot path prediction: less is
                 more",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "202--211",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zahir:2000:CCD,
  author =       "Rumi Zahir and Jonathan Ross and Dale Morris and Drew
                 Hess",
  title =        "{OS} and compiler considerations in the design of the
                 {IA-64} architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "212--221",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Connors:2000:HSD,
  author =       "Daniel A. Connors and Hillery C. Hunter and Ben-Chung
                 Cheng and Wen-mei W. Hwu",
  title =        "Hardware support for dynamic activation of
                 compiler-directed computation reuse",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "222--233",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Snavely:2000:SJS,
  author =       "Allan Snavely and Dean M. Tullsen",
  title =        "Symbiotic job scheduling for a simultaneous
                 multithreaded processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "234--244",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Redstone:2000:AOS,
  author =       "Joshua A. Redstone and Susan J. Eggers and Henry M.
                 Levy",
  title =        "An analysis of operating system behavior on a
                 simultaneous multithreaded architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "245--256",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sundaramoorthy:2000:SPI,
  author =       "Karthik Sundaramoorthy and Zach Purser and Eric
                 Rotenburg",
  title =        "Slipstream processors: improving both performance and
                 fault tolerance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "28",
  number =       "5",
  pages =        "257--268",
  month =        dec,
  year =         "2000",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wilkes:2001:MGF,
  author =       "Maurice V. Wilkes",
  title =        "The memory gap and the future of high performance
                 memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "1",
  pages =        "2--7",
  month =        mar,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Manjikian:2001:MESa,
  author =       "Naraig Manjikian",
  title =        "Multiprocessor enhancements of the {SimpleScalar} tool
                 set",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "1",
  pages =        "8--15",
  month =        mar,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wang:2001:MAH,
  author =       "Frank Wang",
  title =        "A modified architecture for high-density {MRAM}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "1",
  pages =        "16--22",
  month =        mar,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Altman:2001:WWB,
  author =       "Erik R. Altman and David Kaeli",
  title =        "{WBT-2000}: {Workshop on Binary Translation 2000}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "1",
  pages =        "23--25",
  month =        mar,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Srivastava:2001:EOB,
  author =       "Amitabh Srivastava",
  title =        "Emerging opportunities for binary tools",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "1",
  pages =        "26--26",
  month =        mar,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cain:2001:DBT,
  author =       "Harold W. Cain and Kevin M. Lepak and Mikko H.
                 Lipasti",
  title =        "A dynamic binary translation approach to architectural
                 simulation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "1",
  pages =        "27--36",
  month =        mar,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hilgendorf:2001:ITE,
  author =       "Rolf Hilgendorf and Wolfram Sauer",
  title =        "Instruction translation for an experimental {S/390}
                 processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "1",
  pages =        "37--42",
  month =        mar,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ronsse:2001:JRJ,
  author =       "Michiel Ronsse and Koen {De Bosschere}",
  title =        "{JiTI}: a robust just in time instrumentation
                 technique",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "1",
  pages =        "43--54",
  month =        mar,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ung:2001:OHP,
  author =       "David Ung and Cristina Cifuentes",
  title =        "Optimising hot paths in a dynamic binary translator",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "1",
  pages =        "55--65",
  month =        mar,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gschwind:2001:OPE,
  author =       "Michael Gschwind and Erik Altman",
  title =        "Optimization and precise exceptions in dynamic
                 compilation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "1",
  pages =        "66--74",
  month =        mar,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2001:INa,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "1",
  pages =        "75--77",
  month =        mar,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zilles:2001:EBP,
  author =       "Craig Zilles and Gurindar Sohi",
  title =        "Execution-based prediction using speculative slices",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "2--13",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Collins:2001:SPL,
  author =       "Jamison D. Collins and Hong Wang and Dean M. Tullsen
                 and Christopher Hughes and Yong-Fong Lee and Dan Lavery
                 and John P. Shen",
  title =        "Speculative precomputation: long-range prefetching of
                 delinquent loads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "14--25",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Balasubramonian:2001:DAP,
  author =       "Rajeev Balasubramonian and Sandhya Dwarkadas and David
                 H. Albonesi",
  title =        "Dynamically allocating processor resources between
                 nearby and distant {ILP}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "26--37",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Luk:2001:TML,
  author =       "Chi-Keung Luk",
  title =        "Tolerating memory latency through software-controlled
                 pre-execution in simultaneous multithreading
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "40--51",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Annavaram:2001:DPD,
  author =       "Murali Annavaram and Jignesh M. Patel and Edward S.
                 Davidson",
  title =        "Data prefetching by dependence graph precomputation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "52--61",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cuppu:2001:CLS,
  author =       "Vinodh Cuppu and Bruce Jacob",
  title =        "Concurrency, latency, or system overhead: which has
                 the largest impact on uniprocessor {DRAM}-system
                 performance?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "62--71",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fields:2001:FPP,
  author =       "Brian Fields and Shai Rubin and Rastislav Bod{\'\i}k",
  title =        "Focusing processor policies via critical-path
                 prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "74--85",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sherwood:2001:ADF,
  author =       "Timothy Sherwood and Brad Calder",
  title =        "Automated design of finite state machine predictors
                 for customized processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "86--97",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wu:2001:BER,
  author =       "Youfeng Wu and Dong-Yuan Chen and Jesse Fang",
  title =        "Better exploration of region-level value locality with
                 integrated computation reuse and value prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "98--108",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wu:2001:CFF,
  author =       "Lisa Wu and Chris Weaver and Todd Austin",
  title =        "{CryptoManiac}: a fast flexible architecture for
                 secure communication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "110--119",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yum:2001:QPC,
  author =       "Ki Hwan Yum and Eun Jung Kim and Chita R. Das",
  title =        "{QoS} provisioning in clusters: an investigation of
                 {Router} and {NIC} design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "120--129",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Srinivasan:2001:LVC,
  author =       "Srikanth T. Srinivasan and Roy Dz-ching Ju and Alvin
                 R. Lebeck and Chris Wilkerson",
  title =        "Locality vs. criticality",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "132--143",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lai:2001:DBP,
  author =       "An-Chow Lai and Cem Fide and Babak Falsafi",
  title =        "Dead-block prediction \& dead-block correlating
                 prefetchers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "144--154",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ramirez:2001:CLO,
  author =       "Alex Ramirez and Luiz Andr{\'e} Barroso and Kourosh
                 Gharachorloo and Robert Cohn and Josep Larriba-Pey and
                 P. Geoffrey Lowney and Mateo Valero",
  title =        "Code layout optimizations for transaction processing
                 workloads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "155--164",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Niemier:2001:EEW,
  author =       "Michael Thaddeus Niemier and Peter M. Kogge",
  title =        "Exploring and exploiting wire-level pipelining in
                 emerging technologies",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "166--177",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Goldstein:2001:NSC,
  author =       "Seth Copen Goldstein and Mihai Budiu",
  title =        "{NanoFabrics}: spatial computing using molecular
                 electronics",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "178--191",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lie:2001:SME,
  author =       "David Lie and Andy Chou and Dawson Engler and David L.
                 Dill",
  title =        "A simple method for extracting models for protocol
                 code",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "192--203",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Prvulovic:2001:RAB,
  author =       "Milos Prvulovic and Mar{\'\i}a Jes{\'u}s Garzar{\'a}n
                 and Lawrence Rauchwerger and Josep Torrellas",
  title =        "Removing architectural bottlenecks to the scalability
                 of speculative parallelization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "204--215",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bahar:2001:PER,
  author =       "R. Iris Bahar and Srilatha Manne",
  title =        "Power and energy reduction via pipeline balancing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "218--229",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Folegnani:2001:EEI,
  author =       "Daniele Folegnani and Antonio Gonz{\'a}lez",
  title =        "Energy-effective issue logic",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "230--239",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kaxiras:2001:CDE,
  author =       "Stefanos Kaxiras and Zhigang Hu and Margaret
                 Martonosi",
  title =        "Cache decay: exploiting generational behavior to
                 reduce cache leakage power",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "240--251",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hughes:2001:VEM,
  author =       "Christopher J. Hughes and Praful Kaul and Sarita V.
                 Adve and Rohit Jain and Chanik Park and Jayanth
                 Srinivasan",
  title =        "Variability in the execution of multimedia
                 applications and implications for architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "254--265",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sastry:2001:RPS,
  author =       "S. Subramanya Sastry and Rastislav Bod{\'\i}k and
                 James E. Smith",
  title =        "Rapid profiling via stratified sampling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "2",
  pages =        "278--289",
  month =        may,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zilles:2001:BHC,
  author =       "Craig B. Zilles",
  title =        "Benchmark health considered harmful",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "3",
  pages =        "4--5",
  month =        jun,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thornock:2001:NTC,
  author =       "Niki C. Thornock and J. Kelly Flanagan",
  title =        "A national trace collection and distribution
                 resource",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "3",
  pages =        "6--10",
  month =        jun,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2001:INb,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "3",
  pages =        "11--15",
  month =        jun,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Manjikian:2001:MESb,
  author =       "Naraig Manjikian",
  title =        "More enhancements of the {SimpleScalar} tool set",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "4",
  pages =        "5--12",
  month =        sep,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:15 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cantin:2001:CPS,
  author =       "Jason F. Cantin and Mark D. Hill",
  title =        "Cache performance for selected {SPEC CPU2000}
                 benchmarks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "4",
  pages =        "13--18",
  month =        sep,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:15 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhang:2001:PLA,
  author =       "Jinsuo Zhang",
  title =        "The predictability of load address",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "4",
  pages =        "19--28",
  month =        sep,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:15 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2001:INc,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "4",
  pages =        "29--31",
  month =        sep,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:15 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{El-Kharashi:2001:ATA,
  author =       "M. Watheq El-Kharashi and Fayez Elguibaly and Kin F.
                 Li",
  title =        "Adapting {Tomasulo}'s algorithm for bytecode folding
                 based {Java} processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "1--8",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bartolini:2001:PAC,
  author =       "S. Bartolini and R. Giorgi and J. Protic and C. A.
                 Prete and M. Valero",
  title =        "Parallel architecture and compilation techniques:
                 selection of workshop papers, {Guest Editors}'
                 introduction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "9--12",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Acquaviva:2001:ECE,
  author =       "Andrea Acquaviva and Luca Benini and Bruno Ricc{\'o}",
  title =        "Energy characterization of embedded real-time
                 operating systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "13--18",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Moncusi:2001:IES,
  author =       "M. Angels Moncusi and Alex Arenas and Jesus Labarta",
  title =        "Improving energy saving in hard real time systems via
                 a modified dual priority scheduling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "19--24",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vahid:2001:PCP,
  author =       "Frank Vahid and Rilesh Patel and Greg Stitt",
  title =        "Propagating constants past software to hardware
                 peripherals in fixed-application embedded systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "25--30",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Aslot:2001:PCS,
  author =       "Vishal Aslot and Rudolf Eigenmann",
  title =        "Performance characteristics of the {SPEC OMP2001}
                 benchmarks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "31--40",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bull:2001:MSO,
  author =       "J. Mark Bull and Darragh O'Neill",
  title =        "A microbenchmark suite for {OpenMP 2.0}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "41--48",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nikolopoulos:2001:EMA,
  author =       "D. S. Nikolopoulos and E. Artiaga and E. Ayguad{\'e}
                 and J. Labarta",
  title =        "Exploiting memory affinity in {OpenMP} through
                 schedule reuse",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "49--55",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sung:2001:MDA,
  author =       "Michael Sung and Ronny Krashinsky and Krste
                 Asanovi{\'c}",
  title =        "Multithreading decoupled architectures for
                 complexity-effective general purpose computing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "56--61",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Talla:2001:MDA,
  author =       "Deependra Talla and Lizy K. John",
  title =        "{MediaBreeze}: a decoupled architecture for
                 accelerating multimedia applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "62--67",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nakajima:2001:MCS,
  author =       "Tatsuo Nakajima",
  title =        "A middleware component supporting flexible user
                 interaction for networked home appliances",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "68--75",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Touzet:2001:SSE,
  author =       "David Touzet and Jean-Marc Menaud and Fr{\'e}d{\'e}ric
                 Weis and Paul Couderc and Michel Ban{\^a}tre",
  title =        "{SIDE} surfer: enriching casual meetings with
                 spontaneous information gathering",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "76--83",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Altman:2001:WBT,
  author =       "Erik R. Altman and David R. Kaeli",
  title =        "{Workshop on Binary Translation 2001}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "84--85",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2001:INd,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "29",
  number =       "5",
  pages =        "86--90",
  month =        dec,
  year =         "2001",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:22 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Desikan:2002:EME,
  author =       "Rajagopalan Desikan and Doug Burger and Stephen W.
                 Keckler and Llorenc Cruz and Fernando Latorre and
                 Antonio Gonz{\'a}lez and Mateo Valero",
  title =        "Errata on {``Measuring Experimental Error in
                 Microprocessor Simulation''}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "1",
  pages =        "2--4",
  month =        mar,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chang:2002:ATI,
  author =       "Fu-Chi Chang and Chia-Jiu Wang",
  title =        "Architectural tradeoff in implementing {RSA}
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "1",
  pages =        "5--11",
  month =        mar,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Uht:2002:DEE,
  author =       "Augustus K. Uht",
  title =        "Disjoint {Eager Execution}: what it is \slash what it
                 is not",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "1",
  pages =        "12--14",
  month =        mar,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2002:INa,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "1",
  pages =        "15--21",
  month =        mar,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:36 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hartstein:2002:OPD,
  author =       "A. Hartstein and Thomas R. Puzak",
  title =        "The optimum pipeline depth for a microprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "7--13",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hrishikesh:2002:OLD,
  author =       "M. S. Hrishikesh and Doug Burger and Norman P. Jouppi
                 and Stephen W. Keckler and Keith I. Farkas and
                 Premkishore Shivakumar",
  title =        "The optimal logic depth per pipeline stage is 6 to 8
                 {FO4} inverter delays",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "14--24",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sprangle:2002:IPP,
  author =       "Eric Sprangle and Doug Carmean",
  title =        "Increasing processor performance by implementing
                 deeper pipelines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "25--34",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ernst:2002:EDS,
  author =       "Dan Ernst and Todd Austin",
  title =        "Efficient dynamic scheduling through tag elimination",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "37--46",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fields:2002:SMP,
  author =       "Brian Fields and Rastislav Bod{\'\i}k and Mark D.
                 Hill",
  title =        "{Slack}: maximizing performance under technological
                 constraints",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "47--58",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lebeck:2002:LFI,
  author =       "Alvin R. Lebeck and Jinson Koppanalil and Tong Li and
                 Jaidev Patwardhan and Eric Rotenberg",
  title =        "A large, fast instruction window for tolerating cache
                 misses",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "59--70",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kim:2002:ISM,
  author =       "Ho-Seop Kim and James E. Smith",
  title =        "An instruction set and microarchitecture for
                 instruction level distributed processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "71--81",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vijaykumar:2002:TFR,
  author =       "T. N. Vijaykumar and Irith Pomeranz and Karl Cheng",
  title =        "Transient-fault recovery using simultaneous
                 multithreading",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "87--98",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mukherjee:2002:DDE,
  author =       "Shubhendu S. Mukherjee and Michael Kontz and Steven K.
                 Reinhardt",
  title =        "Detailed design and evaluation of redundant
                 multithreading alternatives",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "99--110",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Prvulovic:2002:RCE,
  author =       "Milos Prvulovic and Zheng Zhang and Josep Torrellas",
  title =        "{ReVive}: cost-effective architectural support for
                 rollback recovery in shared-memory multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "111--122",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sorin:2002:SIA,
  author =       "Daniel J. Sorin and Milo M. K. Martin and Mark D. Hill
                 and David A. Wood",
  title =        "{SafetyNet}: improving the availability of shared
                 memory multiprocessors with global checkpoint\slash
                 recovery",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "123--134",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Heo:2002:DFG,
  author =       "Seongmoo Heo and Kenneth Barr and Mark Hampton and
                 Krste Asanovi{\'c}",
  title =        "Dynamic fine-grain leakage reduction using
                 leakage-biased bitlines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "137--147",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Flautner:2002:DCS,
  author =       "Kriszti{\'a}n Flautner and Nam Sung Kim and Steve
                 Martin and David Blaauw and Trevor Mudge",
  title =        "Drowsy caches: simple techniques for reducing leakage
                 power",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "148--157",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Iyer:2002:PPE,
  author =       "Anoop Iyer and Diana Marculescu",
  title =        "Power and performance evaluation of globally
                 asynchronous locally synchronous processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "158--168",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Solihin:2002:UUL,
  author =       "Yan Solihin and Jaejin Lee and Josep Torrellas",
  title =        "Using a user-level memory thread for correlation
                 prefetching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "171--182",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lewis:2002:AIM,
  author =       "Jarrod A. Lewis and Bryan Black and Mikko H. Lipasti",
  title =        "Avoiding initialization misses to the heap",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "183--194",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kandiraju:2002:GDT,
  author =       "Gokul B. Kandiraju and Anand Sivasubramaniam",
  title =        "Going the distance for {TLB} prefetching: an
                 application-driven study",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "195--206",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hu:2002:TMS,
  author =       "Zhigang Hu and Stefanos Kaxiras and Margaret
                 Martonosi",
  title =        "Timekeeping in the memory system: predicting and
                 optimizing memory behavior",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "209--220",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kim:2002:IOD,
  author =       "Ilhyun Kim and Mikko H. Lipasti",
  title =        "Implementing optimizations at decode time",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "221--232",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dhodapkar:2002:MMC,
  author =       "Ashutosh S. Dhodapkar and James E. Smith",
  title =        "Managing multi-configuration hardware via dynamic
                 working set analysis",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "233--244",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Buonadonna:2002:QPI,
  author =       "Philip Buonadonna and David Culler",
  title =        "Queue pair {IP}: a hybrid architecture for system area
                 networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "247--256",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhou:2002:EVC,
  author =       "Yuanyuan Zhou and Angelos Bilas and Suresh Jagannathan
                 and Cezary Dubnicki and James F. Philbin and Kai Li",
  title =        "Experiences with {VI} communication for database
                 storage",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "257--268",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pajuelo:2002:SDV,
  author =       "Alex Pajuelo and Antonio Gonz{\'a}lez and Mateo
                 Valero",
  title =        "Speculative dynamic vectorization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "271--280",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Espasa:2002:TVE,
  author =       "Roger Espasa and Federico Ardanaz and Joel Emer and
                 Stephen Felix and Julio Gago and Roger Gramunt and
                 Isaac Hernandez and Toni Juan and Geoff Lowney and
                 Matthew Mattina and Andr{\'e} Seznec",
  title =        "{Tarantula}: a vector extension to the {Alpha}
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "281--292",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seznec:2002:DTA,
  author =       "Andr{\'e} Seznec and Stephen Felix and Venkata
                 Krishnan and Yiannakis Sazeides",
  title =        "Design tradeoffs for the {Alpha EV8} conditional
                 branch predictor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "295--306",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chappell:2002:DPB,
  author =       "Robert S. Chappell and Francis Tseng and Adi Yoaz and
                 Yale N. Patt",
  title =        "Difficult-path branch prediction using subordinate
                 microthreads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "307--317",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Raasch:2002:SIQ,
  author =       "Steven E. Raasch and Nathan L. Binkert and Steven K.
                 Reinhardt",
  title =        "A scalable instruction queue design using dependence
                 chains",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "2",
  pages =        "318--329",
  month =        may,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Steele:2002:OHH,
  author =       "Ken Steele and Jason Waterman and Eugene Weinstein",
  title =        "The {Oxygen H21} handheld",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "3",
  pages =        "3--4",
  month =        jun,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Keen:2002:HSC,
  author =       "Diana Keen and Frederic T. Chong",
  title =        "Hardware-software co-design of embedded
                 sensor-actuator networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "3",
  pages =        "5--6",
  month =        jun,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kondo:2002:SCC,
  author =       "Masaaki Kondo and Motonobu Fujita and Hiroshi
                 Nakamura",
  title =        "Software-controlled on-chip memory for
                 high-performance and low-power computing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "3",
  pages =        "7--8",
  month =        jun,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sahoo:2002:SHA,
  author =       "Ramendra K. Sahoo and Myung Bae and Jose Moreira",
  title =        "Semi-hierarchical approach for reliability,
                 availability, and serviceability of cellular systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "3",
  pages =        "9--10",
  month =        jun,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Eberle:2002:MDC,
  author =       "Hans Eberle",
  title =        "Monitoring and diagnosing computer systems by radio
                 communication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "3",
  pages =        "11--12",
  month =        jun,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thies:2002:CML,
  author =       "William Thies and Michal Karczmarek and Michael Gordon
                 and David Maze and Jeremy Wong and Henry Hoffmann and
                 Matthew Brown and Saman Amarasinghe",
  title =        "A common machine language for grid-based
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "3",
  pages =        "13--14",
  month =        jun,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wang:2002:NAM,
  author =       "Frank Wang and Na Helian and Farhi Marir",
  title =        "A novel associative memory architecture for quick
                 matching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "3",
  pages =        "15--16",
  month =        jun,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Parker:2002:CUL,
  author =       "Mike Parker",
  title =        "A case for user-level interrupts",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "3",
  pages =        "17--18",
  month =        jun,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Burtscher:2002:IIF,
  author =       "Martin Burtscher",
  title =        "An improved index function for {(D)FCM} predictors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "3",
  pages =        "19--24",
  month =        jun,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2002:INb,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "3",
  pages =        "25--26",
  month =        jun,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gomez:2002:ASA,
  author =       "I. G{\`o}mez and L. Pi{\~n}uel and M. Prieto and F.
                 Tirado",
  title =        "Analysis of simulation-adapted {SPEC 2000}
                 benchmarks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "4",
  pages =        "4--10",
  month =        sep,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:15 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2002:INc,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "4",
  pages =        "11--16",
  month =        sep,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:15 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Estrin:2002:KAS,
  author =       "Deborah Estrin",
  title =        "Keynote address: {Sensor} network research: emerging
                 challenges for architecture, systems, and languages",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "1--4",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rajwar:2002:TLF,
  author =       "Ravi Rajwar and James R. Goodman",
  title =        "Transactional lock-free execution of lock-based
                 programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "5--17",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Martinez:2002:SSA,
  author =       "Jos{\'e} F. Mart{\'\i}nez and Josep Torrellas",
  title =        "Speculative synchronization: applying thread-level
                 speculation to explicitly parallel applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "18--29",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lepak:2002:TSS,
  author =       "Kevin M. Lepak and Mikko H. Lipasti",
  title =        "Temporally silent stores",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "30--41",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sherwood:2002:ACL,
  author =       "Timothy Sherwood and Erez Perelman and Greg Hamerly
                 and Brad Calder",
  title =        "Automatically characterizing large scale program
                 behavior",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "45--57",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ogata:2002:BFO,
  author =       "Kazunori Ogata and Hideaki Komatsu and Toshio
                 Nakatani",
  title =        "Bytecode fetch optimization for a {Java} interpreter",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "58--67",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Li:2002:UIO,
  author =       "Tao Li and Lizy Kurian John and Anand Sivasubramaniam
                 and N. Vijaykrishnan and Juan Rubio",
  title =        "Understanding and improving operating system effects
                 in control flow prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "68--80",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Levis:2002:MTV,
  author =       "Philip Levis and David Culler",
  title =        "{Mat{\'e}}: a tiny virtual machine for sensor
                 networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "85--95",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Juang:2002:EEC,
  author =       "Philo Juang and Hidekazu Oki and Yong Wang and
                 Margaret Martonosi and Li Shiuan Peh and Daniel
                 Rubenstein",
  title =        "Energy-efficient computing for wildlife tracking:
                 design tradeoffs and early experiences with
                 {ZebraNet}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "96--107",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kirovski:2002:ETS,
  author =       "Darko Kirovski and Milenko Drini{\'c} and Miodrag
                 Potkonjak",
  title =        "Enabling trusted software integrity",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "108--120",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zeng:2002:EME,
  author =       "Heng Zeng and Carla S. Ellis and Alvin R. Lebeck and
                 Amin Vahdat",
  title =        "{ECOSystem}: managing energy as a first class
                 operating system resource",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "123--132",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ashok:2002:CMC,
  author =       "Raksit Ashok and Saurabh Chheda and Csaba Andras
                 Moritz",
  title =        "{Cool-Mem}: combining statically speculative memory
                 accessing with selective address translation for energy
                 efficiency",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "133--143",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sasanka:2002:JLG,
  author =       "Ruchira Sasanka and Christopher J. Hughes and Sarita
                 V. Adve",
  title =        "Joint local and global hardware adaptations for
                 energy",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "144--155",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kim:2002:DEC,
  author =       "Dongkeun Kim and Donald Yeung",
  title =        "Design and evaluation of compiler algorithms for
                 pre-execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "159--170",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhai:2002:COS,
  author =       "Antonia Zhai and Christopher B. Colohan and J. Gregory
                 Steffan and Todd C. Mowry",
  title =        "Compiler optimization of scalar value communication
                 between speculative threads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "171--183",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Oplinger:2002:ESR,
  author =       "Jeffrey Oplinger and Monica S. Lam",
  title =        "Enhancing software reliability with speculative
                 threads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "184--196",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Butts:2002:DDI,
  author =       "J. Adam Butts and Guri Sohi",
  title =        "Dynamic dead-instruction detection and elimination",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "199--210",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kim:2002:ANU,
  author =       "Changkyu Kim and Doug Burger and Stephen W. Keckler",
  title =        "An adaptive, non-uniform cache structure for
                 wire-delay dominated on-chip caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "211--222",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mukherjee:2002:CSA,
  author =       "Shubhendu S. Mukherjee and Federico Silla and Peter
                 Bannon and Joel Emer and Steve Lang and David Webb",
  title =        "A comparative study of arbitration algorithms for the
                 {Alpha 21364} pipelined router",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "223--234",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kim:2002:IWS,
  author =       "Hyong-youb Kim and Vijay S. Pai and Scott Rixner",
  title =        "Increasing {Web} server throughput with network
                 interface data caching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "239--250",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kohler:2002:PLO,
  author =       "Eddie Kohler and Robert Morris and Benjie Chen",
  title =        "Programming language optimizations for modular router
                 configurations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "251--263",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sivathanu:2002:ERA,
  author =       "Muthian Sivathanu and Andrea C. Arpaci-Dusseau and
                 Remzi H. Arpaci-Dusseau",
  title =        "Evolving {RPC} for active storage",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "264--276",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cooksey:2002:SCD,
  author =       "Robert Cooksey and Stephan Jourdan and Dirk Grunwald",
  title =        "A stateless, content-directed data prefetching
                 mechanism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "279--290",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gordon:2002:SCC,
  author =       "Michael I. Gordon and William Thies and Michal
                 Karczmarek and Jasper Lin and Ali S. Meli and Andrew A.
                 Lamb and Chris Leger and Jeremy Wong and Henry Hoffmann
                 and David Maze and Saman Amarasinghe",
  title =        "A stream compiler for communication-exposed
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "291--303",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Witchel:2002:MMP,
  author =       "Emmett Witchel and Josh Cates and Krste Asanovi{\'c}",
  title =        "{Mondrian} memory protection",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "30",
  number =       "5",
  pages =        "304--316",
  month =        dec,
  year =         "2002",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Dennis:2003:FBM,
  author =       "Jack B. Dennis",
  title =        "Fresh {Breeze}: a multiprocessor chip architecture
                 guided by modular programming principles",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "1",
  pages =        "7--15",
  month =        mar,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Morano:2003:RHI,
  author =       "D. Morano and A. Khalafi and D. R. Kaeli and A. K.
                 Uht",
  title =        "Realizing high {IPC} through a scalable memory-latency
                 tolerant multipath microarchitecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "1",
  pages =        "16--25",
  month =        mar,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Almasi:2003:DCD,
  author =       "George Alm{\'a}si and C{\u{a}}lin Ca{\c{s}}caval and
                 Jos{\'e} G. Casta{\~n}os and Monty Denneau and Derek
                 Lieber and Jos{\'e} E. Moreira and Henry S. {Warren,
                 Jr.}",
  title =        "Dissecting {Cyclops}: a detailed analysis of a
                 multithreaded architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "1",
  pages =        "26--38",
  month =        mar,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zahran:2003:CMH,
  author =       "Mohamed M. Zahran",
  title =        "On cache memory hierarchy for {Chip-Multiprocessor}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "1",
  pages =        "39--48",
  month =        mar,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Grewal:2003:EAC,
  author =       "Gary Gr{\'e}wal and Tom Wilson and Andrew Morton",
  title =        "An {EGA} approach to the compile-time assignment of
                 data to multiple memories in digital-signal
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "1",
  pages =        "49--59",
  month =        mar,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ramacher:2003:GVP,
  author =       "Ulrich Ramacher and Nico Br{\"u}s and Ulrich Hachmann
                 and Jens Harnisch and Wolfgang Raab and Axel Techmer",
  title =        "{100 GOPS} vision processor for automotive
                 applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "1",
  pages =        "60--68",
  month =        mar,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Pitsianis:2003:IVM,
  author =       "Nikos P. Pitsianis and Gerald G. Pechanek",
  title =        "Indirect {VLIW} memory allocation for the {ManArray}
                 multiprocessor {DSP}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "1",
  pages =        "69--74",
  month =        mar,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shimizu:2003:TLS,
  author =       "Naohiko Shimizu and Ken Takatori",
  title =        "A transparent {Linux} super page kernel for {Alpha},
                 {Sparc64} and {IA32}: reducing {TLB} misses of
                 applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "1",
  pages =        "75--84",
  month =        mar,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bechini:2003:FGD,
  author =       "Alessio Bechini and Pierfrancesco Foglia and Cosimo
                 Antonio Prete",
  title =        "Fine-grain design space exploration for a cartographic
                 {SoC} multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "1",
  pages =        "85--92",
  month =        mar,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2003:INa,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "1",
  pages =        "93--96",
  month =        mar,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Skadron:2003:TAM,
  author =       "Kevin Skadron and Mircea R. Stan and Wei Huang and
                 Sivakumar Velusamy and Karthik Sankaranarayanan and
                 David Tarjan",
  title =        "Temperature-aware microarchitecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "2--13",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Magklis:2003:PBD,
  author =       "Grigorios Magklis and Michael L. Scott and Greg
                 Semeraro and David H. Albonesi and Steven Dropsho",
  title =        "Profile-based dynamic voltage and frequency scaling
                 for a multiple clock domain microprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "14--27",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kim:2003:HPA,
  author =       "Ilhyun Kim and Mikko H. Lipasti",
  title =        "Half-price architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "28--38",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Park:2003:IMP,
  author =       "Il Park and Babak Falsafi and T. N. Vijaykumar",
  title =        "Implicitly-multithreaded processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "39--51",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Citron:2003:MPM,
  author =       "Daniel Citron",
  title =        "{MisSPECulation}: partial and misleading use of {SPEC
                 CPU2000} in computer architecture conferences",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "52--61",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tseng:2003:BMR,
  author =       "Jessica H. Tseng and Krste Asanovi{\'c}",
  title =        "Banked multiported register files for high-frequency
                 superscalar microprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "62--71",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Powell:2003:PDM,
  author =       "Michael D. Powell and T. N. Vijaykumar",
  title =        "Pipeline damping: a microarchitectural technique to
                 reduce inductive noise in supply voltage",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "72--83",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wunderlich:2003:SAM,
  author =       "Roland E. Wunderlich and Thomas F. Wenisch and Babak
                 Falsafi and James C. Hoe",
  title =        "{SMARTS}: accelerating microarchitecture simulation
                 via rigorous statistical sampling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "84--97",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gomaa:2003:TFR,
  author =       "Mohamed Gomaa and Chad Scarbrough and T. N. Vijaykumar
                 and Irith Pomeranz",
  title =        "Transient-fault recovery for chip multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "98--109",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Prvulovic:2003:RUT,
  author =       "Milos Prvulovic and Josep Torrellas",
  title =        "{ReEnact}: using thread-level speculation mechanisms
                 to debug data races in multithreaded codes",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "110--121",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Xu:2003:FDR,
  author =       "Min Xu and Rastislav Bodik and Mark D. Hill",
  title =        "A ``flight data recorder'' for enabling full-system
                 multiprocessor deterministic replay",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "122--135",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhang:2003:HCC,
  author =       "Chuanjun Zhang and Frank Vahid and Walid Najjar",
  title =        "A highly configurable cache architecture for embedded
                 systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "136--146",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Buyuktosunoglu:2003:EEC,
  author =       "Alper Buyuktosuno{\u{g}}lu and Tejas Karkhanis and
                 David H. Albonesi and Pradip Bose",
  title =        "Energy efficient co-adaptive instruction fetch and
                 issue",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "147--156",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Huang:2003:PAP,
  author =       "Michael C. Huang and Jose Renau and Josep Torrellas",
  title =        "Positional adaptation of processors: application to
                 energy reduction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "157--168",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gurumurthi:2003:DDS,
  author =       "Sudhanva Gurumurthi and Anand Sivasubramaniam and
                 Mahmut Kandemir and Hubertus Franke",
  title =        "{DRPM}: dynamic speed control for power management in
                 server class disks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "169--181",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Martin:2003:TCD,
  author =       "Milo M. K. Martin and Mark D. Hill and David A. Wood",
  title =        "Token coherence: decoupling performance and
                 correctness",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "182--193",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Singh:2003:GLB,
  author =       "Arjun Singh and William J. Dally and Amit K. Gupta and
                 Brian Towles",
  title =        "{GOAL}: a load-balanced adaptive routing algorithm for
                 torus networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "194--205",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Martin:2003:UDS,
  author =       "Milo M. K. Martin and Pacia J. Harper and Daniel J.
                 Sorin and Mark D. Hill and David A. Wood",
  title =        "Using destination-set prediction to improve the
                 latency\slash bandwidth tradeoff in shared-memory
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "206--217",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cvetanovic:2003:PAA,
  author =       "Zarka Cvetanovic",
  title =        "Performance analysis of the {Alpha 21364}-based {HP
                 GS1280} multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "218--229",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Oberoi:2003:PFE,
  author =       "Paramjit S. Oberoi and Gurindar S. Sohi",
  title =        "Parallelism in the front-end",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "230--240",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seznec:2003:EAP,
  author =       "Andr{\'e} Seznec and Antony Fraboulet",
  title =        "Effective ahead pipelining of instruction block
                 address generation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "241--252",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ernst:2003:CBF,
  author =       "Dan Ernst and Andrew Hamel and Todd Austin",
  title =        "{Cyclone}: a broadcast-free dynamic instruction
                 scheduler with selective replay",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "253--263",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bhargava:2003:IDC,
  author =       "Ravi Bhargava and Lizy K. John",
  title =        "Improving dynamic cluster assignment for clustered
                 trace cache processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "264--274",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Balasubramonian:2003:DMC,
  author =       "Rajeev Balasubramonian and Sandhya Dwarkadas and David
                 H. Albonesi",
  title =        "Dynamically managing the communication-parallelism
                 trade-off in future clustered processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "275--287",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sherwood:2003:PMA,
  author =       "Timothy Sherwood and George Varghese and Brad Calder",
  title =        "A pipelined memory architecture for high throughput
                 network processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "288--299",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hasan:2003:EUM,
  author =       "Jahangir Hasan and Satish Chandra and T. N.
                 Vijaykumar",
  title =        "Efficient use of memory bandwidth to improve network
                 processor throughput",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "300--313",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thomas:2003:IBP,
  author =       "Renju Thomas and Manoj Franklin and Chris Wilkerson
                 and Jared Stark",
  title =        "Improving branch prediction by dynamic dataflow-based
                 identification of correlated branches from a large
                 global history",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "314--323",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhou:2003:DGS,
  author =       "Huiyang Zhou and Jill Flanagan and Thomas M. Conte",
  title =        "Detecting global stride locality in value streams",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "324--335",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sherwood:2003:PTP,
  author =       "Timothy Sherwood and Suleyman Sair and Brad Calder",
  title =        "Phase tracking and prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "336--349",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anantaraman:2003:VSA,
  author =       "Aravindh Anantaraman and Kiran Seth and Kaustubh Patil
                 and Eric Rotenberg and Frank Mueller",
  title =        "Virtual simple architecture {(VISA)}: exceeding the
                 complexity limit in safe real-time systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "350--361",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Corliss:2003:DPM,
  author =       "Marc L. Corliss and E. Christopher Lewis and Amir
                 Roth",
  title =        "{DISE}: a programmable macro engine for customizing
                 applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "362--373",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Oskin:2003:BQW,
  author =       "Mark Oskin and Frederic T. Chong and Isaac L. Chuang
                 and John Kubiatowicz",
  title =        "Building quantum wires: the long and the short of it",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "374--387",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wang:2003:GRP,
  author =       "Zhenlin Wang and Doug Burger and Kathryn S. McKinley
                 and Steven K. Reinhardt and Charles C. Weems",
  title =        "Guided region prefetching: a cooperative
                 hardware\slash software approach",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "388--398",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kozyrakis:2003:OLC,
  author =       "Christos Kozyrakis and David Patterson",
  title =        "Overcoming the limitations of conventional vector
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "399--409",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Suh:2003:PAP,
  author =       "Jinwoo Suh and Eun-Gyu Kim and Stephen P. Crago and
                 Lakshmi Srinivasan and Matthew C. French",
  title =        "A performance analysis of {PIM}, stream processing,
                 and tiled processing on memory-intensive signal
                 processing kernels",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "410--421",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sankaralingam:2003:EIT,
  author =       "Karthikeyan Sankaralingam and Ramadass Nagarajan and
                 Haiming Liu and Changkyu Kim and Jaehyuk Huh and Doug
                 Burger and Stephen W. Keckler and Charles R. Moore",
  title =        "Exploiting {ILP}, {TLP}, and {DLP} with the
                 polymorphous {TRIPS} architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "422--433",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chen:2003:JSD,
  author =       "Michael K. Chen and Kunle Olukotun",
  title =        "The {Jrpm} system for dynamically parallelizing {Java}
                 programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "2",
  pages =        "434--446",
  month =        may,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fong:2003:CAA,
  author =       "Anthony S. Fong",
  title =        "A computer architecture with access control and cache
                 option tags on individual instruction operands",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "3",
  pages =        "1--5",
  month =        jun,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tan:2003:DAP,
  author =       "Edwin J. Tan and Wendi B. Heinzelman",
  title =        "{DSP} architectures: past, present and futures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "3",
  pages =        "6--19",
  month =        jun,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vintan:2003:ABP,
  author =       "Lucian N. Vintan and Marius Sbera and Ioan Z. Mihu and
                 Adrian Florea",
  title =        "An alternative to branch prediction: pre-computed
                 branches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "3",
  pages =        "20--29",
  month =        jun,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Heinrich:2003:OWA,
  author =       "Mark Heinrich and Mainak Chaudhuri",
  title =        "Ocean warning: avoid drowning",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "3",
  pages =        "30--32",
  month =        jun,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lafitte:2003:QMC,
  author =       "Jean-Louis Lafitte",
  title =        "Qualitatively matching computer architecture with
                 {Turing} machine",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "3",
  pages =        "33--41",
  month =        jun,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Koushiro:2003:TLV,
  author =       "Takenori Koushiro and Toshinori Sato and Itsujiro
                 Arita",
  title =        "A trace-level value predictor for {Contrail}
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "3",
  pages =        "42--47",
  month =        jun,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2003:INb,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "3",
  pages =        "48--54",
  month =        jun,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:00 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorup:2003:CPM,
  author =       "Mikkel Thorup",
  title =        "Combinatorial power in multimedia processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "4",
  pages =        "5--11",
  month =        sep,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:15 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hau:2003:SJA,
  author =       "Gary K. W. Hau and Anthony Fong and Mok Pak Lun",
  title =        "Support of {Java API} for the {jHISC} system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "4",
  pages =        "12--17",
  month =        sep,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:15 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lun:2003:MMO,
  author =       "Mok Pak Lun and Richard Li and Anthony Fong",
  title =        "Method manipulation in an object-oriented processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "4",
  pages =        "18--25",
  month =        sep,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:15 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2003:INc,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "4",
  pages =        "26--32",
  month =        sep,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:15 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Breen:2003:AAA,
  author =       "Kristopher C. Breen and Duncan G. Elliott",
  title =        "Aliasing and anti-aliasing in branch history table
                 prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "5",
  pages =        "1--4",
  month =        dec,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yu:2003:TBS,
  author =       "Ryan W. S. Yu and Gary K. W. Hau and Anthony S. Fong",
  title =        "Test bench for software development of object-oriented
                 processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "5",
  pages =        "5--9",
  month =        dec,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lun:2003:OOP,
  author =       "Mok Pak Lun and Anthony Fong and Gary K. W. Hau",
  title =        "Object-oriented processor requirements with
                 instruction analysis of {Java} programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "5",
  pages =        "10--15",
  month =        dec,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2003:INd,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "31",
  number =       "5",
  pages =        "16--21",
  month =        dec,
  year =         "2003",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:23 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{John:2004:MFS,
  author =       "Lizy Kurian John",
  title =        "More on finding a single number to indicate overall
                 performance of a benchmark suite",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "1",
  pages =        "3--8",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2004:INa,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "1",
  pages =        "9--13",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Taylor:2004:ERM,
  author =       "Michael Bedford Taylor and Walter Lee and Jason Miller
                 and David Wentzlaff and Ian Bratt and Ben Greenwald and
                 Henry Hoffmann and Paul Johnson and Jason Kim and James
                 Psota and Arvind Saraf and Nathan Shnidman and Volker
                 Strumpen and Matt Frank and Saman Amarasinghe and Anant
                 Agarwal",
  title =        "Evaluation of the Raw Microprocessor: An
                 Exposed-Wire-Delay Architecture for {ILP} and
                 {Streams}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "2--2",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2004:GCC,
  author =       "Anonymous",
  title =        "General {Co-Chair}'s Message",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "9--9",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2004:PCM,
  author =       "Anonymous",
  title =        "Program {Chair}'s Message",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "10--10",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2004:C,
  author =       "Anonymous",
  title =        "Committees",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "11--11",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2004:Ra,
  author =       "Anonymous",
  title =        "Reviewers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "13--13",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ahn:2004:EIS,
  author =       "Jung Ho Ahn and William J. Dally and Brucek Khailany
                 and Ujval J. Kapasi and Abhishek Das",
  title =        "Evaluating the {Imagine Stream Architecture}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "14--14",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sias:2004:FTI,
  author =       "John W. Sias and Sain-zee Ueng and Geoff A. Kent and
                 Ian M. Steiner and Erik M. Nystrom and Wen-mei W. Hwu",
  title =        "Field-testing {IMPACT EPIC} research results in
                 {Itanium 2}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "26--26",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Vijaykumar:2004:WDP,
  author =       "T. N. Vijaykumar and Zeshan Chishti",
  title =        "Wire Delay is Not a Problem for {SMT} (In the Near
                 Future)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "40--40",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Krashinsky:2004:VTA,
  author =       "Ronny Krashinsky and Christopher Batten and Mark
                 Hampton and Steve Gerding and Brian Pharris and Jared
                 Casper and Krste Asanovic",
  title =        "The Vector-Thread Architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "52--52",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kumar:2004:SIH,
  author =       "Rakesh Kumar and Dean M. Tullsen and Parthasarathy
                 Ranganathan and Norman P. Jouppi and Keith I. Farkas",
  title =        "Single-{ISA} Heterogeneous Multi-Core Architectures
                 for Multithreaded Workload Performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "64--64",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chou:2004:MOE,
  author =       "Yuan Chou and Brian Fahs and Santosh Abraham",
  title =        "Microarchitecture Optimizations for Exploiting
                 Memory-Level Parallelism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "76--76",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cain:2004:MOV,
  author =       "Harold W. Cain and Mikko H. Lipasti",
  title =        "Memory Ordering: a Value-Based Approach",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "90--90",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hammond:2004:TMC,
  author =       "Lance Hammond and Vicky Wong and Mike Chen and Brian
                 D. Carlstrom and John D. Davis and Ben Hertzberg and
                 Manohar K. Prabhu and Honggo Wijaya and Christos
                 Kozyrakis and Kunle Olukotun",
  title =        "Transactional Memory Coherence and Consistency",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "102--102",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hangal:2004:TPV,
  author =       "Sudheendra Hangal and Durgam Vahia and Chaiyasit
                 Manovit and Juin-Yeu Joseph Lu",
  title =        "{TSOtool}: a Program for Verifying Memory Systems
                 Using the Memory Consistency Model",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "114--114",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chaudhuri:2004:SAN,
  author =       "Mainak Chaudhuri and Mark Heinrich",
  title =        "{SMTp}: {An Architecture} for {Next-generation
                 Scalable Multi-threading}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "124--124",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hughes:2004:FAF,
  author =       "Christopher J. Hughes and Sarita V. Adve",
  title =        "A {Formal Approach} to {Frequent Energy Adaptations}
                 for {Multimedia Applications}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "138--138",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Oliver:2004:SMC,
  author =       "John Oliver and Ravishankar Rao and Paul Sultana and
                 Jedidiah Crandall and Erik Czernikowski and Leslie W.
                 {Jones IV} and Diana Franklin and Venkatesh Akella and
                 Frederic T. Chong",
  title =        "{Synchroscalar}: a Multiple Clock Domain, Power-Aware,
                 Tile-Based Embedded Processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "150--150",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rosner:2004:PAT,
  author =       "Roni Rosner and Yoav Almog and Micha Moffie and
                 Naftali Schwartz and Avi Mendelson",
  title =        "Power Awareness through Selective Dynamically
                 Optimized Traces",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "162--162",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bairavasundaram:2004:XRN,
  author =       "Lakshmi N. Bairavasundaram and Muthian Sivathanu and
                 Andrea C. Arpaci-Dusseau and Remzi H. Arpaci-Dusseau",
  title =        "{X-RAY}: a Non-Invasive Exclusive Caching Mechanism
                 for {RAIDs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "176--176",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mullins:2004:LLV,
  author =       "Robert Mullins and Andrew West and Simon Moore",
  title =        "Low-Latency Virtual-Channel Routers for On-Chip
                 Networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "188--188",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Puente:2004:ICR,
  author =       "V. Puente and J. A. Gregorio and F. Vallejo and R.
                 Beivide",
  title =        "{Immunet}: a Cheap and Robust Fault-Tolerant Packet
                 Routing Mechanism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "198--198",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Alameldeen:2004:ACC,
  author =       "Alaa R. Alameldeen and David A. Wood",
  title =        "Adaptive Cache Compression for High-Performance
                 Processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "212--212",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhou:2004:IEA,
  author =       "Pin Zhou and Feng Qin and Wei Liu and Yuanyuan Zhou
                 and Josep Torrellas",
  title =        "{iWatcher}: Efficient Architectural Support for
                 Software Debugging",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "224--224",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yehia:2004:SDI,
  author =       "Sami Yehia and Olivier Temam",
  title =        "From Sequences of Dependent Instructions to Functions:
                 An Approach for Improving Performance without {ILP} or
                 Speculation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "238--238",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Falcon:2004:PCH,
  author =       "Ayose Falcon and Jared Stark and Alex Ramirez and
                 Konrad Lai and Mateo Valero",
  title =        "Prophet\slash Critic Hybrid Branch Prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "250--250",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Weaver:2004:TRS,
  author =       "Christopher Weaver and Joel Emer and Shubhendu S.
                 Mukherjee and Steven K. Reinhardt",
  title =        "Techniques to Reduce the Soft Error Rate of a
                 High-Performance Microprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "264--264",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Srinivasan:2004:CLR,
  author =       "Jayanth Srinivasan and Sarita V. Adve and Pradip Bose
                 and Jude A. Rivers",
  title =        "The Case for Lifetime Reliability-Aware
                 Microprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "276--276",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Powell:2004:ERB,
  author =       "Michael D. Powell and T. N. Vijaykumar",
  title =        "Exploiting Resonant Behavior to Reduce Inductive
                 Noise",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "288--288",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Butts:2004:UBR,
  author =       "J. Adam Butts and Gurindar S. Sohi",
  title =        "Use-Based Register Caching with Decoupled Indexing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "302--302",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gonzalez:2004:CAI,
  author =       "Gonzalez Gonzalez and Adrian Cristal and Daniel Ortega
                 and Alexander Veidenbaum and Mateo Valero",
  title =        "A Content Aware Integer Register File Organization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "314--314",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lipasti:2004:PRI,
  author =       "Mikko H. Lipasti and Brian R. Mestan and Erika
                 Gunadi",
  title =        "Physical Register Inlining",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "325--325",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Karkhanis:2004:FOS,
  author =       "Tejas S. Karkhanis and James E. Smith",
  title =        "A First-Order Superscalar Processor Model",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "338--338",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Eeckhout:2004:CFM,
  author =       "Lieven Eeckhout and Robert H. {Bell Jr.} and Bastiaan
                 Stougie and Koen {De Bosschere} and Lizy K. John",
  title =        "Control Flow Modeling in Statistical Simulation for
                 Accurate and Efficient Processor Design Studies",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "350--350",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Iyer:2004:ESI,
  author =       "Bharath Iyer and Sadagopan Srinivasan and Bruce
                 Jacob",
  title =        "Extended Split-Issue: Enabling Flexibility in the
                 Hardware Implementation of {NUAL VLIW DSPs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "364--364",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Parashar:2004:CEA,
  author =       "Angshuman Parashar and Sudhanva Gurumurthi and Anand
                 Sivasubramaniam",
  title =        "A Complexity-Effective Approach to {ALU} Bandwidth
                 Enhancement for Instruction-Level Temporal Redundancy",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "376--376",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2004:AI,
  author =       "Anonymous",
  title =        "Author Index",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "2",
  pages =        "387--387",
  month =        mar,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:45 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cristal:2004:CRC,
  author =       "Adri{\'a}n Cristal and Jos{\'e} F. Mart{\'\i}nez and
                 Josep Llosa and Mateo Valero",
  title =        "A case for resource-conscious out-of-order processors:
                 towards kilo-instruction in-flight processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "3",
  pages =        "3--10",
  month =        jun,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kundu:2004:CSI,
  author =       "Partha Kundu and Murali Annavaram and Trung Diep and
                 John Shen",
  title =        "A case for shared instruction cache on chip
                 multiprocessors running {OLTP}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "3",
  pages =        "11--18",
  month =        jun,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Venkateswaran:2004:MPN,
  author =       "N. Venkateswaran and Waran Research Foundation and
                 Aditya Krishnan and S. Niranjan Kumar and Arrvindh
                 Shriraman and Srinivas Sridharan",
  title =        "Memory in processor: a novel design paradigm for
                 supercomputing architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "3",
  pages =        "19--26",
  month =        jun,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Branovic:2004:WCE,
  author =       "I. Branovic and R. Giorgi and E. Martinelli",
  title =        "A workload characterization of elliptic curve
                 cryptography methods in embedded environments",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "3",
  pages =        "27--34",
  month =        jun,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Brifault:2004:DCM,
  author =       "K. Brifault and H. P. Charles",
  title =        "Data cache management on {EPIC} architecture:
                 optimizing memory access for image processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "3",
  pages =        "35--42",
  month =        jun,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shimizu:2004:JOL,
  author =       "Naohiko Shimizu and Chiaki Kon",
  title =        "{Java} object look aside buffer for embedded
                 applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "3",
  pages =        "43--49",
  month =        jun,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sakanaka:2004:LER,
  author =       "Akihito Sakanaka and Seiichirou Fujii and Toshinori
                 Sato",
  title =        "A leakage-energy-reduction technique for
                 highly-associative caches in embedded systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "3",
  pages =        "50--54",
  month =        jun,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Moch:2004:HSM,
  author =       "S. Moch and M. Berekovi{\'c} and H. J. Stolberg and L.
                 Friebe and M. B. Kulaczewski and A. Dehnhardt and P.
                 Pirsch",
  title =        "{HIBRID-SOC}: a multi-core architecture for image and
                 video applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "3",
  pages =        "55--61",
  month =        jun,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Berekovic:2004:SCS,
  author =       "Mladen Berekovic and S{\"o}ren Moch and Peter Pirsch",
  title =        "A scalable, clustered {SMT} processor for digital
                 signal processing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "3",
  pages =        "62--69",
  month =        jun,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bartolini:2004:PIS,
  author =       "S. Bartolini and C. A. Prete",
  title =        "A proposal for input-sensitivity analysis of
                 profile-driven optimizations on embedded applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "3",
  pages =        "70--77",
  month =        jun,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2004:INb,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "3",
  pages =        "78--83",
  month =        jun,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:01 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mashey:2004:WBM,
  author =       "John R. Mashey",
  title =        "War of the benchmark means: time for a truce",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "4",
  pages =        "1--14",
  month =        sep,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:16 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lafitte:2004:YLL,
  author =       "Jean-Louis Lafitte",
  title =        "40 years later \ldots{} a new engine to handle an
                 operating system infrastructure",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "4",
  pages =        "15--22",
  month =        sep,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:16 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2004:INc,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "4",
  pages =        "23--41",
  month =        sep,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:16 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hammond:2004:PTC,
  author =       "Lance Hammond and Brian D. Carlstrom and Vicky Wong
                 and Ben Hertzberg and Mike Chen and Christos Kozyrakis
                 and Kunle Olukotun",
  title =        "Programming with transactional coherence and
                 consistency {(TCC)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "1--13",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Budiu:2004:SC,
  author =       "Mihai Budiu and Girish Venkataramani and Tiberiu
                 Chelcea and Seth Copen Goldstein",
  title =        "Spatial computation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "14--26",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ekanayake:2004:ULP,
  author =       "Virantha Ekanayake and Clinton {Kelly IV} and Rajit
                 Manohar",
  title =        "An ultra low-power processor for sensor networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "27--36",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lumb:2004:DSD,
  author =       "Christopher R. Lumb and Richard Golding",
  title =        "{D-SPTF}: decentralized request distribution in
                 brick-based storage systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "37--47",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Saito:2004:FBD,
  author =       "Yasushi Saito and Svend Fr{\o}lund and Alistair Veitch
                 and Arif Merchant and Susan Spence",
  title =        "{FAB}: building distributed enterprise disk arrays
                 from commodity components",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "48--58",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Denehy:2004:DSA,
  author =       "Timothy E. Denehy and John Bent and Florentina I.
                 Popovici and Andrea C. Arpaci-Dusseau and Remzi H.
                 Arpaci-Dusseau",
  title =        "Deconstructing storage arrays",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "59--71",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhuang:2004:HIE,
  author =       "Xiaotong Zhuang and Tao Zhang and Santosh Pande",
  title =        "{HIDE}: an infrastructure for efficiently protecting
                 information leakage on the address bus",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "72--84",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Suh:2004:SPE,
  author =       "G. Edward Suh and Jae W. Lee and David Zhang and
                 Srinivas Devadas",
  title =        "Secure program execution via dynamic information flow
                 tracking",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "85--96",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Huh:2004:CDM,
  author =       "Jaehyuk Huh and Jichuan Chang and Doug Burger and
                 Gurindar S. Sohi",
  title =        "Coherence decoupling: making use of incoherence",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "97--106",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Srinivasan:2004:CFP,
  author =       "Srikanth T. Srinivasan and Ravi Rajwar and Haitham
                 Akkary and Amit Gandhi and Mike Upton",
  title =        "Continual flow pipelines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "107--119",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Desikan:2004:SSR,
  author =       "Rajagopalan Desikan and Simha Sethumadhavan and Doug
                 Burger and Stephen W. Keckler",
  title =        "Scalable selective re-execution for {EDGE}
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "120--132",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Regehr:2004:HSA,
  author =       "John Regehr and Alastair Reid",
  title =        "{HOIST}: a system for automatically deriving static
                 analyzers for embedded systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "133--143",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wang:2004:HTV,
  author =       "Perry H. Wang and Jamison D. Collins and Hong Wang and
                 Dongkeun Kim and Bill Greene and Kai-Ming Chan and
                 Aamir B. Yunus and Terry Sych and Stephen F. Moore and
                 John P. Shen",
  title =        "Helper threads via virtual multithreading on an
                 experimental {Itanium-2} processor-based platform",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "144--155",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hauswirth:2004:LOM,
  author =       "Matthias Hauswirth and Trishul M. Chilimbi",
  title =        "Low-overhead memory leak detection using adaptive
                 statistical profiling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "156--164",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shen:2004:LPP,
  author =       "Xipeng Shen and Yutao Zhong and Chen Ding",
  title =        "Locality phase prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "165--176",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhou:2004:DTP,
  author =       "Pin Zhou and Vivek Pandey and Jagadeesan Sundaresan
                 and Anand Raghuraman and Yuanyuan Zhou and Sanjeev
                 Kumar",
  title =        "Dynamic tracking of page miss ratio curve for memory
                 management",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "177--188",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rabbah:2004:COP,
  author =       "Rodric M. Rabbah and Hariharan Sandanagobalane and
                 Mongkol Ekpanyapong and Weng-Fai Wong",
  title =        "Compiler orchestrated prefetching via speculation and
                 predication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "189--198",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cher:2004:SPM,
  author =       "Chen-Yong Cher and Antony L. Hosking and T. N.
                 Vijaykumar",
  title =        "Software prefetching for mark-sweep garbage
                 collection: hardware analysis and software redesign",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "199--210",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lowell:2004:DVM,
  author =       "David E. Lowell and Yasushi Saito and Eileen J.
                 Samberg",
  title =        "Devirtualizable virtual machines enabling general,
                 single-node, online maintenance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "211--223",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Smolens:2004:FBS,
  author =       "Jared C. Smolens and Brian T. Gold and Jangwoo Kim and
                 Babak Falsafi and James C. Hoe and Andreas G.
                 Nowatzyk",
  title =        "Fingerprinting: bounding soft-error detection latency
                 and bandwidth",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "224--234",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bronevetsky:2004:ALC,
  author =       "Greg Bronevetsky and Daniel Marques and Keshav Pingali
                 and Peter Szwed and Martin Schulz",
  title =        "Application-level checkpointing for shared memory
                 programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "235--247",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wu:2004:FOM,
  author =       "Qiang Wu and Philo Juang and Margaret Martonosi and
                 Douglas W. Clark",
  title =        "Formal online methods for voltage\slash frequency
                 control in multiple clock domain microprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "248--259",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gomaa:2004:HRL,
  author =       "Mohamed Gomaa and Michael D. Powell and T. N.
                 Vijaykumar",
  title =        "Heat-and-run: leveraging {SMT} and {CMP} to manage
                 power density through the operating system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "260--270",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Li:2004:PDE,
  author =       "Xiaodong Li and Zhenmin Li and Francis David and Pin
                 Zhou and Yuanyuan Zhou and Sarita Adve and Sanjeev
                 Kumar",
  title =        "Performance directed energy management for main memory
                 and disks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "32",
  number =       "5",
  pages =        "271--283",
  month =        dec,
  year =         "2004",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chess:2005:SAC,
  author =       "David M. Chess",
  title =        "Security in autonomic computing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "2--5",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Shi:2005:TIA,
  author =       "Weidong Shi and Hsien-Hsin S. Lee and Chenghuai Lu and
                 Mrinmoy Ghosh",
  title =        "Towards the issues in architectural support for
                 protection of software execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "6--15",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{McGregor:2005:PCK,
  author =       "John P. McGregor and Ruby B. Lee",
  title =        "Protecting cryptographic keys and computations via
                 virtual secure coprocessing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "16--26",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Rogers:2005:MPH,
  author =       "Brian Rogers and Yan Solihin and Milos Prvulovic",
  title =        "Memory predecryption: hiding the latency overhead of
                 memory encryption",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "27--33",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Holland:2005:ADK,
  author =       "David A. Holland and Ada T. Lim and Margo I. Seltzer",
  title =        "An architecture a day keeps the hacker away",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "34--41",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Sidiroglou:2005:HSS,
  author =       "Stelios Sidiroglou and Michael E. Locasto and Angelos
                 D. Keromytis",
  title =        "Hardware support for self-healing software services",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "42--47",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Crandall:2005:SAM,
  author =       "Jedidiah R. Crandall and Frederic T. Chong",
  title =        "A security assessment of the {Minos} architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "48--57",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Burnside:2005:CCP,
  author =       "Matthew Burnside and Angelos D. Keromytis",
  title =        "The case for crypto protocol awareness inside the {OS}
                 kernel",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "58--64",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Corliss:2005:UDP,
  author =       "Marc L. Corliss and E. Christopher Lewis and Amir
                 Roth",
  title =        "Using {DISE} to protect return addresses from attack",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "65--72",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Ye:2005:RRA,
  author =       "Dong Ye and David Kaeli",
  title =        "A reliable return address stack: microarchitectural
                 features to defeat stack smashing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "73--80",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Inoue:2005:EST,
  author =       "Koji Inoue",
  title =        "Energy-security tradeoff in a secure cache
                 architecture against buffer overflow attacks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "81--89",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Uluski:2005:CAW,
  author =       "Derek Uluski and Micha Moffie and David Kaeli",
  title =        "Characterizing antivirus workload execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "90--98",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Aldwairi:2005:CSM,
  author =       "Monther Aldwairi and Thomas Conte and Paul Franzon",
  title =        "Configurable string matching hardware for speeding up
                 intrusion detection",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "99--107",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Milenkovic:2005:UIB,
  author =       "Milena Milenkovi{\'c} and Aleksandar Milenkovi{\'c}
                 and Emil Jovanov",
  title =        "Using instruction block signatures to counter code
                 injection attacks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "108--117",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Zhang:2005:ASP,
  author =       "Youtao Zhang and Jun Yang and Yongjing Lin and Lan
                 Gao",
  title =        "Architectural support for protecting user privacy on
                 trusted processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "118--123",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Shirase:2005:AEC,
  author =       "Masaaki Shirase and Yasushi Hibino",
  title =        "An architecture for elliptic curve cryptography
                 computation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "124--133",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Kgil:2005:CSS,
  author =       "Taeho Kgil and Laura Falk and Trevor Mudge",
  title =        "{ChipLock}: support for secure microarchitectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "134--143",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Workshop on Architectural Support for Security and
                 Anti-Virus (WASSA)",
}

@Article{Ekman:2005:DLC,
  author =       "Magnus Ekman and Fredrik Warg and Jim Nilsson",
  title =        "An in-depth look at computer performance growth",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "144--147",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Venkateswaran:2005:FTB,
  author =       "N. Venkateswaran and S. Balaji and V. Sridhar",
  title =        "Fault tolerant bus architecture for deep submicron
                 based processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "148--155",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2005:INa,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "1",
  pages =        "156--160",
  month =        mar,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:37 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:2005:APC,
  author =       "Ruby B. Lee and Peter C. S. Kwan and John P. McGregor
                 and Jeffrey Dwoskin and Zhenghong Wang",
  title =        "Architecture for Protecting Critical Secrets in
                 Microprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "2--13",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2005:GCM,
  author =       "Anonymous",
  title =        "{General Chair}'s Message",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "9--9",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2005:PCM,
  author =       "Anonymous",
  title =        "Program {Chair}'s Message",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "x--xv",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shi:2005:HEC,
  author =       "Weidong Shi and Hsien-Hsin S. Lee and Mrinmoy Ghosh
                 and Chenghuai Lu and Alexandra Boldyreva",
  title =        "High Efficiency Counter Mode Security Architecture via
                 Prediction and Precomputation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "14--24",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2005:C,
  author =       "Anonymous",
  title =        "Committees",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "16--16",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2005:R,
  author =       "Anonymous",
  title =        "Reviewers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "xvii--xviii",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Suh:2005:DIA,
  author =       "G. Edward Suh and Charles W. O'Donnell and Ishan
                 Sachdev and Srinivas Devadas",
  title =        "Design and Implementation of the {AEGIS} Single-Chip
                 Secure Processor Using Physical Random Functions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "25--36",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gurumurthi:2005:DDR,
  author =       "Sudhanva Gurumurthi and Anand Sivasubramaniam and
                 Vivek K. Natarajan",
  title =        "Disk Drive Roadmap from the Thermal Perspective: a
                 Case for Dynamic Thermal Management",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "38--49",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Huggahalli:2005:DCA,
  author =       "Ram Huggahalli and Ravi Iyer and Scott Tetrick",
  title =        "Direct Cache Access for High Bandwidth Network {I/O}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "50--59",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gunawi:2005:DCS,
  author =       "Haryadi S. Gunawi and Nitin Agrawal and Andrea C.
                 Arpaci-Dusseau and Remzi H. Arpaci-Dusseau and Jiri
                 Schindler",
  title =        "Deconstructing Commodity Storage Clusters",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "60--71",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ekman:2005:RMM,
  author =       "Magnus Ekman and Per Stenstr{\"o}m",
  title =        "A Robust Main-Memory Compression Scheme",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "74--85",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fahs:2005:CO,
  author =       "Brian Fahs and Todd Rafacz and Sanjay J. Patel and
                 Steven S. Lumetta",
  title =        "Continuous Optimization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "86--97",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Petric:2005:RRB,
  author =       "Vlad Petric and Tingting Sha and Amir Roth",
  title =        "{RENO}: a Rename-Based Instruction Optimizer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "98--109",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tan:2005:HTS,
  author =       "Lin Tan and Timothy Sherwood",
  title =        "A High Throughput String Matching Architecture for
                 Intrusion Detection and Prevention",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "112--122",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Baboescu:2005:TBR,
  author =       "Florin Baboescu and Dean M. Tullsen and Grigore Rosu
                 and Sumeet Singh",
  title =        "A Tree Based Router Search Engine Architecture with
                 Single Port Memories",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "123--133",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kyo:2005:IMA,
  author =       "Shorin Kyo and Shin'ichiro Okazaki and Tamio Arai",
  title =        "An Integrated Memory Array Processor Architecture for
                 Embedded Image Recognition Systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "134--145",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reis:2005:DEH,
  author =       "George A. Reis and Jonathan Chang and Neil
                 Vachharajani and Ram Rangan and David I. August and
                 Shubhendu S. Mukherjee",
  title =        "Design and Evaluation of Hybrid Fault-Detection
                 Systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "148--159",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schuchman:2005:RMT,
  author =       "Ethan Schuchman and T. N. Vijaykumar",
  title =        "{Rescue}: a Microarchitecture for Testability and
                 Defect Tolerance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "160--171",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gomaa:2005:OTF,
  author =       "Mohamed A. Gomaa and T. N. Vijaykumar",
  title =        "Opportunistic Transient-Fault Detection",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "172--183",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Balensiefer:2005:EFI,
  author =       "Steven Balensiefer and Lucas Kregor-Stickles and Mark
                 Oskin",
  title =        "An Evaluation Framework and Instruction Set
                 Architecture for Ion-Trap Based Quantum
                 Micro-Architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "186--196",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Nazhandali:2005:EOS,
  author =       "Leyla Nazhandali and Bo Zhai and Javin Olson and Anna
                 Reeves and Michael Minuth and Ryan Helfand and Sanjay
                 Pant and Todd Austin and David Blaauw",
  title =        "Energy Optimization of Subthreshold-Voltage Sensor
                 Network Processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "197--207",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hempstead:2005:ULP,
  author =       "Mark Hempstead and Nikhil Tripathi and Patrick Mauro
                 and Gu-Yeon Wei and David Brooks",
  title =        "An Ultra Low Power System Architecture for Sensor
                 Network Applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "208--219",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wenisch:2005:TSS,
  author =       "Thomas F. Wenisch and Stephen Somogyi and Nikolaos
                 Hardavellas and Jangwoo Kim and Anastassia Ailamaki and
                 Babak Falsafi",
  title =        "Temporal Streaming of Shared Memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "222--233",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Moshovos:2005:REC,
  author =       "Andreas Moshovos",
  title =        "{RegionScout}: Exploiting Coarse Grain Sharing in
                 Snoop-Based Coherence",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "234--245",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cantin:2005:IMP,
  author =       "Jason F. Cantin and Mikko H. Lipasti and James E.
                 Smith",
  title =        "Improving Multiprocessor Performance with Coarse-Grain
                 Coherence Tracking",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "246--257",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hines:2005:IPE,
  author =       "Stephen Hines and Joshua Green and Gary Tyson and
                 David Whalley",
  title =        "Improving Program Efficiency by Packing Instructions
                 into Registers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "260--271",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Clark:2005:AFT,
  author =       "Nathan Clark and Jason Blome and Michael Chu and Scott
                 Mahlke and Stuart Biles and Krisztian Flautner",
  title =        "An Architecture Framework for Transparent Instruction
                 Set Customization in Embedded Processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "272--283",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Narayanasamy:2005:BCR,
  author =       "Satish Narayanasamy and Gilles Pokam and Brad Calder",
  title =        "{BugNet}: Continuously Recording Program Execution for
                 Deterministic Replay Debugging",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "284--295",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Annavaram:2005:MAL,
  author =       "Murali Annavaram and Ed Grochowski and John Shen",
  title =        "Mitigating {Amdahl's Law} through {EPI} Throttling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "298--309",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "energy per instruction (EPI)",
}

@Article{Talpes:2005:ISP,
  author =       "Emil Talpes and Diana Marculescu",
  title =        "Increased Scalability and Power Efficiency by Using
                 Multiple Speed Pipelines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "310--321",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Petric:2005:EEP,
  author =       "Vlad Petric and Amir Roth",
  title =        "Energy-Effectiveness of Pre-Execution and Energy-Aware
                 {P}-Thread Selection",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "322--333",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhang:2005:VRM,
  author =       "Michael Zhang and Krste Asanovic",
  title =        "Victim Replication: Maximizing Capacity while Hiding
                 Wire Delay in Tiled Chip Multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "336--345",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Speight:2005:AMP,
  author =       "Evan Speight and Hazim Shafi and Lixin Zhang and Ram
                 Rajamony",
  title =        "Adaptive Mechanisms and Policies for Managing Cache
                 Hierarchies in Chip Multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "346--356",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chishti:2005:ORC,
  author =       "Zeshan Chishti and Michael D. Powell and T. N.
                 Vijaykumar",
  title =        "Optimizing Replication, Communication, and Capacity
                 Allocation in {CMPs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "357--368",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mutlu:2005:TEP,
  author =       "Onur Mutlu and Hyesoon Kim and Yale N. Patt",
  title =        "Techniques for Efficient Processing in Runahead
                 Execution Engines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "370--381",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jimenez:2005:PLB,
  author =       "Daniel A. Jimenez",
  title =        "Piecewise Linear Branch Prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "382--393",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seznec:2005:AGH,
  author =       "Andre Seznec",
  title =        "Analysis of the {O-GEometric History Length} Branch
                 Predictor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "394--405",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kumar:2005:IMC,
  author =       "Rakesh Kumar and Victor Zyuban and Dean M. Tullsen",
  title =        "Interconnections in Multi-Core Architectures:
                 Understanding Mechanisms, Overheads and Scaling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "408--419",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kim:2005:MHR,
  author =       "John Kim and William J. Dally and Brian Towles and
                 Amit K. Gupta",
  title =        "Microarchitecture of a High-Radix Router",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "420--431",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Seo:2005:NOW,
  author =       "Daeho Seo and Akif Ali and Won-Taek Lim and Nauman
                 Rafique and Mithuna Thottethodi",
  title =        "Near-Optimal Worst-Case Throughput Routing for
                 Two-Dimensional Mesh Networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "432--443",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gandhi:2005:SLS,
  author =       "Amit Gandhi and Haitham Akkary and Ravi Rajwar and
                 Srikanth T. Srinivasan and Konrad Lai",
  title =        "Scalable Load and Store Processing in Latency Tolerant
                 Processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "446--457",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Roth:2005:SVW,
  author =       "Amir Roth",
  title =        "{Store Vulnerability Window (SVW)}: Re-Execution
                 Filtering for Enhanced Load Optimization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "458--468",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Torres:2005:SBD,
  author =       "E. F. Torres and P. Ibanez and V. Vinals and J. M.
                 Llaberia",
  title =        "Store Buffer Design in First-Level Multibanked Data
                 Caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "469--480",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Meixner:2005:DVS,
  author =       "Albert Meixner and Daniel J. Sorin",
  title =        "Dynamic Verification of Sequential Consistency",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "482--493",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rajwar:2005:VTM,
  author =       "Ravi Rajwar and Maurice Herlihy and Konrad Lai",
  title =        "Virtualizing Transactional Memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "494--505",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Balakrishnan:2005:IPA,
  author =       "Saisanthosh Balakrishnan and Ravi Rajwar and Mike
                 Upton and Konrad Lai",
  title =        "The Impact of Performance Asymmetry in Emerging
                 Multicore Architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "506--517",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Srinivasan:2005:ESD,
  author =       "Jayanth Srinivasan and Sarita V. Adve and Pradip Bose
                 and Jude A. Rivers",
  title =        "Exploiting Structural Duplication for Lifetime
                 Reliability Enhancement",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "520--531",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Biswas:2005:CAV,
  author =       "Arijit Biswas and Paul Racunas and Razvan Cheveresan
                 and Joel Emer and Shubhendu S. Mukherjee and Ram
                 Rangan",
  title =        "Computing Architectural Vulnerability Factors for
                 Address-Based Structures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "532--543",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Qureshi:2005:VWC,
  author =       "Moinuddin K. Qureshi and David Thompson and Yale N.
                 Patt",
  title =        "The {V-Way Cache}: Demand Based Associativity via
                 Global Replacement",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "544--555",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2005:AI,
  author =       "Anonymous",
  title =        "Author Index",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "2",
  pages =        "556--557",
  month =        may,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:40:51 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bartolini:2005:GEI,
  author =       "S. Bartolini and P. Foglia and C. A. Prete",
  title =        "{Guests editors'} introduction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "3",
  pages =        "1--2",
  month =        jun,
  year =         "2005",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1152922.1101870",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:44 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In this issue of ACM SigArch Newsletter, we present
                 eight papers from the MEDEA Workshop, held in
                 conjunction with the International Conference on
                 Parallel Architectures and Compilation Techniques
                 (PACT-2004) [1], [2].",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fradj:2005:EAM,
  author =       "Hanene Ben Fradj and Asmaa el Ouardighi and C{\'e}cile
                 Belleudy and Michel Auguin",
  title =        "Energy aware memory architecture configuration",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "3",
  pages =        "3--9",
  month =        jun,
  year =         "2005",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1152922.1101871",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:44 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In the context of battery-driven embedded systems,
                 reducing energy while maintaining performance is one of
                 today's challenges. The on-chip memory count for a
                 great part of the whole system consumption, especially
                 for images and video processing applications that make
                 heavy use of large memory data size. In this paper, we
                 present new technique for efficiently exploiting
                 on-chip memory space (cache, scratchpad) for a specific
                 application to reduce the energy consumption without
                 loss of performance. We configure and compare the
                 impact of three different memory architectures on the
                 energy consumption. The first one is composed of main
                 memory with cache, in the second architecture we find a
                 main memory and scratchpad memory and in the last
                 architecture we combine both cache and scratchpad with
                 the main memory. We show the effectiveness of the last
                 architecture and a saving about 35\% in energy
                 consumption.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Suh:2005:DOC,
  author =       "Hyo-Joong Suh and Sung Woo Chung",
  title =        "{DRACO}: optimized {CC-NUMA} system with novel
                 dual-link interconnections to reduce the memory
                 latency",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "3",
  pages =        "10--16",
  month =        jun,
  year =         "2005",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1152922.1101872",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:44 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The performances of multiprocessor systems mainly rely
                 on the processor clock speed and the memory latency. As
                 the processors speed up rapidly, the memory latency
                 becomes a major performance bottleneck in
                 multiprocessor systems. In this paper, we propose a
                 dual-link interconnection topology and its effective
                 routing scheme to reduce the remote memory latency on
                 the interconnection network. It can be applied at a
                 same implementation cost as traditional bi-directional
                 ring systems. We compare the performance of the
                 proposed system to that of the traditional
                 bi-directional ring-based system and toroidal
                 mesh-based system. By simulations, it is shown that the
                 proposed system outperforms the traditional
                 bi-directional ring-based system by 42~101 \% and
                 excels the toroidal mesh-based system by 4~14\%.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yehia:2005:LSA,
  author =       "Sami Yehia and Jean-Fran{\c{c}}ois Collard and Olivier
                 Temam",
  title =        "Load squared: adding logic close to memory to reduce
                 the latency of indirect loads with high miss ratios",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "3",
  pages =        "17--24",
  month =        jun,
  year =         "2005",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1152922.1101873",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:44 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Indirect memory accesses, where a load is fed by
                 another load, are ubiquitous because of rich data
                 structures and sophisticated software conventions, such
                 as the use of linkage tables and position independent
                 code. Unfortunately, they can be costly: if both loads
                 miss, two round trips to memory are required even
                 though the role of the first load is often limited to
                 fetching the address of the second load. To reduce the
                 total latency of such indirect accesses, a new
                 instruction called load squared is introduced. A load
                 squared does two fetches, the first fetch reading the
                 target address of the second. (An offset is optionally
                 added to the result of the first fetch.) The load
                 squared operation is performed by memory-side logic
                 (typically, the memory controller if it isn't located
                 on the main processor chip). In this study, load
                 squared is not an architecturally visible instruction:
                 the micro-architecture transparently decides which
                 loads should be replaced by loads squared. We show that
                 performance is sometimes improved significantly, and
                 never degraded.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kobayashi:2005:LAC,
  author =       "Hiroaki Kobayashi and Isao Kotera and Hiroyuki
                 Takizawa",
  title =        "Locality analysis to control dynamically way-adaptable
                 caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "3",
  pages =        "25--32",
  month =        jun,
  year =         "2005",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1152922.1101874",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:44 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This paper presents a control mechanism for
                 dynamically way-adaptable caches. The mechanism uses
                 the local and global information about the locality of
                 reference during execution. As the local information,
                 the cache access pattern is evaluated based on the
                 statistics of the LRU (Least-Recently Used) states of
                 cache entries referenced. If the memory accesses are
                 concentrated on and near the most recently used
                 entries, the mechanism knows that the locality of
                 reference is very high and there is room to decrease
                 the number of ways activated to fit the current
                 locality. On the other hand, if the accesses are widely
                 distributed from the most recently used entries to the
                 least recently used ones, the mechanism understands
                 that more ways are needed to improve the performance as
                 long as the resources are available. In addition, to
                 examine the global behavior of the locality of
                 reference, an n-bit state machine like n-bit branch
                 predictors is introduced into the mechanism. The state
                 machine traces a sequence of cache resizing requests
                 and evaluates its stability across the execution time.
                 Therefore, the state machine helps the mechanism avoid
                 unstable actions for enabling/disabling cache ways when
                 the locality shows the highly irregular behavior. The
                 experimental results indicate that an n-bit asymmetric
                 state machine using the LRU status information works
                 well to appropriately control cache ways even in the
                 case of the benchmarks with highly-irregular access
                 behaviors in cache references.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Arakawa:2005:SXE,
  author =       "F. Arakawa and M. Ishikawa and Y. Kondo and T. Kamei
                 and M. Ozawa and O. Nishii and T. Hattori",
  title =        "{SH-X}: an embedded processor core for consumer
                 appliances",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "3",
  pages =        "33--40",
  month =        jun,
  year =         "2005",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1152922.1101875",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:44 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "A SuperH\TM{} embedded processor core SH-X implemented
                 in a 130-nm CMOS process running at 400 MHz achieved
                 720 MIPS and 2.8 GFLOPS at a power of 250 mW under
                 worst-case conditions. It has a dual-issue seven-stage
                 pipeline architecture, but reaches the 1.8 MIPS/MHz of
                 the previous five-stage processor. The on-chip memory
                 configuration is tuned for digital consumer appliances.
                 A new resume-standby mode enables a standby current of
                 less than 100$ \mu $A and a 3-ms recovery time. The
                 processor meets the requirements of a wide range of
                 applications, and is suitable for digital appliances
                 aimed at the consumer market, such as cellular phones,
                 digital still/video cameras, and car navigation
                 systems.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Naz:2005:IDC,
  author =       "Afrin Naz and Mehran Rezaei and Krishna Kavi and
                 Philip Sweany",
  title =        "Improving data cache performance with integrated use
                 of split caches, victim cache and stream buffers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "3",
  pages =        "41--48",
  month =        jun,
  year =         "2005",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1152922.1101876",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:44 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In our prior work we explored a cache organization
                 providing architectural support for distinguishing
                 between memory references that exhibit spatial and
                 temporal locality and mapping them to separate caches.
                 That work showed that using separate (data) caches for
                 indexed or stream data and scalar data items could lead
                 to substantial improvements in terms of cache misses.
                 In addition, such a separation allowed for the design
                 of caches that could be tailored to meet the properties
                 exhibited by different data items. In this paper, we
                 investigate the interaction between three established
                 methods: split cache, victim cache and stream buffer.
                 Since significant amounts of compulsory and conflict
                 misses are avoided, the size of each cache (i.e., array
                 and scalar), as well as the combined cache capacity can
                 be reduced. Our results show that on average 55\%
                 reduction in miss rates over the base configuration.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "array cache; memory access time; scalar cache; stream
                 buffer; victim cache",
}

@Article{Pajuelo:2005:SEH,
  author =       "Alex Pajuelo and Antonio Gonz{\'a}lez and Mateo
                 Valero",
  title =        "Speculative execution for hiding memory latency",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "3",
  pages =        "49--56",
  month =        jun,
  year =         "2005",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1152922.1101877",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:44 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "L2 misses are one of the main causes for stalling the
                 activity in current and future microprocessors. In this
                 paper we present a mechanism to speculatively execute
                 independent instructions of L2-miss loads, even if no
                 entry in the reorder buffer is available. The proposed
                 mechanism generates future instances of instructions
                 that are expected to be independent of the delinquent
                 load. When these dynamic instructions are later
                 fetched, they use the previously precomputed data and
                 directly go to the commit stage without executing. The
                 mechanism replicates strided loads found above the
                 L2-miss load, that produce the data for the target
                 independent instructions. Instructions following the
                 L2-miss load will check if their source operands have
                 been replicated. In this case, multiple speculative
                 instances of them will also be generated. This
                 mechanism is built on top of a superscalar processor
                 with an aggressive prefetch scheme. Compared to this
                 baseline, the mechanism obtains 21\% of performance
                 improvement.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Verdu:2005:ITA,
  author =       "Javier Verd{\'u} and Jorge Garc{\'\i}a and Mario
                 Nemirovsky and Mateo Valero",
  title =        "The impact of traffic aggregation on the memory
                 performance of networking applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "3",
  pages =        "57--62",
  month =        jun,
  year =         "2005",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1152922.1101878",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:44 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The trend of the networking processing is to increase
                 the intelligence of the routers (i.e. security
                 capacities). This means that there is an increment in
                 the workload generated per packet and new types of
                 applications are emerging, such as stateful programs.
                 On the other hand, Internet traffic continues to grow
                 vigorously. This fact involves an increment of the
                 traffic aggregation levels and overloads the processing
                 capacities of the routers. In this paper we show the
                 importance of traffic aggregation level on networking
                 application studies. We also classify the applications
                 according to the data management of the packet
                 processing. Hence, we present the different impacts on
                 the data cache performance depending on the application
                 category. Our results show that traffic aggregation
                 level may affect the cache performance depending on the
                 networking application category. Stateful applications
                 show a significant sensitivity to this impact.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Allu:2005:ERC,
  author =       "Bramha Allu and Wei Zhang",
  title =        "Exploiting the replication cache to improve
                 performance for multiple-issue microprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "3",
  pages =        "63--71",
  month =        jun,
  year =         "2005",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1101868.1101880",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:44 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Performance and reliability are both of great
                 importance for microprocessor design. Recently, the
                 replication cache has been proposed to enhance data
                 cache reliability against soft errors. The replication
                 cache is a small fully associative cache to store the
                 replica for every write to the L1 data cache. In
                 addition to enhance data reliability, this paper
                 proposes several cost-effective techniques to improve
                 performance of multiple-issue microprocessors by
                 exploiting the replication cache. The idea is to make
                 use of the replication cache to increase cache
                 bandwidth through dual load and to reduce the L1 data
                 cache miss rate through partial victim caching. Built
                 upon these two schemes, we also propose a hybrid
                 approach to combine the benefits of both dual load and
                 partial victim caching for improving performance
                 further. Our experimental results show that exploiting
                 a replication cache with only 8 entries can improve
                 performance by 13.0\% on average without compromising
                 the enhanced data integrity.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2005:INb,
  author =       "Mark Thorson",
  title =        "{Internet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "3",
  pages =        "72--74",
  month =        jun,
  year =         "2005",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1101868.1101882",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:44 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This column consists of selected traffic from the
                 comp.arch newsgroup, a forum for discussion of computer
                 architecture on the Internet---an international
                 computer network.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2005:MW,
  author =       "Anonymous",
  title =        "{MEDEA 2004} workshop",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "3",
  pages =        "??--??",
  month =        jun,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:06:44 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jouppi:2005:ISI,
  author =       "Norman P. Jouppi and Rakesh Kumar and Dean Tullsen",
  title =        "Introduction to the special issue on the {2005
                 Workshop on Design, Analysis, and Simulation of Chip
                 Multiprocessors (dasCMP'05)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "4--4",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Special issue: dasCMP'05.",
}

@Article{Laudon:2005:PWN,
  author =       "James Laudon",
  title =        "Performance\slash Watt: the new server focus",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "5--13",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Special issue: dasCMP'05.",
}

@Article{Davis:2005:RRA,
  author =       "John D. Davis and Cong Fu and James Laudon",
  title =        "The {RASE (Rapid, Accurate Simulation Environment)}
                 for chip multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "14--23",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Special issue: dasCMP'05.",
}

@Article{Hsu:2005:ECD,
  author =       "Lisa Hsu and Ravi Iyer and Srihari Makineni and Steve
                 Reinhardt and Donald Newell",
  title =        "Exploring the cache design space for large scale
                 {CMPs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "24--33",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Special issue: dasCMP'05.",
}

@Article{Davis:2005:CPS,
  author =       "John D. Davis and Stephen E. Richardson and Charis
                 Charitsis and Kunle Olukotun",
  title =        "A chip prototyping substrate: the flexible
                 architecture for simulation and testing {(FAST)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "34--43",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Special issue: dasCMP'05.",
}

@Article{Vachharajani:2005:CMP,
  author =       "Neil Vachharajani and Matthew Iyer and Chinmay Ashok
                 and Manish Vachharajani and David I. August and Daniel
                 Connors",
  title =        "Chip multi-processor scalability for single-threaded
                 applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "44--53",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Special issue: dasCMP'05.",
}

@Article{Chen:2005:HMP,
  author =       "Julia Chen and Philo Juang and Kevin Ko and Gilberto
                 Contreras and David Penry and Ram Rangan and Adam
                 Stoler and Li-Shiuan Peh and Margaret Martonosi",
  title =        "Hardware-modulated parallelism in chip
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "54--63",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Special issue: dasCMP'05.",
}

@Article{Sampson:2005:FSC,
  author =       "Jack Sampson and Rub{\'e}n Gonz{\'a}lez and
                 Jean-Fran{\c{c}}ois Collard and Norman P. Jouppi and
                 Mike Schlansker",
  title =        "Fast synchronization for chip multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "64--69",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Special issue: dasCMP'05.",
}

@Article{Shayesteh:2005:DCS,
  author =       "Anahita Shayesteh and Glenn Reinman and Norman Jouppi
                 and Suleyman Sair and Tim Sherwood",
  title =        "Dynamically configurable shared {CMP} helper engines
                 for improved performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "70--79",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Special issue: dasCMP'05.",
}

@Article{Constantinou:2005:PIS,
  author =       "Theofanis Constantinou and Yiannakis Sazeides and
                 Pierre Michaud and Damien Fetis and Andre Seznec",
  title =        "Performance implications of single thread migration on
                 a chip multi-core",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "80--91",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Special issue: dasCMP'05.",
}

@Article{Martin:2005:MGE,
  author =       "Milo M. K. Martin and Daniel J. Sorin and Bradford M.
                 Beckmann and Michael R. Marty and Min Xu and Alaa R.
                 Alameldeen and Kevin E. Moore and Mark D. Hill and
                 David A. Wood",
  title =        "Multifacet's general execution-driven multiprocessor
                 simulator {(GEMS)} toolset",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "92--99",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wang:2005:DMS,
  author =       "David Wang and Brinda Ganesh and Nuengwong Tuaycharoen
                 and Kathleen Baynes and Aamer Jaleel and Bruce Jacob",
  title =        "{DRAMsim}: a memory system simulator",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "100--107",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rountree:2005:NH,
  author =       "Barry Rountree and Robert Springer and David K.
                 Lowenthal and Vincent W. Freeh",
  title =        "Notes from {HPPAC 2005}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "108--112",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wang:2005:GFB,
  author =       "H. C. Wang and C. K. Yuen",
  title =        "A general framework to build new {CPUs} by mapping
                 abstract machine code to instruction level parallel
                 execution hardware",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "113--120",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sam:2005:IMS,
  author =       "Nana B. Sam and Martin Burtscher",
  title =        "Improving memory system performance with
                 energy-efficient value speculation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "121--127",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2005:INc,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "4",
  pages =        "128--133",
  month =        nov,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:08 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kaeli:2005:WIS,
  author =       "David Kaeli and Robert Cohn",
  title =        "{WBIA'05}: Introduction to the special issue",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "1--2",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Hu:2005:CCI,
  author =       "Chunling Hu and John McCabe and Daniel A. Jim{\'e}nez
                 and Ulrich Kremer",
  title =        "The {Camino Compiler} infrastructure",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "3--8",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Schulz:2005:SDB,
  author =       "Martin Schulz and Dong Ahn and Andrew Bernat and
                 Bronis R. de Supinski and Steven Y. Ko and Gregory Lee
                 and Barry Rountree",
  title =        "Scalable dynamic binary instrumentation for {Blue
                 Gene/L}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "9--14",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Borin:2005:DBC,
  author =       "Edson Borin and Cheng Wang and Youfeng Wu and Guido
                 Araujo",
  title =        "Dynamic binary control-flow errors detection",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "15--20",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Moffie:2005:AAS,
  author =       "Micha Moffie and David Kaeli",
  title =        "{ASM}: application security monitor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "21--26",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Zhao:2005:DMO,
  author =       "Qin Zhao and Rodric Rabbah and Weng-Fai Wong",
  title =        "Dynamic memory optimization using pool allocation and
                 prefetching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "27--32",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Gao:2005:AAL,
  author =       "Xiaofeng Gao and Beth Simon and Allan Snavely",
  title =        "{ALITER}: an asynchronous lightweight instrumentation
                 tool for event recording",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "33--38",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{McCurdy:2005:UPM,
  author =       "Collin McCurdy and Charles Fischer",
  title =        "Using {Pin} as a memory reference generator for
                 multiprocessor simulation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "39--44",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Pan:2005:CPE,
  author =       "Heidi Pan and Krste Asanovi{\'c} and Robert Cohn and
                 Chi-Keung Luk",
  title =        "Controlling program execution through binary
                 instrumentation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "45--50",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Faroughi:2005:PPP,
  author =       "Nikrouz Faroughi",
  title =        "Profiling of parallel processing programs on shared
                 memory multiprocessors using {Simics}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "51--56",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Kumar:2005:TDD,
  author =       "Naveen Kumar and Ramesh Peri",
  title =        "Transparent debugging of dynamically instrumented
                 programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "57--62",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Harris:2005:PAS,
  author =       "Laune C. Harris and Barton P. Miller",
  title =        "Practical analysis of stripped binary code",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "63--68",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Reddi:2005:PDC,
  author =       "Vijay Janapa Reddi and Dan Connors and Robert S.
                 Cohn",
  title =        "Persistence in dynamic code transformation systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "69--74",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Srinivasan:2005:MMC,
  author =       "Ram Srinivasan and Olaf Lubeck",
  title =        "{MonteSim}: a {Monte Carlo} performance model for
                 in-order microarchitectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "75--80",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Laurenzano:2005:LCT,
  author =       "Michael Laurenzano and Beth Simon and Allan Snavely
                 and Meghan Gunn",
  title =        "Low cost trace-driven memory simulation using
                 {SimPoint}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "81--86",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "WBIA'05",
}

@Article{Thorson:2005:INd,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "33",
  number =       "5",
  pages =        "87--93",
  month =        dec,
  year =         "2005",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri May 12 09:41:24 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bartolini:2006:MPD,
  author =       "S. Bartolini and P. Foglia and R. Giorgi and C. A.
                 Prete",
  title =        "Memory performance: dealing with applications, systems
                 and architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "1",
  pages =        "1--2",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Friedman:2006:DCR,
  author =       "Scott Friedman and Praveen Krishnamurthy and Roger
                 Chamberlain and Ron K. Cytron and Jason E. Fritts",
  title =        "Dusty caches for reference counting garbage
                 collection",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "1",
  pages =        "3--10",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ramaswamy:2006:DTC,
  author =       "Subramanian Ramaswamy and Jaswanth Sreeram and
                 Sudhakar Yalamanchili and Krishna V. Palem",
  title =        "Data trace cache: an application specific cache
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "1",
  pages =        "11--18",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Naz:2006:MCS,
  author =       "Afrin Naz and Krishna Kavi and Mehran Rezaei and
                 Wentong Li",
  title =        "Making a case for split data caches for embedded
                 applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "1",
  pages =        "19--26",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Allu:2006:ERC,
  author =       "B. Allu and W. Zhang and M. Kandala",
  title =        "Exploiting the replication cache to improve cache read
                 bandwidth cost effectively",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "1",
  pages =        "27--32",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Monchiero:2006:EST,
  author =       "Matteo Monchiero and Gianluca Palermo and Cristina
                 Silvano and Oreste Villa",
  title =        "An efficient synchronization technique for
                 multiprocessor systems on-chip",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "1",
  pages =        "33--40",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Khunjush:2006:HMD,
  author =       "Farshad Khunjush and Nikitas J. Dimopoulos",
  title =        "Hiding message delivery and reducing memory access
                 latency by providing direct-to-cache transfer during
                 receive operations in a message passing environment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "1",
  pages =        "41--48",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yue:2006:NCB,
  author =       "Yao Yue and Chuang Lin and Zhangxi Tan",
  title =        "{NPCryptBench}: a cryptographic benchmark suite for
                 network processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "1",
  pages =        "49--56",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lopez-Lagunas:2006:MBO,
  author =       "Abelardo L{\'o}pez-Lagunas and Sek M. Chai",
  title =        "Memory bandwidth optimization through stream
                 descriptors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "1",
  pages =        "57--64",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chiyonobu:2006:EEI,
  author =       "Akihiro Chiyonobu and Toshinori Sato",
  title =        "Energy-efficient instruction scheduling utilizing
                 cache miss information",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "1",
  pages =        "65--70",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bardine:2006:AEV,
  author =       "Alessandro Bardine and Alessio Bechini and
                 Pierfrancesco Foglia and Cosimo Antonio Prete",
  title =        "Analysis of embedded video coder systems: a
                 system-level approach",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "1",
  pages =        "71--76",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gontmakher:2006:ILG,
  author =       "Alex Gontmakher and Assaf Schuster and Avi Mendelson",
  title =        "{Inthreads}: a low granularity parallelization model",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "1",
  pages =        "77--80",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2006:INa,
  author =       "Mark Thorson",
  title =        "{Internet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "1",
  pages =        "81--86",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Patt:2006:CAR,
  author =       "Yale Patt",
  title =        "Computer Architecture Research and Future
                 Microprocessors: Where Do We Go from Here?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "2--2",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kim:2006:GDE,
  author =       "Jongman Kim and Chrysostomos Nicopoulos and Dongkook
                 Park",
  title =        "A Gracefully Degrading and Energy-Efficient Modular
                 Router Architecture for On-Chip Networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "4--15",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2006:MGC,
  author =       "Anonymous",
  title =        "Message from the General Chair",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "10--10",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2006:MPC,
  author =       "Anonymous",
  title =        "Message from the Program Chair",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "11--11",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2006:R,
  author =       "Anonymous",
  title =        "Reviewers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "14--14",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Scott:2006:BHR,
  author =       "Steve Scott and Dennis Abts and John Kim and William
                 J. Dally",
  title =        "The {BlackWidow} High-Radix {Clos} Network",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "16--28",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2006:SG,
  author =       "Anonymous",
  title =        "{SIGARCH} Guidelines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "17--17",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Arvind:2006:MMI,
  author =       "Arvind Arvind and Jan-Willem Maessen",
  title =        "Memory Model $=$ Instruction Reordering $+$ Store
                 Atomicity",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "29--40",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{vonPraun:2006:CMO,
  author =       "Christoph von Praun and Harold W. Cain and Jong-Deok
                 Choi and Kyung Dong Ryu",
  title =        "Conditional Memory Ordering",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "41--52",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{McDonald:2006:ASP,
  author =       "Austen McDonald and JaeWoong Chung and Brian D.
                 Carlstrom and Chi Cao Minh and Hassan Chafi and
                 Christos Kozyrakis and Kunle Olukotun",
  title =        "Architectural Semantics for Practical Transactional
                 Memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "53--65",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ranganathan:2006:ELP,
  author =       "Parthasarathy Ranganathan and Phil Leech and David
                 Irwin and Jeffrey Chase",
  title =        "Ensemble-level Power Management for Dense Blade
                 Servers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "66--77",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Donald:2006:TMT,
  author =       "James Donald and Margaret Martonosi",
  title =        "Techniques for Multicore Thermal Management:
                 Classification and New Exploration",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "78--88",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lin:2006:SLP,
  author =       "Yuan Lin and Hyunseok Lee and Mark Woh and Yoav Harel
                 and Scott Mahlke and Trevor Mudge and Chaitali
                 Chakrabarti and Krisztian Flautner",
  title =        "{SODA}: a Low-power Architecture For Software Radio",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "89--101",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shi:2006:IFD,
  author =       "Weidong Shi and Hsien-Hsin S. Lee and Laura `Falk and
                 Mrinmoy Ghosh",
  title =        "An Integrated Framework for Dependable and Revivable
                 Architectures Using Multicore Processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "102--113",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hankins:2006:MIS,
  author =       "Richard A. Hankins and Gautham N. Chinya and Jamison
                 D. Collins and Perry H. Wang and Ryan Rakvic and Hong
                 Wang and John P. Shen",
  title =        "Multiple Instruction Stream Processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "114--127",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Emma:2006:ESR,
  author =       "Philip Emma",
  title =        "The End of Scaling? Revolutions in Technology and
                 Microarchitecture as We Pass the 90 Nanometer Node",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "128--128",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Li:2006:DMC,
  author =       "Feihui Li and Chrysostomos Nicopoulos and Thomas
                 Richardson and Yuan Xie and Vijaykrishnan Narayanan and
                 Mahmut Kandemir",
  title =        "Design and Management of {$3$D} Chip Multiprocessors
                 Using Network-in-Memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "130--141",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Garg:2006:SMD,
  author =       "Alok Garg and M. Wasiur Rashid and Michael Huang",
  title =        "Slackened Memory Dependence Enforcement: Combining
                 Opportunistic Forwarding with Decoupled Verification",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "142--154",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Zhang:2006:BCR,
  author =       "Chuanjun Zhang",
  title =        "Balanced Cache: Reducing Conflict Misses of
                 Direct-Mapped Caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "155--166",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Qureshi:2006:CMA,
  author =       "Moinuddin K. Qureshi and Daniel N. Lynch and Onur
                 Mutlu and Yale N. Patt",
  title =        "A Case for {MLP}-Aware Cache Replacement",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "167--178",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yan:2006:ICP,
  author =       "Chenyu Yan and Daniel Englender and Milos Prvulovic
                 and Brian Rogers and Yan Solihin",
  title =        "Improving Cost, Performance, and Security of Memory
                 Encryption and Authentication",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "179--190",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Brodie:2006:SAH,
  author =       "Benjamin C. Brodie and David E. Taylor and Ron K.
                 Cytron",
  title =        "A Scalable Architecture For High-Throughput
                 Regular-Expression Pattern Matching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "191--202",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hasan:2006:CSE,
  author =       "Jahangir Hasan and Srihari Cadambi and Venkatta
                 Jakkula and Srimat Chakradhar",
  title =        "{Chisel}: a Storage-efficient, Collision-free
                 Hash-based Network Processing Architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "203--215",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Colohan:2006:TDB,
  author =       "Christopher B. Colohan and Anastassia Ailamaki and J.
                 Gregory Steffan and Todd C. Mowry",
  title =        "Tolerating Dependences Between Large Speculative
                 Threads Via Sub-Threads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "216--226",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ceze:2006:BDS,
  author =       "Luis Ceze and James Tuck and Josep Torrellas and Calin
                 Cascaval",
  title =        "Bulk Disambiguation of Speculative Threads in
                 Multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "227--238",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Choi:2006:LBS,
  author =       "Seungryul Choi and Donald Yeung",
  title =        "Learning-Based {SMT} Processor Resource Distribution
                 via Hill-Climbing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "239--251",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Somogyi:2006:SMS,
  author =       "Stephen Somogyi and Thomas F. Wenisch and Anastassia
                 Ailamaki and Babak Falsafi and Andreas Moshovos",
  title =        "Spatial Memory Streaming",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "252--263",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chang:2006:CCC,
  author =       "Jichuan Chang and Gurindar S. Sohi",
  title =        "Cooperative Caching for Chip Multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "264--276",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Hu:2006:RST,
  author =       "Shiliang Hu and James E. Smith",
  title =        "Reducing Startup Time in Co-Designed Virtual
                 Machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "277--288",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yang:2006:TAD,
  author =       "Qing Yang and Weijun Xiao and Jin Ren",
  title =        "{TRAP}-Array: a Disk Array Architecture Providing
                 Timely Recovery to Any Point-in-time",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "289--301",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Balakrishnan:2006:PDD,
  author =       "Saisanthosh Balakrishnan and Gurindar S. Sohi",
  title =        "Program Demultiplexing: Data-flow based Speculative
                 Parallelization of Methods in Sequential Programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "302--313",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Swanson:2006:APT,
  author =       "Steven Swanson and Andrew Putnam and Martha Mercaldi
                 and Ken Michelson and Andrew Petersen and Andrew
                 Schwerin and Mark Oskin and Susan J. Eggers",
  title =        "Area-Performance Trade-offs in Tiled Dataflow
                 Architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "314--326",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Strauss:2006:FSA,
  author =       "Karin Strauss and Xiaowei Shen and Josep Torrellas",
  title =        "Flexible Snooping: Adaptive Forwarding and Filtering
                 of Snoops in Embedded-Ring Multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "327--338",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cheng:2006:IAC,
  author =       "Liqun Cheng and Naveen Muralimanohar and Karthik
                 Ramani and Rajeev Balasubramonian and John B. Carter",
  title =        "Interconnect-Aware Coherence Protocols for Chip
                 Multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "339--351",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Herrod:2006:FVT,
  author =       "Steve Herrod",
  title =        "The Future of Virtualization Technology",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "352--352",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{VanMeter:2006:DAQ,
  author =       "Rodney {Van Meter} and Kae Nemoto and W. J. Munro and
                 Kohei M. Itoh",
  title =        "Distributed Arithmetic on a Quantum Multicomputer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "354--365",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Isailovic:2006:INS,
  author =       "Nemanja Isailovic and Yatish Patel and Mark Whitney
                 and John Kubiatowicz",
  title =        "Interconnection Networks for Scalable Quantum
                 Computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "366--377",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thaker:2006:QMH,
  author =       "Darshan D. Thaker and Tzvetan S. Metodi and Andrew W.
                 Cross and Isaac L. Chuang and Frederic T. Chong",
  title =        "Quantum Memory Hierarchies: Efficient Designs to Match
                 Available Parallelism in Quantum Computing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "378--390",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2006:AI,
  author =       "Anonymous",
  title =        "Author Index",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "2",
  pages =        "391--391",
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 21 15:00:05 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Burtscher:2006:TTA,
  author =       "Martin Burtscher",
  title =        "{TCgen 2.0}: a tool to automatically generate lossless
                 trace compressors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "3",
  pages =        "1--8",
  month =        jun,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Sep 4 12:39:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kumar:2006:LLB,
  author =       "Abhas Kumar and Nisheet Jain and Mainak Chaudhuri",
  title =        "Long-latency branches: how much do they matter?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "3",
  pages =        "9--15",
  month =        jun,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Sep 4 12:39:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2006:INb,
  author =       "Mark Thorson",
  title =        "{Internet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "3",
  pages =        "16--21",
  month =        jun,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Sep 4 12:39:50 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Henning:2006:SCB,
  author =       "John L. Henning",
  title =        "{SPEC CPU2006} benchmark descriptions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "4",
  pages =        "1--17",
  month =        sep,
  year =         "2006",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1186736.1186737",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:07:09 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "On August 24, 2006, the Standard Performance
                 Evaluation Corporation (SPEC) announced CPU2006 [2],
                 which replaces CPU2000. The SPEC CPU benchmarks are
                 widely used in both industry and academia [3].",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Citron:2006:HGM,
  author =       "Daniel Citron and Adham Hurani and Alaa Gnadrey",
  title =        "The harmonic or geometric mean: does it really
                 matter?",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "4",
  pages =        "18--25",
  month =        sep,
  year =         "2006",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1186736.1186738",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:07:09 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "For several decades, computer scientists have been
                 arguing which mean is more appropriate for summarizing
                 computer performance: the harmonic or the geometric. We
                 show that many test cases used in the past to discredit
                 one mean or the other are either artificial or
                 incidental. Changing only one of the benchmarks may
                 result in totally different conclusions. In addition,
                 we conclude that for the SPEC CPU2000 benchmark suite,
                 the choice of averaging has very little influence on
                 the relative standing of different machines. Therefore,
                 the decision to purchase one system rather then another
                 should not be influenced by the type of averaging
                 used.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Poe:2006:BBS,
  author =       "James Poe and Tao Li",
  title =        "{BASS}: a benchmark suite for evaluating architectural
                 security systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "4",
  pages =        "26--33",
  month =        sep,
  year =         "2006",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1186736.1186739",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:07:09 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "As software vulnerabilities continue to be exposed on
                 a daily basis and the motivation of cunning adversaries
                 to compromise valuable computer assets grows, novel
                 methods must be developed to ensure security. Recently
                 there has been a growing interest within the computer
                 architecture research community in designing
                 architectural and hardware mechanisms to improve
                 security. Unfortunately, there is currently not a
                 representative set of benchmarks for evaluating the
                 security features of proposed hardware modifications.
                 The frequent result is that great effort is often spent
                 searching for vulnerable programs, and/or evaluations
                 suffer from a lack of diversity. To address this
                 problem, we developed BASS, a benchmark suite to
                 evaluate the security features of proposed
                 architectural solutions under various malicious attack
                 scenarios. BASS v 1.0 currently consists of seven
                 benchmarks chosen to cover a diverse range of
                 architectural attack characteristics. To facilitate the
                 use of these benchmarks in architectural security
                 research, we have developed both vulnerable programs
                 and scripts to automatically generate exploits
                 targeting those vulnerable programs across both 32-bit
                 x86 and 64-bit Alpha Linux platforms. The entire BASS
                 framework including documentation, source code, input
                 data sets, and precompiled binaries for the M5 full
                 system simulator is released under the Gnu GPL and can
                 be freely downloaded at
                 http://www.ideal.ece.ufl.edu/bass.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2006:IN,
  author =       "Mark Thorson",
  title =        "{Internet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "4",
  pages =        "34--37",
  month =        sep,
  year =         "2006",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1186736.1186741",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 12:07:09 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This column consists of selected traffic from the
                 comp.arch newsgroup, a forum for discussion of computer
                 architecture on the Internet---an international
                 computer network. As always, the opinions expressed in
                 this column are the personal views of the authors, and
                 do not necessarily represent the institutions to which
                 they are affiliated. Text which sets the context of a
                 message appears underlined or in italics; this is
                 usually text the author has quoted from earlier
                 messages. The code-like expressions below the authors'
                 names are their addresses on Internet.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Rosenblum:2006:IVC,
  author =       "Mendel Rosenblum",
  title =        "Impact of virtualization on computer architecture and
                 operating systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "1--1",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Adams:2006:CSH,
  author =       "Keith Adams and Ole Agesen",
  title =        "A comparison of software and hardware techniques for
                 {x86} virtualization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "2--13",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jones:2006:GMB,
  author =       "Stephen T. Jones and Andrea C. Arpaci-Dusseau and
                 Remzi H. Arpaci-Dusseau",
  title =        "{Geiger}: monitoring the buffer cache in a virtual
                 machine environment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "14--24",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Crandall:2006:TSD,
  author =       "Jedidiah R. Crandall and Gary Wassermann and Daniela
                 A. S. de Oliveira and Zhendong Su and S. Felix Wu and
                 Frederic T. Chong",
  title =        "Temporal search: detecting hidden malware timebombs
                 with virtual machines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "25--36",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lu:2006:ADA,
  author =       "Shan Lu and Joseph Tucek and Feng Qin and Yuanyuan
                 Zhou",
  title =        "{AVIO}: detecting atomicity violations via access
                 interleaving invariants",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "37--48",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Xu:2006:RTR,
  author =       "Min Xu and Mark D. Hill and Rastislav Bodik",
  title =        "A regulated transitive reduction ({RTR}) for longer
                 memory race recording",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "49--60",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bond:2006:BBE,
  author =       "Michael D. Bond and Kathryn S. McKinley",
  title =        "{Bell}: bit-encoding online memory leak detection",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "61--72",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shyam:2006:ULC,
  author =       "Smitha Shyam and Kypros Constantinides and Sujay
                 Phadke and Valeria Bertacco and Todd Austin",
  title =        "Ultra low-cost defect protection for microprocessor
                 pipelines",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "73--82",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Reddy:2006:UPB,
  author =       "Vimal K. Reddy and Eric Rotenberg and Sailashri
                 Parthasarathy",
  title =        "Understanding prediction-based partial redundant
                 threading for low-overhead, high-coverage fault
                 tolerance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "83--94",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Parashar:2006:SSB,
  author =       "Angshuman Parashar and Anand Sivasubramaniam and
                 Sudhanva Gurumurthi",
  title =        "{SlicK}: slice-based locality exploitation for
                 efficient redundant multithreading",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "95--105",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Heath:2006:MFT,
  author =       "Taliver Heath and Ana Paula Centeno and Pradeep George
                 and Luiz Ramos and Yogesh Jaluria",
  title =        "{Mercury} and {Freon}: temperature emulation and
                 management for server systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "106--116",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kgil:2006:PUS,
  author =       "Taeho Kgil and Shaun D'Souza and Ali Saidi and Nathan
                 Binkert and Ronald Dreslinski and Trevor Mudge and
                 Steven Reinhardt and Krisztian Flautner",
  title =        "{PicoServer}: using {$3$D} stacking technology to
                 enable a compact energy efficient chip multiprocessor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "117--128",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Coons:2006:SPS,
  author =       "Katherine E. Coons and Xia Chen and Doug Burger and
                 Kathryn S. McKinley and Sundeep K. Kushwaha",
  title =        "A spatial path scheduling algorithm for {EDGE}
                 architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "129--140",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mercaldi:2006:IST,
  author =       "Martha Mercaldi and Steven Swanson and Andrew Petersen
                 and Andrew Putnam and Andrew Schwerin and Mark Oskin
                 and Susan J. Eggers",
  title =        "Instruction scheduling for a tiled dataflow
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "141--150",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gordon:2006:ECG,
  author =       "Michael I. Gordon and William Thies and Saman
                 Amarasinghe",
  title =        "Exploiting coarse-grained task, data, and pipeline
                 parallelism in stream programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "151--162",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mishra:2006:TES,
  author =       "Mahim Mishra and Timothy J. Callahan and Tiberiu
                 Chelcea and Girish Venkataramani and Seth C. Goldstein
                 and Mihai Budiu",
  title =        "{Tartan}: evaluating spatial computation for whole
                 program execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "163--174",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Eyerman:2006:PCA,
  author =       "Stijn Eyerman and Lieven Eeckhout and Tejas Karkhanis
                 and James E. Smith",
  title =        "A performance counter architecture for computing
                 accurate {CPI} components",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "175--184",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lee:2006:AER,
  author =       "Benjamin C. Lee and David M. Brooks",
  title =        "Accurate and efficient regression modeling for
                 microarchitectural performance and power prediction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "185--194",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ipek:2006:EEA,
  author =       "Engin {\"I}pek and Sally A. McKee and Rich Caruana and
                 Bronis R. de Supinski and Martin Schulz",
  title =        "Efficiently exploring architectural design spaces via
                 predictive modeling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "195--206",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kharbutli:2006:CEP,
  author =       "Mazen Kharbutli and Xiaowei Jiang and Yan Solihin and
                 Guru Venkataramani and Milos Prvulovic",
  title =        "Comprehensively and efficiently protecting the heap",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "207--218",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chilimbi:2006:HIH,
  author =       "Trishul M. Chilimbi and Vinod Ganapathy",
  title =        "{HeapMD}: identifying heap-based bugs using anomaly
                 detection",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "219--228",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Narayanasamy:2006:RSM,
  author =       "Satish Narayanasamy and Cristiano Pereira and Brad
                 Calder",
  title =        "Recording shared memory dependencies using strata",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "229--240",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Patwardhan:2006:DTS,
  author =       "Jaidev P. Patwardhan and Vijeta Johri and Chris Dwyer
                 and Alvin R. Lebeck",
  title =        "A defect tolerant self-organizing nanoscale {SIMD}
                 architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "241--251",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Schuchman:2006:PTA,
  author =       "Ethan Schuchman and T. N. Vijaykumar",
  title =        "A program transformation and architecture support for
                 quantum uncomputation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "252--263",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Mysore:2006:IC,
  author =       "Shashidhar Mysore and Banit Agrawal and Navin
                 Srivastava and Sheng-Chih Lin and Kaustav Banerjee and
                 Tim Sherwood",
  title =        "Introspective {$3$D} chips",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "264--273",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cantin:2006:SP,
  author =       "Jason F. Cantin and Mikko H. Lipasti and James E.
                 Smith",
  title =        "Stealth prefetching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "274--282",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chakraborty:2006:CSE,
  author =       "Koushik Chakraborty and Philip M. Wells and Gurindar
                 S. Sohi",
  title =        "Computation spreading: employing hardware migration to
                 specialize {CMP} cores on-the-fly",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "283--292",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Miller:2006:SBI,
  author =       "Jason E. Miller and Anant Agarwal",
  title =        "Software-based instruction caching for embedded
                 processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "293--302",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Li:2006:MEM,
  author =       "Xin Li and Marian Boldt and Reinhard von Hanxleden",
  title =        "Mapping {Esterel} onto a multi-threaded embedded
                 processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "303--314",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Binkert:2006:INI,
  author =       "Nathan L. Binkert and Ali G. Saidi and Steven K.
                 Reinhardt",
  title =        "Integrated network interfaces for high-bandwidth
                 {TCP\slash IP}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "315--324",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tarditi:2006:AUD,
  author =       "David Tarditi and Sidd Puri and Jose Oglesby",
  title =        "{Accelerator}: using data parallelism to program
                 {GPUs} for general-purpose uses",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "325--335",
  month =        dec,
  year =         "2006",
  CODEN =        "OSRED8",
  DOI =          "https://doi.org/10.1145/1168857.1168898",
  ISSN =         "0163-5980",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "GPUs are difficult to program for general-purpose
                 uses. Programmers can either learn graphics APIs and
                 convert their applications to use graphics pipeline
                 operations or they can use stream programming
                 abstractions of GPUs. We describe Accelerator, a system
                 that uses data parallelism to program GPUs for
                 general-purpose uses instead. Programmers use a
                 conventional imperative programming language and a
                 library that provides only high-level data-parallel
                 operations. No aspects of GPUs are exposed to
                 programmers. The library implementation compiles the
                 data-parallel operations on the fly to optimized GPU
                 pixel shader code and API calls. We describe the
                 compilation techniques used to do this. We evaluate the
                 effectiveness of using data parallelism to program GPUs
                 by providing results for a set of compute-intensive
                 benchmarks. We compare the performance of Accelerator
                 versions of the benchmarks against hand-written pixel
                 shaders. The speeds of the Accelerator versions are
                 typically within 50\% of the speeds of hand-written
                 pixel shader code. Some benchmarks significantly
                 outperform C versions on a CPU: they are up to 18 times
                 faster than C code running on a CPU.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Damron:2006:HTM,
  author =       "Peter Damron and Alexandra Fedorova and Yossi Lev",
  title =        "Hybrid transactional memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "336--346",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chuang:2006:UPB,
  author =       "Weihaw Chuang and Satish Narayanasamy and Ganesh
                 Venkatesh and Jack Sampson and Michael {Van Biesbrouck}
                 and Gilles Pokam and Brad Calder and Osvaldo Colavin",
  title =        "Unbounded page-based transactional memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "347--358",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Moravan:2006:SNT,
  author =       "Michelle J. Moravan and Jayaram Bobba and Kevin E.
                 Moore and Luke Yen and Mark D. Hill and Ben Liblit and
                 Michael M. Swift and David A. Wood",
  title =        "Supporting nested transactional memory in {logTM}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "359--370",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chung:2006:TTM,
  author =       "JaeWoong Chung and Chi Cao Minh and Austen McDonald
                 and Travis Skare and Hassan Chafi and Brian D.
                 Carlstrom and Christos Kozyrakis and Kunle Olukotun",
  title =        "Tradeoffs in transactional memory virtualization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "371--381",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kawahito:2006:NIR,
  author =       "Motohiro Kawahito and Hideaki Komatsu and Takao
                 Moriyama and Hiroshi Inoue and Toshio Nakatani",
  title =        "A new idiom recognition framework for exploiting
                 hardware-assist instructions",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "382--393",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bansal:2006:AGP,
  author =       "Sorav Bansal and Alex Aiken",
  title =        "Automatic generation of peephole superoptimizers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "394--403",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Solar-Lezama:2006:CSF,
  author =       "Armando Solar-Lezama and Liviu Tancau and Rastislav
                 Bodik and Sanjit Seshia and Vijay Saraswat",
  title =        "Combinatorial sketching for finite programs",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "404--415",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{DaSilva:2006:PPA,
  author =       "Jeff {Da Silva} and J. Gregory Steffan",
  title =        "A probabilistic pointer analysis for speculative
                 optimizations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "34",
  number =       "5",
  pages =        "416--425",
  month =        dec,
  year =         "2006",
  CODEN =        "CANED2",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Oct 27 06:18:30 MDT 2006",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tullsen:2007:ISI,
  author =       "Dean Tullsen and Rakesh Kumar and Norman P. Jouppi",
  title =        "Introduction to the special issue on the {2006
                 Workshop on Design, Analysis, and Simulation of Chip
                 Multiprocessors: (dasCMP'06)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "2--2",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241605",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Chip multiprocessor architectures are becoming
                 increasingly attractive as an option to provide high
                 instruction throughput while keeping power and
                 complexity under control. Such architectures have also
                 been shown to have scalability and productivity
                 advantages. Multi-core processors are fast becoming
                 mainstream.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "{DASCMP'06}",
}

@Article{Mahesri:2007:HSS,
  author =       "Aqeel Mahesri and Nicholas J. Wang and Sanjay J.
                 Patel",
  title =        "Hardware support for software controlled
                 multithreading",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "3--12",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241606",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Chip multi-processors have emerged as one of the most
                 effective uses of the huge number of transistors
                 available today and in the future, but questions remain
                 as to the best way to leverage CMPs to accelerate
                 single threaded applications. Previous approaches rely
                 on significant speculation to accomplish this goal. Our
                 proposal, NXA, is less speculative than previous
                 proposals, relying heavily on software to guarantee
                 thread correctness, though still allowing parallelism
                 in the presence of ambiguous dependences. It divides a
                 single thread of execution into multiple using the
                 master-worker paradigm where some set of master threads
                 execute code that spawns tasks for other, worker
                 threads. The master threads generally consist of
                 performance critical instructions that can prefetch
                 data, compute critical control decisions, or compute
                 performance critical dataflow slices. This prevents
                 non-critical instructions from competing with critical
                 instructions for processor resources, allowing the
                 critical thread (and thus the workload) to complete
                 faster. Empirical results from performance simulation
                 show a 20\% improvement in performance on a 2-way CMP
                 machine, demonstrating that software controlled
                 multithreading can indeed provide a benefit in the
                 presence of hardware support.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "{DASCMP'06}",
}

@Article{Shi:2007:CCP,
  author =       "Xudong Shi and Feiqi Su and Jih-kwon Peir and Ye Xia
                 and Zhen Yang",
  title =        "{CMP} cache performance projection: accessibility vs.
                 capacity",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "13--20",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241607",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Efficient utilizing on-chip storage space on
                 Chip-Multiprocessors (CMPs) has become an important
                 research topic. Tradeoffs between data accessibility
                 and effective on-chip capacity have been studied
                 extensively. It requires costly simulations to
                 understand a wide-spectrum of the design space. In this
                 paper, we first develop an abstract model for
                 understanding the performance impact with respect to
                 data replication. To overcome the lack of real-time
                 interactions among multiple cores in the abstract
                 model, we propose a global stack simulation strategy to
                 study the performance of a variety of cache
                 organizations on CMPs. The global stack logically
                 incorporates a shared stack and per-core private stacks
                 to collect shared/private reuse (stack) distances for
                 every memory reference in a single simulation pass.
                 With the collected reuse distances, performance in
                 terms of hits/misses and average memory access times
                 can be calculated for various cache organizations. We
                 verify the stack results against individual
                 execution-driven simulations that consider realistic
                 cache parameters and delays using a set of commercial
                 multithreaded workloads. The results show that stack
                 simulations can accurately model the performance of
                 various cache organizations. The single-pass stack
                 simulation results demonstrate that the effectiveness
                 of various techniques for optimizing the CMP on-chip
                 storage is closely related to the working sets of the
                 workloads as well as to the total cache sizes.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "CMP caches; data replication; performance modeling and
                 projection; stack simulation",
  remark =       "{DASCMP'06}",
}

@Article{Guo:2007:CQC,
  author =       "Fei Guo and Hari Kannan and Li Zhao and Ramesh
                 Illikkal and Ravi Iyer and Don Newell and Yan Solihin
                 and Christos Kozyrakis",
  title =        "From chaos to {QoS}: case studies in {CMP} resource
                 management",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "21--30",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241608",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "As more and more cores are enabled on the die of
                 future CMP platforms, we expect that several diverse
                 workloads will run simultaneously on the platform. A
                 key example of this trend is the growth of
                 virtualization usage models. When multiple virtual
                 machines or applications or threads run simultaneously,
                 the quality of service (QoS) that the platform provides
                 to each individual thread is non-deterministic today.
                 This occurs because the simultaneously running threads
                 place very different demands on the shared resources
                 (cache space, memory bandwidth, etc) in the platform
                 and in most cases contend with each other. In this
                 paper, we first present case studies that show how this
                 results in non-deterministic performance. Unlike the
                 compute resources managed through scheduling, platform
                 resource allocation to individual threads cannot be
                 controlled today. In order to provide better
                 determinism and QoS, we then examine resource
                 management mechanisms and present QoS-aware
                 architectures and execution environments. The main
                 contribution of this paper is the architecture
                 feasibility analysis through prototypes that allow
                 experimentation with QoS-Aware execution environments
                 and architectural resources. We describe these QoS
                 prototypes and then present preliminary case studies of
                 multi-tasking and virtualization usage models sharing
                 one critical CMP resource (last-level cache). We then
                 demonstrate how proper management of the cache resource
                 can provide service differentiation and deterministic
                 performance behavior when running disparate workloads
                 in future CMP platforms.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "{DASCMP'06}",
}

@Article{Kondo:2007:IFT,
  author =       "Masaaki Kondo and Hiroshi Sasaki and Hiroshi
                 Nakamura",
  title =        "Improving fairness, throughput and energy-efficiency
                 on a chip multiprocessor through {DVFS}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "31--38",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241609",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Recently, a single chip multiprocessor (CMP) is
                 becoming an attractive architecture for improving
                 throughput of program execution. In CMPs, multiple
                 processor cores share several hardware resources such
                 as cache memory and memory bus. Therefore, the resource
                 contention significantly degrades performance of each
                 thread and also loses fairness between threads.\par

                 In this paper, we propose a Dynamic Frequency and
                 Voltage Scaling (DVFS) algorithm for improving total
                 instruction throughput, fairness, and energy efficiency
                 of CMPs. The proposed technique periodically observes
                 the utilization ratio of shared resources and controls
                 the frequency and the voltage of each processor core
                 individually to balance the ratio between threads. We
                 evaluate our technique and the evaluation results show
                 that fairness between threads are greatly improved by
                 the technique. Moreover, the total instruction
                 throughput increases in many cases while reducing
                 energy consumption.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "{DASCMP'06}",
}

@Article{Waliullah:2007:SFC,
  author =       "M. M. Waliullah and Per Stenstrom",
  title =        "Starvation-free commit arbitration policies for
                 transactional memory systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "39--46",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241610",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In transactional memory systems like TCC, unordered
                 transactions are committed on a first-come, first-serve
                 basis. If a transaction has read data that has been
                 modified by the next transaction to commit, it will
                 have to roll-back and a lot of computations can
                 potentially be wasted. Even worse, such simple commit
                 arbitration policies are prone to starvation; in fact,
                 the performance of Raytrace in SPLASH-2 suffered
                 significantly because of this.\par

                 This paper analyzes in detail the design issues for
                 commit arbitration policies and proposes novel policies
                 that reduce the amount of wasted computation due to
                 roll-back and, most importantly, avoid starvation. We
                 analyze in detail how to incorporate them in a TCC-like
                 transactional memory protocol. We find that our
                 proposed schemes have no impact on the common-case
                 performance. In addition, they add modest complexity to
                 the baseline protocol.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "{DASCMP'06}",
}

@Article{Ferri:2007:HSF,
  author =       "Cesare Ferri and Tali Moreshet and R. Iris Bahar and
                 Luca Benini and Maurice Herlihy",
  title =        "A hardware\slash software framework for supporting
                 transactional memory in a {MPSoC} environment",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "47--54",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241611",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Manufacturers are focusing on
                 multiprocessor-system-on-a-chip (MPSoC) architectures
                 in order to provide increased concurrency, rather than
                 increased clock speed, for both large-scale as well as
                 embedded systems. Traditionally lock-based
                 synchronization is provided to support concurrency;
                 however, managing locks can be very difficult and error
                 prone. In addition, the performance and power cost of
                 lock-based synchronization can be high. Transactional
                 memories have been extensively investigated as an
                 alternative to lock-based synchronization in
                 general-purpose systems. It has been shown that
                 transactional memory has advantages over locks in terms
                 of ease of programming, performance and energy
                 consumption. However, their applicability to embedded
                 multi-core platforms has not been explored yet. In this
                 paper, we demonstrate a complete hardware transactional
                 memory solution for an embedded multi-core
                 architecture, consisting of a cache-coherent ARM-based
                 cluster, similar to ARM's MPCore. Using cycle accurate
                 power and performance models for the transactional
                 memory hardware, we evaluate our architectural
                 framework over a set of different system and
                 application settings, and show that transactional
                 memory is a promising solution, even for
                 resource-constrained embedded multiprocessors.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "{DASCMP'06}",
}

@Article{Rul:2007:FLP,
  author =       "Sean Rul and Hans Vandierendonck and Koen {De
                 Bosschere}",
  title =        "Function level parallelism driven by data
                 dependencies",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "55--62",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241612",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "With the rise of Chip multiprocessors (CMPs), the
                 amount of parallel computing power will increase
                 significantly in the near future. However, most
                 programs are sequential in nature and have not been
                 explicitly parallelized, so they cannot exploit these
                 parallel resources. Automatic parallelization of
                 sequential, non-regular codes is very hard, as
                 illustrated by the lack of solutions after more than 30
                 years of research on the topic. The question remains if
                 there is parallelism in sequential programs that can be
                 detected automatically and if so, how much parallelism
                 there is.\par

                 In this paper, we propose a framework for extracting
                 potential parallelism from programs. Applying this
                 framework to sequential programs can teach us how much
                 parallelism is present in a program, but also tells us
                 what the most appropriate parallel construct for a
                 program is, e.g. a pipeline, master/slave work
                 distribution, etc.\par

                 Our framework is profile-based, implying that it is not
                 safe. It builds two new graph representations of the
                 profile-data: the interprocedural data flow graph and
                 the data sharing graph. This graphs show the data-flow
                 between functions and the data structures facilitating
                 this data-flow, respectively.\par

                 We apply our framework on the SPECcpu2000 bzip2
                 benchmark, achieving a speedup of 3.74 of the
                 compression part and a global speedup of 2.45 on a quad
                 processor system.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "{DASCMP'06}",
}

@Article{Henning:2007:GEI,
  author =       "John L. Henning",
  title =        "{Guest editor}'s introduction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "63--64",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241614",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "During the development of the new benchmark suite
                 CPU2006, SPEC analyzed benchmark candidates for various
                 technical attributes, including time profiles, language
                 standard compliance, I/O activity, system resource
                 usage, and many other attributes. Many people
                 contributed to the analysis, as shown in the credits at
                 www.spec.org/cpu2006/docs/credits.html. This issue of
                 Computer Architecture News presents a set of articles
                 flowing from that analysis effort.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Henning:2007:SCS,
  author =       "John L. Henning",
  title =        "{SPEC CPU} suite growth: an historical perspective",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "65--68",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241615",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Since 1989, the SPEC CPU benchmarks have aspired to
                 ambitious goals: fair, portable, comparable tests using
                 the compute-intensive portion of real applications. It
                 may be difficult today to remember just how much of a
                 challenge these goals presented when SPEC was first
                 founded, or how much of a break they were from previous
                 industry practice.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Phansalkar:2007:SSC,
  author =       "Aashish Phansalkar and Ajay Joshi and Lizy K. John",
  title =        "Subsetting the {SPEC CPU2006} benchmark suite",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "69--76",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241616",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "On August 24, 2006, the Standard Performance
                 Evaluation Corporation (SPEC) announced CPU2006 -- the
                 next generation of industry-standardized CPU-intensive
                 benchmark suite. The SPEC CPU benchmark suite has
                 become the most frequently used suite for
                 simulation-based computer architecture research.
                 Detailed processor simulators take days to weeks to
                 simulate each of the SPEC CPU programs. In order to
                 reduce simulation to a tractable time, architects and
                 researchers often use only a subset of benchmarks from
                 the SPEC CPU suite to evaluate the potential of their
                 ideas. Prior research has demonstrated that statistical
                 techniques are most effective to find a representative
                 subset of benchmark programs from a benchmark suite.
                 The objective of this paper is to apply multivariate
                 statistical data analysis techniques for selecting a
                 representative subset of programs from the SPEC CPU2006
                 benchmark suite. We measure a set of performance
                 counter based characteristics for the SPEC CPU2006
                 programs across a large number of architectures and
                 apply multivariate statistical analysis techniques to
                 find a representative subset of benchmarks and
                 representative input sets wherever multiple input sets
                 are provided. The results from this paper will help
                 architects and researchers to find a smaller but
                 representative set of programs from the SPEC CPU2006
                 benchmark suite, when time or resource constraints
                 prohibit experimentation with the entire benchmark
                 suite.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Wong:2007:CBS,
  author =       "Michael Wong",
  title =        "{C++} benchmarks in {SPEC CPU2006}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "77--83",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241617",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In SPEC CPU2006, there are three C++ integer
                 benchmarks and four floating-point C++ benchmarks. This
                 paper describes the work of incorporating C++
                 benchmarks into SPEC CPU2006. It describes the base
                 language standard supported and the basis for run rules
                 adopted to maintain an even playing field for different
                 compilers. It also describes issues that complicate
                 porting C++ benchmarks. It describes some of the C++
                 Standard compliance issues that were technically
                 interesting during the benchmark development phase,
                 using as examples the behavior of const-correctness,
                 nested class access of private member of enclosing
                 class, and unneeded template instantiations.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Henning:2007:SCM,
  author =       "John L. Henning",
  title =        "{SPEC CPU2006} memory footprint",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "84--89",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241618",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The nominal goal for memory consumption by SPEC
                 CPU2006 benchmarks is up to about 900 MB when compiled
                 with 32-bit pointers. The 900 MB maximum was chosen so
                 that a system with 1GB will have about 100MB available
                 for the operating system and overhead processes. By
                 comparison, the goal for SPEC CPU2000 was 200MB [1].",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gove:2007:CWS,
  author =       "Darryl Gove",
  title =        "{CPU2006} working set size",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "90--96",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241619",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "SPEC CPU2000 had a target memory footprint of 200 MB
                 for the benchmarks [1], to enable the suite to run on
                 machines with 256 MB of memory. Six years have elapsed
                 since the release of that suite, and in that time
                 memory sizes have increased significantly, so the
                 memory requirements for the recently released CPU2006
                 reflect this. CPU2006 has been targeted to have a
                 benchmark memory footprint of about 900MB, allowing the
                 suite to run on machines with 1GB of memory.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Korn:2007:SCS,
  author =       "Wendy Korn and Moon S. Chang",
  title =        "{SPEC CPU2006} sensitivity to memory page sizes",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "97--101",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241620",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "SPEC CPU2006 is a compute-intensive industry standard
                 benchmark suite published in August 2006. This paper
                 characterizes the memory access behavior of SPEC
                 CPU2006 running on IBM POWER5+ microprocessors. We
                 measure the maximum and average memory usage of the
                 benchmarks to validate SPEC's memory requirement
                 criteria. This paper also analyzes how different page
                 sizes affect the performance of the benchmarks. The
                 experiment reveals that 64 KB and 16 MB pages improve
                 the performance up to 46.9\% and 50.9\%,
                 respectively.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "CPI analysis; large page size; memory usage;
                 performance optimization; SPEC CPU2006 benchmarks;
                 workload characterization",
}

@Article{Weicker:2007:SPR,
  author =       "Reinhold P. Weicker and John L. Henning",
  title =        "Subroutine profiling results for the {CPU2006}
                 benchmarks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "102--111",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241621",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Subroutine profiling is a well-known performance tool.
                 For application or system programmers, it determines
                 'hot spots' where the program spends most of its time,
                 and where careful rewriting can most help performance.
                 For compiler authors, it can give information about
                 programming style in such hot spots, and can indicate
                 where compiler improvements may be useful. For hardware
                 designers and analysts, it can be the starting point to
                 explain performance behavior.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ye:2007:CFA,
  author =       "Dong Ye and Joydeep Ray and David Kaeli",
  title =        "Characterization of file {I/O} activity for {SPEC
                 CPU2006}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "112--117",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241622",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "SPEC CPU2006 is a compute-intensive benchmark suite
                 designed to stress a computer system's processor,
                 memory subsystem, and compiler. To construct this
                 suite, SPEC has selected benchmarks that are derived
                 from real world applications. When run with their
                 reference inputs, these programs place a significant
                 computational burden on today's mainstream desktops as
                 well as high-end workstations and servers.\par

                 For these applications to thoroughly exercise the
                 merits of a particular processor/memory design point,
                 it is necessary to limit the amount of I/O activity
                 generated. Since these applications come from real
                 world applications, the suite developers have
                 considered how best to limit the amount of file-based
                 I/O activity present in these applications. This paper
                 presents the characteristics of file I/O activity in
                 the resulting suite and its overall impact on the
                 performance of these applications. We also report on
                 some of the choices SPEC has made in order to reduce
                 the file I/O activity in some specific programs of the
                 suite.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Henning:2007:PCD,
  author =       "John L. Henning",
  title =        "Performance counters and development of {SPEC
                 CPU2006}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "118--121",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241623",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Performance counters provide the means to track
                 detailed events that occur on a CPU chip. These events
                 are of interest to both performance analysts and
                 compiler developers. Counting them provides essential
                 clues to guide performance improvement. For example, a
                 tester who sees that a program has a high cache miss
                 rate on a particular system may experiment with
                 compilation options that improve prefetching. A
                 compiler developer who sees the same thing may realize
                 that the code generator's machine model is missing some
                 crucial detail of behavior on that particular system.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gove:2007:ECB,
  author =       "Darryl Gove and Lawrence Spracklen",
  title =        "Evaluating the correspondence between training and
                 reference workloads in {SPEC CPU2006}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "122--129",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241624",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Profile feedback (sometimes called Feedback Directed
                 Optimisation FDO) is a useful technique for providing
                 the compiler with additional information about runtime
                 program flow. The compiler is able to use this
                 information to make optimisation decisions that improve
                 the way the code is laid out in memory or determine
                 which routines are inlined, and hence improve the
                 performance of the application.\par

                 The use of profile feedback requires the code to be
                 compiled twice. The first time the compiler generates
                 an instrumented version of the application. This
                 instrumented version is then run on one or more
                 'representative' training workloads to gather profile
                 data. This profile data contains information such as
                 how many times each routine is executed and how
                 frequently each branch is taken. The second pass
                 through the compiler uses this information to make more
                 enlightened optimisation decisions.\par

                 The quality of the training data impacts the ability of
                 the compiler to do the best job that it can. This paper
                 discusses a method of assessing the similarity of the
                 training workload to the reference workload, and
                 applies this methodology to evaluate the training
                 workloads in the SPEC CPU2006 benchmark suite.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Spradling:2007:SCB,
  author =       "Cloyce D. Spradling",
  title =        "{SPEC CPU2006} benchmark tools",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "130--134",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241625",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The benchmarks that make up the SPEC CPU2006 benchmark
                 suite are set-up, run, timed, and scored by the CPU
                 tools harness. The tools have evolved over time from a
                 collection of edit-it-yourself makefiles, scripts, and
                 an Excel spreadsheet to the current Perl-based suite.
                 The basic purpose of the tools is to make life easier
                 for the benchmarker; they make it easier to tweak
                 compilation settings, easier to keep track of those
                 settings, and most importantly, they make it easier to
                 follow the run and reporting rules.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sridhar:2007:HLO,
  author =       "Swaroop Sridhar and Jonathan S. Shapiro and Prashanth
                 P. Bungale",
  title =        "{HDTrans}: a low-overhead dynamic translator",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "135--140",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241602",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Dynamic translation is a general purpose tool used for
                 instrumenting programs at run time. Many current
                 translators perform substantial rewriting during
                 translation in an attempt to reduce execution time.
                 When dynamic translation is used as a ubiquitous policy
                 enforcement mechanism, the majority of program
                 executions have no dominating inner loop that can be
                 used to amortize the cost of translation. Even under
                 more favorable usage assumptions, our measurements show
                 that such optimizations offer no significant benefit in
                 most cases. A simpler, more maintainable, adaptable,
                 and smaller translator may be preferable to more
                 complicated designs.\par

                 In this paper, we present HDTrans, a light-weight IA-32
                 to IA-32 binary translation system that uses some
                 simple and effective translation techniques in
                 combination with established trace linearization and
                 code caching optimizations. We also present an
                 evaluation of translation overhead under non-ideal
                 conditions, showing that conventional benchmarks do not
                 provide a good prediction of translation overhead when
                 used pervasively.\par

                 A further contribution of this paper is an analysis of
                 the effectiveness of post-compile static
                 pre-translation techniques for overhead reduction. Our
                 results indicate that static pre-translation is
                 effective only when expensive instrumentation or
                 optimization is performed, and that efficient reload of
                 pre-translated code incurs a substantial execution-time
                 penalty.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yan:2007:HMC,
  author =       "Jun Yan and Wei Zhang",
  title =        "Hybrid multi-core architecture for boosting
                 single-threaded performance",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "141--148",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241603",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The scaling of technology and the diminishing return
                 of complicated uniprocessors have driven the industry
                 towards multicore processors. While multithreaded
                 applications can naturally leverage the enhanced
                 throughput of multi-core processors, a large number of
                 important applications are single-threaded, which
                 cannot automatically harness the potential of
                 multi-core processors. In this paper, we propose a
                 compiler-driven heterogeneous multicore architecture,
                 consisting of tightly-integrated VLIW (Very Long
                 Instruction Word) and superscalar processors on a
                 single chip, to automatically boost the performance of
                 single-threaded applications without compromising the
                 capability to support multithreaded programs. In the
                 proposed multi-core architecture, while the
                 high-performance VLIW core is used to run code segments
                 with high instruction-level parallelism (ILP) extracted
                 by the compiler; the superscalar core can be exploited
                 to deal with the runtime events that are typically
                 difficult for the VLIW core to handle, such as L2 cache
                 misses. Our initial experimental results by running the
                 preexecution thread on the superscalar core to mitigate
                 the L2 cache misses of the main thread on the VLIW core
                 indicate that the proposed VLIW/superscalar multi-core
                 processor can automatically improve the performance of
                 single-threaded general-purpose applications by up to
                 40.8\%.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2007:INa,
  author =       "Mark Thorson",
  title =        "{Internet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "1",
  pages =        "149--154",
  month =        mar,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1241601.1241627",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:47:26 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This column consists of selected traffic from the
                 comp.arch newsgroup, a forum for discussion of computer
                 architecture on the Internet---an international
                 computer network.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Shaw:2007:ASP,
  author =       "David E. Shaw and Martin M. Deneroff and Ron O. Dror
                 and Jeffrey S. Kuskin and Richard H. Larson and John K.
                 Salmon and Cliff Young and Brannon Batson and Kevin J.
                 Bowers and Jack C. Chao and Michael P. Eastwood and
                 Joseph Gagliardo and J. P. Grossman and C. Richard Ho
                 and Douglas J. Ierardi and Istv{\'a}n Kolossv{\'a}ry
                 and John L. Klepeis and Timothy Layman and Christine
                 McLeavey and Mark A. Moraes and Rolf Mueller and Edward
                 C. Priest and Yibing Shan and Jochen Spengler and
                 Michael Theobald and Brian Towles and Stanley C. Wang",
  title =        "{Anton}, a special-purpose machine for molecular
                 dynamics simulation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "1--12",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250664",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The ability to perform long, accurate molecular
                 dynamics (MD) simulations involving proteins and other
                 biological macro-molecules could in principle provide
                 answers to some of the most important currently
                 outstanding questions in the fields of biology,
                 chemistry and medicine. A wide range of biologically
                 interesting phenomena, however, occur over time scales
                 on the order of a millisecond--about three orders of
                 magnitude beyond the duration of the longest current MD
                 simulations.\par

                 In this paper, we describe a massively parallel machine
                 called Anton, which should be capable of executing
                 millisecond-scale classical MD simulations of such
                 biomolecular systems. The machine, which is scheduled
                 for completion by the end of 2008, is based on 512
                 identical MD-specific ASICs that interact in a tightly
                 coupled manner using a specialized high-speed
                 communication network. Anton has been designed to use
                 both novel parallel algorithms and special-purpose
                 logic to dramatically accelerate those calculations
                 that dominate the time required for a typical MD
                 simulation. The remainder of the simulation algorithm
                 is executed by a programmable portion of each chip that
                 achieves a substantial degree of parallelism while
                 preserving the flexibility necessary to accommodate
                 anticipated advances in physical models and simulation
                 methods.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "bioinformatics; biomolecular system simulation;
                 computational biology; computational drug design;
                 molecular dynamics; protein folding; protein structure;
                 special-purpose machine",
}

@Article{Fan:2007:PPW,
  author =       "Xiaobo Fan and Wolf-Dietrich Weber and Luiz Andre
                 Barroso",
  title =        "Power provisioning for a warehouse-sized computer",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "13--23",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250665",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Large-scale Internet services require a computing
                 infrastructure that can be appropriately described as a
                 warehouse-sized computing system. The cost of building
                 datacenter facilities capable of delivering a given
                 power capacity to such a computer can rival the
                 recurring energy consumption costs themselves.
                 Therefore, there are strong economic incentives to
                 operate facilities as close as possible to maximum
                 capacity, so that the non-recurring facility costs can
                 be best amortized. That is difficult to achieve in
                 practice because of uncertainties in equipment power
                 ratings and because power consumption tends to vary
                 significantly with the actual computing activity.
                 Effective power provisioning strategies are needed to
                 determine how much computing equipment can be safely
                 and efficiently hosted within a given power
                 budget.\par

                 In this paper we present the aggregate power usage
                 characteristics of large collections of servers (up to
                 15 thousand) for different classes of applications over
                 a period of approximately six months. Those
                 observations allow us to evaluate opportunities for
                 maximizing the use of the deployed power capacity of
                 datacenters, and assess the risks of over-subscribing
                 it. We find that even in well-tuned applications there
                 is a noticeable gap (7 - 16\%)between achieved and
                 theoretical aggregate peak power usage at the cluster
                 level (thousands of servers). The gap grows to almost
                 40\% in whole datacenters. This headroom can be used to
                 deploy additional compute equipment within the same
                 power budget with minimal risk of exceeding it. We use
                 our modeling framework to estimate the potential of
                 power management schemes to reduce peak power and
                 energy usage. We find that the opportunities for power
                 and energy savings are significant, but greater at the
                 cluster-level (thousands of servers) than at the
                 rack-level (tens). Finally we argue that systems need
                 to be power efficient across the activity range, and
                 not only at peak performance levels.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "energy efficiency; power modeling; power
                 provisioning",
}

@Article{Blundell:2007:MFC,
  author =       "Colin Blundell and Joe Devietti and E. Christopher
                 Lewis and Milo M. K. Martin",
  title =        "Making the fast case common and the uncommon case
                 simple in unbounded transactional memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "24--34",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250667",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Hardware transactional memory has great potential to
                 simplify the creation of correct and efficient
                 multithreaded programs, allowing programmers to exploit
                 more effectively the soon-to-be-ubiquitous multi-core
                 designs. Several recent proposals have extended the
                 original bounded transactional memory to unbounded
                 transactional memory, a crucial step toward
                 transactions becoming a general-purpose primitive.
                 Unfortunately, supporting the concurrent execution of
                 an unbounded number of unbounded transactions is
                 challenging, and as a result, many proposed
                 implementations are complex.\par

                 This paper explores a different approach. First, we
                 introduce the permissions-only cache to extend the
                 bound at which transactions overflow to allow the fast,
                 bounded case to be used as frequently as possible.
                 Second, we propose OneTM to simplify the implementation
                 of unbounded transactional memory by bounding the
                 concurrency of transactions that overflow the cache.
                 These mechanisms work synergistically to provide a
                 simple and fast unbounded transactional memory
                 system.\par

                 The permissions-only cache efficiently maintains the
                 coherence permissions --- but not data-for blocks read
                 or written transactionally that have been evicted from
                 the processor's caches. By holding coherence
                 permissions for these blocks, the regular cache
                 coherence protocol can be used to detect transactional
                 conflicts using only a few bits of on-chip storage per
                 overflowed cache block. OneTM allows only one
                 overflowed transaction at a time, relying on the
                 permissions-only cache to ensure that overflow is
                 infrequent. We present two implementations. In
                 OneTM-Serialized, an overflowed transaction simply
                 stalls all other threads in the application.\par

                 In OneTM-Concurrent, non-overflowed transactions and
                 non-transactional code can execute concurrently with
                 the overflowed transaction, providing more concurrency
                 while retaining OneTM's core simplifying assumption.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "concurrency; parallel programming; transactional
                 memory; transactions",
}

@Article{Zhu:2007:SSB,
  author =       "Weirong Zhu and Vugranam C. Sreedhar and Ziang Hu and
                 Guang R. Gao",
  title =        "Synchronization state buffer: supporting efficient
                 fine-grain synchronization on many-core architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "35--45",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250668",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Efficient fine-grain synchronization is extremely
                 important to effectively harness the computational
                 power of many-core architectures. However, designing
                 and implementing fine-grain synchronization in such
                 architectures presents several challenges, including
                 issues of synchronization induced overhead, storage
                 cost, scalability, and the level of granularity to
                 which synchronization is applicable. This paper
                 proposes the Synchronization State Buffer ( SS B), a
                 scalable architectural design for fine-grain
                 synchronization that efficiently performs
                 synchronizations between concurrent threads. The design
                 of SSB is motivated by the following observation: at
                 any instance during the parallel execution only a small
                 fraction of memory locations are actively participating
                 in synchronization. Based on this observation we
                 present a fine-grain synchronization design that
                 records and manages the states of frequently
                 synchronized data using modest hardware support. We
                 have implemented the SSB design in the context of the
                 160-core IBM Cyclops-64 architecture. Using detailed
                 simulation, we present our experience for a set of
                 benchmarks with different workload characteristics.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "fine-grain synchronization; many-core; SSB",
}

@Article{Marty:2007:VHS,
  author =       "Michael R. Marty and Mark D. Hill",
  title =        "Virtual hierarchies to support server consolidation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "46--56",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250670",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Server consolidation is becoming an increasingly
                 popular technique to manage and utilize systems. This
                 paper develops CMP memory systems for server
                 consolidation where most sharing occurs within Virtual
                 Machines (VMs). Our memory systems maximize shared
                 memory accesses serviced within a VM, minimize
                 interference among separate VMs, facilitate dynamic
                 reassignment of VMs to processors and memory, and
                 support content-based page sharing among VMs. We begin
                 with a tiled architecture where each of 64 tiles
                 contains a processor, private L1 caches, and an L2
                 bank. First, we reveal why single-level directory
                 designs fail to meet workload consolidation goals.
                 Second, we develop the paper's central idea of imposing
                 a two-level virtual (or logical) coherence hierarchy on
                 a physically flat CMP that harmonizes with VM
                 assignment. Third, we show that the best of our two
                 virtual hierarchy (VH) variants performs 12-58\% better
                 than the best alternative flat directory protocol when
                 consolidating Apache, OLTP, and Zeus commel workloads
                 on our simulated 64-core CMP.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "cache coherence; chip multiprocessors (CMPs); memory
                 hierarchies; multicore; partitioning; server
                 consolidation; virtual machines",
}

@Article{Nesbit:2007:VPC,
  author =       "Kyle J. Nesbit and James Laudon and James E. Smith",
  title =        "Virtual private caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "57--68",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250671",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Virtual Private Machines (VPM) provide a framework for
                 Quality of Service (QoS) in CMP-based computer systems.
                 VPMs incorporate microarchitecture mechanisms that
                 allow shares of hardware resources to be allocated to
                 executing threads, thus providing applications with an
                 upper bound on execution time regardless of other
                 thread activity. Virtual Private Caches (VPCs) are an
                 important element of VPMs. VPC hardware consists of two
                 major components: the VPC Arbiter, which manages shared
                 cache bandwidth, and the VPC Capacity Manager, which
                 manages the cache storage. Both the VPC Arbiter and VPC
                 Capacity Manager provide minimum service guarantees
                 that, when combined, achieve QoS for the cache
                 subsystem. Simulation-based evaluation shows that
                 conventional cache bandwidth management policies allow
                 concurrently executing threads to affect each other
                 significantly in an uncontrollable manner. The
                 evaluation targets cache bandwidth because the effects
                 of cache capacity sharing have been studied elsewhere.
                 In contrast with the conventional policies, the VPC
                 Arbiter meets its QoS performance objectives on all
                 workloads studied and over a range of allocated
                 bandwidth levels. The VPC Arbiter's fairness policy,
                 which distributes leftover bandwidth, mitigates the
                 effects of cache preemption latencies, thus ensuring
                 threads a high-degree of performance isolation.
                 Furthermore, the VPC Arbiter eliminates negative
                 bandwidth interference which can improve aggregate
                 throughput and resource utilization.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "chip multiprocessor; performance isolation; quality of
                 service; shared caches; soft real-time",
}

@Article{Minh:2007:EHT,
  author =       "Chi Cao Minh and Martin Trautmann and JaeWoong Chung
                 and Austen McDonald and Nathan Bronson and Jared Casper
                 and Christos Kozyrakis and Kunle Olukotun",
  title =        "An effective hybrid transactional memory system with
                 strong isolation guarantees",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "69--80",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250673",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "We propose signature-accelerated transactional memory
                 (SigTM), a hybrid TM system that reduces the overhead
                 of software transactions. SigTM uses hardware
                 signatures to track the read-set and write-set for
                 pending transactions and perform conflict detection
                 between concurrent threads. All other transactional
                 functionality, including data versioning, is
                 implemented in software. Unlike previously proposed
                 hybrid TM systems, SigTM requires no modifications to
                 the hardware caches, which reduces hardware cost and
                 simplifies support for nested transactions and
                 multithreaded processor cores. SigTM is also the first
                 hybrid TM system to provide strong isolation guarantees
                 between transactional blocks and non-transactional
                 accesses without additional read and write barriers in
                 non-transactional code.\par

                 Using a set of parallel programs that make frequent use
                 of coarse-grain transactions, we show that SigTM
                 accelerates software transactions by 30\% to 280\%. For
                 certain workloads, SigTM can match the performance of a
                 full-featured hardware TM system, while for workloads
                 with large read-sets it can be up to two times slower.
                 Overall, we show that SigTM combines the performance
                 characteristics and strong isolation guarantees of
                 hardware TM implementations with the low cost and
                 flexibility of software TM systems.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "multi-core architectures; parallel programming; strong
                 isolation; transactional memory",
}

@Article{Bobba:2007:PPH,
  author =       "Jayaram Bobba and Kevin E. Moore and Haris Volos and
                 Luke Yen and Mark D. Hill and Michael M. Swift and
                 David A. Wood",
  title =        "Performance pathologies in hardware transactional
                 memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "81--91",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250674",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Hardware Transactional Memory (HTM) systems reflect
                 choices from three key design dimensions: conflict
                 detection, version management, and conflict resolution.
                 Previously proposed HTMs represent three points in this
                 design space: lazy conflict detection, lazy version
                 management, committer wins (LL); eager conflict
                 detection, lazy version management, requester wins
                 (EL); and eager conflict detection, eager version
                 management, and requester stalls with conservative
                 deadlock avoidance (EE). To isolate the effects of
                 these high-level design decisions, we develop a common
                 framework that abstracts away differences in cache
                 write policies, interconnects, and ISA to compare these
                 three design points. Not surprisingly, the relative
                 performance of these systems depends on the workload.
                 Under light transactional loads they perform similarly,
                 but under heavy loads they differ by up to 80\%. None
                 of the systems performs best on all of our benchmarks.
                 We identify seven performance pathologies -interactions
                 between workload and system that degrade performance-as
                 the root cause of many performance differences:
                 FriendlyFire, StarvingWriter, SerializedCommit,
                 FutileStall, StarvingElder, RestartConvoy, and
                 DuelingUpgrades. We discuss when and on which systems
                 these pathologies can occur and show that they actually
                 manifest within TM workloads. The insight provided by
                 these pathologies motivated four enhanced systems that
                 often significantly reduce transactional memory
                 overhead. Importantly, by avoiding transaction
                 pathologies, each enhanced system performs well across
                 our suite of benchmarks.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "contention management; hardware; pathology;
                 performance; transactional memory",
}

@Article{Ramadan:2007:MTT,
  author =       "Hany E. Ramadan and Christopher J. Rossbach and Donald
                 E. Porter and Owen S. Hofmann and Aditya Bhandari and
                 Emmett Witchel",
  title =        "{MetaTM\slash TxLinux}: transactional memory for an
                 operating system",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "92--103",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250675",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This paper quantifies the effect of architectural
                 design decisions on the performance of TxLinux. TxLinux
                 is a Linux kernel modified to use transactions in place
                 of locking primitives in several key subsystems. We run
                 TxLinux on MetaTM, which is a new hardware-transaction
                 memory (HTM) model. MetaTM contains features that
                 enable efficient and correct interrupt handling for an
                 x86-like architecture. Live stack overwrites can
                 corrupt non-transactional stack memory and requires a
                 small change to the transaction register checkpoint
                 hardware to ensure correct operation of the operating
                 system. We also propose stack based early release to
                 reduce spurious conflicts on stack memory between
                 kernel code and interrupt handlers. We use MetaTM to
                 examine the performance sensitivity of individual
                 architectural features. For TxLinux we find that Polka
                 and SizeMatters are effective contention management
                 policies, some form of backoff on transaction
                 contention is vital for performance,and stalling on a
                 transaction conflict reduces transaction restart rates,
                 but does not improve performance. Transaction write
                 sets are small, and performance is insensitive to
                 transaction abort costs but sensitive to commit
                 costs.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "MetaTM; OS support; transactional memory; TxLinux",
}

@Article{Shriraman:2007:IHS,
  author =       "Arrvindh Shriraman and Michael F. Spear and Hemayet
                 Hossain and Virendra J. Marathe and Sandhya Dwarkadas
                 and Michael L. Scott",
  title =        "An integrated hardware-software approach to flexible
                 transactional memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "104--115",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250676",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "There has been considerable recent interest in both
                 hardware and software transactional memory (TM). We
                 present an intermediate approach, in which hardware
                 serves to accelerate a TM implementation controlled
                 fundamentally by software. Specifically, we describe an
                 alert on update mechanism (AOU) that allows a thread to
                 receive fast, asynchronous notification when
                 previously-identified lines are written by other
                 threads, and a programmable data isolation mechanism
                 (PDI) that allows a thread to hide its speculative
                 writes from other threads, ignoring conflicts, until
                 software decides to make them visible. These mechanisms
                 reduce bookkeeping, validation, and copying overheads
                 without constraining software policy on a host of
                 design decisions.\par

                 We have used AOU and PDI to implement a
                 hardware-accelerated-software transactional memory
                 system we call RTM. We have also used AOU alone to
                 create a simpler 'RTM-Lite'. Across a range of
                 microbenchmarks, RTM outperforms RSTM, a publicly
                 available software transactional memory system, by as
                 much as 8.7x (geometric mean of 3.5x) in single-thread
                 mode. At 16 threads, it outperforms RSTM by as much as
                 5x, with an average speedup of 2x. Performance degrades
                 gracefully when transactions overflow hardware
                 structures. RTM-Lite is slightly faster than RTM for
                 transactions that modify only small objects; full RTM
                 is significantly faster when objects are large. In a
                 strong argument for policy flexibility, we find that
                 the choice between eager (first-access) and lazy
                 (commit-time) conflict detection can lead to
                 significant performance differences in both directions,
                 depending on application characteristics.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "cache coherence; multiprocessors; RSTM; transactional
                 memory",
}

@Article{Abad:2007:RRE,
  author =       "Pablo Abad and Valentin Puente and Jos{\'e} Angel
                 Gregorio and Pablo Prieto",
  title =        "Rotary router: an efficient architecture for {CMP}
                 interconnection networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "116--125",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250678",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The trend towards increasing the number of processor
                 cores and cache capacity in future Chip-Multiprocessors
                 (CMPs), will require scalable packet-switched
                 interconnection networks adapted to the restrictions
                 imposed by the CMP environment. This paper presents an
                 innovative router design, which successfully addresses
                 CMP cost/performance constraints. The router structure
                 is based on two independent rings, which force packets
                 to circulate either clockwise or anti-clockwise,
                 traveling through every port of the router. It uses a
                 completely decentralized scheduling scheme, which
                 allows the design to: (1) take advantage of wide links,
                 (2) reduce Head of Line blocking, (3) use adaptive
                 routing, (4) be topology agnostic, (5) scale with
                 network degree, and (6) have reasonable power
                 consumption and implementation cost. A thorough
                 comparative performance analysis against competitive
                 conventional routers shows an advantage for our
                 proposal of up to 50 \% in terms of raw performance and
                 nearly 60 \% in terms of energy-delay product.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "chip multi-processors; interconnection networks;
                 router architecture",
}

@Article{Kim:2007:FBC,
  author =       "John Kim and William J. Dally and Dennis Abts",
  title =        "Flattened butterfly: a cost-efficient topology for
                 high-radix networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "126--137",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250679",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Increasing integrated-circuit pin bandwidth has
                 motivated a corresponding increase in the degree or
                 radix of interconnection networks and their routers.
                 This paper introduces the flattened butterfly, a
                 cost-efficient topology for high-radix networks. On
                 benign (load-balanced) traffic, the flattened butterfly
                 approaches the cost/performance of a butterfly network
                 and has roughly half the cost of a comparable
                 performance Clos network. The advantage over the Clos
                 is achieved by eliminating redundant hops when they are
                 not needed for load balance. On adversarial traffic,
                 the flattened butterfly matches the cost/performance of
                 a folded-Clos network and provides an order of
                 magnitude better performance than a conventional
                 butterfly. In this case, global adaptive routing is
                 used to switch the flattened butterfly from minimal to
                 non-minimal routing --- using redundant hops only when
                 they are needed. Minimal and non-minimal, oblivious and
                 adaptive routing algorithms are evaluated on the
                 flattened butterfly. We show that load-balancing
                 adversarial traffic requires nonminimal
                 globally-adaptive routing and show that sequential
                 allocators are required to avoid transient load
                 imbalance when using adaptive routing algorithms. We
                 also compare the cost of the flattened butterfly to
                 folded-Clos, hypercube,and butterfly networks with
                 identical capacity and show that the flattened
                 butterfly is more cost-efficient than folded-Clos and
                 hypercube topologies.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "cost model; flattened butterfly; global adaptive
                 routing; high-radix routers; interconnection networks;
                 topology",
}

@Article{Kim:2007:NDD,
  author =       "Jongman Kim and Chrysostomos Nicopoulos and Dongkook
                 Park and Reetuparna Das and Yuan Xie and Vijaykrishnan
                 Narayanan and Mazin S. Yousif and Chita R. Das",
  title =        "A novel dimensionally-decomposed router for on-chip
                 communication in {$3$D} architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "138--149",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250680",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Much like multi-story buildings in densely packed
                 metropolises, three-dimensional (3D) chip structures
                 are envisioned as a viable solution to skyrocketing
                 transistor densities and burgeoning die sizes in
                 multi-core architectures. Partitioning a larger die
                 into smaller segments and then stacking them in a 3D
                 fashion can significantly reduce latency and energy
                 consumption. Such benefits emanate from the notion that
                 inter-wafer distances are negligible compared to
                 intra-wafer distances. This attribute substantially
                 reduces global wiring length in 3D chips. The work in
                 this paper integrates the increasingly popular idea of
                 packet-based Networks-on-Chip (NoC) into a 3D setting.
                 While NoCs have been studied extensively in the 2D
                 realm, the microarchitectural ramifications of moving
                 into the third dimension have yet to be fully explored.
                 This paper presents a detailed exploration of
                 inter-strata communication architectures in 3D NoCs.
                 Three design options are investigated; a simple
                 bus-based inter-wafer connection, a hop-by-hop standard
                 3D design, and a full 3D crossbar implementation. In
                 this context, we propose a novel partially-connected 3D
                 crossbar structure, called the 3D
                 Dimensionally-Decomposed (DimDe) Router, which provides
                 a good tradeoff between circuit complexity and
                 performance benefits. Simulation results using (a) a
                 stand-alone cycle-accurate 3D NoC simulator running
                 synthetic workloads, and (b) a hybrid 3D NoC/cache
                 simulation environment running real commercial and
                 scientific benchmarks, indicate that the proposed DimDe
                 design provides latency and throughput improvements of
                 over 20\% on average over the other 3D architectures,
                 while remaining within 5\% of the full 3D crossbar
                 performance. Furthermore, based on synthesized hardware
                 implementations in 90 nm technology, the DimDe
                 architecture outperforms all other designs -- including
                 the full 3D crossbar -- by an average of 26\% in terms
                 of the Energy-Delay Product (EDP).",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "3D architecture; 3D integration; network-on-chip
                 (NoC)",
}

@Article{Kumar:2007:EVC,
  author =       "Amit Kumar and Li-Shiuan Peh and Partha Kundu and
                 Niraj K. Jha",
  title =        "Express virtual channels: towards the ideal
                 interconnection fabric",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "150--161",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250681",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Due to wire delay scalability and bandwidth
                 limitations inherent in shared buses and dedicated
                 links, packet-switched on-chip interconnection networks
                 are fast emerging as the pervasive communication fabric
                 to connect different processing elements in many-core
                 chips. However, current state-of-the-art
                 packet-switched networks rely on complex routers which
                 increases the communication overhead and energy
                 consumption as compared to the ideal interconnection
                 fabric.\par

                 In this paper, we try to close the gap between the
                 state-of-the-art packet-switched network and the ideal
                 interconnect by proposing express virtual channels
                 (EVCs), a novel flow control mechanism which allows
                 packets to virtually bypass intermediate routers along
                 their path in a completely non-speculative fashion,
                 thereby lowering the energy/delay towards that of a
                 dedicated wire while simultaneously approaching ideal
                 throughput with a practical design suitable for on-chip
                 networks.\par

                 Our evaluation results using a detailed cycle-accurate
                 simulator on a range of synthetic traffic and SPLASH
                 benchmark traces show upto 84\% reduction in packet
                 latency and upto 23\% improvement in throughput while
                 reducing the average router energy consumption by upto
                 38\% over an existing state-of-the-art packet-switched
                 design. When compared to the ideal interconnect, EVCs
                 add just two cycles to the no-load latency, and are
                 within 14\% of the ideal throughput. Moreover, we show
                 that the proposed design incurs a minimal hardware
                 overhead while exhibiting excellent scalability with
                 increasing network sizes.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "flow-control; packet-switching; router design",
}

@Article{Kumar:2007:CAS,
  author =       "Sanjeev Kumar and Christopher J. Hughes and Anthony
                 Nguyen",
  title =        "{Carbon}: architectural support for fine-grained
                 parallelism on chip multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "162--173",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250683",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Chip multiprocessors (CMPs) are now commonplace, and
                 the number of cores on a CMP is likely to grow
                 steadily. However, in order to harness the additional
                 compute resources of a CMP, applications must expose
                 their thread-level parallelism to the hardware. One
                 common approach to doing this is to decompose a program
                 into parallel 'tasks' and allow an underlying software
                 layer to schedule these tasks to different threads.
                 Software task scheduling can provide good parallel
                 performance as long as tasks are large compared to the
                 software overheads.\par

                 We examine a set of applications from an important
                 emerging domain: Recognition, Mining, and Synthesis
                 (RMS). Many RMS applications are compute-intensive and
                 have abundant thread-level parallelism, and are
                 therefore good targets for running on a CMP. However, a
                 significant number have small tasks for which software
                 task schedulers achieve only limited parallel
                 speedups.\par

                 We propose Carbon, a hardware technique to accelerate
                 dynamic task scheduling on scalable CMPs. Carbon has
                 relatively simple hardware, most of which can be placed
                 far from the cores. We compare Carbon to some highly
                 tuned software task schedulers for a set of RMS
                 benchmarks with small tasks. Carbon delivers
                 significant performance improvements over the best
                 software scheduler: on average for 64 cores, 68\%
                 faster on a set of loop-parallel benchmarks, and 109\%
                 faster on a set of task-parallel benchmarks.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "architectural support; CMP; loop and task
                 parallelism",
}

@Article{Neelakantam:2007:HAR,
  author =       "Naveen Neelakantam and Ravi Rajwar and Suresh Srinivas
                 and Uma Srinivasan and Craig Zilles",
  title =        "Hardware atomicity for reliable software speculation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "174--185",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250684",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Speculative compiler optimizations are effective in
                 improving both single-thread performance and reducing
                 power consumption, but their implementation introduces
                 significant complexity, which can limit their adoption,
                 limit their optimization scope, and negatively impact
                 the reliability of the compilers that implement them.
                 To eliminate much of this complexity, as well as
                 increase the effectiveness of these optimizations, we
                 propose that microprocessors provide
                 architecturally-visible hardware primitives for atomic
                 execution. These primitives provide to the compiler the
                 ability to optimize the program's hot path in
                 isolation, allowing the use of non-speculative
                 formulations of optimization passes to perform
                 speculative optimizations. Atomic execution guarantees
                 that if a speculation invariant does not hold, the
                 speculative updates are discarded, the register state
                 is restored, and control is transferred to a
                 non-speculative version of the code, thereby relieving
                 the compiler from the responsibility of generating
                 compensation code.\par

                 We demonstrate the benefit of hardware atomicity in the
                 context of a Java virtual machine. We find
                 incorporating the notion of atomic regions into an
                 existing compiler intermediate representation to be
                 natural, requiring roughly 3,000 lines of code (~3\% of
                 a JVM's optimizing compiler), most of which were for
                 region formation. Its incorporation creates new
                 opportunities for existing optimization passes, as well
                 as greatly simplifying the implementation of additional
                 optimizations (e.g., partial inlining, partial loop
                 unrolling, and speculative lock elision). These
                 optimizations reduce dynamic instruction count by 11\%
                 on average and result in a 10-15\% average speedup,
                 relative to a baseline compiler with a similar degree
                 of inlining.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "atomicity; checkpoint; isolation; Java; optimization;
                 speculation",
}

@Article{Ipek:2007:CFA,
  author =       "Engin Ipek and Meyrem Kirman and Nevin Kirman and Jose
                 F. Martinez",
  title =        "Core fusion: accommodating software diversity in chip
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "186--197",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250686",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This paper presents core fusion, a reconfigurable chip
                 multiprocessor(CMP) architecture where groups of
                 fundamentally independent cores can dynamically morph
                 into a larger CPU, or they can be used as distinct
                 processing elements, as needed at run time by
                 applications. Core fusion gracefully accommodates
                 software diversity and incremental parallelization in
                 CMPs. It provides a single execution model across all
                 configurations, requires no additional programming
                 effort or specialized compiler support, maintains ISA
                 compatibility, and leverages mature micro-architecture
                 technology.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "chip multiprocessors; reconfigurable architectures;
                 software diversity",
}

@Article{Chi:2007:TQA,
  author =       "Eric Chi and Stephen A. Lyon and Margaret Martonosi",
  title =        "Tailoring quantum architectures to implementation
                 style: a quantum computer for mobile and persistent
                 qubits",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "198--209",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250687",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In recent years, quantum computing (QC) research has
                 moved from the realm of theoretical physics and
                 mathematics into real implementations. With many
                 different potential hardware implementations, quantum
                 computer architecture is a rich field with an
                 opportunity to solve interesting new problems and to
                 revisit old ones. This paper presents a QC architecture
                 tailored to physical implementations with highly mobile
                 and persistent quantum bits (qubits). Implementations
                 with qubit coherency times that are much longer than
                 operation times and qubit transportation times that are
                 orders of magnitude faster than operation times lend
                 greater flexibility to the architecture. This is
                 particularly true in the placement and locality of
                 individual qubits. For concreteness, we assume a
                 physical device model based on electron-spin qubits on
                 liquid helium (eSHe).\par

                 Like many conventional computer architectures, QCs
                 focus on the efficient exposure of parallelism. We
                 present here a QC microarchitecture that enjoys
                 increasing computational parallelism with size and
                 latency scaling only linearly with the number of
                 operations. Although an efficient and high level of
                 parallelism is admirable, quantum hardware is still
                 expensive and difficult to build, so we demonstrate how
                 the software may be optimized to reduce an
                 application's hardware requirements by 25\% with no
                 performance loss. Because the majority of a QC's time
                 and resources are devoted to quantum error correction,
                 we also present noise modeling results that evaluate
                 error correction procedures. These results demonstrate
                 that idle qubits in memory need only be refreshed
                 approximately once every one hundred operation
                 cycles.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "architecture; quantum",
}

@Article{Yang:2007:BSP,
  author =       "Xuejun Yang and Xiaobo Yan and Zuocheng Xing and Yu
                 Deng and Jiang Jiang and Ying Zhang",
  title =        "A 64-bit stream processor architecture for scientific
                 applications",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "210--219",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250689",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Stream architecture is a novel microprocessor
                 architecture with wide application potential. But as
                 for whether it can be used efficiently in scientific
                 computing, many issues await further study. This paper
                 first gives the design and implementation of a 64-bit
                 stream processor, FT64 (Fei Teng 64), for scientific
                 computing. The carrying out of 64-bit extension design
                 and scientific computing oriented optimization are
                 described in such aspects as instruction set
                 architecture, stream controller, micro controller, ALU
                 cluster, memory hierarchy and interconnection interface
                 here. Second, two kinds of communications as message
                 passing and stream communications are put forward. An
                 interconnection based on the communications is designed
                 for FT64-based high performance computers. Third, a
                 novel stream programming language, SF95 (Stream
                 FORTRAN95), and its compiler, SF95Compiler (Stream
                 FORTRAN95 Compiler), are developed to facilitate the
                 development of scientific applications. Finally, nine
                 typical scientific application kernels are tested and
                 the results show the efficiency of stream architecture
                 for scientific computing.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "architecture; compiler; high performance computing;
                 program language; scientific application; stream
                 processor",
}

@Article{Hughes:2007:PSA,
  author =       "Christopher J. Hughes and Radek Grzeszczuk and
                 Eftychios Sifakis and Daehyun Kim and Sanjeev Kumar and
                 Andrew P. Selle and Jatin Chhugani and Matthew Holliman
                 and Yen-Kuang Chen",
  title =        "Physical simulation for animation and visual effects:
                 parallelization and characterization for chip
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "220--231",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250690",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "We explore the emerging application area of
                 physics-based simulation for computer animation and
                 visual special effects. In particular, we examine its
                 parallelization potential and characterize its behavior
                 on a chip multiprocessor (CMP). Applications in this
                 domain model and simulate natural phenomena, and often
                 direct visual components of motion pictures. We study a
                 set of three workloads that exemplify the span and
                 complexity of physical simulation applications used in
                 a production environment: fluid dynamics, facial
                 animation, and cloth simulation. They are
                 computationally demanding, requiring from a few seconds
                 to several minutes to simulate a single frame;
                 therefore, they can benefit greatly from the
                 acceleration possible with large scale
                 CMPs.\par

                 Starting with serial versions of these applications, we
                 parallelize code accounting for at least 96\% of the
                 serial execution time, targeting a large number of
                 threads. We then study the most expensive modules using
                 a simulated 64-core CMP.\par

                 For the code representing key modules, we achieve
                 parallel scaling of 45x, 50x, and 30x for fluid, face,
                 and cloth simulations, respectively. The modules have a
                 spectrum of parallel task granularity and locking
                 behavior, and all but one are dominated by loop-level
                 parallelism. Many modules operate on streams of data.
                 In some cases, modules iterate over their data, leading
                 to significant temporal locality. This streaming
                 behavior leads to very high on-die and main memory
                 bandwidth requirements. Finally, most modules have
                 little inter-thread communication since they are
                 data-parallel, but a few require heavy communication
                 between data-parallel operations.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "characterization; CMP; parallelization; physical
                 simulation",
}

@Article{Yeh:2007:PAR,
  author =       "Thomas Y. Yeh and Petros Faloutsos and Sanjay J. Patel
                 and Glenn Reinman",
  title =        "{ParallAX}: an architecture for real-time physics",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "232--243",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250691",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Future interactive entertainment applications will
                 feature the physical simulation of thousands of
                 interacting objects using explosions, breakable
                 objects, and cloth effects. While these applications
                 require a tremendous amount of performance to satisfy
                 the minimum frame rate of 30 FPS, there is a dramatic
                 amount of parallelism in future physics workloads. How
                 will future physics architectures leverage parallelism
                 to achieve the real-time constraint?.\par

                 We propose and characterize a set of forward-looking
                 benchmarks to represent future physics load and explore
                 the design space of future physics processors. In
                 response to the demand of this workload, we demonstrate
                 an architecture with a set of powerful cores and caches
                 to provide performance for the serial and coarse-grain
                 parallel components of physics simulation, along with a
                 flexible set of simple cores to exploit fine-grain
                 parallelism. Our architecture combines intelligent,
                 application-aware L2 management with dynamic
                 coupling\slash allocation of simple cores to complex
                 cores. Furthermore, we perform sensitivity analysis on
                 interconnect alternatives to determine how tightly to
                 couple these cores.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "application specific processor; chip multiprocessor;
                 interactive entertainment; physics based animation;
                 real-time physics; stream processing",
}

@Article{Kim:2007:AIB,
  author =       "Martha Mercaldi Kim and Mojtaba Mehrara and Mark Oskin
                 and Todd Austin",
  title =        "Architectural implications of brick and mortar silicon
                 manufacturing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "244--253",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250693",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "We introduce a novel chip fabrication technique called
                 'brick and mortar', in which chips are made from small,
                 pre-fabricated ASIC bricks and bonded in a
                 designer-specified arrangement to an inter-brick
                 communication backbone chip. The goal of brick and
                 mortar assembly is to provide a low-overhead method to
                 produce custom chips, yet with performance that tracks
                 an ASIC more closely than an FPGA. This paper examines
                 the architectural design choices in this chip-design
                 system. These choices include the definition of
                 reasonable bricks, both in functionality and size, as
                 well as the communication interconnect that the I/O cap
                 provides. To do this we synthesize candidate bricks,
                 analyze their area and bandwidth demands, and present
                 an architectural design for the inter-brick
                 communication network. We discuss a sample chip design,
                 a 16-way CMP, and analyze the costs and benefits of
                 designing chips with brick and mortar. We find that
                 this method of producing chips incurs only a small
                 performance loss (8\%) compared to a fully custom ASIC,
                 which is significantly less than the degradation seen
                 from other low-overhead chip options, such as FPGAs.
                 Finally, we measure the effect that architectural
                 design decisions have on the behavior of the proposed
                 physical brick assembly technique, fluidic
                 self-assembly.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "chip assembly; design re-use; interconnect design",
}

@Article{Amin:2007:APA,
  author =       "Ahmed M. Amin and Mithuna Thottethodi and T. N.
                 Vijaykumar and Steven Wereley and Stephen C. Jacobson",
  title =        "{Aquacore}: a programmable architecture for
                 microfluidics",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "254--265",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250694",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Advances in microfluidic research has enabled
                 lab-on-a-chip (LoC) technology to achieve
                 miniaturization and integration of biological and
                 chemical analyses to a single chip comprising channels,
                 valves, mixers, heaters, separators, and sensors. These
                 miniature instruments appear to offer the rare
                 combination of faster, cheaper, and higher-precision
                 analyses in comparison to conventional bench-scale
                 methods. LoCs have been applied to diverse domains such
                 as proteomics, genomics, biochemistry, virology, cell
                 biology, and chemical synthesis. However, to date LoCs
                 have been designed as application-specific chips which
                 incurs significant design effort, turn-around time, and
                 cost, and degrades designer and user productivity. To
                 address these limitations, we envision a programmable
                 LoC (PLoC) and propose a comprehensive fluidic
                 instruction set, called AquaCore Instruction Set (AIS),
                 and a fluidic microarchitecture, called AquaCore, to
                 implement AIS. We present four key design aspects in
                 which the AIS and AquaCore differ from their computer
                 counterparts, and our design decisions made on the
                 basis of the implications of these differences. We
                 demonstrate the use of the PLoC in a range of domains
                 by hand-compiling real-world microfluidic assays in
                 AIS, and show a detailed breakdown of the execution
                 times for the assays and an estimate of the chip
                 area.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "fluidic; fluidic microarchitecture; instruction set;
                 microfluidics; programmable lab on a chip",
}

@Article{Wenisch:2007:MSW,
  author =       "Thomas F. Wenisch and Anastasia Ailamaki and Babak
                 Falsafi and Andreas Moshovos",
  title =        "Mechanisms for store-wait-free multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "266--277",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250696",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Store misses cause significant delays in shared-memory
                 multiprocessors because of limited store buffering and
                 ordering constraints required for proper
                 synchronization. Today, programmers must choose from a
                 spectrum of memory consistency models that reduce store
                 stalls at the cost of increased programming complexity.
                 Prior research suggests that the performance gap among
                 consistency models can be closed through
                 speculation--enforcing order only when dynamically
                 necessary. Unfortunately, past designs either provide
                 insufficient buffering, replace all stores with
                 read-modify-write operations, and/or recover from
                 ordering violations via impractical fine-grained
                 rollback mechanisms.\par

                 We propose two mechanisms that, together, enable
                 store-wait-free implementations of any memory
                 consistency model. To eliminate buffer-capacity-related
                 stalls, we propose the scalable store buffer, which
                 places private/speculative values directly into the L1
                 cache, thereby eliminating the non-scalable associative
                 search of conventional store buffers. To eliminate
                 ordering-related stalls, we propose atomic sequence
                 ordering, which enforces ordering constraints over
                 coarse-grain access sequences while relaxing order
                 among individual accesses. Using cycle-accurate
                 full-system simulation of scientific and commercial
                 applications, we demonstrate that these mechanisms
                 allow the simplified programming of strict ordering
                 while outperforming conventional implementations on
                 average by 32\% (sequential consistency), 22\% (SPARC
                 total store order) and 9\% (SPARC relaxed memory
                 order).",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "memory consistency models; store buffer design",
}

@Article{Ceze:2007:BBE,
  author =       "Luis Ceze and James Tuck and Pablo Montesinos and
                 Josep Torrellas",
  title =        "{BulkSC}: bulk enforcement of sequential consistency",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "278--289",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250697",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "While Sequential Consistency (SC) is the most
                 intuitive memory consistency model and the one most
                 programmers likely assume, current multiprocessors do
                 not support it. Instead, they support more relaxed
                 models that deliver high performance. SC
                 implementations are considered either too slow or --
                 when they can match the performance of relaxed models
                 -- too difficult to implement.\par

                 In this paper, we propose Bulk Enforcement of SC
                 (BulkSC), a novel way of providing SC that is simple to
                 implement and offers performance comparable to Release
                 Consistency (RC). The idea is to dynamically group sets
                 of consecutive instructions into chunks that appear to
                 execute atomically and in isolation. The hardware
                 enforces SC at the coarse grain of chunks which, to the
                 program, appears as providing SC at the individual
                 memory access level. BulkSC keeps the implementation
                 simple by largely decoupling memory consistency
                 enforcement from processor structures. Moreover, it
                 delivers high performance by enabling full memory
                 access reordering and overlapping within chunks and
                 across chunks. We describe a complete system
                 architecture that supports BulkSC and show that it
                 delivers performance comparable to RC.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "bulk; chip multiprocessors; memory consistency models;
                 programmability; sequential consistency",
}

@Article{Diniz:2007:LPC,
  author =       "Bruno Diniz and Dorgival Guedes and Wagner {Meira,
                 Jr.} and Ricardo Bianchini",
  title =        "Limiting the power consumption of main memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "290--301",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250699",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The peak power consumption of hardware components
                 affects their power supply, packaging, and cooling
                 requirements. When the peak power consumption is high,
                 the hardware components or the systems that use them
                 can become expensive and bulky. Given that components
                 and systems rarely (if ever) actually require peak
                 power, it is highly desirable to limit power
                 consumption to a less-than-peak power budget, based on
                 which power supply, packaging, and cooling
                 infrastructure scan be more intelligently
                 provisioned.\par

                 In this paper, we study dynamic approaches for limiting
                 the power consumption of main memories. Specifically,
                 we propose four techniques that limit consumption by
                 adjusting the power states of the memory devices, as a
                 function of the load on the memory subsystem. Our
                 simulations of applications from three benchmarks
                 demonstrate that our techniques can consistently limit
                 power to a pre-established budget. Two of the
                 techniques can limit power with very low performance
                 degradation. Our results also show that, when using
                 these superior techniques, limiting power is at least
                 as effective an energy-conservation approach as
                 state-of-the-art techniques explicitly designed for
                 performance-aware energy conservation. These latter
                 results represent a departure from current energy
                 management research and practice.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "main memory; performance; power and energy
                 management",
}

@Article{Mesa-Martinez:2007:PMV,
  author =       "Francisco Javier Mesa-Martinez and Joseph
                 Nayfach-Battilana and Jose Renau",
  title =        "Power model validation through thermal measurements",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "302--311",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250700",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Simulation environments are an indispensable tool in
                 the design, prototyping, performance evaluation, and
                 analysis of computer systems. Simulator must be able to
                 faithfully reflect the behavior of the system being
                 analyzed. To ensure the accuracy of the simulator, it
                 must be verified and determined to closely match
                 empirical data. Modern processors provide enough
                 performance counters to validate the majority of the
                 performance models; nevertheless, the information
                 provided is not enough to validate power and thermal
                 models.\par

                 In order to address some of the difficulties associated
                 with the validation of power and thermal models, this
                 paper proposes an infrared measurement setup to capture
                 run-time power consumption and thermal characteristics
                 of modern chips. We use infrared cameras with high
                 spatial resolution ($ 10 \times 10 $ $ \mu $ m) and
                 high frame rate (125fps) to capture thermal maps. To
                 generate a detailed power breakdown (leakage and
                 dynamic) for each processor floorplan unit, we employ
                 genetic algorithms. The genetic algorithm finds a power
                 equation for each floorplan block that produces the
                 measured temperature for a given thermal package. The
                 difference between the predicted power and the
                 externally measured power consumption for an AMD Athlon
                 analyzed in this paper has less than 1\% discrepancy.
                 As an example of applicability, we compare the obtained
                 measurements with CACTI power models, and propose
                 extensions to existing thermal models to increase
                 accuracy.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "power and thermal measurements",
}

@Article{Lin:2007:TMM,
  author =       "Jiang Lin and Hongzhong Zheng and Zhichun Zhu and
                 Howard David and Zhao Zhang",
  title =        "Thermal modeling and management of {DRAM} memory
                 systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "312--322",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250701",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "With increasing speed and power density,
                 high-performance memories, including FB-DIMM (Fully
                 Buffered DIMM) and DDR2 DRAM, now begin to require
                 dynamic thermal management (DTM) as processors and hard
                 drives did. The DTM of memories, nevertheless, is
                 different in that it should take the processor
                 performance and power consumption into consideration.
                 Existing schemes have ignored that. In this study, we
                 investigate a new approach that controls the memory
                 thermal issues from the source generating memory
                 activities - the processor. It will smooth the program
                 execution when compared with shutting down memory
                 abruptly, and therefore improve the overall system
                 performance and power efficiency. For multicore
                 systems, we propose two schemes called adaptive core
                 gating and coordinated DVFS. The first scheme activates
                 clock gating on selected processor cores and the second
                 one scales down the frequency and voltage levels of
                 processor cores when the memory is to be over-heated.
                 They can successfully control the memory activities and
                 handle thermal emergency. More importantly, they
                 improve performance significantly under the given
                 thermal envelope. Our simulation results show that
                 adaptive core gating improves performance by up to
                 23.3\% (16.3\% on average) on a four-core system with
                 FB-DIMM when compared with DRAM thermal shutdown; and
                 coordinated DVFS with control-theoretic methods
                 improves the performance by up to 18.5\% (8.3\% on
                 average).",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "DRAM memories; thermal management; thermal modeling",
}

@Article{Tiwari:2007:RPA,
  author =       "Abhishek Tiwari and Smruti R. Sarangi and Josep
                 Torrellas",
  title =        "{ReCycle}: pipeline adaptation to tolerate process
                 variation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "323--334",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250703",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Process variation affects processor pipelines by
                 making some stages slower and others faster, therefore
                 exacerbating pipeline unbalance. This reduces the
                 frequency attainable by the pipeline. To improve
                 performance, this paper proposes ReCycle, an
                 architectural framework that comprehensively applies
                 cycle time stealing to the pipeline - transferring the
                 time slack of the faster stages to the slow ones by
                 skewing clock arrival times to latching elements after
                 fabrication. As a result, the pipeline can be clocked
                 with a period equal to the average stage delay rather
                 than the longest one. In addition, ReCycle's frequency
                 gains are enhanced with Donor stages, which are empty
                 stages added to 'donate' slack to the slow stages.
                 Finally, ReCycle can also convert slack into power
                 reductions.\par

                 For a 17FO4 pipeline, ReCycle increases the frequency
                 by 12\% and the application performance by 9\% on
                 average. Combining ReCycle and donor stages delivers
                 improvements of 36\% in frequency and 15\% in
                 performance on average, completely reclaiming the
                 performance losses due to variation.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "clock skew; pipeline; process variation",
}

@Article{Sassone:2007:MSR,
  author =       "Peter G. Sassone and Jeff {Rupley II} and Edward
                 Brekelbaum and Gabriel H. Loh and Bryan Black",
  title =        "Matrix scheduler reloaded",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "335--346",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250704",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "From multiprocessor scale-up to cache sizes to the
                 number of reorder-buffer entries, microarchitects wish
                 to reap the benefits of more computing resources while
                 staying within power and latency bounds. This tension
                 is quite evident in schedulers, which need to be large
                 and single-cycle for maximum performance on
                 out-of-order cores. In this work we present two
                 straightforward modifications to a matrix scheduler
                 implementation which greatly strengthen its
                 scalability. Both are based on the simple observation
                 that the wakeup and picker matrices are sparse, even at
                 small sizes; thus small indirection tables can be used
                 to greatly reduce their width and latency. This
                 technique can be used to create quicker iso-performance
                 schedulers (17-58\% reduced critical path) or larger
                 iso-timing schedulers (7-26\% IPC increase).
                 Importantly, the power and area requirements of the
                 additional hardware are likely offset by the greatly
                 reduced matrix sizes and subsuming the functionality of
                 the power-hungry allocation CAMs.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "matrix; microarchitecture; picker; scheduler; wakeup",
}

@Article{Sethumadhavan:2007:LBE,
  author =       "Simha Sethumadhavan and Franziska Roesner and Joel S.
                 Emer and Doug Burger and Stephen W. Keckler",
  title =        "Late-binding: enabling unordered load-store queues",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "347--357",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250705",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Conventional load/store queues (LSQs) are an
                 impediment to both power-efficient execution in
                 superscalar processors and scaling to large-window
                 designs. In this paper, we propose techniques to
                 improve the area and power efficiency of LSQs by
                 allocating entries when instructions issue ('late
                 binding'), rather than when they are dispatched. This
                 approach enables lower occupancy and thus smaller LSQs.
                 Efficient implementations of late-binding LSQs,
                 however, require the entries in the LSQ to be unordered
                 with respect to age. In this paper, we show how to
                 provide full LSQ functionality in an unordered design
                 with only small additional complexity and negligible
                 performance losses. We show that late-binding,
                 unordered LSQs work well for small-window superscalar
                 processors, but can also be scaled effectively to
                 large, kilo-window processors by breaking the LSQs into
                 address-interleaved banks. To handle the increased
                 overflows, we apply classic network flow control
                 techniques to the processor micronetworks, enabling
                 low-overhead recovery mechanisms from bank overflows.
                 We evaluate three such mechanisms: instruction replay,
                 skid buffers, and virtual-channel buffering in the
                 on-chip memory network. We show that for an
                 80-instruction window, the LSQ can be reduced to 32
                 entries. For a 1024-instruction window, the unordered,
                 late-binding LSQ works well with four banks of 48
                 entries each. By applying a Bloom filter as well, this
                 design achieves full hardware memory disambiguation for
                 a 1,024 instruction window while requiring low average
                 power per load and store access of 8 and 12 CAM
                 entries, respectively.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "late binding; memory disambiguation; network flow
                 control",
}

@Article{Leverich:2007:CMS,
  author =       "Jacob Leverich and Hideho Arakida and Alex
                 Solomatnikov and Amin Firoozshahian and Mark Horowitz
                 and Christos Kozyrakis",
  title =        "Comparing memory systems for chip multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "358--368",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250707",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "There are two basic models for the on-chip memory in
                 CMP systems: hardware-managed coherent caches and
                 software-managed streaming memory. This paper performs
                 a direct comparison of the two models under the same
                 set of assumptions about technology, area, and
                 computational capabilities. The goal is to quantify how
                 and when they differ in terms of performance, energy
                 consumption, bandwidth requirements, and latency
                 tolerance for general-purpose CMPs. We demonstrate that
                 for data-parallel applications, the cache-based and
                 streaming models perform and scale equally well. For
                 certain applications with little data reuse, streaming
                 scales better due to better bandwidth use and
                 macroscopic software prefetching. However, the
                 introduction of techniques such as hardware prefetching
                 and non-allocating stores to the cache-based model
                 eliminates the streaming advantage. Overall, our
                 results indicate that there is not sufficient advantage
                 in building streaming memory systems where all on-chip
                 memory structures are explicitly managed. On the other
                 hand, we show that streaming at the programming model
                 level is particularly beneficial, even with the
                 cache-based model, as it enhances locality and creates
                 opportunities for bandwidth optimizations. Moreover, we
                 observe that stream programming is actually easier with
                 the cache-based model because the hardware guarantees
                 correct, best-effort execution even when the programmer
                 cannot fully regularize an application's code.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "chip multiprocessors; coherent caches; locality
                 optimizations; parallel programming; streaming memory",
}

@Article{Muralimanohar:2007:IDC,
  author =       "Naveen Muralimanohar and Rajeev Balasubramonian",
  title =        "Interconnect design considerations for large {NUCA}
                 caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "369--380",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250708",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The ever increasing sizes of on-chip caches and the
                 growing domination of wire delay necessitate
                 significant changes to cache hierarchy design
                 methodologies. Many recent proposals advocate splitting
                 the cache into a large number of banks and employing a
                 network-on-chip (NoC) to allow fast access to nearby
                 banks (referred to as Non-Uniform Cache
                 Architectures--NUCA). Most studies on NUCA
                 organizations have assumed a generic NoC and focused on
                 logical policies for cache block placement, movement,
                 and search. Since wire/router delay and power are major
                 limiting factors in modern processors, this work
                 focuses on interconnect design and its influence on
                 NUCA performance and power. We extend the widely-used
                 CACTI cache modeling tool to take network design
                 parameters into account. With these overheads
                 appropriately accounted for, the optimal cache
                 organization is typically very different from that
                 assumed in prior NUCA studies. To alleviate the
                 interconnect delay bottleneck, we propose novel cache
                 access optimizations that introduce heterogeneity
                 within the inter-bank network. The careful
                 consideration of interconnect choices for a large cache
                 results in a 51\% performance improvement over a
                 baseline generic NoC and the introduction of
                 heterogeneity within the network yields an additional
                 11-15\% performance improvement.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "cache models; interconnect; memory hierarchies;
                 network-on-chip; non-uniform cache architecture",
}

@Article{Qureshi:2007:AIP,
  author =       "Moinuddin K. Qureshi and Aamer Jaleel and Yale N. Patt
                 and Simon C. Steely and Joel Emer",
  title =        "Adaptive insertion policies for high performance
                 caching",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "381--391",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250709",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The commonly used LRU replacement policy is
                 susceptible to thrashing for memory-intensive workloads
                 that have a working set greater than the available
                 cache size. For such applications, the majority of
                 lines traverse from the MRU position to the LRU
                 position without receiving any cache hits, resulting in
                 inefficient use of cache space. Cache performance can
                 be improved if some fraction of the working set is
                 retained in the cache so that at least that fraction of
                 the working set can contribute to cache hits.\par

                 We show that simple changes to the insertion policy can
                 significantly reduce cache misses for memory-intensive
                 workloads. We propose the LRU Insertion Policy (LIP)
                 which places the incoming line in the LRU position
                 instead of the MRU position. LIP protects the cache
                 from thrashing and results in close to optimal hit rate
                 for applications that have a cyclic reference pattern.
                 We also propose the Bimodal Insertion Policy (BIP) as
                 an enhancement of LIP that adapts to changes in the
                 working set while maintaining the thrashing protection
                 of LIP. We finally propose a Dynamic Insertion Policy
                 (DIP) to choose between BIP and the traditional LRU
                 policy depending on which policy incurs fewer misses.
                 The proposed insertion policies do not require any
                 change to the existing cache structure, are trivial to
                 implement, and have a storage requirement of less than
                 two bytes. We show that DIP reduces the average MPKI of
                 the baseline 1MB 16-way L2 cache by 21\%, bridging
                 two-thirds of the gap between LRU and OPT.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "replacement; set dueling; set sampling; thrashing",
}

@Article{Karger:2007:PSL,
  author =       "Paul A. Karger",
  title =        "Performance and security lessons learned from
                 virtualizing the {Alpha} processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "392--401",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250711",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Virtualization has become much more important
                 throughout the computer industry both to improve
                 security and to support multiple workloads on the same
                 hardware with effective isolation between those
                 workloads. The most widely used chip architecture, the
                 Intel and AMD x86 processors, have begun to support
                 virtualization, but the initial implementations show
                 some limitations. This paper examines the
                 virtualization properties of the Alpha architecture
                 with particular emphasis on features that improve
                 performance and security. It shows how the Alpha's
                 features of PALcode, address space numbers, software
                 handling of translation buffer misses, lack of used and
                 modified bits, and secure handling of unpredictable
                 results all contribute to making virtualization of the
                 Alpha particularly easy. The paper then compares the
                 virtual architecture of the Alpha with Intel's and
                 AMD's virtualization approaches for x86. It also
                 comments briefly on Intel's virtualization technology
                 for Itanium, IBM's zSeries and pSeries hypervisors and
                 Sun's UltraSPARC virtualization. It particularly
                 identifies some differences between translation buffers
                 on x86 and translation buffers on VAX and Alpha that
                 can have adverse performance consequences.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "hypervisors; security; virtual machine monitors;
                 virtualizability",
}

@Article{Karkhanis:2007:ADA,
  author =       "Tejas S. Karkhanis and James E. Smith",
  title =        "Automated design of application specific superscalar
                 processors: an analytical approach",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "402--411",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250712",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Analytical modeling is applied to the automated design
                 of application-specific superscalar processors. Using
                 an analytical method bridges the gap between the size
                 of the design space and the time required for detailed
                 cycle-accurate simulations. The proposed design
                 framework takes as inputs the design targets (upper
                 bounds on execution time, area, and energy), design
                 alternatives, and one or more application programs. The
                 output is the set of out-of-order superscalar
                 processors that are Pareto-optimal with respect to
                 performance-energy-area. The core of the new design
                 framework is made up of analytical performance and
                 energy activity models, and an analytical model-based
                 design optimization process.\par

                 For a set of benchmark programs and a design space of
                 2000 designs, the design framework arrives at all
                 performance-energy-area Pareto-optimal design points
                 within 16 minutes on a 2 GHz Pentium-4. In contrast, it
                 is estimated that a na{\"\i}ve cycle-accurate
                 simulation-based exhaustive search would require at
                 least two months to arrive at the Pareto-optimal design
                 points for the same design space.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "analytical model; application specific processors;
                 design optimization; energy model; performance model",
}

@Article{Phansalkar:2007:ARA,
  author =       "Aashish Phansalkar and Ajay Joshi and Lizy K. John",
  title =        "Analysis of redundancy and application balance in the
                 {SPEC CPU2006} benchmark suite",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "412--423",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250713",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The recently released SPEC CPU2006 benchmark suite is
                 expected to be used by computer designers and computer
                 architecture researchers for pre-silicon early design
                 analysis. Partial use of benchmark suites by
                 researchers, due to simulation time constraints,
                 compiler difficulties, or library or system call issues
                 is likely to happen; but a random subset can lead to
                 misleading results. This paper analyzes the SPEC
                 CPU2006 benchmarks using performance counter based
                 experimentation from several state of the art systems,
                 and uses statistical techniques such as principal
                 component analysis and clustering to draw inferences on
                 the similarity of the benchmarks and the redundancy in
                 the suite and arrive at meaningful subsets.\par

                 The SPEC CPU2006 benchmark suite contains several
                 programs from areas such as artificial intelligence and
                 includes none from the electronic design automation
                 (EDA) application area. Hence there is a concern on the
                 application balance in the suite. An analysis from the
                 perspective of fundamental program characteristics
                 shows that the included programs offer characteristics
                 broader than the EDA programs' space. A subset of 6
                 integer programs and 8 floating point programs can
                 yield most of the information from the entire suite.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "benchmark; clustering; microprocessor performance
                 counters; SPEC",
}

@Article{Kim:2007:VPR,
  author =       "Hyesoon Kim and Jos{\'e} A. Joao and Onur Mutlu and
                 Chang Joo Lee and Yale N. Patt and Robert Cohn",
  title =        "{VPC} prediction: reducing the cost of indirect
                 branches via hardware-based dynamic devirtualization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "424--435",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250715",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Indirect branches have become increasingly common in
                 modular programs written in modern object-oriented
                 languages and virtual machine based runtime systems.
                 Unfortunately, the prediction accuracy of indirect
                 branches has not improved as much as that of
                 conditional branches. Furthermore, previously proposed
                 indirect branch predictors usually require a
                 significant amount of extra hardware storage and
                 complexity, which makes them less attractive to
                 implement.\par

                 This paper proposes a new technique for handling
                 indirect branches, called Virtual Program Counter (VPC)
                 prediction. The key idea of VPC prediction is to treat
                 a single indirect branch as multiple virtual
                 conditional branches in hardware for prediction
                 purposes. Our technique predicts each of the virtual
                 conditional branches using the existing conditional
                 branch prediction hardware. Thus, no separate storage
                 structure is required for predicting indirect branch
                 targets.\par

                 Our evaluation shows that VPC prediction improves
                 average performance by 26.7\% compared to a
                 commonly-used branch target buffer based predictor on
                 12 indirect branch intensive applications. VPC
                 prediction achieves the performance improvement
                 provided by at least a 12KB (and usually a 192KB)
                 tagged target cache predictor on half of the examined
                 applications. We show that VPC prediction can be used
                 with any existing conditional branch prediction
                 mechanism and that the accuracy of VPC prediction
                 improves when a more accurate conditional branch
                 predictor is used.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "devirtualization; indirect branch prediction; virtual
                 functions",
}

@Article{Hilton:2007:GCI,
  author =       "Andrew D. Hilton and Amir Roth",
  title =        "{Ginger}: control independence using tag rewriting",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "436--447",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250716",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The negative performance impact of branch
                 mis-predictions can be reduced by exploiting control
                 independence (CI). When a branch mis-predicts, the
                 wrong-path instructions up to the point where control
                 converges with the correct path are selectively
                 squashed and replaced with correct-path instructions.
                 Instructions beyond the convergence-point-the branch's
                 control-independent (CI) instructions-are spared from
                 squashing. Exploiting CI requires updating the input
                 data dependences of CI instructions to reflect the
                 selective removal and insertion of logically older
                 instructions and transitively re-dispatching those CI
                 instructions whose inputs have changed. This capability
                 is generally called out-of-order renaming. Previously
                 proposed CI designs use out-of-order renaming schemes
                 that either consume excessive rename/dispatch
                 bandwidth, can only be applied in limited cases, or
                 incur a cost even when the branch would be correctly
                 predicted.\par

                 Ginger is a CI design that is both general and
                 bandwidth efficient. Ginger implements out-of-order
                 renaming using tag rewriting, re-linking the input
                 dependences of CI instructions as they sit in the
                 window. To do this, Ginger halts the pipeline uses the
                 idle map table read and write ports and the issue queue
                 match lines and write lines to perform a register-tag
                 'search-and-replace' operation. After a few cycles, the
                 pipeline restarts and execution resumes with correct
                 data dependences. Cycle-level simulation shows that
                 Ginger out-performs previous CI designs, yielding
                 geometric mean speedups over an aggressive non-CI
                 processor of 5\%, 12\%, and 11\%-on SPECint2000,
                 MediaBench, and Comm-Bench-with speedups of 15\% or
                 greater on 11 of 46 programs.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "branch misprediction; control independence;
                 out-of-order renaming; selective re-dispatch",
}

@Article{Al-Zawawi:2007:TCI,
  author =       "Ahmed S. Al-Zawawi and Vimal K. Reddy and Eric
                 Rotenberg and Haitham H. Akkary",
  title =        "Transparent control independence {(TCI)}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "448--459",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250717",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Superscalar architectures have been proposed that
                 exploit control independence, reducing the performance
                 penalty of branch mispredictions by preserving the work
                 of future misprediction-independent instructions. The
                 essential goal of exploiting control independence is to
                 completely decouple future misprediction-independent
                 instructions from deferred misprediction-dependent
                 instructions. Current implementations fall short of
                 this goal because they explicitly maintain program
                 order among misprediction-independent and
                 misprediction-dependent instructions. Explicit
                 approaches sacrifice design efficiency and ultimately
                 performance.\par

                 We observe it is sufficient to emulate program order.
                 Potential misprediction-dependent instructions are
                 singled out a priori and their unchanging source values
                 are checkpointed. These instructions and values are set
                 aside as a 'recovery program'. Checkpointed source
                 values break the data dependencies with co-mingled
                 misprediction-independent instructions - now long since
                 gone from the pipeline - achieving the essential
                 decoupling objective. When the mispredicted branch
                 resolves, recovery is achieved by fetching the
                 self-sufficient, condensed recovery program. Recovery
                 is effectively transparent to the pipeline, in that
                 speculative state is not rolled back and recovery
                 appears as a jump to code. A coarse-grain retirement
                 substrate permits the relaxed order between the
                 decoupled programs. Transparent control independence
                 (TCI) yields a highly streamlined pipeline that quickly
                 recycles resources based on conventional speculation,
                 enabling a large window with small cycle-critical
                 resources, and prevents many mispredictions from
                 disrupting this large window.\par

                 TCI achieves speedups as high as 64\% (16\% average)
                 and 88\% (22\% average) for 4-issue and 8-issue
                 pipelines, respectively, among 15 SPEC integer
                 benchmarks. Factors that limit the performance of
                 explicitly ordered approaches are quantified.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "branch prediction; checkpoints; control independence;
                 selective re-execution; selective recovery;
                 speculation",
}

@Article{Wang:2007:EAA,
  author =       "Nicholas J. Wang and Aqeel Mahesri and Sanjay J.
                 Patel",
  title =        "Examining {ACE} analysis reliability estimates using
                 fault-injection",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "460--469",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1273440.1250719",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "ACE analysis is a technique to provide an early
                 reliability estimate for microprocessors. ACE analysis
                 couples data from abstract performance models with low
                 level design details to identify and rule out transient
                 faults that will not cause incorrect execution. While
                 many transient faults are analyzable in ACE analysis
                 frameworks, some are not. As a result, ACE analysis is
                 conservative and provides a lower bound for the
                 reliability of a processor design. Bounding the
                 reliability of a design is useful since it can
                 guarantee that the given design will meet reliability
                 goals.\par

                 In this work, we quantify and identify the sources of
                 ACE analysis conservatism by comparing an ACE analysis
                 methodology against a rigorous fault-injection study.
                 We evaluate two flavors of ACE analysis: a 'simple'
                 analysis and a refined analysis, finding that even the
                 refined analysis overestimates the soft error
                 vulnerability of an instruction scheduler by 2-3x. The
                 conservatism stems from two key sources: from lack of
                 detail in abstract performance models and from what we
                 term Y-Bits, a result of the single-pass simulation
                 methodology that is typical of ACE analysis. We also
                 examine the efficacy of applying ACE analysis to a
                 class of 'partial coverage' error mitigation
                 techniques. In particular, we perform a case study on
                 one such technique and extrapolate our findings to
                 others.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "fault tolerance; measurement techniques;
                 microprocessors; soft errors",
}

@Article{Aggarwal:2007:CIB,
  author =       "Nidhi Aggarwal and Parthasarathy Ranganathan and
                 Norman P. Jouppi and James E. Smith",
  title =        "Configurable isolation: building high availability
                 systems with commodity multi-core processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "470--481",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250720",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "High availability is an increasingly important
                 requirement for enterprise systems, often valued more
                 than performance. Systems designed for high
                 availability typically use redundant hardware for error
                 detection and continued uptime in the event of a
                 failure. Chip multiprocessors with an abundance of
                 identical resources like cores, cache and
                 interconnection networks would appear to be ideal
                 building blocks for implementing high availability
                 solutions on chip. However, doing so poses significant
                 challenges with respect to error containment and faulty
                 component replacement. Increasing silicon and transient
                 fault rates with future technology scaling exacerbate
                 the problem. This paper proposes a novel,
                 cost-effective, architecture for high availability
                 systems built from future multi-core processors. We
                 propose a new chip multiprocessor architecture that
                 provides configurable isolation for fault containment
                 and component retirement, based upon cost-effective
                 modifications to commodity designs. The design is
                 evaluated for a state-of-the-art industrial fault model
                 and the proposed architecture is shown to provide
                 effective fault isolation and graceful degradation even
                 when the failure rate is high.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "chip multiprocessors; fault isolation; high
                 availability",
}

@Article{Dalton:2007:RFI,
  author =       "Michael Dalton and Hari Kannan and Christos
                 Kozyrakis",
  title =        "{Raksha}: a flexible information flow architecture for
                 software security",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "482--493",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250722",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "High-level semantic vulnerabilities such as SQL
                 injection and cross-site scripting have surpassed
                 buffer overflows as the most prevalent security
                 exploits. The breadth and diversity of software
                 vulnerabilities demand new security solutions that
                 combine the speed and practicality of hardware
                 approaches with the flexibility and robustness of
                 software systems.\par

                 This paper proposes Raksha, an architecture for
                 software security based on dynamic information flow
                 tracking (DIFT). Raksha provides three novel features
                 that allow for a flexible hardware/software approach to
                 security. First, it supports flexible and programmable
                 security policies that enable software to direct
                 hardware analysis towards a wide range of high-level
                 and low-level attacks. Second, it supports multiple
                 active security policies that can protect the system
                 against concurrent attacks. Third, it supports
                 low-overhead security handlers that allow software to
                 correct, complement, or extend the hardware-based
                 analysis without the overhead associated with operating
                 system traps.\par

                 We present an FPGA prototype for Raksha that provides a
                 full featured Linux workstation for security analysis.
                 Using unmodified binaries for real-world applications,
                 we demonstrate that Raksha can detect high-level
                 attacks such as directory traversal, command injection,
                 SQL injection, and cross-site scripting as well as
                 low-level attacks such as buffer overflows. We also
                 show that low overhead exception handling is critical
                 for analyses such as memory corruption protection in
                 order to address false positives that occur due to the
                 diverse code patterns in frequently used software.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "dynamic; semantic vulnerabilities; software security",
}

@Article{Wang:2007:NCD,
  author =       "Zhenghong Wang and Ruby B. Lee",
  title =        "New cache designs for thwarting software cache-based
                 side channel attacks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "494--505",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250723",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Software cache-based side channel attacks are a
                 serious new class of threats for computers. Unlike
                 physical side channel attacks that mostly target
                 embedded cryptographic devices, cache-based side
                 channel attacks can also undermine general purpose
                 systems. The attacks are easy to perform, effective on
                 most platforms, and do not require special instruments
                 or excessive computation power. In recently
                 demonstrated attacks on software implementations of
                 ciphers like AES and RSA, the full key can be recovered
                 by an unprivileged user program performing simple
                 timing measurements based on cache misses.\par

                 We first analyze these attacks, identifying cache
                 interference as the root cause of these attacks. We
                 identify two basic mitigation approaches: the
                 partition-based approach eliminates cache interference
                 whereas the randomization-based approach randomizes
                 cache interference so that zero information can be
                 inferred. We present new security-aware cache designs,
                 the Partition-Locked cache (PLcache) and Random
                 Permutation cache (RPcache), analyze and prove their
                 security, and evaluate their performance. Our results
                 show that our new cache designs with built-in security
                 can defend against cache-based side channel attacks in
                 general-rather than only specific attacks on a given
                 cryptographic algorithm-with very little performance
                 degradation and hardware cost.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "cache; computer architecture; processor; security;
                 side channel; timing attacks",
}

@Article{Soundararajan:2007:MBV,
  author =       "Niranjan Kumar Soundararajan and Angshuman Parashar
                 and Anand Sivasubramaniam",
  title =        "Mechanisms for bounding vulnerabilities of processor
                 structures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "506--515",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250725",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Concern for the increasing susceptibility of processor
                 structures to transient errors has led to several
                 recent research efforts that propose architectural
                 techniques to enhance reliability. However, real
                 systems are typically required to satisfy hard
                 reliability budgets, and barring expensive
                 full-redundancy approaches, none of the proposed
                 solutions treat any reliability budgets or bounds as
                 hard constraints. Meeting vulnerability bounds requires
                 monitoring vulnerabilities of processor structures and
                 taking appropriate actions whenever these bounds are
                 violated. This mandates treating reliability as a
                 first-order microarchitecture design constraint, while
                 optimizing performance as long as reliability
                 requirements are satisfied. This paper makes three key
                 contributions towards this goal: (i) we present a
                 simple infrastructure to monitor and provide upper
                 bounds on the vulnerabilities of key processor
                 structures at cycle-level fidelity; (ii) we propose two
                 distinct control mechanisms - throttling and selective
                 redundancy - to proactively and/or reactively bound the
                 vulnerabilities to any limit specified by the system
                 designer; (iii) within this framework, we propose a
                 novel adaptation of Out-of-Order Commit for
                 vulnerability reduction, which automatically provides
                 additional leverage for the control mechanisms to boost
                 performance while remaining within the reliability
                 budget.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "microarchitecture; redundant threading; transient
                 faults",
}

@Article{Walcott:2007:DPA,
  author =       "Kristen R. Walcott and Greg Humphreys and Sudhanva
                 Gurumurthi",
  title =        "Dynamic prediction of architectural vulnerability from
                 microarchitectural state",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "2",
  pages =        "516--527",
  month =        may,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1250662.1250726",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:43 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Transient faults due to particle strikes are a key
                 challenge in microprocessor design. Driven by
                 exponentially increasing transistor counts, per-chip
                 faults are a growing burden. To protect against soft
                 errors, redundancy techniques such as redundant
                 multithreading (RMT) are often used. However, these
                 techniques assume that the probability that a
                 structural fault will result in a soft error (i.e., the
                 Architectural Vulnerability Factor (AVF)) is 100
                 percent, unnecessarily draining processor resources.
                 Due to the high cost of redundancy, there have been
                 efforts to throttle RMT at runtime. To date, these
                 methods have not incorporated an AVF model and
                 therefore tend to be ad hoc. Unfortunately, computing
                 the AVF of complex microprocessor structures (e.g., the
                 ISQ) can be quite involved.\par

                 To provide probabilistic guarantees about fault
                 tolerance, we have created a rigorous characterization
                 of AVF behavior that can be easily implemented in
                 hardware. We experimentally demonstrate AVF variability
                 within and across the SPEC2000 benchmarks and identify
                 strong correlations between structural AVF values and a
                 small set of processor metrics. Using these simple
                 indicators as predictors, we create a proof-of-concept
                 RMT implementation that demonstrates that AVF
                 prediction can be used to maintain a low fault
                 tolerance level without significant performance
                 impact.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "architecture vulnerability factor; microarchitecture;
                 performance; redundant multithreading; reliability",
}

@Article{Aggarwal:2007:ISI,
  author =       "Aneesh Aggarwal and Pradip Bose and Mohamed Zahran",
  title =        "Introduction to the special issue on the {2006
                 Reconfigurable and Adaptive Architecture Workshop}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "3",
  pages =        "1--1",
  month =        jun,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1294313.1294317",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:27 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The papers that follow comprise the proceedings of the
                 first Reconfigurable and Adaptive Architecture Workshop
                 (RAAW 2006) that was held in conjunction with the
                 39$^{th}$ International Conference on Microarchitecture
                 in Orlando, Florida.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bellas:2007:MSA,
  author =       "Nikolaos Bellas and Sek M. Chai and Malcolm Dwyer and
                 Dan Linzmeier",
  title =        "Mapping streaming architectures on reconfigurable
                 platforms",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "3",
  pages =        "2--8",
  month =        jun,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1294313.1294318",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:27 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Hardware accelerators, used as application-specific
                 extensions to the computational capabilities of a
                 system, are efficient mechanisms to enhance the
                 performance and reduce the power dissipation in a
                 System On Chip (SoC). These accelerators execute on the
                 computationally critical part of the application, and
                 offload computations from the scalar processors. In
                 this paper, we present a design automation tool that
                 generates accelerators based on a given application
                 kernel. The accelerators are processing streaming data,
                 and support a programming model which can naturally
                 express a large number of embedded applications, and
                 which results in efficient and fast hardware
                 implementations. We demonstrate the applicability of
                 the tool for architectural space exploration for a
                 number of media applications, with results on area,
                 throughput, and clock speeds.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Labrecque:2007:CCG,
  author =       "Martin Labrecque and Peter Yiannacouras and J. Gregory
                 Steffan",
  title =        "Custom code generation for soft processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "3",
  pages =        "9--19",
  month =        jun,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1294313.1294319",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:27 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Embedded systems designers that use FPGAs are
                 increasingly including soft processors in their designs
                 (configurable processors built in the programmable
                 logic of the FPGA). While there has been a significant
                 amount of research on adding custom instructions and
                 accelerators to soft processors, these are typically
                 used to extend an unmodified base ISA targeted by
                 generic compilation such as with unmodified gcc. In
                 this paper we explore several opportunities for the
                 compiler to optimize the code generated for soft
                 processors through application-specific customization
                 of the base ISA---techniques that are orthogonal to
                 adding custom instructions. In particular we explore:
                 (i) low level software-hardware trade-offs between
                 basic instructions; (ii) the utility of ISA-specific
                 features---in particular for the delay slots and Hi/Lo
                 registers in the MIPS ISA; and (iii) application
                 specific register management. We find that through
                 these techniques that have no hardware cost we can
                 improve the area efficiency of soft processors by 12\%
                 on average across a suite of benchmarks, and by up to
                 47\% in the best case.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Suri:2007:IIL,
  author =       "Tameesh Suri",
  title =        "Improving instruction level parallelism through
                 reconfigurable units in superscalar processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "3",
  pages =        "20--27",
  month =        jun,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1294313.1294320",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:27 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "With reducing feature sizes, more transistors can be
                 integrated on the chip. The increased transistor budget
                 can be utilized to improve the instruction level
                 parallelism (ILP) exploited from the processor.
                 However, the transistors cannot be used to arbitrarily
                 increase the processor width and size in the hope of
                 exploiting better ILP. In this paper, we propose an
                 architecture where the superscalar datapath is tightly
                 coupled with a reconfigurable unit (RFU). The
                 reconfiguration unit is configured to execute the
                 traces of dynamic instructions that are frequently
                 executed. To address the data dependency issues between
                 the instructions in the superscalar and the RFU, we
                 propose to execute the trace on the RFU with predicted
                 values. When the trace instructions reach the issue
                 queue in the superscalar, the predictions are
                 validated. In this technique, performance improvement
                 is obtained for correct prediction, whereas no
                 performance degradation is incurred for mispredictions.
                 With this architecture, we observe an average
                 instructions per cycle (IPC) improvement of about 11\%
                 over the simulated SPEC 2000 benchmarks, using a very
                 small last value data value predictor.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Najaf-abadi:2007:ACE,
  author =       "Hashem H. Najaf-abadi and Eric Rotenberg",
  title =        "Architectural {\em contesting\/}: exposing and
                 exploiting temperamental behavior",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "3",
  pages =        "28--35",
  month =        jun,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1294313.1294321",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:27 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Previous studies have proposed techniques to
                 dynamically change the architecture of a processor to
                 better suit the characteristics of the workload at
                 hand. However, all such approaches are prone to a
                 fundamental trade-off between the architectural
                 diversity they can provide and the latency of
                 architectural change, their fixed-configuration
                 performance and the complexity of finding the best
                 architectural configuration for the workload at hand.
                 In this study we argue that the full potential of
                 dynamic architectural customization can only be
                 achieved by diminishing the effect of the degree of
                 available architectural diversity on the aforementioned
                 performance factors.\par

                 The performance of a statically designed processing
                 core in a heterogeneous multi-core system is
                 independent of the architectural diversity available.
                 In addition, it is apparent that concurrent execution
                 of code on differently architected cores automatically
                 reveals which architecture is more suitable for the
                 characteristics of a particular workload.\par

                 We therefore propose architectural contesting; the
                 redundant execution of code on a number of differently
                 architected processors (each customized for a different
                 set of workload characteristics) in a leader follower
                 arrangement, such that the leader and follower cores
                 continuously shift roles as one core or the other
                 becomes more favorable for new code phases. In this
                 manner effective execution is naturally transferred
                 from one static architecture to the other with little
                 latency.\par

                 In this study, we show that the contesting of only
                 processor width can yield an average speedup of 7.5\%
                 and up to 12.5\% in integer SPEC benchmarks.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tseng:2007:DHS,
  author =       "Kuo-Kun Tseng and Ying-Dar Lin and Tsern-Huei Lee and
                 Yuan-Cheng Lai",
  title =        "Deterministic high-speed root-hashing automaton
                 matching coprocessor for embedded network processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "3",
  pages =        "36--43",
  month =        jun,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1294313.1294314",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:27 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "While string matching plays an important role in deep
                 packet inspection applications, its software algorithms
                 are insufficient to meet the demands of high-speed
                 performance. Accordingly, we were motivated to propose
                 fast and deterministic performance root-hashing
                 automaton matching (RHAM) coprocessor for embedded
                 network processor. Although automaton algorithms are
                 robust with deterministic matching time, there is still
                 plenty of room for improvement of their average-case
                 performance. The proposed RHAM employs novel
                 root-hashing technique to accelerate automaton
                 matching. In our experiment, RHAM is implemented in a
                 prevalent automaton algorithm, Aho--Corasick (AC) which
                 is often used in many packet inspection applications.
                 Compared to the original AC, RHAM only requires extra
                 vector size in 48 Kbytes for root-hashing, and has
                 about 900\% and 420\% outperformance for 20,000 URLs
                 and 10,000 virus patterns respectively. Implementation
                 of RHAM FPGA can perform at the rate of 12.6 Gbps with
                 the pattern amount in 34,215 bytes. This is superior to
                 all previous matching hardware in terms of throughput
                 and pattern set.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "coprocessor; finite automaton; hashing; packet
                 inspection; string matching",
}

@Article{Sibai:2007:PAW,
  author =       "Fadi N. Sibai",
  title =        "Performance analysis and workload characterization of
                 the {$3$DMark05} benchmark on modern parallel computer
                 platforms",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "3",
  pages =        "44--52",
  month =        jun,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1294313.1294315",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:27 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "With ever increasing CPU and graphics card speeds, and
                 improved sophistication, stunning visual effects, and
                 growing scene detail and real life-like content of 3D
                 games, 3DMark{\reg} emerged as the leading PC benchmark
                 for 3D gaming performance with several millions of
                 worldwide downloads. Its tests are at the cutting edge
                 of consumer graphics and push the limit of 3D rendering
                 with spectacular scenes, and state of the art lighting
                 techniques. The benchmark scores help quickly
                 differentiate the platforms with state of the art
                 graphic cards and processors from those with older
                 components. In this paper, we analyze the scaling of
                 the 3DMark{\reg}05 benchmark with CPU frequency, number
                 of CPUs, number of GPUs, and number of threads
                 supported by the hardware. We also characterize the
                 benchmark's workload. These results reveal that the
                 benchmark scales well indicating that 3D games if
                 implemented with multiple Physics and Artificial
                 Intelligence or other relevant content threads should
                 show good scaling too on multi-CPU and multi-GPU
                 platforms. The characterization results reveal the
                 close dependence of 3D graphics applications on the
                 memory subsystem's performance as 1 out of 2
                 instructions is a load or store instruction. The
                 results also revealed that there is a direct
                 correlation with the Game Tests' performance and the
                 number of cache memory read misses per instruction
                 retired, the number of stores retired per instruction
                 retired, the number of polygons per Draw*Primitive; and
                 the number of set-vertex shader calls per frame. All
                 these events relate to the memory subsystem performance
                 generally linking the 3D graphics applications'
                 performance and the 3DMark{\reg} overall score to the
                 platform's memory performance. Salient
                 microarchitectural performance events of the CPU tests
                 were also memory-related.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "3D graphics performance; multiple CPU and GPU core
                 platforms; workload characterization",
}

@Article{Thorson:2007:INb,
  author =       "Mark Thorson",
  title =        "{Internet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "3",
  pages =        "53--55",
  month =        jun,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1294313.1294323",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:48:27 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This column consists of selected traffic from the
                 comp.arch newsgroup, a forum for discussion of computer
                 architecture on the Internet---an international
                 computer network.\par

                 As always, the opinions expressed in this column are
                 the personal views of the authors, and do not
                 necessarily represent the institutions to which they
                 are affiliated.\par

                 Text which sets the context of a message appears
                 underlined or in italics; this is usually text the
                 author has quoted from earlier messages. The code-like
                 expressions below the authors' names are their
                 addresses on Internet.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bartolini:2007:MPD,
  author =       "S. Bartolini and P. Foglia and C. A. Prete",
  title =        "{MEmory} performance: {DEaling} with applications,
                 systems and architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "4",
  pages =        "4--5",
  month =        sep,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1327312.1327314",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:50:54 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In this issue, we present the papers from MEDEA-2006
                 Workshop [3] held in conjunction with the IEEE-ACM
                 International Conference on Parallel Architectures and
                 Compilation Techniques (PACT-2006) [1,2].",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Medea 2006 workshop.",
}

@Article{Lorton:2007:ABL,
  author =       "K. Patrick Lorton and David S. Wise",
  title =        "Analyzing block locality in {Morton}-order and
                 {Morton}-hybrid matrices",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "4",
  pages =        "6--12",
  month =        sep,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1327312.1327315",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:50:54 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "As the architectures of computers change, introducing
                 more caches onto multicore chips, even more locality
                 becomes necessary. With the bandwidth between caches
                 and RAM now even more valuable, additional locality
                 from new matrix representations will be important to
                 keep multiple processors busy. The default storage
                 representations of both C and Fortran, row- and
                 column-major respectively, have fundamental
                 deficiencies with many matrix computations. By
                 switching the storage representation from Cartesian to
                 block indices, one is able to take better advantage of
                 cache locality at all levels from L1 to paging. This
                 paper only changes storage representation from
                 row-major to Morton-hybrid, and applies it to matrix
                 multiplication. Its purpose is to show that, even with
                 only traditional iterative algorithms, simply changing
                 storage representation offers significant speedups.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "Cholesky factorization; Morton order; quadtrees",
  remark =       "Medea 2006 workshop.",
}

@Article{Deris:2007:ICE,
  author =       "Kaveh Jokar Deris and Amirali Baniasadi",
  title =        "Investigating cache energy and latency break-even
                 points in high performance processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "4",
  pages =        "13--20",
  month =        sep,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1327312.1327316",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:50:54 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In this work we study how cache complexity impacts
                 energy and performance in high performance processors.
                 Moreover, we estimate cache energy budget for two high
                 performance processors. We calculate energy and latency
                 break-even points for realistic and ideal cache
                 organizations for different applications. We show that
                 design efforts made to reduce cache miss rate are only
                 justifiable from the energy and performance point of
                 view only if the associated latency and energy overhead
                 remain below the calculated break-even
                 points.\par

                 Furthermore, we show that, for the processors and
                 applications studied here, the instruction cache has a
                 lower latency break-even point compared to the data
                 cache. However, investing energy in the data cache is
                 likely to result in better energy efficiency compared
                 to the instruction cache.\par

                 We also study alternative cache configurations for
                 different processors and investigate if such
                 alternatives would improve energy efficiency.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Medea 2006 workshop.",
}

@Article{Yan:2007:EIC,
  author =       "Jun Yan and Wei Zhang",
  title =        "Evaluating instruction cache vulnerability to
                 transient errors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "4",
  pages =        "21--28",
  month =        sep,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1327312.1327317",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:50:54 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Recent research shows that microprocessors are
                 increasingly susceptible to transient errors. In order
                 to protect microprocessors cost-effectively, the first
                 step is to accurately understand the impact of
                 transient errors on the system reliability. While many
                 research efforts have been focused on studying the
                 vulnerability of data caches and other on-chip hardware
                 components, instruction caches have received less
                 attention. However, instructions are read every cycle,
                 any undetected or uncorrected soft errors in
                 instructions can lead to erroneous computation, wrong
                 control flow or system crash.\par

                 This paper studies the instruction cache vulnerability
                 by considering both the raw SRAM rate and the cache
                 vulnerability factor. Based on the concept of cache
                 vulnerability factor, we also investigate the impact of
                 different cache configuration parameters on the
                 reliability of instruction caches. We find that on
                 average 67.5\% of instruction cache soft errors can be
                 masked by the I-cache itself without impacting other
                 system components. While quantifying the instruction
                 cache vulnerability itself does not solve the
                 reliability problem of instruction cache against
                 transient errors, we believe this work can provide
                 useful insights for designers to develop cost-effective
                 solutions to protect I-caches and to optimally balance
                 the reliability of instruction caches with other system
                 goals, such as cost, performance and energy.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Medea 2006 workshop.",
}

@Article{Ramirez:2007:EST,
  author =       "Tanaus{\'u} Ram{\'\i}rez and Alex Pajuelo and Oliverio
                 J. Santana and Mateo Valero",
  title =        "Energy saving through a simple load control
                 mechanism",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "4",
  pages =        "29--36",
  month =        sep,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1327312.1327318",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:50:54 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "To alleviate the memory wall problem, current
                 architectural trends suggest implementing large
                 instruction windows able to maintain a high number of
                 in-flight instructions. However, the benefits achieved
                 by these recent proposals may be limited because more
                 instructions are executed down the wrong path of a
                 mispredicted branch. The larger number of misspeculated
                 instructions involves increasing the energy consumed
                 compared to traditional designs with smaller
                 instruction windows. Our analysis shows that, for some
                 SPEC2000 integer benchmarks, up to 2, 5X wrong-path
                 load instructions are executed when the instruction
                 window of a 4-way superscalar processor is increased
                 from 256 to 1024 entries.\par

                 This paper describes a simple speculative control
                 technique to prevent wrong-path load instructions from
                 being executed. Our technique extends the functionality
                 of the load-store queue to block those load
                 instructions that depend on a hard-to-predict
                 conditional branch until it is resolved. If the branch
                 is actually mispredicted, unnecessary cache misses can
                 be avoided, saving energy down the wrong path.
                 Furthermore, instructions that depend on a blocked load
                 are not issued because their source values are not
                 available, which also saves dynamic energy. Our results
                 show that the proposed mechanism reduces, on average,
                 up to 26\% misspeculated load instructions and 18\%
                 wrong-path instructions without any performance loss.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "branch prediction; confidence estimation; energy
                 saving; kilo-instruction processors",
  remark =       "Medea 2006 workshop.",
}

@Article{Ramos:2007:DPC,
  author =       "Luis M. Ramos and Jos{\'e} Luis Briz and Pablo E.
                 Ib{\'a}{\~n}ez and Victor Vi{\~n}als",
  title =        "Data prefetching in a cache hierarchy with high
                 bandwidth and capacity",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "4",
  pages =        "37--44",
  month =        sep,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1327312.1327319",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:50:54 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In this paper we evaluate four hardware data
                 prefetchers in the context of a high-performance
                 three-level on chip cache hierarchy with high bandwidth
                 and capacity. We consider two classic prefetchers
                 (Sequential Tagged and Stride) and two correlating
                 prefetchers: PC/DC, a recent method with a superior
                 score and low-sized tables, and P-DFCM, a new method.
                 Like PC/DC, P-DFCM focuses on local delta sequences,
                 but it is based on the DFCM value predictor. We explore
                 different prefetch degrees and distances. Running
                 SPEC2000, Olden and IAbench applications, results show
                 that this kind of cache hierarchy turns prefetching
                 aggressiveness into success for the four prefetchers.
                 Sequential Tagged is the best, and deserves further
                 attention to cut it losses in some applications. PC/DC
                 results are matched or even improved by P-DFCM, using
                 far fewer accesses to tables while keeping sizes low.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "hardware data prefeching",
  remark =       "Medea 2006 workshop.",
}

@Article{Dybdahl:2007:LBR,
  author =       "Haakon Dybdahl and Per Stenstr{\"o}m and Lasse
                 Natvig",
  title =        "An {LRU}-based replacement algorithm augmented with
                 frequency of access in shared chip-multiprocessor
                 caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "4",
  pages =        "45--52",
  month =        sep,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1327312.1327320",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:50:54 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This paper proposes a new replacement algorithm to
                 protect cache lines with potential future reuse from
                 being evicted. In contrast to the recency based
                 approaches used in the past (LRU for example), our
                 algorithm also uses the notion of frequency of access.
                 Instead of evicting the least recently used block, our
                 algorithm identifies among a set of LRU blocks the one
                 that is also least-frequently-used (according to a
                 heuristic) and chooses that as a victim. We have
                 implemented this replacement algorithm in a detailed
                 simulation model of a chip multiprocessor system driven
                 by SPEC2000 benchmarks. We have found that the new
                 scheme improves performance for memory intensive
                 applications. Moreover, as compared to other attempts,
                 our replacement algorithm provides robust improvements
                 across all benchmarks. We have also extended an earlier
                 scheme proposed by Wong and Baer so it is switched off
                 when performance is not improved. Our results show that
                 this makes the scheme much more suitable for CMP
                 configurations.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Medea 2006 workshop.",
}

@Article{Bardine:2007:IPE,
  author =       "A. Bardine and P. Foglia and G. Gabrielli and C. A.
                 Prete and P. Stenstr{\"o}m",
  title =        "Improving power efficiency of {D-NUCA} caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "4",
  pages =        "53--58",
  month =        sep,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1327312.1327321",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:50:54 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "D-NUCA caches are cache memories that, thanks to
                 banked organization, broadcast search and
                 promotion/demotion mechanism, are able to tolerate the
                 increasing wire delay effects introduced by technology
                 scaling. As a consequence, they will outperform
                 conventional caches (UCA, Uniform Cache Architectures)
                 in future generation cores.\par

                 Due to the promotion/demotion mechanism, we have found
                 that, in a D-NUCA cache, the distribution of hits on
                 the ways varies across applications as well as across
                 different execution phases within a single application.
                 In this paper, we show how such a behavior can be
                 utilized to improve D-NUCA power efficiency as well as
                 to decrease its access latencies. In particular, we
                 propose a new D-NUCA structure, called Way Adaptable
                 D-NUCA cache, in which the number of active (i.e.
                 powered-on) ways is dynamically adapted to the need of
                 the running application. Our initial evaluation shows
                 that a consistent reduction of both the average number
                 of active ways (42\% in average) and the number of bank
                 access requests (29\% in average) is achieved, without
                 significantly affecting the IPC.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  remark =       "Medea 2006 workshop.",
}

@Article{Thorson:2007:INc,
  author =       "Mark Thorson",
  title =        "{Internet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "4",
  pages =        "59--62",
  month =        sep,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1327312.1327323",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:50:54 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This column consists of selected traffic from the
                 comp. arch newsgroup, a forum for discussion of
                 computer architecture on the Internet---an
                 international computer network.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kise:2007:SIA,
  author =       "Kenji Kise and Toshinori Sato and Hironori Nakajo",
  title =        "Special issue: {ALPS'07 -- Advanced Low Power
                 Systems}: Introduction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "5",
  pages =        "1--2",
  month =        dec,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1360464.1360469",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:13 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In this issue, we present the papers from the
                 proceedings of the 2nd International Workshop on
                 Advanced Low Power Systems (ALPS 2007) that was held in
                 conjunction with the 21st International Conference on
                 Supercomputing in Seattle.\par

                 'Thoughtfulness' is an important keyword in the both
                 current and future technologies in all over the world:
                 Thoughtful to human being, thoughtful to our
                 surroundings, thoughtful to the earth, and so on. For
                 the thoughtfulness, Low-power is believed to be one of
                 the most indispensable keyword. The ALPS workshop
                 focuses on the current technological challenges in
                 developing low-power and power-aware computing systems
                 ranging from servers to embedded devices. The goal of
                 the workshop is to bring all aspects of power-aware
                 computing from industry and academia.\par

                 This year, we have one invited talk entitled 'An Under
                 2W 100GOPS Video Recognition Processor Based on a
                 Linear Array of 128 4-Way VLIW Processing Elements' by
                 Shorin Kyo (NEC Corporation) and 6 papers selected
                 based on the full paper review by the program committee
                 members.\par

                 The first set of papers discusses low-power designs. We
                 have three papers: 'Optimal Pipeline Depth with
                 Pipeline Stage Unification Adoption' by Jun Yao, Hajime
                 Shimada, Shinobu Miwa, and Shinji Tomita, 'VCLEARIT: A
                 VLSI CMOS Circuit Leakage Reduction Technique For
                 Nanoscale Technologies' by Preetham Lakshmikanthan and
                 Adrian Nunez, and 'Leakage Energy Reduction in Cache
                 Memory by Data Compression' by Kiyofumi Tanaka and
                 Takahiro Kawahara.\par

                 The second set of papers: 'Preventing Timing Errors on
                 Register Writes: Mechanisms of Detections and
                 Recoveries' by Hidetsugu Irie, Ken Sugimoto, Masahiro
                 Goshima, and Suichi Sakai, 'Not Multi-, but Many-Core:
                 Designing Integral Parallel Architectures for Embedded
                 Computation' by Mihaela Malita, Gheorghe Stefany, and
                 Dominique Thi{\'e}baut, and 'Fine-grain Compensation
                 Method with Consideration of Trade-offs between
                 Computation and Data Transfer for Power Consumption' by
                 Takefumi Miyoshi and Nobuhiko Sugino, covers
                 reliability, many-core and parallelization
                 issues.\par

                 All papers here are going to create the way to the new
                 aspects of low-power systems. We hope you will find the
                 papers of this special issue of Computer Architecture
                 News to be stimulating and that you will be inspired to
                 contribute your efforts to the future low power
                 systems.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Yao:2007:OPD,
  author =       "Jun Yao and Shinobu Miwa and Hajime Shimada and Shinji
                 Tomita",
  title =        "Optimal pipeline depth with pipeline stage unification
                 adoption",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "5",
  pages =        "3--9",
  month =        dec,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1360464.1360470",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:13 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "To find the optimal pipeline design point by
                 considering both performance and power objectives has
                 been one focus of interest in recent researches.
                 However, we found that previous papers did not consider
                 deepening or shrinking pipeline depth dynamically
                 during the program execution. In this paper, with the
                 adoption of the earlier proposed Pipeline Stage
                 Unification (PSU) method, we studied the relationship
                 between power/performance and pipeline depth in
                 processors with a pipeline of multi-usable depths. Our
                 evaluation results of SPECint2000 benchmarks shown in
                 this paper illustrate that the PSU adoption can achieve
                 good efficiency for platforms which concern both energy
                 and performance, even after the utilization of complex
                 clock gating.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "pipeline design point; pipeline stage unification;
                 power/performance",
}

@Article{Lakshmikanthan:2007:VVC,
  author =       "Preetham Lakshmikanthan and Adrian Nu{\~n}ez",
  title =        "{VCLEARIT}: a {VLSI CMOS} circuit leakage reduction
                 technique for nanoscale technologies",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "5",
  pages =        "10--16",
  month =        dec,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1360464.1360471",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:13 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Leakage power loss is a major concern in
                 deep-submicron technologies as it drains the battery
                 even when a circuit is completely idle. In this paper,
                 we first present a novel leakage reduction technique
                 and then compare and contrast it with other well
                 established leakage reduction techniques. Our leakage
                 reduction technique achieves cancellation of leakage
                 effects in both the pull-up network (PUN) as well as
                 the pull-down network (PDN) for CMOS circuits. It
                 involves voltage balancing in the PUN and PDN paths
                 using a combination of high- V$_T$ (high voltage
                 threshold) and standard- V$_T$ sleep transistors.
                 Experiments conducted on a variety of multi-level
                 combinational MCNC'91 benchmarks show significant
                 savings in leakage power (upto 3 orders of magnitude),
                 with lesser area and delay penalty using our leakage
                 reduction technique when compared to other
                 techniques.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tanaka:2007:LER,
  author =       "Kiyofumi Tanaka and Takahiro Kawahara",
  title =        "Leakage energy reduction in cache memory by data
                 compression",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "5",
  pages =        "17--24",
  month =        dec,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1360464.1360472",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:13 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Cache memory is effective in bridging a growing speed
                 gap between a processor and relatively slow external
                 main memory. Almost all of today's commercial
                 processors, not only high-performance microprocessors
                 but embedded ones, have on-chip cache memories.
                 However, energy consumption in the cache memory would
                 approach or exceed 50\% of the total consumption by the
                 processors, which leads to a serious problem in terms
                 of allowable temperature and performance improvement.
                 An important point to note is that, in the near future,
                 static (leakage) energy will dominate the energy
                 consumption in deep sub-micron processes. In this
                 paper, we propose cache memory architecture that
                 exploits gated-Vdd control per cache block and a
                 dynamic data compression scheme in the secondary cache,
                 and achieves efficient reduction of static energy
                 consumed by the secondary cache memory. In the
                 simulation using SPEC95 integer benchmarks, our
                 technique reduced about 45\% of leakage energy in the
                 cache at maximum, and about 28\% on average.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "cache memory; data compression; gated-Vdd; leakage
                 energy",
}

@Article{Irie:2007:PTE,
  author =       "Hidetsugu Irie and Ken Sugimoto and Masahiro Goshima
                 and Shuich Sakai",
  title =        "Preventing timing errors on register writes:
                 mechanisms of detections and recoveries",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "5",
  pages =        "25--31",
  month =        dec,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1360464.1360473",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:13 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "To deal with the increasing variations of the
                 intra-chip transistors, one promising approach is to
                 dynamically detect and recover the timing-errors with
                 microarchitecutre. This will induce dependability and
                 efficiency into microprocessors because it allows VLSI
                 to operate at the optimum frequency and voltage while
                 ensuring accuracy.\par

                 A few approaches for dynamically detecting
                 timing-errors have been proposed, but none of them have
                 focused on register writes. In this paper, we propose a
                 technique for detecting and recovering from timing
                 errors during register writes. We introduce a verifying
                 technique that uses additional buffer (called the write
                 assurance buffer (WAB)) which is provided with a
                 sufficient timing margin. The evaluation results reveal
                 a performance degradation of 4.5\% using an 8-entry
                 WAB; this value becomes negligible when a 16-entry WAB
                 is used.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Malita:2007:MMC,
  author =       "Mihaela Mali{\c{t}}a and Gheorghe {\c{S}}tefan and
                 Dominique Thi{\'e}baut",
  title =        "Not multi-, but many-core: designing integral parallel
                 architectures for embedded computation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "5",
  pages =        "32--38",
  month =        dec,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1360464.1360474",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:13 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Recent embedded systems have switched to fully
                 programmable parallel architectures. To make sure all
                 corner cases usually present in real applications are
                 supported and efficiently implemented in this switch of
                 implementation, new solutions must be found. We
                 introduce the integral parallel architecture (IPA) as a
                 solution supporting intensive data computation in
                 System-on-a-chip (Soc) implementations, fitting in a
                 small area, and requiring low power. An IPA supports
                 naturally all three possible styles of parallelism:
                 data, time, and speculative.\par

                 As an illustrative example, we present the BA1024 chip,
                 a fully programmable SoC designed by BrightScale, Inc.
                 for HDTV codecs. Its main performance figures include
                 60 GOPS/Watt and 2 GOPS/mm$^2$, representing an
                 efficient IPA approach for embedded computation.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "embedded systems; parallel architectures; programmable
                 systems; video processing",
}

@Article{Miyoshi:2007:FGC,
  author =       "Takefumi Miyoshi and Nobuhiko Sugino",
  title =        "Fine-grain compensation method with consideration of
                 trade-offs between computation and data transfer for
                 power consumption",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "5",
  pages =        "39--44",
  month =        dec,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1360464.1360475",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:13 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Fine-grain parallelizing method with consideration of
                 the number of data transfers for low power consumption
                 is proposed. In the proposed method, power consumption
                 by data transfers between processor elements in a
                 multiprocessor is focused on, and the number of data
                 transfers is reduced.\par

                 In this paper, a measure based on the relationship
                 between variables in a given program is defined to
                 evaluate the number of data transfers, firstly. And
                 then a proposed compensation method by use of the
                 evaluation of power consumption based on the measure is
                 explained. Finally, the result of applying proposed
                 compensation method implemented on COINS framework to
                 several example programs is shown.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Romanescu:2007:VSC,
  author =       "Bogdan F. Romanescu and Michael E. Bauer and Sule Ozev
                 and Daniel J. Sorin",
  title =        "{VariaSim}: simulating circuits and systems in the
                 presence of process variability",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "5",
  pages =        "45--48",
  month =        dec,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1360464.1360465",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:13 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In this paper, we present VariaSim, the publicly
                 available Static Statistical Timing Analysis (SSTA)
                 Tool from Duke University. VariaSim enables researchers
                 to analyze the impact of CMOS process variability on
                 the behavior of circuits and systems.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Venkateswaran:2007:FGSa,
  author =       "N. Venkateswaran and Deepak Srinivasan and Madhavan
                 Manivannan and T. P. Ramnath Sai Sagar and Shyamsundar
                 Gopalakrishnan and VinothKrishnan Elangovan and Karthik
                 Chandrasekar and Prem Kumar Ramesh and Viswanath
                 Venkatesan and Arvindakshan Babu and Sudharshan",
  title =        "Future generation supercomputers {I}: a paradigm for
                 node architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "5",
  pages =        "49--60",
  month =        dec,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1360464.1360466",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:13 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "As a result of the increasing requirements of present
                 and future computation intensive applications, there
                 have been many fundamentally divergent approaches such
                 as the Blue-Gene, TRIPS, HERO, Cascade spurred in order
                 to provide increased performance at node level in
                 supercomputing clusters. The design of the node
                 architecture should be such that 'Cost-Effective
                 Supercomputing' is realized without compromising on the
                 requirements of the ever-performance hungry grand
                 challenge applications. However, to increase
                 performance at the cluster level, scalability and
                 likewise tackling the mapping complexity across the
                 large cluster of nodes becomes critical. The potential
                 of such a node architecture can be fully exploited only
                 with an appropriate cluster architecture. In an attempt
                 to address these issues for efficient and
                 Cost-Effective Supercomputing, we propose a novel
                 paradigm for designing High Performance Clusters, in
                 two papers. In paper-II, we discuss the design of
                 operating system and cluster architecture. In this
                 paper, we present a node architecture model based on
                 the Memory In Processor paradigm and discuss the
                 related architectural aspects (ISA, compiler, network
                 interconnection etc). We provide a design space based
                 on the proposed model for which a simulator is
                 developed, with the help of which the performance of
                 such a node architecture is outlined.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Venkateswaran:2007:FGSb,
  author =       "N. Venkateswaran and Deepak Srinivasan and Madhavan
                 Manivannan and T. P. Ramnath Sai Sagar and Shyamsundar
                 Gopalakrishnan and VinothKrishnan Elangovan and Arvind
                 M. and Prem Kumar Ramesh and Karthik Ganesan and
                 Viswanath Krishnamurthy and Sivaramakrishnan",
  title =        "Future generation supercomputers {II}: a paradigm for
                 cluster architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "5",
  pages =        "61--70",
  month =        dec,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1360464.1360467",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:13 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In part-I, a novel multi-core node architecture was
                 proposed which when employed in a cluster environment
                 would be capable of tackling computational complexity
                 associated with wide class of applications.
                 Furthermore, it was discussed that by appropriately
                 scaling the architectural specifications, Teraops
                 computing power could be achieved at the node level. In
                 order to harness the computational power of such a
                 node, we have developed an efficient application
                 execution model with a competent cluster architectural
                 backbone. In this paper we present the novel cluster
                 paradigm, dealing with operating system design,
                 parallel programming model and cluster interconnection
                 network. Our approach in developing the competent
                 cluster design revolves around an execution model to
                 aid the execution of multiple applications
                 simultaneously on all partitions of the cluster,
                 leading to cost sharing across applications. This would
                 be a major initiative towards achieving Cost-Effective
                 Supercomputing.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2007:INd,
  author =       "Mark Thorson",
  title =        "{Internet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "35",
  number =       "5",
  pages =        "71--73",
  month =        dec,
  year =         "2007",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1360464.1360477",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:13 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This column consists of selected traffic from the
                 comp.arch newsgroup, a forum for discussion of computer
                 architecture on the Internet---an international
                 computer network.\par

                 As always, the opinions expressed in this column are
                 the personal views of the authors, and do not
                 necessarily represent the institutions to which they
                 are affiliated.\par

                 Text which sets the context of a message appears
                 underlined or in italics; this is usually text the
                 author has quoted from earlier messages. The code-like
                 expressions below the authors' names are their
                 addresses on Internet.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Winfree:2008:TMP,
  author =       "Erik Winfree",
  title =        "Toward molecular programming with {DNA}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "1--1",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353534.1346282",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Biological organisms are beautiful examples of
                 programming. The program and data are stored in
                 biological molecules such as DNA, RNA, and proteins;
                 the algorithms are carried out by molecular and
                 biochemical processes; and the end result is the
                 creation and function of an organism. If we understood
                 how to program molecular systems, what could we create?
                 Lifelike technologies whose basic operations are
                 chemical reactions? The fields of chemistry, physics,
                 biology, and computer science are converging as we
                 begin to synthesize molecules, molecular machines, and
                 molecular systems of ever increasing complexity,
                 leading to subdisciplines such as DNA nanotechnology,
                 DNA computing, and synthetic biology. Having
                 demonstrated simple devices and systems --
                 self-assembled structures, molecular motors, chemical
                 logic gates -- researchers are now turning to the
                 question of how to create large-scale integrated
                 systems. To do so, we must learn how to manage
                 complexity: how to efficiently specify the structure
                 and behavior of intricate molecular systems, how to
                 compile such specifications down to the design of
                 molecules to be synthesized in the lab, and how to
                 ensure that such systems function robustly. These
                 issues will be illustrated for chemical logic circuits
                 based on cascades of DNA hybridization reactions.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "DNA; molecular programming",
}

@Article{Chen:2008:OVB,
  author =       "Xiaoxin Chen and Tal Garfinkel and E. Christopher
                 Lewis and Pratap Subrahmanyam and Carl A. Waldspurger
                 and Dan Boneh and Jeffrey Dwoskin and Dan R. K. Ports",
  title =        "{Overshadow}: a virtualization-based approach to
                 retrofitting protection in commodity operating
                 systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "2--13",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346284",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Commodity operating systems entrusted with securing
                 sensitive data are remarkably large and complex, and
                 consequently, frequently prone to compromise. To
                 address this limitation, we introduce a
                 virtual-machine-based system called Overshadow that
                 protects the privacy and integrity of application data,
                 even in the event of a total OS compromise. Overshadow
                 presents an application with a normal view of its
                 resources, but the OS with an encrypted view. This
                 allows the operating system to carry out the complex
                 task of managing an application's resources, without
                 allowing it to read or modify them. Thus, Overshadow
                 offers a last line of defense for application
                 data.\par

                 Overshadow builds on multi-shadowing, a novel mechanism
                 that presents different views of 'physical' memory,
                 depending on the context performing the access. This
                 primitive offers an additional dimension of protection
                 beyond the hierarchical protection domains implemented
                 by traditional operating systems and processor
                 architectures.\par

                 We present the design and implementation of Overshadow
                 and show how its new protection semantics can be
                 integrated with existing systems. Our design has been
                 fully implemented and used to protect a wide range of
                 unmodified legacy applications running on an unmodified
                 Linux operating system. We evaluate the performance of
                 our implementation, demonstrating that this approach is
                 practical.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "cloaking; hypervisors; memory protection;
                 multi-shadowing; operating systems; virtual machine
                 monitors; VMM",
}

@Article{McCune:2008:HLC,
  author =       "Jonathan M. McCune and Bryan Parno and Adrian Perrig
                 and Michael K. Reiter and Arvind Seshadri",
  title =        "How low can you go?: recommendations for
                 hardware-supported minimal {TCB} code execution",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "14--25",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346285",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "We explore the extent to which newly available
                 CPU-based security technology can reduce the Trusted
                 Computing Base (TCB) for security-sensitive
                 applications. We find that although this new technology
                 represents a step in the right direction, significant
                 performance issues remain. We offer several suggestions
                 that leverage existing processor technology, retain
                 security, and improve performance. Implementing these
                 recommendations will finally allow application
                 developers to focus exclusively on the security of
                 their own code, enabling it to execute in isolation
                 from the numerous vulnerabilities in the underlying
                 layers of legacy code.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "late launch; secure execution; trusted computing",
}

@Article{Bhargava:2008:ATD,
  author =       "Ravi Bhargava and Benjamin Serebrin and Francesco
                 Spadini and Srilatha Manne",
  title =        "Accelerating two-dimensional page walks for
                 virtualized systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "26--35",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346286",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Nested paging is a hardware solution for alleviating
                 the software memory management overhead imposed by
                 system virtualization. Nested paging complements
                 existing page walk hardware to form a two-dimensional
                 (2D) page walk, which reduces the need for hypervisor
                 intervention in guest page table management. However,
                 the extra dimension also increases the maximum number
                 of architecturally-required page table
                 references.\par

                 This paper presents an in-depth examination of the 2D
                 page table walk overhead and options for decreasing it.
                 These options include using the AMD Opteron processor's
                 page walk cache to exploit the strong reuse of page
                 entry references. For a mix of server and SPEC
                 benchmarks, the presented results show a 15\%-38\%
                 improvement in guest performance by extending the
                 existing page walk cache to also store the nested
                 dimension of the 2D page walk. Caching nested page
                 table translations and skipping multiple page entry
                 references produce an additional 3\%-7\%
                 improvement.\par

                 Much of the remaining 2D page walk overhead is due to
                 low-locality nested page entry references, which result
                 in additional memory hierarchy misses. By using large
                 pages, the hypervisor can eliminate many of these
                 long-latency accesses and further improve the guest
                 performance by 3\%-22\%.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "AMD; hypervisor; memory management; nested paging;
                 page walk caching; TLB; virtual machine monitor;
                 virtualization",
}

@Article{Lee:2008:ETL,
  author =       "Benjamin C. Lee and David Brooks",
  title =        "Efficiency trends and limits from comprehensive
                 microarchitectural adaptivity",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "36--47",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353534.1346288",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Increasing demand for power-efficient,
                 high-performance computing requires tuning applications
                 and/or the underlying hardware to improve the mapping
                 between workload heterogeneity and computational
                 resources. To assess the potential benefits of hardware
                 tuning, we propose a framework that leverages
                 synergistic interactions between recent advances in (a)
                 sampling, (b) predictive modeling, and (c) optimization
                 heuristics. This framework enables qualitatively new
                 capabilities in analyzing the performance and power
                 characteristics of adaptive microarchitectures. For the
                 first time, we are able to simultaneously consider high
                 temporal and comprehensive spatial adaptivity. In
                 particular, we optimize efficiency for many, short
                 adaptive intervals and identify the best configuration
                 of 15 parameters, which define a space of 240B
                 point.\par

                 With frequent sub-application reconfiguration and a
                 fully reconfigurable hardware substrate, adaptive
                 microarchitectures achieve bips$^3$ /w efficiency gains
                 of up to 5.3x (median 2.4x) relative to their static
                 counterparts already optimized for a given application.
                 This 5.3x efficiency gain is derived from a 1.6x
                 performance gain and 0.8x power reduction. Although
                 several applications achieve a significant fraction of
                 their potential efficiency with as few as three
                 adaptive parameters, the three most significant
                 parameters differ across applications. These
                 differences motivate a hardware substrate capable of
                 comprehensive adaptivity to meet these diverse
                 application requirements.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "adaptivity; efficiency; inference; microarchitecture;
                 performance; power; reconfigurablity; regression;
                 simulation; statistics",
}

@Article{Raghavendra:2008:NPS,
  author =       "Ramya Raghavendra and Parthasarathy Ranganathan and
                 Vanish Talwar and Zhikui Wang and Xiaoyun Zhu",
  title =        "No 'power' struggles: coordinated multi-level power
                 management for the data center",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "48--59",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353534.1346289",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Power delivery, electricity consumption, and heat
                 management are becoming key challenges in data center
                 environments. Several past solutions have individually
                 evaluated different techniques to address separate
                 aspects of this problem, in hardware and software, and
                 at local and global levels. Unfortunately, there has
                 been no corresponding work on coordinating all these
                 solutions. In the absence of such coordination, these
                 solutions are likely to interfere with one another, in
                 unpredictable (and potentially dangerous) ways. This
                 paper seeks to address this problem. We make two key
                 contributions. First, we propose and validate a power
                 management solution that coordinates different
                 individual approaches. Using simulations based on 180
                 server traces from nine different real-world
                 enterprises, we demonstrate the correctness, stability,
                 and efficiency advantages of our solution. Second,
                 using our unified architecture as the base, we perform
                 a detailed quantitative sensitivity analysis and draw
                 conclusions about the impact of different
                 architectures, implementations, workloads, and system
                 design choices.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "capping; control theory; coordination; data center;
                 efficiency; power management; virtualization",
}

@Article{Ballapuram:2008:EAS,
  author =       "Chinnakrishnan S. Ballapuram and Ahmad Sharif and
                 Hsien-Hsin S. Lee",
  title =        "Exploiting access semantics and program behavior to
                 reduce snoop power in chip multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "60--69",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346290",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Integrating more processor cores on-die has become the
                 unanimous trend in the microprocessor industry. Most of
                 the current research thrusts using chip multiprocessors
                 (CMPs) as the baseline to analyze problems in various
                 domains. One of the main design issues facing CMP
                 systems is the growing number of snoops required to
                 maintain cache coherency and to support
                 self/cross-modifying code that leads to power and
                 performance limitations. In this paper, we analyze the
                 internal and external snoop behavior in a CMP system
                 and relax the snoopy cache coherence protocol based on
                 the program semantics and properties of the shared
                 variables for saving power. Based on the observations
                 and analyses, we propose two novel techniques:
                 Selective Snoop Probe (SSP) and Essential Snoop Probe
                 (ESP) to reduce power without compromising performance.
                 Our simulation results show that using the SSP
                 technique, 5\% to 65\% data cache energy savings per
                 core for different processor configurations can be
                 achieved with 1\% to 2\% performance improvement. We
                 also show that 5\% to 82\% of data cache energy per
                 core is spent on the non-essential snoop probes that
                 can be saved using the ESP technique.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "chip multiprocessors; internal and external snoops;
                 MESI protocol; self-modifying code",
}

@Article{Mallik:2008:PMU,
  author =       "Arindam Mallik and Jack Cosgrove and Robert P. Dick
                 and Gokhan Memik and Peter Dinda",
  title =        "{PICSEL}: measuring user-perceived performance to
                 control dynamic frequency scaling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "70--79",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353534.1346291",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The ultimate goal of a computer system is to satisfy
                 its users. The success of architectural or system-level
                 optimizations depends largely on having accurate
                 metrics for user satisfaction. We propose to derive
                 such metrics from information that is 'close to flesh'
                 and apparent to the user rather than from information
                 that is 'close to metal' and hidden from the user. We
                 describe and evaluate PICSEL, a dynamic voltage and
                 frequency scaling (DVFS) technique that uses
                 measurements of variations in the rate of change of a
                 computer's video output to estimate user-perceived
                 performance. Our adaptive algorithms, one conservative
                 and one aggressive, use these estimates to dramatically
                 reduce operating frequencies and voltages for
                 graphically-intensive applications while maintaining
                 performance at a satisfactory level for the user. We
                 evaluate PICSEL through user studies conducted on a
                 Pentium M laptop running Windows XP. Experiments
                 performed with 20 users executing three applications
                 indicate that the measured laptop power can be reduced
                 by up to 12.1\%, averaged across all of our users and
                 applications, compared to the default Windows XP DVFS
                 policy. User studies revealed that the difference in
                 overall user satisfaction between the more aggressive
                 version of PICSEL and Windows DVFS were statistically
                 insignificant, whereas the conservative version of
                 PICSEL actually improved user satisfaction when
                 compared to Windows DVFS.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "dynamic voltage and frequency scaling; power
                 management; thermal emergency; user-perceived
                 performance",
}

@Article{Joao:2008:IPO,
  author =       "Jose A. Joao and Onur Mutlu and Hyesoon Kim and Rishi
                 Agarwal and Yale N. Patt",
  title =        "Improving the performance of object-oriented languages
                 with dynamic predication of indirect jumps",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "80--90",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353535.1346293",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Indirect jump instructions are used to implement
                 increasingly-common programming constructs such as
                 virtual function calls, switch-case statements, jump
                 tables, and interface calls. The performance impact of
                 indirect jumps is likely to increase because indirect
                 jumps with multiple targets are difficult to predict
                 even with specialized hardware.\par

                 This paper proposes a new way of handling
                 hard-to-predict indirect jumps: dynamically predicating
                 them. The compiler (static or dynamic) identifies
                 indirect jumps that are suitable for predication along
                 with their control-flow merge (CFM) points. The
                 hardware predicates the instructions between different
                 targets of the jump and its CFM point if the jump turns
                 out to be hard-to-predict at run time. If the jump
                 would actually have been mispredicted, its dynamic
                 predication eliminates a pipeline flush, thereby
                 improving performance.\par

                 Our evaluations show that Dynamic Indirect jump
                 Predication (DIP) improves the performance of a set of
                 object-oriented applications including the Java DaCapo
                 benchmark suite by 37.8\% compared to a commonly-used
                 branch target buffer based predictor, while also
                 reducing energy consumption by 24.8\%. We compare DIP
                 to three previously proposed indirect jump predictors
                 and find that it provides the best performance and
                 energy-efficiency.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "dynamic predication; indirect jumps; object-oriented
                 languages; predicated execution; virtual functions",
}

@Article{Wegiel:2008:MCV,
  author =       "Michal Wegiel and Chandra Krintz",
  title =        "The mapping collector: virtual memory support for
                 generational, parallel, and concurrent compaction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "91--102",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353535.1346294",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Parallel and concurrent garbage collectors are
                 increasingly employed by managed runtime environments
                 (MREs) to maintain scalability, as multi-core
                 architectures and multi-threaded applications become
                 pervasive. Moreover, state-of-the-art MREs commonly
                 implement compaction to eliminate heap fragmentation
                 and enable fast linear object allocation.\par

                 Our empirical analysis of object demographics reveals
                 that unreachable objects in the heap tend to form
                 clusters large enough to be effectively managed at the
                 granularity of virtual memory pages. Even though
                 processes can manipulate the mapping of the virtual
                 address space through the standard operating system
                 (OS) interface on most platforms, extant
                 parallel/concurrent compactors do not do so to exploit
                 this clustering behavior and instead achieve compaction
                 by performing, relatively expensive, object moving and
                 pointer adjustment.\par

                 We introduce the Mapping Collector (MC), which
                 leverages virtual memory operations to reclaim and
                 consolidate free space without moving objects and
                 updating pointers. MC is a nearly-single-phase
                 compactor that is simpler and more efficient than
                 previously reported compactors that comprise two to
                 four phases. Through effective MRE-OS coordination, MC
                 maintains the simplicity of a non-moving collector
                 while providing efficient parallel and concurrent
                 compaction.\par

                 We implement both stop-the-world and concurrent MC in a
                 generational garbage collection framework within the
                 open-source HotSpot Java Virtual Machine. Our
                 experimental evaluation using a multiprocessor
                 indicates that MC significantly increases throughput
                 and scalability as well as reduces pause times,
                 relative to state-of-the-art, parallel and concurrent
                 compactors.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "compaction; concurrent; parallel; virtual memory",
}

@Article{Devietti:2008:HAS,
  author =       "Joe Devietti and Colin Blundell and Milo M. K. Martin
                 and Steve Zdancewic",
  title =        "{Hardbound}: architectural support for spatial safety
                 of the {C} programming language",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "103--114",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346295",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The C programming language is at least as well known
                 for its absence of spatial memory safety guarantees
                 (i.e., lack of bounds checking) as it is for its high
                 performance. C's unchecked pointer arithmetic and array
                 indexing allow simple programming mistakes to lead to
                 erroneous executions, silent data corruption, and
                 security vulnerabilities. Many prior proposals have
                 tackled enforcing spatial safety in C programs by
                 checking pointer and array accesses. However, existing
                 software-only proposals have significant drawbacks that
                 may prevent wide adoption, including: unacceptably high
                 run-time overheads, lack of completeness, incompatible
                 pointer representations, or need for non-trivial
                 changes to existing C source code and compiler
                 infrastructure.\par

                 Inspired by the promise of these software-only
                 approaches, this paper proposes a hardware bounded
                 pointer architectural primitive that supports
                 cooperative hardware/software enforcement of spatial
                 memory safety for C programs. This bounded pointer is a
                 new hardware primitive datatype for pointers that
                 leaves the standard C pointer representation intact,
                 but augments it with bounds information maintained
                 separately and invisibly by the hardware. The bounds
                 are initialized by the software, and they are then
                 propagated and enforced transparently by the hardware,
                 which automatically checks a pointer's bounds before it
                 is dereferenced. One mode of use requires instrumenting
                 only malloc, which enables enforcement of
                 per-allocation spatial safety for heap-allocated
                 objects for existing binaries. When combined with
                 simple intraprocedural compiler instrumentation,
                 hardware bounded pointers enable a low-overhead
                 approach for enforcing complete spatial memory safety
                 in unmodified C programs.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "C programming language; spatial memory safety",
}

@Article{Lvin:2008:ATA,
  author =       "Vitaliy B. Lvin and Gene Novark and Emery D. Berger
                 and Benjamin G. Zorn",
  title =        "{Archipelago}: trading address space for reliability
                 and security",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "115--124",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353535.1346296",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Memory errors are a notorious source of security
                 vulnerabilities that can lead to service interruptions,
                 information leakage and unauthorized access. Because
                 such errors are also difficult to debug, the absence of
                 timely patches can leave users vulnerable to attack for
                 long periods of time. A variety of approaches have been
                 introduced to combat these errors, but these often
                 incur large runtime overheads and generally abort on
                 errors, threatening availability.\par

                 This paper presents Archipelago, a runtime system that
                 takes advantage of available address space to
                 substantially reduce the likelihood that a memory error
                 will affect program execution. Archipelago randomly
                 allocates heap objects far apart in virtual address
                 space, effectively isolating each object from buffer
                 overflows. Archipelago also protects against dangling
                 pointer errors by preserving the contents of freed
                 objects after they are freed. Archipelago thus trades
                 virtual address space---a plentiful resource on 64-bit
                 systems---for significantly improved program
                 reliability and security, while limiting physical
                 memory consumption by tracking the working set of an
                 application and compacting cold objects. We show that
                 Archipelago allows applications to continue to run
                 correctly in the face of thousands of memory errors.
                 Across a suite of server applications, Archipelago's
                 performance overhead is 6\% on average (between -7\%
                 and 22\%), making it especially suitable to protect
                 servers that have known security vulnerabilities due to
                 heap memory errors.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "Archipelago; buffer overflow; dynamic memory
                 allocation; memory errors; probabilistic memory safety;
                 randomized algorithms; virtual memory",
}

@Article{Choi:2008:ABP,
  author =       "Bumyong Choi and Leo Porter and Dean M. Tullsen",
  title =        "Accurate branch prediction for short threads",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "125--134",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353534.1346298",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Multi-core processors, with low communication costs
                 and high availability of execution cores, will increase
                 the use of execution and compilation models that use
                 short threads to expose parallelism. Current branch
                 predictors seek to incorporate large amounts of control
                 flow history to maximize accuracy. However, when that
                 history is absent the predictor fails to work as
                 intended. Thus, modern predictors are almost useless
                 for threads below a certain length.\par

                 Using a Speculative Multithreaded (SpMT) architecture
                 as an example of a system which generates shorter
                 threads, this work examines techniques to improve
                 branch prediction accuracy when a new thread begins to
                 execute on a different core. This paper proposes a
                 minor change to the branch predictor that gives
                 virtually the same performance on short threads as an
                 idealized predictor that incorporates unknowable
                 pre-history of a spawned speculative thread. At the
                 same time, strong performance on long threads is
                 preserved. The proposed technique sets the global
                 history register of the spawned thread to the initial
                 value of the program counter. This novel and simple
                 design reduces branch mispredicts by 29\% and provides
                 as much as a 13\% IPC improvement on selected SPEC2000
                 benchmarks.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "branch prediction; chip multiprocessors",
}

@Article{Srikantaiah:2008:ASP,
  author =       "Shekhar Srikantaiah and Mahmut Kandemir and Mary Jane
                 Irwin",
  title =        "Adaptive set pinning: managing shared caches in chip
                 multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "135--144",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353534.1346299",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "As part of the trend towards Chip Multiprocessors
                 (CMPs) for the next leap in computing performance, many
                 architectures have explored sharing the last level of
                 cache among different processors for better
                 performance-cost ratio and improved resource
                 allocation. Shared cache management is a crucial CMP
                 design aspect for the performance of the system. This
                 paper first presents a new classification of cache
                 misses - CII: Compulsory, Inter-processor and
                 Intra-processor misses - for CMPs with shared caches to
                 provide a better understanding of the interactions
                 between memory transactions of different processors at
                 the level of shared cache in a CMP. We then propose a
                 novel approach, called set pinning, for eliminating
                 inter-processor misses and reducing intra-processor
                 misses in a shared cache. Furthermore, we show that an
                 adaptive set pinning scheme improves over the benefits
                 obtained by the set pinning scheme by significantly
                 reducing the number of off-chip accesses. Extensive
                 analysis of these approaches with SPEComp 2001
                 benchmarks is performed using a full system simulator.
                 Our experiments indicate that the set pinning scheme
                 achieves an average improvement of 22.18\% in the L2
                 miss rate while the adaptive set pinning scheme reduces
                 the miss rates by an average of 47.94\% as compared to
                 the traditional shared cache scheme. They also improve
                 the performance by 7.24\% and 17.88\% respectively.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "CMP; inter-processor; intra-processor; set pinning;
                 shared cache",
}

@Article{Tuck:2008:SSE,
  author =       "James Tuck and Wonsun Ahn and Luis Ceze and Josep
                 Torrellas",
  title =        "{SoftSig}: software-exposed hardware signatures for
                 code analysis and optimization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "145--156",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346300",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Many code analysis techniques for optimization,
                 debugging, or parallelization need to perform runtime
                 disambiguation of sets of addresses. Such operations
                 can be supported efficiently and with low complexity
                 with hardware signatures.\par

                 To enable flexible use of signatures, this paper
                 proposes to expose a Signature Register File to the
                 software through a rich ISA. The software has great
                 flexibility to decide, for each signature,which
                 addresses to collect and which addresses to
                 disambiguate against. We call this architecture
                 SoftSig. In addition, as an example of SoftSig use, we
                 show how to detect redundant function calls efficiently
                 and eliminate them dynamically. We call this algorithm
                 MemoiSE. On average for five popular applications,
                 MemoiSE reduces the number of dynamic instructions by
                 9.3\%, thereby reducing the execution time of the
                 applications by 9\%.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "memory disambiguation; multi-core architectures;
                 runtime optimization",
}

@Article{Burcea:2008:PV,
  author =       "Ioana Burcea and Stephen Somogyi and Andreas Moshovos
                 and Babak Falsafi",
  title =        "Predictor virtualization",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "157--167",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346301",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Many hardware optimizations rely on collecting
                 information about program behavior at runtime. This
                 information is stored in lookup tables. To be accurate
                 and effective, these optimizations usually require
                 large dedicated on-chip tables. Although technology
                 advances offer an increased amount of on-chip
                 resources, these resources are allocated to increase
                 the size of on-chip conventional cache
                 hierarchies.\par

                 This work proposes Predictor Virtualization, a
                 technique that uses the existing memory hierarchy to
                 emulate large predictor tables. We demonstrate the
                 benefits of this technique by virtualizing a
                 state-of-the-art data prefetcher. Full-system,
                 cycle-accurate simulations demonstrate that the
                 virtualized prefetcher preserves the performance
                 benefits of the original design, while reducing the
                 on-chip storage dedicated to the predictor table from
                 60KB down to less than one kilobyte.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "caches; memory hierarchy; metadata; predictor
                 virtualization",
}

@Article{Ganapathy:2008:DIM,
  author =       "Vinod Ganapathy and Matthew J. Renzelmann and Arini
                 Balakrishnan and Michael M. Swift and Somesh Jha",
  title =        "The design and implementation of microdrivers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "168--178",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346303",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Device drivers commonly execute in the kernel to
                 achieve high performance and easy access to kernel
                 services. However, this comes at the price of decreased
                 reliability and increased programming difficulty.
                 Driver programmers are unable to use user-mode
                 development tools and must instead use cumbersome
                 kernel tools. Faults in kernel drivers can cause the
                 entire operating system to crash. User-mode drivers
                 have long been seen as a solution to this problem, but
                 suffer from either poor performance or new interfaces
                 that require a rewrite of existing drivers.\par

                 This paper introduces the Microdrivers architecture
                 that achieves high performance and compatibility by
                 leaving critical path code in the kernel and moving the
                 rest of the driver code to a user-mode process. This
                 allows data-handling operations critical to I/O
                 performance to run at full speed, while management
                 operations such as initialization and configuration run
                 at reduced speed in user-level. To achieve
                 compatibility, we present DriverSlicer, a tool that
                 splits existing kernel drivers into a kernel-level
                 component and a user-level component using a small
                 number of programmer annotations. Experiments show that
                 as much as 65\% of driver code can be removed from the
                 kernel without affecting common-case performance, and
                 that only 1-6 percent of the code requires
                 annotations.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "device drivers; program partitioning; reliability",
}

@Article{Weinsberg:2008:TFC,
  author =       "Yaron Weinsberg and Danny Dolev and Tal Anker and Muli
                 Ben-Yehuda and Pete Wyckoff",
  title =        "Tapping into the fountain of {CPUs}: on operating
                 system support for programmable devices",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "179--188",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346304",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The constant race for faster and more powerful CPUs is
                 drawing to a close. No longer is it feasible to
                 significantly increase the speed of the CPU without
                 paying a crushing penalty in power consumption and
                 production costs. Instead of increasing single thread
                 performance, the industry is turning to multiple CPU
                 threads or cores (such as SMT and CMP) and
                 heterogeneous CPU architectures (such as the Cell
                 Broadband Engine). While this is a step in the right
                 direction, in every modern PC there is a wealth of
                 untapped compute resources. The NIC has a CPU; the disk
                 controller is programmable; some high-end graphics
                 adapters are already more powerful than host CPUs. Some
                 of these CPUs can perform some functions more
                 efficiently than the host CPUs. Our operating systems
                 and programming abstractions should be expanded to let
                 applications tap into these computational resources and
                 make the best use of them.\par

                 Therefore, we propose the H\par

                 YDRA framework, which lets application developers use
                 the combined power of every compute resource in a
                 coherent way. HYDRA is a programming model and a
                 runtime support layer which enables utilization of host
                 processors as well as various programmable peripheral
                 devices' processors. We present the framework and its
                 application for a demonstrative use-case, as well as
                 provide a thorough evaluation of its capabilities.
                 Using HYDRA we were able to cut down the development
                 cost of a system that uses multiple heterogeneous
                 compute resources significantly.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "offloading; operating systems; programming model",
}

@Article{Shen:2008:HCD,
  author =       "Kai Shen and Ming Zhong and Sandhya Dwarkadas and
                 Chuanpeng Li and Christopher Stewart and Xiao Zhang",
  title =        "Hardware counter driven on-the-fly request
                 signatures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "189--200",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346306",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Today's processors provide a rich source of
                 statistical information on application execution
                 through hardware counters. In this paper, we explore
                 the utilization of these statistics as request
                 signatures in server applications for identifying
                 requests and inferring high-level request properties (
                 e.g., CPU and I/O resource needs). Our key finding is
                 that effective request signatures may be constructed
                 using a small amount of hardware statistics while the
                 request is still in an early stage of its execution.
                 Such on-the-fly request identification and property
                 inference allow guided operating system adaptation at
                 request granularity ( e.g., resource-aware request
                 scheduling and on-the-fly request classification). We
                 address the challenges of selecting hardware counter
                 metrics for signature construction and providing
                 necessary operating system support for per-request
                 statistics management. Our implementation in the Linux
                 2.6.10 kernel suggests that our approach requires low
                 overhead suitable for runtime deployment. Our
                 on-the-fly request resource consumption inference
                 (averaging 7\%, 3\%, 20\%, and 41\% prediction errors
                 for four server workloads, TPC-C, TPC-H, J2EE-based
                 RUBiS, and a trace-driven index search, respectively)
                 is much more accurate than the online running-average
                 based prediction (73-82\% errors). Its use for
                 resource-aware request scheduling results in a 15-70\%
                 response time reduction for three CPU-bound
                 applications. Its use for on-the-fly request
                 classification and anomaly detection exhibits high
                 accuracy for the TPC-H workload with synthetically
                 generated anomalous requests following a typical
                 SQL-injection attack pattern.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "anomaly detection; hardware counter; operating system
                 adaptation; request classification; server system",
}

@Article{VanErtvelde:2008:DPA,
  author =       "Luk {Van Ertvelde} and Lieven Eeckhout",
  title =        "Dispersing proprietary applications as benchmarks
                 through code mutation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "201--210",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353534.1346307",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Industry vendors hesitate to disseminate proprietary
                 applications to academia and third party vendors. By
                 consequence, the benchmarking process is typically
                 driven by standardized, open-source benchmarks which
                 may be very different from and likely not
                 representative of the real-life applications of
                 interest.\par

                 This paper proposes code mutation, a novel technique
                 that mutates a proprietary application to complicate
                 reverse engineering so that it can be distributed as a
                 benchmark. The benchmark mutant then serves as a proxy
                 for the proprietary application. The key idea in the
                 proposed code mutation approach is to preserve the
                 proprietary application's dynamic memory access and/or
                 control flow behavior in the benchmark mutant while
                 mutating the rest of the application code. To this end,
                 we compute program slices for memory access operations
                 and/or control flow operations trimmed through constant
                 value and branch profiles; and subsequently mutate the
                 instructions not appearing in these slices through
                 binary rewriting.\par

                 Our experimental results using SPEC CPU2000 and MiBench
                 benchmarks show that code mutation is a promising
                 technique that mutates up to 90\% of the static binary,
                 up to 50\% of the dynamically executed instructions,
                 and up to 35\% of the at run time exposed
                 inter-operation data dependencies. The performance
                 characteristics of the mutant are very similar to those
                 of the proprietary application across a wide range of
                 microarchitectures and hardware implementations.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "benchmark generation; code mutation",
}

@Article{Mysore:2008:UVF,
  author =       "Shashidhar Mysore and Bita Mazloom and Banit Agrawal
                 and Timothy Sherwood",
  title =        "Understanding and visualizing full systems with data
                 flow tomography",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "211--221",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353534.1346308",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "It is not uncommon for modern systems to be composed
                 of a variety of interacting services, running across
                 multiple machines in such a way that most developers do
                 not really understand the whole system. As abstraction
                 is layered atop abstraction, developers gain the
                 ability to compose systems of extraordinary complexity
                 with relative ease. However, many software properties,
                 especially those that cut across abstraction layers,
                 become very difficult to understand in such
                 compositions. The communication patterns involved, the
                 privacy of critical data, and the provenance of
                 information, can be difficult to find and understand,
                 even with access to all of the source code. The goal of
                 Data Flow Tomography is to use the inherent information
                 flow of such systems to help visualize the interactions
                 between complex and interwoven components across
                 multiple layers of abstraction. In the same way that
                 the injection of short-lived radioactive isotopes help
                 doctors trace problems in the cardiovascular system,
                 the use of 'data tagging' can help developers slice
                 through the extraneous layers of software and pin-point
                 those portions of the system interacting with the data
                 of interest. To demonstrate the feasibility of this
                 approach we have developed a prototype system in which
                 tags are tracked both through the machine and in
                 between machines over the network, and from which novel
                 visualizations of the whole system can be derived. We
                 describe the system-level challenges in creating a
                 working system tomography tool and we qualitatively
                 evaluate our system by examining several example real
                 world scenarios.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "data flow tracking; tomography; virtual machine",
}

@Article{Ottoni:2008:COG,
  author =       "Guilherme Ottoni and David I. August",
  title =        "Communication optimizations for global multi-threaded
                 instruction scheduling",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "222--232",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353535.1346310",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The recent shift in the industry towards chip
                 multiprocessor (CMP) designs has brought the need for
                 multi-threaded applications to mainstream computing. As
                 observed in several limit studies, most of the
                 parallelization opportunities require looking for
                 parallelism beyond local regions of code. To exploit
                 these opportunities, especially for sequential
                 applications, researchers have recently proposed global
                 multi-threaded instruction scheduling techniques,
                 including DSWP and GREMIO. These techniques
                 simultaneously schedule instructions from large regions
                 of code, such as arbitrary loop nests or whole
                 procedures, and have been shown to be effective at
                 extracting threads for many applications. A key enabler
                 of these global instruction scheduling techniques is
                 the Multi-Threaded Code Generation (MTCG) algorithm
                 proposed in [16], which generates multi-threaded code
                 for any partition of the instructions into threads.
                 This algorithm inserts communication and
                 synchronization instructions in order to satisfy all
                 inter-thread dependences.\par

                 In this paper, we present a general compiler framework,
                 COCO, to optimize the communication and synchronization
                 instructions inserted by the MTCG algorithm. This
                 framework, based on thread-aware data-flow analyses and
                 graph min-cut algorithms, appropriately models and
                 optimizes all kinds of inter-thread dependences,
                 including register, memory, and control dependences.
                 Our experiments, using a fully automatic compiler
                 implementation of these techniques, demonstrate
                 significant reductions (about 30\% on average) in the
                 number of dynamic communication instructions in code
                 parallelized with DSWP and GREMIO. This reduction in
                 communication translates to performance gains of up to
                 40\%.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "communication; data-flow analysis; graph min-cut;
                 instruction scheduling; multi-threading;
                 synchronization",
}

@Article{Kulkarni:2008:OPB,
  author =       "Milind Kulkarni and Keshav Pingali and Ganesh
                 Ramanarayanan and Bruce Walter and Kavita Bala and L.
                 Paul Chew",
  title =        "Optimistic parallelism benefits from data
                 partitioning",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "233--243",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353534.1346311",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Recent studies of irregular applications such as
                 finite-element mesh generators and data-clustering
                 codes have shown that these applications have a
                 generalized data parallelism arising from the use of
                 iterative algorithms that perform computations on
                 elements of worklists. In some irregular applications,
                 the computations on different elements are independent.
                 In other applications, there may be complex patterns of
                 dependences between these computations.\par

                 The Galois system was designed to exploit this kind of
                 irregular data parallelism on multicore processors. Its
                 main features are (i) two kinds of set iterators for
                 expressing worklist-based data parallelism, and (ii) a
                 runtime system that performs optimistic parallelization
                 of these iterators, detecting conflicts and rolling
                 back computations as needed. Detection of conflicts and
                 rolling back iterations requires information from class
                 implementors.\par

                 In this paper, we introduce mechanisms to improve the
                 execution efficiency of Galois programs: data
                 partitioning, data-centric work assignment, lock
                 coarsening, and over-decomposition. These mechanisms
                 can be used to exploit locality of reference, reduce
                 mis-speculation, and lower synchronization overhead. We
                 also argue that the design of the Galois system permits
                 these mechanisms to be used with relatively little
                 modification to the user code. Finally, we present
                 experimental results that demonstrate the utility of
                 these mechanisms.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "data partitioning; irregular programs; locality; lock
                 coarsening; optimistic parallelism;
                 over-decomposition",
}

@Article{Cox:2008:XEO,
  author =       "Russ Cox and Tom Bergan and Austin T. Clements and
                 Frans Kaashoek and Eddie Kohler",
  title =        "{Xoc}, an extension-oriented compiler for systems
                 programming",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "244--254",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353535.1346312",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Today's system programmers go to great lengths to
                 extend the languages in which they program. For
                 instance, system-specific compilers find errors in
                 Linux and other systems, and add support for
                 specialized control flow to Qt and event-based
                 programs. These compilers are difficult to build and
                 cannot always understand each other's language changes.
                 However, they can greatly improve code
                 understandability and correctness, advantages that
                 should be accessible to all programmers.\par

                 We describe an extension-oriented compiler for C called
                 xoc. An extension-oriented compiler, unlike a
                 conventional extensible compiler, implements new
                 features via many small extensions that are loaded
                 together as needed. Xoc gives extension writers full
                 control over program syntax and semantics while hiding
                 many compiler internals. Xoc programmers concisely
                 define powerful compiler extensions that, by
                 construction, can be combined; even some parts of the
                 base compiler, such as GNU C compatibility, are
                 structured as extensions.\par

                 Xoc is based on two key interfaces. Syntax patterns
                 allow extension writers to manipulate language
                 fragments using concrete syntax. Lazy computation of
                 attributes allows extension writers to use the results
                 of analyses by other extensions or the core without
                 needing to worry about pass scheduling.\par

                 Extensions built using xoc include xsparse, a 345-line
                 extension that mimics Sparse, Linux's C front end, and
                 xlambda, a 170-line extension that adds function
                 expressions to C. An evaluation of xoc using these and
                 13 other extensions shows that xoc extensions are
                 typically more concise than equivalent extensions
                 written for conventional extensible compilers and that
                 it is possible to compose extensions.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "extension-oriented compilers",
}

@Article{Wells:2008:AIF,
  author =       "Philip M. Wells and Koushik Chakraborty and Gurindar
                 S. Sohi",
  title =        "Adapting to intermittent faults in multicore systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "255--264",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353536.1346314",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Future multicore processors will be more susceptible
                 to a variety of hardware failures. In particular,
                 intermittent faults, caused in part by manufacturing,
                 thermal, and voltage variations, can cause bursts of
                 frequent faults that last from several cycles to
                 several seconds or more. Due to practical limitations
                 of circuit techniques, cost-effective reliability will
                 likely require the ability to temporarily suspend
                 execution on a core during periods of intermittent
                 faults.\par

                 We investigate three of the most obvious techniques for
                 adapting to the dynamically changing resource
                 availability caused by intermittent faults, and
                 demonstrate their different system-level implications.
                 We show that system software reconfiguration has very
                 high overhead, that temporarily pausing execution on a
                 faulty core can lead to cascading livelock, and that
                 using spare cores has high fault-free cost. To remedy
                 these and other drawbacks of the three baseline
                 techniques, we propose using a thin hardware/firmware
                 layer to manage an overcommitted system -- one where
                 the OS is configured to use more virtual processors
                 than the number of currently available physical cores.
                 We show that this proposed technique can gracefully
                 degrade performance during intermittent faults of
                 various duration with low overhead, without involving
                 system software, and without requiring spare cores.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "intermittent faults; overcommitted system",
}

@Article{Li:2008:UPH,
  author =       "Man-Lap Li and Pradeep Ramachandran and Swarup Kumar
                 Sahoo and Sarita V. Adve and Vikram S. Adve and
                 Yuanyuan Zhou",
  title =        "Understanding the propagation of hard errors to
                 software and implications for resilient system design",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "265--276",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346315",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "With continued CMOS scaling, future shipped hardware
                 will be increasingly vulnerable to in-the-field faults.
                 To be broadly deployable, the hardware reliability
                 solution must incur low overheads, precluding use of
                 expensive redundancy. We explore a cooperative
                 hardware-software solution that watches for anomalous
                 software behavior to indicate the presence of hardware
                 faults. Fundamental to such a solution is a
                 characterization of how hardware faults indifferent
                 microarchitectural structures of a modern processor
                 propagate through the application and OS.\par

                 This paper aims to provide such a characterization,
                 resulting in identifying low-cost detection methods and
                 providing guidelines for implementation of the recovery
                 and diagnosis components of such a reliability
                 solution. We focus on hard faults because they are
                 increasingly important and have different system
                 implications than the much studied transients. We
                 achieve our goals through fault injection experiments
                 with a microarchitecture-level full system timing
                 simulator. Our main results are: (1) we are able to
                 detect 95\% of the unmasked faults in 7 out of 8
                 studied microarchitectural structures with simple
                 detectors that incur zero to little hardware overhead;
                 (2) over 86\% of these detections are within latencies
                 that existing hardware checkpointing schemes can
                 handle, while others require software checkpointing;
                 and (3) a surprisingly large fraction of the detected
                 faults corrupt OS state, but almost all of these are
                 detected with latencies short enough to use hardware
                 checkpointing, thereby enabling OS recovery in
                 virtually all such cases.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "architecture; error detection; fault injection;
                 permanent fault",
}

@Article{Suleman:2008:FDT,
  author =       "M. Aater Suleman and Moinuddin K. Qureshi and Yale N.
                 Patt",
  title =        "Feedback-driven threading: power-efficient and
                 high-performance execution of multi-threaded workloads
                 on {CMPs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "277--286",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346317",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Extracting high-performance from the emerging Chip
                 Multiprocessors (CMPs) requires that the application be
                 divided into multiple threads. Each thread executes on
                 a separate core thereby increasing concurrency and
                 improving performance. As the number of cores on a CMP
                 continues to increase, the performance of some
                 multi-threaded applications will benefit from the
                 increased number of threads, whereas, the performance
                 of other multi-threaded applications will become
                 limited by data-synchronization and off-chip bandwidth.
                 For applications that get limited by
                 data-synchronization, increasing the number of threads
                 significantly degrades performance and increases
                 on-chip power. Similarly, for applications that get
                 limited by off-chip bandwidth, increasing the number of
                 threads increases on-chip power without providing any
                 performance improvement. Furthermore, whether an
                 application gets limited by data-synchronization, or
                 bandwidth, or neither depends not only on the
                 application but also on the input set and the machine
                 configuration. Therefore, controlling the number of
                 threads based on the run-time behavior of the
                 application can significantly improve performance and
                 reduce power.\par

                 This paper proposes Feedback-Driven Threading (FDT), a
                 framework to dynamically control the number of threads
                 using run-time information. FDT can be used to
                 implement Synchronization-Aware Threading (SAT), which
                 predicts the optimal number of threads depending on the
                 amount of data-synchronization. Our evaluation shows
                 that SAT can reduce both execution time and power by up
                 to 66\% and 78\% respectively. Similarly, FDT can be
                 used to implement Bandwidth-Aware Threading (BAT),
                 which predicts the minimum number of threads required
                 to saturate the off-chip bus. Our evaluation shows that
                 BAT reduces on-chip power by up to 78\%. When SAT and
                 BAT are combined, the average execution time reduces by
                 17\% and power reduces by 59\%. The proposed techniques
                 leverage existing performance counters and require
                 minimal support from the threading library.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "bandwidth; CMP; multi-threaded; synchronization",
}

@Article{Linderman:2008:MPM,
  author =       "Michael D. Linderman and Jamison D. Collins and Hong
                 Wang and Teresa H. Meng",
  title =        "{Merge}: a programming model for heterogeneous
                 multi-core systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "287--296",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346318",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In this paper we propose the Merge framework, a
                 general purpose programming model for heterogeneous
                 multi-core systems. The Merge framework replaces
                 current ad hoc approaches to parallel programming on
                 heterogeneous platforms with a rigorous, library-based
                 methodology that can automatically distribute
                 computation across heterogeneous cores to achieve
                 increased energy and performance efficiency. The Merge
                 framework provides (1) a predicate dispatch-based
                 library system for managing and invoking function
                 variants for multiple architectures; (2) a high-level,
                 library-oriented parallel language based on map-reduce;
                 and (3) a compiler and runtime which implement the
                 map-reduce language pattern by dynamically selecting
                 the best available function implementations for a given
                 input and machine configuration. Using a generic
                 sequencer architecture interface for heterogeneous
                 accelerators, the Merge framework can integrate
                 function variants for specialized accelerators,
                 offering the potential for to-the-metal performance for
                 a wide range of heterogeneous architectures, all
                 transparent to the user. The Merge framework has been
                 prototyped on a heterogeneous platform consisting of an
                 Intel Core 2 Duo CPU and an 8-core 32-thread Intel
                 Graphics and Media Accelerator X3000, and a homogeneous
                 32-way Unisys SMP system with Intel Xeon processors. We
                 implemented a set of benchmarks using the Merge
                 framework and enhanced the library with X3000 specific
                 implementations, achieving speedups of 3.6x -- 8.5x
                 using the X3000 and 5.2x -- 22x using the 32-way system
                 relative to the straight C reference implementation on
                 a single IA32 core.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "GPGPU; heterogeneous multi-core; predicate dispatch",
}

@Article{Gummaraju:2008:SPG,
  author =       "Jayanth Gummaraju and Joel Coburn and Yoshio Turner
                 and Mendel Rosenblum",
  title =        "{Streamware}: programming general-purpose multicore
                 processors using streams",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "297--307",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346319",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Recently, the number of cores on general-purpose
                 processors has been increasing rapidly. Using
                 conventional programming models, it is challenging to
                 effectively exploit these cores for maximal
                 performance. An interesting alternative candidate for
                 programming multiple cores is the stream programming
                 model, which provides a framework for writing programs
                 in a sequential-style while greatly simplifying the
                 task of automatic parallelization. It has been shown
                 that not only traditional media/image applications but
                 also more general-purpose data-intensive applications
                 can be expressed in the stream programming
                 style.\par

                 In this paper, we investigate the potential to use the
                 stream programming model to efficiently utilize
                 commodity multicore general-purpose processors (e.g.,
                 Intel/AMD). Although several stream languages and
                 stream compilers have recently been developed, they
                 typically target special-purpose stream processors. In
                 contrast, we propose a flexible software system,
                 Streamware, which automatically maps stream programs
                 onto a wide variety of general-purpose multicore
                 processor configurations. We leverage existing
                 compilation framework for stream processors and design
                 a runtime environment which takes as input the output
                 of these stream compilers in the form of
                 machine-independent stream virtual machine code. The
                 runtime environment assigns work to processor cores
                 considering processor/cache configurations and adapts
                 to workload variations. We evaluate this approach for a
                 few general-purpose scientific applications on real
                 hardware and a cycle-level simulator set-up to showcase
                 scaling and contention issues. The results show that
                 the stream programming model is a good choice for
                 efficiently exploiting modern and future multicore CPUs
                 for an important class of applications.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "general-purpose multicore processors; programming;
                 runtime system; streams",
}

@Article{Nightingale:2008:PSC,
  author =       "Edmund B. Nightingale and Daniel Peek and Peter M.
                 Chen and Jason Flinn",
  title =        "Parallelizing security checks on commodity hardware",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "308--318",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346321",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Speck (Speculative Parallel Check) is a system that
                 accelerates powerful security checks on commodity
                 hardware by executing them in parallel on multiple
                 cores. Speck provides an infrastructure that allows
                 sequential invocations of a particular security check
                 to run in parallel without sacrificing the safety of
                 the system. Speck creates parallelism in two ways.
                 First, Speck decouples a security check from an
                 application by continuing the application, using
                 speculative execution, while the security check
                 executes in parallel on another core. Second, Speck
                 creates parallelism between sequential invocations of a
                 security check by running later checks in parallel with
                 earlier ones. Speck provides a process-level replay
                 system to deterministically and efficiently synchronize
                 state between a security check and the original
                 process. We use Speck to parallelize three security
                 checks: sensitive data analysis, on-access virus
                 scanning, and taint propagation. Running on a 4-core
                 and an 8-core computer, Speck improves performance 4x
                 and 7.5x for the sensitive data analysis check, 3.3x
                 and 2.8x for the on-access virus scanning check, and
                 1.6x and 2x for the taint propagation check.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "operating systems; parallel; performance; security;
                 speculative execution",
}

@Article{Castro:2008:BBR,
  author =       "Miguel Castro and Manuel Costa and Jean-Philippe
                 Martin",
  title =        "Better bug reporting with better privacy",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "319--328",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1346281.1346322",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Software vendors collect bug reports from customers to
                 improve the quality of their software. These reports
                 should include the inputs that make the software fail,
                 to enable vendors to reproduce the bug. However,
                 vendors rarely include these inputs in reports because
                 they may contain private user data. We describe a
                 solution to this problem that provides software vendors
                 with new input values that satisfy the conditions
                 required to make the software follow the same execution
                 path until it fails, but are otherwise unrelated with
                 the original inputs. These new inputs allow vendors to
                 reproduce the bug while revealing less private
                 information than existing approaches. Additionally, we
                 provide a mechanism to measure the amount of
                 information revealed in an error report. This mechanism
                 allows users to perform informed decisions on whether
                 or not to submit reports. We implemented a prototype of
                 our solution and evaluated it with real errors in real
                 programs. The results show that we can produce error
                 reports that allow software vendors to reproduce bugs
                 while revealing almost no private information.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "bug reports; constraint solving; privacy; symbolic
                 execution",
}

@Article{Lu:2008:LMC,
  author =       "Shan Lu and Soyeon Park and Eunsoo Seo and Yuanyuan
                 Zhou",
  title =        "Learning from mistakes: a comprehensive study on real
                 world concurrency bug characteristics",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "1",
  pages =        "329--339",
  month =        mar,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1353536.1346323",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Tue Jun 17 11:51:35 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The reality of multi-core hardware has made concurrent
                 programs pervasive. Unfortunately, writing correct
                 concurrent programs is difficult. Addressing this
                 challenge requires advances in multiple directions,
                 including concurrency bug detection, concurrent program
                 testing, concurrent programming model design, etc.
                 Designing effective techniques in all these directions
                 will significantly benefit from a deep understanding of
                 real world concurrency bug characteristics.\par

                 This paper provides the first (to the best of our
                 knowledge) comprehensive real world concurrency bug
                 characteristic study. Specifically, we have carefully
                 examined concurrency bug patterns, manifestation, and
                 fix strategies of 105 randomly selected real world
                 concurrency bugs from 4 representative server and
                 client open-source applications (MySQL, Apache, Mozilla
                 and OpenOffice). Our study reveals several interesting
                 findings and provides useful guidance for concurrency
                 bug detection, testing, and concurrent programming
                 language design.\par

                 Some of our findings are as follows: (1) Around one
                 third of the examined non-deadlock concurrency bugs are
                 caused by violation to programmers' order intentions,
                 which may not be easily expressed via synchronization
                 primitives like locks and transactional memories; (2)
                 Around 34\% of the examined non-deadlock concurrency
                 bugs involve multiple variables, which are not well
                 addressed by existing bug detection tools; (3) About
                 92\% of the examined concurrency bugs can be reliably
                 triggered by enforcing certain orders among no more
                 than 4 memory accesses. This indicates that testing
                 concurrent programs can target at exploring possible
                 orders among every small groups of memory accesses,
                 instead of among all memory accesses; (4) About 73\% of
                 the examined non-deadlock concurrency bugs were not
                 fixed by simply adding or changing locks, and many of
                 the fixes were not correct at the first try, indicating
                 the difficulty of reasoning concurrent execution by
                 programmers.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "bug characteristics; concurrency bug; concurrent
                 program",
}

@Article{Anonymous:2008:MGC,
  author =       "Anonymous",
  title =        "Message from the {General Chairs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "x--x",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382166",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2008:MPC,
  author =       "Anonymous",
  title =        "Message from the {Program Chair}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "xi--xi",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382167",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2008:R,
  author =       "Anonymous",
  title =        "Reviewers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "xv--xviii",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382168",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Tseng:2008:AOP,
  author =       "Francis Tseng and Yale N. Patt",
  title =        "Achieving Out-of-Order Performance with Almost
                 In-Order Complexity",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "3--12",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382169",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "There is still much performance to be gained by
                 out-of-order processors with wider issue widths.
                 However, traditional methods of increasing issue width
                 do not scale; that is, they drastically increase design
                 complexity and power requirements. This paper
                 introduces the braid, a compile-time identified entity
                 that enables the execution core to scale to wider
                 widths by exploiting the small fanout and short
                 lifetime of values produced by the program. Braid
                 processing requires identification by the compiler,
                 minor extensions to the ISA, and support by the
                 microarchitecture. The result from processing braids is
                 performance within 9\% of a very aggressive
                 conventional out-of-order microarchitecture with almost
                 the complexity of an in-order implementation.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Agarwal:2008:FCR,
  author =       "Mayank Agarwal and Nitin Navale and Kshitiz Malik and
                 Matthew I. Frank",
  title =        "Fetch-Criticality Reduction through Control
                 Independence",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "13--24",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1109/ISCA.2008.39",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Architectures that exploit control independence (CI)
                 promise to remove in-order fetch bottlenecks, like
                 branch mispredicts, instruction-cache misses and fetch
                 unit stalls, from the critical path of single-threaded
                 execution. By exposing more fetch options, however, CI
                 architectures also expose more performance tradeoffs.
                 These tradeoffs make it hard to design policies that
                 deliver good performance. This paper presents a
                 criticality-based model for reasoning about CI
                 architectures, and uses that model to describe the
                 tradeoffs between gains from control independence
                 versus increased costs of honoring data dependences.
                 The model is then used to derive the design of a
                 criticality-aware task selection policy that strikes
                 the right balance between fetch-criticality and
                 execute-criticality. Finally, the paper validates the
                 model by attacking branch-misprediction induced
                 fetch-criticality through the above derived spawn
                 policy. This leads to as high as 100\% improvements in
                 performance, and in the region of 40\% or more
                 improvements for four of the benchmarks where this is
                 the main problem. Criticality analysis shows that this
                 improvement arises due to reduced fetch-criticality.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "control independence; fetch-criticality; implicit
                 parallelization",
}

@Article{Pericas:2008:TLL,
  author =       "Miquel Peric{\`a}s and Adrian Cristal and Francisco J.
                 Cazorla and Ruben Gonz{\'a}lez and Alex Veidenbaum and
                 Daniel A. Jim{\'e}nez and Mateo Valero",
  title =        "A Two-Level Load\slash Store Queue Based on Execution
                 Locality",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "25--36",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1109/ISCA.2008.10",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Multicore processors have emerged as a powerful
                 platform on which to efficiently exploit thread-level
                 parallelism (TLP). However, due to Amdahl's Law, such
                 designs will be increasingly limited by the remaining
                 sequential components of applications. To overcome this
                 limitation it is necessary to design processors with
                 many lower-performance cores for TLP and some
                 high-performance cores designed to execute sequential
                 algorithms. Such cores will need to address the
                 memory-wall by implementing kilo-instruction windows.
                 Large window processors require large Load/Store Queues
                 that would be too slow if implemented using current
                 CAM-based designs. This paper proposes an Epoch-based
                 Load Store Queue (ELSQ), a new design based on
                 Execution Locality. It is integrated into a
                 large-window processor that has a fast, out-of-order
                 core operating only on L1/L2 cache hits and N slower
                 cores that process L2 misses and their dependent
                 instructions. The large LSQ is coupled with the slow
                 cores and is partitioned into N small and local LSQs,
                 one per core. We evaluate ELSQ in a large-window
                 environment, finding that it enables high performance
                 at low power. By exploiting locality among loads and
                 stores, ELSQ outperforms even an idealized central LSQ
                 when implemented on top of a decoupled processor
                 design.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "execution locality; kilo-instruction processors;
                 load/store queue; power-efficiency",
}

@Article{Ipek:2008:SOM,
  author =       "Engin Ipek and Onur Mutlu and Jos{\'e} F.
                 Mart{\'\i}nez and Rich Caruana",
  title =        "Self-Optimizing Memory Controllers: a Reinforcement
                 Learning Approach",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "39--50",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382172",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Efficiently utilizing off-chip DRAM bandwidth is a
                 critical issue in designing cost-effective,
                 high-performance chip multiprocessors(CMPs).
                 Conventional memory controllers deliver relatively low
                 performance in part because they often employ
                 fixed,rigid access scheduling policies designed for
                 average-case application behavior. As a result, they
                 cannot learn and optimize the long-term performance
                 impact of their scheduling decisions,and cannot adapt
                 their scheduling policies to dynamic workload behavior.
                 We propose a new, self-optimizing memory controller
                 design that operates using the principles of
                 reinforcement learning (RL)to overcome these
                 limitations. Our RL-based memory controller observes
                 the system state and estimates the long-term
                 performance impact of each action it can take. In this
                 way, the controller learns to optimize its scheduling
                 policy on the fly to maximize long-term performance.
                 Our results show that an RL-based memory controller
                 improves the performance of a set of parallel
                 applications run on a 4-core CMP by 19\% on average
                 (upto 33\%), and it improves DRAM bandwidth utilization
                 by 22\%compared to a state-of-the-art controller.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "chip multiprocessors; machine learning; memory
                 controller; memory systems; reinforcement learning",
}

@Article{Thoziyoor:2008:CMM,
  author =       "Shyamkumar Thoziyoor and Jung Ho Ahn and Matteo
                 Monchiero and Jay B. Brockman and Norman P. Jouppi",
  title =        "A Comprehensive Memory Modeling Tool and Its
                 Application to the Design and Analysis of Future Memory
                 Hierarchies",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "51--62",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1109/ISCA.2008.16",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In this paper we introduce CACTI-D, a significant
                 enhancement of CACTI 5.0. CACTI-D adds support for
                 modeling of commodity DRAM technology and support for
                 main memory DRAM chip organization. CACTI-D enables
                 modeling of the complete memory hierarchy with
                 consistent models all the way from SRAM based L1 caches
                 through main memory DRAMs on DIMMs. We illustrate the
                 potential applicability of CACTI-D in the design and
                 analysis of future memory hierarchies by carrying out a
                 last level cache study for a multicore multithreaded
                 architecture at the 32nm technology node. In this study
                 we use CACTI-D to model all components of the memory
                 hierarchy including L1, L2, last level SRAM, logic
                 process based DRAM or commodity DRAM L3 caches, and
                 main memory DRAM chips. We carry out architectural
                 simulation using benchmarks with large data sets and
                 present results of their execution time, breakdown of
                 power in the memory hierarchy, and system energy-delay
                 product for the different system configurations. We
                 find that commodity DRAM technology is most attractive
                 for stacked last level caches, with significantly lower
                 energy-delay products.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "cache; CACTI; commodity DRAM; LLC; logic-process based
                 DRAM; SRAM",
}

@Article{Mutlu:2008:PAB,
  author =       "Onur Mutlu and Thomas Moscibroda",
  title =        "Parallelism-Aware Batch Scheduling: Enhancing both
                 Performance and Fairness of Shared {DRAM} Systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "63--74",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382128",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In a chip-multiprocessor (CMP) system, the DRAM system
                 is shared among cores. In a shared DRAM system,
                 requests from a thread can not only delay requests from
                 other threads by causing bank/bus/row-buffer conflicts
                 but they can also destroy other threads'
                 DRAM-bank-level parallelism. Requests whose latencies
                 would otherwise have been overlapped could effectively
                 become serialized. As a result both fairness and system
                 throughput degrade, and some threads can starve for
                 long time periods. This paper proposes a fundamentally
                 new approach to designing a shared DRAM controller that
                 provides quality of service to threads,while also
                 improving system throughput. Our parallelism-aware
                 batch scheduler (PAR-BS) design is based on two key
                 ideas. First, PARBS processes DRAM requests in batches
                 to provide fairness and to avoid starvation of
                 requests. Second, to optimize system throughput,PAR-BS
                 employs a parallelism-aware DRAM scheduling policy that
                 aims to process requests from a thread in parallel in
                 the DRAM banks, thereby reducing the memory-related
                 stall-time experienced by the thread. PAR-BS seamlessly
                 incorporates support for system-level thread priorities
                 and can provide different service levels, including
                 purely opportunistic service, to threads with different
                 priorities. We evaluate the design trade-offs involved
                 in PAR-BS and compare it to four previously proposed
                 DRAM scheduler designs on 4-, 8-, and16-core systems.
                 Our evaluations show that, averaged over 100 4-core
                 workloads, PAR-BS improves fairness by 1.11X and system
                 throughput by 8.3\% compared to the best previous
                 scheduling technique, Stall-Time Fair Memory (STFM)
                 scheduling. Based on simple request prioritization
                 rules, PAR-BS is also simpler to implement than STFM.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "chip multiprocessors; DRAM systems; fairness; memory
                 scheduling; memory systems; memory-level parallelism;
                 multi-core systems; quality of service",
}

@Article{Kim:2008:TDH,
  author =       "John Kim and William J. Dally and Steve Scott and
                 Dennis Abts",
  title =        "Technology-Driven, Highly-Scalable {Dragonfly}
                 Topology",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "77--88",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1109/ISCA.2008.19",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Evolving technology and increasing pin-bandwidth
                 motivate the use of high-radix routers to reduce the
                 diameter, latency, and cost of interconnection
                 networks. High-radix networks, however, require longer
                 cables than their low-radix counterparts. Because
                 cables dominate network cost, the number of cables, and
                 particularly the number of long, global cables should
                 be minimized to realize an efficient network. In this
                 paper, we introduce the dragonfly topology which uses a
                 group of high-radix routers as a virtual router to
                 increase the effective radix of the network. With this
                 organization, each minimally routed packet traverses at
                 most one global channel. By reducing global channels, a
                 dragonfly reduces cost by 20\% compared to a flattened
                 butterfly and by 52\% compared to a folded Clos network
                 in configurations with $ \geq $ 16K nodes. We also
                 introduce two new variants of global adaptive routing
                 that enable load-balanced routing in the dragonfly.
                 Each router in a dragonfly must make an adaptive
                 routing decision based on the state of a global channel
                 connected to a different router. Because of the
                 indirect nature of this routing decision, conventional
                 adaptive routing algorithms give degraded performance.
                 We introduce the use of selective virtual-channel
                 discrimination and the use of credit round-trip latency
                 to both sense and signal channel congestion. The
                 combination of these two methods gives throughput and
                 latency that approaches that of an ideal adaptive
                 routing algorithm.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "dragonfly; interconnection networks; topology",
}

@Article{Lee:2008:GSF,
  author =       "Jae W. Lee and Man Cheuk Ng and Krste Asanovic",
  title =        "Globally-Synchronized Frames for Guaranteed
                 Quality-of-Service in On-Chip Networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "89--100",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382130",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Future chip multiprocessors (CMPs) may have hundreds
                 to thousands of threads competing to access shared
                 resources, and will require quality-of-service (QoS)
                 support to improve system utilization. Although there
                 has been significant work in QoS support within
                 resources such as caches and memory controllers, there
                 has been less attention paid to QoS support in the
                 multi-hop on-chip networks that will form an important
                 component in future systems. In this paper we introduce
                 Globally-Synchronized Frames (GSF), a framework for
                 providing guaranteed QoS in on-chip networks in terms
                 of minimum bandwidth and a maximum delay bound. The GSF
                 framework can be easily integrated in a conventional
                 virtual channel (VC) router without significantly
                 increasing the hardware complexity. We rely on a fast
                 barrier network, which is feasible in an on-chip
                 environment, to efficiently implement GSF. Performance
                 guarantees are verified by both analysis and
                 simulation. According to our simulations, all
                 concurrent flows receive their guaranteed minimum share
                 of bandwidth in compliance with a given bandwidth
                 allocation. The average throughput degradation of GSF
                 on a 8x8 mesh network is within 10\% compared to the
                 conventional best-effort VC router in most cases.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "chip multiprocessors; interconnects; multicores;
                 on-chip network; quality-of-service; resource
                 management; router; software interface",
}

@Article{Kim:2008:PCN,
  author =       "Martha Mercaldi Kim and John D. Davis and Mark Oskin
                 and Todd Austin",
  title =        "Polymorphic On-Chip Networks",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "101--112",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1109/ISCA.2008.25",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "As the number of cores per die increases, be they
                 processors, memory blocks, or custom accelerators, the
                 on-chip interconnect the cores use to communicate gains
                 importance. We begin this study with an
                 area-performance analysis of the interconnect design
                 space. We find that there is no single network design
                 that yields optimal performance across a range of
                 traffic patterns. This indicates that there is an
                 opportunity to gain performance by customizing the
                 interconnect to a particular application or workload.
                 We propose polymorphic on-chip networks to enable
                 per-application network customization. This network can
                 be configured prior to application runtime, to have the
                 topology and buffering of arbitrary network designs.
                 This paper proposes one such polymorphic network
                 architecture. We demonstrate its modes of
                 configurability, and evaluate the polymorphic network
                 architecture design space, producing polymorphic
                 fabrics that minimize the network area overhead.
                 Finally, we expand the network on chip design space to
                 include a polymorphic network design, showing that a
                 single polymorphic network is capable of implementing
                 all of the pareto optimal fixed-network designs.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "configurable hardware; on-chip network",
}

@Article{Baugh:2008:UHM,
  author =       "Lee Baugh and Naveen Neelakantam and Craig Zilles",
  title =        "Using Hardware Memory Protection to Build a
                 High-Performance, Strongly-Atomic Hybrid Transactional
                 Memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "115--126",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382132",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "We demonstrate how fine-grained memory protection can
                 be used in support of transactional memory systems:
                 first showing how a software transactional memory
                 system (STM) can be made strongly atomic by using
                 memory protection on transactionally-held state, then
                 showing how such a strongly-atomic STM can be used with
                 a bounded hardware TM system to build a hybrid TM
                 system in which zero-overhead hardware transactions may
                 safely run concurrently with potentially-conflicting
                 software transactions. We experimentally demonstrate
                 how this hybrid TM organization avoids the common-case
                 overheads associated with previous hybrid TM proposals,
                 achieving performance rivaling an unbounded HTM system
                 without the hardware complexity of ensuring completion
                 of arbitrary transactions in hardware. As part of our
                 findings, we identify key policies regarding contention
                 management within and across the hardware and software
                 TM components that are key to achieving robust
                 performance with a hybrid TM.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "abort handler; hybrid; memory protection; primitives;
                 strong atomicity; transactional memory",
}

@Article{Bobba:2008:TEE,
  author =       "Jayaram Bobba and Neelam Goyal and Mark D. Hill and
                 Michael M. Swift and David A. Wood",
  title =        "{TokenTM}: Efficient Execution of Large Transactions
                 with Hardware Transactional Memory",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "127--138",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382133",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Current hardware transactional memory systems seek to
                 simplify parallel programming, but assume that large
                 transactions are rare, so it is acceptable to penalize
                 their performance or concurrency. However, future
                 programmers may wish to use large transactions more
                 often in order to integrate with higher-level
                 programming models (e.g., database transactions) or
                 perform selected I/O operations. To prevent the 'small
                 transactions are common' assumption from becoming
                 self-fulfilling, this paper contributes TokenTM --- an
                 unbounded HTM that uses the abstraction of tokens to
                 precisely track conflicts on an unbounded number of
                 memory blocks. TokenTM implements tokens with new
                 mechanisms, including metastate fission/fusion and fast
                 token release. TokenTM executes small transactions
                 fast, executes concurrent large transactions with no
                 penalty to nonconflicting transactions, and gracefully
                 handles paging, context switching, and System-V-style
                 shared memory.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "coherence protocols; hardware transactional memory;
                 metastates; tokens; transactional memory; unbounded
                 transactions",
}

@Article{Shriraman:2008:FDT,
  author =       "Arrvindh Shriraman and Sandhya Dwarkadas and Michael
                 L. Scott",
  title =        "Flexible Decoupled Transactional Memory Support",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "139--150",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1109/ISCA.2008.17",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "A high-concurrency transactional memory (TM)
                 implementation needs to track concurrent accesses,
                 buffer speculative updates, and manage conflicts. We
                 present a system, FlexTM (FLEXible Transactional
                 Memory), that coordinates four decoupled hardware
                 mechanisms: read and write signatures, which summarize
                 per-thread access sets; per-thread conflict summary
                 tables (CSTs), which identify the threads with which
                 conflicts have occurred; Programmable Data Isolation,
                 which maintains speculative updates in the local cache
                 and employs a thread-private buffer (in virtual memory)
                 in the rare event of overflow; and Alert-On-Update,
                 which selectively notifies threads about coherence
                 events. All mechanisms are software-accessible, to
                 enable virtualization and to support transactions of
                 arbitrary length. FlexTM allows software to determine
                 when to manage conflicts (either eagerly or lazily),
                 and to employ a variety of conflict management and
                 commit protocols. We describe an STM-inspired protocol
                 that uses CSTs to manage conflicts in a distributed
                 manner (no global arbitration) and allows parallel
                 commits. In experiments with a prototype on
                 Simics/GEMS, FlexTM exhibits 5x speedup over
                 high-quality software TM, with no loss in policy
                 flexibility. Its distributed commit protocol is also
                 more efficient than a central hardware manager. Our
                 results highlight the importance of flexibility in
                 determining when to manage conflicts: lazy maximizes
                 concurrency and helps to ensure forward progress while
                 eager provides better overall utilization in a
                 multi-programmed system.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "cache coherence; Conflict detection; FlexTM; Hardware;
                 Multiprocessors; RTM; Transactional memory",
}

@Article{Vantrease:2008:CSI,
  author =       "Dana Vantrease and Robert Schreiber and Matteo
                 Monchiero and Moray McLaren and Norman P. Jouppi and
                 Marco Fiorentino and Al Davis and Nathan Binkert and
                 Raymond G. Beausoleil and Jung Ho Ahn",
  title =        "{Corona}: System Implications of Emerging Nanophotonic
                 Technology",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "153--164",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382135",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "We expect that many-core microprocessors will push
                 performance per chip from the 10 gigaflop to the 10
                 teraflop range in the coming decade. To support this
                 increased performance, memory and inter-core bandwidths
                 will also have to scale by orders of magnitude. Pin
                 limitations, the energy cost of electrical signaling,
                 and the non-scalability of chip-length global wires are
                 significant bandwidth impediments. Recent developments
                 in silicon nanophotonic technology have the potential
                 to meet these off- and on-stack bandwidth requirements
                 at acceptable power levels. Corona is a 3D many-core
                 architecture that uses nanophotonic communication for
                 both inter-core communication and off-stack
                 communication to memory or I/O devices. Its peak
                 floating-point performance is 10 teraflops. Dense
                 wavelength division multiplexed optically connected
                 memory modules provide 10 terabyte per second memory
                 bandwidth. A photonic crossbar fully interconnects its
                 256 low-power multithreaded cores at 20 terabyte per
                 second bandwidth. We have simulated a 1024 thread
                 Corona system running synthetic benchmarks and scaled
                 versions of the SPLASH-2 benchmark suite. We believe
                 that in comparison with an electrically-connected
                 many-core alternative that uses the same on-stack
                 interconnect power, Corona can provide 2 to 6 times
                 more performance on many memory intensive workloads,
                 while simultaneously reducing power.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "3D stacking; many-core CMP; nanophotonics; on-chip
                 Networks",
}

@Article{Kreger-Stickles:2008:MAI,
  author =       "Lucas Kreger-Stickles and Mark Oskin",
  title =        "Microcoded Architectures for Ion-Tap Quantum
                 Computers",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "165--176",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382136",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In this paper we present the first ever systematic
                 design space exploration of microcoded software fault
                 tolerant ion-trap quantum computers. This exploration
                 reveals the critical importance of a well-tuned
                 microcode for providing high performance and ensuring
                 system reliability. In addition, we find that, despite
                 recent advances in the reliability of quantum memory,
                 the impact of errors due to stored quantum data is now,
                 and will continue to be, a major source of systemic
                 error. Finally, our exploration reveals a single design
                 which out performs all others we considered in run
                 time, fidelity and area. For completeness our design
                 space exploration includes designs from prior work and
                 we find a novel design that is 1/2 the size, 3 times as
                 fast, and an order of magnitude more reliable.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "architecture; ion-trap; microcoded; quantum",
}

@Article{Isailovic:2008:RQC,
  author =       "Nemanja Isailovic and Mark Whitney and Yatish Patel
                 and John Kubiatowicz",
  title =        "Running a Quantum Circuit at the Speed of Data",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "177--188",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382137",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "We analyze circuits for kernels from popular quantum
                 computing applications, characterizing the hardware
                 resources necessary to take ancilla preparation off the
                 critical path. The result is a chip entirely dominated
                 by ancilla generation circuits. To address this issue,
                 we introduce optimized ancilla factories and analyze
                 their structure and physical layout for ion trap
                 technology. We introduce a new quantum computing
                 architecture with highly concentrated data-only regions
                 surrounded by shared ancilla factories. The results are
                 a reduced dependence on costly teleportation, more
                 efficient distribution of generated ancillae and more
                 than five times speedup over previous proposals.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "ancilla factory; microarchitecture; quantum",
}

@Article{Liang:2008:RVT,
  author =       "Xiaoyao Liang and Gu-Yeon Wei and David Brooks",
  title =        "{ReVIVaL}: a Variation-Tolerant Architecture Using
                 Voltage Interpolation and Variable Latency",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "191--202",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382138",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Process variations are poised to significantly degrade
                 performance benefits sought by moving to the next
                 nanoscale technology node. Parameter fluctuations in
                 devices can introduce large variations in peak
                 operation among chips, among cores on a single chip,
                 and among microarchitectural blocks within one core.
                 Hence, it will be difficult to only rely on traditional
                 frequency binning to efficiently cover the large
                 variations that are expected. Furthermore, multiple
                 voltage/frequency domains introduce significant
                 hardware overhead and alone cannot address the full
                 extent of delay variations expected in future
                 multi-core systems. In this paper, we present ReVIVaL,
                 which combines two fine-grained post-fabrication tuning
                 techniques---voltage interpolation(VI) and variable
                 latency(VL). We show that the frequency variation
                 between chips, between cores on one chip, and between
                 functional units within cores can be reduced to a very
                 small range. The effectiveness of these techniques are
                 further verified through experiments on test chips
                 fabricated in a 130nm CMOS process. Detailed
                 architectural simulations of multi-core processors
                 demonstrate significant performance and power
                 advantages are possible by combining variable latency
                 with voltage interpolation.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "chip multiprocessor; microarchitecture; process
                 variations",
}

@Article{Wilkerson:2008:TCC,
  author =       "Chris Wilkerson and Hongliang Gao and Alaa R.
                 Alameldeen and Zeshan Chishti and Muhammad Khellah and
                 Shih-Lien Lu",
  title =        "Trading off Cache Capacity for Reliability to Enable
                 Low Voltage Operation",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "203--214",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382139",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "One of the most effective techniques to reduce a
                 processor's power consumption is to reduce supply
                 voltage. However, reducing voltage in the context of
                 manufacturing-induced parameter variations can cause
                 many types of memory circuits to fail. As a result,
                 voltage scaling is limited by a minimum voltage, often
                 called Vccmin, beyond which circuits may not operate
                 reliably. Large memory structures (e.g., caches)
                 typically set Vccmin for the whole processor. In this
                 paper, we propose two architectural techniques that
                 enable microprocessor caches (L1and L2), to operate at
                 low voltages despite very high memory cell failure
                 rates. The Word-disable scheme combines two consecutive
                 cache lines, to form a single cache line where only
                 non-failing words are used. The Bit-fix scheme uses a
                 quarter of the ways in a cache set to store positions
                 and fix bits for failing bits in other ways of the set.
                 During high voltage operation, both schemes allow use
                 of the entire cache. During low voltage operation, they
                 sacrifice cache capacity by 50\% and 25\%,
                 respectively, to reduce Vccmin below 500mV. Compared to
                 current designs with a Vccmin of 825mV, our schemes
                 enable a 40\% voltage reduction, which reduces power by
                 85\% and energy per instruction (EPI) by 53\%",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "cache; cache design; low power; low voltage;
                 reliability; SRAM; stability; Vccmin",
}

@Article{Roesner:2008:CDP,
  author =       "Franziska Roesner and Doug Burger and Stephen W.
                 Keckler",
  title =        "Counting Dependence Predictors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "215--226",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382140",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Modern processors rely on memory dependence prediction
                 to execute load instructions as early as possible,
                 speculating that they are not dependent on an earlier,
                 unissued store. To date, the most sophisticated
                 dependence predictors, such as Store Sets, have been
                 tightly coupled to the fetch and execution streams,
                 requiring global knowledge of the in-flight stream of
                 stores to synchronize loads with specific stores. This
                 paper proposes a new dependence predictor design,
                 called a Counting Dependence Predictor (CDP). The key
                 feature of CDPs is that the prediction mechanism
                 predicts some set of events for which a particular
                 dynamic load should wait, which may include some number
                 of matching stores. By waiting for local events only,
                 this dependence predictor can work effectively in a
                 distributed microarchitecture where centralized fetch
                 and execution streams are infeasible or undesirable. We
                 describe and evaluate a distributed Counting Dependence
                 Predictor and protocol that achieves 92\% of the
                 performance of perfect memory disambiguation. It
                 outperforms a load-wait table, similar to the Alpha
                 21264, by 11\%. Idealized, centralized implementations
                 of Store Sets and the Exclusive Collision Predictor,
                 both of which would be difficult to implement in a
                 distributed microarchitecture, achieve 97\% and 94\% of
                 oracular performance, respectively.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "dependence prediction; memory systems; multiprocessor
                 and multicore architectures",
}

@Article{Jerger:2008:VCT,
  author =       "Natalie Enright Jerger and Li-Shiuan Peh and Mikko
                 Lipasti",
  title =        "Virtual Circuit Tree Multicasting: a Case for On-Chip
                 Hardware Multicast Support",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "229--240",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382141",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Current state-of-the-art on-chip networks provide
                 efficiency, high throughput, and low latency for
                 one-to-one (unicast) traffic. The presence of
                 one-to-many (multicast) or one-to-all (broadcast)
                 traffic can significantly degrade the performance of
                 these designs, since they rely on multiple unicasts to
                 provide one-to-many communication. This results in a
                 burst of packets from a single source and is a very
                 inefficient way of performing multicast and broadcast
                 communication. This inefficiency is compounded by the
                 proliferation of architectures and coherence protocols
                 that require multicast and broadcast communication. In
                 this paper, we characterize a wide array of on-chip
                 communication scenarios that benefit from hardware
                 multicast support. We propose Virtual Circuit Tree
                 Multicasting (VCTM) and present a detailed multicast
                 router design that improves network performance by up
                 to 90\% while reducing network activity (hence power)
                 by up to 53\%. Our VCTM router is flexible enough to
                 improve interconnect performance for a broad spectrum
                 of multicasting scenarios,and achieves these benefits
                 with straightforward and inexpensive extensions to a
                 state-of-the-art packet-switched router.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "cache coherence protocol; interconnection network;
                 multiprocessor",
}

@Article{Kodi:2008:IIR,
  author =       "Avinash Karanth Kodi and Ashwini Sarathy and Ahmed
                 Louri",
  title =        "{iDEAL}: Inter-router Dual-Function Energy and
                 Area-Efficient Links for Network-on-Chip {(NoC)}
                 Architectures",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "241--250",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382142",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Network-on-Chip (NoC) architectures have been adopted
                 by a growing number of multi-core designs as a flexible
                 and scalable solution to the increasing wire delay
                 constraints in the deep sub-micron regime. However, the
                 shrinking feature size limits the performance of NoCs
                 due to power and area constraints. Research into the
                 optimization of NoCs has shown that a reduction in the
                 number of buffers in the NoC routers reduces the power
                 and area overhead but degrades the network performance.
                 In this paper, we propose iDEAL, a low-power
                 area-efficient NoC architecture by reducing the number
                 of buffers within the router. To overcome the
                 performance degradation caused by the reduced buffer
                 size, we propose to use adaptive dual-function links
                 capable of data transmission as well as data storage
                 when required. Simulation results for the proposed
                 architecture show that reducing the router buffer size
                 in half and using the adaptive dual-function links
                 achieves nearly 40\% savings in buffer power, 30\%
                 savings in overall network power and about 41\% savings
                 in the router area, with only a marginal 1-3\% drop in
                 performance. Moreover, the performance in iDEAL can be
                 further improved by aggressive and speculative flow
                 control techniques.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "interconnects; low-power architecture;
                 network-on-chip",
}

@Article{Park:2008:MML,
  author =       "Dongkook Park and Soumya Eachempati and Reetuparna Das
                 and Asit K. Mishra and Yuan Xie and N. Vijaykrishnan
                 and Chita R. Das",
  title =        "{MIRA}: a Multi-layered On-Chip Interconnect Router
                 Architecture",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "251--261",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1109/ISCA.2008.13",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Recently, Network-on-Chip (NoC) architectures have
                 gained popularity to address the interconnect delay
                 problem for designing CMP / multi-core / SoC systems in
                 deep sub-micron technology. However, almost all prior
                 studies have focused on 2D NoC designs. Since three
                 dimensional (3D) integration has emerged to mitigate
                 the interconnect delay problem, exploring the NoC
                 design space in 3D can provide ample opportunities to
                 design high performance and energy-efficient NoC
                 architectures. In this paper, we propose a 3D stacked
                 NoC router architecture, called MIRA, which unlike the
                 3D routers in previous works, is stacked into multiple
                 layers and optimized to reduce the overall area
                 requirements and power consumption. We discuss the
                 design details of a four-layer 3D NoC and its enhanced
                 version with additional express channels, and compare
                 them against a ($ 6 \mu $) 2D design and a baseline 3D
                 design. All the designs are evaluated using a
                 cycle-accurate 3D NoC simulator, and integrated with
                 the Orion power model for performance and power
                 analysis. The simulation results with synthetic and
                 application traces demonstrate that the proposed
                 multi-layered NoC routers can outperform the 2D and
                 na{\"\i}ve 3D designs in terms of performance and
                 power. It can achieve up to 42\% reduction in power
                 consumption and up to 51\% improvement in average
                 latency with synthetic workloads. With real workloads,
                 these benefits are around 67\% and 38\%,
                 respectively.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "3D; express channel; express path; Network-on-Chip;
                 NoC; on-chip interconnect; router architecture",
}

@Article{Hower:2008:REE,
  author =       "Derek R. Hower and Mark D. Hill",
  title =        "{Rerun}: Exploiting Episodes for Lightweight Memory
                 Race Recording",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "265--276",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382144",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Multiprocessor deterministic replay has many potential
                 uses in the era of multicore computing, including
                 enhanced debugging, fault tolerance, and intrusion
                 detection. While sources of nondeterminism in a
                 uniprocessor can be recorded efficiently in software,
                 it seems likely that hardware support will be needed in
                 a multiprocessor environment where the outcome of
                 memory races must also be recorded. We develop a memory
                 race recording mechanism, called Rerun, that uses small
                 hardware state ($ \approx 166 $ bytes/core), writes a
                 small race log ($ \approx 4 $ bytes/kilo- instruction),
                 and operates well as the number of cores per system
                 scales (e.g., to 16 cores). Rerun exploits the dual of
                 conventional wisdom in race recording: Rather than
                 record information about individual memory accesses
                 that conflict, we record how long a thread executes
                 without conflicting with other threads. In particular,
                 Rerun passively creates atomic episodes. Each episode
                 is a dynamic instruction sequence that a thread happens
                 to execute without interacting with other threads.
                 Rerun uses Lamport Clocks to order episodes and enable
                 replay of an equivalent execution.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "determinism; multicore; race recording",
}

@Article{Lucia:2008:AAD,
  author =       "Brandon Lucia and Joseph Devietti and Karin Strauss
                 and Luis Ceze",
  title =        "{Atom-Aid}: Detecting and Surviving Atomicity
                 Violations",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "277--288",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382145",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Writing shared-memory parallel programs is
                 error-prone. Among the concurrency errors that
                 programmers often face are atomicity violations, which
                 are especially challenging. They happen when
                 programmers make incorrect assumptions about atomicity
                 and fail to enclose memory accesses that should occur
                 atomically inside the same critical section. If these
                 accesses happen to be interleaved with conflicting
                 accesses from different threads, the program might
                 behave incorrectly. Recent architectural proposals
                 arbitrarily group consecutive dynamic memory operations
                 into atomic blocks to enforce memory ordering at a
                 coarse grain. This provides what we call implicit
                 atomicity, as the atomic blocks are not derived from
                 explicit program annotations. In this paper, we make
                 the fundamental observation that implicit atomicity
                 probabilistically hides atomicity violations by
                 reducing the number of interleaving opportunities
                 between memory operations. We then propose Atom-Aid,
                 which creates implicit atomic blocks intelligently
                 instead of arbitrarily, dramatically reducing the
                 probability that atomicity violations will manifest
                 themselves. Atom-Aid is also able to report where
                 atomicity violations might exist in the code, providing
                 resilience and debuggability. We evaluate Atom-Aid
                 using buggy code from applications including Apache,
                 MySQL, and XMMS, showing that Atom-Aid virtually
                 eliminates the manifestation of atomicity violations.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "bug; multiprocessors; parallel programming; software
                 reliability",
}

@Article{Montesinos:2008:DRD,
  author =       "Pablo Montesinos and Luis Ceze and Josep Torrellas",
  title =        "{DeLorean}: Recording and Deterministically Replaying
                 Shared-Memory Multiprocessor Execution Efficiently",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "289--300",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1109/ISCA.2008.36",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Support for deterministic replay of multithreaded
                 execution can greatly help in finding concurrency bugs.
                 For highest effectiveness, replay schemes should (i)
                 record at production-run speed, (ii) keep their logging
                 requirements minute, and (iii) replay at a speed
                 similar to that of the initial execution. In this
                 paper, we propose a new substrate for deterministic
                 replay that provides substantial advances along these
                 axes. In our proposal, processors execute blocks of
                 instructions atomically, as in transactional memory or
                 speculative multithreading, and the system only needs
                 to record the commit order of these blocks. We call our
                 scheme DeLorean. Our results show that DeLorean records
                 execution at a speed similar to that of Release
                 Consistency (RC) execution and replays at about 82\% of
                 its speed. In contrast, most current schemes only
                 record at the speed of Sequential Consistency (SC)
                 execution. Moreover, DeLorean only needs 7.5\% of the
                 log size needed by a state-of-the-art scheme. Finally,
                 DeLorean can be configured to need only 0.6\% of the
                 log size of the state-of-the-art scheme at the cost of
                 recording at 86\% of RC's execution speed --- still
                 faster than SC. In this configuration, the log of an
                 8-processor 5-GHz machine is estimated to be only about
                 20GB per day.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sankar:2008:IDP,
  author =       "Sriram Sankar and Sudhanva Gurumurthi and Mircea R.
                 Stan",
  title =        "Intra-disk Parallelism: An Idea Whose Time Has Come",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "303--314",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382147",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Server storage systems use a large number of disks to
                 achieve high performance, thereby consuming a
                 significant amount of power. In this paper, we propose
                 to significantly reduce the power consumed by such
                 storage systems via intra-disk parallelism, wherein
                 disk drives can exploit parallelism in the I/O request
                 stream. Intra-disk parallelism can facilitate replacing
                 a large disk array with a smaller one, using the
                 minimum number of disk drives needed to satisfy the
                 capacity requirements. We show that the design space of
                 intra-disk parallelism is large and present a taxonomy
                 to formulate specific implementations within this
                 space. Using a set of commercial workloads, we perform
                 a limit study to identify the key performance
                 bottlenecks that arise when we replace a storage array
                 that is tuned to provide high performance with a single
                 high-capacity disk drive. We show that it is possible
                 to match, and even surpass, the performance of a
                 storage array for these workloads by using a single
                 disk drive of sufficient capacity that exploits
                 intra-disk parallelism, while significantly reducing
                 the power consumed by the storage system. We evaluate
                 the performance and power consumption of disk arrays
                 composed of intra-disk parallel drives, and discuss
                 engineering and cost issues related to the
                 implementation and deployment of such disk drives.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "disk; I/O; parallelism; power; storage",
}

@Article{Lim:2008:UDN,
  author =       "Kevin Lim and Parthasarathy Ranganathan and Jichuan
                 Chang and Chandrakant Patel and Trevor Mudge and Steven
                 Reinhardt",
  title =        "Understanding and Designing New Server Architectures
                 for Emerging Warehouse-Computing Environments",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "315--326",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382148",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This paper seeks to understand and design
                 next-generation servers for emerging
                 'warehouse-computing' environments. We make two key
                 contributions. First, we put together a detailed
                 evaluation infrastructure including a new benchmark
                 suite for warehouse-computing workloads, and detailed
                 performance, cost, and power models, to quantitatively
                 characterize bottlenecks. Second, we study a new
                 solution that incorporates volume non-server-class
                 components in novel packaging solutions, with memory
                 sharing and flash-based disk caching. Our results show
                 that this approach has promise, with a 2X improvement
                 on average in performance-per-dollar for our benchmark
                 suite.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "evaluation; server architecture; warehouse-computing",
}

@Article{Kgil:2008:INF,
  author =       "Taeho Kgil and David Roberts and Trevor Mudge",
  title =        "Improving {NAND} Flash Based Disk Caches",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "327--338",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1109/ISCA.2008.32",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Flash is a widely used storage device that provides
                 high density and low power, appealing properties for
                 general purpose computing. Today, its usual application
                 is in portable special purpose devices such as MP3
                 players. In this paper we examine its use in the server
                 domain --- a more general purpose environment.
                 Aggressive process scaling and the use of multi-level
                 cells continues to improve density ahead of Moore's Law
                 predictions, making Flash even more attractive as a
                 general purpose memory solution. Unfortunately,
                 reliability limits the use of Flash. To seriously
                 consider Flash in the server domain, architectural
                 support must exist to address this concern. This paper
                 first shows how Flash can be used in today's server
                 platforms as a disk cache. It then proposes two
                 improvements. The first improves performance and
                 reliability by splitting Flash based disk caches into
                 separate read and write regions. The second improves
                 reliability by employing a programmable Flash memory
                 controller. It can change the error code strength
                 (number of correctable bits) and the number of bits
                 that a memory cell can store (cell density) according
                 to the demands of the application. Our studies show
                 that Flash reduces overall power consumed by the system
                 memory and hard disk drive up to 3 times while
                 maintaining performance. We also show that Flash
                 lifetime can be improved by a factor of 20 when using a
                 programmable Flash memory controller, if some
                 performance degradation (below 5\%) is acceptable.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "data center; disk cache; Flash; Flash memory
                 controller; NAND Flash",
}

@Article{Li:2008:OEA,
  author =       "Xiaodong Li and Sarita V. Adve and Pradip Bose and
                 Jude A. Rivers",
  title =        "Online Estimation of Architectural Vulnerability
                 Factor for Soft Errors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "341--352",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382150",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "As CMOS technology scales and more transistors are
                 packed on to the same chip, soft error reliability has
                 become an increasingly important design issue for
                 processors. Prior research has shown that there is
                 significant architecture-level masking, and many soft
                 error solutions take advantage of this effect. Prior
                 work has also shown that the degree of such masking can
                 vary significantly across workloads and between
                 individual workload phases, motivating dynamic
                 adaptation of reliability solutions for optimal cost
                 and benefit. For such adaptation, it is important to be
                 able to accurately estimate the amount of masking or
                 the architecture vulnerability factor (AVF) online,
                 while the program is running. Unfortunately, existing
                 solutions for estimating AVF are often based on offline
                 simulators and hard to implement in real processors.
                 This paper proposes a novel way of estimating AVF
                 online, using simple modifications to the processor.
                 The estimation method applies to both logic and storage
                 structures on the processor. Compared to previous
                 methods for estimating AVF, our method does not require
                 any offline simulation or calibration for different
                 workloads. We tested our method with a widely used
                 simulator from industry, for four processor structures
                 and for 100 to 200 intervals of each of eleven SPEC
                 benchmarks. The results show that our method provides
                 acceptably accurate AVF estimates at runtime. The
                 absolute error rarely exceeds 0.08 across all
                 application intervals for all structures, and the mean
                 absolute error for a given application and structure
                 combination is always within 0.05.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "AVF estimation; processor reliability; soft error",
}

@Article{Shin:2008:PWR,
  author =       "Jeonghee Shin and Victor Zyuban and Pradip Bose and
                 Timothy M. Pinkston",
  title =        "A Proactive Wearout Recovery Approach for Exploiting
                 Microarchitectural Redundancy to Extend Cache {SRAM}
                 Lifetime",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "353--362",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382151",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Microarchitectural redundancy has been proposed as a
                 means of improving chip lifetime reliability. It is
                 typically used in a reactive way, allowing chips to
                 maintain operability in the presence of failures by
                 detecting and isolating, correcting, and/or replacing
                 components on a first-come, first-served basis only
                 after they become faulty. In this paper, we explore an
                 alternative, more preferred method of exploiting
                 microarchitectural redundancy to enhance chip lifetime
                 reliability. In our proposed approach, redundancy is
                 used proactively to allow non-faulty microarchitecture
                 components to be temporarily deactivated, on a rotating
                 basis, to suspend and/or recover from certain wearout
                 effects. This approach improves chip lifetime
                 reliability by warding off the onset of wearout
                 failures as opposed to reacting to them posteriorly.
                 Applied to on-chip cache SRAM for combating
                 NBTI-induced wearout failure, our proactive wearout
                 recovery approach increases lifetime reliability
                 (measured in mean-time-to-failure) of the cache by
                 about a factor of seven relative to no use of
                 microarchitectural redundancy and a factor of five
                 relative to conventional reactive use of redundancy
                 having similar area overhead.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "lifetime reliability; microarchitectural redundancy;
                 proactive approach; wearout recovery",
}

@Article{Teodorescu:2008:VAA,
  author =       "Radu Teodorescu and Josep Torrellas",
  title =        "Variation-Aware Application Scheduling and Power
                 Management for Chip Multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "363--374",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1109/ISCA.2008.40",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Within-die process variation causes individual cores
                 in a ChipMultiprocessor (CMP) to differ substantially
                 in both static power consumed and maximum frequency
                 supported. In this environment,ignoring variation
                 effects when scheduling applications or when managing
                 power with Dynamic Voltage and Frequency Scaling (DVFS)
                 is suboptimal. This paper proposes variation-aware
                 algorithms for application scheduling and power
                 management. One such power management algorithm, called
                 {\em LinOpt}, uses linear programming to find the best
                 voltage and frequency levels for each of the cores in
                 the CMP --- maximizing throughput at a given power
                 budget. In a 20-core CMP, the combination of
                 variation-aware application scheduling and {\em
                 LinOpt\/} increases the average throughput by 12--17\%
                 and reduces the average $ E D^2 $ by 30--38\% --- all
                 relative to using variation-aware scheduling together
                 with a simple extension to Intel's Foxton power
                 management algorithm.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "application scheduling; power management; process
                 variation",
}

@Article{Chen:2008:FHA,
  author =       "Shimin Chen and Michael Kozuch and Theodoros Strigkos
                 and Babak Falsafi and Phillip B. Gibbons and Todd C.
                 Mowry and Vijaya Ramachandran and Olatunji Ruwase and
                 Michael Ryan and Evangelos Vlachos",
  title =        "Flexible Hardware Acceleration for Instruction-Grain
                 Program Monitoring",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "377--388",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382153",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Instruction-grain program monitoring tools, which
                 check and analyze executing programs at the granularity
                 of individual instructions, are invaluable for quickly
                 detecting bugs and security attacks and then limiting
                 their damage (via containment and/or recovery).
                 Unfortunately, their fine-grain nature implies very
                 high monitoring overheads for software-only tools,
                 which are typically based on dynamic binary
                 instrumentation. Previous hardware proposals either
                 focus on mechanisms that target specific bugs or
                 address only the cost of binary instrumentation. In
                 this paper, we propose a flexible hardware solution for
                 accelerating a wide range of instruction-grain
                 monitoring tools. By examining a number of diverse
                 tools (for memory checking, security tracking, and data
                 race detection), we identify three significant common
                 sources of overheads and then propose three novel
                 hardware techniques for addressing these overheads:
                 Inheritance Tracking, Idempotent Filters, and
                 Metadata-TLBs. Together, these constitute a
                 general-purpose hardware acceleration framework.
                 Experimental results show our framework reduces
                 overheads by 2-3X over the previous state-of-the-art,
                 while supporting the needed flexibility.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "hardware acceleration; idempotent filter; inheritance
                 tracking; instruction-grain program monitoring; LBA;
                 lifeguards; log-based architectures; metadata-TLB",
}

@Article{Clark:2008:VVE,
  author =       "Nathan Clark and Amir Hormati and Scott Mahlke",
  title =        "{VEAL}: Virtualized Execution Accelerator for Loops",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "389--400",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1109/ISCA.2008.33",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Performance improvement solely through transistor
                 scaling is becoming more and more difficult, thus it is
                 increasingly common to see domain specific accelerators
                 used in conjunction with general purpose processors to
                 achieve future performance goals. There is a serious
                 drawback to accelerators, though: binary compatibility.
                 An application compiled to utilize an accelerator
                 cannot run on a processor without that accelerator, and
                 applications that do not utilize an accelerator will
                 never use it. To overcome this problem, we propose
                 decoupling the instruction set architecture from the
                 underlying accelerators. Computation to be accelerated
                 is expressed using a processor's baseline instruction
                 set, and light-weight dynamic translation maps the
                 representation to whatever accelerators are available
                 in the system. In this paper, we describe the changes
                 to a compilation framework and processor system needed
                 to support this abstraction for an important set of
                 accelerator designs that support innermost loops. In
                 this analysis, we investigate the dynamic overheads
                 associated with abstraction as well as the
                 static/dynamic tradeoffs to improve the dynamic mapping
                 of loop-nests. As part of the exploration, we also
                 provide a quantitative analysis of the hardware
                 characteristics of effective loop accelerators. We
                 conclude that using a hybrid static-dynamic compilation
                 approach to map computation on to loop-level
                 accelerators is a practical way to increase computation
                 efficiency, without the overheads associated with
                 instruction set modification.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Chen:2008:SSP,
  author =       "Haibo Chen and Xi Wu and Liwei Yuan and Binyu Zang and
                 Pen-chung Yew and Frederic T. Chong",
  title =        "From Speculation to Security: Practical and Efficient
                 Information Flow Tracking Using Speculative Hardware",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "401--412",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382156",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Dynamic information flow tracking (also known as taint
                 tracking) is an appealing approach to combat various
                 security attacks. However, the performance of
                 applications can severely degrade without hardware
                 support for tracking taints. This paper observes that
                 information flow tracking can be efficiently emulated
                 using deferred exception tracking in microprocessors
                 supporting speculative execution. Based on this
                 observation, we propose SHIFT, a low-overhead,
                 software-based dynamic information flow tracking system
                 to detect a wide range of attacks. The key idea is to
                 treat tainted state (describing untrusted data) as
                 speculative state (describing deferred exceptions).
                 SHIFT leverages existing architectural support for
                 speculative execution to track tainted state in
                 registers and needs to instrument only load and store
                 instructions to track tainted state in memory using a
                 bitmap, which results in significant performance
                 advantages. Moreover, by decoupling mechanisms for
                 taint tracking from security policies, SHIFT can detect
                 a wide range of exploits, including high-level semantic
                 attacks. We have implemented SHIFT using the Itanium
                 processor, which has support for deferred exceptions,
                 and by modifying GCC to instrument loads and stores. A
                 security assessment shows that SHIFT can detect both
                 low-level memory corruption exploits as well as
                 high-level semantic attacks with no false positives.
                 Performance measurements show that SHIFT incurs about
                 1\% overhead for server applications. The performance
                 slowdown for SPEC-INT2000 is 2.81X and 2.27X for
                 tracking at byte-level and word-level respectively.
                 Minor architectural improvements to the Itanium
                 processor (adding three simple instructions) can reduce
                 the performance slowdown down to 2.32X and 1.8X for
                 byte-level and word-level tracking, respectively.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "deferred exception; dynamic information flow tracking;
                 speculative execution; taint tracking",
}

@Article{Boneti:2008:SCP,
  author =       "Carlos Boneti and Francisco J. Cazorla and Roberto
                 Gioiosa and Alper Buyuktosunoglu and Chen-Yong Cher and
                 Mateo Valero",
  title =        "Software-Controlled Priority Characterization of
                 {POWER5} Processor",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "415--426",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1109/ISCA.2008.8",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Due to the limitations of instruction-level
                 parallelism, thread-level parallelism has become a
                 popular way to improve processor performance. One
                 example is the IBM POWER5TM processor, a two-context
                 simultaneous-multithreaded dual-core chip. In each SMT
                 core, the IBM POWER5 features two levels of thread
                 resource balancing and prioritization. The first level
                 provides automatic in-hardware resource balancing,
                 while the second level is a software-controlled
                 priority mechanism that presents eight levels of thread
                 priorities. Currently, software-controlled
                 prioritization is only used in limited number of cases
                 in the software platforms due to lack of performance
                 characterization of the effects of this mechanism. In
                 this work, we characterize the effects of the
                 software-based prioritization on several different
                 workloads. We show that the impact of the
                 prioritization significantly depends on the workloads
                 coscheduled on a core. By prioritizing the right task,
                 it is possible to obtain more than two times of
                 throughput improvement for synthetic workloads compared
                 to the baseline. We also present two application case
                 studies targeting two different performance metrics:
                 the first case study improves overall throughput by
                 23.7\% and the second case study reduces the total
                 execution time by 9.3\%. In addition, we show the
                 circumstances when a background thread can be run
                 transparently without affecting the performance of the
                 foreground thread.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "IBM POWER5; performance characterization; simultaneous
                 multithreading; SMT; software-controlled
                 prioritization",
}

@Article{Shye:2008:LLR,
  author =       "Alex Shye and Berkin Ozisikyilmaz and Arindam Mallik
                 and Gokhan Memik and Peter A. Dinda and Robert P. Dick
                 and Alok N. Choudhary",
  title =        "Learning and Leveraging the Relationship between
                 Architecture-Level Measurements and Individual User
                 Satisfaction",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "427--438",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382158",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The ultimate goal of computer design is to satisfy the
                 end-user. In particular computing domains, such as
                 interactive applications, there exists a variation in
                 user expectations and user satisfaction relative to the
                 performance of existing computer systems. In this work,
                 we leverage this variation to develop more efficient
                 architectures that are customized to end-users. We
                 first investigate the relationship between
                 microarchitectural parameters and user satisfaction.
                 Specifically, we analyze the relationship between
                 hardware performance counter (HPC) readings and
                 individual satisfaction levels reported by users for
                 representative applications. Our results show that the
                 satisfaction of the user is strongly correlated to the
                 performance of the underlying hardware. More
                 importantly, the results show that user satisfaction is
                 highly user-dependent. To take advantage of these
                 observations, we develop a framework called
                 Individualized Dynamic Voltage and Frequency Scaling
                 (iDVFS). We study a group of users to characterize the
                 relationship between the HPCs and individual user
                 satisfaction levels. Based on this analysis, we use
                 artificial neural networks to model the function from
                 HPCs to user satisfaction for individual users. This
                 model is then used online to predict user satisfaction
                 and set the frequency level accordingly. A second set
                 of user studies demonstrates that iDVFS reduces the CPU
                 power consumption by over 25\% in representative
                 applications as compared to the Windows XP DVFS
                 algorithm.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "dynamic power management; hardware performance
                 counters; learning user satisfaction; user-aware
                 architectures",
}

@Article{Kumar:2008:AVO,
  author =       "Sanjeev Kumar and Daehyun Kim and Mikhail Smelyanskiy
                 and Yen-Kuang Chen and Jatin Chhugani and Christopher
                 J. Hughes and Changkyu Kim and Victor W. Lee and
                 Anthony D. Nguyen",
  title =        "Atomic Vector Operations on Chip Multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "441--452",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382154",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The current trend is for processors to deliver
                 dramatic improvements in parallel performance while
                 only modestly improving serial performance. Parallel
                 performance is harvested through vector/SIMD
                 instructions as well as multithreading (through both
                 multithreaded cores and chip multiprocessors). Vector
                 parallelism can be more efficiently supported than
                 multithreading, but is often harder for software to
                 exploit. In particular, code with sparse data access
                 patterns cannot easily utilize the vector/SIMD
                 instructions of mainstream processors. Hardware to
                 scatter and gather sparse data has previously been
                 proposed to enable vector execution for these codes.
                 However, on multithreaded architectures, a number of
                 applications spend significant time on atomic
                 operations (e.g., parallel reductions), which cannot be
                 vectorized using previously proposed schemes. This
                 paper proposes architectural support for atomic vector
                 operations (referred to as GLSC) that addresses this
                 limitation. GLSC extends scatter-gather hardware to
                 support atomic memory operations. Our experiments show
                 that the GLSC provides an average performance
                 improvement on a set of important RMS kernels of 54\%
                 for 4-wide SIMD.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "locks; multiprocessors; reductions; SIMD; vector",
}

@Article{Loh:2008:SMA,
  author =       "Gabriel H. Loh",
  title =        "{$3$D}-Stacked Memory Architectures for Multi-core
                 Processors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "453--464",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382159",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Three-dimensional integration enables stacking memory
                 directly on top of a microprocessor, thereby
                 significantly reducing wire delay between the two.
                 Previous studies have examined the performance benefits
                 of such an approach, but all of these works only
                 consider commodity 2D DRAM organizations. In this work,
                 we explore more aggressive 3D DRAM organizations that
                 make better use of the additional die-to-die bandwidth
                 provided by 3D stacking, as well as the additional
                 transistor count. Our simulation results show that with
                 a few simple changes to the 3D-DRAM organization, we
                 can achieve a 1.75x speedup over previously proposed
                 3D-DRAM approaches on our memory-intensive
                 multi-programmed workloads on a quad-core processor.
                 The significant increase in memory system performance
                 makes the L2 miss handling architecture (MHA) a new
                 bottleneck, which we address by combining a novel data
                 structure called the Vector Bloom Filter with dynamic
                 MSHR capacity tuning. Our scalable L2 MHA yields an
                 additional 17.8\% performance improvement over our
                 3D-stacked memory architecture.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
  keywords =     "3D integration; memory; multi-core",
}

@Article{Anonymous:2008:AI,
  author =       "Anonymous",
  title =        "Author Index",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "465--466",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382160",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2008:PI,
  author =       "Anonymous",
  title =        "{Publisher}'s Information",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "468--468",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382161",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Anonymous:2008:CA,
  author =       "Anonymous",
  title =        "Cover Art",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "3",
  pages =        "C1--C1",
  month =        jun,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1394608.1382162",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Aug 6 08:35:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Karne:2008:OSC,
  author =       "Ramesh K. Karne and Alexander L. Wijesinha and George
                 H. {Ford, Jr.}",
  title =        "Opinion: stay on course with an evolution or choose a
                 revolution in computing",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "4",
  pages =        "1--6",
  month =        sep,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1462609.1462611",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Dec 8 14:01:02 MST 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2008:INa,
  author =       "Mark Thorson",
  title =        "{Internet} Nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "4",
  pages =        "7--11",
  month =        sep,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1462609.1462613",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Dec 8 14:01:02 MST 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bengtsson:2008:DSA,
  author =       "Jerker Bengtsson and Bertil Svensson",
  title =        "A domain-specific approach for software development on
                 {Manycore} platforms",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "5",
  pages =        "2--10",
  month =        dec,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1556444.1556446",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 26 11:50:56 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "The programming complexity of increasingly parallel
                 processors calls for new tools that assist programmers
                 in utilising the parallel hardware resources. In this
                 paper we present a set of models that we have developed
                 as part of a tool for mapping dataflow graphs onto
                 manycores. One of the models captures the essentials of
                 manycores identified as suitable for signal processing,
                 and which we use as target for our algorithms. As an
                 intermediate representation we introduce timed
                 configuration graphs, which describe the mapping of a
                 model of an application onto a machine model. Moreover,
                 we show how a timed configuration graph by very simple
                 means can be evaluated using an abstract interpretation
                 to obtain performance feedback. This information can be
                 used by our tool and by the programmer in order to
                 discover improved mappings.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Cederman:2008:SLB,
  author =       "Daniel Cederman and Philippas Tsigas",
  title =        "On sorting and load balancing on {GPUs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "5",
  pages =        "11--18",
  month =        dec,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1556444.1556447",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 26 11:50:56 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In this paper we take a look at GPU-Quicksort, an
                 efficient Quicksort algorithm suitable for the highly
                 parallel multi-core graphics processors. Quicksort had
                 previously been considered an inefficient sorting
                 solution for graphics processors, but GPU-Quicksort
                 often performs better than the fastest known sorting
                 implementations for graphics processors, such as radix
                 and bitonic sort. Quicksort can thus be seen as a
                 viable alternative for sorting large quantities of data
                 on graphics processors.\par

                 We also take look at a comparison of different load
                 balancing schemes. To get maximum performance on the
                 many-core graphics processors it is important to have
                 an even balance of the workload so that all processing
                 units contribute equally to the task at hand. This can
                 be hard to achieve when the cost of a task is not known
                 beforehand and when new sub-tasks are created
                 dynamically during execution. With the recent advent of
                 scatter operations and atomic hardware primitives it is
                 now possible to bring some of the more elaborate
                 dynamic load balancing schemes from the conventional
                 SMP systems domain to the graphics processor domain.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Ha:2008:NBP,
  author =       "Phuong Hoai Ha and Philippas Tsigas and Otto J.
                 Anshus",
  title =        "Non-blocking programming on multi-core graphics
                 processors: (extended abstract)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "5",
  pages =        "19--28",
  month =        dec,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1556444.1556448",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 26 11:50:56 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This paper investigates the synchronization power of
                 coalesced memory accesses, a family of memory access
                 mechanisms introduced in recent large multicore
                 architectures like the CUDA graphics processors. We
                 first design three memory access models to capture the
                 fundamental features of the new memory access
                 mechanisms. Subsequently, we prove the exact
                 synchronization power of these models in terms of their
                 consensus numbers. These tight results show that the
                 coalesced memory access mechanisms can facilitate
                 strong synchronization between the threads of multicore
                 processors, without the need of synchronization
                 primitives other than reads and writes.\par

                 Moreover, based on the intrinsic features of recent GPU
                 architectures, we construct strong synchronization
                 objects like wait-free and t-resilient
                 read-modify-write objects for a general model of recent
                 GPU architectures without strong hardware
                 synchronization primitives like test-and-set and
                 compare-and-swap. Accesses to the wait-free objects
                 have time complexity $ O(N) $, where $N$ is the number
                 of processes. Our result demonstrates that it is
                 possible to construct waitfree synchronization
                 mechanisms for GPUs without the need of strong
                 synchronization primitives in hardware and that
                 wait-free programming is possible for GPUs.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Bhattacharyya:2008:ODT,
  author =       "Shuvra S. Bhattacharyya and Gordon Brebner and
                 J{\"o}rn W. Janneck and Johan Eker and Carl von Platen
                 and Marco Mattavelli and Micka{\"e}l Raulet",
  title =        "{OpenDF}: a dataflow toolset for reconfigurable
                 hardware and multicore systems",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "5",
  pages =        "29--35",
  month =        dec,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1556444.1556449",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 26 11:50:56 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This paper presents the OpenDF framework and recalls
                 that dataflow programming was once invented to address
                 the problem of parallel computing. We discuss the
                 problems with an imperative style, von Neumann
                 programs, and present what we believe are the
                 advantages of using a dataflow programming model. The
                 CAL actor language is briefly presented and its role in
                 the ISO/MPEG standard is discussed. The Dataflow
                 Interchange Format (DIF) and related tools can be used
                 for analysis of actors and networks, demonstrating the
                 advantages of a dataflow approach. Finally, an overview
                 of a case study implementing an MPEG- 4 decoder is
                 given.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Kessler:2008:OCP,
  author =       "Christoph W. Kessler and J{\"o}rg Keller",
  title =        "Optimized on-chip pipelining of memory-intensive
                 computations on the cell {BE}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "5",
  pages =        "36--45",
  month =        dec,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1556444.1556450",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 26 11:50:56 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Multiprocessors-on-chip, such as the Cell BE
                 processor, regularly suffer from restricted bandwidth
                 to off-chip main memory. We propose to reduce memory
                 bandwidth requirements, and thus increase performance,
                 by expressing our application as a task graph, by
                 running dependent tasks concurrently and by pipelining
                 results directly from task to task where possible,
                 instead of buffering in off-chip memory. To maximize
                 bandwidth savings and balance load simultaneously, we
                 solve a mapping problem of tasks to SPEs on the Cell
                 BE. We present three approaches: an integer linear
                 programming formulation that allows to compute
                 Paretooptimal mappings for smaller task graphs, general
                 heuristics, and a problem specific approximation
                 algorithm. We validate the mappings for dataparallel
                 computations and sorting.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Lundvall:2008:APS,
  author =       "H{\aa}kan Lundvall and Kristian Stav{\aa}ker and Peter
                 Fritzson and Christoph Kessler",
  title =        "Automatic parallelization of simulation code for
                 equation-based models with software pipelining and
                 measurements on three platforms",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "5",
  pages =        "46--55",
  month =        dec,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1556444.1556451",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 26 11:50:56 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "In this work we report results from a new integrated
                 method of automatically generating parallel code from
                 Modelica models by combining parallelization at two
                 levels of abstraction. Performing inline expansion of a
                 Runge--Kutta solver combined with fine-grained
                 automatic parallelization of the right-hand side of the
                 resulting equation system opens up new possibilities
                 for generating high performance code, which is becoming
                 increasingly relevant when multi-core computers are
                 becoming commonplace. An implementation, in the form of
                 a backend module for the OpenModelica compiler, has
                 been developed and used for measurements on two
                 architectures: Intel Xeon and SGI Altix 3700 Bx2. This
                 paper also contains some very recent results of a
                 prototype implementation of this parallelization
                 approach on the Cell BE processor architecture.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Fang:2008:SDA,
  author =       "Huan Fang and Mats Brorsson",
  title =        "Scalable directory architecture for distributed shared
                 memory chip multiprocessors",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "5",
  pages =        "56--64",
  month =        dec,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1556444.1556452",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 26 11:50:56 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Traditional Directory-based cache coherence protocol
                 is far from optimal for large-scale cache coherent
                 shared memory multiprocessors due to the increasing
                 latency to access directories stored in DRAM memory.
                 Instead of keeping directories in main memory, we
                 consider distributing the directory together with L2
                 cache across all nodes on a Chip Multiprocessor. Each
                 node contains a processing unit, a private L1 cache, a
                 slice of L2 cache, memory controller and a router. Both
                 L2 cache and memories are distributed shared and
                 interleaved by a subset of memory address bits. All
                 nodes are interconnected through a low latency two
                 dimensional Mesh network. Directory, being a split
                 component to L2 cache, only stores sharing information
                 for blocks while L2 cache stores only data blocks
                 exclusive with L1 cache. Shared L2 cache can increase
                 total effective cache capacity on chip, but also
                 increase the miss latency when data is on a remote
                 node. Being different from Directory Cache structure,
                 our proposal totally removes the directory from memory,
                 which saves memory space and reduces access latency.
                 Compared to L2 cache that combines directory
                 information internally, our L2 cache structure saves up
                 to 88\% cache space and achieves similar performance.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Jonsson:2008:SSE,
  author =       "Bengt Jonsson",
  title =        "State-space exploration for concurrent algorithms
                 under weak memory orderings: (preliminary version)",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "5",
  pages =        "65--71",
  month =        dec,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1556444.1556453",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 26 11:50:56 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Several concurrent implementations of familiar data
                 abstractions such as queues, sets, or maps typically do
                 not follow locking disciplines, and often use lock-free
                 synchronization to gain performance. Since such
                 algorithms are exposed to a weak memory model, they are
                 notoriously hard to get correct, as witnessed by many
                 bugs found in published algorithms. We outline a
                 technique for analyzing correctness of concurrent
                 algorithms under weak memory models, in which a model
                 checker is used to search for correctness violations.
                 The algorithm to be analyzed is transformed into a form
                 where statements may be reordered according to a
                 particular weak memory ordering. The transformed
                 algorithm can then be analyzed by a model-checking
                 tool, e.g., by enumerative state exploration. We
                 illustrate the approach on a small example of a queue,
                 which allows an enqueue operation to be concurrent with
                 a dequeue operation, which we analyze with respect to
                 the RMO memory model defined in SPARC v9.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Abdulla:2008:MCR,
  author =       "Parosh Aziz Abdulla and Fr{\'e}d{\'e}ric Haziza and
                 Mats Kindahl",
  title =        "Model checking race-freeness",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "5",
  pages =        "72--79",
  month =        dec,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1556444.1556454",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 26 11:50:56 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "With the introduction of highly concurrent systems in
                 standard desktop computers, ensuring correctness of
                 industrial-size concurrent programs is becoming
                 increasingly important. One of the most important
                 standards in use for developing multi-threaded programs
                 is the POSIX Threads standard, commonly known as
                 PThreads. Of particular importance, the analysis of
                 industrial code should, as far as possible, be
                 automatic and not require annotations or other forms of
                 specifications of the code.\par

                 Model checking has been one of the most successful
                 approaches to program verification during the last two
                 decades. The size and complexity of applications which
                 can be handled have increased rapidly through
                 integration with symbolic techniques. These methods are
                 designed to work on finite (but large) state spaces.
                 This framework fails to deal with several essential
                 aspects of behaviours for multithreaded programs: there
                 is no bound a priori on the number of threads which may
                 arise in a given run of the system; each thread
                 manipulates local variables which often range over
                 unbounded domains; and the system has a dynamic
                 structure in the sense that threads can be created and
                 killed throughout execution of the system. In this
                 paper we concentrate on checking a particular class of
                 properties for concurrent programs, namely safety
                 properties. In particular, we focus on race-freeness,
                 that is, the absence of race conditions (also known as
                 data races) in shared-variable pthreaded
                 programs.\par

                 We will follow a particular methodology which we have
                 earlier developed for model checking general classes of
                 infinite-state systems [1, 3, 6, 8, 9] and apply a
                 symbolic backward reachability analysis to verify the
                 safety property. Since we construct a model as an
                 over-approximation of the original program, proving the
                 safety property in the model implies that the property
                 also holds in the original system. Surprisingly, it
                 leads to a quite efficient analysis which can be
                 carried out fully automatically.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Sundell:2008:NNB,
  author =       "Hakan Sundell and Philippas Tsigas",
  title =        "{NOBLE}: non-blocking programming support via
                 lock-free shared abstract data types",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "5",
  pages =        "80--87",
  month =        dec,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1556444.1556455",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 26 11:50:56 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "An essential part of programming for multi-core and
                 multi-processor includes efficient and reliable means
                 for sharing data. Lock-free data structures are known
                 as very suitable for this purpose, although experienced
                 to be very complex to design. In this paper, we present
                 a software library of non-blocking abstract data types
                 that have been designed to facilitate lock-free
                 programming for non-experts. The system provides: (i)
                 efficient implementations of the most commonly used
                 data types in concurrent and sequential software
                 design, (ii) a lock-free memory management system, and
                 (iii) a run time-system. The library provides clear
                 semantics that are at least as strong as those of
                 corresponding lock-based implementations of the
                 respective data types. Our software library can be used
                 for facilitating lockfree programming; its design
                 enables the programmer to: (i) replace lock-based
                 components of sequential or parallel code easily and
                 efficiently , (ii) use well-tuned concurrent algorithms
                 inside a software or hardware transactional system. In
                 the paper we describe the design and functionality of
                 the system. We also provide experimental results that
                 show that the library can considerably improve the
                 performance of software systems.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Gidenstam:2008:LLF,
  author =       "Anders Gidenstam and Marina Papatriantafilou",
  title =        "{LFTHREADS}: a lock-free thread library",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "5",
  pages =        "88--92",
  month =        dec,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1556444.1556456",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 26 11:50:56 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This extended abstract presents LFTHREADS, a thread
                 library entirely based on lock-free methods, i.e. no
                 spinlocks or similar synchronization mechanisms are
                 employed in the implementation of the multithreading.
                 Since lockfreedom is highly desirable in
                 multiprocessors/multicores due to its advantages in
                 parallelism, fault-tolerance, convoy-avoidance and
                 more, there is an increased demand in lock-free methods
                 in parallel applications, hence also in
                 multiprocessor/multicore system services. LFTHREADS is
                 the first thread library that provides a lock-free
                 implementation of blocking synchronization primitives
                 for application threads; although the latter may sound
                 like a contradicting goal, such objects have several
                 benefits: e.g. library operations that block and
                 unblock threads on the same synchronization object can
                 make progress in parallel while maintaining the desired
                 thread-level semantics and without having to wait for
                 any 'low' operations among them. Besides, as no
                 spin-locks or similar synchronization mechanisms are
                 employed, memory contention can be reduced and
                 processors/cores are able to do useful work. As a
                 consequence, applications, too, can enjoy enhanced
                 parallelism and fault-tolerance. For the
                 synchronization in LFTHREADS we have introduced a new
                 method, which we call responsibility hand-off (RHO),
                 that does not need any special kernel support. The RHO
                 method is also of independent interest, as it can also
                 serve as a tool for lock-free token passing, management
                 of contention and interaction between scheduling and
                 synchronization. This paper gives an outline and the
                 context of LFTHREADS. For more details the reader is
                 referred to [7] and [8].",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Faxen:2008:WWS,
  author =       "Karl-Filip Fax{\'e}n",
  title =        "{Wool} --- a work stealing library",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "5",
  pages =        "93--100",
  month =        dec,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1556444.1556457",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 26 11:50:56 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "This paper presents some preliminary results on a
                 small light weight user level task management library
                 called Wool. The Wool task scheduler is based on work
                 stealing. The objective of the library is to provide a
                 reasonably convenient programming interface (in
                 particular by not forcing the programmer to write in
                 continuation passing style) in ordinary C while still
                 having a very low task creation overhead. Several task
                 scheduling systems based on work stealing exists, but
                 they are typically either programming languages like
                 Cilk-5 or based on C++ like the Intel TBB or C\# as in
                 the Microsoft TPL. Our main conclusions are that such a
                 direct style interface is indeed possible and yields
                 performance that is comparable to that of the Intel
                 TBB.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}

@Article{Thorson:2008:INb,
  author =       "Mark Thorson",
  title =        "{Internet} nuggets",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "36",
  number =       "5",
  pages =        "101--111",
  month =        dec,
  year =         "2008",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/1556444.1556459",
  ISSN =         "0163-5964 (ACM), 0884-7495 (IEEE)",
  ISSN-L =       "0163-5964",
  bibdate =      "Fri Jun 26 11:50:56 MDT 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "https://dl.acm.org/loi/sigarch",
}