Last update:
Mon Dec 11 10:41:22 MST 2023
J. Gait A checkpointing page store for
write-once optical disk . . . . . . . . 2--9
M.-S. Chen and
K. G. Shin and
D. D. Kandlur Addressing, routing, and broadcasting in
hexagonal mesh multiprocessors . . . . . 10--18
M. Choi and
C. M. Krishna An Adaptive Algorithm to Ensure
Differential Service in a Token-Ring
Network . . . . . . . . . . . . . . . . 19--33
P. R. Chang and
C. S. G. Lee A decomposition approach for balancing
large-scale acyclic data flow graphs . . 34--46
D. M. Blough and
G. M. Masson Performance analysis of a generalized
concurrent error detection procedure . . 47--62
K. C. Cheung and
G. S. Sohi and
K. K. Salvia and
D. K. Pradhan Design and analysis of a gracefully
degrading interleaved memory system . . 63--71
Y. Dotan and
B. Arazi Concurrent logic programming as a
hardware description tool . . . . . . . 72--88
Behrooz Parhami Generalized Signed-Digit Number Systems:
a Unifying Framework for Redundant
Number Representations . . . . . . . . . 89--98
K. G. Shin and
M.-S. Chen On the number of acceptable task
assignments in distributed computing
systems . . . . . . . . . . . . . . . . 99--110
D. L. Lee and
F. H. Lochovsky HYTREM --- a hybrid text-retrieval
machine for large databases . . . . . . 111--123
S. Masuda and
K. Nakajima and
T. Kashiwabara and
T. Fujisawa Crossing minimization in linear
embeddings of graphs . . . . . . . . . . 124--127
D. M. Mandelbaum A systematic method for division with
high average bit skipping . . . . . . . 127--130
Y. N. Srikant Parallel parsing of arithmetic
expressions . . . . . . . . . . . . . . 130--132
P. Heidelberger and
A. Norton and
J. T. Robinson Parallel Quicksort using fetch-and-add 133--138
M. G. Karpovsky and
P. Nagvajara Optimal robust compression of test
responses . . . . . . . . . . . . . . . 138--141
Y. Won and
S. Sahni and
Y. El-Ziq A hardware accelerator for maze routing 141--145
J. L. Aravena Recursive moving window DFT algorithm 145--148
M. L. Brady and
M. Sarrafzadeh Stretching a knock-knee layout for
multilayer wiring . . . . . . . . . . . 148--151
L. M. Ewerbring and
F. T. Luk Computing the singular value
decomposition on the Connection Machine 152--155
J. Jacob and
N. N. Biswas and
J. E. Smith Further comments, with reply, on
``Detection of faults in programmable
logic arrays'' by J. E. Smith . . . . . 155--157
K. Kant and
A. Ravichandran Synthesizing robust data structures ---
an introduction . . . . . . . . . . . . 161--173
W. Najjar and
J.-L. Gaudiot Network resilience: a measure of network
fault tolerance . . . . . . . . . . . . 174--181
T.-H. Lin and
K. G. Shin Location of a faulty module in a
computing system . . . . . . . . . . . . 182--194
S. Rangarajan and
D. Fussell and
M. Malek Built-in testing of integrated circuit
wafers . . . . . . . . . . . . . . . . . 195--205
D. M. Nicol and
P. F. Reynolds, Jr. Optimal dynamic remapping of data
parallel computations . . . . . . . . . 206--219
R. David and
A. Fuentes Fault diagnosis of RAMs from random
testing experiments . . . . . . . . . . 220--229
V. Krishnamoorthy and
K. Thulasiraman and
M. N. S. Swamy Incremental distance and diameter
sequences of a graph: new measures of
network performance . . . . . . . . . . 230--237
M. E. Isenman and
D. E. Shasha Performance and architectural issues for
string matching . . . . . . . . . . . . 238--250
B. Sugla and
D. A. Carlson Extreme area-time tradeoffs in VLSI . . 251--257
C. C. Wang and
D. Pei A VLSI design for computing
exponentiations in $\mathrm{GF}(2^m)$
and its application to generate
pseudorandom number sequences . . . . . 258--262
Tsutomu Sasao and
Philipp Besslich On the complexity of mod-$2$ sum PLA's 262--266
F.-C. Lin and
K. Chen On the design of a unidirectional
systolic array for key enumeration . . . 266--269
A. Majumdar and
C. S. Raghavendra and
M. A. Breuer Fault tolerance in linear systolic
arrays using time redundancy . . . . . . 269--276
R. E. Cypher and
J. L. C. Sanz and
L. Snyder Algorithms for image component labeling
on SIMD mesh-connected computers . . . . 276--281
Y. Brandman and
A. Orlitsky and
J. Hennessy A spectral lower bound technique for the
size of decision trees and two-level
AND/OR circuits . . . . . . . . . . . . 282--287
R. David Comments on ``Signature analysis for
multiple output circuits'' by R. David 287--288
R. Boute Correction to ``Representational and
denotational semantics of digital
systems'' . . . . . . . . . . . . . . . 288--288
A. E. Kamal and
V. C. Hamacher Utilizing Bandwidth Sharing in the
Slotted Ring . . . . . . . . . . . . . . 289--299
Arvind and
R. S. Nikhil Executing a program on the MIT
tagged-token dataflow architecture . . . 300--318
H. Yoon and
K. Y. Lee and
M. T. Liu Performance Analysis of Multibuffered
Packet-Switching Networks in
Multiprocessor Systems . . . . . . . . . 319--327
M. Satyanarayanan and
E. H. Siegel Parallel Communication in a Large
Distributed Environment . . . . . . . . 328--348
G. S. Sohi Instruction issue logic for
high-performance, interruptible,
multiple functional unit, pipelined
computers . . . . . . . . . . . . . . . 349--359
S. J. Piestrak Design of high-speed and cost-effective
self-testing checkers for low-cost
arithmetic codes . . . . . . . . . . . . 360--374
C. Vogt A buffer-based method for storage
allocation in an object-oriented system 375--383
M. J. Quinn Analysis and implementation of
branch-and-bound algorithms on a
hypercube multicomputer . . . . . . . . 384--387
J.-C. Lo and
S. Thanawastien On the design of combinational totally
self-checking $1$-out-of-$3$ code
checkers . . . . . . . . . . . . . . . . 387--393
W.-M. Lin and
V. K. P. Kumar A note on the linear transformation
method for systolic array design . . . . 393--399
S. Saxena and
P. C. P. Bhatt and
V. C. Prasad Efficient VLSI parallel algorithm for
Delaunay triangulation on orthogonal
tree network in two and three dimensions 400--404
B.-R. Choi and
K. H. Park and
M. Kim An improved hardware implementation of
the fault-tolerant clock synchronization
algorithm for large multiprocessor
systems . . . . . . . . . . . . . . . . 404--407
A. M. Paschalis and
C. Efstathiou and
C. Halatsis An efficient TSC $1$-out-of-$3$ code
checker . . . . . . . . . . . . . . . . 407--411
S. J. Hong The design of a testable parallel
multiplier . . . . . . . . . . . . . . . 411--416
R. Leveugle and
G. Saucier Optimized synthesis of concurrently
checked controllers . . . . . . . . . . 419--425
V. S. S. Nair and
J. A. Abraham Real-number codes for fault-tolerant
matrix operations on processor arrays 426--435
V. Balasubramanian and
P. Banerjee Compiler-assisted synthesis of
algorithm-based checking in
multiprocessors . . . . . . . . . . . . 436--446
M. Satyanarayanan and
J. J. Kistler and
P. Kumar and
M. E. Okasaki and
E. H. Siegel and
D. C. Steere Coda: a highly available file system for
a distributed workstation environment 447--459
K.-L. Wu and
W. K. Fuchs Recoverable distributed shared virtual
memory . . . . . . . . . . . . . . . . . 460--469
D. S. Ha and
V. P. Kumar On the design of high-yield
reconfigurable PLA's . . . . . . . . . . 470--479
V. P. Roychowdhury and
J. Bruck and
T. Kailath Efficient algorithms for reconfiguration
in VLSI\slash WSI arrays . . . . . . . . 480--489
S. Dutt and
J. P. Hayes On designing and reconfiguring
$k$-fault-tolerant tree architectures 490--503
J. Arlat and
K. Kanoun and
J.-C. Laprie Dependability modeling and evaluation of
software fault-tolerant systems . . . . 504--513
P. Ramanathan and
D. D. Kandlur and
K. G. Shin Hardware-assisted software clock
synchronization for homogeneous
distributed systems . . . . . . . . . . 514--524
R. K. Iyer and
L. T. Young and
P. V. K. Iyer Automatic recognition of intermittent
failures: an experimental study of field
data . . . . . . . . . . . . . . . . . . 525--537
R. Gupta and
M. A. Breuer The Ballast methodology for structured
partial scan design . . . . . . . . . . 538--544
K.-T. Cheng and
V. D. Agrawal A partial scan method for sequential
circuits with feedback . . . . . . . . . 544--548
Y. Tamir and
M. Tremblay High-performance fault-tolerant VLSI
systems using micro rollback . . . . . . 548--554
N. R. Saxena and
E. J. McCluskey Control-flow checking using watchdog
assists and extended-precision checksums 554--559
M.-F. Chang and
W. Shi and
W. K. Fuchs Optimal diagnosis procedures for
$k$-out-of-$n$ structures . . . . . . . 559--564
M. Chean and
J. A. B. Fortes The full-use-of-suitable-spares (FUSS)
approach to hardware reconfiguration for
fault-tolerant processor arrays . . . . 564--571
M. Balakrishnan and
C. S. Raghavendra On reliability modeling of closed
fault-tolerant computer systems . . . . 571--575
J. H. Barton and
E. W. Czeck and
Z. Z. Segall and
D. P. Siewiorek Fault injection experiments using FIAT 575--582
S. C. Seth and
V. D. Agrawal and
H. Farhat A statistical theory of digital circuit
testability . . . . . . . . . . . . . . 582--586
D. K. Pradhan and
S. K. Gupta and
M. G. Karpovsky Aliasing probability for multiple input
signature analyzer . . . . . . . . . . . 586--591
L. A. Dunning and
G. Dial and
M. R. Varanasi Unidirectional byte error detecting
codes for computer memory systems . . . 592--595
M. Lu and
D. Zhang and
T. Murata Analysis of self-stabilizing clock
synchronization by means of stochastic
Petri nets . . . . . . . . . . . . . . . 597--604
F. P. Preparata and
J. E. Vuillemin Practical cellular dividers . . . . . . 605--614
D. Ghosal and
L. N. Bhuyan Performance evaluation of a dataflow
architecture . . . . . . . . . . . . . . 615--627
T. L. Casavant and
J. G. Kuhl A communicating finite automata approach
to modeling distributed computation and
its application to distributed
decision-making . . . . . . . . . . . . 628--639
Chen-Wen Wu and
P. R. Cappello Easily testable iterative logic arrays 640--652
P. C. Mathias and
L. M. Patnaik Systolic evaluation of polynomial
expressions . . . . . . . . . . . . . . 653--665
B. W. Y. Wei and
C. D. Thompson Area-time optimal adder design . . . . . 666--675
H. F. Li and
D. K. Probst Optimal VLSI dictionary machines without
compress instructions . . . . . . . . . 676--693
Wei-Kuan Shih and
Sun Wu and
Y. S. Kuo Unifying maximum cut and minimum cut of
a planar graph . . . . . . . . . . . . . 694--697
S. Matic Emulation of hypercube architecture on
nearest-neighbor mesh-connected
processing elements . . . . . . . . . . 698--700
D. J. Rosenkrantz Half-hot state assignments for finite
state machines . . . . . . . . . . . . . 700--702
M. H. Abd-El-Barr and
Z. G. Vranesic Cost reduction in the CCD realization of
MVMT functions . . . . . . . . . . . . . 702--706
W. Gale and
S. Das and
C. T. Yu Improvements to an algorithm for
equipartitioning . . . . . . . . . . . . 706--710
S. J. Friedman and
K. J. Supowit Finding the optimal variable ordering
for binary decision diagrams . . . . . . 710--713
R. Beigel and
J. Gill Sorting $n$ objects with a $k$-sorter 714--716
H. Ling An approach to implementing
multiplication with small tables . . . . 717--718
P. Ancilotti and
B. Lazzerini and
C. A. Prete and
M. Sacchi A distributed commit protocol for a
multicomputer system . . . . . . . . . . 718--724
M. D. Ercegovac and
T. Lang Redundant and on-line CORDIC:
application to matrix triangularization
and SVD . . . . . . . . . . . . . . . . 725--740
S.-C. Shyu and
V. O. K. Li Performance Analysis of Static Locking
in Distributed Database Systems . . . . 741--751
S. Kundu and
S. M. Reddy On symmetric error correcting and all
unidirectional error detecting codes . . 752--761
H. Fujiwara Computational complexity of
controllability/observability problems
for combinational circuits . . . . . . . 762--767
M. Sasaki and
T. Inoue and
Y. Shirai and
F. Ueno Fuzzy multiple-input maximum and minimum
circuits in current mode and their
analyses using bounded-difference
equations . . . . . . . . . . . . . . . 768--774
W. J. Dally Performance analysis of $k$-ary $n$-cube
interconnection networks . . . . . . . . 775--785
S. P. Dandamudi and
D. L. Eager Hierarchical interconnection networks
for multicomputer systems . . . . . . . 786--797
A. F. Champernowne and
L. B. Bushard and
J. T. Rusterholz and
J. R. Schomburg Latch-to-latch timing rules . . . . . . 798--808
R. M. Owens and
M. J. Irwin Being stingy with multipliers . . . . . 809--818
J. N. Daigle and
R. B. Kuehl and
J. D. Langford Queueing analysis of an optical disk
jukebox based office system . . . . . . 819--828
A. Youssef and
B. W. Arden Equivalence between functionality and
topology of $\log N$-stage banyan
networks . . . . . . . . . . . . . . . . 829--832
K. R. Pattipati and
S. A. Shah On the computational aspects of
performability models of fault-tolerant
computer systems . . . . . . . . . . . . 832--836
B. L. Montgomery and
B. V. K. V. Kumar Systematic random error correcting and
all unidirectional error detecting codes 836--840
E. de Souza e Silva and
R. R. Muntz A note on the computational cost of the
Linearizer algorithm for queueing
networks . . . . . . . . . . . . . . . . 840--842
J. T. Butler and
K. A. Schueller On the equivalence of cost functions in
the design of circuits by cost-table . . 842--844
X. Nie and
D. A. Plaisted Experimental results on subgoal
reordering . . . . . . . . . . . . . . . 845--848
C.-W. Ho and
R. C. T. Lee A parallel algorithm for solving sparse
triangular systems . . . . . . . . . . . 848--852
F. Bonomi On job assignment for a parallel system
of processor sharing queues . . . . . . 858--869
K. G. Shin and
M.-S. Chen Minimal Order Loop-Free Routing Strategy 870--881
F. Belik An efficient deadlock avoidance
technique . . . . . . . . . . . . . . . 882--888
H. Amano and
T. Boku and
T. Kudoh (SM)$^2$-II: a large-scale
multiprocessor for sparse matrix
calculations . . . . . . . . . . . . . . 889--905
K. Kant Performance analysis of real-time
software supporting fault-tolerant
operation . . . . . . . . . . . . . . . 906--918
Z. Fang and
P. Tang and
P.-C. Yew and
C.-Q. Zhu Dynamic processor self-scheduling for
general parallel nested loops . . . . . 919--929
L. Kleeman The jitter model for metastability and
its application to redundant
synchronizers . . . . . . . . . . . . . 930--942
C.-L. Yang Constructing optimal procedures for
testing series systems . . . . . . . . . 943--945
J. P. Fishburn Clock skew optimization . . . . . . . . 945--951
W.-C. Wong and
T. Suda and
L. Bic Performance analysis of a
message-oriented knowledge-base . . . . 951--957
J.-S. Wang and
R. C. T. Lee An efficient channel routing algorithm
to yield an optimal solution . . . . . . 957--962
S.-T. Huang Notes on shuffle/exchange type
permutation sets . . . . . . . . . . . . 962--965
K. Y. Lee and
H. Yoon The B-network: a multistage
interconnection network with backward
links . . . . . . . . . . . . . . . . . 966--969
N. R. Saxena and
E. J. McCluskey Analysis of Checksums,
Extended-Precision Checksums, and Cyclic
Redundancy Checks . . . . . . . . . . . 969--975
I. H. Onyuksel and
K. B. Irani Markovian queueing network models for
performance analysis of a single-bus
multiprocessor system . . . . . . . . . 975--980
P. K. Chan and
M. D. F. Schlag Analysis and design of CMOS Manchester
adders with variable carry-skip . . . . 983--992
T. M. Carter and
J. E. Robertson The set theory of arithmetic
decomposition . . . . . . . . . . . . . 993--1005
H. Sam and
A. Gupta A generalized multibit recoding of two's
complement binary numbers and its proof
with application in multiplier
implementations . . . . . . . . . . . . 1006--1015
M. D. Ercegovac and
T. Lang Radix-$4$ square root without initial
PLA . . . . . . . . . . . . . . . . . . 1016--1024
R. Hashemian Square Rooting Algorithms for Integer
and Floating-Point Numbers . . . . . . . 1025--1029
I. Koren and
O. Zinaty Evaluating Elementary Functions in a
Numerical Coprocessor Based on Rational
Approximations . . . . . . . . . . . . . 1030--1037
H. X. Lin and
H. J. Sips On-line CORDIC algorithms . . . . . . . 1038--1052
C.-C. Su and
H.-Y. Lo An algorithm for scaling and single
residue error correction in residue
number systems . . . . . . . . . . . . . 1053--1064
N. M. Wigley and
G. A. Jullien On modulus replication for residue
arithmetic computations of complex inner
products . . . . . . . . . . . . . . . . 1065--1076
M. G. Arnold and
T. A. Bailey and
J. R. Cowles and
J. J. Cupal Redundant logarithmic arithmetic . . . . 1077--1086
J. E. Vuillemin Exact real computer arithmetic with
continued fractions . . . . . . . . . . 1087--1105
Peter Kornerup and
David W. Matula An algorithm for redundant binary
bit-pipelined rational arithmetic . . . 1106--1115
I. Lee and
S. B. Davidson A Performance Analysis of Timed
Synchronous Communication Primitives . . 1117--1131
P. Banerjee and
J. T. Rahmeh and
C. Stunkel and
V. S. Nair and
K. Roy and
V. Balasubramanian and
J. A. Abraham Algorithm-based fault tolerance on a
hypercube multiprocessor . . . . . . . . 1132--1145
M.-S. Chen and
K. G. Shin Subcube allocation and task migration in
hypercube multiprocessors . . . . . . . 1146--1155
J.-Y. Chung and
J. W. S. Liu and
K.-J. Lin Scheduling periodic jobs that allow
imprecise results . . . . . . . . . . . 1156--1174
L. Sha and
R. Rajkumar and
J. P. Lehoczky Priority inheritance protocols: an
approach to real-time synchronization 1175--1185
W. Zhao and
J. A. Stankovic and
K. Ramamritham A window protocol for transmission of
time-constrained messages . . . . . . . 1186--1203
M. D. Ercegovac and
T. Lang Simple radix-$4$ division with operands
scaling . . . . . . . . . . . . . . . . 1204--1208
S. Pramanik and
M. Kim Parallel processing of large node
B-trees . . . . . . . . . . . . . . . . 1208--1212
J.-R. Sack and
S. Suri An optimal algorithm for detecting weak
visibility of a polygon . . . . . . . . 1213--1219
L. Ciminiera and
P. Montuschi Higher radix square rooting . . . . . . 1220--1231
F. Bonomi and
A. Kumar Adaptive optimal load balancing in a
nonhomogeneous multiserver system with a
central job scheduler . . . . . . . . . 1232--1250
G. Ciardo and
R. A. Marie and
B. Sericola and
K. S. Trivedi Performability analysis using
semi-Markov reward processes . . . . . . 1251--1264
S. W. Hornick and
S. R. Maddila and
E. P. Mucke and
H. Rosenberger and
S. S. Skiena and
I. G. Tollis Searching on a tape . . . . . . . . . . 1265--1272
P. D. Hortensius and
R. D. McLeod and
H. C. Card Cellular automata-based signature
analysis for built-in self-test . . . . 1273--1283
R. David and
K. Wagner Analysis of detection probability and
some applications . . . . . . . . . . . 1284--1291
A. Bobbio and
K. Trivedi Computing cumulative measures of stiff
Markov chains using aggregation . . . . 1291--1298
Joo-Kang Lee and
J. T. Butler A characterization of
$t/s$-diagnosability and sequential
$t$-diagnosability in designs . . . . . 1298--1304
A. L. N. Reddy and
P. Banerjee Algorithm-based fault detection for
signal processing applications . . . . . 1304--1308
E. de Souza e Silva and
H. R. Gail Analyzing scheduled maintenance policies
for repairable computer systems . . . . 1309--1324
D. M. Lewis An architecture for addition and
subtraction of long word length numbers
in the logarithmic number system . . . . 1325--1336
D. M. Nicol and
J. H. Saltz An analysis of scatter decomposition . . 1337--1345
J. Kilian and
S. Kipnis and
C. E. Leiserson The organization of permutation
architectures with bused
interconnections . . . . . . . . . . . . 1346--1358
C. Chakrabarti and
J. Jaja Systolic architectures for the
computation of the discrete Hartley and
the discrete cosine transforms based on
prime factor decomposition . . . . . . . 1359--1368
S. Chakravarty and
H. B. Hunt III On computing signal probability and
detection probability of stuck-at faults 1369--1377
A. Chatterjee and
J. A. Abraham The testability of generalized counters
under multiple faulty cells . . . . . . 1378--1385
M. D. Ercegovac and
T. Lang Fast multiplication without
carry-propagate addition . . . . . . . . 1385--1390
B. C. Kuszmaul Fast, deterministic routing, on
hypercubes, using small buffers . . . . 1390--1393
A. J. Martin and
J. L. A. van de Snepscheut An interconnection network for
distributed recursive computations . . . 1393--1395
M. Sarrafzadeh Area minimization in a three-sided
switchbox by sliding the modules . . . . 1395--1398
B. Bose Group theoretic signature analysis . . . 1398--1403
J. W. Schwartz and
J. K. Wolf A systematic $(12, 8)$ code for
correcting single errors and detecting
adjacent errors . . . . . . . . . . . . 1403--1404
M.-S. Chen and
K. G. Shin Adaptive fault-tolerant routing in
hypercube multicomputers . . . . . . . . 1406--1416
C. J. Zarowski and
H. C. Card On addition and multiplication with
Hensel codes . . . . . . . . . . . . . . 1417--1423
T. M. Carter and
J. E. Robertson Radix-$16$ signed-digit division . . . . 1424--1433
B. S. Fagin and
A. M. Despain The performance of parallel Prolog
programs . . . . . . . . . . . . . . . . 1435--1445
R. G. Melhem and
G.-Y. Hwang Embedding rectangular grids into square
grids with dilation two . . . . . . . . 1446--1455
K.-T. Cheng and
V. D. Agrawal and
E. S. Kuh A simulation-based method for generating
tests for sequential circuits . . . . . 1456--1463
K. Sapiecha and
R. Jarocki Modular architecture for high
performance implementation of the FRR
algorithm . . . . . . . . . . . . . . . 1464--1468
C.-B. Yang and
R. C. T. Lee and
W.-T. Chen Parallel graph algorithms based upon
broadcast communications . . . . . . . . 1468--1472
A. K. Somani Sequential fault occurrence and
reconfiguration in system level
diagnosis . . . . . . . . . . . . . . . 1472--1475
S. D. Kugelmass and
K. Steighlitz An upper bound on expected clock skew in
synchronous systems . . . . . . . . . . 1475--1477
F. Lombardi and
W. Huang Fault detection and design complexity in
C-testable VLSI arrays . . . . . . . . . 1477--1481
N. N. Biswas and
S. Srinivas A reconfigurable tree architecture with
multistage interconnection network . . . 1481--1485
W. Nuang and
F. Lombardi On the constant diagnosability of
baseline interconnection networks . . . 1485--1489
D. H. Linder and
J. C. Harden An adaptive and fault tolerant wormhole
routing strategy for $k$-ary $n$-cubes 2--12
X. Hu and
R. G. Harber and
S. C. Bass Expanding the Range of Convergence of
the CORDIC Algorithm . . . . . . . . . . 13--21
S. W. Ng Improving disk performance via latency
reduction . . . . . . . . . . . . . . . 22--30
B. Perunicic and
S. Lakhani and
V. Milutinovic Stochastic modeling and analysis of
propagation delays in GaAs adders . . . 31--45
J. A. Ellis Embedding rectangular grids into square
grids . . . . . . . . . . . . . . . . . 46--52
S. J. Hong and
S. Muroga Absolute minimization of completely
specified switching functions . . . . . 53--65
G. M. Silberman and
I. Spillinger Functional fault simulation as a guide
for biased-random test pattern
generation . . . . . . . . . . . . . . . 66--79
G. M. Silberman and
I. Spillinger RIDDLE: a foundation for test generation
on a high-level design description . . . 80--87
A.-H. Esfahanian and
L. M. Ni and
B. E. Sagan The twisted $N$-cube with application to
multiprocessing . . . . . . . . . . . . 88--93
A. Sengupta and
P. D. Joshi and
S. Bandyopadhyay A synthesis approach to design optimally
fault tolerant network architecture . . 94--100
P. S. Lewis and
S.-Y. Kung An optimal systolic array for the
algebraic path problem . . . . . . . . . 100--105
H. M. Alnuweiri and
V. K. Prasanna Kumar Optimal VLSI sorting with reduced number
of processors . . . . . . . . . . . . . 105--110
D. J. Haglin and
S. M. Venkatesan Approximation and intractability results
for the maximum cut problem and its
variants . . . . . . . . . . . . . . . . 110--113
Jyh-Jong Fu and
R. C. T. Lee Minimum spanning trees of moving points
in the plane . . . . . . . . . . . . . . 113--118
B. Codenotti and
R. Tamassia A network flow approach to the
reconfiguration of VLSI arrays . . . . . 118--121
M. R. Samatham and
D. K. Pradhan Correction to ``The De Bruijn
multiprocessor network: a versatile
parallel processing and sorting network
for VLSI'' . . . . . . . . . . . . . . . 122--122
S. Saxena and
P. C. P. Bhatt and
V. C. Prasad Correction to ``Parallel algorithm for
Delaunay triangulation on orthogonal
tree network in two and three
dimensions'' . . . . . . . . . . . . . . 122--122
B. Bose On unordered codes . . . . . . . . . . . 125--131
D. Nikolos Theory and design of $t$-error
correcting/$d$-error detecting ($d > t$)
and all unidirectional error detecting
codes . . . . . . . . . . . . . . . . . 132--142
V. Raghavan and
A. R. Tripathi Improved diagnosability algorithms . . . 143--153
R. W. Haddad and
A. T. Dahbura and
A. B. Sharma Increased throughput for the testing and
repair of RAMs with redundancy . . . . . 154--166
P. P. Tirumalai and
J. T. Butler Minimization algorithms for
multiple-valued programmable logic
arrays . . . . . . . . . . . . . . . . . 167--177
K. K. Parhi and
D. G. Messerschmitt Static rate-optimal scheduling of
iterative data-flow programs via optimum
unfolding . . . . . . . . . . . . . . . 178--195
A. Bar-Noy and
D. Peleg Square meshes are not always optimal . . 196--204
R. E. Bryant On the complexity of VLSI
implementations and graph
representations of Boolean functions
with application to integer
multiplication . . . . . . . . . . . . . 205--213
H. J. Sips and
H. Lin An improved vector-reduction method . . 214--217
A. Y. Oruc and
M. Mittal Setup algorithms for cube-connected
parallel computers using recursive
Karnaugh maps . . . . . . . . . . . . . 217--221
A. G. Ferreira A parallel time/hardware tradeoff $T.H =
O(2^{n/2})$ for the knapsack problem . . 221--225
A. Ghafoor and
T. R. Bashkow A study of odd graphs as fault-tolerant
interconnection networks . . . . . . . . 225--232
A. Kavianpour and
K. H. Kim Diagnosabilities of hypercubes under the
pessimistic one-step diagnosis strategy 232--237
E. Pearse O'Grady and
Baek-Kyu K. Young A Hardware-Oriented Algorithm for
Floating-Point Function Generation . . . 237--241
Dug-Kyoo Choi and
B. G. Kim The expected (not worst-case) throughput
of the Ethernet protocol . . . . . . . . 245--252
B. W. Meister A performance study of the ISO transport
protocol . . . . . . . . . . . . . . . . 253--262
H. Lam and
C. Lee and
S. Y. W. Su A special function unit for database
operations (SFU--DB): design and
performance evaluation . . . . . . . . . 263--275
D. T. Harper III and
D. A. Linebarger Conflict-free vector access using a
dynamic storage scheme . . . . . . . . . 276--283
N.-F. Tzeng and
S. Wei Enhanced hypercubes . . . . . . . . . . 284--294
D. M. Nicol and
D. R. O'Hallaron Improved algorithms for mapping
pipelined and parallel computations . . 295--306
G. Vijayan Generalization of min-cut partitioning
to tree structures and its applications 307--314
O. J. Murphy and
R. L. McCraw Designing storage efficient decision
trees . . . . . . . . . . . . . . . . . 315--320
K. D. Heidtmann Arithmetic spectrum applied to fault
detection for combinational networks . . 320--324
S. W. Bollinger and
S. F. Midkiff Heuristic technique for processor and
link assignment in multicomputers . . . 325--333
R. P. Brent and
Z. B. Bing A stabilized parallel algorithm for
direct-form recursive filters . . . . . 333--336
Y.-H. Lee and
C. M. Krishna Optimal scheduling of signature analysis
for VLSI testing . . . . . . . . . . . . 336--341
S. Dutt and
J. P. Hayes Subcube allocation in hypercube
computers . . . . . . . . . . . . . . . 341--352
Q. Yang and
L. N. Bhuyan Analysis of packet-switched multiple-bus
multiprocessor systems . . . . . . . . . 352--357
J. R. Burke and
C. Chen and
T.-Y. Lee and
D. P. Agrawal Performance analysis of single stage
interconnection networks . . . . . . . . 357--365
Y. C. Liu and
H. G. Perros A decomposition procedure for the
analysis of a closed fork/join queueing
system . . . . . . . . . . . . . . . . . 365--370
H.-A. Lin Constructing protocols with alternative
functions . . . . . . . . . . . . . . . 376--386
P. W. King Formalization of protocol engineering
concepts . . . . . . . . . . . . . . . . 387--403
P. Jain and
S. S. Lam Specification of real-time broadcast
networks . . . . . . . . . . . . . . . . 404--422
S. C. Chamberlain and
P. D. Amer Broadcast channels in Estelle . . . . . 423--436
R. Sisto and
L. Ciminiera and
A. Valenzano A protocol for multirendezvous of LOTOS
processes . . . . . . . . . . . . . . . 437--447
M. G. Gouda and
N. J. Multari Stabilizing communication protocols . . 448--458
Y. Kakuda and
H. Saito An integrated approach to design of
protocol specifications using protocol
validation and synthesis . . . . . . . . 459--467
R. L. Probert and
K. Saleh Synthesis of communication protocols:
survey and assessment . . . . . . . . . 468--476
N. Shiratori and
Y.-X. Zhang and
K. Takahashi and
S. Noguchi A user friendly software environment for
protocol synthesis . . . . . . . . . . . 477--486
M. Rajagopal and
R. E. Miller Synthesizing a protocol converter from
executable protocol traces . . . . . . . 487--499
E. Heck and
D. Hogrefe and
B. Muller-Clostermann Hierarchical performance evaluation
based on formally specified
communication protocols . . . . . . . . 500--513
K. Katsuyama and
F. Sato and
T. Nakakawaji and
T. Mizuno Strategic testing environment with
formal description techniques . . . . . 514--525
D. Y. Lee and
J. Y. Lee A well-defined Estelle specification for
the automatic test generation . . . . . 526--542
P. Tripathy and
B. Sarikaya Test generation from LOTOS
specifications . . . . . . . . . . . . . 543--552
H. Ichikawa and
M. Itoh and
J. Kato and
A. Takura and
M. Shibasaki SDE: incremental specification and
development of communications software 553--561
E. J. Cameron and
D. M. Cohen and
T. M. Guinther and
W. M. Keese, Jr. and
L. A. Ness and
C. Norman and
H. N. Srinidhi The L.0 language and environment for
protocol simulation and prototyping . . 562--571
S. B. Davidson and
I. Lee and
V. Wolfe Timed atomic commitment . . . . . . . . 573--583
V. Raghavan and
A. Tripathi Sequential diagnosability is co-NP
complete . . . . . . . . . . . . . . . . 584--595
X. Guan and
M. S. Langston Time-space optimal parallel merging and
sorting . . . . . . . . . . . . . . . . 596--602
J. H. Saltz and
R. Mirchandaney and
K. Crowley Run-time parallelization and scheduling
of loops . . . . . . . . . . . . . . . . 603--612
B. Qin and
H. A. Sholl and
R. A. Ammar Micro time cost analysis of parallel
computations . . . . . . . . . . . . . . 613--628
D. R. Smith and
J. C. Lin The tree-match chip . . . . . . . . . . 629--639
M. Dubois and
J.-C. Wang Shared block contention in a cache
coherence protocol . . . . . . . . . . . 640--644
T. Sasao Bounds on the average number of products
in the minimum sum-of-products
expressions for multiple-value input
two-valued output functions . . . . . . 645--651
J. J. Metzner Efficient replicated remote file
comparison . . . . . . . . . . . . . . . 651--660
D. L. Tao and
C. R. P. Harmann and
P. K. Lala A note on t-EC/d-UED codes . . . . . . . 660--663
Z. Tong and
R. Y. Kain Vote assignments in weighted voting
mechanisms . . . . . . . . . . . . . . . 664--667
G. I. Chen and
Y. H. Lai and
Y.-N. Lien A note on ``Generalized hypercube and
hyperbus structures for a computer
network'' by L. N. Bhuyan and D. P.
Agrawal . . . . . . . . . . . . . . . . 667--668
J. W. Dolter and
P. Ramanathan and
K. G. Shin Performance analysis of virtual
cut-through switching in HARTS: a
hexagonal mesh multicomputer . . . . . . 669--680
A. K. Uht A theory of reduced and minimal
procedural dependencies . . . . . . . . 681--692
B. L. Menezes and
R. Jenevein The KYKLOS multicomputer network:
interconnection strategies, properties,
and applications . . . . . . . . . . . . 693--705
Yu Chin Hsu and
Youn Long Lin and
Hang Ching Hsieh and
Ting Hai Chao Combining logic minimization and folding
for PLAs . . . . . . . . . . . . . . . . 706--713
T.-H. Lai and
A. P. Sprague Placement of the processors of a
hypercube . . . . . . . . . . . . . . . 714--722
W. Shang and
J. A. B. Fortes Time optimal linear schedules for
algorithms with uniform dependencies . . 723--742
D. K. Pradhan and
S. K. Gupta A new framework for designing and
analyzing BIST techniques and zero
aliasing compression . . . . . . . . . . 743--763
O. H. Ibarra and
T.-C. Pong and
S. M. Sohn Parallel recognition and parsing on the
hypercube . . . . . . . . . . . . . . . 764--770
V. K. P. Kumar and
Y.-C. Tsai On synthesizing optimal family of linear
systolic arrays for matrix
multiplication . . . . . . . . . . . . . 770--774
C. K. Cheng and
S. Z. Yao and
T. C. Hu The orientation of modules based on
graph decomposition . . . . . . . . . . 774--780
T. C. Choinski and
T. T. Tylaska Generation of digit reversed address
sequences for fast Fourier transforms 780--784
R. Z. Makki and
S. Bou-Ghazale and
C. Tianshang Automatic test pattern generation with
branch testing . . . . . . . . . . . . . 785--791
L. Sha and
R. Rajkumar and
S. H. Son and
C.-H. Chang A real-time locking protocol . . . . . . 793--800
M. Y. Kim and
A. N. Tantawi Asynchronous disk interleaving:
approximating access delays . . . . . . 801--810
G. J. Milne The formal description and verification
of hardware timing . . . . . . . . . . . 811--826
M. M. Eshaghian Parallel algorithms for image processing
on OMC . . . . . . . . . . . . . . . . . 827--833
Wen Tsuen Chen and
Jang-Pin Sheu Performance analysis of multiple bus
interconnection networks with
hierarchical requesting model . . . . . 834--842
M. H. Nodine and
D. P. Lopresti and
J. S. Vitter I/O overhead and parallel VLSI
architectures for lattice computations 843--852
A. K. Gupta and
S. E. Hambrusch Embedding complete binary trees into
butterfly networks . . . . . . . . . . . 853--863
P. R. Bhattacharjee and
S. K. Basu and
J. C. Paul Translation of the problem of complete
test set generation to pseudo-Boolean
programming . . . . . . . . . . . . . . 864--867
J. P. Robinson Aliasing probabilities for feedback
signature compression of test data . . . 867--873
G. Alia and
E. Martinelli A VLSI modulo $m$ multiplier . . . . . . 873--878
W. Daehn Load balancing in a hybrid ATPG
environment . . . . . . . . . . . . . . 878--882
A. D. Singh and
H. Y. Youn A modular fault-tolerant binary tree
architecture with short links . . . . . 882--890
S. J. Eggers Simplicity versus accuracy in a model of
cache coherency overhead . . . . . . . . 893--906
C. Faloutsos and
D. Metaxas Disk allocation methods using error
correcting codes . . . . . . . . . . . . 907--914
L. Wang and
C.-L. Wu Distributed instruction set computer
architecture . . . . . . . . . . . . . . 915--934
A. Mourad and
B. Ozden and
M. Malek Comprehensive testing of multistage
interconnection networks . . . . . . . . 935--951
F.-S. Lai and
C.-F. E. Wu A hybrid number system processor with
geometric and complex arithmetic
capabilities . . . . . . . . . . . . . . 952--962
A. G. Greenberg and
P. E. Wright Design and analysis of master/slave
multiprocessors . . . . . . . . . . . . 963--976
M. H. Abd-El-Barr and
Z. G. Vranesic and
S. G. Zaky Algorithmic synthesis of MVL functions
for CCD implementation . . . . . . . . . 977--986
K. Sakaniwa and
T. N. Ahn and
T. R. N. Rao A note on $t$-unidirectional error
correcting and $d$ $(d \leq
t)$-unidirectional error detecting
($t$-UEC and $d$-UED) codes . . . . . . 987--988
N. Takagi and
T. Asada and
S. Yajima Redundant CORDIC Methods with a Constant
Scale Factor for Sine and Cosine
Computation . . . . . . . . . . . . . . 989--995
A. Kumar Hierarchical quorum consensus: a new
algorithm for managing replicated data 996--1004
Y. Yang and
G. M. Masson Nonblocking broadcast switching networks 1005--1015
W. J. Dally Express cubes: improving the performance
of $k$-ary $n$-cube interconnection
networks . . . . . . . . . . . . . . . . 1016--1023
I. Koren and
Z. Koren Discrete and continuous models for the
performance of reconfigurable multistage
systems . . . . . . . . . . . . . . . . 1024--1033
M. Damiani and
P. Olivo and
B. Ricco Analysis and design of linear finite
state machines for signature analysis
testing . . . . . . . . . . . . . . . . 1034--1045
J.-Y. Juang and
B. W. Wah A contention-based bus-control scheme
for multiprocessor systems . . . . . . . 1046--1053
C. Chakrabarti and
J. JaJa VLSI architectures for multidimensional
transforms . . . . . . . . . . . . . . . 1053--1057
C. S. Raghavendra and
R. V. Boppana On self-routing in Benes and
shuffle-exchange networks . . . . . . . 1057--1064
N. Yoshida and
E. Goto and
S. Ichikawa Pseudorandom Rounding for Truncated
Multipliers . . . . . . . . . . . . . . 1065--1067
P. Caspi and
J. Piotrowski and
R. Velazco An a priori approach to the evaluation
of signature analysis efficiency . . . . 1068--1071
Kar-Lik Wong and
Wan-Chi Siu Data routing networks for
systolic/pipeline realization of prime
factor mapping . . . . . . . . . . . . . 1072--1074
Y. Min and
Y. K. Malaiya and
B. Jin Analysis of detection capability of
parallel signature analyzers . . . . . . 1075--1081
K. B. Lakshmanan and
B. Ravikumar and
K. Ganesan Coping with erroneous information while
sorting . . . . . . . . . . . . . . . . 1081--1084
S. M. Kim and
R. McNaughton and
R. McCloskey A polynomial time algorithm for the
local testability problem of
deterministic finite automata . . . . . 1087--1093
M. J. Irwin and
R. M. Owens A two-dimensional, distributed logic
architecture . . . . . . . . . . . . . . 1094--1101
C. U. Martel and
W.-H. L. M. Moh Optimal prioritized conflict resolution
on a multiple access channel . . . . . . 1102--1108
R. Beivide and
E. Herrada and
J. L. Balcazar and
A. Arruabarrena Optimal distance networks of low degree
for parallel computers . . . . . . . . . 1109--1124
D. C. McCrackin Eliminating interlocks in deeply
pipelined processors by delay enforced
multistreaming . . . . . . . . . . . . . 1125--1132
A. Chatterjee and
J. A. Abraham Test generation for iterative logic
arrays based on an $N$-cube of cell
states model . . . . . . . . . . . . . . 1133--1148
Y. Han An optimal linked list prefix algorithm
on a local memory computer . . . . . . . 1149--1153
J.-C. Liu and
K. G. Shin A RAM architecture for concurrent access
and on chip testing . . . . . . . . . . 1153--1159
P. K. Dubey and
M. J. Flynn Branch strategies: Modeling and
optimization [pipeline processing] . . . 1159--1167
M. A. Sridhar and
C. S. Raghavendra Fault-tolerant networks based on the de
Bruijn graph . . . . . . . . . . . . . . 1167--1174
J. Koh and
D. Tcha Information dissemination in trees with
nonuniform edge transmission times . . . 1174--1177
J. Savir and
W. H. McAnney and
S. R. Vecchio Testing for coupled cells in
random-access memories . . . . . . . . . 1177--1180
S. Vassiliadis and
E. M. Schwarz and
B. M. Sung Hard-wired multipliers with encoded
partial products . . . . . . . . . . . . 1181--1197
I. Pomeranz and
Z. Kohavi Polynomial complexity algorithms for
increasing the testability of digital
circuits by testing-module insertion . . 1198--1213
V. M. Milutinovic and
D. A. Fura and
W. A. Helbig Pipeline design tradeoffs in a 32-bit
gallium arsenide microprocessor . . . . 1214--1224
S. Ha and
E. A. Lee Compile-time scheduling and assignment
of data-flow program graphs with
data-dependent iteration . . . . . . . . 1225--1238
S. M. R. Islam and
H. H. Ammar Performability analysis of distributed
real-time systems . . . . . . . . . . . 1239--1251
S. Y. H. Su and
M. Cutler and
M. Wang Self-diagnosis of failures in VLSI tree
array processors . . . . . . . . . . . . 1252--1257
B. L. Montgomery Efficient unidirectional error codes for
block memories . . . . . . . . . . . . . 1257--1259
M. Dubois and
F. A. Briggs The run-time efficiency of parallel
asynchronous algorithms . . . . . . . . 1260--1266
D. K. Kostopoulos An Algorithm for the Computation of
Binary Logarithms . . . . . . . . . . . 1267--1270
A. Pelc Undirected graph models for system-level
fault diagnosis . . . . . . . . . . . . 1271--1276
K. Y. Lee and
H. Yoon Indirect star-type networks for large
multiprocessor systems . . . . . . . . . 1277--1282
W. E. Kozlowski and
H. Krawczyk A comparison-based approach to
multicomputer system diagnosis in hybrid
fault situations . . . . . . . . . . . . 1283--1287
D. C. McCrackin and
B. Szabados Using horizontal prefetching to
circumvent the jump problem . . . . . . 1287--1291
Shing-Tsaan Huang and
S. K. Tripathi and
Nian-Shing Chen and
Yu-Chee Tseng An efficient routing algorithm for
realizing linear permutations on
$p^t$-shuffle-exchange networks . . . . 1292--1298
S. Purwar An efficient method of computing
generalized Reed--Muller expansions from
binary decision diagram . . . . . . . . 1298--1301
L. Donatiello and
V. Grassi On evaluating the cumulative performance
distribution of fault-tolerant computer
systems . . . . . . . . . . . . . . . . 1301--1307
M. Sarrafzadeh and
D. T. Lee Topological via minimization revisited 1307--1312
K. Efe A variation on the hypercube with lower
diameter . . . . . . . . . . . . . . . . 1312--1316
C.-T. Lin and
C. S. G. Lee Neural-network-based fuzzy logic control
and decision system . . . . . . . . . . 1320--1336
L.-X. Wang and
J. M. Mendel Three-dimensional structured networks
for matrix equation solving . . . . . . 1337--1346
G. A. Tagliarini and
J. F. Christ and
E. W. Page Optimization using neural networks . . . 1347--1358
D. Suter Constraint networks in vision . . . . . 1359--1367
S. T. Toborg and
K. Hwang Cooperative vision integration through
data-parallel neural computations . . . 1368--1379
L. M. Reyneri and
E. Filippi An analysis on the performance of
silicon implementations of
backpropagation algorithms for
artificial neural networks . . . . . . . 1380--1389
W.-M. Lin and
V. K. Prasanna and
K. W. Przytula Algorithmic mapping of neural network
models onto parallel SIMD machines . . . 1390--1401
K. Y. Siu and
V. P. Roychowdhury and
T. Kailath Depth-size tradeoffs for neural
computation . . . . . . . . . . . . . . 1402--1412
V. Zissimopoulos and
V. T. Paschos and
F. Pekergin On the approximation of NP-complete
problems by using the Boltzmann machine
method: the cases of some covering and
packing problems . . . . . . . . . . . . 1413--1418
G. J. Salem and
T. Y. Young A neural network approach to the
labeling of line drawings . . . . . . . 1419--1424
L. A. Belfore II and
B. W. Johnson The analysis of the faulty behavior of
synchronous neural networks . . . . . . 1424--1429
V. Cherkassky and
K. Fassett and
N. Vassilas Linear algebra approach to neural
associative memories and noise
performance of neural classifiers . . . 1429--1435
I. David and
R. Ginosar and
M. Yoeli An efficient implementation of Boolean
functions as self-timed circuits . . . . 2--11
I. David and
R. Ginosar and
M. Yoeli Implementing sequential machines as
self-timed circuits . . . . . . . . . . 12--17
Chuan-Lin Wu and
Manjai Lee Performance analysis of multistage
interconnection network configurations
and operations . . . . . . . . . . . . . 18--27
Y. Yamamoto and
M. Mukaidono $P$-functions --- ternary logic
functions capable of correcting input
failures and suitable for treating
ambiguities . . . . . . . . . . . . . . 28--35
A. Goyal and
P. Shahabuddin and
P. Heidelberger and
V. F. Nicola and
P. W. Glynn A unified framework for simulating
Markovian models of highly dependable
systems . . . . . . . . . . . . . . . . 36--51
J. Y. Sayah and
C. R. Kime Test scheduling in high performance VLSI
system implementations . . . . . . . . . 52--67
R. M. Fujimoto and
J.-J. Tsai and
G. C. Gopalakrishnan Design and evaluation of the rollback
chip: special purpose hardware for Time
Warp . . . . . . . . . . . . . . . . . . 68--82
K. P. Belkhale and
P. Banerjee Reconfiguration strategies for VLSI
processor arrays and trees using a
modified Diogenes approach . . . . . . . 83--96
P. J. Varman and
K. Doshi Sorting with linear speedup on a
pipelined hypercube . . . . . . . . . . 97--103
Yirng-An Chen and
Youn-Long Lin and
Long-Wen Chang A systolic algorithm for the $k$-nearest
neighbors problem . . . . . . . . . . . 103--108
B. Arazi A circular binary search . . . . . . . . 109--112
O. H. Ibarra and
T. Jiang and
H. Wang String editing on a one-way linear array
of finite-state machines . . . . . . . . 112--118
G.-I. Chen and
T.-H. Lai Constructing parallel paths between two
subcubes . . . . . . . . . . . . . . . . 118--123
A. Boneh and
J. Savir Statistical resistance to detection
[digital circuits testing] . . . . . . . 123--126
A. J. McAuley Four state asynchronous architectures 129--142
A. Varma and
S. Chalasani Fault-tolerance analysis of one-sided
crosspoint switching networks . . . . . 143--158
Yiwan Wong and
J.-M. Delosme Optimization of computation time for
systolic arrays . . . . . . . . . . . . 159--177
K. A. Schueller and
J. T. Butler On the design of cost-tables for
realizing multiple-valued circuits . . . 178--189
W. Shang and
J. A. B. Fortes Independent partitioning of algorithms
with uniform dependencies . . . . . . . 190--206
R. Bubenik and
W. Zwaenepoel Optimistic make [software design] . . . 207--217
L. Campbell and
G. E. Carlsson and
M. J. Dinneen and
V. Faber and
M. R. Fellows and
M. A. Langston and
J. W. Moore and
A. P. Mullhaupt and
H. B. Sexton Small diameter symmetric networks from
linear groups . . . . . . . . . . . . . 218--220
Sy-Yen Kuo and
W. K. Fuchs Fault diagnosis and spare allocation for
yield enhancement in large
reconfigurable PLAs . . . . . . . . . . 221--226
D. T. Harper III Increased memory performance during
vector accesses through the use of
linear address transformations . . . . . 227--230
R. G. Melhem Bi-level reconfigurations of fault
tolerant arrays . . . . . . . . . . . . 231--239
S. P. Dandamudi and
D. L. Eager Hot-spot contention in binary hypercube
networks . . . . . . . . . . . . . . . . 239--244
F. Z. Koksal and
M. D. Yucel Comments on the decoding algorithms of
DBEC--TBED Reed--Solomon codes . . . . . 244--247
W. J. Dally A fast translation method for paging on
top of segmentation . . . . . . . . . . 247--250
J. Savir and
W. H. McAnney A multiple seed linear feedback shift
register . . . . . . . . . . . . . . . . 250--252
C. L. Chen Symbol error-correcting codes for
computer memory systems . . . . . . . . 252--256
N. S. Bowen and
C. N. Nikolaou and
A. Ghafoor On the assignment problem of arbitrary
process systems to heterogeneous
distributed computer systems . . . . . . 257--273
D. Rau and
J. A. B. Fortes and
H. J. Siegel Destination tag routing techniques based
on a state model for the IADM network 274--285
X.-H. Sun and
H. Zhang and
L. M. Ni Efficient tridiagonal solvers on
multicomputers . . . . . . . . . . . . . 286--296
M.-C. Chiang and
G. S. Sohi Evaluating design choices for shared bus
multiprocessors in a throughput-oriented
environment . . . . . . . . . . . . . . 297--317
D. M. Blough and
A. Pelc Complexity of fault diagnosis in
comparison models . . . . . . . . . . . 318--324
K. N. Oikonomou Abstractions of finite-state machines
and immediately-detectable output faults 325--338
P. R. Cappello and
W. L. Miranker Systolic super summation with reduced
hardware . . . . . . . . . . . . . . . . 339--342
P. K. Lui and
J. C. Muzio Boolean matrix transforms for the
minimization of modulo-$2$ canonical
expansions . . . . . . . . . . . . . . . 342--347
B. Wilkinson Comments on ``Design and analysis of
arbitration protocols'' by F. El Guibaly 348--351
Chein-Wei Jen and
Ding-Ming Kwai Data flow representation of iterative
algorithms for systolic arrays . . . . . 351--355
Jong-Chuang Tsay and
Sy Yuan Some combinatorial aspects of parallel
algorithm design for matrix
multiplication . . . . . . . . . . . . . 355--361
H. Jiang and
K. C. Smith PPMB: a partial-multiple-bus
multiprocessor architecture with
improved cost-effectiveness . . . . . . 361--366
T.-C. Tuan On optimal single jog river routing
[VLSI layout] . . . . . . . . . . . . . 366--369
M. Sarrafzadeh and
C. K. Wong Bottleneck Steiner trees in the plane 370--374
K.-T. Cheng and
V. D. Agrawal Initializability consideration in
sequential machine synthesis . . . . . . 374--379
M. Atiquzzaman and
W. K. Shehadah A microprocessor-based office image
processing system --- an extension of
work . . . . . . . . . . . . . . . . . . 379--381
Chonggun Kim and
H. Kameda An algorithm for optimal static load
balancing in distributed computer
systems . . . . . . . . . . . . . . . . 381--384
D. Thiebaut and
J. L. Wolf and
H. S. Stone Synthetic traces for trace-driven
simulation of cache memories . . . . . . 388--410
D. Nikolos and
A. Krokos Theory and design of $t$-error
correcting, $k$-error detecting and
$d$-unidirectional error detecting codes
with $d > k > t$ . . . . . . . . . . . . . 411--419
Y. Huang and
P. Jalote Effect of fault tolerance on response
time-analysis of the primary site
approach . . . . . . . . . . . . . . . . 420--428
A. E. Barbour Solutions to the minimization problem of
fault-tolerant logic circuits . . . . . 429--443
J. W. Davidson and
J. R. Rabung and
D. B. Whalley Relating static and dynamic machine code
measurements . . . . . . . . . . . . . . 444--454
W. P. Groenendijk and
H. Levy Performance analysis of transaction
driven computer systems via queueing
analysis of polling models . . . . . . . 455--466
P.-J. Chuang and
N.-F. Tzeng A fast recognition-complete processor
allocation strategy for hypercube
computers . . . . . . . . . . . . . . . 467--479
C. Knessl and
C. Tier Asymptotic expansions for large closed
queueing networks with multiple job
classes . . . . . . . . . . . . . . . . 480--488
S. Kundu Basis sets for synthesis of switching
functions . . . . . . . . . . . . . . . 489--493
Y. Perl and
L. Gabriel Arithmetic interpolation search for
alphabet tables . . . . . . . . . . . . 493--499
D.-L. Lee Architecture of an array processor using
a nonlinear skewing scheme . . . . . . . 499--505
C. J. Mitchell Authenticating multicast Internet
electronic mail messages using a
bidirectional MAC is insecure . . . . . 505--507
D. Sarkar and
A. Mukherjee Design of optimal systolic algorithms
for the transitive closure problem . . . 508--512
N. S. Bowen and
D. K. Pradhan Virtual checkpoints: architecture and
performance . . . . . . . . . . . . . . 516--525
E. N. Elnozahy and
W. Zwaenepoel Manetho: transparent roll back-recovery
with low overhead, limited rollback, and
fast output commit . . . . . . . . . . . 526--531
V. S. S. Nair and
Y. V. Hoskote and
J. A. Abraham Probabilistic evaluation of online
checks in fault-tolerant multiprocessor
systems . . . . . . . . . . . . . . . . 532--541
S. K. Shrivastava and
P. D. Ezhilchelvan and
N. A. Speirs and
S. Tao and
A. Tully Principal features of the VOLTAN family
of reliable node architectures for
distributed systems . . . . . . . . . . 542--549
R. Geist and
A. J. Offutt and
F. C. Harris, Jr. Estimation and enhancement of real-time
software reliability through mutation
analysis . . . . . . . . . . . . . . . . 550--558
E. W. Czeck and
D. P. Siewiorek Observations on the effects of fault
manifestation as a function of workload 559--566
D. Tang and
R. K. Iyer Analysis and modeling of correlated
failures in multicomputer systems . . . 567--577
F. T. Leighton and
B. M. Maggs Fast algorithms for routing around
faults in multibutterflies and
randomly-wired splitter networks . . . . 578--587
S. Dutt and
J. P. Hayes Some practical issues in the design of
fault-tolerant multiprocessors . . . . . 588--598
J. Bruck and
R. Cypher and
D. Soroker Tolerating faults in hypercubes using
subcube partitioning . . . . . . . . . . 599--605
S. Rangarajan and
D. Fussell Diagnosing arbitrarily connected
parallel computers with high probability 606--615
R. P. Bianchini, Jr. and
R. W. Buskens Implementation of online distributed
system-level diagnosis theory . . . . . 616--626
I. Pomeranz and
S. M. Reddy The multiple observation time test
strategy . . . . . . . . . . . . . . . . 627--637
N. R. Saxena and
P. Franco and
E. J. McCluskey Simple bounds on serial signature
analysis aliasing for random testing . . 638--645
Y. Zorian and
A. Ivanov An effective BIST scheme for ROM's . . . 646--653
W. Xiaoqing and
K. Kinoshita A testable design of logic circuits
under highly observable condition . . . 654--659
Heh-Tyan Liaw and
Chen-Shang Lin On the OBDD-representation of general
Boolean functions . . . . . . . . . . . 661--664
D. Thiebaut and
H. S. Stone and
J. L. Wolf Improving disk cache hit-ratios through
cache partitioning . . . . . . . . . . . 665--676
M. Takesue Cache memories for data flow machines 677--687
E. S. Park and
M. R. Mercer and
T. W. Williams The total delay fault model and
statistical delay fault coverage . . . . 688--698
K. P. Belkhale and
P. Banerjee Parallel algorithms for geometric
connected component labeling on a
hypercube multiprocessor . . . . . . . . 699--709
J. K. Antonio and
G. M. Huang and
W. K. Tsai A fast distributed shortest path
algorithm for a class of hierarchically
clustered data networks . . . . . . . . 710--724
Y. Tamir and
G. L. Frazier Dynamically-allocated multi-queue
buffers for VLSI communication switches 725--737
B. Wilkinson On crossbar switch and multiple bus
interconnection networks with
overlapping connectivity . . . . . . . . 738--746
A. K. Ramani and
P. K. Chande and
P. C. Sharma A general model for performance
investigations of priority based
multiprocessor system . . . . . . . . . 747--754
M. Y. Chan and
F. Y. L. Chin General schedulers for the pinwheel
problem based on double-integer
reduction . . . . . . . . . . . . . . . 755--768
P. Hansen and
K.-W. Lih Improved algorithms for partitioning
problems in parallel, pipelined, and
distributed computing . . . . . . . . . 769--771
J. R. S. Blair and
E. L. Lloyd Minimizing external wires in generalized
single-row routing . . . . . . . . . . . 771--776
R. S. Stevens and
D. J. Kaplan Determinacy of generalized schema . . . 776--779
A. Pelc Optimal fault diagnosis in comparison
models . . . . . . . . . . . . . . . . . 779--786
M. Arnold and
T. Bailey and
J. Cowles Comments on ``An architecture for
addition and subtraction of long word
length numbers in the logarithmic number
system'' by D. M. Lewis . . . . . . . . 786--788
A. Gupta and
W.-D. Weber Cache invalidation patterns in
shared-memory multiprocessors . . . . . 794--810
J. P. Singh and
H. S. Stone and
D. F. Thiebaut A model of workloads and its use in
miss-rate prediction for fully
associative caches . . . . . . . . . . . 811--825
A. K. Uht Concurrency extraction via hardware
methods executing the static instruction
stream . . . . . . . . . . . . . . . . . 826--841
A. Bagchi and
S. L. Hakimi Data transfers in broadcast networks . . 842--847
M. A. Fiol and
A. S. Llado The partial line digraph technique in
the design of large interconnection
networks . . . . . . . . . . . . . . . . 848--857
M. Afghahi and
C. Svensson Performance of synchronous and
asynchronous schemes for VLSI systems 858--872
C.-T. Ho An observation on the bisectional
interconnection networks . . . . . . . . 873--877
Cheol-Hoon Lee and
Dongmyun Lee and
Myunghwan Kim Optimal task assignment in linear array
networks . . . . . . . . . . . . . . . . 877--880
D. L. Tao and
C. R. P. Hartmann and
P. K. Lala A general technique for designing
totally self-checking checker for
$1$-out-of-$N$ code with minimum gate
delay . . . . . . . . . . . . . . . . . 881--886
N. Takagi and
S. Yajima Modular multiplication hardware
algorithms with a redundant
representation and their application to
RSA cryptosystem . . . . . . . . . . . . 887--891
N. Kanopoulos and
D. Pantzartzis and
F. R. Bartram Design of self-checking circuits using
DCVS logic: a case study . . . . . . . . 891--896
A. S. LaPaugh and
R. J. Lipton and
J. S. Sandberg How to store a triangular matrix . . . . 896--899
A. K. Somani and
V. K. Agarwal Distributed diagnosis algorithms for
regular interconnected structures . . . 899--906
A. Vergis On the testability of one-dimensional
ILAs for multiple sequential faults . . 906--916
P. K. Chan and
M. D. F. Schlag and
C. D. Thomborson and
V. G. Oklobdzija Delay optimization of carry-skip adders
and block carry-lookahead adders using
multidimensional dynamic programming . . 920--930
T. Lynch and
E. E. Swartzlander, Jr. A spanning tree carry lookahead adder 931--939
Z.-J. Mou and
F. Jutand `Overturned-stairs' adder trees and
multiplier design . . . . . . . . . . . 940--948
N. Takagi A radix-$4$ modular multiplication
hardware algorithm for modular
exponentiation . . . . . . . . . . . . . 949--956
A. Skavantzos and
P. B. Rao New multipliers modulo $2^N - 1$ . . . . 957--961
M. A. Hasan and
M. Wang and
V. K. Bhargava Modular construction of low complexity
parallel multipliers for a class of
finite fields $\mathrm{GF}(2^m)$ . . . . 962--971
M. A. Hasan and
V. K. Bhargava Bit-serial systolic divider and
multiplier for finite fields
$\mathrm{GF}(2^m)$ . . . . . . . . . . . 972--980
D. Wong and
M. Flynn Fast Division Using Accurate Quotient
Approximations to Reduce the Number of
Iterations . . . . . . . . . . . . . . . 981--995
T. Lang and
P. Montuschi Higher radix square root with prescaling 996--1009
D. Timmermann and
H. Hahn and
B. J. Hosticka Low Latency Time CORDIC Algorithms . . . 1010--1015
J.-A. Lee and
T. Lang Constant-factor redundant CORDIC for
angle calculation and rotation . . . . . 1016--1025
M. Lu and
J.-S. Chiang A novel division algorithm for the
residue number system . . . . . . . . . 1026--1032
H. Yokoo Overflow/Underflow-Free Floating-Point
Number Representations with
Self-Delimiting Variable-Length Exponent
Field . . . . . . . . . . . . . . . . . 1033--1039
M. G. Arnold and
T. A. Bailey and
J. R. Cowles and
M. D. Winkel Applying features of IEEE 754 to
sign/logarithm arithmetic . . . . . . . 1040--1050
H. S. Stone and
J. Turek and
J. L. Wolf Optimal partitioning of cache memory . . 1054--1068
B. S. Fagin Fast addition of large integers . . . . 1069--1077
C. H. Stapper and
H.-S. Lee Synergistic fault-tolerance for memory
chips . . . . . . . . . . . . . . . . . 1078--1087
A. Guha and
L. L. Kinney Relating the cyclic behavior of linear
and intrainverted feedback shift
registers . . . . . . . . . . . . . . . 1088--1100
T. Damarla Generalized transforms for multiple
valued circuits and their fault
detection . . . . . . . . . . . . . . . 1101--1109
M. Zafirovic-Vukotic and
I. G. Niemegeers A performance modeling and evaluation of
the Cambridge Fast Ring . . . . . . . . 1110--1125
D. M. Blough and
G. F. Sullivan and
G. M. Masson Efficient diagnosis of multiprocessor
systems under probabilistic models . . . 1126--1136
C. B. Silio, Jr. and
H. M. Ghafir and
M. R. Parikh An approximate method for the
performance analysis of PLAYTHROUGH
rings . . . . . . . . . . . . . . . . . 1137--1155
S. M. Shatz and
J.-P. Wang and
M. Goto Task allocation for maximizing
reliability of distributed computer
systems . . . . . . . . . . . . . . . . 1156--1168
V. H. Allan and
B. Su and
P. Wijaya and
J. Wang Foresighted instruction scheduling under
timing constraints . . . . . . . . . . . 1169--1172
Kuo-Liang Chung and
Wen-Chin Chen and
Ferng-Ching Lin On the complexity of search algorithms 1172--1176
M. Li and
N. D. Georganas Exact parametric analysis of stochastic
Petri nets . . . . . . . . . . . . . . . 1176--1180
T. P. Kelliher and
R. M. Owens and
M. J. Irwin and
T.-T. Hwang ELM --- a fast addition algorithm
discovered by a program . . . . . . . . 1181--1184
Nen-Fu Huang On the complexity of two circle strongly
connecting problems . . . . . . . . . . 1185--1188
J. H. Weber and
C. de Vroedt and
D. E. Boekee Necessary and sufficient conditions on
block codes correcting/detecting errors
of various types . . . . . . . . . . . . 1189--1193
N. Lopez-Benitez and
J. A. B. Fortes Detailed modeling and reliability
analysis of fault-tolerant processor
arrays . . . . . . . . . . . . . . . . . 1193--1200
I. D. Scherson and
D. A. Kramer and
B. D. Alleyne Bit-parallel arithmetic in a
massively-parallel associative processor 1201--1210
H. Mulder and
M. J. Flynn Processor architecture and data
buffering . . . . . . . . . . . . . . . 1211--1222
P. W. Dowd Wavelength division multiple access
channel hypercube processor
interconnection . . . . . . . . . . . . 1223--1241
T. C. Lee and
J. P. Hayes A fault-tolerant communication scheme
for hypercube computers . . . . . . . . 1242--1256
D. D. Kandlur and
K. G. Shin Traffic routing for multicomputer
networks with virtual cut-through
capability . . . . . . . . . . . . . . . 1257--1270
P. Nain and
D. Towsley Comparison of hybrid minimum
laxity/first-in-first-out scheduling
policies for real-time multiprocessors 1271--1278
R. Berry Computer benchmark evaluation and design
of experiments: a case study . . . . . . 1279--1289
R. Allen and
K. Kennedy Vector register allocation . . . . . . . 1290--1317
J. Bruck and
M. Blaum New techniques for constructing EC/AUED
codes . . . . . . . . . . . . . . . . . 1318--1324
R. J. Cosentino and
J. J. Vaccaro Adaptation of the Mactaggart and Jack
Complex Multiplication Algorithm for
Floating-Point Operators . . . . . . . . 1324--1326
K. S. Hong and
J. Y.-T. Leung On-line scheduling of real-time tasks 1326--1331
A. Skavantzos and
T. Stouraitis Decomposition of complex multipliers
using polynomial encoding . . . . . . . 1331--1333
Y. C. Lim Single-precision multiplier with reduced
circuit complexity for signal processing
applications . . . . . . . . . . . . . . 1333--1336
B. Alspach Cayley graphs with optimal fault
tolerance . . . . . . . . . . . . . . . 1337--1339
F. Lombardi and
C. Feng and
W.-K. Huang Detection and location of multiple
faults in baseline interconnection
networks . . . . . . . . . . . . . . . . 1340--1344
S. R. Whitaker and
G. K. Maki Self synchronized asynchronous
sequential pass transistor circuits . . 1344--1348
J. A. Brzozowski and
J. C. Ebergen On the delay-sensitivity of gate
networks . . . . . . . . . . . . . . . . 1349--1360
Yao-Ming Yeh and
T. Feng On a class of rearrangeable networks . . 1361--1379
E. Boros and
P. L. Hammer and
R. Shamir A polynomial algorithm for balancing
acyclic data flow graphs . . . . . . . . 1380--1385
A. Sengupta and
A. T. Dahbura On self-diagnosable multiprocessor
systems: diagnosis by the comparison
approach . . . . . . . . . . . . . . . . 1386--1396
S. H. Hosseini and
N. Jamal Efficient distributed algorithms for
self testing of multiple processor
systems . . . . . . . . . . . . . . . . 1397--1409
P. Fraigniaud Asymptotically optimal broadcasting and
gossiping in faulty hypercube
multicomputers . . . . . . . . . . . . . 1410--1419
N.-F. Tzeng A cost-effective combining structure for
large-scale shared-memory
multiprocessors . . . . . . . . . . . . 1420--1429
D. M. Blough and
G. F. Sullivan and
G. M. Masson Intermittent fault diagnosis in
multiprocessor systems . . . . . . . . . 1430--1441
E. Drakopoulos and
M. J. Merges Performance analysis of client-server
storage systems . . . . . . . . . . . . 1442--1452
G. A. Orton and
L. E. Peppard and
S. E. Tavares New fault tolerant techniques for
residue number systems . . . . . . . . . 1453--1464
S. Srinivas and
N. N. Biswas Design and analysis of a generalized
architecture for reconfigurable $m$-ary
tree structures . . . . . . . . . . . . 1465--1478
D. Goldfeld and
T. Etzion UPP graphs and UMFA
networks-architecture for parallel
systems . . . . . . . . . . . . . . . . 1479--1483
J. Cortadella and
J. M. Llaberia Evaluation of $A + B = K$ conditions
without carry propagation . . . . . . . 1484--1488
J. M. Peha and
F. A. Tobagi Comments on ``Tolerance of double-loop
computer networks to multimode
failures'' by H. Masuyama and T.
Ichimori . . . . . . . . . . . . . . . . 1488--1490
Guu-Chang Yang and
T. Fuja The reliability of systems with two
levels of fault tolerance: the return of
the `birthday surprise' . . . . . . . . 1490--1496
M. D. Ercegovac and
T. Lang On-the-fly rounding [computing
arithmetic] . . . . . . . . . . . . . . 1497--1503
D. Agrawal and
J. R. Agre Recovering from multiple process
failures in the time warp mechanism . . 1504--1514
G. S. Choi and
R. K. Iyer FOCUS: an experimental environment for
fault sensitivity analysis . . . . . . . 1515--1526
F. Fink and
K. Fuchs and
M. H. Schulz Robust and nonrobust path delay fault
simulation by parallel processing of
patterns . . . . . . . . . . . . . . . . 1527--1536
W. W. Hwu and
P. P. Chang Efficient instruction sequencing with
inline target insertion . . . . . . . . 1537--1551
T. G. Clarkson and
D. Gorse and
J. G. Taylor and
C. K. Ng Learning probabilistic RAM nets using
VLSI structures . . . . . . . . . . . . 1552--1561
A. Hlawiczka Parallel signature analyzers using
hybrid design of their linear feedbacks 1562--1571
R. Krishnamurti and
E. Ma An approximation algorithm for
scheduling tasks on varying partition
sizes in partitionable multiprocessor
systems . . . . . . . . . . . . . . . . 1572--1579
R. Kapur and
M. R. Mercer Bounding signal probabilities for
testability measurement using
conditional syndromes . . . . . . . . . 1580--1588
M. T. O'Keefe and
J. A. B. Fortes and
B. W. Wah On the relationship between two systolic
array design methodologies . . . . . . . 1589--1593
G. M. Megson A fast Faddeev array . . . . . . . . . . 1594--1600
B. Bose and
S. Al-Bassam Byte unidirectional error correcting and
detecting codes . . . . . . . . . . . . 1601--1606
P. Montuschi and
L. Ciminiera Design of a radix $4$ division unit with
simple selection table . . . . . . . . . 1606--1611
N. T. Quach and
M. J. Flynn High-speed addition in CMOS . . . . . . 1612--1615
Sy-Yen Kuo and
Sheng-Chiech Liang Concurrent error detection and
correction in real-time systolic sorting
arrays . . . . . . . . . . . . . . . . . 1615--1620
A. E. Kamal An algorithm for the efficient
utilization of bandwidth in the slotted
ring . . . . . . . . . . . . . . . . . . 1620--1627
E. J. Schwabe A Benes-like theorem for the
shuffle-exchange graph . . . . . . . . . 1627--1630
A. Mendelson and
D. Thiebaut and
D. K. Pradhan Modeling live and dead lines in cache
memory systems . . . . . . . . . . . . . 1--14
H.-A. Lin and
C.-L. Tarng An improved method for constructing
multiphase communications protocols . . 15--26
S. Latifi Combinatorial analysis of the
fault-diameter of the $n$-cube . . . . . 27--33
G. S. Sohi High-bandwidth interleaved memories for
vector processors --- a simulation study 34--44
C. A. Papachristou and
V. R. Immaneni Vertical migration of software functions
and algorithms using enhanced
microsequencing . . . . . . . . . . . . 45--61
D. Tang and
R. K. Iyer Dependability measurement and modeling
of a multicomputer system . . . . . . . 62--75
F. Boeri and
M. Auguin OPSILA: a vector and parallel processor 76--82
A. Thomasian and
V. F. Nicola Performance evaluation of a threshold
policy for scheduling readers and
writers . . . . . . . . . . . . . . . . 83--98
Y. H. Hu and
S. Naganathan An angle recording method for CORDIC
algorithm implementation . . . . . . . . 99--102
D. M. Mandelbaum Some results on a SRT type division
scheme . . . . . . . . . . . . . . . . . 102--106
T.-H. Kuo and
H. C. Lin and
R. C. Potter and
D. Schupe Multiple-valued counter . . . . . . . . 106--109
T. A. Gulliver and
V. K. Bhargava A systematic $(16, 8)$ code for
correcting double errors and detecting
triple-adjacent errors . . . . . . . . . 109--112
A. Spray and
S. Jones Performance tradeoffs in rings of
data-driven elements . . . . . . . . . . 113--118
Christophe Mazenc and
Xavier Merrheim and
Jean-Michel Muller Computing functions $\cos^{-1}$ and
$\sin^{-1}$ using Cordic . . . . . . . . 118--122
H. C. Torng and
M. Day Interrupt handling for out-of-order
execution processors . . . . . . . . . . 122--127
S. Vassiliadis and
E. M. Schwarz Correction to ``Hard-wired multipliers
with encoded partial products'' . . . . 127--127
S. Chakravarty A characterization of binary decision
diagrams . . . . . . . . . . . . . . . . 129--137
I. Chlamtac and
A. Ganz and
M. G. Kienzle An HIPPI interconnection system . . . . 138--150
B. Mukherjee and
S. Banerjee Alternative strategies for improving the
fairness in and an analytical model of
the DQDB network . . . . . . . . . . . . 151--167
J. Duprat and
J.-M. Muller The CORDIC Algorithm: New Results for
Fast VLSI Implementation . . . . . . . . 168--178
N. K. Jha Fault detection in CVS parity trees with
application to strongly self-checking
parity and two-rail checkers . . . . . . 179--189
A. Choi and
M. Ruschitzka Managing locality sets: the model and
fixed-size buffers . . . . . . . . . . . 190--204
D. M. Blough and
A. Pelc Diagnosis and repair in multiprocessor
systems . . . . . . . . . . . . . . . . 205--217
K. T. Sun and
H. C. Fu A hybrid neural network model for
solving optimization problems . . . . . 218--227
T. Kameda and
S. Pilarski and
A. Ivanov Notes on multiple input signature
analysis . . . . . . . . . . . . . . . . 228--234
R. E. Fowkes Hardware Efficient Algorithms for
Trigonometric Functions . . . . . . . . 235--239
P. Montuschi and
L. Ciminiera Reducing iteration time when result
digit is zero for radix $2$ SRT division
and square root with redundant
remainders . . . . . . . . . . . . . . . 239--246
N. F. Tzeng A cube-connected cycles architecture
with high reliability and improved
performance . . . . . . . . . . . . . . 246--253
A. Bagchi and
S. L. Hakimi and
E. F. Schmeichel Gossiping in a distributed network . . . 253--256
A. F. Pour and
M. D. Hill Performance implications of tolerating
cache faults . . . . . . . . . . . . . . 257--267
A. Lioy On the equivalence of fanout-point
faults . . . . . . . . . . . . . . . . . 268--271
N. S. V. Rao Expected-value analysis of two single
fault diagnosis algorithms . . . . . . . 272--280
J. L. Holi and
J.-N. Hwang Finite precision error analysis of
neural network hardware implementations 281--290
A. Sakar and
R. J. Mammone Growing and pruning neural tree networks 291--299
M. Lades and
J. C. Vorbruggen and
J. Buhmann and
J. Lange and
C. von der Malsburg and
R. P. Wurtz and
W. Konen Distortion invariant object recognition
in the dynamic link architecture . . . . 300--311
K. R. Pattipati and
Y. Li and
H. A. P. Blom A unified framework for the
performability evaluation of
fault-tolerant computer systems . . . . 312--326
M. Balakrishnan and
C. S. Raghavendra An analysis of a reliability model for
repairable fault-tolerant systems . . . 327--339
A. K. Das and
P. P. Chaudhuri Vector space theoretic analysis of
additive cellular automata and its
application for pseudoexhaustive test
pattern generation . . . . . . . . . . . 340--352
H. Braun and
F. C. Stephan On optimizing diameter and average
distance of directed interconnected
networks . . . . . . . . . . . . . . . . 353--358
A. van de Liefvoort and
N. Subramanian A new approach for the performance
analysis of a single-bus multiprocessor
system with general service times . . . 358--362
A. M. Gonzalez and
J. M. Llaberia Reducing branch delay to zero in
pipelined processors . . . . . . . . . . 363--371
G. Miel Constant geometry fast Fourier
transforms on array processors . . . . . 371--375
C. D. Walter Systolic modular multiplication . . . . 376--378
B. Parhami On the implementation of arithmetic
support functions for generalized
signed-digit number systems . . . . . . 379--384
T. A. Varvarigou and
V. P. Roychowdhury and
T. Kailth A polynomial time algorithm for
reconfiguring multiple-track models . . 385--395
C. H. Perleberg and
A. J. Smith Branch target buffer design and
optimization . . . . . . . . . . . . . . 396--412
M. Lapointe and
H. T. Huynh and
P. Fortier Systematic design of pipelined recursive
filters . . . . . . . . . . . . . . . . 413--426
E. D. Di Claudio and
G. Orlandi and
F. Piazza A systolic redundant residue arithmetic
error correction circuit . . . . . . . . 427--432
G. R. Redinbo and
L. M. Napolitano, Jr. and
D. D. Andaleon Multibit correcting data interface for
fault-tolerant systems . . . . . . . . . 433--446
N. S. V. Rao Computational complexity issues in
operative diagnosis of graph-based
systems . . . . . . . . . . . . . . . . 447--457
A. K. Nanda and
L. N. Bhuyan Design and analysis of cache coherent
multistage interconnection networks . . 458--470
R. Raghavan and
J. P. Hayes Reducing interference among vector
accesses in interleaved memories . . . . 471--483
S. J. Upadhyaya and
H. Pham Analysis of noncoherent systems and an
architecture for the computation of the
system reliability . . . . . . . . . . . 484--493
B. Arazi Architectures for exponentiation over
$\mathrm{GD}(2^n)$ adopted for smartcard
application . . . . . . . . . . . . . . 494--497
N. Funabiki and
Y. Takefuji and
K. C. Lee Comparisons of seven neural network
models on traffic control problems in
multistage interconnection networks . . 497--501
S.-C. Cheng and
W.-H. Tsai A neural network implementation of the
moment-preserving technique and its
application to thresholding . . . . . . 501--507
J. van den Berg and
D. Toswley Properties of the miss ratio for a
2-level storage model with LRU or FIFO
replacement strategy and independent
references . . . . . . . . . . . . . . . 508--512
S. Y. Berkovich An overlaying technique for solving
linear equations in real-time computing 513--517
D. M. Blough and
A. Pelc A clustered failure model for the memory
array reconfiguration problem . . . . . 518--528
J. Z. Fang and
M. Lu An iteration partition approach for
cache or local memory thrashing on
parallel processing . . . . . . . . . . 529--546
Y. Saitoh and
H. Imai Some codes for correcting and detecting
unidirectional byte errors . . . . . . . 547--552
H. Kakugawa and
S. Fujita and
M. Yamashita and
T. Ae Availability of $k$-coterie . . . . . . 553--558
B. G. Douglass Rearrangeable three-stage
interconnection networks and their
routing properties . . . . . . . . . . . 559--567
D. Brand and
T. Sasao Minimization of AND--EXOR expressions
using rewrite rules . . . . . . . . . . 568--576
C. Qiao and
R. G. Melhem Time-division optical communications in
multiprocessor arrays . . . . . . . . . 577--590
P. P. Trabado and
A. Lloris-Ruiz and
J. Ortega-Lopera Solution of switching equations based on
a tabular algebra . . . . . . . . . . . 591--596
A. Lim and
S.-W. Cheng and
S. Sahni Optimal joining of compacted cells . . . 597--607
G. Dimauro and
S. Impedovo and
G. Pirlo A new technique for fast number
comparison in the residue number system 608--612
D. Ding-Zhu and
Y.-D. Lyuu and
D. F. Hsu Line digraph iterations and connectivity
analysis of de Bruijn and Kautz graphs 612--616
D. T. Harper III and
Y. Costa Analytical estimation of vector access
performance in parallel memory
architectures . . . . . . . . . . . . . 616--624
S. V. R. Madabhushi and
S. Lakshmivarahan and
S. K. Dhall A note on orthogonal graphs . . . . . . 624--630
D. J. Rosenkrantz and
S. S. Ravi Improved bounds for algorithm-based
fault tolerance . . . . . . . . . . . . 630--635
D. Thiebaut and
J. Wolf and
H. Stone Corrigendum to `synthetic traces for
trace-driven simulation of cache
memories' . . . . . . . . . . . . . . . 635--636
Tao Wang and
Xinhau Zhuang and
XiaoLiang Xing and
Xipeng Xiao A neuron-weighted learning algorithm and
its hardware implementation in
associative memories . . . . . . . . . . 636--640
J. Rajski and
J. Tyszer Accumulator-based compaction of test
responses . . . . . . . . . . . . . . . 643--650
E. K. Lee and
R. H. Katz The performance of parity placements in
disk arrays . . . . . . . . . . . . . . 651--664
N. Das and
B. B. Bhattacharya and
J. Dattagupta Isomorphism of conflict graphs in
multistage interconnection networks and
its application to optimal routing . . . 665--677
R. Miller and
V. K. Prasanna-Kumar and
D. I. Reisis and
Q. F. Stout Parallel computations on reconfigurable
meshes . . . . . . . . . . . . . . . . . 678--692
S. E. Eldridge and
C. D. Walter Hardware implementation of Montgomery's
modular multiplication algorithm . . . . 693--699
S. J. Piestrak The minimal test set for multioutput
threshold circuits implemented as
sorting networks . . . . . . . . . . . . 700--712
Y.-Y. Chen and
S. J. Upadhyaya Reliability, reconfiguration, and spare
allocation issues in binary-tree
architectures based on multiple-level
redundancy . . . . . . . . . . . . . . . 713--723
I. Koren and
Z. Koren and
C. H. Stepper A unified negative-binomial distribution
for yield analysis of defect-tolerant
circuits . . . . . . . . . . . . . . . . 724--734
R. Cohen One-bit delay in ring networks . . . . . 735--737
A. E. Kamal and
V. C. Hamacher Response to ``One-bit delay in ring
networks'' by R. Cohen . . . . . . . . . 737--738
D. Fernandez-Baca and
A. Medepalli Parametric module allocation on partial
$k$-trees . . . . . . . . . . . . . . . 738--742
A. Kavianpour and
N. Bagherzadeh A systematic approach for mapping
application tasks in hypercubes . . . . 742--746
H. M. Alnuweiri A new class of optimal bounded-degree
VLSI sorting networks . . . . . . . . . 746--752
R. Hughey Concurrent error detection on
programmable systolic arrays . . . . . . 752--756
S. W. Graham and
S. R. Seidel The cost of broadcasting on star graphs
and $k$-ary hypercubes . . . . . . . . . 756--759
V. Kantabutra Designing optimum one-level carry-skip
adders . . . . . . . . . . . . . . . . . 759--764
V. Raghavan On asymmetric invalidation with partial
tests . . . . . . . . . . . . . . . . . 764--768
K. Kota and
J. R. Cavallaro Numerical Accuracy and Hardware
Tradeoffs for CORDIC Arithmetic for
Special-Purpose Processors . . . . . . . 769--779
R. K. Sitaraman and
N. K. Jha Optimal design of checks for error
detection and location in fault-tolerant
multiprocessor systems . . . . . . . . . 780--793
A. Chatterjee and
M. A. d'Abreu The design of fault-tolerant linear
digital state variable systems: theory
and techniques . . . . . . . . . . . . . 794--808
K. Geihs and
R. Heite and
U. H. Hollberg Protected object references in
heterogeneous distributed systems . . . 809--816
J. Duprat and
Y. Herreros and
S. Kla New redundant representations of complex
numbers and vectors . . . . . . . . . . 817--824
S. Vassiliadis and
J. Phillips and
B. Blaner Interlock collapsing ALU's . . . . . . . 825--839
H. Krishna and
J.-D. Sun On theory and fast algorithms for error
correction in residue number system
product codes . . . . . . . . . . . . . 840--853
E. H.-M. Sha and
K. Steiglitz Reconfigurability and reliability of
systolic/wavefront arrays . . . . . . . 854--862
W. Lin Manipulating general vectors on
synchronous binary $n$-cube . . . . . . 863--871
C. H. Stapper Improved yield models for fault-tolerant
memory chips . . . . . . . . . . . . . . 872--881
S. Lee and
K. G. Shin Optimal and efficient probabilistic
distributed diagnosis schemes . . . . . 882--886
W.-Z. Shen and
G.-H. Hwang and
W.-J. Hsu and
Y.-J. Jan Design of pseudoexhaustive testable PLA
with low overhead . . . . . . . . . . . 887--891
J.-C. Lo and
S. Thanawastien and
T. R. N. Rao Berger check prediction for array
multipliers and array dividers . . . . . 892--896
J. Ortega and
A. Prieto and
A. Lloris and
F. J. Pelayo Generalized Hopfield neural network for
concurrent testing . . . . . . . . . . . 898--912
J. Arlat and
A. Costes and
Y. Crouzet and
J. C. Laprie and
D. Powell Fault injection and dependability
evaluation of fault-tolerant systems . . 913--923
B. Vinnakota and
N. K. Jha Diagnosability and diagnosis of
algorithm-based fault-tolerant systems 924--937
S. N. Bhatt and
G. Pucci and
A. Ranade and
A. L. Rosenberg Scattering and gathering messages in
networks of processors . . . . . . . . . 938--949
Y. Hata and
K. Nakashima and
K. Yamato Some fundamental properties of
multiple-valued Kleenean functions and
determination of their logic formulas 950--961
G. Alia and
E. Martinelli On the lower bound to the VLSI
complexity of number conversion from
weighted to residue representation . . . 962--967
J. Ortega and
A. L. Ruiz and
A. Prieto and
F. J. Pelayo Test-pattern generation based on
Reed--Muller coefficients . . . . . . . 968--980
J. Stephens and
V. Raghavan On single-fault set diagnosability in
the PMC model . . . . . . . . . . . . . 981--983
A. Das and
K. Thulasiraman and
V. K. Agarwal and
K. B. Lakshmanan Multiprocessor fault diagnosis under
local constraints . . . . . . . . . . . 984--988
S. K. Park and
J. H. Kim Geometrical learning algorithm for
multilayer neural networks in a binary
field . . . . . . . . . . . . . . . . . 988--992
D. P. Mehta and
S. Sahni A data structure for circular string
analysis and visualization . . . . . . . 992--997
J. E. Sasinowski and
J. K. Strosnider A dynamic programming algorithm for
cache memory partitioning for real-time
systems . . . . . . . . . . . . . . . . 997--1001
K. Day and
A. Tripathi Embedding of cycles in arrangement
graphs . . . . . . . . . . . . . . . . . 1002--1006
S. Arno and
F. S. Wheeler Signed digit representations of minimal
Hamming weight . . . . . . . . . . . . . 1007--1010
H. Brunner and
A. Curiger and
M. Hofstetter On computing multiplicative inverses in
$\mathrm{GF}(2^m)$ . . . . . . . . . . . 1010--1015
S. Mukherjee and
S. K. Tripathi and
D. Ghosal A multiclass priority-based slotted-ring
LAN and its analysis . . . . . . . . . . 1015--1020
T. R. N. Rao and
G. L. Feng and
M. S. Kolluru and
J. C. Lo Novel totally self-checking Berger code
checker designs based on generalized
Berger code partitioning . . . . . . . . 1020--1024
P. D. Fisher and
Sheng-Fu Wu Race-free state assignments for
synthesizing large-scale asynchronous
sequential logic circuits . . . . . . . 1025--1034
M. G. Karpovsky and
S. M. Chaudhry Design of self-diagnostic boards by
multiple signature analysis . . . . . . 1035--1044
W. Y. Chen and
P. P. Chang and
T. M. Conte and
W. W. Hwu The effect of code expanding
optimizations on instruction cache
design . . . . . . . . . . . . . . . . . 1045--1057
J. Gotze and
S. Paul and
M. Sauer An efficient Jacobi-like algorithm for
parallel eigenvalue computation . . . . 1058--1065
I. Pomeranz and
S. M. Reddy Classification of faults in synchronous
sequential circuits . . . . . . . . . . 1066--1077
J. Kim and
K. G. Shin Deadlock-free fault-tolerant routing in
injured hypercubes . . . . . . . . . . . 1078--1088
J. Bruck and
R. Cypher and
C. Ho Fault-tolerant meshes and hypercubes
with minimal numbers of spares . . . . . 1089--1104
P. W. Dowd and
K. Bogineni and
K. A. Aly and
J. A. Perreault Hierarchical scalable photonic
architectures for high-performance
processor interconnection . . . . . . . 1105--1120
S. Narayanan and
R. Gupta and
M. A. Breuer Optimal configuring of multiple scan
chains . . . . . . . . . . . . . . . . . 1121--1131
W. A. Porter and
Xiaoyan Zheng A nonbinary neural network design . . . 1132--1135
Y.-Y. Chen and
S. J. Upadhyaya Yield analysis of reconfigurable array
processors based on multiple-level
redundancy . . . . . . . . . . . . . . . 1136--1141
Chin-Liang Wang and
Jung-Lung Lin A systolic architecture for computing
inverses and divisions in finite fields
$\mathrm{GF}(2^m)$ . . . . . . . . . . . 1141--1146
K. A. Hua and
L. Liu and
J. Peir Designing high-performance processors
using real address prediction . . . . . 1146--1151
M. Morii and
K. Iwasaki A note on aliasing probability for
multiple input signature analyzer . . . 1152--1152
C. E. Wu and
Y. Hsu and
Y.-H. Liu A quantitative evaluation of cache types
for high-performance computer systems 1154--1162
A. Tyagi A reduced-area scheme for carry-select
adders . . . . . . . . . . . . . . . . . 1163--1170
Sang-Hwa Chung and
D. I. Moldovan and
R. F. DeMara A parallel computational model for
integrated speech and natural language
understanding . . . . . . . . . . . . . 1171--1183
P. F. Chimento and
K. S. Trivedi The completion time of programs on
processors subject to failure and repair 1184--1194
N. F. Vaidya and
D. K. Pradhan Fault-tolerant design strategies for
high reliability and safety . . . . . . 1195--1206
C. J. Colbourn and
J. S. Devitt and
D. D. Harms and
M. Kraetzl Assessing reliability of multistage
interconnection networks . . . . . . . . 1207--1221
A. Saha and
Chuan-Lin Wu and
Dun-Sung Tang Approximation, dimension reduction, and
nonconvex optimization using linear
superpositions of Gaussians . . . . . . 1222--1233
E. M. Schwarz and
M. J. Flynn Parallel high-radix nonrestoring
division . . . . . . . . . . . . . . . . 1234--1246
Nian-Feng Tzeng and
Po-Jen Chuang and
Chwan-Hwa Wu Creating disjoint paths in Gamma
interconnection networks . . . . . . . . 1247--1252
P. J. Bernhard Bounds on the performance of message
routing heuristics . . . . . . . . . . . 1253--1256
T. Stouraitis Borrow: a fault-tolerance scheme for
wavefront array processors . . . . . . . 1257--1261
S. Al-Bassam and
B. Bose Design of efficient error-correcting
balanced codes . . . . . . . . . . . . . 1261--1266
I. Pomeranz and
S. M. Reddy Testing of fault-tolerant hardware
through partial control of inputs . . . 1267--1271
S. Bhide and
N. John and
M. R. Kabuka A Boolean neural network approach for
the traveling salesman problem . . . . . 1271--1278
M. A. Hasan and
M. Z. Wang and
V. K. Bhargava A modified Massey--Omura parallel
multiplier for a class of finite fields 1278--1280
T. A. Varvarigou and
V. P. Roychowdhury and
T. Kailath Reconfiguring processor arrays using
multiple-track models: the
$3$-track-$1$-spare-approach . . . . . . 1281--1293
Mao-Chao Lin Constant weight codes for correcting
symmetric errors and detecting
unidirectional errors . . . . . . . . . 1294--1302
L. A. Laranjeira and
M. Malek and
R. Jenevein Nest: a nested-predicate scheme for
fault tolerance . . . . . . . . . . . . 1303--1324
A. A. Malik and
R. K. Brayton and
A. R. Newton and
A. L. Sangiovanni-Vincentelli Two-level minimization of multivalued
functions with large offsets . . . . . . 1325--1342
G. Chiola and
C. Dutheillet and
G. Franceschinis and
S. Haddad Stochastic well-formed colored nets and
symmetric modeling applications . . . . 1343--1360
T. P. Kelsey and
K. K. Saluja and
S. Y. Lee An efficient algorithm for sequential
circuit test generation . . . . . . . . 1361--1371
K. D. Wilken An optimal graph-construction approach
to placing program signatures for
signature monitoring . . . . . . . . . . 1372--1381
D. H. C. Du and
Ichiang Lin and
K. C. Chang On wafer-packing problems . . . . . . . 1382--1388
V. Kantabutra Accelerated two-level carry-skip adders
--- a type of very fast adders . . . . . 1389--1393
Jenn-Yang Tien and
Ching-Tien Ho and
Wei-Pang Yang Broadcasting on incomplete hypercubes 1393--1398
N. Bagherzadeh and
N. Nassif and
S. Latifi A routing and broadcasting scheme on
faulty star graphs . . . . . . . . . . . 1398--1403
J. H. Kim and
P. K. Rhee The rule-based approach to
reconfiguration of $2$-D processor
arrays . . . . . . . . . . . . . . . . . 1403--1408
Quing Yang Introducing a new cache design into
vector computers . . . . . . . . . . . . 1411--1424
K. A. Hua and
J. X. W. Su Dynamic load balancing in very large
shared-nothing hypercube database
computers . . . . . . . . . . . . . . . 1425--1439
V. F. Nicola and
M. K. Nakayama and
P. Heidelberger and
A. Goyal Fast simulation of highly dependable
systems with general failure and repair
processes . . . . . . . . . . . . . . . 1440--1452
P. Mazumder Design of a fault-tolerant
three-dimensional dynamic random-access
memory with on-chip error-correcting
circuit . . . . . . . . . . . . . . . . 1453--1468
Ching Yuh Jan and
A. Y. Oruc Fast self-routing permutation switching
on an asymptotically minimum cost
network . . . . . . . . . . . . . . . . 1469--1479
R. A. Rowley and
B. Bose Fault-tolerant ring embedding in de
Bruijn networks . . . . . . . . . . . . 1480--1486
A. El-Amawy and
M. Naraghi-Pour and
M. Hegde Noise modeling effects in redundant
synchronizers . . . . . . . . . . . . . 1487--1494
V. Kantabutra A recursive carry-lookahead/carry-select
hybrid adder . . . . . . . . . . . . . . 1495--1499
L. A. Sanchis Multiple-way network partitioning with
different cost functions . . . . . . . . 1500--1504
R. Johansson A class of $(12, 8)$ codes for
correcting single errors and detecting
double errors within a nibble . . . . . 1504--1506
K. Ahn and
S. Sahni NP-hard module rotation problems . . . . 1506--1510
Hong Hao and
E. J. McCluskey Analysis of gate oxide shorts in CMOS
circuits . . . . . . . . . . . . . . . . 1510--1516
J. Rajski and
J. Tyszer Recursive pseudoexhaustive test pattern
generation . . . . . . . . . . . . . . . 1517--1521
Yean-Shiang Leu and
D. H. C. Du Cycle compensation protocol: a fair
protocol for the unidirectional twin-bus
architecture . . . . . . . . . . . . . . 1--12
Z. Miller and
D. Pritikin and
I. H. Sudborough Near embeddings of hypercubes into
Cayley graphs on the symmetric group . . 13--22
Hsing-Lung Chen and
Nian-Feng Tzeng Efficient resource placement in
hypercubes using multiple-adjacency
codes . . . . . . . . . . . . . . . . . 23--33
S. Kawahito and
M. Ishida and
T. Nakamura and
M. Kameyama and
T. Higuchi High-speed area-efficient multiplier
design using multiple-valued
current-mode circuits . . . . . . . . . 34--42
H. Kabuo and
T. Taniguchi and
A. Miyoshi and
H. Yamashita and
M. Urano and
H. Edamatsu and
S. Kuninobu Accurate Rounding Scheme for the
Newton--Raphson Method Using Redundant
Binary Representation . . . . . . . . . 43--51
M. Holliday and
M. Stumm Performance evaluation of hierarchical
ring-based shared memory multiprocessors 52--67
S. J. Piestrak Design of residue generators and
multioperand modular adders using
carry-save adders . . . . . . . . . . . 68--77
N. M. Wigley and
G. A. Jullien and
D. Reaume Large dynamic range computations over
small finite rings . . . . . . . . . . . 78--86
Deng-Jyi Chen and
Min-Sheng Lin On distributed computing systems
reliability analysis under program
execution constraints . . . . . . . . . 87--97
Y. Karkouri and
E. M. Aboulhamid and
E. Cerny and
A. Verreault Use of fault dropping for multiple fault
analysis . . . . . . . . . . . . . . . . 98--103
K. K. Parhi and
F. H. Wu and
K. Genesan Sequential and parallel neural network
vector quantizers . . . . . . . . . . . 104--109
P. Mohapatra and
C. R. Das and
Tse-yun Feng Performance analysis of cluster-based
multiprocessors . . . . . . . . . . . . 109--114
F. Corella Automated verification of behavioral
equivalence for microprocessors . . . . 115--117
K. V. Asari and
C. Eswaran An optimization technique for the design
of multiple valued PLA's . . . . . . . . 118--122
B. Vinnakota and
V. V. B. Rao Generation of all Reed--Muller
expansions of a switching function . . . 122--124
M. Blaum and
J. Bruck and
L. Tolhuizen A note on ``A systematic $(12, 8)$ code
for correcting single errors and
detecting adjacent errors'' . . . . . . 125--125
S. M. Mahmud Comments on ``Synthetic traces for
trace-driven simulation of cache
memories'' . . . . . . . . . . . . . . . 125--126
M. A. Schuette and
J. P. Shen Exploiting instruction-level parallelism
for integrated control-flow monitoring 129--140
M. G. Karpovsky and
L. B. Levitin and
F. S. Vainstein Diagnosis by signature analysis of test
responses . . . . . . . . . . . . . . . 141--152
Youngsong Mun and
Hee Yong Youn Performance analysis of finite buffered
multistage interconnection networks . . 153--162
J. Burns and
C. J. Mitchell Parameter selection for server-aided RSA
computation schemes . . . . . . . . . . 163--174
S. S. Iyengar and
D. N. Jayasimha and
D. Nadig A versatile architecture for the
distributed sensor integration problem 175--185
W. R. Cyre Conceptual representation of waveforms
for temporal reasoning . . . . . . . . . 186--200
Gueesang Lee and
M. J. Irwin and
R. M. Owens Polynomial time testability of circuits
generated by input decomposition . . . . 201--210
T. V. Lakshman and
V. K. Wei Distributed computing on regular
networks with anonymous nodes . . . . . 211--218
S. Latifi and
M. Hegde and
M. Naraghi-Pour Conditional connectivity measures for
large multiprocessor systems . . . . . . 218--222
Si-Qing Zheng Compressed tree machines . . . . . . . . 222--225
Shyue-Win Wei A systolic power-sum circuit for
$\mathrm{GF}(2^m)$ . . . . . . . . . . . 226--229
M. Veeraraghavan and
K. S. Trivedi A combinatorial algorithm for
performance and reliability analysis
using multistate models . . . . . . . . 229--234
In-Cheol Park and
Se-Kyoung Hong and
Chong-Min Kyung Two complementary approaches for
microcode bit optimization . . . . . . . 234--239
T. Y. Chung and
N. Sharma and
D. P. Agrawal Cost-performance trade-offs in Manhattan
Street Network versus $2$-D torus . . . 240--243
Jianxun Ding and
L. N. Bhuyan Finite buffer analysis of multistage
interconnection networks . . . . . . . . 243--247
C. K. Kwok and
B. Mukherjee Transparent (cut-through) bridging of
CSMA/CD networks: performance analysis
and implementation . . . . . . . . . . . 247--253
V. T. Radoytchevsky and
A. J. Shalaev Comments on ``An $O(n^{2.5})$ fault
identification algorithm for diagnosable
systems'' . . . . . . . . . . . . . . . 254--255
A. Shallof and
S. Bennett Comments on ``Performability analysis of
distributed real-time-systems'' . . . . 255--256
J. Phillips and
S. Vassiliadis High-performance $3$-$1$ interlock
collapsing ALU's . . . . . . . . . . . . 257--268
P. Montuschi and
L. Ciminiera Over-redundant digit sets and the design
of digit-by-digit division units . . . . 269--277
W. F. Wong and
E. Goto Fast Hardware-Based Algorithms for
Elementary Function Computations Using
Rectangular Multipliers . . . . . . . . 278--294
L. E. La Forge and
Kaiyuan Huang and
V. K. Agarwal Almost sure diagnosis of almost every
good element [logic testing] . . . . . . 295--305
D. Lee and
M. Yannakakis Testing finite-state machines: state
identification and verification . . . . 306--320
A. V. Goldberg and
B. M. Maggs and
S. A. Plotkin A parallel algorithm for reconfiguring a
multibutterfly network with faulty
switches . . . . . . . . . . . . . . . . 321--326
G. Agrawal and
B. Chen and
W. Zhao and
S. Davari Guaranteeing synchronous message
deadlines with the timed token medium
access control protocol . . . . . . . . 327--339
C. M. Fiduccia and
K. J. Rappoport Perfect shifters [multiprocessor
interconnection networks] . . . . . . . 340--349
D. P. Mehta and
S. Sahni Computing display conflicts in string
visualization . . . . . . . . . . . . . 350--361
S. Al-Bassam and
B. Bose Design of efficient balanced codes . . . 362--365
S. H. Unger Some additions to ``Solution of
switching equations based on a tabular
algebra'' . . . . . . . . . . . . . . . 365--367
N. H. Vaidya and
D. K. Pradham Safe system level diagnosis . . . . . . 367--370
G. L. Feng and
T. R. N. Rao and
M. S. Kolluru Error correcting codes over $Z_2(m)$ for
algorithm-based fault tolerance . . . . 370--374
A. A. Abonamah and
F. N. Sibai and
N. K. Sharma Conflict resolution and fault-free path
selection in multicast-connected
cube-based networks . . . . . . . . . . 374--380
B. Parhami Comments on ``Evaluation of $A + B = K$
conditions without carry propagation'' 381--381
R. Katti Comments on ``Decomposition of Complex
Multipliers Using Polynomial Encoding'' 381--383
I. Wegener Comments on ``A characterization of
binary decision diagrams'' . . . . . . . 383--384
G. Buonanno and
D. Sciuto and
R. Stefanelli Innovative structures for CMOS
combinational gates synthesis . . . . . 385--399
Jien-Chung Lo Reliable Floating-Point Arithmetic
Algorithms for Error-Coded Operands . . 400--412
J. Ramirez and
R. Melhem Computational arrays with flexible
redundancy . . . . . . . . . . . . . . . 413--430
P. K. Dubey and
G. B. Adams III and
M. J. Flynn Instruction window size trade-offs and
characterization of program parallelism 431--442
M. J. Corinthios Optimal parallel and pipelined
processing through a new class of
matrices with application to generalized
spectral analysis . . . . . . . . . . . 443--459
V. Kantabutra and
A. G. Andreou A state assignment approach to
asynchronous CMOS circuit design . . . . 460--469
A. Lagman and
W. A. Najjar and
P. K. Srimani An analysis of edge fault tolerance in
recursively decomposable regular
networks . . . . . . . . . . . . . . . . 470--475
S. J. Upadhyaya and
B. Ramamurthy Concurrent process monitoring with no
reference signatures . . . . . . . . . . 475--480
I. Chlamtac and
A. Farago An optimal channel access protocol with
multiple reception capacity . . . . . . 480--484
S. Kipnis Analysis of asynchronous binary
arbitration on digital transmission-line
busses . . . . . . . . . . . . . . . . . 484--489
S. W. Burns and
N. K. Jha A totally self-checking checker for a
parallel unordered coding scheme . . . . 490--495
Chih-Yuang Su and
Cheng-Wen Wu Testing iterative logic arrays for
sequential faults with a constant number
of patterns . . . . . . . . . . . . . . 495--501
S. W. Ng and
R. L. Mattson Uniform parity group distribution in
disk arrays with multiple failures . . . 501--506
Chien-In Henry Chen and
A. Kumar Comments on ``Area-time optimal adder
design'' . . . . . . . . . . . . . . . . 507--512
T. Soneoka and
T. Ibaraki Logically instantaneous message passing
in asynchronous distributed systems . . 513--527
Chao-Ju Hou and
K. G. Shin Incorporation of optimal timeouts into
distributed real-time load sharing . . . 528--547
S. Prakash and
Yann Hang Lee and
T. Johnson A nonblocking algorithm for shared
queues using compare-and-swap . . . . . 548--559
D. W. Clark and
Lih-Jyh Weng Maximal and near-maximal shift register
sequences: efficient event counters and
easy discrete logarithms . . . . . . . . 560--568
I. Pomeranz and
S. M. Reddy Application of homing sequences to
synchronous sequential circuit testing 569--580
M. Sarrafzadeh and
D. Wagner and
F. Wagner and
K. Weihe Wiring knock-knee layouts: a global
approach . . . . . . . . . . . . . . . . 581--589
S. Al-Bassam and
B. Bose Asymmetric/unidirectional error
correcting and detecting codes . . . . . 590--597
V. L. Chi Salphasic distribution of clock signals
for synchronous systems . . . . . . . . 597--602
M. De and
B. P. Sinha Fast parallel algorithm for ternary
multiplication using multivalued $I^2 L$
technology . . . . . . . . . . . . . . . 603--607
Pei-Ji Yang and
Sing-Ban Tien and
C. S. Raghavendra Embedding of rings and meshes onto
faulty hypercubes using free dimensions 608--613
Bing-Rung Tsai and
K. G. Shin Assignment of task modules in hypercube
multicomputers with component failures
for communication efficiency . . . . . . 613--618
D. T. Harper III A multiaccess frame buffer architecture 618--622
P. Kornerup Digit-set conversions: generalizations
and applications . . . . . . . . . . . . 622--629
R. Swaminathan and
D. Veeramani Decomposition of $\{0, 1\}$-matrices . . 629--633
A. M. Tokarnia Identifying minimal shift counters: a
search technique . . . . . . . . . . . . 633--639
D. Gu and
D. J. Rosenkrantz and
S. S. Ravi Construction of check sets for
algorithm-based fault tolerance . . . . 641--650
J. Torrellas and
H. S. Lam and
J. L. Hennessy False sharing and spatial locality in
multiprocessor caches . . . . . . . . . 651--663
R. E. Kessler and
M. D. Hill and
D. A. Wood A comparison of trace-sampling
techniques for multi-megabyte caches . . 664--675
D. L. Palumbo The derivation and experimental
verification of clock synchronization
theory . . . . . . . . . . . . . . . . . 676--686
C. Thibeault and
Y. Savaria and
J.-L. Houle A fast method to evaluate the optimum
number of spares in defect-tolerant
integrated circuits . . . . . . . . . . 687--697
A. Bagchi and
S. L. Hakimi Information dissemination in distributed
systems with faulty units . . . . . . . 698--710
D. T. Lee and
C. D. Yang and
C. K. Wong On bends and distances of paths among
obstacles in two-layer interconnection
model . . . . . . . . . . . . . . . . . 711--724
M. Franklin and
K. K. Saluja Hypergraph coloring and reconfigured RAM
testing . . . . . . . . . . . . . . . . 725--736
Y.-Y. Chen and
S. J. Upadhyaya Modeling the reliability of a class of
fault-tolerant VLSI/WSI systems based on
multiple-level redundancy . . . . . . . 737--748
Y.-C. Chen and
W.-T. Chen Constant time sorting on reconfigurable
meshes . . . . . . . . . . . . . . . . . 749--751
J.-M. Muller Some characterizations of functions
computable in on-line arithmetic . . . . 752--755
D. A. Hoelzeman and
S. Bettayeb On the genus of star graphs . . . . . . 755--759
D. R. Chowdhury and
S. Basu and
I. S. Gupta and
P. P. Chaudhuri Design of CAECC --- Cellular Automata
Based Error Correcting Code . . . . . . 759--764
M. A. Heap and
M. R. Mercer Least upper bounds on OBDD sizes . . . . 764--767
C.-H. Sun and
S.-D. Wang Comments on ``Distributed algorithms for
network recognition problems'' . . . . . 768--768
Pen-Yuang Chang and
Jong-Chuang Tsay A family of efficient regular arrays for
algebraic path problem . . . . . . . . . 769--777
H. Abu-Amara and
J. Lokre Election in asynchronous complete
networks with intermittent link failures 778--788
S. M. Mahmud Performance analysis of multilevel bus
networks for hierarchical
multiprocessors . . . . . . . . . . . . 789--805
Jong Kim and
C. R. Das Hypercube communication delay with
wormhole routing . . . . . . . . . . . . 806--814
K. W. Tang and
S. A. Padubidri Diagonal and toroidal mesh networks . . 815--826
Jianli Sun and
E. Cerny and
J. Gecsei Fault tolerance in a class of sorting
networks . . . . . . . . . . . . . . . . 827--837
Chin-Liang Wang Bit-level systolic array for fast
exponentiation in $\mathrm{GF}(2^m)$ . . 838--841
P. Banerjee and
M. Peercy Design and evaluation of hardware
strategies for reconfiguring hypercubes
and meshes under faults . . . . . . . . 841--848
Sying-Jyan Wang and
N. K. Jha Algorithm-based fault tolerance for FFT
networks . . . . . . . . . . . . . . . . 849--854
Youngsong Mun and
Hee Yong Youn Performance modeling and evaluation of
circuit switching using Clos networks 854--861
T. Weller and
B. Hajek Comments on ``An optimal shortest-path
routing policy for network computers
with regular mesh-connected topologies'' 862--863
P. W. Dowd and
K. K. Bogineni and
K. A. Aly and
J. A. Perreault Addendum to ``Hierarchical scalable
photonic architectures for
high-performance processor
interconnection'' . . . . . . . . . . . 864--864
J. E. Vuillemin On Circuits and Numbers . . . . . . . . 868--879
D. S. Phatak and
I. Koren Hybrid Signed-Digit Number Systems: a
Unified Framework for Redundant Number
Representations With Bounded Carry
Propagation Chains . . . . . . . . . . . 880--891
P. Kornerup A Systolic, Linear-Array Multiplier for
a Class of Right-Shift Algorithms . . . 892--898
D. Zuras More On Squaring and Multiplying Large
Integers . . . . . . . . . . . . . . . . 899--908
M. D. Ercegovac and
T. Lang and
P. Montuschi Very-High Radix Division with Prescaling
and Selection by Rounding . . . . . . . 909--918
J. Cortadella and
T. Lang High-Radix Division and Square-Root with
Speculation . . . . . . . . . . . . . . 919--931
D. DasSarma and
D. W. Matula Measuring the Accuracy of ROM Reciprocal
Tables . . . . . . . . . . . . . . . . . 932--940
N. D. Hemkumar and
J. R. Cavallaro Redundant and On-Line CORDIC for Unitary
Transformations . . . . . . . . . . . . 941--954
Jean-Claude Bajard and
Sylvanus Kla and
Jean-Michel Muller BKM: a New Hardware Algorithm for
Complex Elementary Functions . . . . . . 955--963
M. J. Schulte and
E. E. Swartzlander, Jr. Hardware Designs for Exactly Rounded
Elementary Functions . . . . . . . . . . 964--973
D. M. Lewis Interleaved Memory Function
Interpolators with Application to an
Accurate LNS Arithmetic Unit . . . . . . 974--982
James W. Demmel and
Xiaoye Li Faster Numerical Algorithms via
Exception Handling . . . . . . . . . . . 983--992
W.-M. W. Hwu and
T. M. Conte The susceptibility of programs to
context switching . . . . . . . . . . . 994--1003
Nian-Feng Tzeng Reliable butterfly distributed-memory
multiprocessors . . . . . . . . . . . . 1004--1013
Tein-Hsiang Lin and
K. G. Shin An optimal retry policy based on fault
classification . . . . . . . . . . . . . 1014--1025
A. Arora and
M. Gouda Distributed reset . . . . . . . . . . . 1026--1038
M. Balakrishnan and
A. Reibman Reliability models for fault-tolerant
private network applications . . . . . . 1039--1053
Dajin Wang Diagnosability of enhanced hypercubes 1054--1061
J. Naganuma and
T. Ogura A highly OR-parallel inference machine
(Multi-ASCA) and its performance
evaluation: an architecture and its load
balancing algorithms . . . . . . . . . . 1062--1075
Chao-Ju Hou and
K. G. Shin Load sharing with consideration of
future task arrivals in heterogeneous
distributed real-time systems . . . . . 1076--1090
D. Paik and
S. Reddy and
S. Sahni Deleting vertices to bound path length 1091--1096
Wen-Ben Jone and
Cheng-Juei Wu Multiple fault detection in parity
checkers . . . . . . . . . . . . . . . . 1096--1099
I. Pomeranz and
S. M. Reddy On the role of hardware reset in
synchronous sequential circuit test
generation . . . . . . . . . . . . . . . 1100--1105
A. Olson and
K. G. Shin Probabilistic clock synchronization in
large distributed systems . . . . . . . 1106--1112
F. N. Sibai and
N. K. Sharma and
A. A. Abonamah Comparison of reconfiguration schemes
for the C2SC MIN operating in the
broadcast mode . . . . . . . . . . . . . 1112--1119
R. Singh Bajwa and
R. M. Owens and
M. J. Irwin Area time trade-offs in micro-grain VLSI
array architectures . . . . . . . . . . 1121--1128
L. Kurian and
P. T. Hulina and
L. D. Coraor Memory latency effects in decoupled
architectures . . . . . . . . . . . . . 1129--1139
G. D. Intrater and
I. Y. Spillinger Performance evaluation of a decoded
instruction cache for variable
instruction length computers . . . . . . 1140--1150
K. G. Shin and
Hagbae Kim A time redundancy approach to TMR
failures using fault-state likelihoods 1151--1162
D. K. Pradhan and
N. H. Vaidya Roll-forward checkpointing scheme: a
novel fault-tolerant architecture . . . 1163--1174
M. Harrington and
A. K. Somani Synchronizing hypercube networks in the
presence of faults . . . . . . . . . . . 1175--1183
S. Bataineh and
Te-Yu Hsiung and
T. G. Robertazzi Closed form solutions for bus and tree
networks of processors load sharing a
divisible job . . . . . . . . . . . . . 1184--1196
J. Gergov and
C. Meinel Efficient Boolean manipulation with
OBDD's can be extended to FBDD's . . . . 1197--1209
J. Bruck and
R. Cypher and
D. Soroker Embedding cube-connected cycles graphs
into faulty hypercubes . . . . . . . . . 1210--1220
D. K. Ray-Chaudhuri and
N. M. Singhi and
S. Sanyal and
P. S. Subramanian Theory and design of t-unidirectional
error-correcting and d-unidirectional
error-detecting code . . . . . . . . . . 1221--1226
R. F. Tinder and
R. I. Klaus and
J. A. Snodderley High-speed microprogrammable
asynchronous controller modules . . . . 1226--1232
D. P.-K. Lun and
Wan-Chi Siu A pipeline design for the realization of
the prime factor algorithm using the
extended diagonal structure . . . . . . 1232--1237
J. Q. Wang and
P. K. Lala Partially strongly fault secure and
partially strongly code disjoint
$1$-out-of-$3$ code checker . . . . . . 1238--1240
R. K. Das and
K. Mukhopadhyaya and
B. P. Sinha A new family of bridged and twisted
hypercubes . . . . . . . . . . . . . . . 1240--1247
L. R. Welch A Parallel Virtual Machine for Programs
Composed of Abstract Data Types . . . . 1249--1261
I. Wegener The size of reduced OBDD's and optimal
read-once branching programs for almost
all Boolean functions . . . . . . . . . 1262--1269
T.-Y. Feng and
S.-W. Seo A new routing algorithm for a class of
rearrangeable networks . . . . . . . . . 1270--1280
A. Dan and
P. S. Yu and
D. M. Dias Performance modelling and comparisons of
global shared buffer management policies
in a cluster environment . . . . . . . . 1281--1297
N. S. V. Rao and
S. Toida On polynomial-time testable
combinational circuits . . . . . . . . . 1298--1308
H. F. Jordan and
D. Lee and
K. Y. Lee and
S. V. Ramanan Serial array time slot interchangers and
optical implementations . . . . . . . . 1309--1318
S. Lee and
M. Lu New self-routing permutation networks 1319--1323
B. E. Segee and
M. J. Carter Comparative fault tolerance of parallel
distributed processing networks . . . . 1323--1329
B. Kosko Fuzzy systems as universal approximators 1329--1333
J. Blazewicz and
D. P. Bovet and
J. Brzezinski and
G. Gambosi and
M. Talamo Optimal centralized algorithms for
store-and-forward deadlock avoidance . . 1333--1338
H. Hahn and
D. Timmermann and
B. J. Hosticka and
B. Rix A unified and division-free CORDIC
argument reduction method with unlimited
convergence domain including inverse
hyperbolic functions . . . . . . . . . . 1339--1344
S. Nandi and
B. K. Kar and
P. Pal Chaudhuri Theory and applications of cellular
automata in cryptography . . . . . . . . 1346--1357
R. I. Greenberg The fat-pyramid and universal parallel
computation independent of wire delay 1358--1364
A. D. Friedman A functional approach to efficient fault
detection in iterative logic arrays . . 1365--1375
R. Cypher and
L. Gravano Storage-efficient, deadlock-free packet
routing algorithms for torus networks 1376--1385
S. Konstantinidou and
L. Snyder The Chaos router . . . . . . . . . . . . 1386--1397
R. Leveugle and
Z. Koren and
I. Koren and
G. Saucier and
N. Wehn The Hyeti defect tolerant
microprocessor: a practical experiment
and its cost-effectiveness analysis . . 1398--1406
M. Spuri and
J. A. Stankovic How to integrate precedence constraints
and shared resources in real-time
scheduling . . . . . . . . . . . . . . . 1407--1412
J. Lopez and
E. L. Zapata Unified architecture for divide and
conquer based tridiagonal system solvers 1413--1425
S. A. Ali and
G. R. Redinbo Tight lower bounds on the detection
probabilities of single faults at
internal signal lines in combinational
circuits . . . . . . . . . . . . . . . . 1426--1428
Ming-Bo Lin and
A. Yavuz Oruc Constant time inner product and matrix
computations on permutation network
processors . . . . . . . . . . . . . . . 1429--1434
Nian-Feng Tzeng and
Hsing-Lung Chen Structural and tree embedding aspects of
incomplete hypercubes . . . . . . . . . 1434--1439
N. Das and
B. B. Bhattacharya and
J. Dattagupta Hierarchical classification of
permutation classes in multistage
interconnection networks . . . . . . . . 1439--1444
P. Ienne and
M. A. Viredaz Bit-serial multipliers and squarers . . 1445--1450
F. K. Hwang and
W. Najjar and
J. L. Gaudiot Comments on ``Network resilience: a
measure of network fault tolerance''
[and reply] . . . . . . . . . . . . . . 1451--1453
G. Ciardo and
C. Lindemann Comments on ``Analysis of
self-stabilizing clock synchronization
by means of stochastic Petri nets'' . . 1453--1456
Shyan-Ming Yuan and
Her-Kun Chang Comments on ``Availability of
$k$-Coterie'' . . . . . . . . . . . . . 1457--1457
A. Takach and
W. Wolf An automaton model for scheduling
constraints in synchronous machines . . 1--12
C. H. Lin and
C. C. Chang and
R. C. T. Lee A new public-key cipher system based
upon the Diophantine equations . . . . . 13--19
M. Woodside and
J. E. Neilson and
D. C. Petriu and
S. Majumdar The stochastic rendezvous network model
for performance of synchronous
client-server-like distributed software 20--34
Chung-Chi Jim Li and
Shyh-Kwei Chen and
W. K. Fuchs and
W.-M. W. Hwu Compiler-based multiple instruction
retry . . . . . . . . . . . . . . . . . 35--46
S. Lennart Johnsson and
Ching-Tien Ho On the conversion between binary code
and binary-reflected Gray code on binary
cubes . . . . . . . . . . . . . . . . . 47--53
P. J. Windley Formal modeling and verification of
microprocessors . . . . . . . . . . . . 54--72
J. K. Strosnider and
J. P. Lehoczky and
Lui Sha The deferrable server algorithm for
enhanced aperiodic responsiveness in
hard real-time environments . . . . . . 73--91
C. Fricker On memory contention problems in vector
multiprocessors . . . . . . . . . . . . 92--105
Chao Chi Tong and
Chuan-Lin Wu Routing in a three-dimensional chip . . 106--117
K. Iwamura and
Y. Dohi and
H. Imai A design of Reed--Solomon decoder with
systolic-array structure . . . . . . . . 118--122
B. L. Menezes and
U. Bakhru New bounds on the reliability of
augmented shuffle-exchange networks . . 123--129
Shuenn-Shyang Wang and
Ming-Yuan Shau Single residue error correction based on
K-term $m_j$-projection . . . . . . . . 129--131
R. Mazzaferri and
T. M. Murray The Connection Network class for Fault
Tolerant Meshes . . . . . . . . . . . . 131--138
I. Pomeranz and
S. M. Reddy Aliasing computation using fault
simulation with fault dropping . . . . . 139--144
P. Montuschi and
L. Ciminiera A remark on ``Reducing iteration time
when result digit is zero for radix-$2$
SRT division and square root with
redundant remainders'' . . . . . . . . . 144--146
N. H. Vaidya and
D. K. Pradhan Degradable Byzantine agreement . . . . . 146--150
J. Bruck and
R. Cypher and
Ching-Tien Ho Wildcard dimensions, coding theory and
fault-tolerant meshes and hypercubes . . 150--155
D. Das and
K. Mukhopadhyaya and
B. P. Sinha Implementation of four common functions
on an LNS co-processor . . . . . . . . . 155--161
N. R. Saxena and
C.-W. D. Chang and
K. Dawallu and
J. Kohli and
P. Helland Fault-tolerant features in the HaL
memory management unit . . . . . . . . . 170--180
S. Poledna Tolerating sensor timing faults in
highly responsive hard real-time systems 181--191
M. Blaum and
J. Brady and
J. Bruck and
Jai Menon EVENODD: an efficient scheme for
tolerating double disk failures in RAID
architectures . . . . . . . . . . . . . 192--202
R. D. Schlichting and
V. T. Thomas Programming language support for writing
fault-tolerant distributed software . . 203--212
W. Ke and
P. R. Menon Synthesis of delay-verifiable
combinational circuits . . . . . . . . . 213--222
S. Hellebrand and
J. Rajski and
S. Tarnick and
S. Venkataraman and
B. Courtois Built-in test for circuits with scan
based on reseeding of
multiple-polynomial linear feedback
shift registers . . . . . . . . . . . . 223--233
A. Majumdar and
S. B. K. Vrudhula Fault coverage and test length
estimation for random pattern testing 234--247
G. A. Kanawati and
N. A. Kanawati and
J. A. Abraham FERRARI: a flexible software-based fault
and error injection system . . . . . . . 248--260
D. Powell and
E. Martins and
J. Arlat and
Y. Crouzet Estimators for fault tolerance coverage
evaluation . . . . . . . . . . . . . . . 261--274
S. Rai Evaluating FTRE's for dependability
measures in fault tolerant systems . . . 275--285
G. Rubino and
B. Sericola Interval availability analysis using
denumerable Markov processes:
application to multiprocessor subject to
breakdowns and repair . . . . . . . . . 286--291
Fuxing Wang and
K. Ramamritham and
J. A. Stankovic Determining redundancy levels for fault
tolerant real-time systems . . . . . . . 292--301
D. Boley and
G. H. Golub and
S. Makar and
N. Saxena and
E. J. McCluskey Floating Point Fault Tolerance with
Backward Error Assertions . . . . . . . 302--311
S. Rangarajan and
A. T. Dahbura and
E. A. Ziegler A distributed system-level diagnosis
algorithm for arbitrary network
topologies . . . . . . . . . . . . . . . 312--334
I. Pomeranz and
S. M. Reddy On fault simulation for synchronous
sequential circuits . . . . . . . . . . 335--340
Jie Xu and
Shi-Ze Huang Sequentially $t$-diagnosable systems: a
characterization and its applications 340--345
Hong-Yi Tzeng and
Kai-Yeung Siu Message-optimal protocols for
fault-tolerant broadcasts/multicasts in
distributed systems with crash failures 346--352
P. P. Chang and
D. M. Lavery and
S. A. Mahlke and
W. Y. Chen and
W.-M. W. Hwu The importance of prepass code
scheduling for superscalar and
superpipelined processors . . . . . . . 353--370
D. R. Chowdhury and
I. S. Gupta and
P. P. Chaudhuri CA-based byte error-correcting code . . 371--382
M. G. Karpovsky and
T. D. Roziner and
C. Moraga Fault detection in multiprocessor
systems and array processors . . . . . . 383--393
S. Akyurek and
K. Salem Management of partially safe buffers . . 394--407
N. S. Bowen and
D. K. Pradhan A fault tolerant hybrid memory structure
and memory management algorithms . . . . 408--418
A. Merchant and
P. S. Yu Analytic modeling and comparisons of
striping strategies for replicated disk
arrays . . . . . . . . . . . . . . . . . 419--433
D. Bhattacharya and
P. Agrawal and
V. D. Agrawal Test generation for path delay faults
using binary decision diagrams . . . . . 434--447
H. Cam and
J. A. B. Fortes A fast VLSI-efficient self-routing
permutation network . . . . . . . . . . 448--453
W. F. Wong and
E. Goto Fast evaluation of the elementary
functions in single precision . . . . . 453--457
D. C. McCrackin Practical delay enforced multistream
(DEMUS) control of deeply pipelined
processors . . . . . . . . . . . . . . . 458--462
S. Rangarajan and
Y. Huang and
S. K. Tripathi Computing reliability intervals for
$k$-resilient protocols . . . . . . . . 462--466
Wei-Kuan Shih and
J. W. S. Liu Algorithms for scheduling imprecise
computations with timing constraints to
minimize maximum error . . . . . . . . . 466--471
R. Gerber and
W. Pugh and
M. Saksena Parametric dispatching of hard real-time
tasks . . . . . . . . . . . . . . . . . 471--479
P. P. Chang and
N. F. Warter and
S. A. Mahlke and
W. Y. Chen and
W. W. Hwu Three architectural models for
compiler-controlled speculative
execution . . . . . . . . . . . . . . . 481--494
P. E. Dunne and
P. H. Leng and
G. F. Nwana On the complexity of Boolean functions
computed by lazy oracles . . . . . . . . 495--502
Jyh-Charn Liu and
K. G. Shin Efficient implementation techniques for
gracefully degradable multiprocessor
systems . . . . . . . . . . . . . . . . 503--517
K. A. Robbins and
S. Robbins Buffered banks in multiprocessor systems 518--530
V. E. Taylor and
A. Ranade and
D. G. Messerschmitt SPAR: a new architecture for large
finite element computations . . . . . . 531--545
C. Faloutsos and
R. Ng and
T. Sellis Flexible and adaptable buffer management
techniques for database management
systems . . . . . . . . . . . . . . . . 546--560
P. B. Goes and
U. Sumita Stochastic models for performance
analysis of database recovery control 561--576
Yao Li and
C. M. Woodside Complete decomposition of stochastic
Petri nets representing generalized
service networks . . . . . . . . . . . . 577--592
L. Auletta and
A. A. Rescigno and
V. Scarano Embedding graphs onto the Supercube . . 593--597
M. A. Lopez and
R. Thurimella On computing connected components of
line segments . . . . . . . . . . . . . 597--601
Yuen-Hsien Tseng and
Ja-Ling Wu On a constant-time, low-complexity
winner-take-all neural network . . . . . 601--604
Xiaojun Shen and
Mao Xu and
Xiangzu Wang An optimal algorithm for permutation
admissibility to multistage
interconnection networks . . . . . . . . 604--608
Tien-Fu Chen and
Jean-Loup Baer Effective hardware-based data
prefetching for high-performance
processors . . . . . . . . . . . . . . . 609--623
E. D. Di Claudio and
F. Piazza and
G. Orlandi Fast combinatorial RNS processors for
DSP applications . . . . . . . . . . . . 624--633
M. Valero and
T. Lang and
M. Peiron and
E. Ayguade Conflict-free access for streams in
multimodule memories . . . . . . . . . . 634--646
P. Cull and
S. M. Larson The Möbius cubes . . . . . . . . . . . . 647--659
M. Blaum and
J. Bruck Delay-insensitive pipelined
communication on parallel buses . . . . 660--668
K. G. Shin and
Yi-Chieh Chang A coordinated location policy for load
sharing in hypercube-connected
multicomputers . . . . . . . . . . . . . 669--682
Jong-Chuang Tsay and
Pen-Yuang Chang Design of space-optimal regular arrays
for algorithms with linear schedules . . 683--694
H. Cam and
J. A. B. Fortes Frames: a simple characterization of
permutations realized by frequently used
networks . . . . . . . . . . . . . . . . 695--697
R. Nair Optimal 2-bit branch predictors . . . . 698--702
Jie Wu Safety levels --- an efficient mechanism
for achieving reliable broadcasting in
hypercubes . . . . . . . . . . . . . . . 702--706
D. Cohen-Or and
A. Kaufman A $3$D skewing and de-skewing scheme for
conflict-free access to rays in volume
rendering . . . . . . . . . . . . . . . 707--710
N. H. Vaidya Unidirectional bit/byte error control 710--714
Xiaojun Shen Optimal realization of any BPC
permutation on $K$-extra-stage Omega
networks . . . . . . . . . . . . . . . . 714--719
C. E. Wu and
Yarsun Hsu and
Yew-Huey Liu Efficient stack simulation for
set-associative virtual address caches
with real tags . . . . . . . . . . . . . 719--723
C. Thibeault and
Y. Savaria and
J. L. Houle Equivalence proofs of some yield
modeling methods for defect-tolerant
integrated circuits . . . . . . . . . . 724--728
Sung-Ming Yen and
Chi-Sung Laih Improved digital signature algorithm . . 729--730
Jae Young Lee and
Hee Yong Youn and
A. D. Singh Adaptive unanimous voting (UV) scheme
for distributed self-diagnosis . . . . . 730--735
J. Wu and
R. Das and
J. Saltz and
H. Berryman and
S. Hiranandan Distributed memory compiler design for
sparse problems . . . . . . . . . . . . 737--753
S. H. Unger Hazards, critical races, and
metastability . . . . . . . . . . . . . 754--768
Q. M. Malluhi and
M. A. Bayoumi and
T. R. N. Rao Efficient mapping of ANNs on hypercube
massively parallel machines . . . . . . 769--779
S. Pilarski and
K. J. Wiebe Counter-based compaction: Delay and
stuck-open faults . . . . . . . . . . . 780--791
I. Pomeranz and
S. M. Reddy INCREDYBLE: a new search strategy for
design automation problems with
applications to testing . . . . . . . . 792--804
S. Boubezari and
B. Kaminska A deterministic built-in self-test
generator based on cellular automata
structures . . . . . . . . . . . . . . . 805--816
Yuejian Wu and
A. Ivanov Single-reference multiple intermediate
signature (SREMIS) analysis for BIST . . 817--825
H. R. Srinivas and
K. K. Parhi A fast radix-4 division algorithm and
its architecture . . . . . . . . . . . . 826--831
G. F. Sullivan and
D. S. Wilson and
G. M. Masson Certification of computational results 833--847
R. V. Boppana and
S. Chalasani Fault-tolerant wormhole routing
algorithms for mesh networks . . . . . . 848--864
S. Tridandapani and
A. K. Somani and
U. R. Sandadi Low overhead multiprocessor allocation
strategies exploiting system spare
capacity for fault detection and
location . . . . . . . . . . . . . . . . 865--877
L. A. Barroso and
M. Dubois Performance evaluation of the slotted
ring multiprocessor . . . . . . . . . . 878--890
Y. Shintani and
K. Inoue and
E. Kamada and
T. Shonai A performance and cost analysis of
applying superscalar method to mainframe
computers . . . . . . . . . . . . . . . 891--902
Y. G. Saab A fast and robust network bisection
algorithm . . . . . . . . . . . . . . . 903--913
M. J. Atallah and
D. Z. Chen Optimal parallel hypercube algorithms
for polygon problems . . . . . . . . . . 914--922
P. Kulasinghe and
S. Bettayeb Embedding binary trees into crossed
cubes . . . . . . . . . . . . . . . . . 923--929
C. J. Zarowski Parallel implementation of the Schur
Berlekamp--Massey algorithm on a
linearly connected processor array . . . 930--932
N. Burgess and
T. Williams Choices of operand truncation in the SRT
division algorithm . . . . . . . . . . . 933--937
M. A. Hasan and
V. K. Bhargava Architecture for a low complexity
rate-adaptive Reed--Solomon encoder . . 938--942
E. Dekker and
L. Dekker Parallel minimal norm method for
tridiagonal linear systems . . . . . . . 942--946
S. Paul and
J. Gotze and
M. Sauer Error analysis of CORDIC-based Jacobi
algorithms . . . . . . . . . . . . . . . 947--951
Y. Chang and
L. N. Bhuyan A combinatorial analysis of subcube
reliability in hypercubes . . . . . . . 952--956
S.-M. Yen and
C.-S. Laih Improved digital signature suitable for
batch verification . . . . . . . . . . . 957--959
Zhongde Wang and
G. A. Jullien and
W. C. Miller A new design technique for column
compression multipliers . . . . . . . . 962--970
S. E. McQuillan and
J. V. McCanny A systematic methodology for the design
of high performance recursive digital
filters . . . . . . . . . . . . . . . . 971--982
Markus A. Hitz and
Erich Kaltofen Integer division in residue number
systems . . . . . . . . . . . . . . . . 983--989
Shen-Fu Hsiao and
J.-M. Delosme Householder CORDIC algorithms . . . . . 990--1001
Jun-Woo Kang and
Chin-Long Wey and
P. D. Fisher Application of bipartite graphs for
achieving race-free state assignments 1002--1011
Z. Zilic and
Z. G. Vranesic A multiple-valued Reed--Muller transform
for incompletely specified functions . . 1012--1020
B. Bose and
B. Broeg and
Younggeun Kwon and
Y. Ashir Lee distance and topological properties
of $k$-ary $n$-cubes . . . . . . . . . . 1021--1030
Yao Li and
C. M. Woodside Complete decomposition of stochastic
Petri nets representing generalized
service networks . . . . . . . . . . . . 1031--1046
G. A. De Biase and
C. Ferrone and
A. Massini An $O(\log_2 N)$ depth asymptotically
nonblocking . . . . . . . . . . . . . . 1047--1051
S. W. Turner and
L. M. Ni and
B. H. C. Cheng Contention-free $2$D-mesh cluster
allocation in hypercubes . . . . . . . . 1051--1055
V. V. Dimakopoulos and
G. Sourtziotis and
A. Paschalis and
D. Nikolos On TSC checkers for $m$-out-of-n codes 1055--1059
P. T. Gaughan and
S. Yalamanchili A performance model of pipelined $k$-ary
$n$-cubes . . . . . . . . . . . . . . . 1059--1063
Burton S. Kaliski, Jr. The Montgomery inverse and its
applications . . . . . . . . . . . . . . 1064--1065
A. El-Amawy and
Yi Chang Tseng Maximum performance pipelines with
switchable reservation tables . . . . . 1066--1069
P. Mohapatra and
C. R. Das On dependability evaluation of
mesh-connected processors . . . . . . . 1073--1084
Tsang-Ling Sheu and
Woei Lin and
C. R. Das Distributed fault diagnosis in
multistage network-based multiprocessors 1085--1095
N. J. Alewine and
Shyh-Kwei Chen and
W. Kent Fuchs and
W.-M. W. Hwu Compiler-assisted multiple instruction
rollback recovery using a read buffer 1096--1107
Y. Chang and
L. N. Bhuyan Subcube fault tolerance in hypercube
multiprocessors . . . . . . . . . . . . 1108--1120
J. C. Smith and
F. J. Taylor A fault-tolerant CEQRNS processing
element for linear systolic array DSP
applications . . . . . . . . . . . . . . 1121--1130
H. M. Heys and
S. E. Tavares Avalanche characteristics of
substitution-permutation encryption
networks . . . . . . . . . . . . . . . . 1131--1139
D. I. Katcher and
S. S. Sathaye and
J. K. Strosnider Fixed priority scheduling with limited
priority levels . . . . . . . . . . . . 1140--1144
Xiaojun Shen An optimal $O(N \lg N)$ algorithm for
permutation admissibility to extra-stage
cube-type networks . . . . . . . . . . . 1144--1149
L. O'Connor A differential cryptanalysis of
tree-structured substitution-permutation
networks . . . . . . . . . . . . . . . . 1150--1152
C. S. Raghavendra and
Pei-Ji Yang and
Sing-Ban Tien Free dimensions --- an effective
approach to achieving fault tolerance in
hypercubes . . . . . . . . . . . . . . . 1152--1157
Choong Gun Oh and
Hee Yong Youn and
V. K. Raj An efficient algorithm-based concurrent
error detection for FFT networks . . . . 1157--1162
Jie Wu and
Kejun Yao A limited-global-information-based
multicasting scheme for faulty
hypercubes . . . . . . . . . . . . . . . 1162--1167
Yuanyuan Yang and
G. M. Masson Broadcast ring sandwich networks . . . . 1169--1180
Wei-Kuo Liao and
Chung-Ta King Valved routing: efficient flow control
for adaptive nonminimal routing in
interconnection networks . . . . . . . . 1181--1193
T. Johnson Characterizing the performance of
algorithms for lock-free objects . . . . 1194--1207
F. T. Hady and
B. L. Menezes The performance of crossbar-based binary
hypercubes . . . . . . . . . . . . . . . 1208--1215
P. Semal Refinable bounds for large Markov chains 1216--1222
R. H. Saavedra and
A. J. Smith Measuring cache and TLB performance and
their effect on benchmark runtimes . . . 1223--1235
V. Catania and
A. Puliafito and
S. Riccobene and
L. Vita Design and performance analysis of a
disk array system . . . . . . . . . . . 1236--1247
P. Kulasinghe and
A. El-Amawy On the complexity of optimal bused
interconnections . . . . . . . . . . . . 1248--1251
M. Soufi and
Y. Savaria and
F. Darlay and
B. Kaminska Producing reliable initialization and
test of sequential circuits with
pseudorandom vectors . . . . . . . . . . 1251--1256
K. M. Sammut and
S. R. Jones Arithmetic unit design for neural
accelerators: cost performance issues 1256--1260
D. R. Chowdhury and
I. S. Gupta and
P. P. Chaudhuri A low-cost high-capacity associative
memory design using cellular automata 1260--1264
Shou-Ping Feng and
T. Fujiwara and
T. Kasami and
K. Iwasaki On the maximum value of aliasing
probabilities for single input signature
registers . . . . . . . . . . . . . . . 1265--1274
M. Kopec Can nonlinear compactors be better than
linear ones? . . . . . . . . . . . . . . 1275--1282
M. Lempel and
S. K. Gupta Zero-aliasing for modeled faults . . . . 1283--1295
K. Roy and
S. Nag On routability for FPGAs under faulty
conditions . . . . . . . . . . . . . . . 1296--1305
H. Hulgaard and
S. M. Burns and
T. Amon and
G. Borriello An algorithm for exact bounds on the
time separation of events in concurrent
systems . . . . . . . . . . . . . . . . 1306--1317
T. Haniotakis and
A. Paschalis and
D. Nikolos Efficient totally self-checking checkers
for a class of Borden codes . . . . . . 1318--1322
B. Olstad and
F. Manne Efficient partitioning of sequences . . 1322--1326
D. M. Mandelbaum Division using a logarithmic-exponential
transform to form a short reciprocal . . 1326--1330
A. G. Skolleborg and
J. H. Weber Construction of systematic codes for
unidirectional error control . . . . . . 1331--1334
Kuo-Liang Chung and
Wen-Ming Yan Fast vectorization for calculating a
moving sum . . . . . . . . . . . . . . . 1335--1337
T. Ishikawa Hypercube multiprocessors with bus
connections for improving communication
performance . . . . . . . . . . . . . . 1338--1344
Ching Yu Hung and
B. Parhami Error analysis of approximate
Chinese-Remainder-Theorem decoding . . . 1344--1348
Roger Alan Smith A Continued-Fraction Analysis of
Trigonometric Argument Reduction . . . . 1348--1351
B. Vinnakota Implementing multiplication with split
read-only memory . . . . . . . . . . . . 1352--1356
Gihyan Jung Comments on ``Some additions to solution
of switching equations based on a
tabular algebra'' . . . . . . . . . . . 1357--1358
R. Sisto and
A. Valenzano Mapping Petri nets with inhibitor arcs
onto basic LOTOS behavior expressions 1361--1370
J. C. S. Lui and
R. R. Muntz and
D. Towsley Bounding the mean response time of the
minimum expected delay routing policy:
an algorithmic approach . . . . . . . . 1371--1382
B. Fagin and
A. Mital The performance of counter- and
correlation-based schemes for branch
target buffers . . . . . . . . . . . . . 1383--1393
Wei-Bo Gong and
Hong Yang Rational approximants for some
performance analysis problems . . . . . 1394--1404
K. G. Shin and
Yi-Chieh Chang A reservation-based algorithm for
scheduling both periodic and aperiodic
real-time tasks . . . . . . . . . . . . 1405--1419
M. Hamdaoui and
P. Ramanathan Deferring real-time traffic for improved
non-real-time communication in FDDI
networks . . . . . . . . . . . . . . . . 1420--1428
A. Burchard and
J. Liebeherr and
Yingfeng Oh and
S. H. Son New strategies for assigning real-time
tasks to multiprocessor systems . . . . 1429--1442
M. Hamdaoui and
P. Ramanathan A dynamic priority assignment technique
for streams with $(m, k)$-firm deadlines 1443--1451
K. Mukhopadhyaya and
B. P. Sinha Fault-tolerant routing in distributed
loop networks . . . . . . . . . . . . . 1452--1456
M. Valencia and
M. J. Bellido and
J. L. Huertas and
A. J. Acosta and
S. Sanchez-Solano Modular asynchronous arbiter insensitive
to metastability . . . . . . . . . . . . 1456--1461
K. W. Tang and
B. W. Arden Class-congruence property and two-phase
routing of Borel Cayley graphs . . . . . 1462--1468
F. K. Hwang and
P. E. Wright Survival reliability of some double-loop
networks and chordal rings . . . . . . . 1468--1471
R. S. Katti and
T. A. Gulliver and
V. K. Bhargava Comments on ``A systematic $(16, 8)$
code for correcting double errors and
detecting triple-adjacent errors'' [and
reply] . . . . . . . . . . . . . . . . . 1472--1474
S. Nandi and
P. Pal Chaudhuri Analysis of periodic and intermediate
boundary 90/150 cellular automata . . . 1--12
Rajendra S. Katti A new residue arithmetic error
correction scheme . . . . . . . . . . . 13--19
I. Pomeranz and
S. M. Reddy On removing redundancies from
synchronous sequential circuits with
synchronizing sequences . . . . . . . . 20--32
Chien-Chung Tsai and
M. Marek-Sadowska Generalized Reed--Muller forms as a tool
to detect symmetries . . . . . . . . . . 33--40
J. D. Golic Linear models for keystream generators 41--49
I. Pomeranz and
S. M. Reddy On the number of tests to detect all
path delay faults in combinational logic
circuits . . . . . . . . . . . . . . . . 50--62
S. K. Gupta and
D. K. Pradhan Utilization of on-line (concurrent)
checkers during built-in self-test and
vice versa . . . . . . . . . . . . . . . 63--73
D. Kagaris and
S. Tragoudas Retiming-based partial scan . . . . . . 74--87
O. C.-S. Choy and
Lap-Kong Chan and
R. Chan and
C. F. Chan Test generation with dynamic probe
points in high observability testing
environment . . . . . . . . . . . . . . 88--96
Qing Hu and
Xiaojun Shen and
Weifa Liang Optimally routing LC permutations on
$k$-extra-stage cube-type networks . . . 97--103
Chi-Sung Laih and
Ching-Nung Yang On the analysis and design of group
theoretical t-syEC/AUED codes . . . . . 103--108
M. D. Smith and
P. Mazumder Generation of minimal vertex covers for
row/column allocation in self-repairable
arrays . . . . . . . . . . . . . . . . . 109--115
Suresh Rai and
Weian Deng Hyperneural network --- an efficient
model for test generation in digital
circuits . . . . . . . . . . . . . . . . 115--121
A. Orailoglu and
R. Karri Automatic synthesis of self-recovering
VLSI systems . . . . . . . . . . . . . . 131--142
Ge-Ming Chiu and
Shui-Pao Wu A fault-tolerant routing strategy in
hypercube multicomputers . . . . . . . . 143--155
J. Opatrny and
D. Sotteau and
N. Srinivasan and
K. Thulasiraman DCC linear congruential graphs: a new
class of interconnection networks . . . 156--164
Y. Atar and
J. Naor and
R. Rom Routing strategies for fast networks . . 165--173
P. Fragopoulou and
S. G. Akl Edge-disjoint spanning trees on the star
network with applications to fault
tolerance . . . . . . . . . . . . . . . 174--185
S. Bettayeb and
Bin Cong and
M. Girou and
I. H. Sudborough Embedding star networks into hypercubes 186--194
B. J. Oommen and
E. V. de St. Croix Graph partitioning using learning
automata . . . . . . . . . . . . . . . . 195--208
Jun Gu and
Qian-Ping Gu and
Ding-Zhu Du Convergence properties of optimization
algorithms for the SAT problem . . . . . 209--219
S. H. Bokhari Multiphase complete exchange: a
theoretical analysis . . . . . . . . . . 220--229
S. Latifi and
P. K. Srimani Transposition networks as a class of
fault-tolerant robust networks . . . . . 230--238
A.-R. Chowdhury and
P. Banerjee A new error analysis based method for
tolerance computation for
algorithm-based checks . . . . . . . . . 238--243
R. Katti A note on SEC/AUED codes . . . . . . . . 244--246
Yung-Te Lai and
M. Pedram and
S. B. K. Vrudhula Formal verification using edge-valued
binary decision diagrams . . . . . . . . 247--255
Chih-Ang Chen and
S. K. Gupta BIST test pattern generators for
two-pattern testing-theory and design
algorithms . . . . . . . . . . . . . . . 257--269
K. Iwasaki and
S. Nakamura Aliasing error for a mask ROM built-in
self-test . . . . . . . . . . . . . . . 270--277
Meng-Chou Chang and
Feipei Lai Efficient exploitation of
instruction-level parallelism for
superscalar processors by the conjugate
register file scheme . . . . . . . . . . 278--293
V. G. Oklobdzija and
D. Villeger and
S. S. Liu A method for speed optimized partial
product reduction and generation of fast
parallel multipliers using an
algorithmic approach . . . . . . . . . . 294--306
H. Dawid and
H. Meyr The differential CORDIC algorithm:
Constant scale factor redundant
implementation without correcting
iterations . . . . . . . . . . . . . . . 307--318
S. T. J. Fenn and
M. Benaissa and
D. Taylor $\mathrm{GF}(2^m)$ multiplication and
division over the dual basis . . . . . . 319--327
V. Kantabutra On hardware for computing exponential
and trigonometric functions . . . . . . 328--339
A. De Gloria and
M. Olivieri Statistical carry lookahead adders . . . 340--347
L. Dadda and
V. Piuri Pipelined adders . . . . . . . . . . . . 348--356
J. M. Chang and
E. F. Gehringer A high performance memory allocator for
object-oriented systems . . . . . . . . 357--366
A. Merchant and
P. S. Yu Analytic modeling of clustered RAID with
mapping based on nearly random
permutation . . . . . . . . . . . . . . 367--373
Chao-Ju Hou and
K. G. Shin Determination of an optimal retry time
in multiple-module computing systems . . 374--379
S. Kundu and
E. S. Sogomonyan and
M. Goessel and
S. Tarnick Self-checking comparator with one
periodic output . . . . . . . . . . . . 379--380
M. Knor A note on radially Moore digraphs . . . 381--382
Jien-Chung Lo and
S. Thanawastien and
T. R. N. Rao Correction to ``Berger Check Prediction
for Array Multipliers and Array
Dividers'' . . . . . . . . . . . . . . . 383--383
Manuel Blum and
H. Wasserman Reflections on the Pentium Division Bug 385--393
A. Roy-Chowdhury and
N. Bellas and
P. Banerjee Algorithm-based error-detection schemes
for iterative solution of partial
differential equations . . . . . . . . . 394--407
S. Dutt and
F. T. Assaad Mantissa-preserving operations and
robust algorithm based fault tolerance
for matrix computations . . . . . . . . 408--424
Jan-Lung Sung and
G. R. Redinbo Algorithm based fault tolerant synthesis
for linear operations . . . . . . . . . 425--438
M. H. Azadmanesh and
R. M. Kieckhafer New hybrid fault models for asynchronous
approximate agreement . . . . . . . . . 439--449
Jien-Chung Lo and
E. Fujiwara Probability to achieve TSC goal . . . . 450--460
S. J. Piestrak Design of self-testing checkers for
Borden codes . . . . . . . . . . . . . . 461--469
S. Tragoudas Min-cut partitioning on underlying tree
and graph structures . . . . . . . . . . 470--474
N. Bagherzadeh and
M. Dowd and
N. Nassif Embedding an arbitrary binary tree into
the star graph . . . . . . . . . . . . . 475--481
J. D. Golic and
S. V. Petrovic Correlation attacks on clock-controlled
shift registers in keystream generators 482--486
S. Chattopadhyay and
S. Roy and
P. P. Chaudhuri Synthesis of highly testable
fixed-polarity AND--XOR canonical
networks --- a genetic algorithm-based
approach . . . . . . . . . . . . . . . . 487--490
H. Nabli and
B. Sericola Performability analysis: a new algorithm 491--494
C. S. Raghavendra and
M. A. Sridhar Global commutative and associative
reduction operations in faulty SIMD
hypercubes . . . . . . . . . . . . . . . 495--498
V. S. S. Nair and
J. A. Abraham and
P. Banerjee Efficient techniques for the analysis of
algorithm-based fault tolerance (ABFT)
schemes . . . . . . . . . . . . . . . . 499--503
N. H. Vaidya Comparison of duplex and triplex memory
reliability . . . . . . . . . . . . . . 503--507
Sihai Xiao and
Xiaofa Shi and
Guiliang Feng and
T. R. N. Rao A generalization of the single $b$-Bit
byte error correcting and double bit
error detecting codes for high-speed
memory systems . . . . . . . . . . . . . 508--511
Q. M. Malluhi and
M. A. Bayoumi and
T. R. N. Rao Correction to ``Efficient Mapping of
ANNs on Hypercube Massively Parallel
Machines'' . . . . . . . . . . . . . . . 511--511
M. J. Corinthios A weighted $Z$ spectrum, parallel
algorithm, and processors for
mathematical model estimation . . . . . 513--528
S. Rajasekaran Mesh connected computers with fixed and
reconfigurable buses: packet routing and
sorting . . . . . . . . . . . . . . . . 529--539
Sang Bang Choi and
A. K. Somani Design and performance analysis of
load-distributing fault-tolerant network 540--551
M. Franklin and
G. S. Sohi ARB: a hardware mechanism for dynamic
reordering of memory references . . . . 552--571
Jong Kim and
K. G. Shin Execution time analysis of communicating
tasks in distributed systems . . . . . . 572--579
L. K. John and
Yu-Cheng Liu Performance model for a prioritized
multiple-bus multiprocessor system . . . 580--588
Y. Shintani and
T. Shonai and
H. Kurokawa and
K. Kuriyama and
A. Yamaoka Hierarchical execution to speed up
pipeline interlock in mainframe
computers . . . . . . . . . . . . . . . 589--599
P. Mohapatra and
Chansu Yu and
C. R. Das Allocation and mapping based reliability
analysis of multistage interconnection
networks . . . . . . . . . . . . . . . . 600--606
R. S. Katti and
M. Blaum An improvement on constructions of
t-EC/AUED codes . . . . . . . . . . . . 607--608
R. A. Ayoubi and
Q. M. Malluhi and
M. A. Bayoumi The extended cube connected cycles: an
efficient interconnection for massively
parallel systems . . . . . . . . . . . . 609--614
C. P. Low and
H. W. Leong A new class of efficient algorithms for
reconfiguration of memory arrays . . . . 614--618
A. Symvonis and
J. Tidswell An empirical study of off-line
permutation packet routing on
two-dimensional meshes based on the
multistage routing method . . . . . . . 619--625
Yuke Wang and
C. McCrosky Negation trees: a unified approach to
Boolean function complementation . . . . 626--630
Wang-Jiunn Cheng and
Wen-Tsuen Chen A new self-routing permutation network 630--636
B. Parhami and
S. Kawahito and
M. Ishida and
T. Nakamura and
M. Kameyama and
T. Higuchi Comments on ``High-speed area-efficient
multiplier design using multiple-valued
current-mode circuits'' . . . . . . . . 637--639
S. Kawahito and
M. Ishida and
T. Nakamura and
M. Kameyama and
T. Higuchi Author's Reply . . . . . . . . . . . . . 639--639
Yuh-Rong Leu and
Sy-Yen Kuo A fault-tolerant tree communication
scheme for hypercube systems . . . . . . 641--650
P. T. Gaughan and
B. V. Dao and
S. Yalamanchili and
D. E. Schimmel Distributed, deadlock-free routing in
faulty, pipelined, direct
interconnection networks . . . . . . . . 651--665
Chien-Chun Su and
K. G. Shin Adaptive fault-tolerant deadlock-free
routing in meshes and hypercubes . . . . 666--683
K. G. Shin and
S. W. Daniel Analysis and implementation of hybrid
switching . . . . . . . . . . . . . . . 684--692
E. A. Varvarigos and
D. P. Bertsekas A conflict sense routing protocol and
its performance for hypercubes . . . . . 693--703
S. Felperin and
P. Raghavan and
E. Upfal A theory of wormhole routing in parallel
computers . . . . . . . . . . . . . . . 704--713
S. N. Bhatt and
G. Bilardi and
G. Pucci and
A. Ranade and
A. L. Rosenberg and
E. J. Schwabe On bufferless routing of variable length
messages in leveled networks . . . . . . 714--729
D. M. Nicol and
R. Simha and
D. Towsley Static assignment of stochastic tasks
using majorization . . . . . . . . . . . 730--740
M. Schlag and
F. J. Ferguson Detection of multiple faults in
two-dimensional ILAs . . . . . . . . . . 741--746
A. Kumar and
D. P. Agrawal Parameters for system effectiveness
evaluation of distributed systems . . . 746--752
A. D. Singh and
C. M. Krishna On the effect of defect clustering on
test transparency and IC test
optimization . . . . . . . . . . . . . . 753--757
M. A. Al-Mouhamed and
S. S. Seiden Minimization of memory and network
contention for accessing arbitrary data
patterns in SIMD systems . . . . . . . . 757--762
K. Lai and
P. K. Lala Multiple fault detection in fan-out free
circuits using minimal single fault test
set . . . . . . . . . . . . . . . . . . 763--765
B. A. Pearlmutter Doing the twist: diagonal meshes are
isomorphic to twisted toroidal meshes 766--767
C. Padro and
P. Morillo and
M. A. Fiol Comments on ``Line digraph iterations
and connectivity analysis of de Bruijn
and Kautz graphs'' . . . . . . . . . . . 768--768
S. Chakraborty and
D. Roy Chowdhury and
P. Pal Chaudhuri Theory and application of nongroup
cellular automata for synthesis of
easily testable finite state machines 769--781
K. Cattell and
J. C. Muzio Analysis of one-dimensional linear
hybrid cellular automata over
$\mathrm{GF}(q)$ . . . . . . . . . . . . 782--792
A. Merchant and
B. Melamed and
E. Schenfeld and
B. Sengupta Analysis of a control mechanism for a
variable speed processor . . . . . . . . 793--801
J. K. Dey and
J. Kurose and
D. Towsley On-line scheduling policies for a class
of IRIS (Increasing Reward with
Increasing Service) real-time tasks . . 802--813
Ching-Chih Han and
Kwei-Jay Lin and
Chao-Ju Hou Distance-constrained scheduling and its
applications to real-time systems . . . 814--826
Weijia Shang and
E. Hodzic and
Zhigang Chen On uniformization of affine dependence
algorithms . . . . . . . . . . . . . . . 827--840
Thang Nguyen Bui and
Byung Ro Moon Genetic algorithm and graph partitioning 841--855
C. Paar A new architecture for a parallel finite
field multiplier with low complexity
based on composite fields . . . . . . . 856--861
Bin Wei Comments on ``A multiaccess frame buffer
architecture'' . . . . . . . . . . . . . 862--862
Ding-Zhu Du and
D. F. Hsu and
Yuh-Dauh Lyuu Corrigendum to ``Line Digraph Iterations
and Connectivity Analysis of de Bruijn
and Kautz Graphs'' . . . . . . . . . . . 863--863
Anonymous Correction to ``Improved Digital
Signature Algorithm'' . . . . . . . . . 864--864
N. S. Bowen and
D. K. Pradhan The effect of program behavior on fault
observability . . . . . . . . . . . . . 868--880
C. R. Yount and
D. P. Siewiorek A methodology for the rapid injection of
transient hardware errors . . . . . . . 881--891
A. K. Somani and
O. Peleg On diagnosability of large fault sets in
regular topology-based computer systems 892--903
A. Majumdar On evaluating and optimizing weights for
weighted random pattern testing . . . . 904--916
J. Salinas and
Yinan Shen and
F. Lombardi A sweeping line approach to interconnect
testing . . . . . . . . . . . . . . . . 917--929
J. Savir Reducing the MISR size . . . . . . . . . 930--938
S. Gupta and
J. Rajski and
J. Tyszer Arithmetic additive generators of
pseudo-exhaustive test patterns . . . . 939--949
R. D. Blanton and
J. P. Hayes Testability of convergent tree circuits 950--963
P. Kulasinghe and
A. El-Amawy Optimal realization of sets of
interconnection functions on synchronous
multiple bus systems . . . . . . . . . . 964--969
S. Rai and
V. P. Kirpalani A modified TRAM architecture . . . . . . 969--974
D. T. Smith and
B. W. Johnson and
J. A. Profeta III System dependability evaluation via a
fault list generation algorithm . . . . 974--979
H. Lalgudi and
L. F. Akyildiz and
S. Yalamanchili Augmented binary hypercube: a new
architecture for processor management 980--984
S. Chakravarty Synthesis of delay fault testability
circuits . . . . . . . . . . . . . . . . 985--991
B. Bollig and
I. Wegener Improving the variable ordering of OBDDs
is NP-complete . . . . . . . . . . . . . 993--1002
K. Sasidhar and
S. Chattopadhyay and
P. P. Chaudhuri CAA decoder for cellular automata based
byte error correcting code . . . . . . . 1003--1016
C. L. Chen and
B. W. Curran Switching codes for delta-$I$ noise
reduction . . . . . . . . . . . . . . . 1017--1021
Jien-Chung Lo A hyper optimal encoding scheme for
self-checking circuits . . . . . . . . . 1022--1030
D. H. Linder and
J. H. Harden Phased logic: supporting the synchronous
design paradigm with delay-insensitive
circuitry . . . . . . . . . . . . . . . 1031--1044
Ming Zhang and
S. Vassiliadis and
J. G. Delgado-Frias Sigmoid generators for neural computing
using piecewise approximations . . . . . 1045--1049
L. Ciminiera and
P. Montuschi Carry-save multiplication schemes
without final addition . . . . . . . . . 1050--1055
Zhen Liu and
Ting-Yi Sung Routing and transmitting problems in de
Bruijn networks . . . . . . . . . . . . 1056--1062
S. Vassilladis and
S. Contofana and
K. Bertels $2$-$1$ addition and related arithmetic
operations with threshold logic . . . . 1062--1067
E. Antelo and
J. D. Bruguera and
E. L. Zapata Unified mixed radix $2$-$4$ redundant
CORDIC processor . . . . . . . . . . . . 1068--1073
C. U. Martel and
W. M. Moh and
Teng-Sheng Moh Dynamic prioritized conflict resolution
on multiple access broadcast networks 1074--1079
Chung-Len Lee and
Meng-Lieh Sheu A multiple-sequence generator based on
inverted nonlinear autonomous machines 1079--1083
Haomin Wu and
M. A. Perkowski and
Xiaoqiang Zeng and
Nan Zhuang Generalized partially-mixed-polarity
Reed--Muller expansion and its fast
computation . . . . . . . . . . . . . . 1084--1088
Chung-Ho Chen and
A. K. Somani Architecture technique trade-offs using
mean memory delay time . . . . . . . . . 1089--1100
M. Banatre and
A. Gefflaut and
P. Joubert and
C. Morin and
P. A. Lee An architecture for tolerating processor
failures in shared-memory
multiprocessors . . . . . . . . . . . . 1101--1115
Shenze Chen and
D. Towsley A performance evaluation of RAID
architectures . . . . . . . . . . . . . 1116--1130
S. Chakravarty and
P. J. Thadikaran Simulation and generation of IDDQ tests
for bridging faults in combinational
circuits . . . . . . . . . . . . . . . . 1131--1140
M. Nicolaidis Theory of transparent BIST for RAMs . . 1141--1156
Chao Feng and
L. N. Bhuyan and
F. Lombardi Adaptive system-level diagnosis for
hypercube multiprocessors . . . . . . . 1157--1170
Zheng-Ou Wang A bidirectional associative memory based
on optimal linear associative memory . . 1171--1179
Bruce L. Jacob and
Peter M. Chen and
Seth R. Silverman and
Trevor N. Mudge An Analytical Model for Designing Memory
Hierarchies . . . . . . . . . . . . . . 1180--1194
S. Sahni Scheduling master-slave multiprocessor
systems . . . . . . . . . . . . . . . . 1195--1199
Weiping Shi and
Ming-Feng Chang and
W. K. Fuchs Harvest rate of reconfigurable pipelines 1200--1203
Yi-Chieh Chang and
K. G. Shin Load sharing in hypercube-connected
multicomputers in the presence of node
failures . . . . . . . . . . . . . . . . 1203--1211
J. Rajski and
J. Tyszer On linear dependencies in subspaces of
LFSR-generated sequences . . . . . . . . 1212--1216
Hagbae Kim and
K. G. Shin Design and analysis of an optimal
instruction-retry policy for TMR
controller computers . . . . . . . . . . 1217--1225
F. V. Brasileiro and
P. D. Ezhilchelvan and
S. K. Shrivastava and
N. A. Speirs and
S. Tao Implementing fail-silent nodes for
distributed systems . . . . . . . . . . 1226--1238
A. Roy-Chowdhury and
P. Banerjee Algorithm-based fault location and
recovery for matrix computations on
multiprocessor systems . . . . . . . . . 1239--1247
Hungse Cha and
E. M. Rudnick and
J. H. Patel and
R. K. Iyer and
G. S. Choi A gate-level simulation environment for
alpha-particle-induced transient faults 1248--1256
Haigeng Wang and
A. Nicolau and
K.-Y. S. Siu The strict time lower bound and optimal
schedules for parallel prefix with
resource constraints . . . . . . . . . . 1257--1271
Hyunmin Park and
D. P. Agrawal WICI: an efficient hybrid routing scheme
for scalable and hierarchical networks 1272--1281
P. Dierrich and
R. R. Rao Request resubmission in a blocking,
circuit-switched, interconnection
network . . . . . . . . . . . . . . . . 1282--1293
R. Drechsler and
M. Theobald and
B. Becker Fast OFDD-based minimization of fixed
polarity Reed--Muller expressions . . . 1294--1299
W. G. Schneeweiss A necessary and sufficient criterion for
the monotonicity of Boolean functions
with deterministic and stochastic
applications . . . . . . . . . . . . . . 1300--1302
Nian-Feng Tzeng and
Guanghua Lin Efficient determination of maximum
incomplete subcubes in hypercubes with
faults . . . . . . . . . . . . . . . . . 1303--1308
J. Walker and
A. Cantoni A new synchronizer design . . . . . . . 1308--1311
Yuan-Chieh Hsu and
S. K. Gupta A simulator for at-speed robust testing
of path delay faults in combinational
circuits . . . . . . . . . . . . . . . . 1312--1318
K. Grimsrud and
J. Archibald and
R. Frost and
B. Nelson Locality as a visualization tool . . . . 1319--1326
S. Fujita and
M. Yamashita Fast gossiping on mesh-bus computers . . 1326--1330
Hagbae Kim and
K. G. Shin Sequencing tasks to minimize the effects
of near-coincident faults in TMR
controller computers . . . . . . . . . . 1331--1337
N. R. Saxena and
E. J. McCluskey Counting two-state transition-tour
sequences . . . . . . . . . . . . . . . 1337--1342
A. Wrzyszcz and
D. Milford and
E. L. Dagless A new approach to fixed-coefficient
inner product computation over finite
rings . . . . . . . . . . . . . . . . . 1345--1355
Eric M. Schwarz and
Michael J. Flynn Hardware Starting Approximation Method
and Its Application to the Square Root
Operation . . . . . . . . . . . . . . . 1356--1369
Yu Hen Hu and
H. H. M. Chern A novel implementation of CORDIC
algorithm using backward angle recoding
(BAR) . . . . . . . . . . . . . . . . . 1370--1378
Kwang-Ting Cheng and
A. Krstic and
Hsi-Chuan Chen Generation of high quality tests for
robustly untestable path delay faults 1379--1392
A. Ivanov and
B. K. Tsuji and
Y. Zorian Programmable BIST space compactors . . . 1393--1404
D. Kagaris and
S. Tragoudas and
A. Majumdar On the use of counters for reproducing
deterministic test sets . . . . . . . . 1405--1419
E. G. Bernard Efficient fault location for globally
controlled and comparison-based
multistage interconnection networks . . 1420--1425
B. J. Oommen and
K. Zhang and
W. Lee Numerical similarity and dissimilarity
measures between two trees . . . . . . . 1426--1434
V. Raghavan Weighted diagnosis with asymmetric
invalidation . . . . . . . . . . . . . . 1435--1438
Qingyan Wang and
N. L. Passos and
Edwin Hsing-Mean Sha Optimal data scheduling for uniform
multidimensional applications . . . . . 1439--1444
Honghai Jiang and
J. C. Majithia Suggestion for a new representation for
binary function . . . . . . . . . . . . 1445--1449
Y. Tohma and
Y. Koyanagi Fault-tolerant design of neural networks
for solving optimization problems . . . 1450--1455
Anonymous 1996 Index IEEE Transactions on
Computers Volume 45 . . . . . . . . . . INDEX:1--INDEX:15
L. Sha and
S. S. Sathaye and
J. K. Strosnider Analysis of dual-link networks for
real-time applications . . . . . . . . . 1--13
S. Dolev and
J. L. Welch Crash resilient communication in dynamic
networks . . . . . . . . . . . . . . . . 14--26
S. Papadimitriou and
A. Bezerianos and
T. Bountis Secure communication with chaotic
systems of difference equations . . . . 27--38
S. Khanna and
W. K. Fuchs A graph partitioning approach to
sequential diagnosis . . . . . . . . . . 39--47
I. Pomeranz and
S. M. Reddy On dictionary-based fault location in
digital logic circuits . . . . . . . . . 48--59
K. K. Goswami DEPEND: a simulation-based environment
for system level dependability analysis 60--74
R. S. Katti Nonprime memory systems and error
correction in address translation . . . 75--79
Y. R. Shayan and
T. Le-Ngoc A cellular structure for a versatile
Reed--Solomon decoder . . . . . . . . . 80--85
H. R. Srinivas and
K. K. Parhi and
L. A. Montalvo Radix $2$ division with over-redundant
quotient selection . . . . . . . . . . . 85--92
H. Ural and
Xiaolin Wu and
Fan Zhang On minimizing the lengths of checking
sequences . . . . . . . . . . . . . . . 93--99
K. H. Yeung and
T. S. Yum Selective broadcast data distribution
systems . . . . . . . . . . . . . . . . 100--104
M. Hamada and
E. Fujiwara A class of error control codes for byte
organized memory systems-SbEC-(Sb+S)ED
codes . . . . . . . . . . . . . . . . . 105--109
S. K. Bhogavilli and
H. Abu-Amara Design and analysis of high performance
multistage interconnection networks . . 110--117
Qing Hu and
Xiaojun Shen and
Jingyu Yang Topologies of combined $(2 \log N -
1)$-stage interconnection networks . . . 118--124
Anonymous 1996 Reviewers List . . . . . . . . . . 125--128
Eisuke Kinoshita and
Ki-Ja Lee A Residue Arithmetic Extension for
Reliable Scientific Computation . . . . 129--138
C. D. Walter Space/time trade-offs for higher radix
modular multiplication using repeated
addition . . . . . . . . . . . . . . . . 139--141
Ming-Bo Lin and
A. Y. Oruc The design of an optoelectronic
arithmetic processor based on
permutation networks . . . . . . . . . . 142--153
S. F. Oberman and
M. J. Flynn Design Issues in Division and Other
Floating-Point Operations . . . . . . . 154--161
Huapeng Wu and
M. A. Hasan Efficient exponentiation of a primitive
root in $\mathrm{GF}(2^m)$ . . . . . . . 162--172
Chien-Chung Tsai and
M. Marek-Sadowska Boolean functions classification via
fixed polarity Reed--Muller forms . . . 173--186
R. A. Rowley and
B. Bose Distributed ring embedding in faulty De
Bruijn networks . . . . . . . . . . . . 187--190
J. Upadhyay and
V. Varavithya and
P. Mohapatra A traffic-balanced adaptive wormhole
routing scheme for two-dimensional
meshes . . . . . . . . . . . . . . . . . 190--197
F. S. Annexstein Generating de Bruijn sequences: an
efficient implementation . . . . . . . . 198--200
K. Diks and
A. Pelc Globally optimal diagnosis in systems
with random faults . . . . . . . . . . . 200--204
K. A. Schueller and
J. T. Butler Complexity analysis of the cost-table
approach to the design of
multiple-valued logic circuits . . . . . 205--209
A. Seznec Decoupled sectored caches . . . . . . . 210--215
Rong-Huei Hou and
Sy-Yen Kuo and
Yi-Ping Chang Optimal release times for software
systems with scheduled delivery time
based on the HGDM . . . . . . . . . . . 216--221
Jehn-Ruey Jiang and
Shing-Tsaan Huang and
Yu-Chen Kuo Cohorts structures for fault-tolerant
$k$ entries to a critical section . . . 222--228
J. Fridman and
S. Rangarajan Maximizing mean-time to failure in
$k$-resilient systems with repair . . . 229--234
P. A. Franaszek and
J. T. Robinson On variable scope of parity protection
in disk arrays . . . . . . . . . . . . . 234--240
Jie Wu Reliable unicasting in faulty hypercubes
using safety levels . . . . . . . . . . 241--247
Jien-Chung Lo A fast binary adder with conditional
carry generation . . . . . . . . . . . . 248--253
I. Chlamtac and
Yi-Bing Lin Mobile Computing: When Mobility Meets
Computation . . . . . . . . . . . . . . 257--259
A. V. Bakre and
B. R. Badrinath Implementation and performance
evaluation of Indirect TCP . . . . . . . 260--278
M. Zorzi and
R. R. Rao Error control and energy consumption in
communications for nomadic computing . . 279--289
R. Dube and
C. D. Rais and
S. K. Tripathi Improving NFS performance over wireless
links . . . . . . . . . . . . . . . . . 290--298
Qi Lu and
M. Satyanarayanan Resource conservation in a mobile
transaction system . . . . . . . . . . . 299--311
Kyungshik Lim and
Yann-Hang Lee Optimal partitioning of heterogeneous
traffic sources in mobile communications
networks . . . . . . . . . . . . . . . . 312--325
Xuefeng Dong and
Ten-Hwang Lai An efficient protocol for call setup and
path migration in IEEE 802.6 based
personal communication networks . . . . 326--336
A. D. Joseph and
J. A. Tauber and
M. F. Kaashoek Mobile computing with the Rover toolkit 337--352
S. Alagar and
S. Venkatesan Causal ordering in distributed mobile
systems . . . . . . . . . . . . . . . . 353--361
K. K. Leung Update algorithm for replicated
signaling databases in wireless and
advanced intelligent networks . . . . . 362--367
B. Gavish and
S. Sridhar Threshold priority policy for channel
assignment in cellular networks . . . . 367--370
Anonymous Reviewers List for Special Issue on
Mobile Computing . . . . . . . . . . . . 371--371
D. K. Pradhan and
N. H. Vaidya Roll-forward and rollback recovery:
performance-reliability trade-off . . . 372--378
Hsing-Lung Chen and
Nian-Feng Tzeng On-line task migration in hypercubes
through double disjoint paths . . . . . 379--384
J. V. Woods and
P. Day and
S. B. Furber and
J. D. Garside and
N. C. Paver and
S. Temple AMULET1: an asynchronous ARM
microprocessor . . . . . . . . . . . . . 385--398
B. K. Gunther Multithreading with distributed
functional units . . . . . . . . . . . . 399--411
K. D. Wilken and
T. Kong Concurrent detection of software and
hardware data-access faults . . . . . . 412--424
N. R. Saxena and
E. J. McCluskey Parallel signature analysis design with
bounds on aliasing . . . . . . . . . . . 425--438
Hung-Kuei Ku and
J. P. Hayes Systematic design of fault-tolerant
multiprocessors with shared buses . . . 439--455
Yi-Min Wang Consistent global checkpoints that
contain a given set of local checkpoints 456--468
D. R. Kaeli and
P. G. Emma Improving the accuracy of history-based
branch prediction . . . . . . . . . . . 469--472
D. Kazakos and
L. F. Merakos and
H. Delic Random multiple access algorithms using
a control mini-slot . . . . . . . . . . 473--476
S. R. Tate Band ordering in lossless compression of
multispectral images . . . . . . . . . . 477--483
Jie Wu and
Ke Huang The balanced hypercube: a cube-based
system for fault-tolerant applications 484--490
J. T. Butler and
D. S. Herscovici and
T. Sasao and
R. J. Barton III Average and worst case number of nodes
in decision diagrams of symmetric
multiple-valued functions . . . . . . . 491--494
M. Ito and
N. Takagi and
S. Yajima Efficient initial approximation for
multiplicative division and square root
by a multiplication with operand
modification . . . . . . . . . . . . . . 495--498
Jong Kim and
Heejo Lee and
Sunggu Lee Replicated process allocation for load
distribution in fault-tolerant
multicomputers . . . . . . . . . . . . . 499--505
P. Fitzpatrick Extending backward error assertions to
tolerance of large errors in floating
point computations . . . . . . . . . . . 505--510
C. S. Laih and
M. J. Gau Cryptanalysis of a Diophantine equation
oriented public key cryptosystem . . . . 511--512
S. R. Blackburn and
S. Murphy and
K. G. Paterson A comment on ``A new public-key cipher
system based upon the Diophantine
equations'' . . . . . . . . . . . . . . 512--512
P. Lenders and
S. Rajopadhye Multirate VLSI arrays and their
synthesis . . . . . . . . . . . . . . . 515--529
F. Bodin and
A. Seznec Skewed associativity improves program
performance and enhances predictability 530--544
S. N. Bhatt and
F. R. K. Chung and
F. T. Leighton and
A. L. Rosenberg On optimal strategies for cycle-stealing
in networks of workstations . . . . . . 545--557
A. Merigot Associative nets: a graph-based parallel
computing model . . . . . . . . . . . . 558--571
A. W. Apon and
L. W. Dowdy The circulating processor model of
parallel systems . . . . . . . . . . . . 572--587
Chung-Chin Lu A search of minimal key functions for
normal basis multipliers . . . . . . . . 588--592
Yu-Chee Tseng and
Jang-Ping Sheu Toward optimal broadcast in a star graph
using multiple spanning trees . . . . . 593--599
J. L. Ganley and
J. P. Cohoon Minimum-congestion hypergraph embedding
in a cycle . . . . . . . . . . . . . . . 600--602
D. Stiliadis and
A. Varma Selective victim caching: a method to
improve the performance of direct-mapped
caches . . . . . . . . . . . . . . . . . 603--610
M. G. Parker and
M. Benaissa Modular arithmetic using low order
redundant bases . . . . . . . . . . . . 611--616
S. Chalasani and
R. V. Boppana Communication in multicomputers with
nonconvex faults . . . . . . . . . . . . 616--622
M. Daumas and
D. W. Matula Validated roundings of dot products by
sticky accumulation . . . . . . . . . . 623--629
Keqin Li Stochastic bounds for parallel program
execution times with processor
constraints . . . . . . . . . . . . . . 630--636
S. R. Blackburn and
S. Murphy and
K. G. Paterson and
S. Nandi and
P. P. Chaudhuri Comments on ``Theory and applications of
cellular automata in cryptography'' [and
reply] . . . . . . . . . . . . . . . . . 637--639
S. Nandi and
P. P. Chaudhuri Reply to Comments on ``Theory And
Application Of Cellular Automata In
Cryptography'' . . . . . . . . . . . . . 639--639
B. P. Buckles and
S. Chanson Guest Editors' Introduction . . . . . . 641--641
O. Babaoglu and
A. Bartoli and
G. Dini Enriched view synchrony: a programming
paradigm for partitionable asynchronous
distributed systems . . . . . . . . . . 642--658
J. A. Cobb and
M. G. Gouda The request reply family of group
routing protocols . . . . . . . . . . . 659--672
M. Papazoglou and
A. Dells and
A. Bouguettaya and
M. Haghjoo Class library support for workflow
environments and applications . . . . . 673--686
Y. M. Boura and
C. R. Das Performance analysis of buffering
schemes in wormhole routers . . . . . . 687--694
Guoping Liu and
K. Y. Lee and
H. F. Jordan TDM and TWDM de Bruijn networks and
ShuffleNets for optical communications 695--701
T. Hamano and
N. Takagi and
S. Yajima and
F. P. Preparata $O(n)$-depth modular exponentiation
circuit algorithm . . . . . . . . . . . 701--704
M. A. Hasan Division-and-accumulation over
$\mathrm{GF}(2^m)$ . . . . . . . . . . . 705--708
T. Sasao Easily testable realizations for
generalized Reed--Muller expressions . . 709--716
F. K. Hwang and
P. J. Wan Comparing file copies with at most three
disagreeing pages . . . . . . . . . . . 716--718
S. Kartik and
C. Siva Ram Murthy Task allocation algorithms for
maximizing reliability of distributed
computing systems . . . . . . . . . . . 719--724
D. L. Tao and
K. Kantawala Evaluating reliability improvements of
fault tolerant array processors using
algorithm-based fault tolerance . . . . 725--730
Yuke Wang and
M. Abd-el-Barr and
C. McCrosky An algorithm for total symmetric OBDD
detection . . . . . . . . . . . . . . . 731--733
D. M. Marom and
D. Mendlovic Comment on ``A new routing algorithm for
a class of rearrangeable networks'' . . 734--734
Y. Ofek and
B. Yener and
M. Yung Concurrent asynchronous broadcast on the
MetaNet . . . . . . . . . . . . . . . . 737--748
S. Park and
B. Bose All-to-all broadcasting in faulty
hypercubes . . . . . . . . . . . . . . . 749--755
Ching-Chih Han and
Chao-Ju Hou and
K. G. Shin On slot allocation for time-constrained
messages in dual-bus networks . . . . . 756--767
S. Ha and
E. A. Lee Compile-time scheduling of dynamic
constructs in dataflow program graphs 768--778
L. Lamport How to make a correct multiprocess
program execute correctly on a
multiprocessor . . . . . . . . . . . . . 779--782
I. Pomeranz and
S. M. Reddy Test generation for multiple state-table
faults in finite-state machines . . . . 783--794
N. Mukherjee and
J. Rajski and
J. Tyszer Design of testable multipliers for
fixed-width data paths . . . . . . . . . 795--810
M. A. Thornton Signed binary addition circuitry with
inherent even parity outputs . . . . . . 811--816
D. L. Tao A self-testing nonincreasing order
checker . . . . . . . . . . . . . . . . 817--820
M. K. Kim and
H. Yoon and
S. R. Maeng On the correctness of inside-out routing
algorithm . . . . . . . . . . . . . . . 820--823
W. S. VanScheik and
R. F. Tinderr High speed externally
asynchronous/internally clocked systems 824--829
S. F. Oberman and
M. J. Flynn Division Algorithms and Implementations 833--854
E. Antelo and
J. Villalba and
J. D. Bruguera and
E. L. Zapata High performance rotation architectures
based on the radix-4 CORDIC algorithm 855--870
Hsing-Lung Chen and
Nian-Feng Tzeng Subcube determination in faulty
hypercubes . . . . . . . . . . . . . . . 871--879
Xiaojun Shen and
Weifa Liang and
Qing Hu On embedding between $2$D meshes of the
same size . . . . . . . . . . . . . . . 880--889
A. Albrecht and
S. K. Cheung and
K. C. Hui and
K. S. Leung and
C. K. Wong Optimal placements of flexible objects.
I. Analytical results for the unbounded
case . . . . . . . . . . . . . . . . . . 890--904
A. Albrecht and
S. K. Cheung and
K. C. Hui and
K. S. Leung and
C. K. Wong Optimal placements of flexible objects.
II. A simulated annealing approach for
the bounded case . . . . . . . . . . . . 905--929
C. D. Yang The smallest pair of noncrossing paths
in a rectilinear polygon . . . . . . . . 930--941
N. H. Vaidya Impact of checkpoint latency on overhead
ratio of a checkpointing scheme . . . . 942--947
Yu-Chee Tseng A dilated-diagonal-based scheme for
broadcast in a wormhole-routed $2$D
torus . . . . . . . . . . . . . . . . . 947--952
Ge-Ming Chiu and
Kai-Shung Chen Use of routing capability for
fault-tolerant routing in hypercube
multicomputers . . . . . . . . . . . . . 953--958
F. K. Hwang A modification to a decomposition
algorithm of Gordon and Srikanthan . . . 958--960
D. Michelucci and
J.-M. Moreau Lazy arithmetic . . . . . . . . . . . . 961--975
A. Ziv and
J. Bruck An on-line algorithm for checkpoint
placement . . . . . . . . . . . . . . . 976--985
A. Mehra and
J. Rexford and
F. Jahanian Design and evaluation of a
window-consistent replication service 986--996
S. Dutt and
N. R. Mahapatra Node-covering, error-correcting codes
and multiprocessors with very high
average fault tolerance . . . . . . . . 997--1015
H. Hansson and
L. Lawson and
O. Bridal and
C. Eriksson and
S. Larsson and
H. Lon and
M. Stromberg BASEMENT: an architecture and
methodology for distributed automotive
real-time systems . . . . . . . . . . . 1016--1027
Shyue-Kung Lu and
Sy-Yen Kuo and
Cheng-Wen Wu Fault-tolerant interleaved memory
systems with two-level redundancy . . . 1028--1034
S. K. Baruah and
J. R. Haritsa Scheduling for overload in real-time
systems . . . . . . . . . . . . . . . . 1034--1039
Pao-Hwa Sui and
Sheng-De Wang An improved algorithm for fault-tolerant
wormhole routing in meshes . . . . . . . 1040--1042
Qian-Ping Gu and
Shietung Peng $K$-pairwise cluster fault tolerant
routing in hypercubes . . . . . . . . . 1042--1049
N. Tabrizi and
M. J. Liebelt and
K. Eshraghian A tabular method for guard
strengthening, symmetrization, and
operator reduction for Martin's
asynchronous design methodology . . . . 1050--1054
T. H. Szymanski Design principles for practical
self-routing nonblocking switching
networks with $O(N \cdot \log N)$
bit-complexity . . . . . . . . . . . . . 1057--1069
A. Fernandez and
K. Efe Efficient VLSI layouts for homogeneous
product networks . . . . . . . . . . . . 1070--1082
M. M. Bae Resource placement in torus-based
networks . . . . . . . . . . . . . . . . 1083--1092
K. Olukotun and
T. N. Mudge and
R. B. Brown Multilevel optimization of pipelined
caches . . . . . . . . . . . . . . . . . 1093--1102
O. I. Pentakalos and
D. A. Menasce and
M. Halem and
Y. Yesha Analytical performance modeling of
hierarchical mass storage systems . . . 1103--1118
A. L. Rosenberg and
V. Scarano and
R. K. Sitaraman The reconfigurable ring of processors:
fine-grain tree-structured computations 1119--1131
M. De and
D. Das and
M. Ghosh and
B. P. Sinha An efficient sorting algorithm on the
multi-mesh network . . . . . . . . . . . 1132--1137
Yi-Min Wang and
Yennun Huang and
C. Kintala Progressive retry for software failure
recovery in message-passing applications 1137--1141
B. Fagin Partial resolution in branch target
buffers . . . . . . . . . . . . . . . . 1142--1145
F. Pourbigharaz A signed-digit architecture for residue
to binary transformation . . . . . . . . 1146--1150
B. L. Jacob and
P. M. Chen and
T. N. Mudge and
S. R. Silverman A comment on ``An analytical model for
designing memory hierarchies'' . . . . . 1151--1151
S. Srbljic and
Z. G. Vranesic and
M. Stumm and
L. Budin Analytical prediction of performance for
cache coherence protocols . . . . . . . 1155--1173
V. Phalke and
B. Gopinath Compression-based program
characterization for improving cache
memory performance . . . . . . . . . . . 1174--1186
H. Wang and
T. Sun and
Q. Yang Minimizing area cost of on-chip cache
memories by caching address tags . . . . 1187--1201
S. Wang and
V. Piuri and
E. E. Swartzlander, Jr. Hybrid CORDIC algorithms . . . . . . . . 1202--1207
A. Chatterjee and
R. K. Roy Concurrent error detection in nonlinear
digital circuits using time-freeze
linearization . . . . . . . . . . . . . 1208--1218
D. J. Neebel and
C. R. Kime Cellular automata for weighted random
pattern generation . . . . . . . . . . . 1219--1229
J. Jain and
J. Bitner and
M. S. Abadir and
J. A. Abraham and
D. S. Fussell Indexed BDDs: algorithmic advances in
techniques to represent and verify
Boolean functions . . . . . . . . . . . 1230--1245
Kuan-Jen Lin and
Chi-Wen Kuo and
Chen-Shang Lin Synthesis of hazard-free asynchronous
circuits based on characteristic graph 1246--1263
E. Antelo and
J. D. Bruguera and
T. Lang and
E. L. Zapata Error analysis and reduction for angle
calculation using the CORDIC algorithm 1264--1271
B. J. Falkowski and
Chip-Hong Chang Forward and inverse transformations
between Haar spectra and ordered binary
decision diagrams of Boolean functions 1272--1279
K. Bolding and
M. Fulgham and
L. Snyder The case for chaotic adaptive routing 1281--1292
Chi-Chang Chen and
Jianer Chen Optimal parallel routing in star
networks . . . . . . . . . . . . . . . . 1293--1303
J. D. Bright and
G. F. Sullivan and
G. M. Masson A formally verified sorting certifier 1304--1312
Tei-Wei Kuo and
A. K. Mok Incremental reconfiguration and load
adjustment in adaptive real time systems 1313--1324
M. Hamsaoui and
P. Ramanathan Evaluating dynamic failure probability
for streams with $(m, k)$-firm deadlines 1325--1337
Chao-Ju Hou and
K. G. Shin Allocation of periodic task modules with
precedence and deadline constraints in
distributed real-time systems . . . . . 1338--1356
N. W. Lo and
B. S. Carlson and
D. L. Tao Fault tolerant algorithms for
broadcasting on the star graph network 1357--1362
Yung-Yuan Chen and
S. J. Upadhyaya and
Ching-Hwa Cheng A comprehensive reconfiguration scheme
for fault-tolerant VLSI/WSI array
processors . . . . . . . . . . . . . . . 1363--1371
Yiu-Wing Leung Processor assignment and execution
sequence for multiversion software . . . 1371--1377
M. V. Ramakrishna and
E. Fu and
E. Bahcekapili Efficient hardware hashing functions for
high performance computers . . . . . . . 1378--1381
K. Kanoun and
I. Pomeranz Guest Editors' Introduction . . . . . . 1--1
D. Moundanos and
J. A. Abraham and
Y. V. Hoskote Abstraction techniques for validation
coverage analysis and test generation 2--14
F. Hanchek and
S. Dutt Methodologies for tolerating cell and
interconnect faults in FPGAs . . . . . . 15--33
E. P. Duarte, Jr. and
T. Nanya A hierarchical adaptive distributed
system-level diagnosis algorithm . . . . 34--45
Seungjae Han and
K. G. Shin A primary-backup channel approach to
dependable real-time communication in
multihop networks . . . . . . . . . . . 46--61
M. Nicolaidis Fail-safe interfaces for VLSI:
theoretical foundations and
implementation . . . . . . . . . . . . . 62--77
J.-C. Fabre and
T. Perennou A metaobject architecture for
fault-tolerant distributed systems: the
FRIENDS approach . . . . . . . . . . . . 78--95
S. Garg and
A. Puliafito and
M. Telek and
K. Trivedi Analysis of preventive maintenance in
transactions based software systems . . 96--107
D. T. Stott and
G. Ries and
Mei-Chen Hsueh and
R. K. Iyer Dependability analysis of a high-speed
network using software-implemented fault
injection and simulated fault injection 108--119
M. Blaum and
J. Bruck and
K. Rubin and
W. Lenth A coding approach for detection of
tampering in write-once optical disks 120--125
R. W. Linderman and
R. L. R. Kohler and
M. H. Linderman A dependable high performance wafer
scale architecture for embedded signal
processing . . . . . . . . . . . . . . . 125--128
L. Nachman and
K. Saluja and
S. J. Upadhyaya and
R. Reuse A novel approach to random pattern
testing of sequential circuits . . . . . 129--134
Fong Pong and
M. Browne and
A. Nowatzyk and
M. Dubois Design verification of the S3.mp
cache-coherent shared-memory system . . 135--140
J.-M. Muller and
A. Scherbyna and
A. Tisserand Semi-logarithmic number systems . . . . 145--151
E. Antelo and
T. Lang and
J. D. Bruguera Computation of $\sqrt{(x /d)}$ in a very
high radix combined division/square-root
unit with scaling and selection by
rounding . . . . . . . . . . . . . . . . 152--161
C. Paar and
P. Fleischmann and
P. Roeise Efficient multiplier architectures for
Galois fields $\mathrm{GF}(2^{4n})$ . . 162--170
Yuke Wang and
C. McCrosky Solving Boolean equations using ROSOP
forms . . . . . . . . . . . . . . . . . 171--177
E. Rosti and
E. Smirni and
L. W. Dowdy and
G. Serazzi and
K. C. Sevcik Processor saving scheduling policies for
multiprocessor systems . . . . . . . . . 178--189
Shih-Yi Yuan and
Sy-Yen Kuo A new technique for optimization
problems in graph theory . . . . . . . . 190--196
M. Sarrafzadeh and
Wei-Liang Lin and
C. K. Wong Floating Steiner trees . . . . . . . . . 197--211
Pen-Yuang Chang and
Jong-Chuang Tsay An approach to designing modular
extensible linear arrays for regular
algorithms . . . . . . . . . . . . . . . 212--216
W. G. Schneeweiss On the polynomial form of Boolean
functions: derivations and applications 217--221
A. Ziv and
J. Bruck Analysis of checkpointing schemes with
task duplication . . . . . . . . . . . . 222--227
A. Varma and
Q. Jacobson Destage algorithms for disk arrays with
nonvolatile caches . . . . . . . . . . . 228--235
M. Lubaszewski and
B. Courtois A reliable fail-safe system . . . . . . 236--241
G. Hasteer and
P. Banerjee A parallel algorithm for state
assignment of finite state machines . . 242--246
Zheng Tang and
Qi-Ping Cao and
O. Ishizuka A learning multiple-valued logic
network: algebra, algorithm, and
applications . . . . . . . . . . . . . . 247--251
A. R. Hurson and
K. Kavi and
J. T. Lim Cyclic staggered scheme: a loop
allocation policy for DOACROSS loops . . 251--255
Seongmoon Wang and
S. K. Gupta ATPG for heat dissipation minimization
during test application . . . . . . . . 256--262
M. Barbehenn A note on the complexity of Dijkstra's
algorithm for graphs with weighted
vertices . . . . . . . . . . . . . . . . 263--263
A. El-Amawy and
P. Kulasinghe On the complexity of designing optimal
branch-and-combine clock networks . . . 264--269
P. F. Stelling and
C. U. Martel and
V. G. Oklobdzija and
R. Ravi Optimal circuits for parallel
multipliers . . . . . . . . . . . . . . 273--285
B. Mans and
N. Santoro Optimal elections in faulty loop
networks and applications . . . . . . . 286--297
A. Pelc Optimal diagnosis of heterogeneous
systems with random faults . . . . . . . 298--304
J. Savir Random pattern testability of memory
control logic . . . . . . . . . . . . . 305--312
D. Nikolos Optimal self-testing embedded parity
checkers . . . . . . . . . . . . . . . . 313--321
Jie Li and
H. Kameda Load balancing problems for multiclass
jobs in distributed/parallel computer
systems . . . . . . . . . . . . . . . . 322--332
Yutai Ma A simplified architecture for modulo
$(2^n + 1)$ multiplication . . . . . . . 333--337
B. Chess and
T. Larrabee Logic testing of bridging faults in CMOS
integrated circuits . . . . . . . . . . 338--345
R. Sastry and
N. Ranganathan A VLSI architecture for approximate tree
matching . . . . . . . . . . . . . . . . 346--352
C. K. Koc and
B. Sunar Low-complexity bit-parallel canonical
and normal basis multipliers for a class
of finite fields . . . . . . . . . . . . 353--356
S. Bettola and
V. Piuri High performance fault-tolerant digital
neural networks . . . . . . . . . . . . 357--363
W. Guo and
A. Y. Oruc Regular sparse crossbar concentrators 363--368
S. K. Tripathi Guest Editor's Introduction [The 17th
IEEE International Conference of
Distributed Computing Systems] . . . . . 369--370
P. Mishra and
M. Srivastava Effect of connection rerouting on
application performance in mobile
networks . . . . . . . . . . . . . . . . 371--390
A. S. Gokhale and
D. C. Schmidt Measuring and optimizing CORBA latency
and scalability over high-speed networks 391--413
K. Thitikamol and
P. Keleher Per-node multithreading and remote
latency . . . . . . . . . . . . . . . . 414--426
M. Zaharioudakis and
M. J. Carey Hierarchical, adaptive cache consistency
in a page server OODBMS . . . . . . . . 427--444
Pei Cao and
Chengjie Liu Maintaining strong cache consistency in
the World Wide Web . . . . . . . . . . . 445--457
R. Strom and
G. Banavar and
K. Miller and
A. Prakash and
M. Ward Concurrency control and view
notification algorithms for
collaborative replicated objects . . . . 458--471
C. Alippi and
L. Briozzo Accuracy vs. precision in digital VLSI
architectures for signal processing . . 472--477
Sheng-Uei Guan and
Hsiao-Yeh Yu and
Jen-Shun Yang A prioritized Petri net model and its
application in distributed multimedia
systems . . . . . . . . . . . . . . . . 477--481
F. C. M. Lau and
W. C. Poon Throughput analysis of B-networks . . . 482--485
J. Savir Salvaging test windows in BIST
diagnostics . . . . . . . . . . . . . . 486--491
Ching-Nung Yang and
Chi-Sung Laih DC$_m$ codes for constructing
$t$-EC/AUED codes . . . . . . . . . . . 492--495
W.-C. Hsu and
J. E. Smith A performance study of instruction cache
prefetching methods . . . . . . . . . . 497--508
J. Tse and
A. J. Smith CPU cache prefetching: Timing evaluation
of hardware implementations . . . . . . 509--526
G. Jin and
Z. Li and
F. Chen An efficient solution to the cache
thrashing problem caused by true data
sharing . . . . . . . . . . . . . . . . 527--543
L. G. Tallini and
B. Bose Theory and design of adjacent asymmetric
error masking codes . . . . . . . . . . 544--555
L. G. Tallini and
B. Bose Design of balanced and constant weight
codes for VLSI systems . . . . . . . . . 556--572
M. A. Hiltunen and
R. D. Schlichting A configurable membership service . . . 573--586
D. S. Phatak Double step branching CORDIC: a new
algorithm for fast sine and cosine
generation . . . . . . . . . . . . . . . 587--602
T.-H. Lin and
K. G. Shin Damage assessment for optimal rollback
recovery . . . . . . . . . . . . . . . . 603--613
E. Dekker Architecture scalability of parallel
vector computers with a shared memory 614--624
J. Llosa and
M. Valero and
E. Agyuade and
A. Gonzalez Module scheduling with reduced register
pressure . . . . . . . . . . . . . . . . 625--638
G. R. Redinbo Generalized algorithm-based fault
tolerance: error correction via Kalman
estimation . . . . . . . . . . . . . . . 639--655
N. H. Vaidya A case for two-level recovery schemes 656--666
G. R. Ganger and
Y. N. Patt Using system-level models to evaluate
I/O subsystem designs . . . . . . . . . 667--678
Y. Fang and
I. Chlamtac and
Yi-Bing Lin Channel occupancy times and handoff rate
for mobile computing and PCS networks 679--692
M. J. Atallah and
D. E. Comer Algorithms for variable length subnet
address assignment . . . . . . . . . . . 693--699
Chang-Gun Lee and
Hoosun Hahn and
Yang-Min Seo and
Sang Lyul Min and
Rhan Ha and
Seongsoo Hong and
Chang Yun Park and
Minsuk Lee and
Chong Sang Kim Analysis of cache-related preemption
delay in fixed-priority preemptive
scheduling . . . . . . . . . . . . . . . 700--713
T. M. Conte and
M. A. Hirsch and
W.-M. W. Hwu Combining trace sampling with single
pass methods for efficient cache
simulation . . . . . . . . . . . . . . . 714--720
Anonymous Papers from the 13th IEEE Symposium on
Computer Arithmetic . . . . . . . . . . 721--721
M. R. Stan and
A. F. Tenca and
M. D. Ercegovac Long and fast up/down counters . . . . . 722--735
T. Lang and
E. Antelo CORDIC vectoring with arbitrary target
value . . . . . . . . . . . . . . . . . 736--749
W. Krämer A priori worst case error bounds for
floating-point computations . . . . . . 750--756
C. D. Walter Exponentiation using division chains . . 757--765
J.-C. Bajard and
L.-S. Didier and
P. Kornerup An RNS Montgomery modular multiplication
algorithm . . . . . . . . . . . . . . . 766--776
M. G. Arnold and
T. A. Bailey and
J. R. Cowles and
M. D. Winkel Arithmetic co-transformations in the
real and complex logarithmic number
systems . . . . . . . . . . . . . . . . 777--786
Anonymous Special Section Referee List . . . . . . 787--787
T. Ikenaga and
T. Ogura CAM$^2$: a highly-parallel
two-dimensional cellular automaton
architecture . . . . . . . . . . . . . . 788--801
V. Akella and
N. H. Vaidya and
G. R. Redinbo Asynchronous comparison-based decoders
for delay-insensitive codes . . . . . . 802--811
S. K. Baruah and
Shun-Shii Lin Pfair scheduling of generalized pinwheel
task systems . . . . . . . . . . . . . . 812--816
S. Chattopadhyay and
D. F. Chowdhury and
S. Bhattacharjee and
P. P. Chaudhuri Cellular-automata-array-based diagnosis
of board level faults . . . . . . . . . 817--828
S. Bose and
P. Agrawal and
V. D. Agrawal Deriving logic systems for path delay
test generation . . . . . . . . . . . . 829--846
H. C. Card and
G. K. Rosendahl and
D. K. McNeill and
R. D. McLeod Competitive learning algorithms and
neurocomputer architecture . . . . . . . 847--858
J. Cortadella and
M. Kishinevsky and
L. Lavagno and
A. Yakovlev Deriving Petri nets from finite
transition systems . . . . . . . . . . . 859--882
Huapeng Wu and
M. A. Hasan Low complexity bit-parallel multipliers
for a class of finite fields . . . . . . 883--887
Jie Wu and
Guanghui Guo Fault tolerance measures for $m$-ary
$n$-dimensional hypercubes based on
forbidden faulty sets . . . . . . . . . 888--893
R. Rovatti and
M. Borgatti and
R. Guerrieri A geometric approach to maximum-speed
$n$-dimensional continuous linear
interpolation in rectangular grids . . . 894--899
Yuanyuan Yang A class of interconnection networks for
multicasting . . . . . . . . . . . . . . 899--906
S. Reches and
S. Weiss Implementation and analysis of path
history in dynamic branch prediction
schemes . . . . . . . . . . . . . . . . 907--912
J. S. Moore and
T. W. Lynch and
M. Kaufmann A mechanically checked proof of the
AMD5$_K$ 86\TM floating-point division
program . . . . . . . . . . . . . . . . 913--926
R. M. Jessani and
M. Putrino Comparison of Single- and Dual-Pass
Multiply-Add Fused Floating-Point Units 927--937
G. Drolet A new representation of elements of
finite fields $\mathrm{GF}(2^m)$
yielding small complexity arithmetic
circuits . . . . . . . . . . . . . . . . 938--946
A. F. Gonzalez and
P. Mazumder Multiple-valued signed digit adder using
negative differential resistance devices 947--959
M. A. Hasan Double-basis multiplicative inversion
over $\mathrm{GF}(2^m)$ . . . . . . . . 960--970
Z. Zilic and
Z. G. Vranesic Using decision diagrams to design ULMs
for FPGAs . . . . . . . . . . . . . . . 971--982
Tsern-Huei Lee and
Jin-Jye Chou Some topological properties of bitonic
sorters . . . . . . . . . . . . . . . . 983--997
G. Gravenstreter and
R. G. Melhem Realizing common communication patterns
in partitioned optical passive stars
(POPS) networks . . . . . . . . . . . . 998--1013
L. A. Montalvo and
K. K. Parhi and
A. Guyot New Svoboda--Tung division . . . . . . . 1014--1020
Chin-Long Wey and
Ming-Der Shieh Design of a high-speed square generator 1021--1026
S. K. Baruah and
M. E. Hickey Competitive on-line scheduling of
imprecise computations . . . . . . . . . 1027--1032
J. Agrawal and
Yixin Zhang A fast and low cost self-routing
permutation network . . . . . . . . . . 1033--1036
D. S. Phatak Comments on Duprat and Muller's
branching CORDIC paper . . . . . . . . . 1037--1040
F. Dahlgren and
M. Dubois and
P. Stenstrom Performance evaluation and cost analysis
of cache protocol extensions for
shared-memory multiprocessors . . . . . 1041--1055
S. K. Reinhardt and
R. W. Pfile and
D. A. Wood Hardware support for flexible
distributed shared memory . . . . . . . 1056--1072
T. E. Truman and
T. Pering and
R. Doering and
R. W. Brodersen The InfoPad multimedia terminal: a
portable device for wireless information
access . . . . . . . . . . . . . . . . . 1073--1087
J. Rexford and
J. Hall and
K. G. Shin A router architecture for real-time
communication in multicomputer networks 1088--1101
M. Pandya and
M. Malek Minimum achievable utilization for
fault-tolerant processing of periodic
tasks . . . . . . . . . . . . . . . . . 1102--1112
J. H. Slye and
E. N. Elnozahy Support for software interrupts in
log-based rollback-recovery . . . . . . 1113--1123
I. Pomeranz and
S. M. Reddy Location of stuck-at faults and bridging
faults based on circuit partitioning . . 1124--1135
Lan Zhao and
D. M. H. Walker and
F. Lombardi I$_{\rm DDQ}$ testing of bridging faults
in logic resources of reconfigurable
field programmable gate arrays . . . . . 1136--1152
M. G. Kuhn Cipher instruction search attack on the
bus-encryption security microcontroller
DS5002FP . . . . . . . . . . . . . . . . 1153--1157
R. Libeskindg-Hadas A tight lower bound on the number of
channels required for deadlock-free
wormhole routing . . . . . . . . . . . . 1158--1160
Jyh-Huei Guo and
Chin-Liang Wang Systolic array implementation of
Euclid's algorithm for inversion and
division in $\mathrm{GF}(2^m)$ . . . . . 1161--1167
K. Chakrabarty and
B. T. Murray and
J. P. Hayes Optimal zero-aliasing space compaction
of test responses . . . . . . . . . . . 1171--1187
J. Rajski and
J. Tyszer and
N. Zacharia Test data decompression for multiple
scan designs with boundary scan . . . . 1188--1200
H. A. Al-Twaijry and
M. J. Flynn Technology scaling effects on
multipliers . . . . . . . . . . . . . . 1201--1215
N. Takagi Powering by a table look-up and a
multiplication with operand modification 1216--1222
H. Wu and
M. A. Hasan and
I. F. Blake New low-complexity bit-parallel finite
field multipliers using weakly dual
bases . . . . . . . . . . . . . . . . . 1223--1234
Vincent Lef\`evre and
Jean-Michel Muller and
Arnaud Tisserand Toward correctly rounded transcendentals 1235--1243
R. Manohar and
J. A. Tierno Asynchronous parallel prefix computation 1244--1252
Jun-Dong Cho and
S. Raje and
M. Sarrafzadeh Fast approximation algorithms on maxcut,
$k$-coloring, and $k$-color ordering for
VLSI applications . . . . . . . . . . . 1253--1266
J. D. Fix and
R. E. Ladner Sorting by parallel insertion on a
one-dimensional subbus array . . . . . . 1267--1281
A. L. Oliveira and
L. P. Carloni and
T. Villa and
A. L. Sangiovanni-Vincentelli Exact minimization of binary decision
diagrams using implicit techniques . . . 1282--1296
A. Papakostas and
I. G. Tollis Interactive orthogonal graph drawing . . 1297--1309
T. Carpenter and
S. Cosares and
J. L. Ganley and
I. Saniee A simple approximation algorithm for two
problems in circuit design . . . . . . . 1310--1312
E. Fujiwara and
T. Ritthongpitak and
M. Kitakami Optimal two-level unequal error control
codes for computer systems . . . . . . . 1313--1325
Ching-Tien Ho and
J. Bruck and
R. Agrawal Partial-sum queries in OLAP data cubes
using covering codes . . . . . . . . . . 1326--1340
R. Baldoni A positive acknowledgment protocol for
causal broadcasting . . . . . . . . . . 1341--1350
M. K. Reiter and
S. G. Stubblebine Resilient authentication using path
independence . . . . . . . . . . . . . . 1351--1362
J. Torrellas and
Chun Xia and
R. L. Daigle Optimizing the instruction cache
performance of the operating system . . 1363--1381
S. Banerjia and
S. W. Sathaye and
K. N. Menezes and
T. M. Conte MPS: miss-path scheduling for
multiple-issue processors . . . . . . . 1382--1397
R. Drechsler and
B. Becker and
A. Jahnke On variable ordering and decomposition
type choice in OKFDDs . . . . . . . . . 1398--1403
Feng Cao and
D. H. C. Du and
A. Pavan Topological embedding into WDM optical
passive star networks with tunable
transmitters of limited tuning range . . 1404--1413
M. S. Elsaholy and
S. I. Shaheen and
R. H. Seireg A unified analytical expression for
aliasing error probability using
single-input external- and internal-XOR
LFSR . . . . . . . . . . . . . . . . . . 1414--1417
D. Sundararajan and
M. O. Ahmad Index mapping approach of deriving the
PM DFT algorithms . . . . . . . . . . . 1418--1424
J. C. Lo Correction to ``A Fast Binary Adder with
Conditional Carry Generation'' . . . . . 1425--1425
N. Nicolici and
B. M. Al-Hashimi Correction to ``The Proof of Theorem 2
In `Parallel Signature Analysis Design
With Bounds On Allasing''' . . . . . . . 1426--1426
Anonymous 1998 Index IEEE Transactions On
Computers --- Author Index . . . . . . . 1427--1431
Anonymous Subject Index . . . . . . . . . . . . . 1431--1440
A. Nannarelli and
T. Lang Low-Power Divider . . . . . . . . . . . 2--14
K. Z. Pekmestzi Multiplexer-based array multipliers . . 15--23
A. W. Tomita and
K. Sakamura Improving design dependability by
exploiting an open model-based
specification . . . . . . . . . . . . . 24--37
A. Savva and
T. Nanya A gracefully degrading massively
parallel system using the BSP model, and
its evaluation . . . . . . . . . . . . . 38--52
C. A. Healy and
R. D. Arnold and
F. Mueller and
D. B. Whalley and
M. G. Harmon Bounding pipeline and instruction cache
performance . . . . . . . . . . . . . . 53--70
Hoang Pham and
Xuemei Zhang A software cost model with warranty and
risk costs . . . . . . . . . . . . . . . 71--75
N. Takagi and
T. Horiyama A high-speed reduced-size adder under
left-to-right input arrival . . . . . . 76--80
Yuh-Rong Leu and
Sy-Yen Kuo Distributed fault-tolerant ring
embedding and reconfiguration in
hypercubes . . . . . . . . . . . . . . . 81--88
Feng Cao and
Ding-Zhu Du and
F. Hsu and
Shang-Hua Teng Fault tolerance properties of pyramid
networks . . . . . . . . . . . . . . . . 88--93
V. Milutinovic and
M. Valero Guest Editors' Introduction: Cache
Memory and Related Problems: Enhancing
and Exploiting the Locality . . . . . . 97--99
Jih-Kwon Peir and
W. W. Hsu and
A. J. Smith Functional implementation techniques for
CPU cache memories . . . . . . . . . . . 100--110
E. Rotenberg and
S. Bennett and
J. E. Smith A trace cache microarchitecture and
evaluation . . . . . . . . . . . . . . . 111--120
D. Joseph and
D. Grunwald Prefetching using Markov predictors . . 121--133
Chi-Keung Luk and
T. C. Mowry Automatic compiler-inserted prefetching
for pointer-based applications . . . . . 134--141
P. R. Panda and
H. Nakamura and
N. D. Dutt and
A. Nicolau Augmenting loop tiling with data
alignment for improved cache performance 142--149
O. Temam An algorithm for optimally exploiting
spatial and temporal locality in upper
memory levels . . . . . . . . . . . . . 150--158
M. Kandemir and
J. Ramanujam and
A. Choudhary Improving cache locality by a
combination of loop and data
transformations . . . . . . . . . . . . 159--167
J. Kalamatianos and
A. Khalafi and
D. R. Kaeli and
W. Meleis Analysis of temporal-based program
behavior for improved instruction cache
performance . . . . . . . . . . . . . . 168--175
H. Kwak and
B. Lee and
A. R. Hurson and
Suk-Han Yoon and
Woo-Jong Hahn Effects of multithreading on cache
performance . . . . . . . . . . . . . . 176--184
N. Topham and
A. Gonzalez Randomized cache placement for
eliminating conflicts . . . . . . . . . 185--192
S. J. Patel and
D. H. Friendly and
Y. N. Patt Evaluation of design options for the
trace cache fetch mechanism . . . . . . 193--204
M. Heinrich and
V. Soundararajan and
J. Hennessy and
A. Gupta A quantitative analysis of the
performance and scalability of
distributed shared memory cache
coherence protocols . . . . . . . . . . 205--217
V. S. Pai and
P. Ranganathan and
H. Abdel-Shafi and
S. Adve The impact of exploiting
instruction-level parallelism on
shared-memory multiprocessors . . . . . 218--226
Seungjoon Park and
D. L. Dill An executable specification and verifier
for relaxed memory order . . . . . . . . 227--235
Dongai Dai and
D. K. Panda Exploiting the benefits of multiple-path
network in DSM systems: architectural
alternatives and performance evaluation 236--244
M. M. Michael and
A. K. Nanda and
Beng-Hong Lim Coherence controller architectures for
scalable shared-memory multiprocessors 245--255
Zheng Zhang and
M. Cintra and
J. Torrellas Excel-NUMA: toward programmability,
simplicity, and high performance . . . . 256--264
Yuanyuan Yang and
Jianchao Wang Wide-sense nonblocking Clos networks
under packing strategy . . . . . . . . . 265--284
K. Cattell and
Shujian Zhang and
M. Serra and
J. C. Muzio $2$-by-$n$ hybrid cellular automata with
regular configuration: theory and
application . . . . . . . . . . . . . . 285--295
F. Luccio and
L. Pagli On a new Boolean function with
applications . . . . . . . . . . . . . . 296--310
M. S. Hsiao and
E. M. Rudnick and
J. H. Patel Fast static compaction algorithms for
sequential circuit test vectors . . . . 311--322
E. M. Rudnick and
J. H. Patel Efficient techniques for dynamic test
sequence compaction . . . . . . . . . . 323--330
Tong Sun and
Qing Yang A comparative analysis of cache designs
for vector processing . . . . . . . . . 331--344
A. Bernasconi and
B. Codenotti Spectral analysis of Boolean functions
as a graph eigenvalue problem . . . . . 345--351
Yeimkuan Chang and
L. N. Bhuyan An efficient tree cache coherence
protocol for distributed shared memory
multiprocessors . . . . . . . . . . . . 352--360
R. Battiti and
A. A. Bertossi Greedy, prohibition, and reactive
heuristics for graph partitioning . . . 361--385
Chung-Ho Chen and
A. K. Somani Fault-containment in cache memories for
TMR redundant processor systems . . . . 386--397
L. E. LaForge Configuration of locally spared arrays
in the presence of multiple fault types 398--416
B. P. Dave and
N. K. Jha COFTA: hardware-software co-synthesis of
heterogeneous distributed embedded
systems for low overhead fault tolerance 417--441
M. J. Liebelt and
N. Burgess Detecting exitory stuck-at faults in
semimodular asynchronous circuits . . . 442--448
A. M. Dal Corral and
J. M. Llaberia Minimizing conflicts between vector
streams in interleaved memory systems 449--456
Chien-Ming Chen and
Chung-Ta King Walk-time address adjustment for
improving the accuracy of dynamic branch
prediction . . . . . . . . . . . . . . . 457--469
D. M. Blough and
H. W. Brown The broadcast comparison model for
on-line fault diagnosis in multicomputer
systems: theory and implementation . . . 470--493
Chun Xia and
J. Torrellas Comprehensive hardware and software
support for operating systems to exploit
MP memory hierarchies . . . . . . . . . 494--505
J. P. Marques-Silva and
K. A. Sakallah GRASP: a search algorithm for
propositional satisfiability . . . . . . 506--521
B. Sunar and
Ç. K. Koç Mastrovito multiplier for all trinomials 522--527
K. Kanoun and
M. Borrel and
T. Morteveille and
A. Peytavin Availability of CAUTRA, a subset of the
French air traffic control system . . . 528--535
D. Das and
M. De and
B. P. Sinha A new network topology with multiple
meshes . . . . . . . . . . . . . . . . . 536--551
J. Gaudiot and
F. Lombardi Guest Editors' introduction . . . . . . 553--555
E. Sanchez and
M. Sipper and
J.-O. Haenni and
J.-L. Beuchat and
A. Stauffer and
A. Perez-Uribe Static and dynamic configurable systems 556--564
D. Chang and
M. Marek-Sadowska Partitioning sequential circuits on
dynamically reconfigurable FPGAs . . . . 565--578
K. M. G. Purna and
D. Bhatia Temporal partitioning and scheduling
data flow graphs for reconfigurable
computers . . . . . . . . . . . . . . . 579--590
J. S. N. Jean and
K. Tomko and
V. Yavagal and
J. Shah and
R. Cook Dynamic reconfiguration to support
concurrent applications . . . . . . . . 591--602
Hoon Choi and
Jong-Sun Kim and
Chi-Won Yoon and
In-Cheol Park and
Sung Ho Hwang and
Chong-Min Kyung Synthesis of application specific
instructions for embedded DSP software 603--614
C. Thibeault and
G. Begin A scan-based configurable, programmable,
and scalable architecture for sliding
window-based operations . . . . . . . . 615--627
M. Murakawa and
S. Yoshizawa and
I. Kajitani and
X. Yao and
N. Kajihara and
M. Iwata and
T. Higuchi The GRD chip: genetic reconfiguration of
DSPs for neural network processing . . . 628--639
P. D. Fiore Parallel multiplication using fast
sorting networks . . . . . . . . . . . . 640--645
T. M. Pinkston Flexible and efficient routing based on
progressive deadlock recovery . . . . . 649--669
M. W. Goudreau and
K. Lang and
S. B. Rao and
T. Suel and
T. Tsantilas Portable and efficient parallel
computing using the BSP model . . . . . 670--689
Chih-Wei Liu and
Kuo-Tai Huang and
Chung-Chin Lu A systolic array implementation of the
Feng--Rao algorithm . . . . . . . . . . 690--706
M. Cukier and
D. Powell and
J. Ariat Coverage estimation methods for
stratified fault-injection . . . . . . . 707--723
J. Rajski and
J. Tyszer Diagnosis of scan cells in BIST
environment . . . . . . . . . . . . . . 724--731
Jenn-Yang Ke and
Jong-Chuang Tsay An approach to checking link conflicts
in the mapping of uniform dependence
algorithms into lower dimensional
processor arrays . . . . . . . . . . . . 732--737
S. Q. Zheng and
M. Sun Constructing optimal search trees in
optimal time . . . . . . . . . . . . . . 738--743
T. Harada and
M. Yamashita Improving the availability of mutual
exclusion systems on incomplete networks 744--747
A. Garcia and
A. Lloris A look-up scheme for scaling in the RNS 748--751
S. S. H. Tse and
F. C. M. Lau On the space requirement of interval
routing . . . . . . . . . . . . . . . . 752--757
Qian-Yu Tang and
Xiaoyu Song Diagnosis of parallel computers
arbitrary connectivity . . . . . . . . . 757--761
P. Prabhakaran and
P. Banerjee Parallel algorithms for force directed
scheduling of flattened and hierarchical
signal flow graphs . . . . . . . . . . . 762--768
L. Benini and
G. De Micheli and
A. Lioy and
E. Macii and
G. Odasso and
M. Poncino Automatic synthesis of large telescopic
units based on near-minimum timed
supersetting . . . . . . . . . . . . . . 769--779
Chung-Ho Chen and
Feng-Fu Lin An easy-to-use approach for practical
bus-based system design . . . . . . . . 780--793
L. G. Tallini and
B. Bose Balanced codes with parallel encoding
and decoding . . . . . . . . . . . . . . 794--814
Wen-Feng Chang and
Cheng-Wen Wu Low-cost modular totally self-checking
checker design for $m$-out-of-$n$ code 815--826
T. Lang and
P. Montuschi Very high radix square root with
prescaling and rounding and a combined
division/square root unit . . . . . . . 827--841
M. J. Schulte and
J. E. Stine Approximating Elementary Functions with
Symmetric Bipartite Tables . . . . . . . 842--847
Huapeng Wu and
M. A. Hasan Closed-form expression for the average
weight of signed-digit representations 848--851
R. Conway and
J. Nelson Fast converter for 3 moduli RNS using
new property of CRT . . . . . . . . . . 852--860
B. J. Falkowski A note on the polynomial form of Boolean
functions and related topics . . . . . . 860--864
V. Krishnan and
J. Torrellas A chip-multiprocessor architecture with
speculative multithreading . . . . . . . 866--880
Jenn-Yuan Tsai and
Jian Huang and
C. Amlo and
D. J. Lilja and
Pen-Chung Yew The superthreaded processor architecture 881--902
S. W. Kekckler and
A. Chang and
W. S. L. S. Chatterjee and
W. J. Dally Concurrent event handling through
multithreading . . . . . . . . . . . . . 903--916
A. Raha and
S. Kamat and
Xiaohua Jia and
Wei Zhao Using traffic regulation to meet
end-to-end deadlines in ATM networks . . 917--935
D. Gizopoulos and
A. Paschalis and
Y. Zorian An effective built-in self-test scheme
for parallel multipliers . . . . . . . . 936--950
F. Marino and
E. Swartzlander, Jr. Parallel implementation of
multidimensional transforms without
interprocessor communication . . . . . . 951--960
Shih-Chieh Chang and
L. P. P. P. Van Ginneken and
M. Marek-Sadowska Circuit optimization by rewiring . . . . 962--970
J. Lafferty and
A. Vardy Ordered binary decision diagrams and
minimal trellises . . . . . . . . . . . 971--986
R. Drechsler Pseudo-Kronecker expressions for
symmetric functions . . . . . . . . . . 987--990
S. Rahardja and
B. J. Falkowski Fast linearly independent arithmetic
expansions . . . . . . . . . . . . . . . 991--999
P. Pan and
C. L. Liu Partial scan with preselected scan
signals . . . . . . . . . . . . . . . . 1000--1005
J. S. Harper and
D. J. Kerbyson and
G. R. Nudd Analytical modeling of set-associative
cache behavior . . . . . . . . . . . . . 1009--1024
C. Paar and
P. Fleischmann and
P. Soria-Rodriguez Fast arithmetic for public-key
algorithms in Galois fields with
composite exponents . . . . . . . . . . 1025--1034
G. C. Buttazzo and
F. Sensini Optimal deadline assignment for
scheduling soft aperiodic tasks in hard
real-time environments . . . . . . . . . 1035--1052
G. H. Chisholm and
A. S. Wojcik An application of formal analysis to
software in a fault-tolerant environment 1053--1064
Yu-Chee Tseng and
Sze-Yao Ni and
Jang-Ping Sheu Toward optimal complete exchange on
wormhole-routed tori . . . . . . . . . . 1065--1082
J. D. Bruguera and
T. Lang Leading-one prediction with concurrent
position correction . . . . . . . . . . 1083--1097
V. S. Dimitrov and
G. A. Jullien and
W. C. Miller Theory and Applications of the
Double-Base Number System . . . . . . . 1098--1106
Guang-Ming Wu and
Yao-Wen Chang Quasi-universal switch matrices for FPD
design . . . . . . . . . . . . . . . . . 1107--1122
S. Fujita A fault-tolerant broadcast scheme in the
star graph under the single-port,
half-duplex communication model . . . . 1123--1126
P. P. Chakrabarti Partial precedence constrained
scheduling . . . . . . . . . . . . . . . 1127--1130
G. Panchapakesan and
A. Sengupta On a lightwave network topology using
Kautz digraphs . . . . . . . . . . . . . 1131--1137
D. Nikolos and
H. T. Vergos On the yield of VLSI processors with
on-chip CPU cache . . . . . . . . . . . 1138--1144
I. Pomeranz and
S. M. Reddy A cone-based genetic optimization
procedure for test generation and its
application to $n$-detections in
combinational circuits . . . . . . . . . 1145--1152
A. M. Nielsen and
P. Kornerup Redundant radix representations of rings 1153--1165
B. Sericola Availability analysis of repairable
computer systems and stationarity
detection . . . . . . . . . . . . . . . 1166--1172
K. E. Hoganson Workload execution strategies and
parallel speedup on clustered computers 1173--1182
T. K. Tsai and
Mei-Chen Hsueh and
Hong Zhao and
Z. Kalbarczyk and
R. K. Iyer Stress-based and path-based fault
injection . . . . . . . . . . . . . . . 1183--1201
S. P. Dandamudi and
S. Ayachi Performance of hierarchical processor
scheduling in shared-memory
multiprocessor systems . . . . . . . . . 1202--1213
Yuanyuan Yang and
G. M. Masson The necessary conditions for Clos-type
nonblocking multicast networks . . . . . 1214--1227
C.-J. J. Hou Routing virtual circuits with temporal
QoS requirements in virtual path-based
ATM networks . . . . . . . . . . . . . . 1228--1243
E. S. Tam and
J. A. Rivers and
V. Srinivasan and
G. S. Tyson and
E. S. Davidson Active management of data caches by
exploiting reuse information . . . . . . 1244--1259
K. Skadron and
P. S. Ahuja and
M. Martonosi and
D. W. Clark Branch prediction, instruction-window
size, and cache size: performance
trade-offs and simulation techniques . . 1260--1281
Yu-Chee Tseng and
Ming-Hour Yang and
Tong-Ying Juang Achieving fault-tolerant multicast in
injured wormhole-routed tori and meshes
based on Euler path construction . . . . 1282--1296
M. Ould-Khaoua A performance model for Duato's fully
adaptive routing algorithm in $k$-ary
$n$-cubes . . . . . . . . . . . . . . . 1297--1304
F. Fummi and
D. Sciuto and
M. Serra Synthesis for testability of highly
complex controllers by functional
redundancy removal . . . . . . . . . . . 1305--1323
J. F. Ramos and
A. G. Bohorquez Two operand binary adders with threshold
logic . . . . . . . . . . . . . . . . . 1324--1337
T. L. Johnson and
D. A. Connors and
M. C. Merten and
W.-M. W. Hwu Run-time cache bypassing . . . . . . . . 1338--1354
X. Yuan and
R. Melhem and
R. Gupta Distributed path reservation algorithms
for multiplexed all-optical
interconnection networks . . . . . . . . 1355--1363
J. Savir Distributed generation of weighted
random patterns . . . . . . . . . . . . 1364--1368
D. Wang Diagnosability of hypercubes and
enhanced hypercubes under the comparison
diagnosis model . . . . . . . . . . . . 1369--1374
M. A. Iverson and
F. Ozguner and
L. Potter Statistical prediction of task execution
times through analytic benchmarking for
scheduling in a heterogeneous
environment . . . . . . . . . . . . . . 1374--1379
Anonymous Author Index . . . . . . . . . . . . . . 1380--1384
Anonymous Subject Index . . . . . . . . . . . . . 1384--1392
Ping Tak Peter Tang Table-Driven Implementation of the \tt
Expm1 Function in IEEE Floating-Point
Arithmetic . . . . . . . . . . . . . . . 211--222