# bibtab

bibtype: inproceedings
filename: fparith.bib
label: Boldo:2007:PCA
author: Sylvie Boldo and Marc Daumas and William Kahan and Guillaume Melquiond
title: Proof and certification of an accurate discriminant
crossref: Luther:2007:GII
pages: ??--??
year: 2007
bibdate: Wed Jun 24 22:27:02 2009
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2009.06.24 22:27:02 ???
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo and Marc Daumas and William Kahan and Guillaume Melquiond
rawtitle: Proof and certification of an accurate discriminant
entry:
@InProceedings{Boldo:2007:PCA,
  author =       "Sylvie Boldo and Marc Daumas and William Kahan and
                 Guillaume Melquiond",
  title =        "Proof and certification of an accurate discriminant",
  crossref =     "Luther:2007:GII",
  pages =        "??--??",
  year =         "2007",
  bibdate =      "Wed Jun 24 22:27:02 2009",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Brent:2007:EBC
author: Richard Brent and Colin Percival and Paul Zimmermann
title: Error bounds on complex floating-point multiplication
journal: j-MATH-COMPUT
volume: 76
number: 259
pages: 1469--1481
year: 2007
CODEN: MCMPAF
DOI: https://doi.org/10.1090/S0025-5718-07-01931-X
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
MRclass: 65G50
MRnumber: MR2299783 (2008b:65062)
bibdate: Thu Nov 8 19:16:14 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 19:16:14 ???
fjournal: Mathematics of Computation
keywords: rounding errors
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Richard Brent and Colin Percival and Paul Zimmermann
rawtitle: Error bounds on complex floating-point multiplication
abstract:
Given floating-point arithmetic with $t$-digit base-$ beta $ significands in which all arithmetic operations are performed as if calculated to infinite precision and rounded to a nearest representable value, we prove that the product of complex values $ z_0 $ and $ z_1 $ can be computed with maximum absolute error $ vert z_0 Vert z_1 vert frac 12 beta ^1 - t sqrt 5 $. In particular, this provides relative error bounds of $ 2^-24 sqrt 5 $ and $ 2^-53 sqrt 5 $ for IEEE 754 single and double precision arithmetic respectively, provided that overflow, underflow, and denormals do not occur. We also provide the numerical worst cases for IEEE 754 single and double precision arithmetic.

rawabstract:
Given floating-point arithmetic with $t$-digit base-$ \beta $ significands in which all arithmetic operations are performed as if calculated to infinite precision and rounded to a nearest representable value, we prove that the product of complex values $ z_0 $ and $ z_1 $ can be computed with maximum absolute error $ \vert z_0 \Vert z_1 \vert \frac {1}{2} \beta^{1 - t} \sqrt {5} $. In particular, this provides relative error bounds of $ 2^{-24} \sqrt {5} $ and $ 2^{-53} \sqrt {5} $ for IEEE 754 single and double precision arithmetic respectively, provided that overflow, underflow, and denormals do not occur. We also provide the numerical worst cases for IEEE 754 single and double precision arithmetic.

entry:
@Article{Brent:2007:EBC,
  author =       "Richard Brent and Colin Percival and Paul Zimmermann",
  title =        "Error bounds on complex floating-point
                 multiplication",
  journal =      j-MATH-COMPUT,
  volume =       "76",
  number =       "259",
  pages =        "1469--1481",
  year =         "2007",
  CODEN =        "MCMPAF",
  DOI =          "https://doi.org/10.1090/S0025-5718-07-01931-X",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  MRclass =      "65G50",
  MRnumber =     "MR2299783 (2008b:65062)",
  bibdate =      "Thu Nov 8 19:16:14 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Given floating-point arithmetic with $t$-digit base-$
                 \beta $ significands in which all arithmetic operations
                 are performed as if calculated to infinite precision
                 and rounded to a nearest representable value, we prove
                 that the product of complex values $ z_0 $ and $ z_1 $
                 can be computed with maximum absolute error $ \vert z_0
                 \Vert z_1 \vert \frac {1}{2} \beta^{1 - t} \sqrt {5} $.
                 In particular, this provides relative error bounds of $
                 2^{-24} \sqrt {5} $ and $ 2^{-53} \sqrt {5} $ for IEEE
                 754 single and double precision arithmetic
                 respectively, provided that overflow, underflow, and
                 denormals do not occur. We also provide the numerical
                 worst cases for IEEE 754 single and double precision
                 arithmetic.",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
  keywords =     "rounding errors",
}


bibtype: article
filename: fparith.bib
label: Brisebarre:2007:CRA
author: Nicolas Brisebarre and Jean-Michel Muller
title: Correct rounding of algebraic functions
journal: j-INFORM-THEOR-APPL
volume: 41
number: 1
pages: 71--83
month: jan
monthnumber: 1
year: 2007
CODEN: RSITD7, RITAE4
DOI: https://doi.org/10.1051/ita:2007002
ISSN: 0988-3754 (print), 1290-385X (electronic) OR 09883754 (print), 1290385X (electronic)
ISSNL: 0988-3754 OR 09883754
bibdate: Fri Dec 8 09:49:12 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.08 09:49:12 ???
fjournal: RAIRO. Informatique theorique et applications := Theoretical informatics and applications
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Jean-Michel Muller
rawtitle: Correct rounding of algebraic functions
entry:
@Article{Brisebarre:2007:CRA,
  author =       "Nicolas Brisebarre and Jean-Michel Muller",
  title =        "Correct rounding of algebraic functions",
  journal =      j-INFORM-THEOR-APPL,
  volume =       "41",
  number =       "1",
  pages =        "71--83",
  month =        jan,
  year =         "2007",
  CODEN =        "RSITD7, RITAE4",
  DOI =          "https://doi.org/10.1051/ita:2007002",
  ISSN =         "0988-3754 (print), 1290-385X (electronic)",
  ISSN-L =       "0988-3754",
  bibdate =      "Fri Dec 8 09:49:12 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "RAIRO. Informatique th{\'e}orique et applications :=
                 Theoretical informatics and applications",
}


bibtype: inproceedings
filename: fparith.bib
label: Brisebarre:2007:EPA
author: Nicolas Brisebarre and Sylvain Chevillard
title: Efficient polynomial $ L^infty $-approximations
crossref: Kornerup:2007:PIS
pages: 169--176
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.17
bibdate: Tue Oct 9 17:16:03 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 17:16:03 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Sylvain Chevillard
rawtitle: Efficient polynomial {$ L^\infty $}-approximations
abstract:
We address the problem of computing a good floating-point-coefficient polynomial approximation to a function, with respect to the supremum norm. This is a key step in most processes of evaluation of a function. We present a fast and efficient method, based on lattice basis reduction, that often gives the best polynomial possible and most of the time returns a very good approximation.

rawabstract:
We address the problem of computing a good floating-point-coefficient polynomial approximation to a function, with respect to the supremum norm. This is a key step in most processes of evaluation of a function. We present a fast and efficient method, based on lattice basis reduction, that often gives the best polynomial possible and most of the time returns a very good approximation.

entry:
@InProceedings{Brisebarre:2007:EPA,
  author =       "Nicolas Brisebarre and Sylvain Chevillard",
  title =        "Efficient polynomial {$ L^\infty $}-approximations",
  crossref =     "Kornerup:2007:PIS",
  pages =        "169--176",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.17",
  bibdate =      "Tue Oct 9 17:16:03 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We address the problem of computing a good
                 floating-point-coefficient polynomial approximation to
                 a function, with respect to the supremum norm. This is
                 a key step in most processes of evaluation of a
                 function. We present a fast and efficient method, based
                 on lattice basis reduction, that often gives the best
                 polynomial possible and most of the time returns a very
                 good approximation.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: inproceedings
filename: fparith.bib
label: Brisebarre:2007:FPA
author: Nicolas Brisebarre and Guillaume Hanrot
title: Floating-point $ L^2 $-approximations to functions
crossref: Kornerup:2007:PIS
pages: 177--186
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.38
bibdate: Tue Oct 9 17:16:03 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 17:16:03 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Guillaume Hanrot
rawtitle: Floating-point {$ L^2 $}-approximations to functions
abstract:
In the present paper, we investigate the approximation of a function by a polynomial with floating-point coefficients; we are looking for the best approximation in the $ L^2 $ sense. Finding a best polynomial $ L^2 $-approximation with real coefficients is an easy exercise about orthogonal projections. However, truncating the coefficients to floating-point numbers, which is needed for further computations, makes the approximation way worse. Hence, we study the problem of computing best approximations under the constraint that coefficients are floating-point numbers. We show that the corresponding problem is NP-hard, by reduction to the CVP problem. We investigate the practical behaviour of exact and approximate algorithms for this problem. The conclusion is that it is possible in a short amount of time to obtain a relative or absolute best $ L^2 $-approximation. The main applications are for large dimension, as a preliminary step of finding $L$-approximations and for functions with large variations, for which relative best approximation is by far more interesting than absolute.

rawabstract:
In the present paper, we investigate the approximation of a function by a polynomial with floating-point coefficients; we are looking for the best approximation in the $ L^2 $ sense. Finding a best polynomial $ L^2 $-approximation with real coefficients is an easy exercise about orthogonal projections. However, truncating the coefficients to floating-point numbers, which is needed for further computations, makes the approximation way worse. Hence, we study the problem of computing best approximations under the constraint that coefficients are floating-point numbers. We show that the corresponding problem is NP-hard, by reduction to the CVP problem. We investigate the practical behaviour of exact and approximate algorithms for this problem. The conclusion is that it is possible in a short amount of time to obtain a relative or absolute best $ L^2 $-approximation. The main applications are for large dimension, as a preliminary step of finding $L$-approximations and for functions with large variations, for which relative best approximation is by far more interesting than absolute.

entry:
@InProceedings{Brisebarre:2007:FPA,
  author =       "Nicolas Brisebarre and Guillaume Hanrot",
  title =        "Floating-point {$ L^2 $}-approximations to functions",
  crossref =     "Kornerup:2007:PIS",
  pages =        "177--186",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.38",
  bibdate =      "Tue Oct 9 17:16:03 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In the present paper, we investigate the approximation
                 of a function by a polynomial with floating-point
                 coefficients; we are looking for the best approximation
                 in the $ L^2 $ sense. Finding a best polynomial $ L^2
                 $-approximation with real coefficients is an easy
                 exercise about orthogonal projections. However,
                 truncating the coefficients to floating-point numbers,
                 which is needed for further computations, makes the
                 approximation way worse. Hence, we study the problem of
                 computing best approximations under the constraint that
                 coefficients are floating-point numbers. We show that
                 the corresponding problem is NP-hard, by reduction to
                 the CVP problem. We investigate the practical behaviour
                 of exact and approximate algorithms for this problem.
                 The conclusion is that it is possible in a short amount
                 of time to obtain a relative or absolute best $ L^2
                 $-approximation. The main applications are for large
                 dimension, as a preliminary step of finding
                 $L$-approximations and for functions with large
                 variations, for which relative best approximation is by
                 far more interesting than absolute.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: inproceedings
filename: fparith.bib
label: Burgess:2007:DAV
author: Neil Burgess and Chris N. Hinds
title: Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell
crossref: Kornerup:2007:PIS
pages: 87--96
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.15
bibdate: Tue Oct 9 16:32:41 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 16:32:41 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Neil Burgess and Chris N. Hinds
rawtitle: Design of the {ARM VFP11} Divide and Square Root Synthesisable Macrocell
abstract:
This paper presents the detailed design of the ARM VFP11 Divide and Square Root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit recurrence algorithm, and this paper describes a novel acceleration technique employed to achieve the required processor clock frequency of up to 750MHz in 90nm CMOS. Logical Effort theory is used to provide a delay analysis of the unit, which demonstrates the balanced nature of the two critical paths therein.

rawabstract:
This paper presents the detailed design of the ARM VFP11 Divide and Square Root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit recurrence algorithm, and this paper describes a novel acceleration technique employed to achieve the required processor clock frequency of up to 750MHz in 90nm CMOS. Logical Effort theory is used to provide a delay analysis of the unit, which demonstrates the balanced nature of the two critical paths therein.

entry:
@InProceedings{Burgess:2007:DAV,
  author =       "Neil Burgess and Chris N. Hinds",
  title =        "Design of the {ARM VFP11} Divide and Square Root
                 Synthesisable Macrocell",
  crossref =     "Kornerup:2007:PIS",
  pages =        "87--96",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.15",
  bibdate =      "Tue Oct 9 16:32:41 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents the detailed design of the ARM
                 VFP11 Divide and Square Root synthesisable macrocell.
                 The macrocell was designed using the minimum-redundancy
                 radix-4 SRT digit recurrence algorithm, and this paper
                 describes a novel acceleration technique employed to
                 achieve the required processor clock frequency of up to
                 750MHz in 90nm CMOS. Logical Effort theory is used to
                 provide a delay analysis of the unit, which
                 demonstrates the balanced nature of the two critical
                 paths therein.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: article
filename: fparith.bib
label: Ceberio:2007:ITA
title: Interval-type and affine arithmetic-type techniques for handling uncertainty in expert systems
journal: j-J-COMPUT-APPL-MATH
volume: 199
number: 2
pages: 403--410
day: 15
month: feb
monthnumber: 2
year: 2007
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:12:04 MST 2017
bibtimestamp: 2017.02.25 13:12:04 MST
URL: http://www.sciencedirect.com/science/article/pii/S037704270500779X
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawtitle: Interval-type and affine arithmetic-type techniques for handling uncertainty in expert systems
author:
Martine Ceberio and Vladik Kreinovich and Sanjeev Chopra and Luc Longpre and Hung T. Nguyen and Bertram Ludascher and Chitta Baral

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2005.bib

rawauthor:
Martine Ceberio and Vladik Kreinovich and Sanjeev Chopra and Luc Longpr{\'e} and Hung T. Nguyen and Bertram Lud{\"a}scher and Chitta Baral

entry:
@Article{Ceberio:2007:ITA,
  author =       "Martine Ceberio and Vladik Kreinovich and Sanjeev
                 Chopra and Luc Longpr{\'e} and Hung T. Nguyen and
                 Bertram Lud{\"a}scher and Chitta Baral",
  title =        "Interval-type and affine arithmetic-type techniques
                 for handling uncertainty in expert systems",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "199",
  number =       "2",
  pages =        "403--410",
  day =          "15",
  month =        feb,
  year =         "2007",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:12:04 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2005.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S037704270500779X",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: article
filename: fparith.bib
label: Chaves:2007:IRN
author: R. Chaves and L. Sousa
journal: IET Computers & Digital Techniques
volume: 1
number: 5
pages: 472--480
month: sep
monthnumber: 9
year: 2007
CODEN: ICDTEA, ICDTEX
DOI: https://doi.org/10.1049/iet-cdt:20060059
ISSN: 1751-8601 (print), 1751-861X (electronic) OR 17518601 (print), 1751861X (electronic)
ISSNL: 1751-8601 OR 17518601
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
ajournal: IEE Proc.-Comput. Digit. Tech
journalURL: https://digital-library.theiet.org/content/journals/iet-cdt;jsessionid=1s2tx6k4du6p5.x-iet-live-01
rawauthor: R. Chaves and L. Sousa
title:
Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures

URL:
http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4117424; http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=4312767

rawtitle:
Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures

entry:
@Article{Chaves:2007:IRN,
  author =       "R. Chaves and L. Sousa",
  title =        "Improving residue number system multiplication with
                 more balanced moduli sets and enhanced modular
                 arithmetic structures",
  journal =      "IET Computers \& Digital Techniques",
  volume =       "1",
  number =       "5",
  pages =        "472--480",
  month =        sep,
  year =         "2007",
  CODEN =        "ICDTEA, ICDTEX",
  DOI =          "https://doi.org/10.1049/iet-cdt:20060059",
  ISSN =         "1751-8601 (print), 1751-861X (electronic)",
  ISSN-L =       "1751-8601",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4117424;
                 http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=4312767",
  acknowledgement = ack-nhfb,
  ajournal =     "IEE Proc.-Comput. Digit. Tech",
  journal-URL =  "https://digital-library.theiet.org/content/journals/iet-cdt;jsessionid=1s2tx6k4du6p5.x-iet-live-01",
  keywords =     "residue arithmetic; residue number system",
}


bibtype: article
filename: fparith.bib
label: Chen:2007:NSA
author: Gang Chen and Guoqiang Bai and Hongyi Chen
title: A New Systolic Architecture for Modular Division
journal: j-IEEE-TRANS-COMPUT
volume: 56
number: 2
pages: 282--286
month: feb
monthnumber: 2
year: 2007
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.20
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:03:37 MDT 2011
bibtimestamp: 2011.07.04 15:03:37 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4042687
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Gang Chen and Guoqiang Bai and Hongyi Chen
rawtitle: A New Systolic Architecture for Modular Division
entry:
@Article{Chen:2007:NSA,
  author =       "Gang Chen and Guoqiang Bai and Hongyi Chen",
  title =        "A New Systolic Architecture for Modular Division",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "56",
  number =       "2",
  pages =        "282--286",
  month =        feb,
  year =         "2007",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.20",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:03:37 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4042687",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Cho:2007:BBL
author: Wendy K. Tam Cho and Brian J. Gaines
title: Breaking the (Benford) Law
journal: j-AMER-STAT
volume: 61
number: 3
pages: 218--223
month: aug
monthnumber: 8
year: 2007
CODEN: ASTAAJ
DOI: https://doi.org/10.1198/000313007X223496
ISSN: 0003-1305 (print), 1537-2731 (electronic) OR 00031305 (print), 15372731 (electronic)
ISSNL: 0003-1305 OR 00031305
bibdate: Thu Aug 26 21:48:27 MDT 2010
bibtimestamp: 2010.08.26 21:48:27 MDT
fjournal: The American Statistician
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/utas20
rawauthor: Wendy K. Tam Cho and Brian J. Gaines
rawtitle: Breaking the {(Benford) Law}
bibsource:
http://www.amstat.org/publications/tas/; https://www.math.utah.edu/pub/tex/bib/amstat.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Cho:2007:BBL,
  author =       "Wendy K. Tam Cho and Brian J. Gaines",
  title =        "Breaking the {(Benford) Law}",
  journal =      j-AMER-STAT,
  volume =       "61",
  number =       "3",
  pages =        "218--223",
  month =        aug,
  year =         "2007",
  CODEN =        "ASTAAJ",
  DOI =          "https://doi.org/10.1198/000313007X223496",
  ISSN =         "0003-1305 (print), 1537-2731 (electronic)",
  ISSN-L =       "0003-1305",
  bibdate =      "Thu Aug 26 21:48:27 MDT 2010",
  bibsource =    "http://www.amstat.org/publications/tas/;
                 https://www.math.utah.edu/pub/tex/bib/amstat.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "The American Statistician",
  journal-URL =  "http://www.tandfonline.com/loi/utas20",
}


bibtype: inproceedings
filename: fparith.bib
label: Cho:2007:SPM
author: Heumpil Cho and Earl E. Swartzlander, Jr.
title: Serial Parallel Multiplier Design in Quantum-dot Cellular Automata
crossref: Kornerup:2007:PIS
pages: 7--15
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.32
bibdate: Tue Oct 9 16:32:41 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 16:32:41 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Heumpil Cho and Earl E. {Swartzlander, Jr.}
rawtitle: Serial Parallel Multiplier Design in Quantum-dot Cellular Automata
abstract:
An emerging nanotechnology, quantum-dot cellular automata (QCA), has the potential for attractive features such as faster speed, smaller size, and lower power consumption than transistor based technology. Quantum-dot cellular automata has a simple cell as the basic element. The cell is used as a building block to construct gates, wires, and memories. Several adder designs have been proposed, but multiplier design in QCA is a rather unexplored research area. This paper utilizes the QCA characteristics to design serial parallel multipliers. Two types of serial parallel multipliers are designed and simulated with several different operand sizes. Those designs are compared in terms of complexity, area, and latency. The serial parallel multipliers have simple and regular structures.

rawabstract:
An emerging nanotechnology, quantum-dot cellular automata (QCA), has the potential for attractive features such as faster speed, smaller size, and lower power consumption than transistor based technology. Quantum-dot cellular automata has a simple cell as the basic element. The cell is used as a building block to construct gates, wires, and memories. Several adder designs have been proposed, but multiplier design in QCA is a rather unexplored research area. This paper utilizes the QCA characteristics to design serial parallel multipliers. Two types of serial parallel multipliers are designed and simulated with several different operand sizes. Those designs are compared in terms of complexity, area, and latency. The serial parallel multipliers have simple and regular structures.

entry:
@InProceedings{Cho:2007:SPM,
  author =       "Heumpil Cho and Earl E. {Swartzlander, Jr.}",
  title =        "Serial Parallel Multiplier Design in Quantum-dot
                 Cellular Automata",
  crossref =     "Kornerup:2007:PIS",
  pages =        "7--15",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.32",
  bibdate =      "Tue Oct 9 16:32:41 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "An emerging nanotechnology, quantum-dot cellular
                 automata (QCA), has the potential for attractive
                 features such as faster speed, smaller size, and lower
                 power consumption than transistor based technology.
                 Quantum-dot cellular automata has a simple cell as the
                 basic element. The cell is used as a building block to
                 construct gates, wires, and memories. Several adder
                 designs have been proposed, but multiplier design in
                 QCA is a rather unexplored research area. This paper
                 utilizes the QCA characteristics to design serial
                 parallel multipliers. Two types of serial parallel
                 multipliers are designed and simulated with several
                 different operand sizes. Those designs are compared in
                 terms of complexity, area, and latency. The serial
                 parallel multipliers have simple and regular
                 structures.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: inproceedings
filename: fparith.bib
label: Chung:2007:ASF
author: Jaewook Chung and M. Anwar Hasan
title: Asymmetric Squaring Formulae
crossref: Kornerup:2007:PIS
pages: 113--122
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.11
bibdate: Tue Oct 9 16:32:41 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 16:32:41 MDT
acknowledgement: ack-nhfb
rawauthor: Jaewook Chung and M. Anwar Hasan
rawtitle: Asymmetric Squaring Formulae
abstract:
We present efficient squaring formulae based on the Toom--Cook multiplication algorithm. The latter always requires at least one non-trivial constant division in the interpolation step. We show such non-trivial divisions are not needed in the case two operands are equal for three, four and five-way squarings. Our analysis shows that our 3-way squaring algorithms have much less overhead than the best known 3-way Toom--Cook algorithm. Our experimental results show that one of our new 3-way squaring methods performs faster than mpz_mul() in GNU multiple precision library (GMP) for squaring integers of approximately 2400-6700 bits on Pentium IV Prescott 3.2GHz. For squaring in $ Z[x] $, our 3-way squaring algorithms are much superior to other known squaring algorithms for small input size. In addition, we present 4-way and 5-way squaring formulae which do not require any constant divisions by integers other than a power of 2. Under some reasonable assumptions, our 5-way squaring formula is faster than the recently proposed Montgomery's 5-way Karatsuba-like formulae.

keywords:
ARITH-18; Cook multiplication algorithm; Karatsuba algorithm; Karatsuba-like formulae; Montgomery's Squaring; Toom-multiple-precision arithmetic

rawabstract:
We present efficient squaring formulae based on the Toom--Cook multiplication algorithm. The latter always requires at least one non-trivial constant division in the interpolation step. We show such non-trivial divisions are not needed in the case two operands are equal for three, four and five-way squarings. Our analysis shows that our 3-way squaring algorithms have much less overhead than the best known 3-way Toom--Cook algorithm. Our experimental results show that one of our new 3-way squaring methods performs faster than mpz\_mul() in GNU multiple precision library (GMP) for squaring integers of approximately 2400-6700 bits on Pentium IV Prescott 3.2GHz. For squaring in $ Z[x] $, our 3-way squaring algorithms are much superior to other known squaring algorithms for small input size. In addition, we present 4-way and 5-way squaring formulae which do not require any constant divisions by integers other than a power of 2. Under some reasonable assumptions, our 5-way squaring formula is faster than the recently proposed Montgomery's 5-way Karatsuba-like formulae.

entry:
@InProceedings{Chung:2007:ASF,
  author =       "Jaewook Chung and M. Anwar Hasan",
  title =        "Asymmetric Squaring Formulae",
  crossref =     "Kornerup:2007:PIS",
  pages =        "113--122",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.11",
  bibdate =      "Tue Oct 9 16:32:41 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We present efficient squaring formulae based on the
                 Toom--Cook multiplication algorithm. The latter always
                 requires at least one non-trivial constant division in
                 the interpolation step. We show such non-trivial
                 divisions are not needed in the case two operands are
                 equal for three, four and five-way squarings. Our
                 analysis shows that our 3-way squaring algorithms have
                 much less overhead than the best known 3-way Toom--Cook
                 algorithm. Our experimental results show that one of
                 our new 3-way squaring methods performs faster than
                 mpz\_mul() in GNU multiple precision library (GMP) for
                 squaring integers of approximately 2400-6700 bits on
                 Pentium IV Prescott 3.2GHz. For squaring in $ Z[x] $,
                 our 3-way squaring algorithms are much superior to
                 other known squaring algorithms for small input size.
                 In addition, we present 4-way and 5-way squaring
                 formulae which do not require any constant divisions by
                 integers other than a power of 2. Under some reasonable
                 assumptions, our 5-way squaring formula is faster than
                 the recently proposed Montgomery's 5-way Karatsuba-like
                 formulae.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18; Cook multiplication algorithm; Karatsuba
                 algorithm; Karatsuba-like formulae; Montgomery's
                 Squaring; Toom-multiple-precision arithmetic",
}


bibtype: article
filename: fparith.bib
label: Chung:2007:LWP
author: Jaewook Chung and M. Anwar Hasan
title: Low-Weight Polynomial Form Integers for Efficient Modular Multiplication
journal: j-IEEE-TRANS-COMPUT
volume: 56
number: 1
pages: 44--57
month: jan
monthnumber: 1
year: 2007
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.250622
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:03:36 MDT 2011
bibtimestamp: 2011.07.04 15:03:36 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4016496
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Jaewook Chung and M. Anwar Hasan
rawtitle: Low-Weight Polynomial Form Integers for Efficient Modular Multiplication
entry:
@Article{Chung:2007:LWP,
  author =       "Jaewook Chung and M. Anwar Hasan",
  title =        "Low-Weight Polynomial Form Integers for Efficient
                 Modular Multiplication",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "56",
  number =       "1",
  pages =        "44--57",
  month =        jan,
  year =         "2007",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.250622",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:03:36 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4016496",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Chung:2007:MRA
author: Jaewook Chung and M. Anwar Hasan
title: Montgomery Reduction Algorithm for Modular Multiplication Using Low-Weight Polynomial Form Integers
crossref: Kornerup:2007:PIS
pages: 230--239
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.23
bibdate: Tue Oct 9 17:16:03 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 17:16:03 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Jaewook Chung and M. Anwar Hasan
abstract:
In this paper, we extend a recent piece of work on low-weight polynomial form integers (LWPFIs). We present a new coefficient reduction algorithm based on the Montgomery reduction algorithm and provide its detailed analysis results. We give a condition for eliminating the final subtractions at the end of our Montgomery reduction algorithm adapted to perform the coefficient reduction. Our experimental results show that a new coefficient reduction algorithm is indeed more efficient than the one presented in [1].

rawabstract:
In this paper, we extend a recent piece of work on low-weight polynomial form integers (LWPFIs). We present a new coefficient reduction algorithm based on the Montgomery reduction algorithm and provide its detailed analysis results. We give a condition for eliminating the final subtractions at the end of our Montgomery reduction algorithm adapted to perform the coefficient reduction. Our experimental results show that a new coefficient reduction algorithm is indeed more efficient than the one presented in [1].

rawtitle:
{Montgomery} Reduction Algorithm for Modular Multiplication Using Low-Weight Polynomial Form Integers

entry:
@InProceedings{Chung:2007:MRA,
  author =       "Jaewook Chung and M. Anwar Hasan",
  title =        "{Montgomery} Reduction Algorithm for Modular
                 Multiplication Using Low-Weight Polynomial Form
                 Integers",
  crossref =     "Kornerup:2007:PIS",
  pages =        "230--239",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.23",
  bibdate =      "Tue Oct 9 17:16:03 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper, we extend a recent piece of work on
                 low-weight polynomial form integers (LWPFIs). We
                 present a new coefficient reduction algorithm based on
                 the Montgomery reduction algorithm and provide its
                 detailed analysis results. We give a condition for
                 eliminating the final subtractions at the end of our
                 Montgomery reduction algorithm adapted to perform the
                 coefficient reduction. Our experimental results show
                 that a new coefficient reduction algorithm is indeed
                 more efficient than the one presented in [1].",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: inproceedings
filename: fparith.bib
label: Cornea:2007:SII
crossref: Kornerup:2007:PIS
pages: 29--37
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.7
bibdate: Tue Oct 09 12:00:30 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 12:00:30 ???
URL: http://www.lirmm.fr/arith18/papers/CorneaM_Decimal_ARITH18.pdf
keywords: ARITH-18; BID rounding; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
author:
Marius Cornea and Cristina Anderson and John Harrison and Ping Tak Peter Tang and Eric Schneider and Charles Tsen

title:
A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format

abstract:
The IEEE Standard 754-1985 for Binary Floating-Point Arithmetic [1] was revised [2], and an important addition is the definition of decimal floating-point arithmetic. This is intended mainly to provide a robust, reliable framework for financial applications that are often subject to legal requirements concerning rounding and precision of the results, because the binary floating-point arithmetic may introduce small but unacceptable errors. Using binary floating-point calculations to emulate decimal calculations in order to correct this issue has led to the existence of numerous proprietary software packages, each with its own characteristics and capabilities. IEEE 754R decimal arithmetic should unify the ways decimal floating-point calculations are carried out on various platforms. New algorithms and properties are presented in this paper which are used in a software implementation of the IEEE 754R decimal floating-point arithmetic, with emphasis on using binary operations efficiently. The focus is on rounding techniques for decimal values stored in binary format, but algorithms for the more important or interesting operations of addition, multiplication, division, and conversions between binary and decimal floating-point formats are also outlined. Performance results are included for a wider range of operations, showing promise that our approach is viable for applications that require decimal floating-point calculations

rawabstract:
The IEEE Standard 754-1985 for Binary Floating-Point Arithmetic [1] was revised [2], and an important addition is the definition of decimal floating-point arithmetic. This is intended mainly to provide a robust, reliable framework for financial applications that are often subject to legal requirements concerning rounding and precision of the results, because the binary floating-point arithmetic may introduce small but unacceptable errors. Using binary floating-point calculations to emulate decimal calculations in order to correct this issue has led to the existence of numerous proprietary software packages, each with its own characteristics and capabilities. IEEE 754R decimal arithmetic should unify the ways decimal floating-point calculations are carried out on various platforms. New algorithms and properties are presented in this paper which are used in a software implementation of the IEEE 754R decimal floating-point arithmetic, with emphasis on using binary operations efficiently. The focus is on rounding techniques for decimal values stored in binary format, but algorithms for the more important or interesting operations of addition, multiplication, division, and conversions between binary and decimal floating-point formats are also outlined. Performance results are included for a wider range of operations, showing promise that our approach is viable for applications that require decimal floating-point calculations

rawauthor:
Marius Cornea and Cristina Anderson and John Harrison and Ping Tak Peter Tang and Eric Schneider and Charles Tsen

rawtitle:
A Software Implementation of the {IEEE 754R} Decimal Floating-Point Arithmetic Using the Binary Encoding Format

entry:
@InProceedings{Cornea:2007:SII,
  author =       "Marius Cornea and Cristina Anderson and John Harrison
                 and Ping Tak Peter Tang and Eric Schneider and Charles
                 Tsen",
  title =        "A Software Implementation of the {IEEE 754R} Decimal
                 Floating-Point Arithmetic Using the Binary Encoding
                 Format",
  crossref =     "Kornerup:2007:PIS",
  pages =        "29--37",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.7",
  bibdate =      "Tue Oct 09 12:00:30 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.lirmm.fr/arith18/papers/CorneaM_Decimal_ARITH18.pdf",
  abstract =     "The IEEE Standard 754-1985 for Binary Floating-Point
                 Arithmetic [1] was revised [2], and an important
                 addition is the definition of decimal floating-point
                 arithmetic. This is intended mainly to provide a
                 robust, reliable framework for financial applications
                 that are often subject to legal requirements concerning
                 rounding and precision of the results, because the
                 binary floating-point arithmetic may introduce small
                 but unacceptable errors. Using binary floating-point
                 calculations to emulate decimal calculations in order
                 to correct this issue has led to the existence of
                 numerous proprietary software packages, each with its
                 own characteristics and capabilities. IEEE 754R decimal
                 arithmetic should unify the ways decimal floating-point
                 calculations are carried out on various platforms. New
                 algorithms and properties are presented in this paper
                 which are used in a software implementation of the IEEE
                 754R decimal floating-point arithmetic, with emphasis
                 on using binary operations efficiently. The focus is on
                 rounding techniques for decimal values stored in binary
                 format, but algorithms for the more important or
                 interesting operations of addition, multiplication,
                 division, and conversions between binary and decimal
                 floating-point formats are also outlined. Performance
                 results are included for a wider range of operations,
                 showing promise that our approach is viable for
                 applications that require decimal floating-point
                 calculations",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18; BID rounding; correct rounding;
                 floating-point arithmetic",
}


bibtype: manual
filename: fparith.bib
label: Cowlishaw:2007:DCL
author: Mike Cowlishaw
title: The decNumber C library
organization: pub-IBM
address: pub-IBM:adr
pages: 29--37
day: 18
month: apr
monthnumber: 4
year: 2007
bibdate: Fri Apr 20 08:02:33 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.04.20 08:02:33 ???
note: Version 3.40
URL: http://download.icu-project.org/ex/files/decNumber/decNumber-icu-340.zip
keywords: decimal floating-point arithmetic; DPD encoding
acknowledgement: ack-nhfb
rawauthor: Mike Cowlishaw
rawnote: Version 3.40
rawtitle: The {decNumber C} library
entry:
@Manual{Cowlishaw:2007:DCL,
  author =       "Mike Cowlishaw",
  title =        "The {decNumber C} library",
  organization = pub-IBM,
  address =      pub-IBM:adr,
  day =          "18",
  month =        apr,
  year =         "2007",
  bibdate =      "Fri Apr 20 08:02:33 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Version 3.40",
  URL =          "http://download.icu-project.org/ex/files/decNumber/decNumber-icu-340.zip",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic; DPD encoding",
}


bibtype: article
filename: fparith.bib
label: Dadda:2007:MPD
author: Luigi Dadda
title: Multioperand Parallel Decimal Adder: a Mixed Binary and BCD Approach
journal: j-IEEE-TRANS-COMPUT
volume: 56
number: 10
pages: 1320--1328
month: oct
monthnumber: 10
year: 2007
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.1067
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Aug 07 17:48:41 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 17:48:41 ???
fjournal: IEEE Transactions on Computers
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
authordates: 29 April 1923--26 October 2012
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Luigi Dadda
rawtitle: Multioperand Parallel Decimal Adder: a Mixed Binary and {BCD} Approach
abstract:
Decimal arithmetic has been in recent years revived due to the large amount of data in commercial applications. We consider the problem of Multi Operand Parallel Decimal Addition with an approach that uses binary arithmetic, suggested by the adoption of BCD numbers. This involves corrections in order to obtain the BCD result, or a binary to decimal conversion. We adopt the latter approach, particularly efficient for a large number of addends. Conversion requires a relatively small area and can afford fast operation. The BD conversion, moreover, allows an easy alignment of the sums of adjacent columns. We treat the design of BCD digit adders using fast carry free adders and the conversion problem through a known parallel scheme using elementary conversion cells. Spreadsheets have been developed for adding several BCD digits and for simulating the binary to decimal conversion as design tool.

rawabstract:
Decimal arithmetic has been in recent years revived due to the large amount of data in commercial applications. We consider the problem of Multi Operand Parallel Decimal Addition with an approach that uses binary arithmetic, suggested by the adoption of BCD numbers. This involves corrections in order to obtain the BCD result, or a binary to decimal conversion. We adopt the latter approach, particularly efficient for a large number of addends. Conversion requires a relatively small area and can afford fast operation. The BD conversion, moreover, allows an easy alignment of the sums of adjacent columns. We treat the design of BCD digit adders using fast carry free adders and the conversion problem through a known parallel scheme using elementary conversion cells. Spreadsheets have been developed for adding several BCD digits and for simulating the binary to decimal conversion as design tool.

entry:
@Article{Dadda:2007:MPD,
  author =       "Luigi Dadda",
  title =        "Multioperand Parallel Decimal Adder: a Mixed Binary
                 and {BCD} Approach",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "56",
  number =       "10",
  pages =        "1320--1328",
  month =        oct,
  year =         "2007",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.1067",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Aug 07 17:48:41 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Decimal arithmetic has been in recent years revived
                 due to the large amount of data in commercial
                 applications. We consider the problem of Multi Operand
                 Parallel Decimal Addition with an approach that uses
                 binary arithmetic, suggested by the adoption of BCD
                 numbers. This involves corrections in order to obtain
                 the BCD result, or a binary to decimal conversion. We
                 adopt the latter approach, particularly efficient for a
                 large number of addends. Conversion requires a
                 relatively small area and can afford fast operation.
                 The BD conversion, moreover, allows an easy alignment
                 of the sums of adjacent columns. We treat the design of
                 BCD digit adders using fast carry free adders and the
                 conversion problem through a known parallel scheme
                 using elementary conversion cells. Spreadsheets have
                 been developed for adding several BCD digits and for
                 simulating the binary to decimal conversion as design
                 tool.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  author-dates = "29 April 1923--26 October 2012",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: David:2007:HCM
author: J. P. David and K. Kalach and N. Tittley
title: Hardware Complexity of Modular Multiplication and Exponentiation
journal: j-IEEE-TRANS-COMPUT
volume: 56
number: 10
pages: 1308--1319
month: oct
monthnumber: 10
year: 2007
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.1084
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:03:41 MDT 2011
bibtimestamp: 2011.07.04 15:03:41 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4302704
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: J. P. David and K. Kalach and N. Tittley
rawtitle: Hardware Complexity of Modular Multiplication and Exponentiation
entry:
@Article{David:2007:HCM,
  author =       "J. P. David and K. Kalach and N. Tittley",
  title =        "Hardware Complexity of Modular Multiplication and
                 Exponentiation",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "56",
  number =       "10",
  pages =        "1308--1319",
  month =        oct,
  year =         "2007",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.1084",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:03:41 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4302704",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: deDinechin:2007:FCR
author: Florent de Dinechin and Christoph Lauter and Jean-Michel Muller
title: Fast and correctly rounded logarithms in double-precision
journal: j-INFORM-THEOR-APPL
volume: 41
number: 1
pages: 85--102
month: jan
monthnumber: 1
year: 2007
CODEN: RSITD7, RITAE4
DOI: https://doi.org/10.1051/ita:2007003
ISSN: 0988-3754 (print), 1290-385X (electronic) OR 09883754 (print), 1290385X (electronic)
ISSNL: 0988-3754 OR 09883754
bibdate: Fri Dec 8 09:46:23 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.08 09:46:23 ???
fjournal: RAIRO. Informatique theorique et applications := Theoretical informatics and applications
acknowledgement: ack-nhfb
rawauthor: Florent de Dinechin and Christoph Lauter and Jean-Michel Muller
rawtitle: Fast and correctly rounded logarithms in double-precision
entry:
@Article{deDinechin:2007:FCR,
  author =       "Florent de Dinechin and Christoph Lauter and
                 Jean-Michel Muller",
  title =        "Fast and correctly rounded logarithms in
                 double-precision",
  journal =      j-INFORM-THEOR-APPL,
  volume =       "41",
  number =       "1",
  pages =        "85--102",
  month =        jan,
  year =         "2007",
  CODEN =        "RSITD7, RITAE4",
  DOI =          "https://doi.org/10.1051/ita:2007003",
  ISSN =         "0988-3754 (print), 1290-385X (electronic)",
  ISSN-L =       "0988-3754",
  bibdate =      "Fri Dec 8 09:46:23 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "RAIRO. Informatique th{\'e}orique et applications :=
                 Theoretical informatics and applications",
}


bibtype: inproceedings
filename: fparith.bib
label: Detrey:2007:RHF
author: Jeremie Detrey and Florent de Dinechin and Xavier Pujol
title: Return of the hardware floating-point elementary function
crossref: Kornerup:2007:PIS
pages: 161--168
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.29
bibdate: Tue Oct 9 17:16:03 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 17:16:03 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Jeremie Detrey and Florent de Dinechin and Xavier Pujol
rawtitle: Return of the hardware floating-point elementary function
abstract:
The study of specific hardware circuits for the evaluation of floating-point elementary functions was once an active research area, until it was realized that these functions were not frequent enough to justify dedicating silicon to them. Research then turned to software functions. This situation may be about to change again with the advent of reconfigurable co-processors based on field-programmable gate arrays. Such co-processors now have a capacity that allows them to accommodate double-precision floating-point computing. Hardware operators for elementary functions targeted to such platforms have the potential to vastly outperform software functions, and will not permanently waste silicon resources. This article studies the optimization, for this target technology, of operators for the exponential and logarithm functions up to double-precision. These operators are freely available from http://www.ens-lyon.fr/LIP/Arenaire/.

rawabstract:
The study of specific hardware circuits for the evaluation of floating-point elementary functions was once an active research area, until it was realized that these functions were not frequent enough to justify dedicating silicon to them. Research then turned to software functions. This situation may be about to change again with the advent of reconfigurable co-processors based on field-programmable gate arrays. Such co-processors now have a capacity that allows them to accommodate double-precision floating-point computing. Hardware operators for elementary functions targeted to such platforms have the potential to vastly outperform software functions, and will not permanently waste silicon resources. This article studies the optimization, for this target technology, of operators for the exponential and logarithm functions up to double-precision. These operators are freely available from http://www.ens-lyon.fr/LIP/Arenaire/.

entry:
@InProceedings{Detrey:2007:RHF,
  author =       "Jeremie Detrey and Florent de Dinechin and Xavier
                 Pujol",
  title =        "Return of the hardware floating-point elementary
                 function",
  crossref =     "Kornerup:2007:PIS",
  pages =        "161--168",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.29",
  bibdate =      "Tue Oct 9 17:16:03 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The study of specific hardware circuits for the
                 evaluation of floating-point elementary functions was
                 once an active research area, until it was realized
                 that these functions were not frequent enough to
                 justify dedicating silicon to them. Research then
                 turned to software functions. This situation may be
                 about to change again with the advent of reconfigurable
                 co-processors based on field-programmable gate arrays.
                 Such co-processors now have a capacity that allows them
                 to accommodate double-precision floating-point
                 computing. Hardware operators for elementary functions
                 targeted to such platforms have the potential to vastly
                 outperform software functions, and will not permanently
                 waste silicon resources. This article studies the
                 optimization, for this target technology, of operators
                 for the exponential and logarithm functions up to
                 double-precision. These operators are freely available
                 from http://www.ens-lyon.fr/LIP/Arenaire/.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: article
filename: fparith.bib
label: Detrey:2007:TUC
author: Jeremie Detrey and Florent Dinechin
title: A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
journal: j-J-VLSI-SIGNAL-PROC
volume: 49
number: 1
pages: 161--175
month: oct
monthnumber: 10
year: 2007
CODEN: JVSPED
DOI: https://doi.org/10.1007/s11265-007-0048-7
ISSN: 0922-5773 (print), 1573-109x (electronic) OR 09225773 (print), 1573109x (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Mon Nov 05 19:20:45 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.05 19:20:45 ???
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
rawauthor: J{\'e}r{\'e}mie Detrey and Florent Dinechin
rawtitle: A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
abstract:
For applications requiring a large dynamic, real numbers may be represented either in floating-point, or in the logarithm number system (LNS). Which system is best for a given application is difficult to know in advance, because the cost and performance of LNS operators depend on the target accuracy in a highly non linear way. Therefore, a comparison of the pros and cons of both number systems in terms of cost, performance and overall accuracy is only relevant on a per-application basis. To make such a comparison possible, two concurrent libraries of parameterized arithmetic operators, targeting recent field-programmable gate arrays, are presented. They are unbiased in the sense that they strive to reflect the state-of-the-art for both number systems. These libraries are freely available at http://www.ens-lyon.fr/LIP/Arenaire/.

rawabstract:
For applications requiring a large dynamic, real numbers may be represented either in floating-point, or in the logarithm number system (LNS). Which system is best for a given application is difficult to know in advance, because the cost and performance of LNS operators depend on the target accuracy in a highly non linear way. Therefore, a comparison of the pros and cons of both number systems in terms of cost, performance and overall accuracy is only relevant on a per-application basis. To make such a comparison possible, two concurrent libraries of parameterized arithmetic operators, targeting recent field-programmable gate arrays, are presented. They are unbiased in the sense that they strive to reflect the state-of-the-art for both number systems. These libraries are freely available at http://www.ens-lyon.fr/LIP/Arenaire/.

entry:
@Article{Detrey:2007:TUC,
  author =       "J{\'e}r{\'e}mie Detrey and Florent Dinechin",
  title =        "A Tool for Unbiased Comparison between Logarithmic and
                 Floating-point Arithmetic",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "49",
  number =       "1",
  pages =        "161--175",
  month =        oct,
  year =         "2007",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1007/s11265-007-0048-7",
  ISSN =         "0922-5773 (print), 1573-109x (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Mon Nov 05 19:20:45 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "For applications requiring a large dynamic, real
                 numbers may be represented either in floating-point, or
                 in the logarithm number system (LNS). Which system is
                 best for a given application is difficult to know in
                 advance, because the cost and performance of LNS
                 operators depend on the target accuracy in a highly non
                 linear way. Therefore, a comparison of the pros and
                 cons of both number systems in terms of cost,
                 performance and overall accuracy is only relevant on a
                 per-application basis. To make such a comparison
                 possible, two concurrent libraries of parameterized
                 arithmetic operators, targeting recent
                 field-programmable gate arrays, are presented. They are
                 unbiased in the sense that they strive to reflect the
                 state-of-the-art for both number systems. These
                 libraries are freely available at
                 http://www.ens-lyon.fr/LIP/Arenaire/.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of VLSI Signal Processing",
}


bibtype: article
filename: fparith.bib
label: Diekmann:2007:FDU
author: Andreas Diekmann
title: Not the First Digit! Using Benford's Law to Detect Fraudulent Scientific Data
journal: j-J-APPL-STAT
volume: 34
number: 3
pages: 321--329
year: 2007
DOI: https://doi.org/10.1080/02664760601004940
ISSN: 0266-4763 (print), 1360-0532 (electronic) OR 02664763 (print), 13600532 (electronic)
ISSNL: 0266-4763 OR 02664763
bibdate: Wed Aug 25 11:41:54 MDT 2010
bibtimestamp: 2010.08.25 11:41:54 MDT
fjournal: Journal of Applied Statistics
acknowledgement: ack-nhfb
journalURL: http://www.tandfonline.com/loi/cjas20
rawauthor: Andreas Diekmann
rawtitle: Not the First Digit! Using {Benford's Law} to Detect Fraudulent Scientific Data
abstract:
Digits in statistical data produced by natural or social processes are often distributed in a manner described by 'Benford's law'. Recently, a test against this distribution was used to identify fraudulent accounting data. This test is based on the supposition that first, second, third, and other digits in real data follow the Benford distribution while the digits in fabricated data do not. Is it possible to apply Benford tests to detect fabricated or falsified scientific data as well as fraudulent financial data? We approached this question in two ways. First, we examined the use of the Benford distribution as a standard by checking the frequencies of the nine possible first and ten possible second digits in published statistical estimates. Second, we conducted experiments in which subjects were asked to fabricate statistical estimates (regression coefficients). The digits in these experimental data were scrutinized for possible deviations from the Benford distribution. There were two main findings. First, both digits of the published regression coefficients were approximately Benford distributed or at least followed a pattern of monotonic decline. Second, the experimental results yielded new insights into the strengths and weaknesses of Benford tests. Surprisingly, first digits of faked data also exhibited a pattern of monotonic decline, while second, third, and fourth digits were distributed less in accordance with Benford's law. At least in the case of regression coefficients, there were indications that checks for digit-preference anomalies should focus less on the first (i.e. leftmost) and more on later digits.

keywords:
Benford's Law; data fabrication; digital analysis; distribution of digits from regression coefficients; first digit law; Zipf's Law

rawabstract:
Digits in statistical data produced by natural or social processes are often distributed in a manner described by 'Benford's law'. Recently, a test against this distribution was used to identify fraudulent accounting data. This test is based on the supposition that first, second, third, and other digits in real data follow the Benford distribution while the digits in fabricated data do not. Is it possible to apply Benford tests to detect fabricated or falsified scientific data as well as fraudulent financial data? We approached this question in two ways. First, we examined the use of the Benford distribution as a standard by checking the frequencies of the nine possible first and ten possible second digits in published statistical estimates. Second, we conducted experiments in which subjects were asked to fabricate statistical estimates (regression coefficients). The digits in these experimental data were scrutinized for possible deviations from the Benford distribution. There were two main findings. First, both digits of the published regression coefficients were approximately Benford distributed or at least followed a pattern of monotonic decline. Second, the experimental results yielded new insights into the strengths and weaknesses of Benford tests. Surprisingly, first digits of faked data also exhibited a pattern of monotonic decline, while second, third, and fourth digits were distributed less in accordance with Benford's law. At least in the case of regression coefficients, there were indications that checks for digit-preference anomalies should focus less on the first (i.e. leftmost) and more on later digits.

entry:
@Article{Diekmann:2007:FDU,
  author =       "Andreas Diekmann",
  title =        "Not the First Digit! Using {Benford's Law} to Detect
                 Fraudulent Scientific Data",
  journal =      j-J-APPL-STAT,
  volume =       "34",
  number =       "3",
  pages =        "321--329",
  year =         "2007",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1080/02664760601004940",
  ISSN =         "0266-4763 (print), 1360-0532 (electronic)",
  ISSN-L =       "0266-4763",
  bibdate =      "Wed Aug 25 11:41:54 MDT 2010",
  bibsource =    "http://www.tandf.co.uk/journals/routledge/02664763.html;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Digits in statistical data produced by natural or
                 social processes are often distributed in a manner
                 described by 'Benford's law'. Recently, a test against
                 this distribution was used to identify fraudulent
                 accounting data. This test is based on the supposition
                 that first, second, third, and other digits in real
                 data follow the Benford distribution while the digits
                 in fabricated data do not. Is it possible to apply
                 Benford tests to detect fabricated or falsified
                 scientific data as well as fraudulent financial data?
                 We approached this question in two ways. First, we
                 examined the use of the Benford distribution as a
                 standard by checking the frequencies of the nine
                 possible first and ten possible second digits in
                 published statistical estimates. Second, we conducted
                 experiments in which subjects were asked to fabricate
                 statistical estimates (regression coefficients). The
                 digits in these experimental data were scrutinized for
                 possible deviations from the Benford distribution.
                 There were two main findings. First, both digits of the
                 published regression coefficients were approximately
                 Benford distributed or at least followed a pattern of
                 monotonic decline. Second, the experimental results
                 yielded new insights into the strengths and weaknesses
                 of Benford tests. Surprisingly, first digits of faked
                 data also exhibited a pattern of monotonic decline,
                 while second, third, and fourth digits were distributed
                 less in accordance with Benford's law. At least in the
                 case of regression coefficients, there were indications
                 that checks for digit-preference anomalies should focus
                 less on the first (i.e. leftmost) and more on later
                 digits.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Applied Statistics",
  journal-URL =  "http://www.tandfonline.com/loi/cjas20",
  keywords =     "Benford's Law; data fabrication; digital analysis;
                 distribution of digits from regression coefficients;
                 first digit law; Zipf's Law",
}


bibtype: article
filename: fparith.bib
label: Dieter:2007:LCM
author: W. R. Dieter and A. Kaveti and H. G. Dietz
title: Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy
journal: j-IEEE-COMPUT-ARCHIT-LETT
volume: 6
number: 1
pages: 13--16
month: jan
monthnumber: 1
year: 2007
DOI: https://doi.org/10.1109/L-CA.2007.1
ISSN: 1556-6056 (print), 1556-6064 (electronic) OR 15566056 (print), 15566064 (electronic)
ISSNL: 1556-6056 OR 15566056
bibdate: Fri Jun 21 05:49:19 2019
bibtimestamp: 2019.06.21 05:49:19 ???
fjournal: IEEE Computer Architecture Letters
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10208
rawauthor: W. R. Dieter and A. Kaveti and H. G. Dietz
rawtitle: Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeecomputarchitlett.bib

abstract:
Some processors designed for consumer applications, such as graphics processing units (CPUs) and the CELL processor, promise outstanding floating-point performance for scientific applications at commodity prices. However, IEEE single precision is the most precise floating-point data type these processors directly support in hardware. Pairs of native floating-point numbers can be used to represent a base result and a residual term to increase accuracy, but the resulting order of magnitude slowdown dramatically reduces the price/performance advantage of these systems. By adding a few simple microarchitectural features, acceptable accuracy can be obtained with relatively little performance penalty. To reduce the cost of native-pair arithmetic, a residual register is used to hold information that would normally have been discarded after each floating-point computation. The residual register dramatically simplifies the code, providing both lower latency and better instruction-level parallelism.

keywords:
Application software; B Hardware; B.2 Arithmetic and Logic Structures; B.2.4 High-Speed Arithmetic; B.2.4.b Cost/performance; C Computer Systems Organization; C.0 General; C.0.b Hardware/software interfaces; C.1 Processor Architectures; C.1.5 Micro-architecture implementation considerations; CELL processor; computer architecture; Costs; floating point arithmetic; floating-point accuracy; Floating-point arithmetic; G Mathematics of Computing; G.1 Numerical Analysis; G.1.0 General; G.1.0.e Multiple precision arithmetic; Graphics; graphics processing units; Hardware; I Computing Methodologies; I.3 Computer Graphics; I.3.1 Hardware Architecture; I.3.1.a Graphics processors; IEEE single precision; instruction-level parallelism; microarchitectural support; Microarchitecture; parallel processing; Pipelines; Registers; Software algorithms; Software performance

rawabstract:
Some processors designed for consumer applications, such as graphics processing units (CPUs) and the CELL processor, promise outstanding floating-point performance for scientific applications at commodity prices. However, IEEE single precision is the most precise floating-point data type these processors directly support in hardware. Pairs of native floating-point numbers can be used to represent a base result and a residual term to increase accuracy, but the resulting order of magnitude slowdown dramatically reduces the price/performance advantage of these systems. By adding a few simple microarchitectural features, acceptable accuracy can be obtained with relatively little performance penalty. To reduce the cost of native-pair arithmetic, a residual register is used to hold information that would normally have been discarded after each floating-point computation. The residual register dramatically simplifies the code, providing both lower latency and better instruction-level parallelism.

entry:
@Article{Dieter:2007:LCM,
  author =       "W. R. Dieter and A. Kaveti and H. G. Dietz",
  title =        "Low-Cost Microarchitectural Support for Improved
                 Floating-Point Accuracy",
  journal =      j-IEEE-COMPUT-ARCHIT-LETT,
  volume =       "6",
  number =       "1",
  pages =        "13--16",
  month =        jan,
  year =         "2007",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/L-CA.2007.1",
  ISSN =         "1556-6056 (print), 1556-6064 (electronic)",
  ISSN-L =       "1556-6056",
  bibdate =      "Fri Jun 21 05:49:19 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeecomputarchitlett.bib",
  abstract =     "Some processors designed for consumer applications,
                 such as graphics processing units (CPUs) and the CELL
                 processor, promise outstanding floating-point
                 performance for scientific applications at commodity
                 prices. However, IEEE single precision is the most
                 precise floating-point data type these processors
                 directly support in hardware. Pairs of native
                 floating-point numbers can be used to represent a base
                 result and a residual term to increase accuracy, but
                 the resulting order of magnitude slowdown dramatically
                 reduces the price/performance advantage of these
                 systems. By adding a few simple microarchitectural
                 features, acceptable accuracy can be obtained with
                 relatively little performance penalty. To reduce the
                 cost of native-pair arithmetic, a residual register is
                 used to hold information that would normally have been
                 discarded after each floating-point computation. The
                 residual register dramatically simplifies the code,
                 providing both lower latency and better
                 instruction-level parallelism.",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Computer Architecture Letters",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10208",
  keywords =     "Application software; B Hardware; B.2 Arithmetic and
                 Logic Structures; B.2.4 High-Speed Arithmetic; B.2.4.b
                 Cost/performance; C Computer Systems Organization; C.0
                 General; C.0.b Hardware/software interfaces; C.1
                 Processor Architectures; C.1.5 Micro-architecture
                 implementation considerations; CELL processor; computer
                 architecture; Costs; floating point arithmetic;
                 floating-point accuracy; Floating-point arithmetic; G
                 Mathematics of Computing; G.1 Numerical Analysis; G.1.0
                 General; G.1.0.e Multiple precision arithmetic;
                 Graphics; graphics processing units; Hardware; I
                 Computing Methodologies; I.3 Computer Graphics; I.3.1
                 Hardware Architecture; I.3.1.a Graphics processors;
                 IEEE single precision; instruction-level parallelism;
                 microarchitectural support; Microarchitecture; parallel
                 processing; Pipelines; Registers; Software algorithms;
                 Software performance",
}


bibtype: inproceedings
filename: fparith.bib
label: Dimitrov:2007:MCS
author: Vassil Dimitrov and Laurent Imbert and Andrew Zakaluzny
title: Multiplication by a Constant is Sublinear
crossref: Kornerup:2007:PIS
pages: 261--268
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.24
bibdate: Tue Oct 9 17:16:03 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 17:16:03 MDT
keywords: ARITH-18; Double-Based Number System (DBNS)
acknowledgement: ack-nhfb
rawauthor: Vassil Dimitrov and Laurent Imbert and Andrew Zakaluzny
rawtitle: Multiplication by a Constant is Sublinear
abstract:
This paper explores the use of the double-base number system (DBNS) for constant integer multiplication. The DBNS recoding scheme represents integers --- in this case constants --- in a multiple-radix way in the hope of minimizing the number of additions to be performed during constant multiplication. On the theoretical side, we propose a formal proof which shows that our recoding technique diminishes the number of additions in a sublinear way. Therefore, we prove Lefevre's conjecture that the multiplication by an integer constant is achievable in sublinear time. In a second part, we investigate various strategies and we provide numerical data showcasing the potential interest of our approach.

rawabstract:
This paper explores the use of the double-base number system (DBNS) for constant integer multiplication. The DBNS recoding scheme represents integers --- in this case constants --- in a multiple-radix way in the hope of minimizing the number of additions to be performed during constant multiplication. On the theoretical side, we propose a formal proof which shows that our recoding technique diminishes the number of additions in a sublinear way. Therefore, we prove Lef{\`e}vre's conjecture that the multiplication by an integer constant is achievable in sublinear time. In a second part, we investigate various strategies and we provide numerical data showcasing the potential interest of our approach.

entry:
@InProceedings{Dimitrov:2007:MCS,
  author =       "Vassil Dimitrov and Laurent Imbert and Andrew
                 Zakaluzny",
  title =        "Multiplication by a Constant is Sublinear",
  crossref =     "Kornerup:2007:PIS",
  pages =        "261--268",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.24",
  bibdate =      "Tue Oct 9 17:16:03 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper explores the use of the double-base number
                 system (DBNS) for constant integer multiplication. The
                 DBNS recoding scheme represents integers --- in this
                 case constants --- in a multiple-radix way in the hope
                 of minimizing the number of additions to be performed
                 during constant multiplication. On the theoretical
                 side, we propose a formal proof which shows that our
                 recoding technique diminishes the number of additions
                 in a sublinear way. Therefore, we prove Lef{\`e}vre's
                 conjecture that the multiplication by an integer
                 constant is achievable in sublinear time. In a second
                 part, we investigate various strategies and we provide
                 numerical data showcasing the potential interest of our
                 approach.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18; Double-Based Number System (DBNS)",
}


bibtype: article
filename: fparith.bib
label: Doornik:2007:CHP
author: Jurgen A. Doornik
title: Conversion of high-period random numbers to floating point
journal: j-TOMACS
volume: 17
number: 1
pages: ??--??
month: jan
monthnumber: 1
year: 2007
CODEN: ATMCEZ
DOI: https://doi.org/10.1145/1189756.1189759
ISSN: 1049-3301 (print), 1558-1195 (electronic) OR 10493301 (print), 15581195 (electronic)
ISSNL: 1049-3301 OR 10493301
bibdate: Sat Apr 14 09:34:46 MDT 2007
bibtimestamp: 2007.04.14 09:34:46 MDT
fjournal: ACM Transactions on Modeling and Computer Simulation
acknowledgement: ack-nhfb
articleno: 3
journalURL: http://portal.acm.org/browse_dl.cfm?&idx=J781
rawauthor: Jurgen A. Doornik
rawtitle: Conversion of high-period random numbers to floating point
bibsource:
http://www.acm.org/pubs/contents/journals/tomacs/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Doornik:2007:CHP,
  author =       "Jurgen A. Doornik",
  title =        "Conversion of high-period random numbers to floating
                 point",
  journal =      j-TOMACS,
  volume =       "17",
  number =       "1",
  pages =        "??--??",
  month =        jan,
  year =         "2007",
  CODEN =        "ATMCEZ",
  DOI =          "https://doi.org/10.1145/1189756.1189759",
  ISSN =         "1049-3301 (print), 1558-1195 (electronic)",
  ISSN-L =       "1049-3301",
  bibdate =      "Sat Apr 14 09:34:46 MDT 2007",
  bibsource =    "http://www.acm.org/pubs/contents/journals/tomacs/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  fjournal =     "ACM Transactions on Modeling and Computer Simulation",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?&idx=J781",
}


bibtype: article
filename: fparith.bib
label: Duale:2007:DFP
author: A. Y. Duale and M. H. Decker and H.-G. Zipperer and M. Aharoni and T. J. Bohizic
title: Decimal floating-point in z9: An implementation and testing perspective
journal: j-IBM-JRD
volume: 51
number: 1/2
pages: 217--227
month: jan
monthnumber: 1
year: 2007
CODEN: IBMJAE
DOI: https://doi.org/10.1147/rd.511.0217
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Fri Feb 9 20:31:06 MST 2007
bibsource: http://www.research.ibm.com/journal/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.02.09 20:31:06 MST
URL: http://www.research.ibm.com/journal/rd/511/duale.html
fjournal: IBM Journal of Research and Development
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawauthor: A. Y. Duale and M. H. Decker and H.-G. Zipperer and M. Aharoni and T. J. Bohizic
rawtitle: Decimal floating-point in {z9}: An implementation and testing perspective
abstract:
Although decimal arithmetic is widely used in commercial and financial applications, the related computations are handled in software. As a result, applications that use decimal data may experience performance degradations. Use of the newly defined decimal floating-point (DFP) format instead of binary floating-point is expected to significantly improve the performance of such applications. System z9 is the first IBM machine to support the DFP instructions. We present an overview of this implementation and provide some measurement of the performance gained using hardware assists. Various tools and techniques employed for the DFP verification on unit, element, and system levels are presented in detail. Several groups within IBM collaborated on the verification of the new DFP facility, using a common reference model to predict DFP results.

rawabstract:
Although decimal arithmetic is widely used in commercial and financial applications, the related computations are handled in software. As a result, applications that use decimal data may experience performance degradations. Use of the newly defined decimal floating-point (DFP) format instead of binary floating-point is expected to significantly improve the performance of such applications. System z9 is the first IBM machine to support the DFP instructions. We present an overview of this implementation and provide some measurement of the performance gained using hardware assists. Various tools and techniques employed for the DFP verification on unit, element, and system levels are presented in detail. Several groups within IBM collaborated on the verification of the new DFP facility, using a common reference model to predict DFP results.

entry:
@Article{Duale:2007:DFP,
  author =       "A. Y. Duale and M. H. Decker and H.-G. Zipperer and M.
                 Aharoni and T. J. Bohizic",
  title =        "Decimal floating-point in {z9}: An implementation and
                 testing perspective",
  journal =      j-IBM-JRD,
  volume =       "51",
  number =       "1/2",
  pages =        "217--227",
  month =        jan # " \slash " # mar,
  year =         "2007",
  CODEN =        "IBMJAE",
  DOI =          "https://doi.org/10.1147/rd.511.0217",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Fri Feb 9 20:31:06 MST 2007",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.research.ibm.com/journal/rd/511/duale.html",
  abstract =     "Although decimal arithmetic is widely used in
                 commercial and financial applications, the related
                 computations are handled in software. As a result,
                 applications that use decimal data may experience
                 performance degradations. Use of the newly defined
                 decimal floating-point (DFP) format instead of binary
                 floating-point is expected to significantly improve the
                 performance of such applications. System z9 is the
                 first IBM machine to support the DFP instructions. We
                 present an overview of this implementation and provide
                 some measurement of the performance gained using
                 hardware assists. Various tools and techniques employed
                 for the DFP verification on unit, element, and system
                 levels are presented in detail. Several groups within
                 IBM collaborated on the verification of the new DFP
                 facility, using a common reference model to predict DFP
                 results.",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "decimal floating-point arithmetic",
  ordernumber =  "????",
}


bibtype: article
filename: fparith.bib
label: Eisen:2007:IPA
title: IBM POWER6 accelerators: VMX and DFU
journal: j-IBM-JRD
volume: 51
number: 6
pages: 663--683
month: nov
monthnumber: 11
year: 2007
CODEN: IBMJAE
ISSN: 0018-8646 (print), 2151-8556 (electronic) OR 00188646 (print), 21518556 (electronic)
ISSNL: 0018-8646 OR 00188646
bibdate: Mon Jul 7 21:49:07 MDT 2008
bibsource: http://www.research.ibm.com/journal/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.07.07 21:49:07 MDT
URL: http://www.research.ibm.com/journal/rd/516/eisen.html
fjournal: IBM Journal of Research and Development
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520
rawtitle: {IBM POWER6} accelerators: {VMX} and {DFU}
author:
L. Eisen and J. W. Ward III and H.-W. Tast and N. Mading and J. Leenstra and S. M. Mueller and C. Jacobi and J. Preiss and E. M. Schwarz and S. R. Carlough

abstract:
The IBM POWER6 microprocessor core includes two accelerators for increasing performance of specific workloads. The vector multimedia extension (VMX) provides a vector acceleration of graphic and scientific workloads. It provides single instructions that work on multiple data elements. The instructions separate a 128-bit vector into different components that are operated on concurrently. The decimal floating-point unit (DFU) provides acceleration of commercial workloads, more specifically, financial transactions. It provides a new number system that performs implicit rounding to decimal radix points, a feature essential to monetary transactions. The IBM POWER processor instruction set is substantially expanded with the addition of these two accelerators. The VMX architecture contains 176 instructions, while the DFU architecture adds 54 instructions to the base architecture. The IEEE 754R Binary Floating-Point Arithmetic Standard defines decimal floating-point formats, and the POWER6 processor---on which a substantial amount of area has been devoted to increasing performance of both scientific and commercial workloads---is the first commercial hardware implementation of this format.

rawabstract:
The IBM POWER6 microprocessor core includes two accelerators for increasing performance of specific workloads. The vector multimedia extension (VMX) provides a vector acceleration of graphic and scientific workloads. It provides single instructions that work on multiple data elements. The instructions separate a 128-bit vector into different components that are operated on concurrently. The decimal floating-point unit (DFU) provides acceleration of commercial workloads, more specifically, financial transactions. It provides a new number system that performs implicit rounding to decimal radix points, a feature essential to monetary transactions. The IBM POWER processor instruction set is substantially expanded with the addition of these two accelerators. The VMX architecture contains 176 instructions, while the DFU architecture adds 54 instructions to the base architecture. The IEEE 754R Binary Floating-Point Arithmetic Standard defines decimal floating-point formats, and the POWER6 processor---on which a substantial amount of area has been devoted to increasing performance of both scientific and commercial workloads---is the first commercial hardware implementation of this format.

rawauthor:
L. Eisen and J. W. {Ward III} and H.-W. Tast and N. M{\"a}ding and J. Leenstra and S. M. Mueller and C. Jacobi and J. Preiss and E. M. Schwarz and S. R. Carlough

entry:
@Article{Eisen:2007:IPA,
  author =       "L. Eisen and J. W. {Ward III} and H.-W. Tast and N.
                 M{\"a}ding and J. Leenstra and S. M. Mueller and C.
                 Jacobi and J. Preiss and E. M. Schwarz and S. R.
                 Carlough",
  title =        "{IBM POWER6} accelerators: {VMX} and {DFU}",
  journal =      j-IBM-JRD,
  volume =       "51",
  number =       "6",
  pages =        "663--683",
  month =        nov,
  year =         "2007",
  CODEN =        "IBMJAE",
  ISSN =         "0018-8646 (print), 2151-8556 (electronic)",
  ISSN-L =       "0018-8646",
  bibdate =      "Mon Jul 7 21:49:07 MDT 2008",
  bibsource =    "http://www.research.ibm.com/journal/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.research.ibm.com/journal/rd/516/eisen.html",
  abstract =     "The IBM POWER6 microprocessor core includes two
                 accelerators for increasing performance of specific
                 workloads. The vector multimedia extension (VMX)
                 provides a vector acceleration of graphic and
                 scientific workloads. It provides single instructions
                 that work on multiple data elements. The instructions
                 separate a 128-bit vector into different components
                 that are operated on concurrently. The decimal
                 floating-point unit (DFU) provides acceleration of
                 commercial workloads, more specifically, financial
                 transactions. It provides a new number system that
                 performs implicit rounding to decimal radix points, a
                 feature essential to monetary transactions. The IBM
                 POWER processor instruction set is substantially
                 expanded with the addition of these two accelerators.
                 The VMX architecture contains 176 instructions, while
                 the DFU architecture adds 54 instructions to the base
                 architecture. The IEEE 754R Binary Floating-Point
                 Arithmetic Standard defines decimal floating-point
                 formats, and the POWER6 processor---on which a
                 substantial amount of area has been devoted to
                 increasing performance of both scientific and
                 commercial workloads---is the first commercial hardware
                 implementation of this format.",
  acknowledgement = ack-nhfb,
  fjournal =     "IBM Journal of Research and Development",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5288520",
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Eisinberg:2007:AFP
author: A. Eisinberg and G. Fedele
title: Accurate floating-point summation: a new approach
journal: j-APPL-MATH-COMP
volume: 189
number: 1
pages: 410--424
year: 2007
CODEN: AMHCBQ
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
MRclass: 65B10
MRnumber: MR2330219
bibdate: Thu Nov 8 19:16:14 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 19:16:14 ???
fjournal: Applied Mathematics and Computation
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: A. Eisinberg and G. Fedele
rawtitle: Accurate floating-point summation: a new approach
abstract:
The aim of this paper is to find an accurate and efficient algorithm for evaluating the summation of large sets of floating-point numbers. We present a new representation of the floating-point number system in which a number is represented as a linear combination of integers and the coefficients are powers of the base of the floating-point system. The approach allows to build up an accurate floating-point summation algorithm based on the fact that no rounding error occurs whenever two integer numbers are summed or a floating-point number is multiplied by powers of the base of the floating-point system. The proposed algorithm seems to be competitive in terms of computational effort and, under some assumptions, the computed sum is greatly accurate. With such assumptions, less-conservative in the practical applications, we prove that the relative error of the computed sum is bounded by the unit roundoff.

rawabstract:
The aim of this paper is to find an accurate and efficient algorithm for evaluating the summation of large sets of floating-point numbers. We present a new representation of the floating-point number system in which a number is represented as a linear combination of integers and the coefficients are powers of the base of the floating-point system. The approach allows to build up an accurate floating-point summation algorithm based on the fact that no rounding error occurs whenever two integer numbers are summed or a floating-point number is multiplied by powers of the base of the floating-point system. The proposed algorithm seems to be competitive in terms of computational effort and, under some assumptions, the computed sum is greatly accurate. With such assumptions, less-conservative in the practical applications, we prove that the relative error of the computed sum is bounded by the unit roundoff.

entry:
@Article{Eisinberg:2007:AFP,
  author =       "A. Eisinberg and G. Fedele",
  title =        "Accurate floating-point summation: a new approach",
  journal =      j-APPL-MATH-COMP,
  volume =       "189",
  number =       "1",
  pages =        "410--424",
  year =         "2007",
  CODEN =        "AMHCBQ",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  MRclass =      "65B10",
  MRnumber =     "MR2330219",
  bibdate =      "Thu Nov 8 19:16:14 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The aim of this paper is to find an accurate and
                 efficient algorithm for evaluating the summation of
                 large sets of floating-point numbers. We present a new
                 representation of the floating-point number system in
                 which a number is represented as a linear combination
                 of integers and the coefficients are powers of the base
                 of the floating-point system. The approach allows to
                 build up an accurate floating-point summation algorithm
                 based on the fact that no rounding error occurs
                 whenever two integer numbers are summed or a
                 floating-point number is multiplied by powers of the
                 base of the floating-point system. The proposed
                 algorithm seems to be competitive in terms of
                 computational effort and, under some assumptions, the
                 computed sum is greatly accurate. With such
                 assumptions, less-conservative in the practical
                 applications, we prove that the relative error of the
                 computed sum is bounded by the unit roundoff.",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
  keywords =     "accurate floating-point summation",
}


bibtype: article
filename: fparith.bib
label: Ercegovac:2007:CSR
author: Milos D. Ercegovac and Jean-Michel Muller
title: Complex Square Root with Operand Prescaling
journal: j-J-VLSI-SIGNAL-PROC
volume: 49
number: 1
pages: 19--30
month: oct
monthnumber: 10
year: 2007
CODEN: JVSPED
DOI: https://doi.org/10.1007/s11265-006-0029-2
ISSN: 0922-5773 (print), 1573-109x (electronic) OR 09225773 (print), 1573109x (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Mon Nov 05 19:24:36 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.05 19:24:36 ???
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
rawauthor: Milo{\v{s}} D. Ercegovac and Jean-Michel Muller
rawtitle: Complex Square Root with Operand Prescaling
abstract:
We propose a radix-$r$ digit-recurrence algorithm for complex square-root. The operand is prescaled to allow the selection of square-root digits by rounding of the residual. This leads to a simple hardware implementation of digit selection. Moreover, the use of digit recurrence approach allows correct rounding of the result if needed. The algorithm, compatible with the complex division presented in Ercegovac and Muller (``Complex Division with Prescaling of the Operands,'' in Proc. Application-Specific Systems, Architectures, and Processors (ASAP'03), The Hague, The Netherlands, June 24---26, 2003), and its design are described. We also give rough estimates of its latency and cost with respect to implementation based on standard floating-point instructions as used in software routines for complex square root.

rawabstract:
We propose a radix-$r$ digit-recurrence algorithm for complex square-root. The operand is prescaled to allow the selection of square-root digits by rounding of the residual. This leads to a simple hardware implementation of digit selection. Moreover, the use of digit recurrence approach allows correct rounding of the result if needed. The algorithm, compatible with the complex division presented in Ercegovac and Muller (``Complex Division with Prescaling of the Operands,'' in Proc. Application-Specific Systems, Architectures, and Processors (ASAP'03), The Hague, The Netherlands, June 24---26, 2003), and its design are described. We also give rough estimates of its latency and cost with respect to implementation based on standard floating-point instructions as used in software routines for complex square root.

entry:
@Article{Ercegovac:2007:CSR,
  author =       "Milo{\v{s}} D. Ercegovac and Jean-Michel Muller",
  title =        "Complex Square Root with Operand Prescaling",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "49",
  number =       "1",
  pages =        "19--30",
  month =        oct,
  year =         "2007",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1007/s11265-006-0029-2",
  ISSN =         "0922-5773 (print), 1573-109x (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Mon Nov 05 19:24:36 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We propose a radix-$r$ digit-recurrence algorithm for
                 complex square-root. The operand is prescaled to allow
                 the selection of square-root digits by rounding of the
                 residual. This leads to a simple hardware
                 implementation of digit selection. Moreover, the use of
                 digit recurrence approach allows correct rounding of
                 the result if needed. The algorithm, compatible with
                 the complex division presented in Ercegovac and Muller
                 (``Complex Division with Prescaling of the Operands,''
                 in Proc. Application-Specific Systems, Architectures,
                 and Processors (ASAP'03), The Hague, The Netherlands,
                 June 24---26, 2003), and its design are described. We
                 also give rough estimates of its latency and cost with
                 respect to implementation based on standard
                 floating-point instructions as used in software
                 routines for complex square root.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of VLSI Signal Processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Ercegovac:2007:HOM
author: Milos D. Ercegovac and Jean-Michel Muller
editor: IEEE
title: A Hardware-Oriented Method for Evaluating Complex Polynomials
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 122--127
year: 2007
DOI: https://doi.org/10.1109/ASAP.2007.4429968
ISBN: 1-4244-1027-4 OR 1424410274
ISBN13: 978-1-4244-1027-9 OR 9781424410279
bibdate: Fri Sep 29 10:42:47 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 10:42:47 ???
acknowledgement: ack-nhfb
rawauthor: Milo{\v{s}} D. Ercegovac and Jean-Michel Muller
raweditor: {IEEE}
rawtitle: A Hardware-Oriented Method for Evaluating Complex Polynomials
booktitle:
2007 IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Montreal, Canada, July 8--11, 2007

rawbooktitle:
{2007 IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Montr{\'e}al, Canada, July 8--11, 2007}

entry:
@InProceedings{Ercegovac:2007:HOM,
  author =       "Milo{\v{s}} D. Ercegovac and Jean-Michel Muller",
  editor =       "{IEEE}",
  booktitle =    "{2007 IEEE International Conference on
                 Application-specific Systems, Architectures and
                 Processors (ASAP), Montr{\'e}al, Canada, July 8--11,
                 2007}",
  title =        "A Hardware-Oriented Method for Evaluating Complex
                 Polynomials",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "122--127",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ASAP.2007.4429968",
  ISBN =         "1-4244-1027-4",
  ISBN-13 =      "978-1-4244-1027-9",
  bibdate =      "Fri Sep 29 10:42:47 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Erle:2007:DFP
author: Mark A. Erle and Michael J. Schulte and Brian J. Hickmann
title: Decimal Floating-Point Multiplication Via Carry-Save Addition
crossref: Kornerup:2007:PIS
pages: 46--55
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.14
bibdate: Tue Oct 9 16:32:41 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 16:32:41 MDT
URL: http://www.lirmm.fr/arith18/papers/erlem-DFPmultiplication-v2.pdf
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Mark A. Erle and Michael J. Schulte and Brian J. Hickmann
rawtitle: Decimal Floating-Point Multiplication Via Carry-Save Addition
abstract:
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents the design of a decimal floating-point multiplier that complies with specifications for decimal multiplication given in the draft revision of the IEEE 754 Standard for Floating-point Arithmetic (IEEE 754R). This multiplier extends a previously published decimal fixedpoint multiplier design by adding several features including exponent generation, sticky bit generation, shifting of the intermediate product, rounding, and exception detection and handling. The core of the decimal multiplication algorithm is an iterative scheme of partial product accumulation employing decimal carry-save addition to reduce the critical path delay. Novel features of the proposed multiplier include support for decimal floating-point numbers, on-the-fly generation of the sticky bit, early estimation of the shift amount, and efficient decimal rounding. Area and delay estimates are provided for a verified Verilog register transfer level model of the multiplier.

rawabstract:
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents the design of a decimal floating-point multiplier that complies with specifications for decimal multiplication given in the draft revision of the IEEE 754 Standard for Floating-point Arithmetic (IEEE 754R). This multiplier extends a previously published decimal fixedpoint multiplier design by adding several features including exponent generation, sticky bit generation, shifting of the intermediate product, rounding, and exception detection and handling. The core of the decimal multiplication algorithm is an iterative scheme of partial product accumulation employing decimal carry-save addition to reduce the critical path delay. Novel features of the proposed multiplier include support for decimal floating-point numbers, on-the-fly generation of the sticky bit, early estimation of the shift amount, and efficient decimal rounding. Area and delay estimates are provided for a verified Verilog register transfer level model of the multiplier.

entry:
@InProceedings{Erle:2007:DFP,
  author =       "Mark A. Erle and Michael J. Schulte and Brian J.
                 Hickmann",
  title =        "Decimal Floating-Point Multiplication Via Carry-Save
                 Addition",
  crossref =     "Kornerup:2007:PIS",
  pages =        "46--55",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.14",
  bibdate =      "Tue Oct 9 16:32:41 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.lirmm.fr/arith18/papers/erlem-DFPmultiplication-v2.pdf",
  abstract =     "Decimal multiplication is important in many commercial
                 applications including financial analysis, banking, tax
                 calculation, currency conversion, insurance, and
                 accounting. This paper presents the design of a decimal
                 floating-point multiplier that complies with
                 specifications for decimal multiplication given in the
                 draft revision of the IEEE 754 Standard for
                 Floating-point Arithmetic (IEEE 754R). This multiplier
                 extends a previously published decimal fixedpoint
                 multiplier design by adding several features including
                 exponent generation, sticky bit generation, shifting of
                 the intermediate product, rounding, and exception
                 detection and handling. The core of the decimal
                 multiplication algorithm is an iterative scheme of
                 partial product accumulation employing decimal
                 carry-save addition to reduce the critical path delay.
                 Novel features of the proposed multiplier include
                 support for decimal floating-point numbers, on-the-fly
                 generation of the sticky bit, early estimation of the
                 shift amount, and efficient decimal rounding. Area and
                 delay estimates are provided for a verified Verilog
                 register transfer level model of the multiplier.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: article
filename: fparith.bib
label: Fan:2007:NAS
author: Haining Fan and M. Anwar Hasan
title: A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields
journal: j-IEEE-TRANS-COMPUT
volume: 56
number: 2
pages: 224--233
month: feb
monthnumber: 2
year: 2007
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.19
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:03:37 MDT 2011
bibtimestamp: 2011.07.04 15:03:37 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4042682
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Haining Fan and M. Anwar Hasan
rawtitle: A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields
entry:
@Article{Fan:2007:NAS,
  author =       "Haining Fan and M. Anwar Hasan",
  title =        "A New Approach to Subquadratic Space Complexity
                 Parallel Multipliers for Extended Binary Fields",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "56",
  number =       "2",
  pages =        "224--233",
  month =        feb,
  year =         "2007",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.19",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:03:37 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4042682",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Fan:2007:SCC
author: Haining Fan and M. Anwar Hasan
journal: j-IEEE-TRANS-COMPUT
volume: 56
number: 10
pages: 1435--1437
month: oct
monthnumber: 10
year: 2007
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.1076
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:03:42 MDT 2011
bibtimestamp: 2011.07.04 15:03:42 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4302715
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Haining Fan and M. Anwar Hasan
title:
Subquadratic Computational Complexity Schemes for Extended Binary Field Multiplication Using Optimal Normal Bases

rawtitle:
Subquadratic Computational Complexity Schemes for Extended Binary Field Multiplication Using Optimal Normal Bases

entry:
@Article{Fan:2007:SCC,
  author =       "Haining Fan and M. Anwar Hasan",
  title =        "Subquadratic Computational Complexity Schemes for
                 Extended Binary Field Multiplication Using Optimal
                 Normal Bases",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "56",
  number =       "10",
  pages =        "1435--1437",
  month =        oct,
  year =         "2007",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.1076",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:03:42 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4302715",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Fousse:2007:AMP
author: Laurent Fousse
title: Accurate Multiple-Precision Gauss--Legendre Quadrature
crossref: Kornerup:2007:PIS
pages: 150--160
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.8
bibdate: Tue Oct 9 16:32:41 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 16:32:41 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Laurent Fousse
rawtitle: Accurate Multiple-Precision {Gauss--Legendre} Quadrature
abstract:
Numerical integration is an operation that is frequently available in multiple precision numerical software packages. The different quadrature schemes used are considered well studied but the rounding errors that result from the computation are often neglected, and the actual accuracy of the results are therefore seldom rigorously proven. We propose an implementation of the Gauss--Legendre quadrature scheme with bounded error: given a bound on the derivatives of a function we are able to compute an interval containing the true value of the integral, in arbitrary precision. The error analysis is given as well as experimental error measurements and timings, and a complete quadrature example.

rawabstract:
Numerical integration is an operation that is frequently available in multiple precision numerical software packages. The different quadrature schemes used are considered well studied but the rounding errors that result from the computation are often neglected, and the actual accuracy of the results are therefore seldom rigorously proven. We propose an implementation of the Gauss--Legendre quadrature scheme with bounded error: given a bound on the derivatives of a function we are able to compute an interval containing the true value of the integral, in arbitrary precision. The error analysis is given as well as experimental error measurements and timings, and a complete quadrature example.

entry:
@InProceedings{Fousse:2007:AMP,
  author =       "Laurent Fousse",
  title =        "Accurate Multiple-Precision {Gauss--Legendre}
                 Quadrature",
  crossref =     "Kornerup:2007:PIS",
  pages =        "150--160",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.8",
  bibdate =      "Tue Oct 9 16:32:41 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Numerical integration is an operation that is
                 frequently available in multiple precision numerical
                 software packages. The different quadrature schemes
                 used are considered well studied but the rounding
                 errors that result from the computation are often
                 neglected, and the actual accuracy of the results are
                 therefore seldom rigorously proven. We propose an
                 implementation of the Gauss--Legendre quadrature scheme
                 with bounded error: given a bound on the derivatives of
                 a function we are able to compute an interval
                 containing the true value of the integral, in arbitrary
                 precision. The error analysis is given as well as
                 experimental error measurements and timings, and a
                 complete quadrature example.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: article
filename: fparith.bib
label: Fousse:2007:MMP
author: Laurent Fousse and Guillaume Hanrot and Vincent Lefevre and Patrick Pelissier and Paul Zimmermann
title: MPFR: a multiple-precision binary floating-point library with correct rounding
journal: j-TOMS
volume: 33
number: 2
pages: 1--15
month: jun
monthnumber: 6
year: 2007
CODEN: ACMSCU
DOI: https://doi.org/10.1145/1236463.1236468
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
MRclass: 65G99
MRnumber: MR2326955
bibdate: Thu Jul 26 17:36:59 MDT 2007
bibtimestamp: 2007.07.26 17:36:59 MDT
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 13
journalURL: https://dl.acm.org/loi/toms
rawtitle: {MPFR}: a multiple-precision binary floating-point library with correct rounding
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

abstract:
This article presents a multiple-precision binary floating-point library, written in the ISO C language, and based on the GNU MP library. Its particularity is to extend to arbitrary-precision, ideas from the IEEE 754 standard, by providing correct rounding and exceptions. We demonstrate how these strong semantics are achieved---with no significant slowdown with respect to other arbitrary-precision tools---and discuss a few applications where such a library can be useful.

rawabstract:
This article presents a multiple-precision binary floating-point library, written in the ISO C language, and based on the GNU MP library. Its particularity is to extend to arbitrary-precision, ideas from the IEEE 754 standard, by providing correct rounding and exceptions. We demonstrate how these strong semantics are achieved---with no significant slowdown with respect to other arbitrary-precision tools---and discuss a few applications where such a library can be useful.

rawauthor:
Laurent Fousse and Guillaume Hanrot and Vincent Lef{\`e}vre and Patrick P{\'e}lissier and Paul Zimmermann

entry:
@Article{Fousse:2007:MMP,
  author =       "Laurent Fousse and Guillaume Hanrot and Vincent
                 Lef{\`e}vre and Patrick P{\'e}lissier and Paul
                 Zimmermann",
  title =        "{MPFR}: a multiple-precision binary floating-point
                 library with correct rounding",
  journal =      j-TOMS,
  volume =       "33",
  number =       "2",
  pages =        "1--15",
  month =        jun,
  year =         "2007",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/1236463.1236468",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  MRclass =      "65G99",
  MRnumber =     "MR2326955",
  bibdate =      "Thu Jul 26 17:36:59 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  abstract =     "This article presents a multiple-precision binary
                 floating-point library, written in the ISO C language,
                 and based on the GNU MP library. Its particularity is
                 to extend to arbitrary-precision, ideas from the IEEE
                 754 standard, by providing correct rounding and
                 exceptions. We demonstrate how these strong semantics
                 are achieved---with no significant slowdown with
                 respect to other arbitrary-precision tools---and
                 discuss a few applications where such a library can be
                 useful.",
  acknowledgement = ack-nhfb,
  articleno =    "13",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Fousse:2007:MPC
author: Laurent Fousse
title: Multiple-Precision Correctly rounded Newton--Cotes quadrature
journal: j-INFORM-THEOR-APPL
volume: 41
number: 1
pages: 103--121
month: jan
monthnumber: 1
year: 2007
CODEN: RSITD7, RITAE4
DOI: https://doi.org/10.1051/ita:2007004
ISSN: 0988-3754 (print), 1290-385X (electronic) OR 09883754 (print), 1290385X (electronic)
ISSNL: 0988-3754 OR 09883754
bibdate: Fri Dec 8 09:50:26 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.08 09:50:26 ???
fjournal: RAIRO. Informatique theorique et applications := Theoretical informatics and applications
acknowledgement: ack-nhfb
rawauthor: Laurent Fousse
rawtitle: Multiple-Precision Correctly rounded {Newton--Cotes} quadrature
entry:
@Article{Fousse:2007:MPC,
  author =       "Laurent Fousse",
  title =        "Multiple-Precision Correctly rounded {Newton--Cotes}
                 quadrature",
  journal =      j-INFORM-THEOR-APPL,
  volume =       "41",
  number =       "1",
  pages =        "103--121",
  month =        jan,
  year =         "2007",
  CODEN =        "RSITD7, RITAE4",
  DOI =          "https://doi.org/10.1051/ita:2007004",
  ISSN =         "0988-3754 (print), 1290-385X (electronic)",
  ISSN-L =       "0988-3754",
  bibdate =      "Fri Dec 8 09:50:26 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "RAIRO. Informatique th{\'e}orique et applications :=
                 Theoretical informatics and applications",
}


bibtype: article
filename: fparith.bib
label: Frommer:2007:PEZ
author: A. Frommer and F. Hoxha and B. Lang
title: Proving the existence of zeros using the topological degree and interval arithmetic
journal: j-J-COMPUT-APPL-MATH
volume: 199
number: 2
pages: 397--402
day: 15
month: feb
monthnumber: 2
year: 2007
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:12:04 MST 2017
bibtimestamp: 2017.02.25 13:12:04 MST
URL: http://www.sciencedirect.com/science/article/pii/S0377042705007788
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: A. Frommer and F. Hoxha and B. Lang
rawtitle: Proving the existence of zeros using the topological degree and interval arithmetic
entry:
@Article{Frommer:2007:PEZ,
  author =       "A. Frommer and F. Hoxha and B. Lang",
  title =        "Proving the existence of zeros using the topological
                 degree and interval arithmetic",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "199",
  number =       "2",
  pages =        "397--402",
  day =          "15",
  month =        feb,
  year =         "2007",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:12:04 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2005.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042705007788",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: inproceedings
filename: fparith.bib
label: Furer:2007:FIM
author: Martin Furer
title: Faster integer multiplication
crossref: ACM:2007:SPA
pages: 57--66
year: 2007
DOI: https://doi.org/10.1145/1250790.1250800
bibdate: Fri Jun 20 18:28:53 MDT 2008
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.06.20 18:28:53 MDT
keywords: complexity; computer arithmetic; discrete Fourier transform; FFT; integer multiplication
acknowledgement: ack-nhfb
rawauthor: Martin F{\"u}rer
rawtitle: Faster integer multiplication
abstract:
For more than 35 years, the fastest known method for integer multiplication has been the Schonhage-Strassen algorithm running in time $ O(n log n log log n) $. Under certain restrictive conditions there is a corresponding $ Omega (n log n) $ lower bound. The prevailing conjecture has always been that the complexity of an optimal algorithm is $ Theta (n log n) $. We present a major step towards closing the gap from above by presenting an algorithm running in time $ n log n, 2^O(log * n) $.par The main result is for Boolean circuits as well as for multitape Turing machines, but it has consequences to other models of computation as well.

rawabstract:
For more than 35 years, the fastest known method for integer multiplication has been the Sch{\"o}nhage-Strassen algorithm running in time $ O(n \log n \log \log n) $. Under certain restrictive conditions there is a corresponding $ \Omega (n \log n) $ lower bound. The prevailing conjecture has always been that the complexity of an optimal algorithm is $ \Theta (n \log n) $. We present a major step towards closing the gap from above by presenting an algorithm running in time $ n \log n, 2^{O(\log * n)} $.\par The main result is for Boolean circuits as well as for multitape Turing machines, but it has consequences to other models of computation as well.

entry:
@InProceedings{Furer:2007:FIM,
  author =       "Martin F{\"u}rer",
  title =        "Faster integer multiplication",
  crossref =     "ACM:2007:SPA",
  pages =        "57--66",
  year =         "2007",
  DOI =          "https://doi.org/10.1145/1250790.1250800",
  bibdate =      "Fri Jun 20 18:28:53 MDT 2008",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "For more than 35 years, the fastest known method for
                 integer multiplication has been the
                 Sch{\"o}nhage-Strassen algorithm running in time $ O(n
                 \log n \log \log n) $. Under certain restrictive
                 conditions there is a corresponding $ \Omega (n \log n)
                 $ lower bound. The prevailing conjecture has always
                 been that the complexity of an optimal algorithm is $
                 \Theta (n \log n) $. We present a major step towards
                 closing the gap from above by presenting an algorithm
                 running in time $ n \log n, 2^{O(\log * n)} $.\par

                 The main result is for Boolean circuits as well as for
                 multitape Turing machines, but it has consequences to
                 other models of computation as well.",
  acknowledgement = ack-nhfb,
  keywords =     "complexity; computer arithmetic; discrete Fourier
                 transform; FFT; integer multiplication",
}


bibtype: inproceedings
filename: fparith.bib
label: Gaudry:2007:GBI
author: Pierrick Gaudry and Alexander Kruppa and Paul Zimmermann
title: A tt gmp-based implementation of Schonhage--Strassen's large integer multiplication algorithm
crossref: Brown:2007:PIS
pages: 167--174
year: 2007
DOI: https://doi.org/10.1145/1277548.1277572
bibdate: Fri Jun 20 08:46:50 MDT 2008
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.06.20 08:46:50 MDT
keywords: integer multiplication; multiprecision arithmetic
acknowledgement: ack-nhfb
rawauthor: Pierrick Gaudry and Alexander Kruppa and Paul Zimmermann
abstract:
Schonhage--Strassen's algorithm is one of the best known algorithms for multiplying large integers. Implementing it efficiently is of utmost importance, since many other algorithms rely on it as a subroutine. We present here an improved implementation, based on the one distributed within the GMP library. The following ideas and techniques were used or tried: faster arithmetic modulo $ 2^n + 1 $, improved cache locality, Mersenne transforms, Chinese Remainder Reconstruction, the $ sqrt 2 $ trick, Harley's and Granlund's tricks, improved tuning.

rawabstract:
Sch{\"o}nhage--Strassen's algorithm is one of the best known algorithms for multiplying large integers. Implementing it efficiently is of utmost importance, since many other algorithms rely on it as a subroutine. We present here an improved implementation, based on the one distributed within the GMP library. The following ideas and techniques were used or tried: faster arithmetic modulo $ 2^n + 1 $, improved cache locality, Mersenne transforms, Chinese Remainder Reconstruction, the $ \sqrt 2 $ trick, Harley's and Granlund's tricks, improved tuning.

rawtitle:
A {\tt gmp}-based implementation of {Sch{\"o}nhage--Strassen}'s large integer multiplication algorithm

entry:
@InProceedings{Gaudry:2007:GBI,
  author =       "Pierrick Gaudry and Alexander Kruppa and Paul
                 Zimmermann",
  title =        "A {\tt gmp}-based implementation of
                 {Sch{\"o}nhage--Strassen}'s large integer
                 multiplication algorithm",
  crossref =     "Brown:2007:PIS",
  pages =        "167--174",
  year =         "2007",
  DOI =          "https://doi.org/10.1145/1277548.1277572",
  bibdate =      "Fri Jun 20 08:46:50 MDT 2008",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Sch{\"o}nhage--Strassen's algorithm is one of the best
                 known algorithms for multiplying large integers.
                 Implementing it efficiently is of utmost importance,
                 since many other algorithms rely on it as a subroutine.
                 We present here an improved implementation, based on
                 the one distributed within the GMP library. The
                 following ideas and techniques were used or tried:
                 faster arithmetic modulo $ 2^n + 1 $, improved cache
                 locality, Mersenne transforms, Chinese Remainder
                 Reconstruction, the $ \sqrt 2 $ trick, Harley's and
                 Granlund's tricks, improved tuning.",
  acknowledgement = ack-nhfb,
  keywords =     "integer multiplication; multiprecision arithmetic",
}


bibtype: article
filename: fparith.bib
label: Goel:2007:RMS
author: S. Goel and S. K. Dash
title: Response of model simulated weather parameters to round-off-errors on different systems
journal: Environmental Modelling & Software
volume: 22
number: 8
pages: 1164--1174
month: aug
monthnumber: 8
year: 2007
CODEN: EMSOFT
DOI: https://doi.org/10.1016/j.envsoft.2006.06.011
ISSN: 1364-8152 (print), 1873-6726 (electronic) OR 13648152 (print), 18736726 (electronic)
ISSNL: 1364-8152 OR 13648152
bibdate: Fri Aug 08 08:49:37 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.08 08:49:37 ???
keywords: round-off error; rounding error
acknowledgement: ack-nhfb
ajournal: Environ. Model. Softw.
journalURL: https://www.sciencedirect.com/journal/environmental-modelling-and-software
rawauthor: S. Goel and S. K. Dash
rawtitle: Response of model simulated weather parameters to round-off-errors on different systems
abstract:
In this study, the weather forecasting model of the National Centre for Medium Range Weather Forecasting (NCMRWF) is used for examining the characteristics of round-off-errors on three different computer architectures --- PARAM 10K, SUNFIRE 6800 and Dec Alpha for several meteorological parameters such as precipitation, temperature at the surface and mid-atmosphere, and upper and lower level winds. It is well known that the implementation of floating point arithmetic varies from one computing system to another. As a result, meteorological parameters simulated by numerical models on two different systems may deviate from each other and the difference field becomes larger as the model is integrated for longer time, for example, in the scale of several months. This paper focuses on the reduction of such round-off-errors by a simple method of modifying the format representation of the initial data supplied to the model. In all the three systems, the model has been integrated for 4 months starting from 4th May, 1996. It is found that after 5 days of model integration with the modified data, the round-off-errors become insignificant. The rate of reduction of round-off-errors is fast up to a month of model integration and thereafter the rate slows down and stabilises. It is further noticed that at the end of four months of integration, the reduction in round-off-errors over the tropical region and oceans is much more than over the rest of the globe.

rawabstract:
In this study, the weather forecasting model of the National Centre for Medium Range Weather Forecasting (NCMRWF) is used for examining the characteristics of round-off-errors on three different computer architectures --- PARAM 10K, SUNFIRE 6800 and Dec Alpha for several meteorological parameters such as precipitation, temperature at the surface and mid-atmosphere, and upper and lower level winds. It is well known that the implementation of floating point arithmetic varies from one computing system to another. As a result, meteorological parameters simulated by numerical models on two different systems may deviate from each other and the difference field becomes larger as the model is integrated for longer time, for example, in the scale of several months. This paper focuses on the reduction of such round-off-errors by a simple method of modifying the format representation of the initial data supplied to the model. In all the three systems, the model has been integrated for 4 months starting from 4th May, 1996. It is found that after 5 days of model integration with the modified data, the round-off-errors become insignificant. The rate of reduction of round-off-errors is fast up to a month of model integration and thereafter the rate slows down and stabilises. It is further noticed that at the end of four months of integration, the reduction in round-off-errors over the tropical region and oceans is much more than over the rest of the globe.

entry:
@Article{Goel:2007:RMS,
  author =       "S. Goel and S. K. Dash",
  title =        "Response of model simulated weather parameters to
                 round-off-errors on different systems",
  journal =      "Environmental Modelling \& Software",
  volume =       "22",
  number =       "8",
  pages =        "1164--1174",
  month =        aug,
  year =         "2007",
  CODEN =        "EMSOFT",
  DOI =          "https://doi.org/10.1016/j.envsoft.2006.06.011",
  ISSN =         "1364-8152 (print), 1873-6726 (electronic)",
  ISSN-L =       "1364-8152",
  bibdate =      "Fri Aug 08 08:49:37 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this study, the weather forecasting model of the
                 National Centre for Medium Range Weather Forecasting
                 (NCMRWF) is used for examining the characteristics of
                 round-off-errors on three different computer
                 architectures --- PARAM 10K, SUNFIRE 6800 and Dec Alpha
                 for several meteorological parameters such as
                 precipitation, temperature at the surface and
                 mid-atmosphere, and upper and lower level winds. It is
                 well known that the implementation of floating point
                 arithmetic varies from one computing system to another.
                 As a result, meteorological parameters simulated by
                 numerical models on two different systems may deviate
                 from each other and the difference field becomes larger
                 as the model is integrated for longer time, for
                 example, in the scale of several months. This paper
                 focuses on the reduction of such round-off-errors by a
                 simple method of modifying the format representation of
                 the initial data supplied to the model. In all the
                 three systems, the model has been integrated for 4
                 months starting from 4th May, 1996. It is found that
                 after 5 days of model integration with the modified
                 data, the round-off-errors become insignificant. The
                 rate of reduction of round-off-errors is fast up to a
                 month of model integration and thereafter the rate
                 slows down and stabilises. It is further noticed that
                 at the end of four months of integration, the reduction
                 in round-off-errors over the tropical region and oceans
                 is much more than over the rest of the globe.",
  acknowledgement = ack-nhfb,
  ajournal =     "Environ. Model. Softw.",
  journal-URL =  "https://www.sciencedirect.com/journal/environmental-modelling-and-software",
  keywords =     "round-off error; rounding error",
}


bibtype: inproceedings
filename: fparith.bib
label: Goldberg:2007:FIP
author: R. Goldberg and G. Even and P.-M. Seidel
title: An FPGA implementation of pipelined multiplicative division with IEEE rounding
crossref: Pocek:2007:PAI
pages: 185--196
year: 2007
DOI: https://doi.org/10.1109/FCCM.2007.59
bibdate: Sat Oct 9 12:43:39 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.10.09 12:43:39 ???
acknowledgement: ack-nhfb
rawauthor: R. Goldberg and G. Even and P.-M. Seidel
rawtitle: An {FPGA} implementation of pipelined multiplicative division with {IEEE} rounding
abstract:
We report the results of an FPGA implementation of double precision floating-point division with IEEE rounding. We achieve a total latency (i.e., cycles times clock period) that is 2:6 times smaller than the latency of the fastest previous implementation on FPGAs. The amount of hardware, on the other hand, is comparable to commercial cores. The division circuit is based on Goldschmidt's algorithm. All IEEE rounding modes are supported and are implemented using dewpoint rounding. The precision of the initial approximation of the reciprocal is 14 bits. To save hardware and reduce the critical path, a half-sized 62x30 Booth radix-8 multiplier is used. This multiplier can receive both the multiplicand and the multiplier in carry-save representation. The division circuit is partitioned into four pipeline stages, has a latency of 11 cycles, and may restart a new double precision division operation after 8 cycles. Synthesis results of an implementation (not including the computation of the initial approximation of the reciprocal and the exponent path) guarantee a clock frequency of 131 MHz on an Altera Stratix II using 3592 ALMs. The implementation was successfully tested with over 10 million random vectors as well as over a million hard-to-round vectors.

rawabstract:
We report the results of an FPGA implementation of double precision floating-point division with IEEE rounding. We achieve a total latency (i.e., cycles times clock period) that is 2:6 times smaller than the latency of the fastest previous implementation on FPGAs. The amount of hardware, on the other hand, is comparable to commercial cores. The division circuit is based on Goldschmidt's algorithm. All IEEE rounding modes are supported and are implemented using dewpoint rounding. The precision of the initial approximation of the reciprocal is 14 bits. To save hardware and reduce the critical path, a half-sized 62x30 Booth radix-8 multiplier is used. This multiplier can receive both the multiplicand and the multiplier in carry-save representation. The division circuit is partitioned into four pipeline stages, has a latency of 11 cycles, and may restart a new double precision division operation after 8 cycles. Synthesis results of an implementation (not including the computation of the initial approximation of the reciprocal and the exponent path) guarantee a clock frequency of 131 MHz on an Altera Stratix II using 3592 ALMs. The implementation was successfully tested with over 10 million random vectors as well as over a million hard-to-round vectors.

entry:
@InProceedings{Goldberg:2007:FIP,
  author =       "R. Goldberg and G. Even and P.-M. Seidel",
  title =        "An {FPGA} implementation of pipelined multiplicative
                 division with {IEEE} rounding",
  crossref =     "Pocek:2007:PAI",
  pages =        "185--196",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/FCCM.2007.59",
  bibdate =      "Sat Oct 9 12:43:39 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We report the results of an FPGA implementation of
                 double precision floating-point division with IEEE
                 rounding. We achieve a total latency (i.e., cycles
                 times clock period) that is 2:6 times smaller than the
                 latency of the fastest previous implementation on
                 FPGAs. The amount of hardware, on the other hand, is
                 comparable to commercial cores. The division circuit is
                 based on Goldschmidt's algorithm. All IEEE rounding
                 modes are supported and are implemented using dewpoint
                 rounding. The precision of the initial approximation of
                 the reciprocal is 14 bits. To save hardware and reduce
                 the critical path, a half-sized 62x30 Booth radix-8
                 multiplier is used. This multiplier can receive both
                 the multiplicand and the multiplier in carry-save
                 representation. The division circuit is partitioned
                 into four pipeline stages, has a latency of 11 cycles,
                 and may restart a new double precision division
                 operation after 8 cycles. Synthesis results of an
                 implementation (not including the computation of the
                 initial approximation of the reciprocal and the
                 exponent path) guarantee a clock frequency of 131 MHz
                 on an Altera Stratix II using 3592 ALMs. The
                 implementation was successfully tested with over 10
                 million random vectors as well as over a million
                 hard-to-round vectors.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Hanrot:2007:WCP
author: Guillaume Hanrot and Vincent Lefevre and Damien Stehle and Paul Zimmermann
title: Worst Cases of a Periodic Function for Large Arguments
crossref: Kornerup:2007:PIS
pages: 133--140
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.37
bibdate: Tue Oct 9 16:32:41 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 16:32:41 MDT
keywords: ARITH-18; correct rounding; floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Guillaume Hanrot and Vincent Lef{\`e}vre and Damien Stehle and Paul Zimmermann
rawtitle: Worst Cases of a Periodic Function for Large Arguments
abstract:
One considers the problem of finding hard to round cases of a periodic function for large floating-point inputs, more precisely when the function cannot be efficiently approximated by a polynomial. This is one of the last few issues that prevents from guaranteeing an efficient computation of correctly rounded transcendentals for the whole IEEE-754 double precision format. The first non-naive algorithm for that problem is presented, with a heuristic complexity of O(20.676p) for a precision of p bits. The efficiency of the algorithm is shown on the largest IEEE-754 double precision binade for the sine function, and some corresponding bad cases are given. We can hope that all the worst cases of the trigonometric functions in their whole domain will be found within a few years, a task that was considered out of reach until now.

rawabstract:
One considers the problem of finding hard to round cases of a periodic function for large floating-point inputs, more precisely when the function cannot be efficiently approximated by a polynomial. This is one of the last few issues that prevents from guaranteeing an efficient computation of correctly rounded transcendentals for the whole IEEE-754 double precision format. The first non-naive algorithm for that problem is presented, with a heuristic complexity of O(20.676p) for a precision of p bits. The efficiency of the algorithm is shown on the largest IEEE-754 double precision binade for the sine function, and some corresponding bad cases are given. We can hope that all the worst cases of the trigonometric functions in their whole domain will be found within a few years, a task that was considered out of reach until now.

entry:
@InProceedings{Hanrot:2007:WCP,
  author =       "Guillaume Hanrot and Vincent Lef{\`e}vre and Damien
                 Stehle and Paul Zimmermann",
  title =        "Worst Cases of a Periodic Function for Large
                 Arguments",
  crossref =     "Kornerup:2007:PIS",
  pages =        "133--140",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.37",
  bibdate =      "Tue Oct 9 16:32:41 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "One considers the problem of finding hard to round
                 cases of a periodic function for large floating-point
                 inputs, more precisely when the function cannot be
                 efficiently approximated by a polynomial. This is one
                 of the last few issues that prevents from guaranteeing
                 an efficient computation of correctly rounded
                 transcendentals for the whole IEEE-754 double precision
                 format. The first non-naive algorithm for that problem
                 is presented, with a heuristic complexity of O(20.676p)
                 for a precision of p bits. The efficiency of the
                 algorithm is shown on the largest IEEE-754 double
                 precision binade for the sine function, and some
                 corresponding bad cases are given. We can hope that all
                 the worst cases of the trigonometric functions in their
                 whole domain will be found within a few years, a task
                 that was considered out of reach until now.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18; correct rounding; floating-point
                 arithmetic",
}


bibtype: article
filename: fparith.bib
label: Harrison:2007:FPV
author: J. Harrison
title: Floating-Point Verification
journal: j-J-UCS
volume: 13
number: 5
pages: 629--638
year: 2007
ISSN: 0948-6968 OR 09486968
ISSNL: 0948-6968 OR 09486968
bibdate: Thu Jul 10 06:41:41 MDT 2008
bibsource: http://www.jucs.org/jucs; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.07.10 06:41:41 MDT
URL: http://www.jucs.org/jucs_13_5/floating_point_verification
fjournal: J.UCS: Journal of Universal Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.jucs.org/jucs
rawauthor: J. Harrison
rawtitle: Floating-Point Verification
abstract:
This paper overviews the application of formal verification techniques to hardware in general, and to floating-point hardware in particular. A specific challenge is to connect the usual mathematical view of continuous arithmetic operations with the discrete world, in a credible and verifiable way.

rawabstract:
This paper overviews the application of formal verification techniques to hardware in general, and to floating-point hardware in particular. A specific challenge is to connect the usual mathematical view of continuous arithmetic operations with the discrete world, in a credible and verifiable way.

entry:
@Article{Harrison:2007:FPV,
  author =       "J. Harrison",
  title =        "Floating-Point Verification",
  journal =      j-J-UCS,
  volume =       "13",
  number =       "5",
  pages =        "629--638",
  month =        "????",
  year =         "2007",
  CODEN =        "????",
  ISSN =         "0948-6968",
  ISSN-L =       "0948-6968",
  bibdate =      "Thu Jul 10 06:41:41 MDT 2008",
  bibsource =    "http://www.jucs.org/jucs;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.jucs.org/jucs_13_5/floating_point_verification",
  abstract =     "This paper overviews the application of formal
                 verification techniques to hardware in general, and to
                 floating-point hardware in particular. A specific
                 challenge is to connect the usual mathematical view of
                 continuous arithmetic operations with the discrete
                 world, in a credible and verifiable way.",
  acknowledgement = ack-nhfb,
  fjournal =     "J.UCS: Journal of Universal Computer Science",
  journal-URL =  "http://www.jucs.org/jucs",
}


bibtype: inproceedings
filename: fparith.bib
label: Hasenplaugh:2007:FMR
author: William Hasenplaugh and Gunnar Gaubatz and Vinodh Gopal
title: Fast Modular Reduction
crossref: Kornerup:2007:PIS
pages: 225--229
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.18
bibdate: Tue Oct 9 17:16:03 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 17:16:03 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: William Hasenplaugh and Gunnar Gaubatz and Vinodh Gopal
rawtitle: Fast Modular Reduction
abstract:
It is widely acknowledged that efficient modular multiplication is a key to high-performance implementation of public-key cryptography, be it classical RSA, Diffie--Hellman, or (hyper-) elliptic curve algorithms. In the recent decade, practitioners have relied mainly on two popular methods: Montgomery Multiplication and regular long-integer multiplication in combination with Barrett's modular reduction technique. In this paper, we propose a modification to Barrett's algorithm that leads to a significant reduction (25% to 75%) in multiplications and additions.

rawabstract:
It is widely acknowledged that efficient modular multiplication is a key to high-performance implementation of public-key cryptography, be it classical RSA, Diffie--Hellman, or (hyper-) elliptic curve algorithms. In the recent decade, practitioners have relied mainly on two popular methods: Montgomery Multiplication and regular long-integer multiplication in combination with Barrett's modular reduction technique. In this paper, we propose a modification to Barrett's algorithm that leads to a significant reduction (25\% to 75\%) in multiplications and additions.

entry:
@InProceedings{Hasenplaugh:2007:FMR,
  author =       "William Hasenplaugh and Gunnar Gaubatz and Vinodh
                 Gopal",
  title =        "Fast Modular Reduction",
  crossref =     "Kornerup:2007:PIS",
  pages =        "225--229",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.18",
  bibdate =      "Tue Oct 9 17:16:03 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "It is widely acknowledged that efficient modular
                 multiplication is a key to high-performance
                 implementation of public-key cryptography, be it
                 classical RSA, Diffie--Hellman, or (hyper-) elliptic
                 curve algorithms. In the recent decade, practitioners
                 have relied mainly on two popular methods: Montgomery
                 Multiplication and regular long-integer multiplication
                 in combination with Barrett's modular reduction
                 technique. In this paper, we propose a modification to
                 Barrett's algorithm that leads to a significant
                 reduction (25\% to 75\%) in multiplications and
                 additions.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: article
filename: fparith.bib
label: Hernandez:2007:MPO
author: M. A. Hernandez and N. Romero
title: Methods with prefixed order for approximating square roots with global and general convergence
journal: j-APPL-MATH-COMP
volume: 194
number: 2
pages: 346--353
day: 15
month: dec
monthnumber: 12
year: 2007
CODEN: AMHCBQ
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Sat Jul 12 09:03:09 MDT 2008
bibtimestamp: 2008.07.12 09:03:09 MDT
fjournal: Applied Mathematics and Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: M. A. Hern{\'a}ndez and N. Romero
rawtitle: Methods with prefixed order for approximating square roots with global and general convergence
entry:
@Article{Hernandez:2007:MPO,
  author =       "M. A. Hern{\'a}ndez and N. Romero",
  title =        "Methods with prefixed order for approximating square
                 roots with global and general convergence",
  journal =      j-APPL-MATH-COMP,
  volume =       "194",
  number =       "2",
  pages =        "346--353",
  day =          "15",
  month =        dec,
  year =         "2007",
  CODEN =        "AMHCBQ",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Sat Jul 12 09:03:09 MDT 2008",
  bibsource =    "http://www.sciencedirect.com/science/journal/00963003;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
}


bibtype: inproceedings
filename: fparith.bib
label: Hilewitz:2007:PAB
author: Yedidya Hilewitz and Ruby B. Lee
title: Performing Advanced Bit Manipulations Efficiently in General-Purpose Processors
crossref: Kornerup:2007:PIS
pages: 251--260
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.27
bibdate: Tue Oct 9 17:16:03 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 17:16:03 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Yedidya Hilewitz and Ruby B. Lee
rawtitle: Performing Advanced Bit Manipulations Efficiently in General-Purpose Processors
abstract:
This paper describes a new basis for the implementation of a shifter functional unit. We present a design based on the inverse butterfly and butterfly datapath circuits that performs the standard shift and rotate operations, as well as more advanced extract, deposit and mix operations found in some processors. Additionally, it also supports important new classes of even more advanced bit manipulation instructions recently proposed: these include arbitrary bit permutations, bit scatter and bit gather instructions. The new functional unit's datapath is comparable in latency to that of the classic barrel shifter. It replaces two existing functional units --- shifter and mix --- with a much more powerful one.

rawabstract:
This paper describes a new basis for the implementation of a shifter functional unit. We present a design based on the inverse butterfly and butterfly datapath circuits that performs the standard shift and rotate operations, as well as more advanced extract, deposit and mix operations found in some processors. Additionally, it also supports important new classes of even more advanced bit manipulation instructions recently proposed: these include arbitrary bit permutations, bit scatter and bit gather instructions. The new functional unit's datapath is comparable in latency to that of the classic barrel shifter. It replaces two existing functional units --- shifter and mix --- with a much more powerful one.

entry:
@InProceedings{Hilewitz:2007:PAB,
  author =       "Yedidya Hilewitz and Ruby B. Lee",
  title =        "Performing Advanced Bit Manipulations Efficiently in
                 General-Purpose Processors",
  crossref =     "Kornerup:2007:PIS",
  pages =        "251--260",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.27",
  bibdate =      "Tue Oct 9 17:16:03 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper describes a new basis for the
                 implementation of a shifter functional unit. We present
                 a design based on the inverse butterfly and butterfly
                 datapath circuits that performs the standard shift and
                 rotate operations, as well as more advanced extract,
                 deposit and mix operations found in some processors.
                 Additionally, it also supports important new classes of
                 even more advanced bit manipulation instructions
                 recently proposed: these include arbitrary bit
                 permutations, bit scatter and bit gather instructions.
                 The new functional unit's datapath is comparable in
                 latency to that of the classic barrel shifter. It
                 replaces two existing functional units --- shifter and
                 mix --- with a much more powerful one.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: article
filename: fparith.bib
label: Holmes:2007:BA
author: Neville Holmes
title: Binary Arithmetic
journal: j-COMPUTER
volume: 40
number: 6
pages: 90--93
month: jun
monthnumber: 6
year: 2007
CODEN: CPTRB4
DOI: https://doi.org/10.1109/MC.2007.196
ISSN: 0018-9162 (print), 1558-0814 (electronic) OR 00189162 (print), 15580814 (electronic)
ISSNL: 0018-9162 OR 00189162
bibdate: Fri Jun 29 14:19:11 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.06.29 14:19:11 ???
fjournal: Computer
keywords: complete arithmetic; interval arithmetic
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2
rawauthor: Neville Holmes
rawtitle: Binary Arithmetic
entry:
@Article{Holmes:2007:BA,
  author =       "Neville Holmes",
  title =        "Binary Arithmetic",
  journal =      j-COMPUTER,
  volume =       "40",
  number =       "6",
  pages =        "90--93",
  month =        jun,
  year =         "2007",
  CODEN =        "CPTRB4",
  DOI =          "https://doi.org/10.1109/MC.2007.196",
  ISSN =         "0018-9162 (print), 1558-0814 (electronic)",
  ISSN-L =       "0018-9162",
  bibdate =      "Fri Jun 29 14:19:11 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2",
  keywords =     "complete arithmetic; interval arithmetic",
}


bibtype: article
filename: fparith.bib
label: Homann:2007:IFPa
author: Holger Homann and Jurgen Dreher and Rainer Grauer
journal: arXiv.org
pages: ??--??
day: 22
month: may
monthnumber: 5
year: 2007
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
note: Published in cite Homann:2007:IFPb.
URL: http://arxiv.org/abs/0705.3144
subject: Computational Physics (physics.comp-ph); Fluid Dynamics (physics.flu-dyn)
acknowledgement: ack-nhfb
rawauthor: Holger Homann and J{\"u}rgen Dreher and Rainer Grauer
rawnote: Published in \cite{Homann:2007:IFPb}.
title:
Impact of the floating-point precision and interpolation scheme on the results of DNS of turbulence by pseudo-spectral codes

abstract:
In this paper we investigate the impact of the floating-point precision and interpolation scheme on the results of direct numerical simulations (DNS) of turbulence by pseudo-spectral codes. Three different types of floating-point precision configurations show no differences in the statistical results. This implies that single precision computations allow for increased Reynolds numbers due to the reduced amount of memory needed. The interpolation scheme for obtaining velocity values at particle positions has a noticeable impact on the Lagrangian acceleration statistics. A tri-cubic scheme results in a slightly broader acceleration probability density function than a tri-linear scheme. Furthermore the scaling behavior obtained by the cubic interpolation scheme exhibits a tendency towards a slightly increased degree of intermittency compared to the linear one.

rawabstract:
In this paper we investigate the impact of the floating-point precision and interpolation scheme on the results of direct numerical simulations (DNS) of turbulence by pseudo-spectral codes. Three different types of floating-point precision configurations show no differences in the statistical results. This implies that single precision computations allow for increased Reynolds numbers due to the reduced amount of memory needed. The interpolation scheme for obtaining velocity values at particle positions has a noticeable impact on the Lagrangian acceleration statistics. A tri-cubic scheme results in a slightly broader acceleration probability density function than a tri-linear scheme. Furthermore the scaling behavior obtained by the cubic interpolation scheme exhibits a tendency towards a slightly increased degree of intermittency compared to the linear one.

rawtitle:
Impact of the floating-point precision and interpolation scheme on the results of {DNS} of turbulence by pseudo-spectral codes

entry:
@Article{Homann:2007:IFPa,
  author =       "Holger Homann and J{\"u}rgen Dreher and Rainer
                 Grauer",
  title =        "Impact of the floating-point precision and
                 interpolation scheme on the results of {DNS} of
                 turbulence by pseudo-spectral codes",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "22",
  month =        may,
  year =         "2007",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Published in \cite{Homann:2007:IFPb}.",
  URL =          "http://arxiv.org/abs/0705.3144",
  abstract =     "In this paper we investigate the impact of the
                 floating-point precision and interpolation scheme on
                 the results of direct numerical simulations (DNS) of
                 turbulence by pseudo-spectral codes. Three different
                 types of floating-point precision configurations show
                 no differences in the statistical results. This implies
                 that single precision computations allow for increased
                 Reynolds numbers due to the reduced amount of memory
                 needed. The interpolation scheme for obtaining velocity
                 values at particle positions has a noticeable impact on
                 the Lagrangian acceleration statistics. A tri-cubic
                 scheme results in a slightly broader acceleration
                 probability density function than a tri-linear scheme.
                 Furthermore the scaling behavior obtained by the cubic
                 interpolation scheme exhibits a tendency towards a
                 slightly increased degree of intermittency compared to
                 the linear one.",
  acknowledgement = ack-nhfb,
  subject =      "Computational Physics (physics.comp-ph); Fluid
                 Dynamics (physics.flu-dyn)",
}


bibtype: article
filename: fparith.bib
label: Homann:2007:IFPb
author: Holger Homann and Jurgen Dreher and Rainer Grauer
journal: j-COMP-PHYS-COMM
volume: 177
number: 7
pages: 560--565
day: 1
month: oct
monthnumber: 10
year: 2007
CODEN: CPHCBZ
DOI: https://doi.org/10.1016/j.cpc.2007.05.019
ISSN: 0010-4655 (print), 1879-2944 (electronic) OR 00104655 (print), 18792944 (electronic)
ISSNL: 0010-4655 OR 00104655
bibdate: Mon Feb 13 23:42:25 MST 2012
bibtimestamp: 2012.02.13 23:42:25 MST
URL: http://www.sciencedirect.com/science/article/pii/S0010465507002998
fjournal: Computer Physics Communications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00104655
rawauthor: Holger Homann and J{\"u}rgen Dreher and Rainer Grauer
title:
Impact of the floating-point precision and interpolation scheme on the results of DNS of turbulence by pseudo-spectral codes

bibsource:
https://www.math.utah.edu/pub/tex/bib/compphyscomm2000.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

rawtitle:
Impact of the floating-point precision and interpolation scheme on the results of {DNS} of turbulence by pseudo-spectral codes

entry:
@Article{Homann:2007:IFPb,
  author =       "Holger Homann and J{\"u}rgen Dreher and Rainer
                 Grauer",
  title =        "Impact of the floating-point precision and
                 interpolation scheme on the results of {DNS} of
                 turbulence by pseudo-spectral codes",
  journal =      j-COMP-PHYS-COMM,
  volume =       "177",
  number =       "7",
  pages =        "560--565",
  day =          "1",
  month =        oct,
  year =         "2007",
  CODEN =        "CPHCBZ",
  DOI =          "https://doi.org/10.1016/j.cpc.2007.05.019",
  ISSN =         "0010-4655 (print), 1879-2944 (electronic)",
  ISSN-L =       "0010-4655",
  bibdate =      "Mon Feb 13 23:42:25 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compphyscomm2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0010465507002998",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Physics Communications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00104655",
}


bibtype: article
filename: fparith.bib
label: Hosangadi:2007:AMO
author: Anup Hosangadi and Farzan Fallah and Ryan Kastner
title: Algebraic Methods for Optimizing Constant Multiplications in Linear Systems
journal: j-J-VLSI-SIGNAL-PROC
volume: 49
number: 1
pages: 31--50
month: oct
monthnumber: 10
year: 2007
CODEN: JVSPED
DOI: https://doi.org/10.1007/s11265-007-0137-7
ISSN: 0922-5773 (print), 1573-109x (electronic) OR 09225773 (print), 1573109x (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Mon Nov 05 19:29:43 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.05 19:29:43 ???
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
rawauthor: Anup Hosangadi and Farzan Fallah and Ryan Kastner
rawtitle: Algebraic Methods for Optimizing Constant Multiplications in Linear Systems
abstract:
Constant multiplications can be efficiently implemented in hardware by converting them into a sequence of nested additions and shift operations. They can be optimized further by finding common subexpressions among these operations. In this work, we present algebraic methods for eliminating common subexpressions. Algebraic techniques are established in multi-level logic synthesis for the minimization of the number of literals and hence gates to implement Boolean logic. In this work we use the concepts of two of these methods, namely rectangle covering and fast extract (FX) and adapt them to the problem of optimizing linear arithmetic expressions. The main advantage of using such methods is that we can optimize systems consisting of multiple variables, which is not possible using the conventional optimization techniques. Our optimizations are aimed at reducing the area and power consumption of the hardware, and experimental results show up to 30.3% improvement in the number of operations over conventional techniques. Synthesis and simulation results show up to 30% area reduction and up to 27% power reduction. We also modified our algorithm to perform delay aware optimization, where we perform common subexpression elimination such that the delay is not exceeded beyond a particular value.

rawabstract:
Constant multiplications can be efficiently implemented in hardware by converting them into a sequence of nested additions and shift operations. They can be optimized further by finding common subexpressions among these operations. In this work, we present algebraic methods for eliminating common subexpressions. Algebraic techniques are established in multi-level logic synthesis for the minimization of the number of literals and hence gates to implement Boolean logic. In this work we use the concepts of two of these methods, namely rectangle covering and fast extract (FX) and adapt them to the problem of optimizing linear arithmetic expressions. The main advantage of using such methods is that we can optimize systems consisting of multiple variables, which is not possible using the conventional optimization techniques. Our optimizations are aimed at reducing the area and power consumption of the hardware, and experimental results show up to 30.3\% improvement in the number of operations over conventional techniques. Synthesis and simulation results show up to 30\% area reduction and up to 27\% power reduction. We also modified our algorithm to perform delay aware optimization, where we perform common subexpression elimination such that the delay is not exceeded beyond a particular value.

entry:
@Article{Hosangadi:2007:AMO,
  author =       "Anup Hosangadi and Farzan Fallah and Ryan Kastner",
  title =        "Algebraic Methods for Optimizing Constant
                 Multiplications in Linear Systems",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "49",
  number =       "1",
  pages =        "31--50",
  month =        oct,
  year =         "2007",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1007/s11265-007-0137-7",
  ISSN =         "0922-5773 (print), 1573-109x (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Mon Nov 05 19:29:43 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Constant multiplications can be efficiently
                 implemented in hardware by converting them into a
                 sequence of nested additions and shift operations. They
                 can be optimized further by finding common
                 subexpressions among these operations. In this work, we
                 present algebraic methods for eliminating common
                 subexpressions. Algebraic techniques are established in
                 multi-level logic synthesis for the minimization of the
                 number of literals and hence gates to implement Boolean
                 logic. In this work we use the concepts of two of these
                 methods, namely rectangle covering and fast extract
                 (FX) and adapt them to the problem of optimizing linear
                 arithmetic expressions. The main advantage of using
                 such methods is that we can optimize systems consisting
                 of multiple variables, which is not possible using the
                 conventional optimization techniques. Our optimizations
                 are aimed at reducing the area and power consumption of
                 the hardware, and experimental results show up to
                 30.3\% improvement in the number of operations over
                 conventional techniques. Synthesis and simulation
                 results show up to 30\% area reduction and up to 27\%
                 power reduction. We also modified our algorithm to
                 perform delay aware optimization, where we perform
                 common subexpression elimination such that the delay is
                 not exceeded beyond a particular value.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of VLSI Signal Processing",
}


bibtype: inproceedings
filename: fparith.bib
label: Hosseinzadeh:2007:NMS
author: M. Hosseinzadeh and K. Navi and S. Gorgin
booktitle: ICEE '07, International Conference on Electrical Engineering, 11--12 April 2007
title: A New Moduli Set for Residue Number System: $ r^n - 2, r^n - 1, r^n $
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--6
year: 2007
DOI: https://doi.org/10.1109/ICEE.2007.4287306
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawauthor: M. Hosseinzadeh and K. Navi and S. Gorgin
rawbooktitle: {ICEE '07}, International Conference on Electrical Engineering, 11--12 April 2007
rawtitle: A New Moduli Set for Residue Number System: $ \{ r^n - 2, r^n - 1, r^n \} $
entry:
@InProceedings{Hosseinzadeh:2007:NMS,
  author =       "M. Hosseinzadeh and K. Navi and S. Gorgin",
  booktitle =    "{ICEE '07}, International Conference on Electrical
                 Engineering, 11--12 April 2007",
  title =        "A New Moduli Set for Residue Number System: $ \{ r^n -
                 2, r^n - 1, r^n \} $",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--6",
  year =         "2007",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/ICEE.2007.4287306",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "In this paper a new moduli set is for Residue Number
                 System: introduced where $r = 2k + 1$ and $k = 1, 2, 3,
                 \ldots{}$. This moduli set includes pair wise
                 relatively prime moduli, so it offers the maximum
                 possible dynamic range. For this moduli set, the
                 related circuits are simply realizable in the Multiple
                 Valued Logic (MVL) and arithmetic in this moduli set
                 enjoys very high speed operations and simple
                 reverse\slash forward conversion (RNS to MVL\slash MVL
                 to RNS).\par

                 After introducing the new moduli set, we design its
                 related circuits and converters. Finally, we compare
                 the results of those of similar moduli sets and show
                 that our moduli set significantly improves the time
                 complexity while offering greater dynamic range.",
}


bibtype: inproceedings
filename: fparith.bib
label: Huang:2007:NAM
author: Libo Huang and Li Shen and Kui Dai and Zhiying Wang
title: A New Architecture for Multiple-Precision Floating-Point Multiply-Add Fused Unit Design
crossref: Kornerup:2007:PIS
pages: 69--76
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.5
bibdate: Tue Oct 9 16:32:41 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 16:32:41 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Libo Huang and Li Shen and Kui Dai and Zhiying Wang
rawtitle: A New Architecture for Multiple-Precision Floating-Point Multiply-Add Fused Unit Design
abstract:
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floating-point performance in scientific and multimedia applications. This paper proposes a new architecture for the MAF unit that supports multiple IEEE precisions multiply-add operation (A*B+C) with Single Instruction Multiple Data (SIMD) feature. The proposed MAF unit can perform either one double-precision or two parallel single-precision operations using about 18% more hardware than a conventional double-precision MAF unit and with 9% increase in delay. To accommodate the simultaneous computation of two single-precision MAF operations, several basic modules of double-precision MAF unit are redesigned. They are either segmented by precision mode dependent multiplexers or attached by the duplicated hardware. The proposed MAF unit can be fully pipelined and the experimental results show that it is suitable for processors with floating-point unit (FPU).

rawabstract:
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floating-point performance in scientific and multimedia applications. This paper proposes a new architecture for the MAF unit that supports multiple IEEE precisions multiply-add operation (A*B+C) with Single Instruction Multiple Data (SIMD) feature. The proposed MAF unit can perform either one double-precision or two parallel single-precision operations using about 18\% more hardware than a conventional double-precision MAF unit and with 9\% increase in delay. To accommodate the simultaneous computation of two single-precision MAF operations, several basic modules of double-precision MAF unit are redesigned. They are either segmented by precision mode dependent multiplexers or attached by the duplicated hardware. The proposed MAF unit can be fully pipelined and the experimental results show that it is suitable for processors with floating-point unit (FPU).

entry:
@InProceedings{Huang:2007:NAM,
  author =       "Libo Huang and Li Shen and Kui Dai and Zhiying Wang",
  title =        "A New Architecture for Multiple-Precision
                 Floating-Point Multiply-Add Fused Unit Design",
  crossref =     "Kornerup:2007:PIS",
  pages =        "69--76",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.5",
  bibdate =      "Tue Oct 9 16:32:41 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The floating-point multiply-add fused (MAF) unit sets
                 a new trend in the processor design to speed up
                 floating-point performance in scientific and multimedia
                 applications. This paper proposes a new architecture
                 for the MAF unit that supports multiple IEEE precisions
                 multiply-add operation (A*B+C) with Single Instruction
                 Multiple Data (SIMD) feature. The proposed MAF unit can
                 perform either one double-precision or two parallel
                 single-precision operations using about 18\% more
                 hardware than a conventional double-precision MAF unit
                 and with 9\% increase in delay. To accommodate the
                 simultaneous computation of two single-precision MAF
                 operations, several basic modules of double-precision
                 MAF unit are redesigned. They are either segmented by
                 precision mode dependent multiplexers or attached by
                 the duplicated hardware. The proposed MAF unit can be
                 fully pipelined and the experimental results show that
                 it is suitable for processors with floating-point unit
                 (FPU).",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: inproceedings
filename: fparith.bib
label: Iguchi:2007:DRC
author: Yukihiro Iguchi and Tsutomu Sasao and Munehiro Matsuura
title: On Designs of Radix Converters Using Arithmetic Decompositions---Binary to Decimal Converters---
crossref: IEEE:2007:IPI
pages: 32--32
year: 2007
DOI: https://doi.org/10.1109/ISMVL.2007.39
bibdate: Thu Aug 07 17:34:11 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 17:34:11 ???
keywords: decimal floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Yukihiro Iguchi and Tsutomu Sasao and Munehiro Matsuura
rawtitle: On Designs of Radix Converters Using Arithmetic Decompositions---Binary to Decimal Converters---
abstract:
In digital signal processing, radixes other than two are often used for high-speed computation. In the computation for finance, decimal numbers are used instead of binary numbers. In such cases, radix converters are necessary. This paper considers design methods for binary to $q$-nary converters. It introduces a new design technique based on weighted-sum (WS) functions. The method computes a WS function for each digit by an LUT cascade and a binary adder, then adds adjacent digits with $q$-nary adders. A 16-bit binary to decimal converter is designed to show the method.

rawabstract:
In digital signal processing, radixes other than two are often used for high-speed computation. In the computation for finance, decimal numbers are used instead of binary numbers. In such cases, radix converters are necessary. This paper considers design methods for binary to $q$-nary converters. It introduces a new design technique based on weighted-sum (WS) functions. The method computes a WS function for each digit by an LUT cascade and a binary adder, then adds adjacent digits with $q$-nary adders. A 16-bit binary to decimal converter is designed to show the method.

entry:
@InProceedings{Iguchi:2007:DRC,
  author =       "Yukihiro Iguchi and Tsutomu Sasao and Munehiro
                 Matsuura",
  title =        "On Designs of Radix Converters Using Arithmetic
                 Decompositions---Binary to Decimal Converters---",
  crossref =     "IEEE:2007:IPI",
  pages =        "32--32",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ISMVL.2007.39",
  bibdate =      "Thu Aug 07 17:34:11 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In digital signal processing, radixes other than two
                 are often used for high-speed computation. In the
                 computation for finance, decimal numbers are used
                 instead of binary numbers. In such cases, radix
                 converters are necessary. This paper considers design
                 methods for binary to $q$-nary converters. It
                 introduces a new design technique based on weighted-sum
                 (WS) functions. The method computes a WS function for
                 each digit by an LUT cascade and a binary adder, then
                 adds adjacent digits with $q$-nary adders. A 16-bit
                 binary to decimal converter is designed to show the
                 method.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal floating-point arithmetic",
}


bibtype: article
filename: fparith.bib
label: Ihsberner:2007:REA
author: Katja Ihsberner
title: Roundoff error analysis of fast DCT algorithms in fixed point arithmetic
journal: j-NUMER-ALGORITHMS
volume: 46
number: 1
pages: 1--22
month: sep
monthnumber: 9
year: 2007
CODEN: NUALEG
DOI: https://doi.org/10.1007/s11075-007-9123-1
ISSN: 1017-1398 (print), 1572-9265 (electronic) OR 10171398 (print), 15729265 (electronic)
ISSNL: 1017-1398 OR 10171398
MRclass: subject classification (2000); 65T50; 65G50
bibdate: Tue Jul 8 19:14:29 MDT 2008
bibtimestamp: 2008.07.08 19:14:29 MDT
URL: http://www.springerlink.com/openurl.asp?genre=article&issn=1017-1398&volume=46&issue=1&spage=1
fjournal: Numerical Algorithms
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11075
rawauthor: Katja Ihsberner
rawtitle: Roundoff error analysis of fast {DCT} algorithms in fixed point arithmetic
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=1017-1398&volume=46&issue=1; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
Discrete cosine transform; Factorization of cosine matrix; Fast cosine transform; Fixed point arithmetic; Numerical stability; Roundoff error

entry:
@Article{Ihsberner:2007:REA,
  author =       "Katja Ihsberner",
  title =        "Roundoff error analysis of fast {DCT} algorithms in
                 fixed point arithmetic",
  journal =      j-NUMER-ALGORITHMS,
  volume =       "46",
  number =       "1",
  pages =        "1--22",
  month =        sep,
  year =         "2007",
  CODEN =        "NUALEG",
  DOI =          "https://doi.org/10.1007/s11075-007-9123-1",
  ISSN =         "1017-1398 (print), 1572-9265 (electronic)",
  ISSN-L =       "1017-1398",
  MRclass =      "subject classification (2000); 65T50; 65G50",
  bibdate =      "Tue Jul 8 19:14:29 MDT 2008",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=1017-1398&volume=46&issue=1;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.springerlink.com/openurl.asp?genre=article&issn=1017-1398&volume=46&issue=1&spage=1",
  acknowledgement = ack-nhfb,
  fjournal =     "Numerical Algorithms",
  journal-URL =  "http://link.springer.com/journal/11075",
  keywords =     "Discrete cosine transform; Factorization of cosine
                 matrix; Fast cosine transform; Fixed point arithmetic;
                 Numerical stability; Roundoff error",
}


bibtype: inproceedings
filename: fparith.bib
label: James:2007:QAD
author: Rekha K. James and Shahana T. K. and K. Poulose Jacob and Sreela Sasi
title: Quick Addition of Decimals Using Reversible Conservative Logic
crossref: IEEE:2007:API
pages: 191--195
year: 2007
DOI: https://doi.org/10.1109/ADCOM.2007.108
bibdate: Thu Aug 07 18:33:41 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 18:33:41 ???
keywords: decimal arithmetic; delay reduction; fault detection; reversible logic
acknowledgement: ack-nhfb
rawauthor: Rekha K. James and Shahana T. K. and K. Poulose Jacob and Sreela Sasi
rawtitle: Quick Addition of Decimals Using Reversible Conservative Logic
abstract:
In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

rawabstract:
In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

entry:
@InProceedings{James:2007:QAD,
  author =       "Rekha K. James and Shahana T. K. and K. Poulose Jacob
                 and Sreela Sasi",
  title =        "Quick Addition of Decimals Using Reversible
                 Conservative Logic",
  crossref =     "IEEE:2007:API",
  pages =        "191--195",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ADCOM.2007.108",
  bibdate =      "Thu Aug 07 18:33:41 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In recent years, reversible logic has emerged as one
                 of the most important approaches for power optimization
                 with its application in low power CMOS, nanotechnology
                 and quantum computing. This research proposes quick
                 addition of decimals (QAD) suitable for multi-digit BCD
                 addition, using reversible conservative logic. The
                 design makes use of reversible fault tolerant Fredkin
                 gates only. The implementation strategy is to reduce
                 the number of levels of delay there by increasing the
                 speed, which is the most important factor for high
                 speed circuits.",
  acknowledgement = ack-nhfb,
  keywords =     "decimal arithmetic; delay reduction; fault detection;
                 reversible logic",
}


bibtype: inproceedings
filename: fparith.bib
label: Kapre:2007:OPF
author: Nachiket Kapre and Andre DeHon
title: Optimistic Parallelization of Floating-Point Accumulation
crossref: Kornerup:2007:PIS
pages: 205--216
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.25
bibdate: Tue Oct 9 17:16:03 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 17:16:03 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Nachiket Kapre and Andre DeHon
rawtitle: Optimistic Parallelization of Floating-Point Accumulation
abstract:
Floating-point arithmetic is notoriously nonassociative due to the limited precision representation which demands intermediate values be rounded to fit in the available precision. The resulting cyclic dependency in floating-point accumulation inhibits parallelization of the computation, including efficient use of pipelining. In practice, however, we observe that floating-point operations are ``mostly'' associative. This observation can be exploited to parallelize floating-point accumulation using a form of optimistic concurrency. In this scheme, we first compute an optimistic associative approximation to the sum and then relax the computation by iteratively propagating errors until the correct sum is obtained. We map this computation to a network of 16 statically-scheduled, pipelined, double-precision floating-point adders on the Virtex-4 LX160 (-12) device where each floating-point adder runs at 296MHz and has a pipeline depth of 10. On this 16 PE design, we demonstrate an average speedup of 6AA -- with randomly generated data and 3-7AA --- with summations extracted from Conjugate Gradient benchmarks.

rawabstract:
Floating-point arithmetic is notoriously nonassociative due to the limited precision representation which demands intermediate values be rounded to fit in the available precision. The resulting cyclic dependency in floating-point accumulation inhibits parallelization of the computation, including efficient use of pipelining. In practice, however, we observe that floating-point operations are ``mostly'' associative. This observation can be exploited to parallelize floating-point accumulation using a form of optimistic concurrency. In this scheme, we first compute an optimistic associative approximation to the sum and then relax the computation by iteratively propagating errors until the correct sum is obtained. We map this computation to a network of 16 statically-scheduled, pipelined, double-precision floating-point adders on the Virtex-4 LX160 (-12) device where each floating-point adder runs at 296MHz and has a pipeline depth of 10. On this 16 PE design, we demonstrate an average speedup of 6{\AA} -- with randomly generated data and 3-7{\AA} --- with summations extracted from Conjugate Gradient benchmarks.

entry:
@InProceedings{Kapre:2007:OPF,
  author =       "Nachiket Kapre and Andre DeHon",
  title =        "Optimistic Parallelization of Floating-Point
                 Accumulation",
  crossref =     "Kornerup:2007:PIS",
  pages =        "205--216",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.25",
  bibdate =      "Tue Oct 9 17:16:03 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Floating-point arithmetic is notoriously
                 nonassociative due to the limited precision
                 representation which demands intermediate values be
                 rounded to fit in the available precision. The
                 resulting cyclic dependency in floating-point
                 accumulation inhibits parallelization of the
                 computation, including efficient use of pipelining. In
                 practice, however, we observe that floating-point
                 operations are ``mostly'' associative. This observation
                 can be exploited to parallelize floating-point
                 accumulation using a form of optimistic concurrency. In
                 this scheme, we first compute an optimistic associative
                 approximation to the sum and then relax the computation
                 by iteratively propagating errors until the correct sum
                 is obtained. We map this computation to a network of 16
                 statically-scheduled, pipelined, double-precision
                 floating-point adders on the Virtex-4 LX160 (-12)
                 device where each floating-point adder runs at 296MHz
                 and has a pipeline depth of 10. On this 16 PE design,
                 we demonstrate an average speedup of 6{\AA} -- with
                 randomly generated data and 3-7{\AA} --- with
                 summations extracted from Conjugate Gradient
                 benchmarks.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: article
filename: fparith.bib
label: Kechagias:2007:CME
author: P. S. Kechagias and Basil K. Papadopoulos
title: Computational method to evaluate fuzzy arithmetic operations
journal: j-APPL-MATH-COMP
volume: 185
number: 1
pages: 169--177
day: 1
month: feb
monthnumber: 2
year: 2007
CODEN: AMHCBQ
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Sat Jul 12 09:03:01 MDT 2008
bibtimestamp: 2008.07.12 09:03:01 MDT
fjournal: Applied Mathematics and Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003
rawauthor: P. S. Kechagias and Basil K. Papadopoulos
rawtitle: Computational method to evaluate fuzzy arithmetic operations
entry:
@Article{Kechagias:2007:CME,
  author =       "P. S. Kechagias and Basil K. Papadopoulos",
  title =        "Computational method to evaluate fuzzy arithmetic
                 operations",
  journal =      j-APPL-MATH-COMP,
  volume =       "185",
  number =       "1",
  pages =        "169--177",
  day =          "1",
  month =        feb,
  year =         "2007",
  CODEN =        "AMHCBQ",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Sat Jul 12 09:03:01 MDT 2008",
  bibsource =    "http://www.sciencedirect.com/science/journal/00963003;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003",
}


bibtype: article
filename: fparith.bib
label: Khabbazian:2007:DPC
author: M. Khabbazian and T. A. Gulliver and V. K. Bhargava
title: Double Point Compression with Applications to Speeding Up Random Point Multiplication
journal: j-IEEE-TRANS-COMPUT
volume: 56
number: 3
pages: 305--313
month: mar
monthnumber: 3
year: 2007
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.47
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:03:37 MDT 2011
bibtimestamp: 2011.07.04 15:03:37 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4079514
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: M. Khabbazian and T. A. Gulliver and V. K. Bhargava
rawtitle: Double Point Compression with Applications to Speeding Up Random Point Multiplication
entry:
@Article{Khabbazian:2007:DPC,
  author =       "M. Khabbazian and T. A. Gulliver and V. K. Bhargava",
  title =        "Double Point Compression with Applications to Speeding
                 Up Random Point Multiplication",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "56",
  number =       "3",
  pages =        "305--313",
  month =        mar,
  year =         "2007",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.47",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:03:37 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4079514",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Knowles:2007:RSE
author: Simon Knowles
title: The Return of Silicon Efficiency
crossref: Kornerup:2007:PIS
pages: 3--3
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.36
bibdate: Tue Oct 9 16:32:41 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 16:32:41 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Simon Knowles
rawtitle: The Return of Silicon Efficiency
abstract:
The economic and physical forces which have always shaped the business of digital chip design are again evolving to change the priorities of designers. Key physical trends include the end of gate oxide thickness scaling, and the effect of small dopant populations on threshold voltage variance. Key economic trends include the need to tolerate specification shift and design error, and the need to amortise chip development cost over multiple market sockets.

rawabstract:
The economic and physical forces which have always shaped the business of digital chip design are again evolving to change the priorities of designers. Key physical trends include the end of gate oxide thickness scaling, and the effect of small dopant populations on threshold voltage variance. Key economic trends include the need to tolerate specification shift and design error, and the need to amortise chip development cost over multiple market sockets.

entry:
@InProceedings{Knowles:2007:RSE,
  author =       "Simon Knowles",
  title =        "The Return of Silicon Efficiency",
  crossref =     "Kornerup:2007:PIS",
  pages =        "3--3",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.36",
  bibdate =      "Tue Oct 9 16:32:41 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The economic and physical forces which have always
                 shaped the business of digital chip design are again
                 evolving to change the priorities of designers. Key
                 physical trends include the end of gate oxide thickness
                 scaling, and the effect of small dopant populations on
                 threshold voltage variance. Key economic trends include
                 the need to tolerate specification shift and design
                 error, and the need to amortise chip development cost
                 over multiple market sockets.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: inproceedings
filename: fparith.bib
label: Kobayashi:2007:AIG
author: Katsuki Kobayashi and Naofumi Takagi and Kazuyoshi Takagi
crossref: Kornerup:2007:PIS
pages: 105--112
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.9
bibdate: Tue Oct 9 16:32:41 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 16:32:41 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Katsuki Kobayashi and Naofumi Takagi and Kazuyoshi Takagi
title:
An Algorithm for Inversion in $ mathrm GF(2^m) $ Suitable for Implementation Using a Polynomial Multiply Instruction on $ mathrm GF(2) $

abstract:
An algorithm for inversion in $ mathrm GF(2^m) $ suitable for implementation using a polynomial multiply instruction on $ mathrm GF(2) $ is proposed. It is based on the extended Euclid's algorithm. In the algorithm, operations corresponding to several contiguous iterations of the VLSI algorithm proposed by Brunner et al. is represented as a matrix. They are calculated at once through the matrix efficiently by means of a polynomial multiply instruction on $ mathrm GF(2) $. For example, in the case where the word size of a processor and $m$ are $ 32 $ and $ 571 $, respectively, the algorithm calculates inversion with about the half number of instructions of the conventional algorithm on the average.

rawabstract:
An algorithm for inversion in $ \mathrm {GF}(2^m) $ suitable for implementation using a polynomial multiply instruction on $ \mathrm {GF}(2) $ is proposed. It is based on the extended Euclid's algorithm. In the algorithm, operations corresponding to several contiguous iterations of the VLSI algorithm proposed by Brunner et al. is represented as a matrix. They are calculated at once through the matrix efficiently by means of a polynomial multiply instruction on $ \mathrm {GF}(2) $. For example, in the case where the word size of a processor and $m$ are $ 32 $ and $ 571 $, respectively, the algorithm calculates inversion with about the half number of instructions of the conventional algorithm on the average.

rawtitle:
An Algorithm for Inversion in {$ \mathrm {GF}(2^m) $} Suitable for Implementation Using a Polynomial Multiply Instruction on {$ \mathrm {GF}(2) $}

entry:
@InProceedings{Kobayashi:2007:AIG,
  author =       "Katsuki Kobayashi and Naofumi Takagi and Kazuyoshi
                 Takagi",
  title =        "An Algorithm for Inversion in {$ \mathrm {GF}(2^m) $}
                 Suitable for Implementation Using a Polynomial Multiply
                 Instruction on {$ \mathrm {GF}(2) $}",
  crossref =     "Kornerup:2007:PIS",
  pages =        "105--112",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.9",
  bibdate =      "Tue Oct 9 16:32:41 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "An algorithm for inversion in $ \mathrm {GF}(2^m) $
                 suitable for implementation using a polynomial multiply
                 instruction on $ \mathrm {GF}(2) $ is proposed. It is
                 based on the extended Euclid's algorithm. In the
                 algorithm, operations corresponding to several
                 contiguous iterations of the VLSI algorithm proposed by
                 Brunner et al. is represented as a matrix. They are
                 calculated at once through the matrix efficiently by
                 means of a polynomial multiply instruction on $ \mathrm
                 {GF}(2) $. For example, in the case where the word size
                 of a processor and $m$ are $ 32 $ and $ 571 $,
                 respectively, the algorithm calculates inversion with
                 about the half number of instructions of the
                 conventional algorithm on the average.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: article
filename: fparith.bib
label: Kornerup:2007:CIPa
author: Peter Kornerup and Vincent Lefevre and Jean-Michel Muller
title: Computing Integer Powers in Floating-Point Arithmetic
journal: arXiv.org
pages: ??--??
day: 30
month: may
monthnumber: 5
year: 2007
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
note: Published in cite Kornerup:2007:CIPb.
URL: http://arxiv.org/abs/0705.4369
keywords: correct rounding; floating-point arithmetic
subject: Numerical Analysis (cs.NA); Mathematical Software (cs.MS)
acknowledgement: ack-nhfb
rawauthor: Peter Kornerup and Vincent Lef{\`e}vre and Jean-Michel Muller
rawnote: Published in \cite{Kornerup:2007:CIPb}.
rawtitle: Computing Integer Powers in Floating-Point Arithmetic
abstract:
We introduce two algorithms for accurately evaluating powers to a positive integer in floating-point arithmetic, assuming a fused multiply-add (fma) instruction is available. We show that our log-time algorithm always produce faithfully-rounded results, discuss the possibility of getting correctly rounded results, and show that results correctly rounded in double precision can be obtained if extended-precision is available with the possibility to round into double precision (with a single rounding).

rawabstract:
We introduce two algorithms for accurately evaluating powers to a positive integer in floating-point arithmetic, assuming a fused multiply-add (fma) instruction is available. We show that our log-time algorithm always produce faithfully-rounded results, discuss the possibility of getting correctly rounded results, and show that results correctly rounded in double precision can be obtained if extended-precision is available with the possibility to round into double precision (with a single rounding).

entry:
@Article{Kornerup:2007:CIPa,
  author =       "Peter Kornerup and Vincent Lef{\`e}vre and Jean-Michel
                 Muller",
  title =        "Computing Integer Powers in Floating-Point
                 Arithmetic",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "30",
  month =        may,
  year =         "2007",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Published in \cite{Kornerup:2007:CIPb}.",
  URL =          "http://arxiv.org/abs/0705.4369",
  abstract =     "We introduce two algorithms for accurately evaluating
                 powers to a positive integer in floating-point
                 arithmetic, assuming a fused multiply-add (fma)
                 instruction is available. We show that our log-time
                 algorithm always produce faithfully-rounded results,
                 discuss the possibility of getting correctly rounded
                 results, and show that results correctly rounded in
                 double precision can be obtained if extended-precision
                 is available with the possibility to round into double
                 precision (with a single rounding).",
  acknowledgement = ack-nhfb,
  keywords =     "correct rounding; floating-point arithmetic",
  subject =      "Numerical Analysis (cs.NA); Mathematical Software
                 (cs.MS)",
}


bibtype: inproceedings
filename: fparith.bib
label: Kornerup:2007:CIPb
author: Peter Kornerup and Vincent Lefevre and Jean-Michel Muller
editor: Michael B. Matthews
title: Computing Integer Powers in Floating-Point Arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 343--347
year: 2007
DOI: https://doi.org/10.1109/ACSSC.2007.4487226
ISBN: 1-4244-2110-1 OR 1424421101
ISBN13: 978-1-4244-2110-7 OR 9781424421107
ISSN: 1058-6393 OR 10586393
ISSNL: 1058-6393 OR 10586393
bibdate: Fri Sep 29 10:55:50 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 10:55:50 ???
acknowledgement: ack-nhfb
rawauthor: Peter Kornerup and Vincent Lefevre and Jean-Michel Muller
raweditor: Michael B. Matthews
rawtitle: Computing Integer Powers in Floating-Point Arithmetic
booktitle:
2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers, November 4--7, 2007. Pacific Grove, California

abstract:
We introduce two algorithms for accurately evaluating powers to a positive integer in floating-point arithmetic, assuming a fused multiply-add (fma) instruction is available. We show that our log-time algorithm always produce faithfully-rounded results, discuss the possibility of getting correctly rounded results, and show that results correctly rounded in double precision can be obtained if extended precision is available with the possibility to round into double precision (with a single rounding).

rawabstract:
We introduce two algorithms for accurately evaluating powers to a positive integer in floating-point arithmetic, assuming a fused multiply-add (fma) instruction is available. We show that our log-time algorithm always produce faithfully-rounded results, discuss the possibility of getting correctly rounded results, and show that results correctly rounded in double precision can be obtained if extended precision is available with the possibility to round into double precision (with a single rounding).

rawbooktitle:
{2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers, November 4--7, 2007. Pacific Grove, California}

entry:
@InProceedings{Kornerup:2007:CIPb,
  author =       "Peter Kornerup and Vincent Lefevre and Jean-Michel
                 Muller",
  editor =       "Michael B. Matthews",
  booktitle =    "{2007 Conference Record of the Forty-First Asilomar
                 Conference on Signals, Systems and Computers, November
                 4--7, 2007. Pacific Grove, California}",
  title =        "Computing Integer Powers in Floating-Point
                 Arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "343--347",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ACSSC.2007.4487226",
  ISBN =         "1-4244-2110-1",
  ISBN-13 =      "978-1-4244-2110-7",
  ISSN =         "1058-6393",
  ISSN-L =       "1058-6393",
  bibdate =      "Fri Sep 29 10:55:50 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We introduce two algorithms for accurately evaluating
                 powers to a positive integer in floating-point
                 arithmetic, assuming a fused multiply-add (fma)
                 instruction is available. We show that our log-time
                 algorithm always produce faithfully-rounded results,
                 discuss the possibility of getting correctly rounded
                 results, and show that results correctly rounded in
                 double precision can be obtained if extended precision
                 is available with the possibility to round into double
                 precision (with a single rounding).",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Kuliamin:2007:STI
author: V. V. Kuliamin
title: Standardization and testing of implementations of mathematical functions in floating point numbers
journal: j-PROG-COMP-SOFT
volume: 33
number: 3
pages: 154--173
year: 2007
CODEN: PCSODA
DOI: https://doi.org/10.1134/S036176880703005X
ISSN: 0361-7688 (print), 1608-3261 (electronic) OR 03617688 (print), 16083261 (electronic)
ISSNL: 0361-7688 OR 03617688
bibdate: Fri Aug 08 09:01:30 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.08 09:01:30 ???
fjournal: Programming and Computer Software; translation of Programmirovaniye (Moscow, USSR) Plenum
keywords: floating-point function testing and verification
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11086
rawauthor: V. V. Kuliamin
rawtitle: Standardization and testing of implementations of mathematical functions in floating point numbers
abstract:
Requirements definition and test suites development for implementations of mathematical functions in floating point arithmetic in the framework of the IEEE 754 standard are considered. A method based on this standard is proposed for defining requirements for such functions. This method can be used for the standardization of implementations of such functions; this kind of standardization extends IEEE 754. A method for designing test suites for the verification of those requirements is presented. The proposed methods are based on specific properties of the representation of floating point numbers and on some features of the functions under examination.

rawabstract:
Requirements definition and test suites development for implementations of mathematical functions in floating point arithmetic in the framework of the IEEE 754 standard are considered. A method based on this standard is proposed for defining requirements for such functions. This method can be used for the standardization of implementations of such functions; this kind of standardization extends IEEE 754. A method for designing test suites for the verification of those requirements is presented. The proposed methods are based on specific properties of the representation of floating point numbers and on some features of the functions under examination.

entry:
@Article{Kuliamin:2007:STI,
  author =       "V. V. Kuliamin",
  title =        "Standardization and testing of implementations of
                 mathematical functions in floating point numbers",
  journal =      j-PROG-COMP-SOFT,
  volume =       "33",
  number =       "3",
  pages =        "154--173",
  year =         "2007",
  CODEN =        "PCSODA",
  DOI =          "https://doi.org/10.1134/S036176880703005X",
  ISSN =         "0361-7688 (print), 1608-3261 (electronic)",
  ISSN-L =       "0361-7688",
  bibdate =      "Fri Aug 08 09:01:30 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Requirements definition and test suites development
                 for implementations of mathematical functions in
                 floating point arithmetic in the framework of the IEEE
                 754 standard are considered. A method based on this
                 standard is proposed for defining requirements for such
                 functions. This method can be used for the
                 standardization of implementations of such functions;
                 this kind of standardization extends IEEE 754. A method
                 for designing test suites for the verification of those
                 requirements is presented. The proposed methods are
                 based on specific properties of the representation of
                 floating point numbers and on some features of the
                 functions under examination.",
  acknowledgement = ack-nhfb,
  fjournal =     "Programming and Computer Software; translation of
                 Programmirovaniye (Moscow, USSR) Plenum",
  journal-URL =  "http://link.springer.com/journal/11086",
  keywords =     "floating-point function testing and verification",
}


bibtype: article
filename: fparith.bib
label: Lambov:2007:REI
author: Branimir Lambov
title: RealLib: An efficient implementation of exact real arithmetic
journal: Mathematical Structures in Computer Science
volume: 17
number: 1
pages: 81--98
month: feb
monthnumber: 2
year: 2007
ISSN: 0960-1295 OR 09601295
bibdate: Thu Aug 07 19:25:30 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 19:25:30 ???
URL: http://www.brics.dk/~barnie/RealPractical.pdf
acknowledgement: ack-nhfb
rawauthor: Branimir Lambov
rawtitle: {RealLib}: An efficient implementation of exact real arithmetic
abstract:
This paper is an introduction to the RealLib package for exact real number computations. The library provides certified accuracy, but tries to achieve this at performance close to the performance of hardware floating point for problems that do not require higher precision. The paper gives the motivation and features of the design of the library and compares it with other packages for exact real arithmetic.

rawabstract:
This paper is an introduction to the RealLib package for exact real number computations. The library provides certified accuracy, but tries to achieve this at performance close to the performance of hardware floating point for problems that do not require higher precision. The paper gives the motivation and features of the design of the library and compares it with other packages for exact real arithmetic.

entry:
@Article{Lambov:2007:REI,
  author =       "Branimir Lambov",
  title =        "{RealLib}: An efficient implementation of exact real
                 arithmetic",
  journal =      "Mathematical Structures in Computer Science",
  volume =       "17",
  number =       "1",
  pages =        "81--98",
  month =        feb,
  year =         "2007",
  ISSN =         "0960-1295",
  bibdate =      "Thu Aug 07 19:25:30 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.brics.dk/~barnie/RealPractical.pdf",
  abstract =     "This paper is an introduction to the RealLib package
                 for exact real number computations. The library
                 provides certified accuracy, but tries to achieve this
                 at performance close to the performance of hardware
                 floating point for problems that do not require higher
                 precision. The paper gives the motivation and features
                 of the design of the library and compares it with other
                 packages for exact real arithmetic.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Lang:2007:RDR
author: Tomas Lang and Alberto Nannarelli
title: A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
journal: j-IEEE-TRANS-COMPUT
volume: 56
number: 6
pages: 727--739
month: jun
monthnumber: 6
year: 2007
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.1038
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:03:39 MDT 2011
bibtimestamp: 2011.07.04 15:03:39 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4167785
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Tomas Lang and Alberto Nannarelli
rawtitle: A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
abstract:
In this work, we present a radix-10 division unit that is based on the digit-recurrence algorithm. The previous decimal division designs do not include recent developments in the theory and practice of this type of algorithm, which were developed for radix-$ 2^k $ dividers. In addition to the adaptation of these features, the radix-10 quotient digit is decomposed into a radix-2 digit and a radix-5 digit in such a way that only five and two times the divisor are required in the recurrence. Moreover, the most significant slice of the recurrence, which includes the selection function, is implemented in radix-2, avoiding the additional delay introduced by the radix--10 carry-save additions and allowing the balancing of the paths to reduce the cycle delay. The results of the implementation of the proposed radix-10 division unit show that its latency is close to that of radix-16 division units (comparable dynamic range of significands) and it has a shorter latency than a radix-10 unit based on the Newton--Raphson approximation.

keywords:
algorithms and architectures for floating-point arithmetic; decimal arithmetic; decimal division; decimal floating-point arithmetic; digit-recurrence division

rawabstract:
In this work, we present a radix-10 division unit that is based on the digit-recurrence algorithm. The previous decimal division designs do not include recent developments in the theory and practice of this type of algorithm, which were developed for radix-$ 2^k $ dividers. In addition to the adaptation of these features, the radix-10 quotient digit is decomposed into a radix-2 digit and a radix-5 digit in such a way that only five and two times the divisor are required in the recurrence. Moreover, the most significant slice of the recurrence, which includes the selection function, is implemented in radix-2, avoiding the additional delay introduced by the radix--10 carry-save additions and allowing the balancing of the paths to reduce the cycle delay. The results of the implementation of the proposed radix-10 division unit show that its latency is close to that of radix-16 division units (comparable dynamic range of significands) and it has a shorter latency than a radix-10 unit based on the Newton--Raphson approximation.

entry:
@Article{Lang:2007:RDR,
  author =       "Tomas Lang and Alberto Nannarelli",
  title =        "A Radix-10 Digit-Recurrence Division Unit: Algorithm
                 and Architecture",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "56",
  number =       "6",
  pages =        "727--739",
  month =        jun,
  year =         "2007",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.1038",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:03:39 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4167785",
  abstract =     "In this work, we present a radix-10 division unit that
                 is based on the digit-recurrence algorithm. The
                 previous decimal division designs do not include recent
                 developments in the theory and practice of this type of
                 algorithm, which were developed for radix-$ 2^k $
                 dividers. In addition to the adaptation of these
                 features, the radix-10 quotient digit is decomposed
                 into a radix-2 digit and a radix-5 digit in such a way
                 that only five and two times the divisor are required
                 in the recurrence. Moreover, the most significant slice
                 of the recurrence, which includes the selection
                 function, is implemented in radix-2, avoiding the
                 additional delay introduced by the radix--10 carry-save
                 additions and allowing the balancing of the paths to
                 reduce the cycle delay. The results of the
                 implementation of the proposed radix-10 division unit
                 show that its latency is close to that of radix-16
                 division units (comparable dynamic range of
                 significands) and it has a shorter latency than a
                 radix-10 unit based on the Newton--Raphson
                 approximation.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "algorithms and architectures for floating-point
                 arithmetic; decimal arithmetic; decimal division;
                 decimal floating-point arithmetic; digit-recurrence
                 division",
}


bibtype: inproceedings
filename: fparith.bib
label: Langlois:2007:HEF
author: Philippe Langlois and Nicolas Louvet
title: How to Ensure a Faithful Polynomial Evaluation with the Compensated Horner Algorithm
crossref: Kornerup:2007:PIS
pages: 141--149
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.21
bibdate: Tue Oct 9 16:32:41 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 16:32:41 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Philippe Langlois and Nicolas Louvet
rawtitle: How to Ensure a Faithful Polynomial Evaluation with the Compensated {Horner} Algorithm
abstract:
The compensated Horner algorithm improves the accuracy of polynomial evaluation in IEEE-754 floating point arithmetic: the computed result is as accurate as if it was computed with the classic Horner algorithm in twice the working precision. Since the condition number still governs the accuracy of this computation, it may return an arbitrary number of inexact digits. We address here how to compute a faithfully rounded result, that is one of the two floating point neighbors of the exact evaluation. We propose an a priori sufficient condition on the condition number to ensure that the compensated evaluation is faithfully rounded. We also propose a validated and dynamic method to test at the running time if the compensated result is actually faithfully rounded. Numerical experiments illustrate the behavior of these two conditions and that the associated running time over-cost is really interesting.

rawabstract:
The compensated Horner algorithm improves the accuracy of polynomial evaluation in IEEE-754 floating point arithmetic: the computed result is as accurate as if it was computed with the classic Horner algorithm in twice the working precision. Since the condition number still governs the accuracy of this computation, it may return an arbitrary number of inexact digits. We address here how to compute a faithfully rounded result, that is one of the two floating point neighbors of the exact evaluation. We propose an a priori sufficient condition on the condition number to ensure that the compensated evaluation is faithfully rounded. We also propose a validated and dynamic method to test at the running time if the compensated result is actually faithfully rounded. Numerical experiments illustrate the behavior of these two conditions and that the associated running time over-cost is really interesting.

entry:
@InProceedings{Langlois:2007:HEF,
  author =       "Philippe Langlois and Nicolas Louvet",
  title =        "How to Ensure a Faithful Polynomial Evaluation with
                 the Compensated {Horner} Algorithm",
  crossref =     "Kornerup:2007:PIS",
  pages =        "141--149",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.21",
  bibdate =      "Tue Oct 9 16:32:41 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The compensated Horner algorithm improves the accuracy
                 of polynomial evaluation in IEEE-754 floating point
                 arithmetic: the computed result is as accurate as if it
                 was computed with the classic Horner algorithm in twice
                 the working precision. Since the condition number still
                 governs the accuracy of this computation, it may return
                 an arbitrary number of inexact digits. We address here
                 how to compute a faithfully rounded result, that is one
                 of the two floating point neighbors of the exact
                 evaluation. We propose an a priori sufficient condition
                 on the condition number to ensure that the compensated
                 evaluation is faithfully rounded. We also propose a
                 validated and dynamic method to test at the running
                 time if the compensated result is actually faithfully
                 rounded. Numerical experiments illustrate the behavior
                 of these two conditions and that the associated running
                 time over-cost is really interesting.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: techreport
filename: fparith.bib
label: Langlois:2007:MIL
author: Philippe Langlois and Nicolas Louvet
title: More Instruction Level Parallelism Explains the Actual Efficiency of Compensated Algorithms
institution: Laboratoire de Physique Appliquee et d'Automatique
address: Perpignan, France
pages: 11
year: 2007
bibdate: Sat Apr 01 07:54:10 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.04.01 07:54:10 ???
acknowledgement: ack-nhfb
rawauthor: Philippe Langlois and Nicolas Louvet
rawtitle: More Instruction Level Parallelism Explains the Actual Efficiency of Compensated Algorithms
URL:
http://hal.archives-ouvertes.fr/hal-00165020; https://hal.archives-ouvertes.fr/hal-00165020/document

abstract:
The compensated Horner algorithm and the Horner algorithm with double-double arithmetic improve the accuracy of polynomial evaluation in IEEE-754 floating point arithmetic. Both yield a polynomial evaluation as accurate as if it was computed with the classic Horner algorithm in twice the working precision. Both algorithms also share the same low-level computation of the floating point rounding errors and cost a similar number of floating point operations. We report numerical experiments to exhibit that the compensated algorithm runs at least twice as fast as the double-double one on modern processors. We propose to explain such efficiency by identifying more instruction level parallelism in the compensated implementation. Such property also applies to other compensated algorithms for summation, dot product and triangular linear system solving. More generally this paper illustrates how this kind of performance analysis may be useful to highlight the actual efficiency of numerical algorithms.

rawabstract:
The compensated Horner algorithm and the Horner algorithm with double-double arithmetic improve the accuracy of polynomial evaluation in IEEE-754 floating point arithmetic. Both yield a polynomial evaluation as accurate as if it was computed with the classic Horner algorithm in twice the working precision. Both algorithms also share the same low-level computation of the floating point rounding errors and cost a similar number of floating point operations. We report numerical experiments to exhibit that the compensated algorithm runs at least twice as fast as the double-double one on modern processors. We propose to explain such efficiency by identifying more instruction level parallelism in the compensated implementation. Such property also applies to other compensated algorithms for summation, dot product and triangular linear system solving. More generally this paper illustrates how this kind of performance analysis may be useful to highlight the actual efficiency of numerical algorithms.

entry:
@TechReport{Langlois:2007:MIL,
  author =       "Philippe Langlois and Nicolas Louvet",
  title =        "More Instruction Level Parallelism Explains the Actual
                 Efficiency of Compensated Algorithms",
  institution =  "Laboratoire de Physique Appliqu{\'e}e et
                 d'Automatique",
  address =      "Perpignan, France",
  pages =        "11",
  year =         "2007",
  bibdate =      "Sat Apr 01 07:54:10 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://hal.archives-ouvertes.fr/hal-00165020;
                 https://hal.archives-ouvertes.fr/hal-00165020/document",
  abstract =     "The compensated Horner algorithm and the Horner
                 algorithm with double-double arithmetic improve the
                 accuracy of polynomial evaluation in IEEE-754 floating
                 point arithmetic. Both yield a polynomial evaluation as
                 accurate as if it was computed with the classic Horner
                 algorithm in twice the working precision. Both
                 algorithms also share the same low-level computation of
                 the floating point rounding errors and cost a similar
                 number of floating point operations. We report
                 numerical experiments to exhibit that the compensated
                 algorithm runs at least twice as fast as the
                 double-double one on modern processors. We propose to
                 explain such efficiency by identifying more instruction
                 level parallelism in the compensated implementation.
                 Such property also applies to other compensated
                 algorithms for summation, dot product and triangular
                 linear system solving. More generally this paper
                 illustrates how this kind of performance analysis may
                 be useful to highlight the actual efficiency of
                 numerical algorithms.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Laurie:2007:VPA
author: Dirk Laurie
title: Variable-precision arithmetic considered perilous --- a detective story
journal: j-ELECTRON-TRANS-NUMER-ANAL
volume: 28
pages: 168--173
year: 2007 / 2008
ISSN: 1068-9613 (print), 1097-4067 (electronic) OR 10689613 (print), 10974067 (electronic)
ISSNL: 1068-9613 OR 10689613
bibdate: Mon Sep 6 12:28:30 MDT 2010
bibsource: http://etna.mcs.kent.edu/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.09.06 12:28:30 MDT
note: Special volume for Gene Golub.
URL: http://etna.mcs.kent.edu/vol.28.2007-2008/pp168-173.dir/pp168-173.pdf
fjournal: Electronic Transactions on Numerical Analysis
acknowledgement: ack-nhfb
journalURL: http://etna.mcs.kent.edu/
rawauthor: Dirk Laurie
rawnote: Special volume for Gene Golub.
rawtitle: Variable-precision arithmetic considered perilous --- a detective story
entry:
@Article{Laurie:2007:VPA,
  author =       "Dirk Laurie",
  title =        "Variable-precision arithmetic considered perilous ---
                 a detective story",
  journal =      j-ELECTRON-TRANS-NUMER-ANAL,
  volume =       "28",
  pages =        "168--173",
  year =         "2007\slash 2008",
  CODEN =        "????",
  ISSN =         "1068-9613 (print), 1097-4067 (electronic)",
  ISSN-L =       "1068-9613",
  bibdate =      "Mon Sep 6 12:28:30 MDT 2010",
  bibsource =    "http://etna.mcs.kent.edu/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Special volume for Gene Golub.",
  URL =          "http://etna.mcs.kent.edu/vol.28.2007-2008/pp168-173.dir/pp168-173.pdf",
  acknowledgement = ack-nhfb,
  fjournal =     "Electronic Transactions on Numerical Analysis",
  journal-URL =  "http://etna.mcs.kent.edu/",
}


bibtype: techreport
filename: fparith.bib
label: Lefevre:2007:SNP
author: Vincent Lefevre and Jean-Michel Muller
title: Some notes on the possible under / overflow of the most common elementary functions
type: Report
institution: LIP, Ecole Normale Superieure de Lyon
address: Lyon, France
pages: 7
year: 2007
bibdate: Fri May 25 16:18:32 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.05.25 16:18:32 ???
URL: http://prunel.ccsd.cnrs.fr/ensl-00149414
keywords: elementary functions; floating-point arithmetic; overflow; underflow
acknowledgement: ack-nhfb
rawauthor: Vincent Lef{\'e}vre and Jean-Michel Muller
rawtitle: Some notes on the possible under\slash overflow of the most common elementary functions
abstract:
The purpose of this short note is not to describe when underflow or overflow must be signalled (it is quite clear that the rules are the same as for the basic arithmetic operations). We just want to show that for some of the most common functions and floating-point formats, in many cases, we can know in advance that the results will always lie in the range of the numbers that are representable by normal floating-point numbers, so that in these cases there is no need to worry about underflow or overflow. Note that when it is not the case, an implementation is still possible using a run-time test.

rawabstract:
The purpose of this short note is not to describe when underflow or overflow must be signalled (it is quite clear that the rules are the same as for the basic arithmetic operations). We just want to show that for some of the most common functions and floating-point formats, in many cases, we can know in advance that the results will always lie in the range of the numbers that are representable by normal floating-point numbers, so that in these cases there is no need to worry about underflow or overflow. Note that when it is not the case, an implementation is still possible using a run-time test.

entry:
@TechReport{Lefevre:2007:SNP,
  author =       "Vincent Lef{\'e}vre and Jean-Michel Muller",
  title =        "Some notes on the possible under\slash overflow of the
                 most common elementary functions",
  type =         "Report",
  institution =  "LIP, {\'E}cole Normale Sup{\'e}rieure de Lyon",
  address =      "Lyon, France",
  pages =        "7",
  year =         "2007",
  bibdate =      "Fri May 25 16:18:32 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://prunel.ccsd.cnrs.fr/ensl-00149414",
  abstract =     "The purpose of this short note is not to describe when
                 underflow or overflow must be signalled (it is quite
                 clear that the rules are the same as for the basic
                 arithmetic operations). We just want to show that for
                 some of the most common functions and floating-point
                 formats, in many cases, we can know in advance that the
                 results will always lie in the range of the numbers
                 that are representable by normal floating-point
                 numbers, so that in these cases there is no need to
                 worry about underflow or overflow. Note that when it is
                 not the case, an implementation is still possible using
                 a run-time test.",
  acknowledgement = ack-nhfb,
  keywords =     "elementary functions; floating-point arithmetic;
                 overflow; underflow",
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2007:DDP
author: Zhaolin Li and Gongqiong Li
crossref: Becker:2007:EVT
pages: 492--497
year: 2007
DOI: https://doi.org/10.1109/ISVLSI.2007.37
bibdate: Sun Feb 20 10:48:57 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.20 10:48:57 ???
acknowledgement: ack-nhfb
rawauthor: Zhaolin Li and Gongqiong Li
title:
Design of a Double-Precision Floating-Point Multiply-Add-Fused Unit with Consideration of Data Dependence

rawtitle:
Design of a Double-Precision Floating-Point Multiply-Add-Fused Unit with Consideration of Data Dependence

entry:
@InProceedings{Li:2007:DDP,
  author =       "Zhaolin Li and Gongqiong Li",
  title =        "Design of a Double-Precision Floating-Point
                 Multiply-Add-Fused Unit with Consideration of Data
                 Dependence",
  crossref =     "Becker:2007:EVT",
  pages =        "492--497",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ISVLSI.2007.37",
  bibdate =      "Sun Feb 20 10:48:57 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2007:DEF
author: Zhaolin Li and Gongqiong Li
crossref: IEEE:2007:ICI
pages: 17--20
year: 2007
DOI: https://doi.org/10.1109/ISICIR.2007.4441785
bibdate: Sun Feb 20 10:13:02 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.20 10:13:02 ???
acknowledgement: ack-nhfb
rawauthor: Zhaolin Li and Gongqiong Li
title:
Design of an Extended Floating-Point Multiply-Add-Fused Unit for Exploiting Instruction-Level Parallelism

abstract:
This paper presents an extended single-precision floating-point multiply-add-fused unit, called EMAF unit, which is designed for exploiting instruction-level parallelism. Concurrent addition and multiplication instructions can be executed in parallel besides traditional multiply-add-fused instructions. Moreover, some other kinds of two consecutive but dependent instructions can also be accelerated without stalling anyone. At the same time the accuracy is also increased over the traditional multiply-add-fused units. The EMAF unit is implemented with three pipeline stages. Experiment results show that compared with the traditional multiply-add-fused unit up to 26% cycle reduction is gained at the cost of 0.1 ns time penalty.

rawabstract:
This paper presents an extended single-precision floating-point multiply-add-fused unit, called EMAF unit, which is designed for exploiting instruction-level parallelism. Concurrent addition and multiplication instructions can be executed in parallel besides traditional multiply-add-fused instructions. Moreover, some other kinds of two consecutive but dependent instructions can also be accelerated without stalling anyone. At the same time the accuracy is also increased over the traditional multiply-add-fused units. The EMAF unit is implemented with three pipeline stages. Experiment results show that compared with the traditional multiply-add-fused unit up to 26\% cycle reduction is gained at the cost of 0.1 ns time penalty.

rawtitle:
Design of an Extended Floating-Point Multiply-Add-Fused Unit for Exploiting Instruction-Level Parallelism

entry:
@InProceedings{Li:2007:DEF,
  author =       "Zhaolin Li and Gongqiong Li",
  title =        "Design of an Extended Floating-Point
                 Multiply-Add-Fused Unit for Exploiting
                 Instruction-Level Parallelism",
  crossref =     "IEEE:2007:ICI",
  pages =        "17--20",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ISICIR.2007.4441785",
  bibdate =      "Sun Feb 20 10:13:02 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "This paper presents an extended single-precision
                 floating-point multiply-add-fused unit, called EMAF
                 unit, which is designed for exploiting
                 instruction-level parallelism. Concurrent addition and
                 multiplication instructions can be executed in parallel
                 besides traditional multiply-add-fused instructions.
                 Moreover, some other kinds of two consecutive but
                 dependent instructions can also be accelerated without
                 stalling anyone. At the same time the accuracy is also
                 increased over the traditional multiply-add-fused
                 units. The EMAF unit is implemented with three pipeline
                 stages. Experiment results show that compared with the
                 traditional multiply-add-fused unit up to 26\% cycle
                 reduction is gained at the cost of 0.1 ns time
                 penalty.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2007:DFP
author: Gongqiong Li and Zhaolin Li
title: Design of a Fully Pipelined Single-Precision Multiply-Add-Fused Unit
crossref: IEEE:2007:ICV
pages: 318--323
year: 2007
DOI: https://doi.org/10.1109/VLSID.2007.64
bibdate: Sun Feb 20 10:15:37 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.20 10:15:37 ???
acknowledgement: ack-nhfb
rawauthor: Gongqiong Li and Zhaolin Li
rawtitle: Design of a Fully Pipelined Single-Precision Multiply-Add-Fused Unit
abstract:
The floating point multiply-add operation A+BtimesC is fundamental in many scientific and multimedia applications. This paper presents a fully pipelined single-precision multiply-add fused unit, which is based on the combination of the final addition with rounding. Normalization is performed before the final addition to determine the rounding position. A three-step normalization method is proposed for attaining latency reduction. Moreover, this paper presents a method to eliminate a one-bit error of the multiply result for increasing the precision. Finally, a new technique to deal with the number of 1, which is added in the LSB of the operand to get 2's complement, is proposed to reduce logic complexity and time delay. The overall MAF unit has a latency of 5 cycles, a throughput of 1 cycle, and a cycle time of 1.82 ns in 0.18 mum CMOS technology.

rawabstract:
The floating point multiply-add operation A+BtimesC is fundamental in many scientific and multimedia applications. This paper presents a fully pipelined single-precision multiply-add fused unit, which is based on the combination of the final addition with rounding. Normalization is performed before the final addition to determine the rounding position. A three-step normalization method is proposed for attaining latency reduction. Moreover, this paper presents a method to eliminate a one-bit error of the multiply result for increasing the precision. Finally, a new technique to deal with the number of 1, which is added in the LSB of the operand to get 2's complement, is proposed to reduce logic complexity and time delay. The overall MAF unit has a latency of 5 cycles, a throughput of 1 cycle, and a cycle time of 1.82 ns in 0.18 mum CMOS technology.

entry:
@InProceedings{Li:2007:DFP,
  author =       "Gongqiong Li and Zhaolin Li",
  title =        "Design of a Fully Pipelined Single-Precision
                 Multiply-Add-Fused Unit",
  crossref =     "IEEE:2007:ICV",
  pages =        "318--323",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/VLSID.2007.64",
  bibdate =      "Sun Feb 20 10:15:37 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The floating point multiply-add operation A+BtimesC is
                 fundamental in many scientific and multimedia
                 applications. This paper presents a fully pipelined
                 single-precision multiply-add fused unit, which is
                 based on the combination of the final addition with
                 rounding. Normalization is performed before the final
                 addition to determine the rounding position. A
                 three-step normalization method is proposed for
                 attaining latency reduction. Moreover, this paper
                 presents a method to eliminate a one-bit error of the
                 multiply result for increasing the precision. Finally,
                 a new technique to deal with the number of 1, which is
                 added in the LSB of the operand to get 2's complement,
                 is proposed to reduce logic complexity and time delay.
                 The overall MAF unit has a latency of 5 cycles, a
                 throughput of 1 cycle, and a cycle time of 1.82 ns in
                 0.18 mum CMOS technology.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Li:2007:FAT
author: Xin Li and Marc Moreno Maza and Eric Schost
title: Fast arithmetic for triangular sets: from theory to practice
crossref: Brown:2007:PIS
pages: 269--276
year: 2007
DOI: https://doi.org/10.1145/1277548.1277585
bibdate: Fri Jun 20 08:46:50 MDT 2008
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.06.20 08:46:50 MDT
keywords: high-performance; multiplication; triangular set
acknowledgement: ack-nhfb
rawauthor: Xin Li and Marc Moreno Maza and {\'E}ric Schost
rawtitle: Fast arithmetic for triangular sets: from theory to practice
abstract:
We study arithmetic operations for triangular families of polynomials, concentrating on multiplication in dimension zero. By a suitable extension of fast univariate Euclidean division, we obtain theoretical and practical improvements over a direct recursive approach; for a family of special cases, we reach quasi-linear complexity. The main outcome we have in mind is the acceleration of higher-level algorithms, by interfacing our low-level implementation with languages such as AXIOM or Maple We show the potential for huge speed-ups, by comparing two AXIOM implementations of van Hoeij and Monagan's modular GCD algorithm.

rawabstract:
We study arithmetic operations for triangular families of polynomials, concentrating on multiplication in dimension zero. By a suitable extension of fast univariate Euclidean division, we obtain theoretical and practical improvements over a direct recursive approach; for a family of special cases, we reach quasi-linear complexity. The main outcome we have in mind is the acceleration of higher-level algorithms, by interfacing our low-level implementation with languages such as AXIOM or Maple We show the potential for huge speed-ups, by comparing two AXIOM implementations of van Hoeij and Monagan's modular GCD algorithm.

entry:
@InProceedings{Li:2007:FAT,
  author =       "Xin Li and Marc Moreno Maza and {\'E}ric Schost",
  title =        "Fast arithmetic for triangular sets: from theory to
                 practice",
  crossref =     "Brown:2007:PIS",
  pages =        "269--276",
  year =         "2007",
  DOI =          "https://doi.org/10.1145/1277548.1277585",
  bibdate =      "Fri Jun 20 08:46:50 MDT 2008",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We study arithmetic operations for triangular families
                 of polynomials, concentrating on multiplication in
                 dimension zero. By a suitable extension of fast
                 univariate Euclidean division, we obtain theoretical
                 and practical improvements over a direct recursive
                 approach; for a family of special cases, we reach
                 quasi-linear complexity. The main outcome we have in
                 mind is the acceleration of higher-level algorithms, by
                 interfacing our low-level implementation with languages
                 such as AXIOM or Maple We show the potential for huge
                 speed-ups, by comparing two AXIOM implementations of
                 van Hoeij and Monagan's modular GCD algorithm.",
  acknowledgement = ack-nhfb,
  keywords =     "high-performance; multiplication; triangular set",
}


bibtype: inproceedings
filename: fparith.bib
label: Lopez:2007:EIF
author: Guillermo A. Lopez and Michela Taufer and Patricia J. Teller
crossref: Morales:2007:TRT
pages: 1--4
year: 2007
bibdate: Fri Aug 08 08:39:30 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.08 08:39:30 ???
acknowledgement: ack-nhfb
rawauthor: Guillermo A. Lopez and Michela Taufer and Patricia J. Teller
title:
Evaluation of IEEE 754 floating-point arithmetic compliance across a wide range of heterogeneous computers

abstract:
Scientific applications rely heavily on floating-point arithmetic and, therefore, are affected by the precision and implementation of floating-point operations. Although the computers we use are IEEE compliant, this only assures the same representation of floating-point numbers; it does not guarantee that floating-point operations will be performed in the same way on all computers. As a result the same program run on different computers may yield different results. This paper is a first step in understanding the reason for this, in particular, different results for the execution of the application Charmm on different computers. We report on our use of a well-known test suite, IeeeCC754, to evaluate IEEE 754 compliance across a wide range of heterogeneous computers with different architectures, operating systems, precisions, and compilers.

rawabstract:
Scientific applications rely heavily on floating-point arithmetic and, therefore, are affected by the precision and implementation of floating-point operations. Although the computers we use are IEEE compliant, this only assures the same representation of floating-point numbers; it does not guarantee that floating-point operations will be performed in the same way on all computers. As a result the same program run on different computers may yield different results. This paper is a first step in understanding the reason for this, in particular, different results for the execution of the application Charmm on different computers. We report on our use of a well-known test suite, IeeeCC754, to evaluate IEEE 754 compliance across a wide range of heterogeneous computers with different architectures, operating systems, precisions, and compilers.

rawtitle:
Evaluation of {IEEE 754} floating-point arithmetic compliance across a wide range of heterogeneous computers

entry:
@InProceedings{Lopez:2007:EIF,
  author =       "Guillermo A. Lopez and Michela Taufer and Patricia J.
                 Teller",
  title =        "Evaluation of {IEEE 754} floating-point arithmetic
                 compliance across a wide range of heterogeneous
                 computers",
  crossref =     "Morales:2007:TRT",
  pages =        "1--4",
  year =         "2007",
  bibdate =      "Fri Aug 08 08:39:30 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Scientific applications rely heavily on floating-point
                 arithmetic and, therefore, are affected by the
                 precision and implementation of floating-point
                 operations. Although the computers we use are IEEE
                 compliant, this only assures the same representation of
                 floating-point numbers; it does not guarantee that
                 floating-point operations will be performed in the same
                 way on all computers. As a result the same program run
                 on different computers may yield different results.
                 This paper is a first step in understanding the reason
                 for this, in particular, different results for the
                 execution of the application Charmm on different
                 computers. We report on our use of a well-known test
                 suite, IeeeCC754, to evaluate IEEE 754 compliance
                 across a wide range of heterogeneous computers with
                 different architectures, operating systems, precisions,
                 and compilers.",
  acknowledgement = ack-nhfb,
}


bibtype: phdthesis
filename: fparith.bib
label: Louvet:2007:ACA
author: Nicolas Louvet
title: Algorithmes compenses en arithmetique flottante: precision, validation, performances
type: Docteur de l'universite de Perpignan specialite: Informatique
address: Perpignan, France
pages: vi + 188
day: 27
month: nov
monthnumber: 11
year: 2007
bibdate: Mon Mar 19 14:32:15 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.03.19 14:32:15 ???
URL: https://tel.archives-ouvertes.fr/tel-01315543/en
acknowledgement: ack-nhfb
rawauthor: Nicolas Louvet
rawtitle: Algorithmes compens{\'e}s en arithm{\'e}tique flottante: pr{\'e}cision, validation, performances
school:
Laboratoire ELIAUS: Electronique, Informatique, Automatique et Systemes, Universite de Perpignan Via Domitia

abstract:
Rounding error may totally corrupt the result of a floating point computation. How to improve and validate the accuracy of a floating point computation, without large computing time overheads ? We consider two case studies: polynomial evaluation and linear triangular system solving. In both cases we use compensation of the rounding errors to improve the accuracy of the computed result. The contributions of this work are divided into three levels. (1) Improving the accuracy. We propose a compensated Horner scheme that computes polynomial evaluation with the same accuracy as the classic Horner algorithm performed in twice the working precision. Generalizing this algorithm, we present another compensated version of the Horner scheme simulating $K$ times the working precision ($ K > 1$). We also show how to compensate the rounding errors generated by the substitution algorithm for triangular system solving. (2) Validating the computed result. We show how to validate the quality of the compensated polynomial evaluation. We propose a method to compute an ``a posteriori'' error bound together with the compensated result. This error bound is computed using only basic floating point operations, which ensures portability and efficiency of the method. (3) Performances of compensated algorithms. Our computing time measures show the interest of compensated algorithms compared to other software solutions that provide the same output accuracy. We also justify good practical performances of compensated algorithms thanks to a detailed study of the instruction-level parallelism they contain.

keywords:
compensated algorithms; Computer arithmetic; efficient algorithms; IEEE-754 standard; numerical algorithms

rawabstract:
Rounding error may totally corrupt the result of a floating point computation. How to improve and validate the accuracy of a floating point computation, without large computing time overheads ? We consider two case studies: polynomial evaluation and linear triangular system solving. In both cases we use compensation of the rounding errors to improve the accuracy of the computed result. The contributions of this work are divided into three levels. (1) Improving the accuracy. We propose a compensated Horner scheme that computes polynomial evaluation with the same accuracy as the classic Horner algorithm performed in twice the working precision. Generalizing this algorithm, we present another compensated version of the Horner scheme simulating $K$ times the working precision ($ K > 1$). We also show how to compensate the rounding errors generated by the substitution algorithm for triangular system solving. (2) Validating the computed result. We show how to validate the quality of the compensated polynomial evaluation. We propose a method to compute an ``a posteriori'' error bound together with the compensated result. This error bound is computed using only basic floating point operations, which ensures portability and efficiency of the method. (3) Performances of compensated algorithms. Our computing time measures show the interest of compensated algorithms compared to other software solutions that provide the same output accuracy. We also justify good practical performances of compensated algorithms thanks to a detailed study of the instruction-level parallelism they contain.

entry:
@PhdThesis{Louvet:2007:ACA,
  author =       "Nicolas Louvet",
  title =        "Algorithmes compens{\'e}s en arithm{\'e}tique
                 flottante: pr{\'e}cision, validation, performances",
  type =         "{Docteur de l'universit{\'e} de Perpignan
                 sp{\'e}cialit{\'e}: Informatique}",
  school =       "Laboratoire ELIAUS: {\'E}lectronique, Informatique,
                 Automatique et Syst{\`e}mes, Universit{\'e} de
                 Perpignan Via Domitia",
  address =      "Perpignan, France",
  pages =        "vi + 188",
  day =          "27",
  month =        nov,
  year =         "2007",
  bibdate =      "Mon Mar 19 14:32:15 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://tel.archives-ouvertes.fr/tel-01315543/en",
  abstract =     "Rounding error may totally corrupt the result of a
                 floating point computation. How to improve and validate
                 the accuracy of a floating point computation, without
                 large computing time overheads ? We consider two case
                 studies: polynomial evaluation and linear triangular
                 system solving. In both cases we use compensation of
                 the rounding errors to improve the accuracy of the
                 computed result. The contributions of this work are
                 divided into three levels. (1) Improving the accuracy.
                 We propose a compensated Horner scheme that computes
                 polynomial evaluation with the same accuracy as the
                 classic Horner algorithm performed in twice the working
                 precision. Generalizing this algorithm, we present
                 another compensated version of the Horner scheme
                 simulating $K$ times the working precision ($ K > 1$).
                 We also show how to compensate the rounding errors
                 generated by the substitution algorithm for triangular
                 system solving. (2) Validating the computed result. We
                 show how to validate the quality of the compensated
                 polynomial evaluation. We propose a method to compute
                 an ``a posteriori'' error bound together with the
                 compensated result. This error bound is computed using
                 only basic floating point operations, which ensures
                 portability and efficiency of the method. (3)
                 Performances of compensated algorithms. Our computing
                 time measures show the interest of compensated
                 algorithms compared to other software solutions that
                 provide the same output accuracy. We also justify good
                 practical performances of compensated algorithms thanks
                 to a detailed study of the instruction-level
                 parallelism they contain.",
  acknowledgement = ack-nhfb,
  keywords =     "compensated algorithms; Computer arithmetic; efficient
                 algorithms; IEEE-754 standard; numerical algorithms",
}


bibtype: misc
filename: fparith.bib
label: Lundvall:2007:CDF
author: Shawn D. Lundvall and Eric M. Schwarz and Ronald M. Smith, Sr. and Phil C. Yeh
title: Composition of decimal floating point data, and methods therefor
pages: vi + 188
day: 26
month: apr
monthnumber: 4
year: 2007
bibdate: Thu Mar 15 09:28:54 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.03.15 09:28:54 ???
URL: https://patents.google.com/patent/US8060545
acknowledgement: ack-nhfb
howpublished: US Patent 8060545B2.
rawauthor: Shawn D. Lundvall and Eric M. Schwarz and Ronald M. {Smith, Sr.} and Phil C. Yeh
rawtitle: Composition of decimal floating point data, and methods therefor
abstract:
A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.

rawabstract:
A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.

entry:
@Misc{Lundvall:2007:CDF,
  author =       "Shawn D. Lundvall and Eric M. Schwarz and Ronald M.
                 {Smith, Sr.} and Phil C. Yeh",
  title =        "Composition of decimal floating point data, and
                 methods therefor",
  howpublished = "US Patent 8060545B2.",
  day =          "26",
  month =        apr,
  year =         "2007",
  bibdate =      "Thu Mar 15 09:28:54 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://patents.google.com/patent/US8060545",
  abstract =     "A decimal floating point finite number in a decimal
                 floating point format is composed from the number in a
                 different format. A decimal floating point format
                 includes fields to hold information relating to the
                 sign, exponent and significand of the decimal floating
                 point finite number. Other decimal floating point data,
                 including infinities and NaNs (not a number), are also
                 composed. Decimal floating point data are also
                 decomposed from the decimal floating point format to a
                 different format.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Lundvall:2007:DDF
author: Shawn D. Lundvall and Eric M. Schwarz and Ronald M. Smith, Sr. and Phil C. Yeh
title: Decomposition of decimal floating point data
pages: vi + 188
day: 26
month: apr
monthnumber: 4
year: 2007
bibdate: Thu Mar 15 09:31:05 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.03.15 09:31:05 ???
URL: https://patents.google.com/patent/US9690580B2/en
acknowledgement: ack-nhfb
howpublished: US Patent 9690580B2.
rawauthor: Shawn D. Lundvall and Eric M. Schwarz and Ronald M. {Smith, Sr.} and Phil C. Yeh
rawtitle: Decomposition of decimal floating point data
abstract:
A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.

entry:
@Misc{Lundvall:2007:DDF,
  author =       "Shawn D. Lundvall and Eric M. Schwarz and Ronald M.
                 {Smith, Sr.} and Phil C. Yeh",
  title =        "Decomposition of decimal floating point data",
  howpublished = "US Patent 9690580B2.",
  day =          "26",
  month =        apr,
  year =         "2007",
  bibdate =      "Thu Mar 15 09:31:05 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://patents.google.com/patent/US9690580B2/en",
  abstract =     "A decimal floating point finite number in a decimal
                 floating point format is composed from the number in a
                 different format. A decimal floating point format
                 includes fields to hold information relating to the
                 sign, exponent and significand of the decimal floating
                 point finite number. Other decimal floating point data,
                 including infinities and NaNs (not a number), are also
                 composed. Decimal floating point data are also
                 decomposed from the decimal floating point format to a
                 different format.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Maslennikow:2007:DFB
title: Design of FPGA-based Residue Number System Converters for Digital Signal Processing Systems
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 194--201
year: 2007
DOI: https://doi.org/10.1109/CADSM.2007.4297523
bibdate: Fri Nov 9 11:38:59 MST 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.09 11:38:59 MST
keywords: residue arithmetic; residue number system
acknowledgement: ack-nhfb
rawtitle: Design of {FPGA}-based Residue Number System Converters for Digital Signal Processing Systems
author:
Oleg Maslennikow and Natalia Maslennikowa and Magdalena Rajewska and Dariusz Gretkowski and Jean-Pierre Lienou

booktitle:
CADSM '07. 9th International Conference --- The Experience of Designing and Applications of CAD Systems in Microelectronics

rawauthor:
Oleg Maslennikow and Natalia Maslennikowa and Magdalena Rajewska and Dariusz Gretkowski and Jean-Pierre Lienou

rawbooktitle:
{CADSM '07}. 9th International Conference --- The Experience of Designing and Applications of {CAD} Systems in Microelectronics

entry:
@InProceedings{Maslennikow:2007:DFB,
  author =       "Oleg Maslennikow and Natalia Maslennikowa and
                 Magdalena Rajewska and Dariusz Gretkowski and
                 Jean-Pierre Lienou",
  booktitle =    "{CADSM '07}. 9th International Conference --- The
                 Experience of Designing and Applications of {CAD}
                 Systems in Microelectronics",
  title =        "Design of {FPGA}-based Residue Number System
                 Converters for Digital Signal Processing Systems",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "194--201",
  year =         "2007",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1109/CADSM.2007.4297523",
  ISSN =         "????",
  bibdate =      "Fri Nov 9 11:38:59 MST 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "residue arithmetic; residue number system",
  summary =      "In this paper, two new and simple structures of the
                 q-operands multi-operand modular adder have been
                 proposed, which are adapted to realization in the
                 Xilinx FPGA devices. The main purpose of new MOMA
                 designs has been the reduction of hardware \ldots{}",
}


bibtype: article
filename: fparith.bib
label: Melquiond:2007:FCF
author: Guillaume Melquiond and Sylvain Pion
title: Formally certified floating-point filters for homogeneous geometric predicates
journal: j-INFORM-THEOR-APPL
volume: 41
number: 1
pages: 57--69
year: 2007
CODEN: RSITD7, RITAE4
DOI: https://doi.org/10.1051/ita:2007005
ISSN: 0988-3754 (print), 1290-385X (electronic) OR 09883754 (print), 1290385X (electronic)
ISSNL: 0988-3754 OR 09883754
MRclass: 68U05 (65G50)
MRnumber: MR2330043
bibdate: Thu Nov 08 19:16:32 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.08 19:16:32 ???
fjournal: Theoretical Informatics and Applications. Informatique Theorique et Applications
acknowledgement: ack-nhfb
rawauthor: Guillaume Melquiond and Sylvain Pion
rawtitle: Formally certified floating-point filters for homogeneous geometric predicates
entry:
@Article{Melquiond:2007:FCF,
  author =       "Guillaume Melquiond and Sylvain Pion",
  title =        "Formally certified floating-point filters for
                 homogeneous geometric predicates",
  journal =      j-INFORM-THEOR-APPL,
  volume =       "41",
  number =       "1",
  pages =        "57--69",
  year =         "2007",
  CODEN =        "RSITD7, RITAE4",
  DOI =          "https://doi.org/10.1051/ita:2007005",
  ISSN =         "0988-3754 (print), 1290-385X (electronic)",
  ISSN-L =       "0988-3754",
  MRclass =      "68U05 (65G50)",
  MRnumber =     "MR2330043",
  bibdate =      "Thu Nov 08 19:16:32 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "Theoretical Informatics and Applications. Informatique
                 Th\'eorique et Applications",
}


bibtype: article
filename: fparith.bib
label: Mine:2007:RAD
author: Antoine Mine
title: Relational Abstract Domains for the Detection of Floating-Point Run-Time Errors
journal: arXiv.org
pages: ??--??
day: 15
month: mar
monthnumber: 3
year: 2007
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
note: Published in European Symposium on Programming (ESOP) (03/2004) 3--17.
URL: http://arxiv.org/abs/cs/0703077
subject: Programming Languages (cs.PL)
acknowledgement: ack-nhfb
rawauthor: Antoine Min{\'e}
rawnote: Published in European Symposium on Programming (ESOP) (03/2004) 3--17.
rawtitle: Relational Abstract Domains for the Detection of Floating-Point Run-Time Errors
abstract:
We present a new idea to adapt relational abstract domains to the analysis of IEEE 754-compliant floating-point numbers in order to statically detect, through abstract Interpretation-based static analyses, potential floating-point run-time exceptions such as overflows or invalid operations. In order to take the non-linearity of rounding into account, expressions are modeled as linear forms with interval coefficients. We show how to extend already existing numerical abstract domains, such as the octagon abstract domain, to efficiently abstract transfer functions based on interval linear forms. We discuss specific fixpoint stabilization techniques and give some experimental results.

rawabstract:
We present a new idea to adapt relational abstract domains to the analysis of IEEE 754-compliant floating-point numbers in order to statically detect, through abstract Interpretation-based static analyses, potential floating-point run-time exceptions such as overflows or invalid operations. In order to take the non-linearity of rounding into account, expressions are modeled as linear forms with interval coefficients. We show how to extend already existing numerical abstract domains, such as the octagon abstract domain, to efficiently abstract transfer functions based on interval linear forms. We discuss specific fixpoint stabilization techniques and give some experimental results.

entry:
@Article{Mine:2007:RAD,
  author =       "Antoine Min{\'e}",
  title =        "Relational Abstract Domains for the Detection of
                 Floating-Point Run-Time Errors",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "15",
  month =        mar,
  year =         "2007",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Published in European Symposium on Programming (ESOP)
                 (03/2004) 3--17.",
  URL =          "http://arxiv.org/abs/cs/0703077",
  abstract =     "We present a new idea to adapt relational abstract
                 domains to the analysis of IEEE 754-compliant
                 floating-point numbers in order to statically detect,
                 through abstract Interpretation-based static analyses,
                 potential floating-point run-time exceptions such as
                 overflows or invalid operations. In order to take the
                 non-linearity of rounding into account, expressions are
                 modeled as linear forms with interval coefficients. We
                 show how to extend already existing numerical abstract
                 domains, such as the octagon abstract domain, to
                 efficiently abstract transfer functions based on
                 interval linear forms. We discuss specific fixpoint
                 stabilization techniques and give some experimental
                 results.",
  acknowledgement = ack-nhfb,
  subject =      "Programming Languages (cs.PL)",
}


bibtype: techreport
filename: fparith.bib
label: Mitchell:2007:MFP
author: D. Mitchell and S. Noble
title: Multiprecision floating-point arithmetic on Apple systems
type: Report
institution: Advanced Computation Group, Apple Computer
address: Cupertino, CA, USA
pages: 23
day: 13
month: mar
monthnumber: 3
year: 2007
bibdate: Tue Mar 19 10:22:50 2013
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2013.03.19 10:22:50 ???
URL: http://images.apple.com/acg/pdf/MP_Floating_Point_20070313.pdf
keywords: ARPREC; GMP
acknowledgement: ack-nhfb
rawauthor: D. Mitchell and S. Noble
rawtitle: Multiprecision floating-point arithmetic on {Apple} systems
entry:
@TechReport{Mitchell:2007:MFP,
  author =       "D. Mitchell and S. Noble",
  title =        "Multiprecision floating-point arithmetic on {Apple}
                 systems",
  type =         "Report",
  institution =  "Advanced Computation Group, Apple Computer",
  address =      "Cupertino, CA, USA",
  pages =        "23",
  day =          "13",
  month =        mar,
  year =         "2007",
  bibdate =      "Tue Mar 19 10:22:50 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://images.apple.com/acg/pdf/MP_Floating_Point_20070313.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "ARPREC; GMP",
}


bibtype: article
filename: fparith.bib
label: Miyajima:2007:ETS
author: Shinya Miyajima and Masahide Kashiwagi
title: Existence test for solution of nonlinear systems applying affine arithmetic
journal: j-J-COMPUT-APPL-MATH
volume: 199
number: 2
pages: 304--309
day: 15
month: feb
monthnumber: 2
year: 2007
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:12:04 MST 2017
bibtimestamp: 2017.02.25 13:12:04 MST
URL: http://www.sciencedirect.com/science/article/pii/S037704270500765X
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Shinya Miyajima and Masahide Kashiwagi
rawtitle: Existence test for solution of nonlinear systems applying affine arithmetic
entry:
@Article{Miyajima:2007:ETS,
  author =       "Shinya Miyajima and Masahide Kashiwagi",
  title =        "Existence test for solution of nonlinear systems
                 applying affine arithmetic",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "199",
  number =       "2",
  pages =        "304--309",
  day =          "15",
  month =        feb,
  year =         "2007",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:12:04 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2005.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S037704270500765X",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: article
filename: fparith.bib
label: Monniaux:2007:AZT
author: David Monniaux
title: Applying the $Z$-transform for the static analysis of floating-point numerical filters
journal: arXiv.org
pages: ??--??
day: 2
month: jun
monthnumber: 6
year: 2007
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/0706.0252
subject: Programming Languages (cs.PL); Numerical Analysis (cs.NA)
acknowledgement: ack-nhfb
rawauthor: David Monniaux
rawtitle: Applying the {$Z$}-transform for the static analysis of floating-point numerical filters
abstract:
Digital linear filters are used in a variety of applications (sound treatment, control/command, etc.), implemented in software, in hardware, or a combination thereof. For safety-critical applications, it is necessary to bound all variables and outputs of all filters. We give a compositional, effective abstraction for digital linear filters expressed as block diagrams, yielding sound, precise bounds for fixed-point or floating-point implementations of the filters.

rawabstract:
Digital linear filters are used in a variety of applications (sound treatment, control/command, etc.), implemented in software, in hardware, or a combination thereof. For safety-critical applications, it is necessary to bound all variables and outputs of all filters. We give a compositional, effective abstraction for digital linear filters expressed as block diagrams, yielding sound, precise bounds for fixed-point or floating-point implementations of the filters.

entry:
@Article{Monniaux:2007:AZT,
  author =       "David Monniaux",
  title =        "Applying the {$Z$}-transform for the static analysis
                 of floating-point numerical filters",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "2",
  month =        jun,
  year =         "2007",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/0706.0252",
  abstract =     "Digital linear filters are used in a variety of
                 applications (sound treatment, control/command, etc.),
                 implemented in software, in hardware, or a combination
                 thereof. For safety-critical applications, it is
                 necessary to bound all variables and outputs of all
                 filters. We give a compositional, effective abstraction
                 for digital linear filters expressed as block diagrams,
                 yielding sound, precise bounds for fixed-point or
                 floating-point implementations of the filters.",
  acknowledgement = ack-nhfb,
  subject =      "Programming Languages (cs.PL); Numerical Analysis
                 (cs.NA)",
}


bibtype: techreport
filename: fparith.bib
label: Monniaux:2007:PVFa
author: David Monniaux
title: The pitfalls of verifying floating-point computations
type: Technical report
number: HAL-00128124
institution: CNRS / Ecole Normale Superieure
address: 45, rue d'Ulm 75230 Paris cedex 5, France
pages: 44
day: 29
month: jun
monthnumber: 6
year: 2007
bibdate: Fri Jul 06 18:10:00 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.07.06 18:10:00 ???
note: Published in cite Monniaux:2008:PVF.
URL: http://hal.archives-ouvertes.fr/docs/00/15/88/63/PDF/floating-point.pdf
acknowledgement: ack-nhfb
rawauthor: David Monniaux
rawnote: Published in \cite{Monniaux:2008:PVF}.
rawtitle: The pitfalls of verifying floating-point computations
abstract:
Current critical systems often use a lot of floating-point computations, and thus the testing or static analysis of programs containing floating-point operators has become a priority. However, correctly defining the semantics of common implementations of floating-point is tricky, because semantics may change according to many factors beyond source-code level, such as choices made by compilers. We here give concrete examples of problems that can appear and solutions for implementing in analysis software

rawabstract:
Current critical systems often use a lot of floating-point computations, and thus the testing or static analysis of programs containing floating-point operators has become a priority. However, correctly defining the semantics of common implementations of floating-point is tricky, because semantics may change according to many factors beyond source-code level, such as choices made by compilers. We here give concrete examples of problems that can appear and solutions for implementing in analysis software

entry:
@TechReport{Monniaux:2007:PVFa,
  author =       "David Monniaux",
  title =        "The pitfalls of verifying floating-point
                 computations",
  type =         "Technical report",
  number =       "HAL-00128124",
  institution =  "CNRS\slash {\'E}cole Normale Sup{\'e}rieure",
  address =      "45, rue d'Ulm 75230 Paris cedex 5, France",
  pages =        "44",
  day =          "29",
  month =        jun,
  year =         "2007",
  bibdate =      "Fri Jul 06 18:10:00 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Published in \cite{Monniaux:2008:PVF}.",
  URL =          "http://hal.archives-ouvertes.fr/docs/00/15/88/63/PDF/floating-point.pdf",
  abstract =     "Current critical systems often use a lot of
                 floating-point computations, and thus the testing or
                 static analysis of programs containing floating-point
                 operators has become a priority. However, correctly
                 defining the semantics of common implementations of
                 floating-point is tricky, because semantics may change
                 according to many factors beyond source-code level,
                 such as choices made by compilers. We here give
                 concrete examples of problems that can appear and
                 solutions for implementing in analysis software",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Monniaux:2007:PVFb
author: David Monniaux
title: The pitfalls of verifying floating-point computations
journal: arXiv.org
pages: ??--??
day: 30
month: jan
monthnumber: 1
year: 2007
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
note: Published in cite Monniaux:2008:PVF.
URL: http://arxiv.org/abs/cs/0701192
subject: Programming Languages (cs.PL); Numerical Analysis (cs.NA)
acknowledgement: ack-nhfb
rawauthor: David Monniaux
rawnote: Published in \cite{Monniaux:2008:PVF}.
rawtitle: The pitfalls of verifying floating-point computations
abstract:
Current critical systems commonly use a lot of floating-point computations, and thus the testing or static analysis of programs containing floating-point operators has become a priority. However, correctly defining the semantics of common implementations of floating-point is tricky, because semantics may change with many factors beyond source-code level, such as choices made by compilers. We here give concrete examples of problems that can appear and solutions to implement in analysis software.

rawabstract:
Current critical systems commonly use a lot of floating-point computations, and thus the testing or static analysis of programs containing floating-point operators has become a priority. However, correctly defining the semantics of common implementations of floating-point is tricky, because semantics may change with many factors beyond source-code level, such as choices made by compilers. We here give concrete examples of problems that can appear and solutions to implement in analysis software.

entry:
@Article{Monniaux:2007:PVFb,
  author =       "David Monniaux",
  title =        "The pitfalls of verifying floating-point
                 computations",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "30",
  month =        jan,
  year =         "2007",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  note =         "Published in \cite{Monniaux:2008:PVF}.",
  URL =          "http://arxiv.org/abs/cs/0701192",
  abstract =     "Current critical systems commonly use a lot of
                 floating-point computations, and thus the testing or
                 static analysis of programs containing floating-point
                 operators has become a priority. However, correctly
                 defining the semantics of common implementations of
                 floating-point is tricky, because semantics may change
                 with many factors beyond source-code level, such as
                 choices made by compilers. We here give concrete
                 examples of problems that can appear and solutions to
                 implement in analysis software.",
  acknowledgement = ack-nhfb,
  subject =      "Programming Languages (cs.PL); Numerical Analysis
                 (cs.NA)",
}


bibtype: article
filename: fparith.bib
label: Montuschi:2007:DDA
author: P. Montuschi and J. D. Bruguera and L. Ciminiera and J.-A. Pieiro
title: A Digit-by-Digit Algorithm for $m$ th Root Extraction
journal: j-IEEE-TRANS-COMPUT
volume: 56
number: 12
pages: 1696--1706
month: dec
monthnumber: 12
year: 2007
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.70764
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:03:43 MDT 2011
bibtimestamp: 2011.07.04 15:03:43 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4358221
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: P. Montuschi and J. D. Bruguera and L. Ciminiera and J.-A. Pieiro
rawtitle: A Digit-by-Digit Algorithm for $m$ th Root Extraction
abstract:
A general digit-recurrence algorithm for the computation of the $m$ th root (with an $m$ integer) is presented in this paper. Based on the concept of completing the mth root, a detailed analysis of the convergence conditions is performed and iteration- independent digit-selection rules are obtained for any radix and redundant digit set. A radix-2 version for mth rooting is also studied, together with closed formulas for both the digit selection rules and the number of bits required to perform correct selections.

rawabstract:
A general digit-recurrence algorithm for the computation of the $m$ th root (with an $m$ integer) is presented in this paper. Based on the concept of completing the mth root, a detailed analysis of the convergence conditions is performed and iteration- independent digit-selection rules are obtained for any radix and redundant digit set. A radix-2 version for mth rooting is also studied, together with closed formulas for both the digit selection rules and the number of bits required to perform correct selections.

entry:
@Article{Montuschi:2007:DDA,
  author =       "P. Montuschi and J. D. Bruguera and L. Ciminiera and
                 J.-A. Pieiro",
  title =        "A Digit-by-Digit Algorithm for $m$ th Root
                 Extraction",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "56",
  number =       "12",
  pages =        "1696--1706",
  month =        dec,
  year =         "2007",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.70764",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:03:43 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4358221",
  abstract =     "A general digit-recurrence algorithm for the
                 computation of the $m$ th root (with an $m$ integer) is
                 presented in this paper. Based on the concept of
                 completing the mth root, a detailed analysis of the
                 convergence conditions is performed and iteration-
                 independent digit-selection rules are obtained for any
                 radix and redundant digit set. A radix-2 version for
                 mth rooting is also studied, together with closed
                 formulas for both the digit selection rules and the
                 number of bits required to perform correct
                 selections.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Muller-Olm:2007:AMA
author: Markus Muller-Olm and Helmut Seidl
title: Analysis of modular arithmetic
journal: j-TOPLAS
volume: 29
number: 5
pages: 29:1--29:27
month: aug
monthnumber: 8
year: 2007
CODEN: ATPSDT
DOI: https://doi.org/10.1145/1275497.1275504
ISSN: 0164-0925 (print), 1558-4593 (electronic) OR 01640925 (print), 15584593 (electronic)
ISSNL: 0164-0925 OR 01640925
bibdate: Wed Jun 11 19:22:40 MDT 2008
bibtimestamp: 2008.06.11 19:22:40 MDT
fjournal: ACM Transactions on Programming Languages and Systems
acknowledgement: ack-nhfb
articleno: 29
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J783
rawauthor: Markus M{\"u}ller-Olm and Helmut Seidl
rawtitle: Analysis of modular arithmetic
bibsource:
http://www.acm.org/pubs/contents/journals/toplas/; https://www.math.utah.edu/pub/tex/bib/fparith.bib

abstract:
We consider integer arithmetic modulo a power of 2 as provided by mainstream programming languages like Java or standard implementations of C. The difficulty here is that, for $ w > 1 $, the ring $ Z_m $ of integers modulo $ m = 2^w $ has zero divisors and thus cannot be embedded into a field. Not withstanding that, we present intra- and interprocedural algorithms for inferring for every program point u affine relations between program variables valid at $u$. If conditional branching is replaced with nondeterministic branching, our algorithms are not only sound but also complete in that they detect all valid affine relations in a natural class of programs. Moreover, they run in time linear in the program size and polynomial in the number of program variables and can be implemented by using the same modular integer arithmetic as the target language to be analyzed. We also indicate how our analysis can be extended to deal with equality guards, even in an interprocedural setting.

rawabstract:
We consider integer arithmetic modulo a power of 2 as provided by mainstream programming languages like Java or standard implementations of C. The difficulty here is that, for $ w > 1 $, the ring $ Z_m $ of integers modulo $ m = 2^w $ has zero divisors and thus cannot be embedded into a field. Not withstanding that, we present intra- and interprocedural algorithms for inferring for every program point u affine relations between program variables valid at $u$. If conditional branching is replaced with nondeterministic branching, our algorithms are not only sound but also complete in that they detect all valid affine relations in a natural class of programs. Moreover, they run in time linear in the program size and polynomial in the number of program variables and can be implemented by using the same modular integer arithmetic as the target language to be analyzed. We also indicate how our analysis can be extended to deal with equality guards, even in an interprocedural setting.

entry:
@Article{Muller-Olm:2007:AMA,
  author =       "Markus M{\"u}ller-Olm and Helmut Seidl",
  title =        "Analysis of modular arithmetic",
  journal =      j-TOPLAS,
  volume =       "29",
  number =       "5",
  pages =        "29:1--29:27",
  month =        aug,
  year =         "2007",
  CODEN =        "ATPSDT",
  DOI =          "https://doi.org/10.1145/1275497.1275504",
  ISSN =         "0164-0925 (print), 1558-4593 (electronic)",
  ISSN-L =       "0164-0925",
  bibdate =      "Wed Jun 11 19:22:40 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toplas/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We consider integer arithmetic modulo a power of 2 as
                 provided by mainstream programming languages like Java
                 or standard implementations of C. The difficulty here
                 is that, for $ w > 1 $, the ring $ Z_m $ of integers
                 modulo $ m = 2^w $ has zero divisors and thus cannot be
                 embedded into a field. Not withstanding that, we
                 present intra- and interprocedural algorithms for
                 inferring for every program point u affine relations
                 between program variables valid at $u$. If conditional
                 branching is replaced with nondeterministic branching,
                 our algorithms are not only sound but also complete in
                 that they detect all valid affine relations in a
                 natural class of programs. Moreover, they run in time
                 linear in the program size and polynomial in the number
                 of program variables and can be implemented by using
                 the same modular integer arithmetic as the target
                 language to be analyzed. We also indicate how our
                 analysis can be extended to deal with equality guards,
                 even in an interprocedural setting.",
  acknowledgement = ack-nhfb,
  articleno =    "29",
  fjournal =     "ACM Transactions on Programming Languages and
                 Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J783",
}


bibtype: article
filename: fparith.bib
label: Nikmehr:2007:FRF
author: Hooman Nikmehr and Braden Phillips and Cheng-Chew Lim
title: A Fast Radix-4 Floating-Point Divider with Quotient Digit Selection by Comparison Multiples
journal: j-COMP-J
volume: 50
number: 1
pages: 81--92
month: jan
monthnumber: 1
year: 2007
CODEN: CMPJA6
DOI: https://doi.org/10.1093/comjnl/bxl048
ISSN: 0010-4620 (print), 1460-2067 (electronic) OR 00104620 (print), 14602067 (electronic)
ISSNL: 0010-4620 OR 00104620
bibdate: Wed Apr 28 14:33:32 MDT 2010
bibtimestamp: 2010.04.28 14:33:32 MDT
fjournal: The Computer Journal
acknowledgement: ack-nhfb
journalURL: http://comjnl.oxfordjournals.org/
rawauthor: Hooman Nikmehr and Braden Phillips and Cheng-Chew Lim
rawtitle: A Fast Radix-4 Floating-Point Divider with Quotient Digit Selection by Comparison Multiples
bibsource:
http://comjnl.oxfordjournals.org/content/vol50/issue1/index.dtl; https://www.math.utah.edu/pub/tex/bib/fparith.bib

URL:
http://comjnl.oxfordjournals.org/cgi/content/abstract/50/1/81; http://comjnl.oxfordjournals.org/cgi/content/full/50/1/81; http://comjnl.oxfordjournals.org/cgi/reprint/50/1/81

entry:
@Article{Nikmehr:2007:FRF,
  author =       "Hooman Nikmehr and Braden Phillips and Cheng-Chew
                 Lim",
  title =        "A Fast Radix-4 Floating-Point Divider with Quotient
                 Digit Selection by Comparison Multiples",
  journal =      j-COMP-J,
  volume =       "50",
  number =       "1",
  pages =        "81--92",
  month =        jan,
  year =         "2007",
  CODEN =        "CMPJA6",
  DOI =          "https://doi.org/10.1093/comjnl/bxl048",
  ISSN =         "0010-4620 (print), 1460-2067 (electronic)",
  ISSN-L =       "0010-4620",
  bibdate =      "Wed Apr 28 14:33:32 MDT 2010",
  bibsource =    "http://comjnl.oxfordjournals.org/content/vol50/issue1/index.dtl;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://comjnl.oxfordjournals.org/cgi/content/abstract/50/1/81;
                 http://comjnl.oxfordjournals.org/cgi/content/full/50/1/81;
                 http://comjnl.oxfordjournals.org/cgi/reprint/50/1/81",
  acknowledgement = ack-nhfb,
  fjournal =     "The Computer Journal",
  journal-URL =  "http://comjnl.oxfordjournals.org/",
}


bibtype: inproceedings
filename: fparith.bib
label: Osborne:2007:AAG
author: W. Osborne and R. Cheung and J. Coutinho and W. Luk and O. Mencer
title: Automatic accuracy-guaranteed bit-width optimization for fixed and floating-point systems
crossref: Bertels:2007:PIC
pages: 617--620
year: 2007
bibdate: Thu Mar 24 20:53:04 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.03.24 20:53:04 ???
URL: http://ieeexplore.ieee.org/servlet/opac?punumber=4380601
acknowledgement: ack-nhfb
rawauthor: W. Osborne and R. Cheung and J. Coutinho and W. Luk and O. Mencer
rawtitle: Automatic accuracy-guaranteed bit-width optimization for fixed and floating-point systems
entry:
@InProceedings{Osborne:2007:AAG,
  author =       "W. Osborne and R. Cheung and J. Coutinho and W. Luk
                 and O. Mencer",
  title =        "Automatic accuracy-guaranteed bit-width optimization
                 for fixed and floating-point systems",
  crossref =     "Bertels:2007:PIC",
  pages =        "617--620",
  year =         "2007",
  bibdate =      "Thu Mar 24 20:53:04 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/servlet/opac?punumber=4380601",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Pan:2007:EFS
author: V. Y. Pan and B. Murphy and G. Qian and R. E. Rosholt
title: Error-free summations via floating-point operations
type: Report
number: 2007010 and 2007013
institution: CUNY Ph.D. Program in Computer Science, Graduate Center, City University of New York
address: New York, NY, USA
pages: 617--620
year: 2007
bibdate: Mon Mar 06 17:24:08 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.03.06 17:24:08 ???
acknowledgement: ack-nhfb
rawauthor: V. Y. Pan and B. Murphy and G. Qian and R. E. Rosholt
rawtitle: Error-free summations via floating-point operations
entry:
@TechReport{Pan:2007:EFS,
  author =       "V. Y. Pan and B. Murphy and G. Qian and R. E.
                 Rosholt",
  title =        "Error-free summations via floating-point operations",
  type =         "Report",
  number =       "2007010 and 2007013",
  institution =  "CUNY Ph.D. Program in Computer Science, Graduate
                 Center, City University of New York",
  address =      "New York, NY, USA",
  year =         "2007",
  bibdate =      "Mon Mar 06 17:24:08 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Pan:2007:SAS
author: V. Y. Pan and B. Murphy and R. E. Rosholt and M. Tabanjeh
editor: Jan Verschelde and Stephen M. Watt
title: The Schur aggregation for solving linear systems of equations
publisher: pub-ACM
address: pub-ACM:adr
pages: 142--151
year: 2007
DOI: https://doi.org/10.1145/1277500.1277522
ISBN: 1-59593-744-7 (paperback) OR 1595937447 (paperback)
ISBN13: 978-1-59593-744-5 (paperback) OR 9781595937445 (paperback)
LCCN: QA9.59 .S53 2007
bibdate: Mon Mar 06 17:26:18 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; z3950.loc.gov:7090/Voyager
bibtimestamp: 2017.03.06 17:26:18 ???
acknowledgement: ack-nhfb
bookpages: viii + 299
rawauthor: V. Y. Pan and B. Murphy and R. E. Rosholt and M. Tabanjeh
raweditor: Jan Verschelde and Stephen M. Watt
rawtitle: The {Schur} aggregation for solving linear systems of equations
booktitle:
SNC'07: proceedings of the 2007 International Workshop on Symbolic--Numeric Computation, London (Ontario, Canada), July 25--27, 2007

abstract:
According to our previous theoretical and experimental study, additive preconditioners can be readily computed for ill conditioned matrices, but application of such preconditioners to facilitating matrix computations is not straight-forward. In the present paper we develop some nontrivial techniques for this task.They enabled us to confine the original numerical problems to the computation of the Schur aggregates of smaller sizes. We overcome these problems by extending the Wilkinson's iterative refinement and applying some advanced semi-symbolic algorithms for multiplication and summation.In particular with these techniques we control precision throughout our computations.

keywords:
accurate floating-point summation; Additive preconditioning; Determinants; Iterative refinement; Linear systems of equations; Sherman Morrison Woodbury formula

subject:
Computable functions; Data processing; Congresses; Numerical analysis; Logic, Symbolic and mathematical

rawabstract:
According to our previous theoretical and experimental study, additive preconditioners can be readily computed for ill conditioned matrices, but application of such preconditioners to facilitating matrix computations is not straight-forward. In the present paper we develop some nontrivial techniques for this task.They enabled us to confine the original numerical problems to the computation of the Schur aggregates of smaller sizes. We overcome these problems by extending the Wilkinson's iterative refinement and applying some advanced semi-symbolic algorithms for multiplication and summation.In particular with these techniques we control precision throughout our computations.

rawbooktitle:
{SNC'07: proceedings of the 2007 International Workshop on Symbolic--Numeric Computation, London (Ontario, Canada), July 25--27, 2007}

entry:
@InProceedings{Pan:2007:SAS,
  author =       "V. Y. Pan and B. Murphy and R. E. Rosholt and M.
                 Tabanjeh",
  editor =       "Jan Verschelde and Stephen M. Watt",
  booktitle =    "{SNC'07: proceedings of the 2007 International
                 Workshop on Symbolic--Numeric Computation, London
                 (Ontario, Canada), July 25--27, 2007}",
  title =        "The {Schur} aggregation for solving linear systems of
                 equations",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  bookpages =    "viii + 299",
  pages =        "142--151",
  year =         "2007",
  DOI =          "https://doi.org/10.1145/1277500.1277522",
  ISBN =         "1-59593-744-7 (paperback)",
  ISBN-13 =      "978-1-59593-744-5 (paperback)",
  LCCN =         "QA9.59 .S53 2007",
  bibdate =      "Mon Mar 06 17:26:18 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 z3950.loc.gov:7090/Voyager",
  abstract =     "According to our previous theoretical and experimental
                 study, additive preconditioners can be readily computed
                 for ill conditioned matrices, but application of such
                 preconditioners to facilitating matrix computations is
                 not straight-forward. In the present paper we develop
                 some nontrivial techniques for this task.They enabled
                 us to confine the original numerical problems to the
                 computation of the Schur aggregates of smaller sizes.
                 We overcome these problems by extending the Wilkinson's
                 iterative refinement and applying some advanced
                 semi-symbolic algorithms for multiplication and
                 summation.In particular with these techniques we
                 control precision throughout our computations.",
  acknowledgement = ack-nhfb,
  keywords =     "accurate floating-point summation; Additive
                 preconditioning; Determinants; Iterative refinement;
                 Linear systems of equations; Sherman Morrison Woodbury
                 formula",
  subject =      "Computable functions; Data processing; Congresses;
                 Numerical analysis; Logic, Symbolic and mathematical",
}


bibtype: article
filename: fparith.bib
label: Patel:2007:FMA
author: R. A. Patel and M. Benaissa and S. Boussakta
title: Fast Modulo $ 2^n - (2^n - 2 + 1) $ Addition: a New Class of Adder for RNS
journal: j-IEEE-TRANS-COMPUT
volume: 56
number: 4
pages: 572--576
month: apr
monthnumber: 4
year: 2007
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.1001
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:03:38 MDT 2011
bibtimestamp: 2011.07.04 15:03:38 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4118680
fjournal: IEEE Transactions on Computers
keywords: residue number system (RNS)
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: R. A. Patel and M. Benaissa and S. Boussakta
rawtitle: Fast Modulo $ 2^n - (2^{n - 2} + 1) $ Addition: a New Class of Adder for {RNS}
entry:
@Article{Patel:2007:FMA,
  author =       "R. A. Patel and M. Benaissa and S. Boussakta",
  title =        "Fast Modulo $ 2^n - (2^{n - 2} + 1) $ Addition: a New
                 Class of Adder for {RNS}",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "56",
  number =       "4",
  pages =        "572--576",
  month =        apr,
  year =         "2007",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.1001",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:03:38 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4118680",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "residue number system (RNS)",
}


bibtype: inproceedings
filename: fparith.bib
label: Patil:2007:REE
author: Dinesh Patil and Omid Azizi and Mark Horowitz and Ron Ho and Rajesh Ananthraman
title: Robust Energy-Efficient Adder Topologies
crossref: Kornerup:2007:PIS
pages: 16--28
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.31
bibdate: Tue Oct 9 16:32:41 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 16:32:41 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Dinesh Patil and Omid Azizi and Mark Horowitz and Ron Ho and Rajesh Ananthraman
rawtitle: Robust Energy-Efficient Adder Topologies
abstract:
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determine how architectural features and design techniques affect energy efficiency. Optimizing different adders for the supply and threshold voltages, and transistor sizing, we show that topologies with the least number of logic stages having an average fanin of two per stage, and fewest wires are most energy efficient. While a design with fully custom sizes can be extremely tedious to layout, we show that custom sizing can be used as a guide to group different gates in the design, resulting in a manageable layout overhead without significant loss of energy efficiency.

rawabstract:
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determine how architectural features and design techniques affect energy efficiency. Optimizing different adders for the supply and threshold voltages, and transistor sizing, we show that topologies with the least number of logic stages having an average fanin of two per stage, and fewest wires are most energy efficient. While a design with fully custom sizes can be extremely tedious to layout, we show that custom sizing can be used as a guide to group different gates in the design, resulting in a manageable layout overhead without significant loss of energy efficiency.

entry:
@InProceedings{Patil:2007:REE,
  author =       "Dinesh Patil and Omid Azizi and Mark Horowitz and Ron
                 Ho and Rajesh Ananthraman",
  title =        "Robust Energy-Efficient Adder Topologies",
  crossref =     "Kornerup:2007:PIS",
  pages =        "16--28",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.31",
  bibdate =      "Tue Oct 9 16:32:41 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In this paper we explore the relationship between
                 adder topology and energy efficiency. We compare the
                 energy-delay tradeoff curves of selected 32-bit adder
                 topologies, to determine how architectural features and
                 design techniques affect energy efficiency. Optimizing
                 different adders for the supply and threshold voltages,
                 and transistor sizing, we show that topologies with the
                 least number of logic stages having an average fanin of
                 two per stage, and fewest wires are most energy
                 efficient. While a design with fully custom sizes can
                 be extremely tedious to layout, we show that custom
                 sizing can be used as a guide to group different gates
                 in the design, resulting in a manageable layout
                 overhead without significant loss of energy
                 efficiency.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: article
filename: fparith.bib
label: Pearce:2007:MLH
author: Roman Pearce and Michael Monagan
title: A Maple library for high performance sparse polynomial arithmetic
journal: j-ACM-COMM-COMP-ALGEBRA
volume: 41
number: 3
pages: 110--111
month: sep
monthnumber: 9
year: 2007
DOI: https://doi.org/10.1145/1358190.1358203
ISSN: 1932-2232 (print), 1932-2240 (electronic) OR 19322232 (print), 19322240 (electronic)
ISSNL: 1932-2232 OR 19322232
bibdate: Wed Jun 18 09:23:01 MDT 2008
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.06.18 09:23:01 MDT
fjournal: ACM Communications in Computer Algebra
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J1000
issue: 161
rawauthor: Roman Pearce and Michael Monagan
rawtitle: A {Maple} library for high performance sparse polynomial arithmetic
abstract:
We have developed a library for sparse polynomial arithmetic to supplement Maple's internal routines. Along the way we identified three common sources of inefficiency in existing implementations.

rawabstract:
We have developed a library for sparse polynomial arithmetic to supplement Maple's internal routines. Along the way we identified three common sources of inefficiency in existing implementations.

entry:
@Article{Pearce:2007:MLH,
  author =       "Roman Pearce and Michael Monagan",
  title =        "A {Maple} library for high performance sparse
                 polynomial arithmetic",
  journal =      j-ACM-COMM-COMP-ALGEBRA,
  volume =       "41",
  number =       "3",
  pages =        "110--111",
  month =        sep,
  year =         "2007",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/1358190.1358203",
  ISSN =         "1932-2232 (print), 1932-2240 (electronic)",
  ISSN-L =       "1932-2232",
  bibdate =      "Wed Jun 18 09:23:01 MDT 2008",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We have developed a library for sparse polynomial
                 arithmetic to supplement Maple's internal routines.
                 Along the way we identified three common sources of
                 inefficiency in existing implementations.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Communications in Computer Algebra",
  issue =        "161",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J1000",
}


bibtype: article
filename: fparith.bib
label: Rauh:2007:ROI
author: Andreas Rauh and Marco Kletting and Harald Aschemann and Eberhard P. Hofer
journal: j-J-COMPUT-APPL-MATH
volume: 199
number: 2
pages: 207--212
day: 15
month: feb
monthnumber: 2
year: 2007
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:12:04 MST 2017
bibtimestamp: 2017.02.25 13:12:04 MST
URL: http://www.sciencedirect.com/science/article/pii/S0377042705007521
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Andreas Rauh and Marco Kletting and Harald Aschemann and Eberhard P. Hofer
title:
Reduction of overestimation in interval arithmetic simulation of biological wastewater treatment processes

rawtitle:
Reduction of overestimation in interval arithmetic simulation of biological wastewater treatment processes

entry:
@Article{Rauh:2007:ROI,
  author =       "Andreas Rauh and Marco Kletting and Harald Aschemann
                 and Eberhard P. Hofer",
  title =        "Reduction of overestimation in interval arithmetic
                 simulation of biological wastewater treatment
                 processes",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "199",
  number =       "2",
  pages =        "207--212",
  day =          "15",
  month =        feb,
  year =         "2007",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:12:04 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2005.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042705007521",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: inproceedings
filename: fparith.bib
label: Saldamli:2007:SME
author: Gokay Saldamli and Cetin K. Koc
title: Spectral Modular Exponentiation
crossref: Kornerup:2007:PIS
pages: 123--132
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.34
bibdate: Tue Oct 9 16:32:41 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 16:32:41 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Gokay Saldamli and Cetin K. Koc
rawtitle: Spectral Modular Exponentiation
abstract:
We describe a new method to perform the modular exponentiation operation, i.e., the computation of $ c = m e bmod n $, where $c$, $m$, $e$ and $n$ are large integers. The new method uses the discrete Fourier transform over a finite ring, and relies on new techniques to perform multiplication and reduction operations. The method yields efficient and highly parallel architectures for hardware realizations of public-key cryptosystems requiring the modular exponentiation as the core computation, such as the RSA and Diffie--Hellman algorithms.

rawabstract:
We describe a new method to perform the modular exponentiation operation, i.e., the computation of $ c = m e \bmod n $, where $c$, $m$, $e$ and $n$ are large integers. The new method uses the discrete Fourier transform over a finite ring, and relies on new techniques to perform multiplication and reduction operations. The method yields efficient and highly parallel architectures for hardware realizations of public-key cryptosystems requiring the modular exponentiation as the core computation, such as the RSA and Diffie--Hellman algorithms.

entry:
@InProceedings{Saldamli:2007:SME,
  author =       "Gokay Saldamli and Cetin K. Koc",
  title =        "Spectral Modular Exponentiation",
  crossref =     "Kornerup:2007:PIS",
  pages =        "123--132",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.34",
  bibdate =      "Tue Oct 9 16:32:41 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "We describe a new method to perform the modular
                 exponentiation operation, i.e., the computation of $ c
                 = m e \bmod n $, where $c$, $m$, $e$ and $n$ are large
                 integers. The new method uses the discrete Fourier
                 transform over a finite ring, and relies on new
                 techniques to perform multiplication and reduction
                 operations. The method yields efficient and highly
                 parallel architectures for hardware realizations of
                 public-key cryptosystems requiring the modular
                 exponentiation as the core computation, such as the RSA
                 and Diffie--Hellman algorithms.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: article
filename: fparith.bib
label: Saqib:2007:CAI
author: Nazar Abbas Saqib
title: Complexity Analysis for 4-Input / 1-Output FPGAs Applied to Multiplier Designs
journal: j-SCPE
volume: 8
number: 4
pages: 411--422
month: dec
monthnumber: 12
year: 2007
ISSN: 1895-1767 OR 18951767
bibdate: Thu Sep 2 11:55:11 MDT 2010
bibsource: http://www.scpe.org/content/8/4.toc; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.09.02 11:55:11 MDT
acknowledgement: ack-nhfb
journalURL: http://www.scpe.org/
rawauthor: Nazar Abbas Saqib
rawtitle: Complexity Analysis for 4-Input\slash 1-Output {FPGAs} Applied to Multiplier Designs
URL:
http://www.scpe.org/vols/vol08/no4/SCPE_8_4_07.pdf; http://www.scpe.org/vols/vol08/no4/SCPE_8_4_07.zip

entry:
@Article{Saqib:2007:CAI,
  author =       "Nazar Abbas Saqib",
  title =        "Complexity Analysis for 4-Input\slash 1-Output {FPGAs}
                 Applied to Multiplier Designs",
  journal =      j-SCPE,
  volume =       "8",
  number =       "4",
  pages =        "411--422",
  month =        dec,
  year =         "2007",
  CODEN =        "????",
  ISSN =         "1895-1767",
  bibdate =      "Thu Sep 2 11:55:11 MDT 2010",
  bibsource =    "http://www.scpe.org/content/8/4.toc;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.scpe.org/vols/vol08/no4/SCPE_8_4_07.pdf;
                 http://www.scpe.org/vols/vol08/no4/SCPE_8_4_07.zip",
  acknowledgement = ack-nhfb,
  journal-URL =  "http://www.scpe.org/",
}


bibtype: inproceedings
filename: fparith.bib
label: Schulte:2007:FPD
author: M. J. Schulte and D. Tan and C. E. Lemonds
editor: IEEE
booktitle: Proceedings of the 25th IEEE International Conference on Computer Design: 7--10 October 2007
title: Floating-Point Division Algorithms for an x86 Microprocessor with a Rectangular Multiplier
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 304--310
year: 2007
DOI: https://doi.org/10.1109/ICCD.2007.4601917
bibdate: Sun Dec 10 14:03:42 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.10 14:03:42 ???
acknowledgement: ack-nhfb
rawauthor: M. J. Schulte and D. Tan and C. E. Lemonds
rawbooktitle: Proceedings of the 25th {IEEE} International Conference on Computer Design: {7--10 October 2007}
raweditor: {IEEE}
rawtitle: Floating-Point Division Algorithms for an x86 Microprocessor with a Rectangular Multiplier
abstract:
Floating-point division is an important operation in scientific computing and multimedia applications. This paper presents and compares two division algorithms for an x86 microprocessor, which utilizes a rectangular multiplier that is optimized for multimedia applications. The proposed division algorithms are based on Goldschmidt's division algorithm and provide correctly rounded results for IEEE 754 single, double, and extended precision floating-point numbers. Compared to a previous Goldschmidt division algorithm, the fastest proposed algorithm requires 25% to 37% fewer cycles, while utilizing a multiplier that is roughly 2.5 times smaller.

rawabstract:
Floating-point division is an important operation in scientific computing and multimedia applications. This paper presents and compares two division algorithms for an x86 microprocessor, which utilizes a rectangular multiplier that is optimized for multimedia applications. The proposed division algorithms are based on Goldschmidt's division algorithm and provide correctly rounded results for IEEE 754 single, double, and extended precision floating-point numbers. Compared to a previous Goldschmidt division algorithm, the fastest proposed algorithm requires 25\% to 37\% fewer cycles, while utilizing a multiplier that is roughly 2.5 times smaller.

entry:
@InProceedings{Schulte:2007:FPD,
  author =       "M. J. Schulte and D. Tan and C. E. Lemonds",
  editor =       "{IEEE}",
  booktitle =    "Proceedings of the 25th {IEEE} International
                 Conference on Computer Design: {7--10 October 2007}",
  title =        "Floating-Point Division Algorithms for an x86
                 Microprocessor with a Rectangular Multiplier",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "304--310",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ICCD.2007.4601917",
  bibdate =      "Sun Dec 10 14:03:42 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Floating-point division is an important operation in
                 scientific computing and multimedia applications. This
                 paper presents and compares two division algorithms for
                 an x86 microprocessor, which utilizes a rectangular
                 multiplier that is optimized for multimedia
                 applications. The proposed division algorithms are
                 based on Goldschmidt's division algorithm and provide
                 correctly rounded results for IEEE 754 single, double,
                 and extended precision floating-point numbers. Compared
                 to a previous Goldschmidt division algorithm, the
                 fastest proposed algorithm requires 25\% to 37\% fewer
                 cycles, while utilizing a multiplier that is roughly
                 2.5 times smaller.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Scott:2007:NHC
author: N. S. Scott and F. Jezequel and C. Denis and J.-M. Chesneaux
title: Numerical `health check' for scientific codes: the CADNA approach
journal: j-COMP-PHYS-COMM
volume: 176
number: 8
pages: 507--521
day: 15
month: apr
monthnumber: 4
year: 2007
CODEN: CPHCBZ
DOI: https://doi.org/10.1016/j.cpc.2007.01.005
ISSN: 0010-4655 (print), 1879-2944 (electronic) OR 00104655 (print), 18792944 (electronic)
ISSNL: 0010-4655 OR 00104655
bibdate: Mon Feb 13 23:42:15 MST 2012
bibtimestamp: 2012.02.13 23:42:15 MST
URL: http://www.sciencedirect.com/science/article/pii/S0010465507000331
fjournal: Computer Physics Communications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00104655
rawauthor: N. S. Scott and F. J{\'e}z{\'e}quel and C. Denis and J.-M. Chesneaux
rawtitle: Numerical `health check' for scientific codes: the {CADNA} approach
bibsource:
https://www.math.utah.edu/pub/tex/bib/compphyscomm2000.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Scott:2007:NHC,
  author =       "N. S. Scott and F. J{\'e}z{\'e}quel and C. Denis and
                 J.-M. Chesneaux",
  title =        "Numerical `health check' for scientific codes: the
                 {CADNA} approach",
  journal =      j-COMP-PHYS-COMM,
  volume =       "176",
  number =       "8",
  pages =        "507--521",
  day =          "15",
  month =        apr,
  year =         "2007",
  CODEN =        "CPHCBZ",
  DOI =          "https://doi.org/10.1016/j.cpc.2007.01.005",
  ISSN =         "0010-4655 (print), 1879-2944 (electronic)",
  ISSN-L =       "0010-4655",
  bibdate =      "Mon Feb 13 23:42:15 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compphyscomm2000.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0010465507000331",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Physics Communications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00104655",
}


bibtype: inproceedings
filename: fparith.bib
label: Shams:2007:EHA
author: R. Shams and R. Kennedy
title: Efficient histogram algorithms for NVIDIA CUDA compatible devices
pages: 418--422
year: 2007
bibdate: Sat Oct 31 07:03:20 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.10.31 07:03:20 ???
acknowledgement: ack-nhfb
rawauthor: R. Shams and R. Kennedy
rawtitle: Efficient histogram algorithms for {NVIDIA CUDA} compatible devices
booktitle:
Proceedings of the International Conference on Signal Processing and Communications Systems (ICSPCS), Gold Coast, Australia, 2007

rawbooktitle:
{Proceedings of the International Conference on Signal Processing and Communications Systems (ICSPCS), Gold Coast, Australia, 2007}

entry:
@InProceedings{Shams:2007:EHA,
  author =       "R. Shams and R. Kennedy",
  editor =       "????",
  booktitle =    "{Proceedings of the International Conference on Signal
                 Processing and Communications Systems (ICSPCS), Gold
                 Coast, Australia, 2007}",
  title =        "Efficient histogram algorithms for {NVIDIA CUDA}
                 compatible devices",
  publisher =    "????",
  address =      "????",
  pages =        "418--422",
  year =         "2007",
  bibdate =      "Sat Oct 31 07:03:20 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Shpilka:2007:IDA
author: Amir Shpilka
title: Interpolation of depth-3 arithmetic circuits with two multiplication gates
crossref: ACM:2007:SPA
pages: 284--293
year: 2007
DOI: https://doi.org/10.1145/1250790.1250833
bibdate: Fri Jun 20 18:28:53 MDT 2008
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.06.20 18:28:53 MDT
keywords: arithmetic circuits; depth-3; exact learning; interpolation
acknowledgement: ack-nhfb
rawauthor: Amir Shpilka
rawtitle: Interpolation of depth-3 arithmetic circuits with two multiplication gates
entry:
@InProceedings{Shpilka:2007:IDA,
  author =       "Amir Shpilka",
  title =        "Interpolation of depth-3 arithmetic circuits with two
                 multiplication gates",
  crossref =     "ACM:2007:SPA",
  pages =        "284--293",
  year =         "2007",
  DOI =          "https://doi.org/10.1145/1250790.1250833",
  bibdate =      "Fri Jun 20 18:28:53 MDT 2008",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "arithmetic circuits; depth-3; exact learning;
                 interpolation",
}


bibtype: inproceedings
filename: fparith.bib
label: Sousa:2007:EMM
author: Leonel Sousa
title: Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli
crossref: Kornerup:2007:PIS
pages: 240--250
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.16
bibdate: Tue Oct 9 17:16:03 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 17:16:03 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Leonel Sousa
rawtitle: Efficient Method for Magnitude Comparison in {RNS} Based on Two Pairs of Conjugate Moduli
abstract:
The non-positional nature of Residue Number Systems (RNS) is very useful to achieve carry free arithmetic. However it makes the comparison of numbers more difficult than in the traditional weighted number systems: there is no any efficient general method for magnitude comparison in RNS. Moreover, magnitude comparison for RNS that rely on pairs of conjugate moduli, which are not relatively prime moduli sets recently proposed because of the large dynamic ranges and the simplicity of the arithmetic units, is a new unsolved problem. In this paper an efficient method and a VLSI architecture is proposed for magnitude comparison in RNS based on sets formed by two pairs of conjugate moduli. This proposed method is much more efficient than the other known ones and is the only one valid for moduli sets not formed by relatively prime integers. The method has been applied to design a very fast Sum-of-Absolute Differences (SAD) unit for motion estimation in video sequences that performs the function entirely within the RNS channels. Experimental results show that this new SAD unit, implemented in the internal memory blocks of the xc2vp50-7 FPGA, is capable of achieving the high throughput required to perform real-time motion estimation in high resolution images.

rawabstract:
The non-positional nature of Residue Number Systems (RNS) is very useful to achieve carry free arithmetic. However it makes the comparison of numbers more difficult than in the traditional weighted number systems: there is no any efficient general method for magnitude comparison in RNS. Moreover, magnitude comparison for RNS that rely on pairs of conjugate moduli, which are not relatively prime moduli sets recently proposed because of the large dynamic ranges and the simplicity of the arithmetic units, is a new unsolved problem. In this paper an efficient method and a VLSI architecture is proposed for magnitude comparison in RNS based on sets formed by two pairs of conjugate moduli. This proposed method is much more efficient than the other known ones and is the only one valid for moduli sets not formed by relatively prime integers. The method has been applied to design a very fast Sum-of-Absolute Differences (SAD) unit for motion estimation in video sequences that performs the function entirely within the RNS channels. Experimental results show that this new SAD unit, implemented in the internal memory blocks of the xc2vp50-7 FPGA, is capable of achieving the high throughput required to perform real-time motion estimation in high resolution images.

entry:
@InProceedings{Sousa:2007:EMM,
  author =       "Leonel Sousa",
  title =        "Efficient Method for Magnitude Comparison in {RNS}
                 Based on Two Pairs of Conjugate Moduli",
  crossref =     "Kornerup:2007:PIS",
  pages =        "240--250",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.16",
  bibdate =      "Tue Oct 9 17:16:03 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The non-positional nature of Residue Number Systems
                 (RNS) is very useful to achieve carry free arithmetic.
                 However it makes the comparison of numbers more
                 difficult than in the traditional weighted number
                 systems: there is no any efficient general method for
                 magnitude comparison in RNS. Moreover, magnitude
                 comparison for RNS that rely on pairs of conjugate
                 moduli, which are not relatively prime moduli sets
                 recently proposed because of the large dynamic ranges
                 and the simplicity of the arithmetic units, is a new
                 unsolved problem. In this paper an efficient method and
                 a VLSI architecture is proposed for magnitude
                 comparison in RNS based on sets formed by two pairs of
                 conjugate moduli. This proposed method is much more
                 efficient than the other known ones and is the only one
                 valid for moduli sets not formed by relatively prime
                 integers. The method has been applied to design a very
                 fast Sum-of-Absolute Differences (SAD) unit for motion
                 estimation in video sequences that performs the
                 function entirely within the RNS channels. Experimental
                 results show that this new SAD unit, implemented in the
                 internal memory blocks of the xc2vp50-7 FPGA, is
                 capable of achieving the high throughput required to
                 perform real-time motion estimation in high resolution
                 images.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: misc
filename: fparith.bib
label: Steele:2007:CSP
author: Guy L. Steele Jr.
title: Circuit for selectively providing maximum or minimum of a pair of floating point operands
pages: 240--250
day: 05
month: jun
monthnumber: 6
year: 2007
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/7228324/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 7228324
rawauthor: Guy L. {Steele Jr.}
rawtitle: Circuit for selectively providing maximum or minimum of a pair of floating point operands
abstract:
A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point tatus information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal, and a result assembler circuit, coupled to the decision circuit, for producing a result indicating which of the first floating point operand and the second floating point operand meet the threshold condition, based on the at least one assembly control signal. The format of the floating point operands may be from a group comprising: not-a-number (NaN), positive infinity, negative infinity, normalized, denormalized, positive overflow, negative overflow, positive underflow, negative underflow, inexact, exact, division by zero, invalid operation, positive zero, and negative zero. The result produced may be a third floating point operand having encoded floating point status information, and at least part of the encoded floating point status information in the result may come from either the first floating point operand or the second floating point operand.

rawabstract:
A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point tatus information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal, and a result assembler circuit, coupled to the decision circuit, for producing a result indicating which of the first floating point operand and the second floating point operand meet the threshold condition, based on the at least one assembly control signal. The format of the floating point operands may be from a group comprising: not-a-number (NaN), positive infinity, negative infinity, normalized, denormalized, positive overflow, negative overflow, positive underflow, negative underflow, inexact, exact, division by zero, invalid operation, positive zero, and negative zero. The result produced may be a third floating point operand having encoded floating point status information, and at least part of the encoded floating point status information in the result may come from either the first floating point operand or the second floating point operand.

entry:
@Misc{Steele:2007:CSP,
  author =       "Guy L. {Steele Jr.}",
  title =        "Circuit for selectively providing maximum or minimum
                 of a pair of floating point operands",
  howpublished = "US Patent 7228324",
  day =          "05",
  month =        jun,
  year =         "2007",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7228324/fulltext.html",
  abstract =     "A floating point max/min circuit for determining the
                 maximum or minimum of two floating point operands
                 includes a first analysis circuit configured to
                 determine a format of a first floating point operand of
                 the two floating point operands based upon floating
                 point tatus information encoded within the first
                 floating point operand, a second analysis circuit
                 configured to determine a format of a second floating
                 point operand of the two floating point operands based
                 upon floating point status information encoded within
                 the second floating point operand, a decision circuit,
                 coupled to the first analysis circuit and to the second
                 analysis circuit and responding to a function control
                 signal that indicates the threshold condition is one of
                 a maximum of the two floating point operands and a
                 minimum of the two floating point operands, for
                 generating at least one assembly control signal based
                 on the format of a first floating point operand, the
                 format of a second floating point operand, and the
                 function control signal, and a result assembler
                 circuit, coupled to the decision circuit, for producing
                 a result indicating which of the first floating point
                 operand and the second floating point operand meet the
                 threshold condition, based on the at least one assembly
                 control signal. The format of the floating point
                 operands may be from a group comprising: not-a-number
                 (NaN), positive infinity, negative infinity,
                 normalized, denormalized, positive overflow, negative
                 overflow, positive underflow, negative underflow,
                 inexact, exact, division by zero, invalid operation,
                 positive zero, and negative zero. The result produced
                 may be a third floating point operand having encoded
                 floating point status information, and at least part of
                 the encoded floating point status information in the
                 result may come from either the first floating point
                 operand or the second floating point operand.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Steele:2007:CUC
author: Guy L. Steele Jr.
title: Comparator unit for comparing values of floating point operands
pages: 240--250
day: 13
month: mar
monthnumber: 3
year: 2007
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/7191202/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 7191202
rawauthor: Guy L. {Steele Jr.}
rawtitle: Comparator unit for comparing values of floating point operands
abstract:
A floating point comparator circuit for comparing a plurality of floating point operands includes a plurality of analysis circuits, one for each of the floating point operands, configured to determine a format of each of the floating point operands based upon floating point status information encoded within each of the floating point operands, and a result generator circuit coupled to the analysis circuits, the result generator circuit configured to generate a result signal based on the format determined by each analysis circuit and based on a comparative relationship among the floating point operands. The format of each of the floating point operands may be from a group including: not-a-number (NaN), infinity, normalized, denormalized, zero, invalid operation, overflow, underflow, division by zero, exact, and inexact. The result generator circuit may ignore the encoded floating point statuses of the plurality of floating point operands when comparing just the magnitudes of the plurality of floating point operands.

rawabstract:
A floating point comparator circuit for comparing a plurality of floating point operands includes a plurality of analysis circuits, one for each of the floating point operands, configured to determine a format of each of the floating point operands based upon floating point status information encoded within each of the floating point operands, and a result generator circuit coupled to the analysis circuits, the result generator circuit configured to generate a result signal based on the format determined by each analysis circuit and based on a comparative relationship among the floating point operands. The format of each of the floating point operands may be from a group including: not-a-number (NaN), infinity, normalized, denormalized, zero, invalid operation, overflow, underflow, division by zero, exact, and inexact. The result generator circuit may ignore the encoded floating point statuses of the plurality of floating point operands when comparing just the magnitudes of the plurality of floating point operands.

entry:
@Misc{Steele:2007:CUC,
  author =       "Guy L. {Steele Jr.}",
  title =        "Comparator unit for comparing values of floating point
                 operands",
  howpublished = "US Patent 7191202",
  day =          "13",
  month =        mar,
  year =         "2007",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7191202/fulltext.html",
  abstract =     "A floating point comparator circuit for comparing a
                 plurality of floating point operands includes a
                 plurality of analysis circuits, one for each of the
                 floating point operands, configured to determine a
                 format of each of the floating point operands based
                 upon floating point status information encoded within
                 each of the floating point operands, and a result
                 generator circuit coupled to the analysis circuits, the
                 result generator circuit configured to generate a
                 result signal based on the format determined by each
                 analysis circuit and based on a comparative
                 relationship among the floating point operands. The
                 format of each of the floating point operands may be
                 from a group including: not-a-number (NaN), infinity,
                 normalized, denormalized, zero, invalid operation,
                 overflow, underflow, division by zero, exact, and
                 inexact. The result generator circuit may ignore the
                 encoded floating point statuses of the plurality of
                 floating point operands when comparing just the
                 magnitudes of the plurality of floating point
                 operands.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Steele:2007:MSCa
author: Guy L. Steele Jr.
title: Methods and systems for computing the quotient of floating-point intervals
pages: 240--250
day: 26
month: jun
monthnumber: 6
year: 2007
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/7236999/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 7236999
rawauthor: Guy L. {Steele Jr.}
rawtitle: Methods and systems for computing the quotient of floating-point intervals
abstract:
Computing an output interval includes producing a first result from a conditional selection using a first operand, a second operand, and a third operand, the operands respectively including a second input interval upper-point, a first input interval upper-point, and a first input interval lower-point. Next, computing an output interval includes producing a second result from the conditional selection, the operands respectively including a second input interval upper-point, the first input interval upper-point, and the first input interval lower-point. Furthermore, computing an output interval includes producing a third result from a conditional division using the first operand, the second operand, and the third operand, the operands respectively including the first result, the second input interval upper-point, and the second input interval lower-point. And finally, a fourth result is produced from the conditional division, the operands respectively including the second result, the second input interval lower-point, and the second input interval upper-point.

rawabstract:
Computing an output interval includes producing a first result from a conditional selection using a first operand, a second operand, and a third operand, the operands respectively including a second input interval upper-point, a first input interval upper-point, and a first input interval lower-point. Next, computing an output interval includes producing a second result from the conditional selection, the operands respectively including a second input interval upper-point, the first input interval upper-point, and the first input interval lower-point. Furthermore, computing an output interval includes producing a third result from a conditional division using the first operand, the second operand, and the third operand, the operands respectively including the first result, the second input interval upper-point, and the second input interval lower-point. And finally, a fourth result is produced from the conditional division, the operands respectively including the second result, the second input interval lower-point, and the second input interval upper-point.

entry:
@Misc{Steele:2007:MSCa,
  author =       "Guy L. {Steele Jr.}",
  title =        "Methods and systems for computing the quotient of
                 floating-point intervals",
  howpublished = "US Patent 7236999",
  day =          "26",
  month =        jun,
  year =         "2007",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7236999/fulltext.html",
  abstract =     "Computing an output interval includes producing a
                 first result from a conditional selection using a first
                 operand, a second operand, and a third operand, the
                 operands respectively including a second input interval
                 upper-point, a first input interval upper-point, and a
                 first input interval lower-point. Next, computing an
                 output interval includes producing a second result from
                 the conditional selection, the operands respectively
                 including a second input interval upper-point, the
                 first input interval upper-point, and the first input
                 interval lower-point. Furthermore, computing an output
                 interval includes producing a third result from a
                 conditional division using the first operand, the
                 second operand, and the third operand, the operands
                 respectively including the first result, the second
                 input interval upper-point, and the second input
                 interval lower-point. And finally, a fourth result is
                 produced from the conditional division, the operands
                 respectively including the second result, the second
                 input interval lower-point, and the second input
                 interval upper-point.",
  acknowledgement = ack-nhfb,
}


bibtype: misc
filename: fparith.bib
label: Steele:2007:MSCb
author: Guy L. Steele Jr.
title: Methods and systems for computing floating-point intervals
pages: 240--250
day: 15
month: may
monthnumber: 5
year: 2007
bibdate: Tue Dec 23 15:06:47 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.12.23 15:06:47 ???
URL: http://www.patentstorm.us/patents/7219117/fulltext.html
acknowledgement: ack-nhfb
howpublished: US Patent 7219117
rawauthor: Guy L. {Steele Jr.}
rawtitle: Methods and systems for computing floating-point intervals
abstract:
Computing an output interval includes producing a first product resulting from a conditional multiplication using a first operand, a second operand, and a third operand. Next a second product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Then a third product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Next a fourth product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. And finally, the output interval is produced including an output interval lower-point and an output interval upper-point, the output interval lower-point being the minimum of the first product and the third product, and the output interval upper-point being the maximum of the second product and the fourth product.

rawabstract:
Computing an output interval includes producing a first product resulting from a conditional multiplication using a first operand, a second operand, and a third operand. Next a second product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Then a third product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Next a fourth product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. And finally, the output interval is produced including an output interval lower-point and an output interval upper-point, the output interval lower-point being the minimum of the first product and the third product, and the output interval upper-point being the maximum of the second product and the fourth product.

entry:
@Misc{Steele:2007:MSCb,
  author =       "Guy L. {Steele Jr.}",
  title =        "Methods and systems for computing floating-point
                 intervals",
  howpublished = "US Patent 7219117",
  day =          "15",
  month =        may,
  year =         "2007",
  bibdate =      "Tue Dec 23 15:06:47 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.patentstorm.us/patents/7219117/fulltext.html",
  abstract =     "Computing an output interval includes producing a
                 first product resulting from a conditional
                 multiplication using a first operand, a second operand,
                 and a third operand. Next a second product is produced
                 resulting from the conditional multiplication using the
                 first operand, the second operand, and the third
                 operand. Then a third product is produced resulting
                 from the conditional multiplication using the first
                 operand, the second operand, and the third operand.
                 Next a fourth product is produced resulting from the
                 conditional multiplication using the first operand, the
                 second operand, and the third operand. And finally, the
                 output interval is produced including an output
                 interval lower-point and an output interval
                 upper-point, the output interval lower-point being the
                 minimum of the first product and the third product, and
                 the output interval upper-point being the maximum of
                 the second product and the fourth product.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Stern:2007:MLA
author: Richard Stern
journal: j-IEEE-MICRO
volume: 27
number: 3
pages: 106--109
month: may
monthnumber: 5
year: 2007
CODEN: IEMIDZ
DOI: https://doi.org/10.1109/MM.2007.47
ISSN: 0272-1732 (print), 1937-4143 (electronic) OR 02721732 (print), 19374143 (electronic)
ISSNL: 0272-1732 OR 02721732
bibdate: Wed Jul 2 21:58:03 MDT 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.07.02 21:58:03 MDT
fjournal: IEEE Micro
acknowledgement: ack-nhfb
journalURL: http://www.computer.org/csdl/mags/mi/index.html
rawauthor: Richard Stern
title:
Micro Law: Antitrust Division Gives IEEE Standard Setters the Okay to Ask Patentees How RAND They Are

rawtitle:
Micro Law: Antitrust Division Gives {IEEE Standard} Setters the Okay to Ask Patentees How {RAND} They Are

entry:
@Article{Stern:2007:MLA,
  author =       "Richard Stern",
  title =        "Micro Law: Antitrust Division Gives {IEEE Standard}
                 Setters the Okay to Ask Patentees How {RAND} They Are",
  journal =      j-IEEE-MICRO,
  volume =       "27",
  number =       "3",
  pages =        "106--109",
  month =        may # "\slash " # jun,
  year =         "2007",
  CODEN =        "IEMIDZ",
  DOI =          "https://doi.org/10.1109/MM.2007.47",
  ISSN =         "0272-1732 (print), 1937-4143 (electronic)",
  ISSN-L =       "0272-1732",
  bibdate =      "Wed Jul 2 21:58:03 MDT 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Micro",
  journal-URL =  "http://www.computer.org/csdl/mags/mi/index.html",
}


bibtype: article
filename: fparith.bib
label: Stoutemyer:2007:UCN
author: David R. Stoutemyer
title: Useful Computations Need Useful Numbers
journal: j-ACM-COMM-COMP-ALGEBRA
volume: 41
number: 3
pages: 75--99
month: sep
monthnumber: 9
year: 2007
DOI: https://doi.org/10.1145/1358190.1358192
ISSN: 1932-2232 (print), 1932-2240 (electronic) OR 19322232 (print), 19322240 (electronic)
ISSNL: 1932-2232 OR 19322232
bibdate: Wed Jun 18 09:23:01 MDT 2008
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.06.18 09:23:01 MDT
fjournal: ACM Communications in Computer Algebra
keywords: interval arithmetic
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J1000
issue: 161
rawauthor: David R. Stoutemyer
rawtitle: Useful Computations Need Useful Numbers
abstract:
Most of us have taken the exact rational and approximate numbers in our computer algebra systems for granted for a long time, not thinking to ask if they could be significantly better. With exact rational arithmetic and adjustable-precision floating-point arithmetic to precision limited only by the total computer memory or our patience, what more could we want for such numbers? It turns out that there is much more that can be done that permits us to obtain exact results more often, more intelligible results, approximate results guaranteed to have requested error bounds, and recovery of exact results from approximate ones.

rawabstract:
Most of us have taken the exact rational and approximate numbers in our computer algebra systems for granted for a long time, not thinking to ask if they could be significantly better. With exact rational arithmetic and adjustable-precision floating-point arithmetic to precision limited only by the total computer memory or our patience, what more could we want for such numbers? It turns out that there is much more that can be done that permits us to obtain exact results more often, more intelligible results, approximate results guaranteed to have requested error bounds, and recovery of exact results from approximate ones.

entry:
@Article{Stoutemyer:2007:UCN,
  author =       "David R. Stoutemyer",
  title =        "Useful Computations Need Useful Numbers",
  journal =      j-ACM-COMM-COMP-ALGEBRA,
  volume =       "41",
  number =       "3",
  pages =        "75--99",
  month =        sep,
  year =         "2007",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/1358190.1358192",
  ISSN =         "1932-2232 (print), 1932-2240 (electronic)",
  ISSN-L =       "1932-2232",
  bibdate =      "Wed Jun 18 09:23:01 MDT 2008",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Most of us have taken the exact rational and
                 approximate numbers in our computer algebra systems for
                 granted for a long time, not thinking to ask if they
                 could be significantly better. With exact rational
                 arithmetic and adjustable-precision floating-point
                 arithmetic to precision limited only by the total
                 computer memory or our patience, what more could we
                 want for such numbers? It turns out that there is much
                 more that can be done that permits us to obtain exact
                 results more often, more intelligible results,
                 approximate results guaranteed to have requested error
                 bounds, and recovery of exact results from approximate
                 ones.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Communications in Computer Algebra",
  issue =        "161",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J1000",
  keywords =     "interval arithmetic",
}


bibtype: article
filename: fparith.bib
label: Swartzlander:2007:NTC
author: Earl E. Swartzlander, Jr.
title: The Negative Two's Complement Number System
journal: j-J-VLSI-SIGNAL-PROC
volume: 49
number: 1
pages: 177--183
month: oct
monthnumber: 10
year: 2007
CODEN: JVSPED
DOI: https://doi.org/10.1007/s11265-007-0052-y
ISSN: 0922-5773 (print), 1573-109x (electronic) OR 09225773 (print), 1573109x (electronic)
ISSNL: 0922-5773 OR 09225773
bibdate: Mon Nov 05 19:26:21 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.11.05 19:26:21 ???
fjournal: Journal of VLSI Signal Processing
acknowledgement: ack-nhfb
rawauthor: Earl E. {Swartzlander, Jr.}
rawtitle: The Negative Two's Complement Number System
abstract:
The two's complement fractional fixed-point number system is widely used to implement digital signal processing on VLSI chips. It has a range of values from $ - 1 $ to one least significant bit below +1. Either the multiplication of $ - 1 $ - $ - 1 $ or taking the absolute value of $ - 1 $ produces a result ($ + 1 $) that cannot be represented. A new system, the negative two's complement number system, is described here that has a range of one least significant bit above $ - 1 $ to $ + 1 $ which eliminates the problem. This paper presents the new number system and describes algorithms for the basic arithmetic operations.

rawabstract:
The two's complement fractional fixed-point number system is widely used to implement digital signal processing on VLSI chips. It has a range of values from $ - 1 $ to one least significant bit below +1. Either the multiplication of $ - 1 $ - $ - 1 $ or taking the absolute value of $ - 1 $ produces a result ($ + 1 $) that cannot be represented. A new system, the negative two's complement number system, is described here that has a range of one least significant bit above $ - 1 $ to $ + 1 $ which eliminates the problem. This paper presents the new number system and describes algorithms for the basic arithmetic operations.

entry:
@Article{Swartzlander:2007:NTC,
  author =       "Earl E. {Swartzlander, Jr.}",
  title =        "The Negative Two's Complement Number System",
  journal =      j-J-VLSI-SIGNAL-PROC,
  volume =       "49",
  number =       "1",
  pages =        "177--183",
  month =        oct,
  year =         "2007",
  CODEN =        "JVSPED",
  DOI =          "https://doi.org/10.1007/s11265-007-0052-y",
  ISSN =         "0922-5773 (print), 1573-109x (electronic)",
  ISSN-L =       "0922-5773",
  bibdate =      "Mon Nov 05 19:26:21 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The two's complement fractional fixed-point number
                 system is widely used to implement digital signal
                 processing on VLSI chips. It has a range of values from
                 $ - 1 $ to one least significant bit below +1. Either
                 the multiplication of $ - 1 $ - $ - 1 $ or taking the
                 absolute value of $ - 1 $ produces a result ($ + 1 $)
                 that cannot be represented. A new system, the negative
                 two's complement number system, is described here that
                 has a range of one least significant bit above $ - 1 $
                 to $ + 1 $ which eliminates the problem. This paper
                 presents the new number system and describes algorithms
                 for the basic arithmetic operations.",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of VLSI Signal Processing",
  xxnote =       "Check math in abstract??",
}


bibtype: inproceedings
filename: fparith.bib
label: Tang:2007:MMU
author: Ping Tak Peter Tang
title: Modular Multiplication using Redundant Digit Division
crossref: Kornerup:2007:PIS
pages: 217--224
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.22
bibdate: Tue Oct 9 17:16:03 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 17:16:03 MDT
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Ping Tak Peter Tang
rawtitle: Modular Multiplication using Redundant Digit Division
abstract:
Most implementations of the modular exponentiation, $ M E bmod N $, computation in cryptographic algorithms employ Montgomery multiplication, $ (A B R - 1) bmod N $, instead of modular multiplication, $ A B bmod N $, even the former requires some transformational overheads. This is so because a state-of-the-art Montgomery multiplication implementation has a performance advantage over direct modular multiplication based on the Barrett algorithm that more than compensates for the overhead. In this paper, we present a direct modular multiplication method that is comparable in speed to Montgomery multiplication. One consequence is that when the exponent in small, direct computation (which does not incur the transformational overhead) using the modular multiplication algorithm presented here results in practical performance gain. For the exponent 17, for instance, which requires five modular multiplication, a saving of up to 40% can be achieved.

rawabstract:
Most implementations of the modular exponentiation, $ M E \bmod N $, computation in cryptographic algorithms employ Montgomery multiplication, $ (A B R - 1) \bmod N $, instead of modular multiplication, $ A B \bmod N $, even the former requires some transformational overheads. This is so because a state-of-the-art Montgomery multiplication implementation has a performance advantage over direct modular multiplication based on the Barrett algorithm that more than compensates for the overhead. In this paper, we present a direct modular multiplication method that is comparable in speed to Montgomery multiplication. One consequence is that when the exponent in small, direct computation (which does not incur the transformational overhead) using the modular multiplication algorithm presented here results in practical performance gain. For the exponent 17, for instance, which requires five modular multiplication, a saving of up to 40\% can be achieved.

entry:
@InProceedings{Tang:2007:MMU,
  author =       "Ping Tak Peter Tang",
  title =        "Modular Multiplication using Redundant Digit
                 Division",
  crossref =     "Kornerup:2007:PIS",
  pages =        "217--224",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.22",
  bibdate =      "Tue Oct 9 17:16:03 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Most implementations of the modular exponentiation, $
                 M E \bmod N $, computation in cryptographic algorithms
                 employ Montgomery multiplication, $ (A B R - 1) \bmod N
                 $, instead of modular multiplication, $ A B \bmod N $,
                 even the former requires some transformational
                 overheads. This is so because a state-of-the-art
                 Montgomery multiplication implementation has a
                 performance advantage over direct modular
                 multiplication based on the Barrett algorithm that more
                 than compensates for the overhead. In this paper, we
                 present a direct modular multiplication method that is
                 comparable in speed to Montgomery multiplication. One
                 consequence is that when the exponent in small, direct
                 computation (which does not incur the transformational
                 overhead) using the modular multiplication algorithm
                 presented here results in practical performance gain.
                 For the exponent 17, for instance, which requires five
                 modular multiplication, a saving of up to 40\% can be
                 achieved.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: article
filename: fparith.bib
label: Thapliyal:2007:CIV
author: Himanshu Thapliyal and Hamid R. Arabnia and Rajnish Bajpai and Kamal K. Sharma
title: Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs
journal: arXiv.org
pages: ??--??
day: 16
month: nov
monthnumber: 11
year: 2007
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/0711.2671
subject: Hardware Architecture (cs.AR)
acknowledgement: ack-nhfb
rawauthor: Himanshu Thapliyal and Hamid R. Arabnia and Rajnish Bajpai and Kamal K. Sharma
abstract:
In this paper, we propose an architecture/methodology for making FPGAs suitable for integer as well as variable precision floating point multiplication. The proposed work will of great importance in applications which requires variable precision floating point multiplication such as multi-media processing applications. In the proposed architecture/methodology, we propose the replacement of existing 18x18 bit and 25x18 bit dedicated multipliers in FPGAs with dedicated 24x24 bit and 24x9 bit multipliers, respectively. We have proved that our approach of providing the dedicated 24x24 bit and 24x9 bit multipliers in FPGAs will make them efficient for performing integer as well as single precision, double precision, and Quadruple precision floating point multiplications.

rawabstract:
In this paper, we propose an architecture/methodology for making FPGAs suitable for integer as well as variable precision floating point multiplication. The proposed work will of great importance in applications which requires variable precision floating point multiplication such as multi-media processing applications. In the proposed architecture/methodology, we propose the replacement of existing 18x18 bit and 25x18 bit dedicated multipliers in FPGAs with dedicated 24x24 bit and 24x9 bit multipliers, respectively. We have proved that our approach of providing the dedicated 24x24 bit and 24x9 bit multipliers in FPGAs will make them efficient for performing integer as well as single precision, double precision, and Quadruple precision floating point multiplications.

rawtitle:
Combined Integer and Variable Precision {(CIVP)} Floating Point Multiplication Architecture for {FPGAs}

entry:
@Article{Thapliyal:2007:CIV,
  author =       "Himanshu Thapliyal and Hamid R. Arabnia and Rajnish
                 Bajpai and Kamal K. Sharma",
  title =        "Combined Integer and Variable Precision {(CIVP)}
                 Floating Point Multiplication Architecture for
                 {FPGAs}",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "16",
  month =        nov,
  year =         "2007",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/0711.2671",
  abstract =     "In this paper, we propose an architecture/methodology
                 for making FPGAs suitable for integer as well as
                 variable precision floating point multiplication. The
                 proposed work will of great importance in applications
                 which requires variable precision floating point
                 multiplication such as multi-media processing
                 applications. In the proposed architecture/methodology,
                 we propose the replacement of existing 18x18 bit and
                 25x18 bit dedicated multipliers in FPGAs with dedicated
                 24x24 bit and 24x9 bit multipliers, respectively. We
                 have proved that our approach of providing the
                 dedicated 24x24 bit and 24x9 bit multipliers in FPGAs
                 will make them efficient for performing integer as well
                 as single precision, double precision, and Quadruple
                 precision floating point multiplications.",
  acknowledgement = ack-nhfb,
  subject =      "Hardware Architecture (cs.AR)",
}


bibtype: inproceedings
filename: fparith.bib
label: Trong:2007:PBF
author: Son Dao Trong and Martin Schmookler and Eric. M. Schwarz and Michael Kroener
title: P6 Binary Floating-Point Unit
crossref: Kornerup:2007:PIS
pages: 77--86
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.26
bibdate: Tue Oct 9 16:32:41 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 16:32:41 MDT
acknowledgement: ack-nhfb
rawauthor: Son Dao Trong and Martin Schmookler and Eric. M. Schwarz and Michael Kroener
rawtitle: {P6} Binary Floating-Point Unit
abstract:
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a technology independent measure. For most dependent instructions, its fused multiply-add dataflow has only 6 effective pipeline stages. This is nearly equivalent to its predecessor, the Power 5, even though its technology independent frequency has increased over 70%. Overall the frequency has improved over 100%. It achieves this high performance through aggressive feedback paths, circuit design and layout. The pipeline has 7 stages but data may be fed back to dependent operations prior to rounding and complete normalization. Division and square root algorithms are also described which take advantage of high-precision linear approximation hardware for obtaining a reciprocal or reciprocal square root approximation

keywords:
aggressive data forwarding; ARITH-18; data processing without stalls; denormal result handling; floating-point unit; high-frequency design

rawabstract:
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a technology independent measure. For most dependent instructions, its fused multiply-add dataflow has only 6 effective pipeline stages. This is nearly equivalent to its predecessor, the Power 5, even though its technology independent frequency has increased over 70\%. Overall the frequency has improved over 100\%. It achieves this high performance through aggressive feedback paths, circuit design and layout. The pipeline has 7 stages but data may be fed back to dependent operations prior to rounding and complete normalization. Division and square root algorithms are also described which take advantage of high-precision linear approximation hardware for obtaining a reciprocal or reciprocal square root approximation

entry:
@InProceedings{Trong:2007:PBF,
  author =       "Son Dao Trong and Martin Schmookler and Eric. M.
                 Schwarz and Michael Kroener",
  title =        "{P6} Binary Floating-Point Unit",
  crossref =     "Kornerup:2007:PIS",
  pages =        "77--86",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.26",
  bibdate =      "Tue Oct 9 16:32:41 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "The floating point unit of the next generation PowerPC
                 is detailed. It has been tested at over 5 GHz. The
                 design supports an extremely aggressive cycle time of
                 13 FO4 using a technology independent measure. For most
                 dependent instructions, its fused multiply-add dataflow
                 has only 6 effective pipeline stages. This is nearly
                 equivalent to its predecessor, the Power 5, even though
                 its technology independent frequency has increased over
                 70\%. Overall the frequency has improved over 100\%. It
                 achieves this high performance through aggressive
                 feedback paths, circuit design and layout. The pipeline
                 has 7 stages but data may be fed back to dependent
                 operations prior to rounding and complete
                 normalization. Division and square root algorithms are
                 also described which take advantage of high-precision
                 linear approximation hardware for obtaining a
                 reciprocal or reciprocal square root approximation",
  acknowledgement = ack-nhfb,
  keywords =     "aggressive data forwarding; ARITH-18; data processing
                 without stalls; denormal result handling;
                 floating-point unit; high-frequency design",
}


bibtype: inproceedings
filename: fparith.bib
label: Tsen:2007:HDBa
author: C. Tsen and S. Gonzalez-Navarro and M. Schulte
title: Hardware Design of a Binary Integer Decimal-based Floating-point Adder
crossref: IEEE:2007:ICC
pages: 288--295
year: 2007
DOI: https://doi.org/10.1109/ICCD.2007.4601915
bibdate: Sat Dec 04 10:20:58 2010
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2010.12.04 10:20:58 ???
acknowledgement: ack-nhfb
rawauthor: C. Tsen and S. Gonzalez-Navarro and M. Schulte
rawtitle: Hardware Design of a Binary Integer Decimal-based Floating-point Adder
abstract:
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P754). In this paper, we present a novel algorithm and hardware design for a DFP adder. The adder performs addition and subtraction on 64-bit operands that use the IEEE P754 binary encoding of DFP numbers, widely known as the binary integer decimal (BID) encoding. The BID adder uses a novel hardware component for decimal digit counting and an enhanced version of a previously published BID rounding unit. By adding more sophisticated control, operations are performed with variable latency to optimize for common cases. We show that a BID-based DFP adder design can be achieved with a modest area increase compared to a single 2-stage pipelined 64-bit fixed-point multiplier. Over 70% of the BID adder's area is due to the 64-bit fixed-point multiplier, which can be shared with a binary floating-point multiplier and hardware for other DFP operations. To our knowledge, this is the first hardware design for adding and subtracting IEEE P754 BID-encoded DFP numbers

rawabstract:
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P754). In this paper, we present a novel algorithm and hardware design for a DFP adder. The adder performs addition and subtraction on 64-bit operands that use the IEEE P754 binary encoding of DFP numbers, widely known as the binary integer decimal (BID) encoding. The BID adder uses a novel hardware component for decimal digit counting and an enhanced version of a previously published BID rounding unit. By adding more sophisticated control, operations are performed with variable latency to optimize for common cases. We show that a BID-based DFP adder design can be achieved with a modest area increase compared to a single 2-stage pipelined 64-bit fixed-point multiplier. Over 70\% of the BID adder's area is due to the 64-bit fixed-point multiplier, which can be shared with a binary floating-point multiplier and hardware for other DFP operations. To our knowledge, this is the first hardware design for adding and subtracting IEEE P754 BID-encoded DFP numbers

entry:
@InProceedings{Tsen:2007:HDBa,
  author =       "C. Tsen and S. Gonzalez-Navarro and M. Schulte",
  title =        "Hardware Design of a Binary Integer Decimal-based
                 Floating-point Adder",
  crossref =     "IEEE:2007:ICC",
  pages =        "288--295",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ICCD.2007.4601915",
  bibdate =      "Sat Dec 04 10:20:58 2010",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Because of the growing importance of decimal
                 floating-point (DFP) arithmetic, specifications for it
                 are included in the IEEE Draft Standard for
                 Floating-point Arithmetic (IEEE P754). In this paper,
                 we present a novel algorithm and hardware design for a
                 DFP adder. The adder performs addition and subtraction
                 on 64-bit operands that use the IEEE P754 binary
                 encoding of DFP numbers, widely known as the binary
                 integer decimal (BID) encoding. The BID adder uses a
                 novel hardware component for decimal digit counting and
                 an enhanced version of a previously published BID
                 rounding unit. By adding more sophisticated control,
                 operations are performed with variable latency to
                 optimize for common cases. We show that a BID-based DFP
                 adder design can be achieved with a modest area
                 increase compared to a single 2-stage pipelined 64-bit
                 fixed-point multiplier. Over 70\% of the BID adder's
                 area is due to the 64-bit fixed-point multiplier, which
                 can be shared with a binary floating-point multiplier
                 and hardware for other DFP operations. To our
                 knowledge, this is the first hardware design for adding
                 and subtracting IEEE P754 BID-encoded DFP numbers",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Tsen:2007:HDBb
author: Charles Tsen and Michael Schulte and Sonia Gonzalez-Navarro
title: Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit
crossref: IEEE:2007:ACP
pages: 115--121
year: 2007
bibdate: Sun Feb 20 17:42:56 2011
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2011.02.20 17:42:56 ???
acknowledgement: ack-nhfb
rawauthor: Charles Tsen and Michael Schulte and Sonia Gonzalez-Navarro
rawtitle: Hardware Design of a Binary Integer Decimal-based {IEEE P754} Rounding Unit
abstract:
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it were recently added to the draft revision of the IEEE 754 Standard (IEEE P754). In this paper, we present a hardware design for a rounding unit for 64-bit DFP numbers (decimal 64) that use the IEEE P754 binary encoding of DFP numbers, which is widely known as the Binary Integer Decimal (BID) encoding. We summarize the technique used for rounding, present the theory and design of the BID rounding unit, and evaluate its critical path delay, latency, and area for combinational and pipelined designs. Over 86% of the rounding unit's area is due to a 55-bit by 54-bit binary multiplier, which can be shared with a double-precision binary floating-point multiplier. To our knowledge, this is the first hardware design for rounding IEEE P754 BID-encoded DFP numbers.

keywords:
BID rounding; binary integer decimal encoding; decimal floating-point arithmetic; double-precision binary floating-point multiplier; hardware design; IEEE 754 standard; IEEE P754 binary encoding; IEEE P754 rounding unit

rawabstract:
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it were recently added to the draft revision of the IEEE 754 Standard (IEEE P754). In this paper, we present a hardware design for a rounding unit for 64-bit DFP numbers (decimal 64) that use the IEEE P754 binary encoding of DFP numbers, which is widely known as the Binary Integer Decimal (BID) encoding. We summarize the technique used for rounding, present the theory and design of the BID rounding unit, and evaluate its critical path delay, latency, and area for combinational and pipelined designs. Over 86\% of the rounding unit's area is due to a 55-bit by 54-bit binary multiplier, which can be shared with a double-precision binary floating-point multiplier. To our knowledge, this is the first hardware design for rounding IEEE P754 BID-encoded DFP numbers.

entry:
@InProceedings{Tsen:2007:HDBb,
  author =       "Charles Tsen and Michael Schulte and Sonia
                 Gonzalez-Navarro",
  title =        "Hardware Design of a Binary Integer Decimal-based
                 {IEEE P754} Rounding Unit",
  crossref =     "IEEE:2007:ACP",
  pages =        "115--121",
  year =         "2007",
  bibdate =      "Sun Feb 20 17:42:56 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "Because of the growing importance of decimal
                 floating-point (DFP) arithmetic, specifications for it
                 were recently added to the draft revision of the IEEE
                 754 Standard (IEEE P754). In this paper, we present a
                 hardware design for a rounding unit for 64-bit DFP
                 numbers (decimal 64) that use the IEEE P754 binary
                 encoding of DFP numbers, which is widely known as the
                 Binary Integer Decimal (BID) encoding. We summarize the
                 technique used for rounding, present the theory and
                 design of the BID rounding unit, and evaluate its
                 critical path delay, latency, and area for
                 combinational and pipelined designs. Over 86\% of the
                 rounding unit's area is due to a 55-bit by 54-bit
                 binary multiplier, which can be shared with a
                 double-precision binary floating-point multiplier. To
                 our knowledge, this is the first hardware design for
                 rounding IEEE P754 BID-encoded DFP numbers.",
  acknowledgement = ack-nhfb,
  keywords =     "BID rounding; binary integer decimal encoding; decimal
                 floating-point arithmetic; double-precision binary
                 floating-point multiplier; hardware design; IEEE 754
                 standard; IEEE P754 binary encoding; IEEE P754 rounding
                 unit",
}


bibtype: article
filename: fparith.bib
label: Vasudevan:2007:AVA
author: S. Vasudevan and V. Viswanath and R. W. Sumners and J. A. Abraham
journal: j-IEEE-TRANS-COMPUT
volume: 56
number: 10
pages: 1401--1414
month: oct
monthnumber: 10
year: 2007
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2007.1073
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jul 4 15:03:42 MDT 2011
bibtimestamp: 2011.07.04 15:03:42 MDT
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4302711
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: S. Vasudevan and V. Viswanath and R. W. Sumners and J. A. Abraham
title:
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems

rawtitle:
Automatic Verification of Arithmetic Circuits in {RTL} Using Stepwise Refinement of Term Rewriting Systems

entry:
@Article{Vasudevan:2007:AVA,
  author =       "S. Vasudevan and V. Viswanath and R. W. Sumners and J.
                 A. Abraham",
  title =        "Automatic Verification of Arithmetic Circuits in {RTL}
                 Using Stepwise Refinement of Term Rewriting Systems",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "56",
  number =       "10",
  pages =        "1401--1414",
  month =        oct,
  year =         "2007",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2007.1073",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jul 4 15:03:42 MDT 2011",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2000.bib",
  URL =          "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4302711",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Vazquez:2007:NFH
author: Alvaro Vazquez and Elisardo Antelo and Paolo Montuschi
title: A New Family of High-Performance Parallel Decimal Multipliers
crossref: Kornerup:2007:PIS
pages: 195--204
year: 2007
DOI: https://doi.org/10.1109/ARITH.2007.6
bibdate: Tue Oct 9 17:16:03 MDT 2007
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2007.10.09 17:16:03 MDT
URL: http://www.lirmm.fr/arith18/papers/vazquez-DecimalMultiplier.pdf
keywords: ARITH-18
acknowledgement: ack-nhfb
rawauthor: Alvaro Vazquez and Elisardo Antelo and Paolo Montuschi
rawtitle: A New Family of High-Performance Parallel Decimal Multipliers
abstract:
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry-save multioperand addition that uses a novel BCD-4221 recoding for decimal digits. It significantly improves the area and latency of the partial product reduction tree with respect to previous proposals. We also present three schemes for fast and efficient generation of partial products in parallel. The recoding of the BCD-8421 multiplier operand into minimally redundant signed-digit radix-10, radix-4 and radix-5 representations using new recoders reduces the complexity of partial product generation. In addition, SD radix-4 and radix-5 recodings allow the reuse of a conventional parallel binary radix-4 multiplier to perform combined binary/ decimal multiplications. Evaluation results show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and radix-8 parallel binary multipliers and other representative alternatives for decimal multiplication.

rawabstract:
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry-save multioperand addition that uses a novel BCD-4221 recoding for decimal digits. It significantly improves the area and latency of the partial product reduction tree with respect to previous proposals. We also present three schemes for fast and efficient generation of partial products in parallel. The recoding of the BCD-8421 multiplier operand into minimally redundant signed-digit radix-10, radix-4 and radix-5 representations using new recoders reduces the complexity of partial product generation. In addition, SD radix-4 and radix-5 recodings allow the reuse of a conventional parallel binary radix-4 multiplier to perform combined binary/ decimal multiplications. Evaluation results show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and radix-8 parallel binary multipliers and other representative alternatives for decimal multiplication.

entry:
@InProceedings{Vazquez:2007:NFH,
  author =       "Alvaro Vazquez and Elisardo Antelo and Paolo
                 Montuschi",
  title =        "A New Family of High-Performance Parallel Decimal
                 Multipliers",
  crossref =     "Kornerup:2007:PIS",
  pages =        "195--204",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ARITH.2007.6",
  bibdate =      "Tue Oct 9 17:16:03 MDT 2007",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.lirmm.fr/arith18/papers/vazquez-DecimalMultiplier.pdf",
  abstract =     "This paper introduces two novel architectures for
                 parallel decimal multipliers. Our multipliers are based
                 on a new algorithm for decimal carry-save multioperand
                 addition that uses a novel BCD-4221 recoding for
                 decimal digits. It significantly improves the area and
                 latency of the partial product reduction tree with
                 respect to previous proposals. We also present three
                 schemes for fast and efficient generation of partial
                 products in parallel. The recoding of the BCD-8421
                 multiplier operand into minimally redundant
                 signed-digit radix-10, radix-4 and radix-5
                 representations using new recoders reduces the
                 complexity of partial product generation. In addition,
                 SD radix-4 and radix-5 recodings allow the reuse of a
                 conventional parallel binary radix-4 multiplier to
                 perform combined binary/ decimal multiplications.
                 Evaluation results show that the proposed architectures
                 have interesting area-delay figures compared to
                 conventional Booth radix-4 and radix-8 parallel binary
                 multipliers and other representative alternatives for
                 decimal multiplication.",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-18",
}


bibtype: inproceedings
filename: fparith.bib
label: Veeramachaneni:2007:NHS
title: Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format
crossref: Becker:2007:EVT
pages: 343--350
year: 2007
DOI: https://doi.org/10.1109/ISVLSI.2007.71
bibdate: Thu Aug 07 18:55:05 2008
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.08.07 18:55:05 ???
acknowledgement: ack-nhfb
rawtitle: Novel, High-Speed 16-Digit {BCD} Adders Conforming to {IEEE 754r} Format
author:
Sreehari Veeramachaneni and M. Kirthi Krishna and Lingamneni Avinash and Reddy P. Sreekanth and M. B. Srinivas

abstract:
In view of increasing prominence of commercial, financial and Internet-based applications that process data in decimal format, there is a renewed interest in providing hardware support to handle decimal data. In this paper, a new architecture for efficient 1-digit decimal addition of binary coded decimal (BCD) operands, which is the core of high speed multi-operand adders and floating decimal-point arithmetic, is proposed. Based on this 1-digit BCD adder, novel architectures for higher order (n-digit) BCD adders such as ripple carry adder and carry look-ahead adder are derived. The proposed circuits are compared (both qualitatively as well as quantitatively) with the existing circuits in literature and are shown to perform better. Simulation results show that the proposed 1-digit BCD adder achieves an improvement of 40% in delay. The 16-digit BCD lookahead adder using prefix logic is shown to perform at least 80% faster than the existing ripple carry one.

rawabstract:
In view of increasing prominence of commercial, financial and Internet-based applications that process data in decimal format, there is a renewed interest in providing hardware support to handle decimal data. In this paper, a new architecture for efficient 1-digit decimal addition of binary coded decimal (BCD) operands, which is the core of high speed multi-operand adders and floating decimal-point arithmetic, is proposed. Based on this 1-digit BCD adder, novel architectures for higher order (n-digit) BCD adders such as ripple carry adder and carry look-ahead adder are derived. The proposed circuits are compared (both qualitatively as well as quantitatively) with the existing circuits in literature and are shown to perform better. Simulation results show that the proposed 1-digit BCD adder achieves an improvement of 40\% in delay. The 16-digit BCD lookahead adder using prefix logic is shown to perform at least 80\% faster than the existing ripple carry one.

rawauthor:
Sreehari Veeramachaneni and M. Kirthi Krishna and Lingamneni Avinash and Reddy P. Sreekanth and M. B. Srinivas

entry:
@InProceedings{Veeramachaneni:2007:NHS,
  author =       "Sreehari Veeramachaneni and M. Kirthi Krishna and
                 Lingamneni Avinash and Reddy P. Sreekanth and M. B.
                 Srinivas",
  title =        "Novel, High-Speed 16-Digit {BCD} Adders Conforming to
                 {IEEE 754r} Format",
  crossref =     "Becker:2007:EVT",
  pages =        "343--350",
  year =         "2007",
  DOI =          "https://doi.org/10.1109/ISVLSI.2007.71",
  bibdate =      "Thu Aug 07 18:55:05 2008",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "In view of increasing prominence of commercial,
                 financial and Internet-based applications that process
                 data in decimal format, there is a renewed interest in
                 providing hardware support to handle decimal data. In
                 this paper, a new architecture for efficient 1-digit
                 decimal addition of binary coded decimal (BCD)
                 operands, which is the core of high speed multi-operand
                 adders and floating decimal-point arithmetic, is
                 proposed. Based on this 1-digit BCD adder, novel
                 architectures for higher order (n-digit) BCD adders
                 such as ripple carry adder and carry look-ahead adder
                 are derived. The proposed circuits are compared (both
                 qualitatively as well as quantitatively) with the
                 existing circuits in literature and are shown to
                 perform better. Simulation results show that the
                 proposed 1-digit BCD adder achieves an improvement of
                 40\% in delay. The 16-digit BCD lookahead adder using
                 prefix logic is shown to perform at least 80\% faster
                 than the existing ripple carry one.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Voronenko:2007:MMC
author: Yevgen Voronenko and Markus Puschel
title: Multiplierless multiple constant multiplication
journal: j-TALG
volume: 3
number: 2
pages: 11:1--11:??
month: may
monthnumber: 5
year: 2007
DOI: https://doi.org/10.1145/1240233.1240234
ISSN: 1549-6325 (print), 1549-6333 (electronic) OR 15496325 (print), 15496333 (electronic)
ISSNL: 1549-6325 OR 15496325
bibdate: Mon Jun 16 11:54:42 MDT 2008
bibsource: http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2008.06.16 11:54:42 MDT
fjournal: ACM Transactions on Algorithms (TALG)
keywords: Addition chains; directed graph; FIR filter; fixed-point arithmetic; strength reduction
acknowledgement: ack-nhfb
articleno: 11
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J982
rawauthor: Yevgen Voronenko and Markus P{\"u}schel
rawtitle: Multiplierless multiple constant multiplication
abstract:
A variable can be multiplied by a given set of fixed-point constants using a multiplier block that consists exclusively of additions, subtractions, and shifts. The generation of a multiplier block from the set of constants is known as the multiple constant multiplication (MCM) problem. Finding the optimal solution, namely, the one with the fewest number of additions and subtractions, is known to be NP-complete. We propose a new algorithm for the MCM problem, which produces solutions that require up to 20% less additions and subtractions than the best previously known algorithm. At the same time our algorithm, in contrast to the closest competing algorithm, is not limited by the constant bitwidths. We present our algorithm using a unifying formal framework for the best, graph-based MCM algorithms and provide a detailed runtime analysis and experimental evaluation. We show that our algorithm can handle problem sizes as large as 100 32-bit constants in a time acceptable for most applications. The implementation of the new algorithm is available at url www.spiral.net.

rawabstract:
A variable can be multiplied by a given set of fixed-point constants using a multiplier block that consists exclusively of additions, subtractions, and shifts. The generation of a multiplier block from the set of constants is known as the multiple constant multiplication (MCM) problem. Finding the optimal solution, namely, the one with the fewest number of additions and subtractions, is known to be NP-complete. We propose a new algorithm for the MCM problem, which produces solutions that require up to 20\% less additions and subtractions than the best previously known algorithm. At the same time our algorithm, in contrast to the closest competing algorithm, is not limited by the constant bitwidths. We present our algorithm using a unifying formal framework for the best, graph-based MCM algorithms and provide a detailed runtime analysis and experimental evaluation. We show that our algorithm can handle problem sizes as large as 100 32-bit constants in a time acceptable for most applications. The implementation of the new algorithm is available at \url{www.spiral.net}.

entry:
@Article{Voronenko:2007:MMC,
  author =       "Yevgen Voronenko and Markus P{\"u}schel",
  title =        "Multiplierless multiple constant multiplication",
  journal =      j-TALG,
  volume =       "3",
  number =       "2",
  pages =        "11:1--11:??",
  month =        may,
  year =         "2007",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/1240233.1240234",
  ISSN =         "1549-6325 (print), 1549-6333 (electronic)",
  ISSN-L =       "1549-6325",
  bibdate =      "Mon Jun 16 11:54:42 MDT 2008",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  abstract =     "A variable can be multiplied by a given set of
                 fixed-point constants using a multiplier block that
                 consists exclusively of additions, subtractions, and
                 shifts. The generation of a multiplier block from the
                 set of constants is known as the multiple constant
                 multiplication (MCM) problem. Finding the optimal
                 solution, namely, the one with the fewest number of
                 additions and subtractions, is known to be NP-complete.
                 We propose a new algorithm for the MCM problem, which
                 produces solutions that require up to 20\% less
                 additions and subtractions than the best previously
                 known algorithm. At the same time our algorithm, in
                 contrast to the closest competing algorithm, is not
                 limited by the constant bitwidths. We present our
                 algorithm using a unifying formal framework for the
                 best, graph-based MCM algorithms and provide a detailed
                 runtime analysis and experimental evaluation. We show
                 that our algorithm can handle problem sizes as large as
                 100 32-bit constants in a time acceptable for most
                 applications. The implementation of the new algorithm
                 is available at \url{www.spiral.net}.",
  acknowledgement = ack-nhfb,
  articleno =    "11",
  fjournal =     "ACM Transactions on Algorithms (TALG)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J982",
  keywords =     "Addition chains; directed graph; FIR filter;
                 fixed-point arithmetic; strength reduction",
}


