# bibtab

bibtype: article
filename: fparith.bib
label: Yan:2012:RBC
author: Song Yan
title: Review of booktitle Modern Computer Arithmetic, by Richard Brent and Paul Zimmermann
journal: j-SIGACT
volume: 43
number: 4
pages: 49--51
month: dec
monthnumber: 12
year: 2012
CODEN: SIGNDM
DOI: https://doi.org/10.1145/2421119.2421130
ISSN: 0163-5700 (print), 1943-5827 (electronic) OR 01635700 (print), 19435827 (electronic)
ISSNL: 0163-5700 OR 01635700
bibdate: Sun May 5 10:25:40 MDT 2013
bibtimestamp: 2013.05.05 10:25:40 MDT
fjournal: ACM SIGACT News
acknowledgement: ack-nhfb
journalURL: http://dl.acm.org/citation.cfm?id=J697
rawauthor: Song Yan
rawtitle: Review of {{\booktitle{Modern Computer Arithmetic}}, by Richard Brent and Paul Zimmermann}
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigact.bib

entry:
@Article{Yan:2012:RBC,
  author =       "Song Yan",
  title =        "Review of {{\booktitle{Modern Computer Arithmetic}},
                 by Richard Brent and Paul Zimmermann}",
  journal =      j-SIGACT,
  volume =       "43",
  number =       "4",
  pages =        "49--51",
  month =        dec,
  year =         "2012",
  CODEN =        "SIGNDM",
  DOI =          "https://doi.org/10.1145/2421119.2421130",
  ISSN =         "0163-5700 (print), 1943-5827 (electronic)",
  ISSN-L =       "0163-5700",
  bibdate =      "Sun May 5 10:25:40 MDT 2013",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigact.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGACT News",
  journal-URL =  "http://dl.acm.org/citation.cfm?id=J697",
}


bibtype: article
filename: fparith.bib
label: Yan:2012:RMC
author: Song Yan
title: Review of booktitle Modern Computer Arithmetic, by Richard Brent and Paul Zimmermann
journal: j-SIGACT
volume: 43
number: 4
pages: 49--51
month: dec
monthnumber: 12
year: 2012
CODEN: SIGNDM
DOI: https://doi.org/10.1145/2421119.2421130
ISSN: 0163-5700 (print), 1943-5827 (electronic) OR 01635700 (print), 19435827 (electronic)
ISSNL: 0163-5700 OR 01635700
bibdate: Sun May 5 10:25:40 MDT 2013
bibtimestamp: 2013.05.05 10:25:40 MDT
fjournal: ACM SIGACT News
acknowledgement: ack-nhfb
journalURL: http://dl.acm.org/citation.cfm?id=J697
rawauthor: Song Yan
rawtitle: Review of {{\booktitle{Modern Computer Arithmetic}}, by Richard Brent and Paul Zimmermann}
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigact.bib

entry:
@Article{Yan:2012:RMC,
  author =       "Song Yan",
  title =        "Review of {{\booktitle{Modern Computer Arithmetic}},
                 by Richard Brent and Paul Zimmermann}",
  journal =      j-SIGACT,
  volume =       "43",
  number =       "4",
  pages =        "49--51",
  month =        dec,
  year =         "2012",
  CODEN =        "SIGNDM",
  DOI =          "https://doi.org/10.1145/2421119.2421130",
  ISSN =         "0163-5700 (print), 1943-5827 (electronic)",
  ISSN-L =       "0163-5700",
  bibdate =      "Sun May 5 10:25:40 MDT 2013",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigact.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGACT News",
  journal-URL =  "http://dl.acm.org/citation.cfm?id=J697",
}


bibtype: article
filename: fparith.bib
label: Anguita:2013:EES
author: D. Anguita and A. Ghio and L. Oneto and X. Parra and J. L. Reyes-Ortiz
title: Energy Efficient Smartphone-Based Activity Recognition using Fixed-Point Arithmetic
journal: j-J-UCS
volume: 19
number: 9
pages: 1295--??
year: 2013
ISSN: 0948-695X (print), 0948-6968 (electronic) OR 0948695X (print), 09486968 (electronic)
ISSNL: 0948-6968 OR 09486968
bibdate: Fri Sep 13 11:19:07 MDT 2013
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jucs.bib
bibtimestamp: 2013.09.13 11:19:07 MDT
URL: http://www.jucs.org/jucs_19_9/energy_efficient_smartphone_based
fjournal: J.UCS: Journal of Universal Computer Science
acknowledgement: ack-nhfb
journalURL: http://www.jucs.org/jucs
rawauthor: D. Anguita and A. Ghio and L. Oneto and X. Parra and J. L. Reyes-Ortiz
rawtitle: Energy Efficient {Smartphone}-Based Activity Recognition using Fixed-Point Arithmetic
entry:
@Article{Anguita:2013:EES,
  author =       "D. Anguita and A. Ghio and L. Oneto and X. Parra and
                 J. L. Reyes-Ortiz",
  title =        "Energy Efficient {Smartphone}-Based Activity
                 Recognition using Fixed-Point Arithmetic",
  journal =      j-J-UCS,
  volume =       "19",
  number =       "9",
  pages =        "1295--??",
  month =        "????",
  year =         "2013",
  CODEN =        "????",
  ISSN =         "0948-695X (print), 0948-6968 (electronic)",
  ISSN-L =       "0948-6968",
  bibdate =      "Fri Sep 13 11:19:07 MDT 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jucs.bib",
  URL =          "http://www.jucs.org/jucs_19_9/energy_efficient_smartphone_based",
  acknowledgement = ack-nhfb,
  fjournal =     "J.UCS: Journal of Universal Computer Science",
  journal-URL =  "http://www.jucs.org/jucs",
}


bibtype: inproceedings
filename: fparith.bib
label: Anonymous:2013:DML
author: Anonymous
title: Dedication: In memory of Luigi Ciminiera 1954--2012 and In memory of Luigi Dadda 1923--2012
crossref: IEEE:2013:PIS
pages: ix--xi
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.11
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
keywords: ARITH-21; Biographies; Ciminiera, Luigi; Dadda, Luigi; Obituaries
acknowledgement: ack-nhfb
rawauthor: Anonymous
rawtitle: Dedication: In memory of {Luigi Ciminiera} 1954--2012 and In memory of {Luigi Dadda} 1923--2012
entry:
@InProceedings{Anonymous:2013:DML,
  author =       "Anonymous",
  title =        "Dedication: In memory of {Luigi Ciminiera} 1954--2012
                 and In memory of {Luigi Dadda} 1923--2012",
  crossref =     "IEEE:2013:PIS",
  pages =        "ix--xi",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.11",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-21; Biographies; Ciminiera, Luigi; Dadda, Luigi;
                 Obituaries",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2013:IOF
author: Anonymous
title: Intel overstates FPU accuracy
pages: ix--xi
day: 1
month: jun
monthnumber: 6
year: 2013
bibdate: Sat Jun 04 16:53:16 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.06.04 16:53:16 ???
URL: http://www.notabs.org/fpuaccuracy/
acknowledgement: ack-nhfb
howpublished: Web document
rawauthor: Anonymous
rawtitle: {Intel} overstates {FPU} accuracy
abstract:
For nearly 20 years Intel has claimed high accuracy for the transcendental floating point instructions in its PC processor products. Intel documentation for the 1993 Pentium states: On the Pentium processor, the worst case error on functions is less than 1 ulp when rounding to the nearest-even and less than 1.5 ulps when rounding in other modes. This claim has never been true for the instructions fsin, fcos, fsincos, and fptan. The red in the plots below show ranges where the error exceeds 1.0 ulp.

rawabstract:
For nearly 20 years Intel has claimed high accuracy for the transcendental floating point instructions in its PC processor products. Intel documentation for the 1993 Pentium states: On the Pentium processor, the worst case error on functions is less than 1 ulp when rounding to the nearest-even and less than 1.5 ulps when rounding in other modes. This claim has never been true for the instructions fsin, fcos, fsincos, and fptan. The red in the plots below show ranges where the error exceeds 1.0 ulp.

entry:
@Misc{Anonymous:2013:IOF,
  author =       "Anonymous",
  title =        "{Intel} overstates {FPU} accuracy",
  howpublished = "Web document",
  day =          "1",
  month =        jun,
  year =         "2013",
  bibdate =      "Sat Jun 04 16:53:16 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.notabs.org/fpuaccuracy/",
  abstract =     "For nearly 20 years Intel has claimed high accuracy
                 for the transcendental floating point instructions in
                 its PC processor products. Intel documentation for the
                 1993 Pentium states: On the Pentium processor, the
                 worst case error on functions is less than 1 ulp when
                 rounding to the nearest-even and less than 1.5 ulps
                 when rounding in other modes. This claim has never been
                 true for the instructions fsin, fcos, fsincos, and
                 fptan. The red in the plots below show ranges where the
                 error exceeds 1.0 ulp.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Antao:2013:CFA
author: Samuel Antao and Leonel Sousa
title: The CRNS framework and its application to programmable and reconfigurable cryptography
journal: j-TACO
volume: 9
number: 4
pages: 33:1--33:??
month: jan
monthnumber: 1
year: 2013
DOI: https://doi.org/10.1145/2400682.2400692
ISSN: 1544-3566 (print), 1544-3973 (electronic) OR 15443566 (print), 15443973 (electronic)
ISSNL: 1544-3566 OR 15443566
bibdate: Fri Jan 18 10:57:16 MST 2013
bibtimestamp: 2013.01.18 10:57:16 MST
fjournal: ACM Transactions on Architecture and Code Optimization (TACO)
acknowledgement: ack-nhfb
articleno: 33
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J924
rawauthor: Samuel Ant{\~a}o and Leonel Sousa
rawtitle: The {CRNS} framework and its application to programmable and reconfigurable cryptography
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/taco.bib

abstract:
This article proposes the Computing with the Residue Number System (CRNS) framework, which aims at the design automation of accelerators for Modular Arithmetic (MA). The framework provides a comprehensive set of tools ranging from a programming language and respective compiler to back-ends targeting parallel computation platforms such as Graphical Processing Units (GPUs) and reconfigurable hardware. Given an input algorithm described with a high-level programming language, the CRNS can be used to obtain in a few seconds the corresponding optimized Parallel Thread Execution (PTX) program ready to be run on GPUs or the Hardware Description Language (HDL) specification of a fully functional accelerator suitable for reconfigurable hardware and embedded systems. The resulting framework's implementations benefit from the Residue Number System (RNS) arithmetic's parallelization properties in a fully automated way. Designers do not need to be familiar with the mathematical details concerning the employed arithmetic, namely the RNS representation. In order to thoroughly describe and evaluate the proposed framework, experimental results obtained for the supported back-ends (GPU and HDL) are presented targeting the implementation of the modular exponentiation used in the Rivest--Shamir--Adleman (RSA) algorithm and Elliptic Curve (EC) point multiplication. Results suggest competitive latency and throughput with minimum design effort and overcoming all the development issues that arise in the specification and verification of dedicated solutions.

rawabstract:
This article proposes the Computing with the Residue Number System (CRNS) framework, which aims at the design automation of accelerators for Modular Arithmetic (MA). The framework provides a comprehensive set of tools ranging from a programming language and respective compiler to back-ends targeting parallel computation platforms such as Graphical Processing Units (GPUs) and reconfigurable hardware. Given an input algorithm described with a high-level programming language, the CRNS can be used to obtain in a few seconds the corresponding optimized Parallel Thread Execution (PTX) program ready to be run on GPUs or the Hardware Description Language (HDL) specification of a fully functional accelerator suitable for reconfigurable hardware and embedded systems. The resulting framework's implementations benefit from the Residue Number System (RNS) arithmetic's parallelization properties in a fully automated way. Designers do not need to be familiar with the mathematical details concerning the employed arithmetic, namely the RNS representation. In order to thoroughly describe and evaluate the proposed framework, experimental results obtained for the supported back-ends (GPU and HDL) are presented targeting the implementation of the modular exponentiation used in the Rivest--Shamir--Adleman (RSA) algorithm and Elliptic Curve (EC) point multiplication. Results suggest competitive latency and throughput with minimum design effort and overcoming all the development issues that arise in the specification and verification of dedicated solutions.

entry:
@Article{Antao:2013:CFA,
  author =       "Samuel Ant{\~a}o and Leonel Sousa",
  title =        "The {CRNS} framework and its application to
                 programmable and reconfigurable cryptography",
  journal =      j-TACO,
  volume =       "9",
  number =       "4",
  pages =        "33:1--33:??",
  month =        jan,
  year =         "2013",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/2400682.2400692",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Fri Jan 18 10:57:16 MST 2013",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  abstract =     "This article proposes the Computing with the Residue
                 Number System (CRNS) framework, which aims at the
                 design automation of accelerators for Modular
                 Arithmetic (MA). The framework provides a comprehensive
                 set of tools ranging from a programming language and
                 respective compiler to back-ends targeting parallel
                 computation platforms such as Graphical Processing
                 Units (GPUs) and reconfigurable hardware. Given an
                 input algorithm described with a high-level programming
                 language, the CRNS can be used to obtain in a few
                 seconds the corresponding optimized Parallel Thread
                 Execution (PTX) program ready to be run on GPUs or the
                 Hardware Description Language (HDL) specification of a
                 fully functional accelerator suitable for
                 reconfigurable hardware and embedded systems. The
                 resulting framework's implementations benefit from the
                 Residue Number System (RNS) arithmetic's
                 parallelization properties in a fully automated way.
                 Designers do not need to be familiar with the
                 mathematical details concerning the employed
                 arithmetic, namely the RNS representation. In order to
                 thoroughly describe and evaluate the proposed
                 framework, experimental results obtained for the
                 supported back-ends (GPU and HDL) are presented
                 targeting the implementation of the modular
                 exponentiation used in the Rivest--Shamir--Adleman
                 (RSA) algorithm and Elliptic Curve (EC) point
                 multiplication. Results suggest competitive latency and
                 throughput with minimum design effort and overcoming
                 all the development issues that arise in the
                 specification and verification of dedicated
                 solutions.",
  acknowledgement = ack-nhfb,
  articleno =    "33",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J924",
}


bibtype: inproceedings
filename: fparith.bib
label: Arnold:2013:DLN
author: Mark G. Arnold and Sylvain Collange
editor: IEEE
title: The denormal logarithmic number system
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 117--124
year: 2013
DOI: https://doi.org/10.1109/ASAP.2013.6567564
LCCN: QA76.5
bibdate: Mon May 30 07:23:44 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.05.30 07:23:44 ???
URL: http://ieeexplore.ieee.org/servlet/opac?punumber=6558539
acknowledgement: ack-nhfb
rawauthor: Mark G. Arnold and Sylvain Collange
raweditor: {IEEE}
rawtitle: The denormal logarithmic number system
booktitle:
24th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 5--7 June 2013

ISBN:
1-4799-0493-7, 1-4799-0494-5 (paperback), 1-4799-0492-9 OR 1479904937, 1479904945 (paperback), 1479904929

ISBN13:
978-1-4799-0493-8, 978-1-4799-0494-5 (paperback), 978-1-4799-0492-1 OR 9781479904938, 9781479904945 (paperback), 9781479904921

rawbooktitle:
{24th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 5--7 June 2013}

entry:
@InProceedings{Arnold:2013:DLN,
  author =       "Mark G. Arnold and Sylvain Collange",
  editor =       "{IEEE}",
  booktitle =    "{24th IEEE International Conference on
                 Application-Specific Systems, Architectures and
                 Processors (ASAP), 5--7 June 2013}",
  title =        "The denormal logarithmic number system",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "117--124",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ASAP.2013.6567564",
  ISBN =         "1-4799-0493-7, 1-4799-0494-5 (paperback),
                 1-4799-0492-9",
  ISBN-13 =      "978-1-4799-0493-8, 978-1-4799-0494-5 (paperback),
                 978-1-4799-0492-1",
  LCCN =         "QA76.5",
  bibdate =      "Mon May 30 07:23:44 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/servlet/opac?punumber=6558539",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Bagnara:2013:EBF
author: Roberto Bagnara and Matthieu Carlier and Roberta Gori and Arnaud Gotlieb
journal: arXiv.org
pages: 1--51
day: 18
month: aug
monthnumber: 8
year: 2013
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1308.3847
subject: Artificial Intelligence (cs.AI); Software Engineering (cs.SE)
acknowledgement: ack-nhfb
rawauthor: Roberto Bagnara and Matthieu Carlier and Roberta Gori and Arnaud Gotlieb
title:
Exploiting Binary Floating-Point Representations for Constraint Propagation: The Complete Unabridged Version

abstract:
Floating-point computations are quickly finding their way in the design of safety- and mission-critical systems, despite the fact that designing floating-point algorithms is significantly more difficult than designing integer algorithms. For this reason, verification and validation of floating-point computations is a hot research topic. An important verification technique, especially in some industrial sectors, is testing. However, generating test data for floating-point intensive programs proved to be a challenging problem. Existing approaches usually resort to random or search-based test data generation, but without symbolic reasoning it is almost impossible to generate test inputs that execute complex paths controlled by floating-point computations. Moreover, as constraint solvers over the reals or the rationals do not natively support the handling of rounding errors, the need arises for efficient constraint solvers over floating-point domains. In this paper, we present and fully justify improved algorithms for the propagation of arithmetic IEEE 754 binary floating-point constraints. The key point of these algorithms is a generalization of an idea by B. Marre and C. Michel that exploits a property of the representation of floating-point numbers.

rawabstract:
Floating-point computations are quickly finding their way in the design of safety- and mission-critical systems, despite the fact that designing floating-point algorithms is significantly more difficult than designing integer algorithms. For this reason, verification and validation of floating-point computations is a hot research topic. An important verification technique, especially in some industrial sectors, is testing. However, generating test data for floating-point intensive programs proved to be a challenging problem. Existing approaches usually resort to random or search-based test data generation, but without symbolic reasoning it is almost impossible to generate test inputs that execute complex paths controlled by floating-point computations. Moreover, as constraint solvers over the reals or the rationals do not natively support the handling of rounding errors, the need arises for efficient constraint solvers over floating-point domains. In this paper, we present and fully justify improved algorithms for the propagation of arithmetic IEEE 754 binary floating-point constraints. The key point of these algorithms is a generalization of an idea by B. Marre and C. Michel that exploits a property of the representation of floating-point numbers.

rawtitle:
Exploiting Binary Floating-Point Representations for Constraint Propagation: The Complete Unabridged Version

entry:
@Article{Bagnara:2013:EBF,
  author =       "Roberto Bagnara and Matthieu Carlier and Roberta Gori
                 and Arnaud Gotlieb",
  title =        "Exploiting Binary Floating-Point Representations for
                 Constraint Propagation: The Complete Unabridged
                 Version",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--51",
  day =          "18",
  month =        aug,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1308.3847",
  abstract =     "Floating-point computations are quickly finding their
                 way in the design of safety- and mission-critical
                 systems, despite the fact that designing floating-point
                 algorithms is significantly more difficult than
                 designing integer algorithms. For this reason,
                 verification and validation of floating-point
                 computations is a hot research topic. An important
                 verification technique, especially in some industrial
                 sectors, is testing. However, generating test data for
                 floating-point intensive programs proved to be a
                 challenging problem. Existing approaches usually resort
                 to random or search-based test data generation, but
                 without symbolic reasoning it is almost impossible to
                 generate test inputs that execute complex paths
                 controlled by floating-point computations. Moreover, as
                 constraint solvers over the reals or the rationals do
                 not natively support the handling of rounding errors,
                 the need arises for efficient constraint solvers over
                 floating-point domains. In this paper, we present and
                 fully justify improved algorithms for the propagation
                 of arithmetic IEEE 754 binary floating-point
                 constraints. The key point of these algorithms is a
                 generalization of an idea by B. Marre and C. Michel
                 that exploits a property of the representation of
                 floating-point numbers.",
  acknowledgement = ack-nhfb,
  subject =      "Artificial Intelligence (cs.AI); Software Engineering
                 (cs.SE)",
}


bibtype: inproceedings
filename: fparith.bib
label: Bailey:2013:KHP
author: David H. Bailey
title: Keynote I: High-precision computation: Applications and challenges
crossref: IEEE:2013:PIS
pages: 3--3
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.39
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
keywords: ARITH-21
acknowledgement: ack-nhfb
rawauthor: David H. Bailey
rawtitle: Keynote {I}: High-precision computation: Applications and challenges
entry:
@InProceedings{Bailey:2013:KHP,
  author =       "David H. Bailey",
  title =        "Keynote {I}: High-precision computation: Applications
                 and challenges",
  crossref =     "IEEE:2013:PIS",
  pages =        "3--3",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.39",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-21",
}


bibtype: inproceedings
filename: fparith.bib
label: Bajard:2013:FDR
author: Jean-Claude Bajard and Julien Eynard and Filippo Gandino
title: Fault Detection in RNS Montgomery Modular Multiplication
crossref: IEEE:2013:PIS
pages: 119--126
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.31
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Jean-Claude Bajard and Julien Eynard and Filippo Gandino
rawtitle: Fault Detection in {RNS} {Montgomery} Modular Multiplication
keywords:
ARITH-21; Base Conversions; Computer architecture; cryptographic functions; Cryptography; cryptography; fault attacks; Fault detection; fault detection; Fault Detection; fault diagnosis; fault injection; field programmable gate arrays; FPGA; GPU; Hardware; leak resistant arithmetic; modular arithmetic; Montgomery Reduction; Redundancy; Residue Number System; residue number systems; Resistance; RNS; RNS Montgomery modular multiplication; side channel attacks; Standards

entry:
@InProceedings{Bajard:2013:FDR,
  author =       "Jean-Claude Bajard and Julien Eynard and Filippo
                 Gandino",
  title =        "Fault Detection in {RNS} {Montgomery} Modular
                 Multiplication",
  crossref =     "IEEE:2013:PIS",
  pages =        "119--126",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.31",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-21; Base Conversions; Computer architecture;
                 cryptographic functions; Cryptography; cryptography;
                 fault attacks; Fault detection; fault detection; Fault
                 Detection; fault diagnosis; fault injection; field
                 programmable gate arrays; FPGA; GPU; Hardware; leak
                 resistant arithmetic; modular arithmetic; Montgomery
                 Reduction; Redundancy; Residue Number System; residue
                 number systems; Resistance; RNS; RNS Montgomery modular
                 multiplication; side channel attacks; Standards",
}


bibtype: article
filename: fparith.bib
label: Bao:2013:FDI
author: Tao Bao and Xiangyu Zhang
title: On-the-fly detection of instability problems in floating-point program execution
journal: j-SIGPLAN
volume: 48
number: 10
pages: 817--832
month: oct
monthnumber: 10
year: 2013
CODEN: SINODQ
DOI: https://doi.org/10.1145/2544173.2509526
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Mon Dec 9 09:19:33 MST 2013
bibtimestamp: 2013.12.09 09:19:33 MST
note: OOPSLA '13 conference proceedings.
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Tao Bao and Xiangyu Zhang
rawnote: OOPSLA '13 conference proceedings.
rawtitle: On-the-fly detection of instability problems in floating-point program execution
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib

abstract:
The machine representation of floating point values has limited precision such that errors may be introduced during execution. These errors may get propagated and magnified by the following operations, leading to instability problems, e.g., control flow path may be undesirably altered and faulty output may be emitted. In this paper, we develop an on-the-fly efficient monitoring technique that can predict if an execution is stable. The technique does not explicitly compute errors as doing so incurs high overhead. Instead, it detects possible places where an error becomes substantially inflated regarding the corresponding value, and then tags the value with one bit to denote that it has an inflated error. It then tracks inflation bit propagation, taking care of operations that may cut off such propagation. It reports instability if any inflation bit reaches a critical execution point, such as a predicate, where the inflated error may induce substantial execution difference, such as different execution paths. Our experiment shows that with appropriate thresholds, the technique can correctly detect that over 99.999996% of the inputs of all the programs we studied are stable while a traditional technique relying solely on inflation detection mistakenly classifies majority of the inputs as unstable for some of the programs. Compared to the state of the art technique that is based on high precision computation and causes several hundred times slowdown, our technique only causes 7.91 times slowdown on average and can report all the true unstable executions with the appropriate thresholds.

rawabstract:
The machine representation of floating point values has limited precision such that errors may be introduced during execution. These errors may get propagated and magnified by the following operations, leading to instability problems, e.g., control flow path may be undesirably altered and faulty output may be emitted. In this paper, we develop an on-the-fly efficient monitoring technique that can predict if an execution is stable. The technique does not explicitly compute errors as doing so incurs high overhead. Instead, it detects possible places where an error becomes substantially inflated regarding the corresponding value, and then tags the value with one bit to denote that it has an inflated error. It then tracks inflation bit propagation, taking care of operations that may cut off such propagation. It reports instability if any inflation bit reaches a critical execution point, such as a predicate, where the inflated error may induce substantial execution difference, such as different execution paths. Our experiment shows that with appropriate thresholds, the technique can correctly detect that over 99.999996\% of the inputs of all the programs we studied are stable while a traditional technique relying solely on inflation detection mistakenly classifies majority of the inputs as unstable for some of the programs. Compared to the state of the art technique that is based on high precision computation and causes several hundred times slowdown, our technique only causes 7.91 times slowdown on average and can report all the true unstable executions with the appropriate thresholds.

entry:
@Article{Bao:2013:FDI,
  author =       "Tao Bao and Xiangyu Zhang",
  title =        "On-the-fly detection of instability problems in
                 floating-point program execution",
  journal =      j-SIGPLAN,
  volume =       "48",
  number =       "10",
  pages =        "817--832",
  month =        oct,
  year =         "2013",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/2544173.2509526",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Mon Dec 9 09:19:33 MST 2013",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  note =         "OOPSLA '13 conference proceedings.",
  abstract =     "The machine representation of floating point values
                 has limited precision such that errors may be
                 introduced during execution. These errors may get
                 propagated and magnified by the following operations,
                 leading to instability problems, e.g., control flow
                 path may be undesirably altered and faulty output may
                 be emitted. In this paper, we develop an on-the-fly
                 efficient monitoring technique that can predict if an
                 execution is stable. The technique does not explicitly
                 compute errors as doing so incurs high overhead.
                 Instead, it detects possible places where an error
                 becomes substantially inflated regarding the
                 corresponding value, and then tags the value with one
                 bit to denote that it has an inflated error. It then
                 tracks inflation bit propagation, taking care of
                 operations that may cut off such propagation. It
                 reports instability if any inflation bit reaches a
                 critical execution point, such as a predicate, where
                 the inflated error may induce substantial execution
                 difference, such as different execution paths. Our
                 experiment shows that with appropriate thresholds, the
                 technique can correctly detect that over 99.999996\% of
                 the inputs of all the programs we studied are stable
                 while a traditional technique relying solely on
                 inflation detection mistakenly classifies majority of
                 the inputs as unstable for some of the programs.
                 Compared to the state of the art technique that is
                 based on high precision computation and causes several
                 hundred times slowdown, our technique only causes 7.91
                 times slowdown on average and can report all the true
                 unstable executions with the appropriate thresholds.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
}


bibtype: article
filename: fparith.bib
label: Barr:2013:ADF
author: Earl T. Barr and Thanh Vo and Vu Le and Zhendong Su
title: Automatic detection of floating-point exceptions
journal: j-SIGPLAN
volume: 48
number: 1
pages: 549--560
month: jan
monthnumber: 1
year: 2013
CODEN: SINODQ
DOI: https://doi.org/10.1145/2480359.2429133
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Mon Jul 1 17:15:03 MDT 2013
bibtimestamp: 2013.07.01 17:15:03 MDT
fjournal: ACM SIGPLAN Notices
remark: POPL '13 conference proceedings.
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Earl T. Barr and Thanh Vo and Vu Le and Zhendong Su
rawtitle: Automatic detection of floating-point exceptions
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib

abstract:
It is well-known that floating-point exceptions can be disastrous and writing exception-free numerical programs is very difficult. Thus, it is important to automatically detect such errors. In this paper, we present Ariadne, a practical symbolic execution system specifically designed and implemented for detecting floating-point exceptions. Ariadne systematically transforms a numerical program to explicitly check each exception triggering condition. Ariadne symbolically executes the transformed program using real arithmetic to find candidate real-valued inputs that can reach and trigger an exception. Ariadne converts each candidate input into a floating-point number, then tests it against the original program. In general, approximating floating-point arithmetic with real arithmetic can change paths from feasible to infeasible and vice versa. The key insight of this work is that, for the problem of detecting floating-point exceptions, this approximation works well in practice because, if one input reaches an exception, many are likely to, and at least one of them will do so over both floating-point and real arithmetic. To realize Ariadne, we also devised a novel, practical linearization technique to solve nonlinear constraints. We extensively evaluated Ariadne over 467 scalar functions in the widely used GNU Scientific Library (GSL). Our results show that Ariadne is practical and identifies a large number of real runtime exceptions in GSL. The GSL developers confirmed our preliminary findings and look forward to Ariadne's public release, which we plan to do in the near future.

rawabstract:
It is well-known that floating-point exceptions can be disastrous and writing exception-free numerical programs is very difficult. Thus, it is important to automatically detect such errors. In this paper, we present Ariadne, a practical symbolic execution system specifically designed and implemented for detecting floating-point exceptions. Ariadne systematically transforms a numerical program to explicitly check each exception triggering condition. Ariadne symbolically executes the transformed program using real arithmetic to find candidate real-valued inputs that can reach and trigger an exception. Ariadne converts each candidate input into a floating-point number, then tests it against the original program. In general, approximating floating-point arithmetic with real arithmetic can change paths from feasible to infeasible and vice versa. The key insight of this work is that, for the problem of detecting floating-point exceptions, this approximation works well in practice because, if one input reaches an exception, many are likely to, and at least one of them will do so over both floating-point and real arithmetic. To realize Ariadne, we also devised a novel, practical linearization technique to solve nonlinear constraints. We extensively evaluated Ariadne over 467 scalar functions in the widely used GNU Scientific Library (GSL). Our results show that Ariadne is practical and identifies a large number of real runtime exceptions in GSL. The GSL developers confirmed our preliminary findings and look forward to Ariadne's public release, which we plan to do in the near future.

entry:
@Article{Barr:2013:ADF,
  author =       "Earl T. Barr and Thanh Vo and Vu Le and Zhendong Su",
  title =        "Automatic detection of floating-point exceptions",
  journal =      j-SIGPLAN,
  volume =       "48",
  number =       "1",
  pages =        "549--560",
  month =        jan,
  year =         "2013",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/2480359.2429133",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Mon Jul 1 17:15:03 MDT 2013",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  abstract =     "It is well-known that floating-point exceptions can be
                 disastrous and writing exception-free numerical
                 programs is very difficult. Thus, it is important to
                 automatically detect such errors. In this paper, we
                 present Ariadne, a practical symbolic execution system
                 specifically designed and implemented for detecting
                 floating-point exceptions. Ariadne systematically
                 transforms a numerical program to explicitly check each
                 exception triggering condition. Ariadne symbolically
                 executes the transformed program using real arithmetic
                 to find candidate real-valued inputs that can reach and
                 trigger an exception. Ariadne converts each candidate
                 input into a floating-point number, then tests it
                 against the original program. In general, approximating
                 floating-point arithmetic with real arithmetic can
                 change paths from feasible to infeasible and vice
                 versa. The key insight of this work is that, for the
                 problem of detecting floating-point exceptions, this
                 approximation works well in practice because, if one
                 input reaches an exception, many are likely to, and at
                 least one of them will do so over both floating-point
                 and real arithmetic. To realize Ariadne, we also
                 devised a novel, practical linearization technique to
                 solve nonlinear constraints. We extensively evaluated
                 Ariadne over 467 scalar functions in the widely used
                 GNU Scientific Library (GSL). Our results show that
                 Ariadne is practical and identifies a large number of
                 real runtime exceptions in GSL. The GSL developers
                 confirmed our preliminary findings and look forward to
                 Ariadne's public release, which we plan to do in the
                 near future.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  remark =       "POPL '13 conference proceedings.",
}


bibtype: inproceedings
filename: fparith.bib
label: Boldo:2013:FVC
author: Sylvie Boldo and Jacques-Henri Jourdan and Xavier Leroy and Guillaume Melquiond
title: A Formally-Verified C Compiler Supporting Floating-Point Arithmetic
crossref: IEEE:2013:PIS
pages: 107--115
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.30
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo and Jacques-Henri Jourdan and Xavier Leroy and Guillaume Melquiond
rawtitle: A Formally-Verified {C} Compiler Supporting Floating-Point Arithmetic
keywords:
ARITH-21; ARM microprocessor; C compiler; Comp Cert compilation; Computer architecture; floating point arithmetic; floating-point arithmetic; floating-point semantic preservation; formal proof; formal verification; IEEE standards; IEEE-754 standard; Java; Libraries; mathematical specification; microprocessor chips; Optimization; PowerPC microprocessor; program compilers; Program processors; programming language; Semantics; Standards; verified compilation; x86-SSE2 microprocessor

entry:
@InProceedings{Boldo:2013:FVC,
  author =       "Sylvie Boldo and Jacques-Henri Jourdan and Xavier
                 Leroy and Guillaume Melquiond",
  title =        "A Formally-Verified {C} Compiler Supporting
                 Floating-Point Arithmetic",
  crossref =     "IEEE:2013:PIS",
  pages =        "107--115",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.30",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-21; ARM microprocessor; C compiler; Comp Cert
                 compilation; Computer architecture; floating point
                 arithmetic; floating-point arithmetic; floating-point
                 semantic preservation; formal proof; formal
                 verification; IEEE standards; IEEE-754 standard; Java;
                 Libraries; mathematical specification; microprocessor
                 chips; Optimization; PowerPC microprocessor; program
                 compilers; Program processors; programming language;
                 Semantics; Standards; verified compilation; x86-SSE2
                 microprocessor",
}


bibtype: inproceedings
filename: fparith.bib
label: Boldo:2013:HCA
author: Sylvie Boldo
title: How to Compute the Area of a Triangle: A Formal Revisit
crossref: IEEE:2013:PIS
pages: 91--98
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.29
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo
rawtitle: How to Compute the Area of a Triangle: A Formal Revisit
keywords:
Accuracy; Algorithm design and analysis; algorithm proof; algorithm theory; ARITH-21; Coq; Digital arithmetic; Electronic mail; Error analysis; floating point arithmetic; floating-point arithmetic; formal proof; Kahan algorithm; Libraries; mathematical value; Standards; theorem proving; triangle; triangle area; underflow

entry:
@InProceedings{Boldo:2013:HCA,
  author =       "Sylvie Boldo",
  title =        "How to Compute the Area of a Triangle: A Formal
                 Revisit",
  crossref =     "IEEE:2013:PIS",
  pages =        "91--98",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.29",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; Algorithm design and analysis; algorithm
                 proof; algorithm theory; ARITH-21; Coq; Digital
                 arithmetic; Electronic mail; Error analysis; floating
                 point arithmetic; floating-point arithmetic; formal
                 proof; Kahan algorithm; Libraries; mathematical value;
                 Standards; theorem proving; triangle; triangle area;
                 underflow",
}


bibtype: inproceedings
filename: fparith.bib
label: Brisebarre:2013:CBB
author: Nicolas Brisebarre and Marc Mezzarobba and Jean-Michel Muller and Christof Lauter
title: Comparison between Binary64 and Decimal64 Floating-Point Numbers
crossref: IEEE:2013:PIS
pages: 145--152
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.23
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Nicolas Brisebarre and Marc Mezzarobba and Jean-Michel Muller and Christof Lauter
rawtitle: Comparison between {Binary64} and {Decimal64} Floating-Point Numbers
keywords:
Accuracy; Approximation methods; ARITH-21; binary encoding; Binary64 floating-point numbers; binary64 FP number; Decimal Floating-Point; Decimal64 floating-point numbers; decimal64 FP number; Digital arithmetic; Encoding; encoding; first pass; floating point arithmetic; Floating-Point Arithmetic; Floating-Point Comparisons; FP arithmetic; Hardware; IEEE 754-2008 standard; IEEE standards; second pass; software-oriented algorithm; Standards; Testing; two-step algorithm

entry:
@InProceedings{Brisebarre:2013:CBB,
  author =       "Nicolas Brisebarre and Marc Mezzarobba and Jean-Michel
                 Muller and Christof Lauter",
  title =        "Comparison between {Binary64} and {Decimal64}
                 Floating-Point Numbers",
  crossref =     "IEEE:2013:PIS",
  pages =        "145--152",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.23",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; Approximation methods; ARITH-21; binary
                 encoding; Binary64 floating-point numbers; binary64 FP
                 number; Decimal Floating-Point; Decimal64
                 floating-point numbers; decimal64 FP number; Digital
                 arithmetic; Encoding; encoding; first pass; floating
                 point arithmetic; Floating-Point Arithmetic;
                 Floating-Point Comparisons; FP arithmetic; Hardware;
                 IEEE 754-2008 standard; IEEE standards; second pass;
                 software-oriented algorithm; Standards; Testing;
                 two-step algorithm",
}


bibtype: article
filename: fparith.bib
label: Carter:2013:ESF
author: Ashley R. Carter
title: Evolution of the Significant Figure Rules
journal: j-PHYS-TEACHER
volume: 51
number: 6
pages: 340--343
month: sep
monthnumber: 9
year: 2013
CODEN: PHTEAH
DOI: https://doi.org/10.1119/1.4818368
ISSN: 0031-921X (print), 1943-4928 (electronic) OR 0031921X (print), 19434928 (electronic)
ISSNL: 0031-921X OR 0031921X
bibdate: Mon May 21 11:31:50 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.05.21 11:31:50 ???
fjournal: The Physics Teacher
acknowledgement: ack-nhfb
journalURL: http://scitation.aip.org/content/aapt/journal/tpt
rawauthor: Ashley R. Carter
rawtitle: Evolution of the Significant Figure Rules
entry:
@Article{Carter:2013:ESF,
  author =       "Ashley R. Carter",
  title =        "Evolution of the Significant Figure Rules",
  journal =      j-PHYS-TEACHER,
  volume =       "51",
  number =       "6",
  pages =        "340--343",
  month =        sep,
  year =         "2013",
  CODEN =        "PHTEAH",
  DOI =          "https://doi.org/10.1119/1.4818368",
  ISSN =         "0031-921X (print), 1943-4928 (electronic)",
  ISSN-L =       "0031-921X",
  bibdate =      "Mon May 21 11:31:50 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "The Physics Teacher",
  journal-URL =  "http://scitation.aip.org/content/aapt/journal/tpt",
}


bibtype: inproceedings
filename: fparith.bib
label: Chabrier:2013:FMB
author: Thomas Chabrier and Arnaud Tisserand
title: On-the-Fly Multi-base Recoding for ECC Scalar Multiplication without Pre-computations
crossref: IEEE:2013:PIS
pages: 219--228
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.17
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Thomas Chabrier and Arnaud Tisserand
rawtitle: On-the-Fly Multi-base Recoding for {ECC} Scalar Multiplication without Pre-computations
keywords:
ARITH-21; base point multiples; cheap divisibility tests; Clocks; Cryptography; curve-level operations; DBNS; digital arithmetic; divisibility test; double-base number system; ECC scalar multiplication; elliptic curve cryptography; exact division by constant; fast recoding methods; field programmable gate arrays; Field programmable gate arrays; FPGA implementation; greedy algorithm; greedy algorithms; Hardware; MBNS; multibase number system; nonadjacent form; off-line conversion; on-the-fly multibase recoding; public key cryptography; scalar multiplication; scalar recoding; Standards; Table lookup

entry:
@InProceedings{Chabrier:2013:FMB,
  author =       "Thomas Chabrier and Arnaud Tisserand",
  title =        "On-the-Fly Multi-base Recoding for {ECC} Scalar
                 Multiplication without Pre-computations",
  crossref =     "IEEE:2013:PIS",
  pages =        "219--228",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.17",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-21; base point multiples; cheap divisibility
                 tests; Clocks; Cryptography; curve-level operations;
                 DBNS; digital arithmetic; divisibility test;
                 double-base number system; ECC scalar multiplication;
                 elliptic curve cryptography; exact division by
                 constant; fast recoding methods; field programmable
                 gate arrays; Field programmable gate arrays; FPGA
                 implementation; greedy algorithm; greedy algorithms;
                 Hardware; MBNS; multibase number system; nonadjacent
                 form; off-line conversion; on-the-fly multibase
                 recoding; public key cryptography; scalar
                 multiplication; scalar recoding; Standards; Table
                 lookup",
}


bibtype: article
filename: fparith.bib
label: Chen:2013:PGF
author: Doris Chen and Deshanand Singh
title: Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor applications
journal: j-TACO
volume: 9
number: 4
pages: 43:1--43:??
month: jan
monthnumber: 1
year: 2013
DOI: https://doi.org/10.1145/2400682.2400702
ISSN: 1544-3566 (print), 1544-3973 (electronic) OR 15443566 (print), 15443973 (electronic)
ISSNL: 1544-3566 OR 15443566
bibdate: Fri Jan 18 10:57:16 MST 2013
bibtimestamp: 2013.01.18 10:57:16 MST
fjournal: ACM Transactions on Architecture and Code Optimization (TACO)
acknowledgement: ack-nhfb
articleno: 43
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J924
rawauthor: Doris Chen and Deshanand Singh
rawtitle: Profile-guided floating- to fixed-point conversion for hybrid {FPGA}-processor applications
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/taco.bib

abstract:
The key to enabling widespread use of FPGAs for algorithm acceleration is to allow programmers to create efficient designs without the time-consuming hardware design process. Programmers are used to developing scientific and mathematical algorithms in high-level languages (C/C++) using floating point data types. Although easy to implement, the dynamic range provided by floating point is not necessary in many applications; more efficient implementations can be realized using fixed point arithmetic. While this topic has been studied previously [Han et al. 2006; Olson et al. 1999; Gaffar et al. 2004; Aamodt and Chow 1999], the degree of full automation has always been lacking. We present a novel design flow for cases where FPGAs are used to offload computations from a microprocessor. Our LLVM-based algorithm inserts value profiling code into an unmodified C/C++ application to guide its automatic conversion to fixed point. This allows for fast and accurate design space exploration on a host microprocessor before any accelerators are mapped to the FPGA. Through experimental results, we demonstrate that fixed-point conversion can yield resource savings of up to 2x--3x reductions. Embedded RAM usage is minimized, and 13%--22% higher $ F_rm max $ than the original floating-point implementation is observed. In a case study, we show that 17% reduction in logic and 24% reduction in register usage can be realized by using our algorithm in conjunction with a High-Level Synthesis (HLS) tool.

rawabstract:
The key to enabling widespread use of FPGAs for algorithm acceleration is to allow programmers to create efficient designs without the time-consuming hardware design process. Programmers are used to developing scientific and mathematical algorithms in high-level languages (C/C++) using floating point data types. Although easy to implement, the dynamic range provided by floating point is not necessary in many applications; more efficient implementations can be realized using fixed point arithmetic. While this topic has been studied previously [Han et al. 2006; Olson et al. 1999; Gaffar et al. 2004; Aamodt and Chow 1999], the degree of full automation has always been lacking. We present a novel design flow for cases where FPGAs are used to offload computations from a microprocessor. Our LLVM-based algorithm inserts value profiling code into an unmodified C/C++ application to guide its automatic conversion to fixed point. This allows for fast and accurate design space exploration on a host microprocessor before any accelerators are mapped to the FPGA. Through experimental results, we demonstrate that fixed-point conversion can yield resource savings of up to 2x--3x reductions. Embedded RAM usage is minimized, and 13\%--22\% higher $ F_{\rm max} $ than the original floating-point implementation is observed. In a case study, we show that 17\% reduction in logic and 24\% reduction in register usage can be realized by using our algorithm in conjunction with a High-Level Synthesis (HLS) tool.

entry:
@Article{Chen:2013:PGF,
  author =       "Doris Chen and Deshanand Singh",
  title =        "Profile-guided floating- to fixed-point conversion for
                 hybrid {FPGA}-processor applications",
  journal =      j-TACO,
  volume =       "9",
  number =       "4",
  pages =        "43:1--43:??",
  month =        jan,
  year =         "2013",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/2400682.2400702",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Fri Jan 18 10:57:16 MST 2013",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  abstract =     "The key to enabling widespread use of FPGAs for
                 algorithm acceleration is to allow programmers to
                 create efficient designs without the time-consuming
                 hardware design process. Programmers are used to
                 developing scientific and mathematical algorithms in
                 high-level languages (C/C++) using floating point data
                 types. Although easy to implement, the dynamic range
                 provided by floating point is not necessary in many
                 applications; more efficient implementations can be
                 realized using fixed point arithmetic. While this topic
                 has been studied previously [Han et al. 2006; Olson et
                 al. 1999; Gaffar et al. 2004; Aamodt and Chow 1999],
                 the degree of full automation has always been lacking.
                 We present a novel design flow for cases where FPGAs
                 are used to offload computations from a microprocessor.
                 Our LLVM-based algorithm inserts value profiling code
                 into an unmodified C/C++ application to guide its
                 automatic conversion to fixed point. This allows for
                 fast and accurate design space exploration on a host
                 microprocessor before any accelerators are mapped to
                 the FPGA. Through experimental results, we demonstrate
                 that fixed-point conversion can yield resource savings
                 of up to 2x--3x reductions. Embedded RAM usage is
                 minimized, and 13\%--22\% higher $ F_{\rm max} $ than
                 the original floating-point implementation is observed.
                 In a case study, we show that 17\% reduction in logic
                 and 24\% reduction in register usage can be realized by
                 using our algorithm in conjunction with a High-Level
                 Synthesis (HLS) tool.",
  acknowledgement = ack-nhfb,
  articleno =    "43",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J924",
}


bibtype: inproceedings
filename: fparith.bib
label: Chevillard:2013:MPE
author: Sylvain Chevillard and Marc Mezzarobba
title: Multiple-Precision Evaluation of the Airy Ai Function with Reduced Cancellation
crossref: IEEE:2013:PIS
pages: 175--182
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.33
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Sylvain Chevillard and Marc Mezzarobba
rawtitle: Multiple-Precision Evaluation of the {Airy} {Ai} Function with Reduced Cancellation
keywords:
Accuracy; Airy Ai function; algorithm; Algorithm design and analysis; Approximation algorithms; Approximation methods; arbitrary precision; ARITH-21; asymptotics; cancellation reduction; classical Miller algorithm; correct rounding; differential equations; Equations; error bounds; ill-conditioned three-term recurrence; linear ordinary differential equation; Miller method; multiple-precision evaluation; nonnegative Taylor expansions; numerical evaluation; series (mathematics); series expansion; Shape; Special functions; Taylor coefficients; Taylor series

entry:
@InProceedings{Chevillard:2013:MPE,
  author =       "Sylvain Chevillard and Marc Mezzarobba",
  title =        "Multiple-Precision Evaluation of the {Airy} {Ai}
                 Function with Reduced Cancellation",
  crossref =     "IEEE:2013:PIS",
  pages =        "175--182",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.33",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; Airy Ai function; algorithm; Algorithm
                 design and analysis; Approximation algorithms;
                 Approximation methods; arbitrary precision; ARITH-21;
                 asymptotics; cancellation reduction; classical Miller
                 algorithm; correct rounding; differential equations;
                 Equations; error bounds; ill-conditioned three-term
                 recurrence; linear ordinary differential equation;
                 Miller method; multiple-precision evaluation;
                 nonnegative Taylor expansions; numerical evaluation;
                 series (mathematics); series expansion; Shape; Special
                 functions; Taylor coefficients; Taylor series",
}


bibtype: article
filename: fparith.bib
label: Cleveland:2013:OIR
author: Mathew A. Cleveland and Thomas A. Brunner and Nicholas A. Gentile and Jeffrey A. Keasler
journal: j-J-COMPUT-PHYS
volume: 251
pages: 223--236
day: 15
month: oct
monthnumber: 10
year: 2013
CODEN: JCTPAH
DOI: https://doi.org/10.1016/j.jcp.2013.05.041
ISSN: 0021-9991 (print), 1090-2716 (electronic) OR 00219991 (print), 10902716 (electronic)
ISSNL: 0021-9991 OR 00219991
bibdate: Tue Aug 6 11:36:34 MDT 2013
bibtimestamp: 2013.08.06 11:36:34 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0021999113004075
fjournal: Journal of Computational Physics
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00219991
rawauthor: Mathew A. Cleveland and Thomas A. Brunner and Nicholas A. Gentile and Jeffrey A. Keasler
title:
Obtaining identical results with double precision global accuracy on different numbers of processors in parallel particle Monte Carlo simulations

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jcomputphys2010.bib

rawtitle:
Obtaining identical results with double precision global accuracy on different numbers of processors in parallel particle {Monte Carlo} simulations

entry:
@Article{Cleveland:2013:OIR,
  author =       "Mathew A. Cleveland and Thomas A. Brunner and Nicholas
                 A. Gentile and Jeffrey A. Keasler",
  title =        "Obtaining identical results with double precision
                 global accuracy on different numbers of processors in
                 parallel particle {Monte Carlo} simulations",
  journal =      j-J-COMPUT-PHYS,
  volume =       "251",
  number =       "??",
  pages =        "223--236",
  day =          "15",
  month =        oct,
  year =         "2013",
  CODEN =        "JCTPAH",
  DOI =          "https://doi.org/10.1016/j.jcp.2013.05.041",
  ISSN =         "0021-9991 (print), 1090-2716 (electronic)",
  ISSN-L =       "0021-9991",
  bibdate =      "Tue Aug 6 11:36:34 MDT 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputphys2010.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0021999113004075",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational Physics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00219991",
  keywords =     "accurate floating-point summation",
}


bibtype: techreport
filename: fparith.bib
label: Corden:2013:DFP
author: Martyn Corden
type: Report
institution: inst-INTEL
address: inst-INTEL:adr
pages: 6
year: 2013
bibdate: Sat Oct 31 06:56:03 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.10.31 06:56:03 ???
acknowledgement: ack-nhfb
rawauthor: Martyn Corden
title:
Differences in Floating-Point Arithmetic Between Intel Xeon Processors and the Intel Xeon Phi Coprocessor

URL:
https://software.intel.com/en-us/articles/differences-in-floating-point-arithmetic-between-intel-xeon-processors-and-the-intel-xeon; https://software.intel.com/file/420203/download

rawtitle:
Differences in Floating-Point Arithmetic Between {Intel Xeon} Processors and the {Intel Xeon Phi} Coprocessor

entry:
@TechReport{Corden:2013:DFP,
  author =       "Martyn Corden",
  title =        "Differences in Floating-Point Arithmetic Between
                 {Intel Xeon} Processors and the {Intel Xeon Phi}
                 Coprocessor",
  type =         "Report",
  institution =  inst-INTEL,
  address =      inst-INTEL:adr,
  pages =        "6",
  year =         "2013",
  bibdate =      "Sat Oct 31 06:56:03 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://software.intel.com/en-us/articles/differences-in-floating-point-arithmetic-between-intel-xeon-processors-and-the-intel-xeon;
                 https://software.intel.com/file/420203/download",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Cornea:2013:PAR
author: Marius Cornea
title: Precision, Accuracy, and Rounding Error Propagation in Exascale Computing
crossref: IEEE:2013:PIS
pages: 231--234
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.42
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Marius Cornea
rawtitle: Precision, Accuracy, and Rounding Error Propagation in Exascale Computing
keywords:
Accuracy; ARITH-21; Computational modeling; computer architects; Digital arithmetic; exascale computing; exascale level computers; Hardware; parallel machines; Parallel processing; rounding error propagation; supercomputers; Supercomputers

entry:
@InProceedings{Cornea:2013:PAR,
  author =       "Marius Cornea",
  title =        "Precision, Accuracy, and Rounding Error Propagation in
                 Exascale Computing",
  crossref =     "IEEE:2013:PIS",
  pages =        "231--234",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.42",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; ARITH-21; Computational modeling; computer
                 architects; Digital arithmetic; exascale computing;
                 exascale level computers; Hardware; parallel machines;
                 Parallel processing; rounding error propagation;
                 supercomputers; Supercomputers",
}


bibtype: article
filename: fparith.bib
label: De:2013:FIM
author: Anindya De and Piyush P. Kurur and Chandan Saha and Ramprasad Saptharishi
title: Fast Integer Multiplication Using Modular Arithmetic
journal: j-SIAM-J-COMPUT
volume: 42
number: 2
pages: 685--699
year: 2013
CODEN: SMJCAT
DOI: https://doi.org/10.1137/100811167
ISSN: 0097-5397 (print), 1095-7111 (electronic) OR 00975397 (print), 10957111 (electronic)
ISSNL: 0097-5397 OR 00975397
bibdate: Tue Feb 11 17:21:19 MST 2014
bibtimestamp: 2014.02.11 17:21:19 MST
fjournal: SIAM Journal on Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sicomp
onlinedate: January 2013
rawauthor: Anindya De and Piyush P. Kurur and Chandan Saha and Ramprasad Saptharishi
rawtitle: Fast Integer Multiplication Using Modular Arithmetic
bibsource:
http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/42/2; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjcomput.bib

entry:
@Article{De:2013:FIM,
  author =       "Anindya De and Piyush P. Kurur and Chandan Saha and
                 Ramprasad Saptharishi",
  title =        "Fast Integer Multiplication Using Modular Arithmetic",
  journal =      j-SIAM-J-COMPUT,
  volume =       "42",
  number =       "2",
  pages =        "685--699",
  month =        "????",
  year =         "2013",
  CODEN =        "SMJCAT",
  DOI =          "https://doi.org/10.1137/100811167",
  ISSN =         "0097-5397 (print), 1095-7111 (electronic)",
  ISSN-L =       "0097-5397",
  bibdate =      "Tue Feb 11 17:21:19 MST 2014",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toclist/SICOMP/42/2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjcomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Computing",
  journal-URL =  "http://epubs.siam.org/sicomp",
  onlinedate =   "January 2013",
}


bibtype: article
filename: fparith.bib
label: deDinechin:2013:FPE
author: Florent de Dinechin and Pedro Echeverria and Marisa Lopez-Vallejo and Bogdan Pasca
title: Floating-Point Exponentiation Units for Reconfigurable Computing
journal: j-TRETS
volume: 6
number: 1
pages: 4:1--4:??
month: may
monthnumber: 5
year: 2013
DOI: https://doi.org/10.1145/2457443.2457447
ISSN: 1936-7406 (print), 1936-7414 (electronic) OR 19367406 (print), 19367414 (electronic)
ISSNL: 1936-7406 OR 19367406
bibdate: Thu Mar 13 08:09:42 MDT 2014
bibtimestamp: 2014.03.13 08:09:42 MDT
fjournal: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
acknowledgement: ack-nhfb
articleno: 4
journalURL: http://portal.acm.org/toc.cfm?id=J1151
rawauthor: Florent de Dinechin and Pedro Echeverr{\'\i}a and Marisa L{\'o}pez-Vallejo and Bogdan Pasca
rawtitle: Floating-Point Exponentiation Units for Reconfigurable Computing
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/trets.bib

abstract:
The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function $ x^y $ as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floating-point multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.

rawabstract:
The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function $ x^y $ as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floating-point multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.

entry:
@Article{deDinechin:2013:FPE,
  author =       "Florent de Dinechin and Pedro Echeverr{\'\i}a and
                 Marisa L{\'o}pez-Vallejo and Bogdan Pasca",
  title =        "Floating-Point Exponentiation Units for Reconfigurable
                 Computing",
  journal =      j-TRETS,
  volume =       "6",
  number =       "1",
  pages =        "4:1--4:??",
  month =        may,
  year =         "2013",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/2457443.2457447",
  ISSN =         "1936-7406 (print), 1936-7414 (electronic)",
  ISSN-L =       "1936-7406",
  bibdate =      "Thu Mar 13 08:09:42 MDT 2014",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/trets.bib",
  abstract =     "The high performance and capacity of current FPGAs
                 makes them suitable as acceleration co-processors. This
                 article studies the implementation, for such
                 accelerators, of the floating-point power function $
                 x^y $ as defined by the C99 and IEEE 754-2008
                 standards, generalized here to arbitrary exponent and
                 mantissa sizes. Last-bit accuracy at the smallest
                 possible cost is obtained thanks to a careful study of
                 the various subcomponents: a floating-point logarithm,
                 a modified floating-point exponential, and a truncated
                 floating-point multiplier. A parameterized architecture
                 generator in the open-source FloPoCo project is
                 presented in details and evaluated.",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Transactions on Reconfigurable Technology and
                 Systems (TRETS)",
  journal-URL =  "http://portal.acm.org/toc.cfm?id=J1151",
}


bibtype: article
filename: fparith.bib
label: deDinechin:2013:FPT
author: Florent de Dinechin and Matei Istoan and Guillaume Sergent
title: Fixed-point trigonometric functions on FPGAs
journal: j-COMP-ARCH-NEWS
volume: 41
number: 5
pages: 83--88
month: dec
monthnumber: 12
year: 2013
CODEN: CANED2
DOI: https://doi.org/10.1145/2641361.2641375
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Mon Aug 18 17:12:43 MDT 2014
bibtimestamp: 2014.08.18 17:12:43 MDT
fjournal: ACM SIGARCH Computer Architecture News
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J89
rawauthor: Florent de Dinechin and Matei Istoan and Guillaume Sergent
rawtitle: Fixed-point trigonometric functions on {FPGAs}
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigarch.bib

abstract:
Three approaches for computing sines and cosines on FPGAs are studied in this paper, with a focus of high-throughput pipelined architecture, and state-of-the-art implementation techniques. The first approach is the classical CORDIC iteration, for which we suggest a reduced iteration technique and fine optimizations in datapath width and latency. The second is an ad-hoc architecture specifically designed around trigonometric identities. The third uses a generic table- and DSP-based polynomial approximator. These three architectures are implemented and compared in the FloPoCo framework.

rawabstract:
Three approaches for computing sines and cosines on FPGAs are studied in this paper, with a focus of high-throughput pipelined architecture, and state-of-the-art implementation techniques. The first approach is the classical CORDIC iteration, for which we suggest a reduced iteration technique and fine optimizations in datapath width and latency. The second is an ad-hoc architecture specifically designed around trigonometric identities. The third uses a generic table- and DSP-based polynomial approximator. These three architectures are implemented and compared in the FloPoCo framework.

entry:
@Article{deDinechin:2013:FPT,
  author =       "Florent de Dinechin and Matei Istoan and Guillaume
                 Sergent",
  title =        "Fixed-point trigonometric functions on {FPGAs}",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "41",
  number =       "5",
  pages =        "83--88",
  month =        dec,
  year =         "2013",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/2641361.2641375",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 18 17:12:43 MDT 2014",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Three approaches for computing sines and cosines on
                 FPGAs are studied in this paper, with a focus of
                 high-throughput pipelined architecture, and
                 state-of-the-art implementation techniques. The first
                 approach is the classical CORDIC iteration, for which
                 we suggest a reduced iteration technique and fine
                 optimizations in datapath width and latency. The second
                 is an ad-hoc architecture specifically designed around
                 trigonometric identities. The third uses a generic
                 table- and DSP-based polynomial approximator. These
                 three architectures are implemented and compared in the
                 FloPoCo framework.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
}


bibtype: article
filename: fparith.bib
label: deDinechin:2013:ZRT
author: Florent de Dinechin and Christoph Lauter and Jean-Michel Muller and Serge Torres
title: On Ziv's rounding test
journal: j-TOMS
volume: 39
number: 4
pages: 25:1--25:19
month: jul
monthnumber: 7
year: 2013
CODEN: ACMSCU
DOI: https://doi.org/10.1145/2491491.2491495
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Fri Jul 19 17:20:56 MDT 2013
bibtimestamp: 2013.07.19 17:20:56 MDT
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 25
journalURL: https://dl.acm.org/loi/toms
rawauthor: Florent de Dinechin and Christoph Lauter and Jean-Michel Muller and Serge Torres
rawtitle: On {Ziv}'s rounding test
abstract:
A very simple test, introduced by Ziv, allows one to determine if an approximation to the value f(x) of an elementary function at a given point x suffices to return the floating-point number nearest f(x). The same test may be used when implementing floating-point operations with input and output operands of different formats, using arithmetic operators tailored for manipulating operands of the same format. That test depends on a ``magic constant'' e. We show how to choose that constant e to make the test reliable and efficient. Various cases are considered, depending on the availability of an fma instruction, and on the range of f(x).

rawabstract:
A very simple test, introduced by Ziv, allows one to determine if an approximation to the value f(x) of an elementary function at a given point x suffices to return the floating-point number nearest f(x). The same test may be used when implementing floating-point operations with input and output operands of different formats, using arithmetic operators tailored for manipulating operands of the same format. That test depends on a ``magic constant'' e. We show how to choose that constant e to make the test reliable and efficient. Various cases are considered, depending on the availability of an fma instruction, and on the range of f(x).

entry:
@Article{deDinechin:2013:ZRT,
  author =       "Florent de Dinechin and Christoph Lauter and
                 Jean-Michel Muller and Serge Torres",
  title =        "On {Ziv}'s rounding test",
  journal =      j-TOMS,
  volume =       "39",
  number =       "4",
  pages =        "25:1--25:19",
  month =        jul,
  year =         "2013",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/2491491.2491495",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Fri Jul 19 17:20:56 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toms/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  abstract =     "A very simple test, introduced by Ziv, allows one to
                 determine if an approximation to the value f(x) of an
                 elementary function at a given point x suffices to
                 return the floating-point number nearest f(x). The same
                 test may be used when implementing floating-point
                 operations with input and output operands of different
                 formats, using arithmetic operators tailored for
                 manipulating operands of the same format. That test
                 depends on a ``magic constant'' e. We show how to
                 choose that constant e to make the test reliable and
                 efficient. Various cases are considered, depending on
                 the availability of an fma instruction, and on the
                 range of f(x).",
  acknowledgement = ack-nhfb,
  articleno =    "25",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: misc
filename: fparith.bib
label: Demmel:2013:ERF
author: James Demmel and Hong Diep Nguyen
title: Efficient Reproducible Floating-Point Reduction Operations on Large Scale Systems
pages: 25:1--25:19
day: 8--12
month: jul
monthnumber: 7
year: 2013
bibdate: Mon Jan 04 15:49:09 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.01.04 15:49:09 ???
URL: http://bebop.cs.berkeley.edu/reproblas/docs/talks/SIAM_AN13.pdf
acknowledgement: ack-nhfb
howpublished: SIAM AN13 talk slides.
rawauthor: James Demmel and Hong Diep Nguyen
rawtitle: Efficient Reproducible Floating-Point Reduction Operations on Large Scale Systems
entry:
@Misc{Demmel:2013:ERF,
  author =       "James Demmel and Hong Diep Nguyen",
  title =        "Efficient Reproducible Floating-Point Reduction
                 Operations on Large Scale Systems",
  howpublished = "SIAM AN13 talk slides.",
  day =          "8--12",
  month =        jul,
  year =         "2013",
  bibdate =      "Mon Jan 04 15:49:09 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://bebop.cs.berkeley.edu/reproblas/docs/talks/SIAM_AN13.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Demmel:2013:FRF
author: James Demmel and Hong Diep Nguyen
title: Fast Reproducible Floating-Point Summation
crossref: IEEE:2013:PIS
pages: 163--172
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.9
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
URL: http://www.eecs.berkeley.edu/~hdnguyen/public/papers/ARITH21_Fast_Sum.pdf
acknowledgement: ack-nhfb
rawauthor: James Demmel and Hong Diep Nguyen
rawtitle: Fast Reproducible Floating-Point Summation
keywords:
Accuracy; Algorithm design and analysis; ARITH-21; correct rounding; correctness check; debugging; dynamic scheduling; Educational institutions; error-free vector transformation; floating point arithmetic; floating point nonassociativity; floating-point; floating-point operation; floating-point summation; Numerical analysis; parallel computing resource; Parallel processing; parallel processing; parallelism; Program processors; reduction operation; reproducibility; reproducibility property; rounding error; rounding mode; Rump algorithm; scheduling; summation; summation order; Vectors

entry:
@InProceedings{Demmel:2013:FRF,
  author =       "James Demmel and Hong Diep Nguyen",
  title =        "Fast Reproducible Floating-Point Summation",
  crossref =     "IEEE:2013:PIS",
  pages =        "163--172",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.9",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.eecs.berkeley.edu/~hdnguyen/public/papers/ARITH21_Fast_Sum.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; Algorithm design and analysis; ARITH-21;
                 correct rounding; correctness check; debugging; dynamic
                 scheduling; Educational institutions; error-free vector
                 transformation; floating point arithmetic; floating
                 point nonassociativity; floating-point; floating-point
                 operation; floating-point summation; Numerical
                 analysis; parallel computing resource; Parallel
                 processing; parallel processing; parallelism; Program
                 processors; reduction operation; reproducibility;
                 reproducibility property; rounding error; rounding
                 mode; Rump algorithm; scheduling; summation; summation
                 order; Vectors",
}


bibtype: inproceedings
filename: fparith.bib
label: Demmel:2013:NRA
author: James Demmel and Hong Diep Nguyen
title: Numerical Reproducibility and Accuracy at Exascale
crossref: IEEE:2013:PIS
pages: 235--237
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.43
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: James Demmel and Hong Diep Nguyen
rawtitle: Numerical Reproducibility and Accuracy at Exascale
URL:
http://bebop.cs.berkeley.edu/reproblas/docs/talks/ARITH21_ExaScale.pdf; http://www.eecs.berkeley.edu/~hdnguyen/public/papers/ARITH21_ExaScale.pdf

keywords:
Accuracy; addition; ARITH-21; Computational modeling; Digital arithmetic; dynamic scheduling; Educational institutions; exascale computing; floating point arithmetic; floating point operations; Hardware; hardware heterogeneity; hardware trends; intermittent failures; numerical accuracy; numerical reproducibility; parallel processing; Program processors; Shape

entry:
@InProceedings{Demmel:2013:NRA,
  author =       "James Demmel and Hong Diep Nguyen",
  title =        "Numerical Reproducibility and Accuracy at Exascale",
  crossref =     "IEEE:2013:PIS",
  pages =        "235--237",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.43",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://bebop.cs.berkeley.edu/reproblas/docs/talks/ARITH21_ExaScale.pdf;
                 http://www.eecs.berkeley.edu/~hdnguyen/public/papers/ARITH21_ExaScale.pdf",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; addition; ARITH-21; Computational modeling;
                 Digital arithmetic; dynamic scheduling; Educational
                 institutions; exascale computing; floating point
                 arithmetic; floating point operations; Hardware;
                 hardware heterogeneity; hardware trends; intermittent
                 failures; numerical accuracy; numerical
                 reproducibility; parallel processing; Program
                 processors; Shape",
}


bibtype: misc
filename: fparith.bib
label: Demmel:2013:RRB
author: James Demmel and Hong Diep Nguyen
title: ReproBLAS: Reproducible BLAS
pages: 235--237
day: 22
month: nov
monthnumber: 11
year: 2013
bibdate: Mon Jan 04 15:49:09 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.01.04 15:49:09 ???
URL: http://bebop.cs.berkeley.edu/reproblas/docs/talks/SC13.pdf
acknowledgement: ack-nhfb
howpublished: SC'13 talk slides.
rawauthor: James Demmel and Hong Diep Nguyen
rawtitle: {ReproBLAS}: Reproducible {BLAS}
entry:
@Misc{Demmel:2013:RRB,
  author =       "James Demmel and Hong Diep Nguyen",
  title =        "{ReproBLAS}: Reproducible {BLAS}",
  howpublished = "SC'13 talk slides.",
  day =          "22",
  month =        nov,
  year =         "2013",
  bibdate =      "Mon Jan 04 15:49:09 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://bebop.cs.berkeley.edu/reproblas/docs/talks/SC13.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Detrey:2013:RCF
author: Jeremie Detrey and Pierrick Gaudry and Marion Videau
title: Relation Collection for the Function Field Sieve
crossref: IEEE:2013:PIS
pages: 201--210
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.28
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: J{\'e}r{\'e}mie Detrey and Pierrick Gaudry and Marion Videau
rawtitle: Relation Collection for the Function Field Sieve
keywords:
algorithmic techniques; ARITH-21; Arrays; cache storage; cache-aware sieving algorithms; cryptographic size; Cryptography; discrete logarithm; FFS; finite-field arithmetic; Function Field Sieve; function field sieve; Lattices; low-degree prime ideals; medium-to record-sized computations; polynomial arithmetic; polynomial arithmetic technique; polynomials; Polynomials; public key cryptography; record-sized discrete-logarithm computations; relation collection step; small-characteristic finite fields; Vectors

entry:
@InProceedings{Detrey:2013:RCF,
  author =       "J{\'e}r{\'e}mie Detrey and Pierrick Gaudry and Marion
                 Videau",
  title =        "Relation Collection for the Function Field Sieve",
  crossref =     "IEEE:2013:PIS",
  pages =        "201--210",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.28",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "algorithmic techniques; ARITH-21; Arrays; cache
                 storage; cache-aware sieving algorithms; cryptographic
                 size; Cryptography; discrete logarithm; FFS;
                 finite-field arithmetic; Function Field Sieve; function
                 field sieve; Lattices; low-degree prime ideals;
                 medium-to record-sized computations; polynomial
                 arithmetic; polynomial arithmetic technique;
                 polynomials; Polynomials; public key cryptography;
                 record-sized discrete-logarithm computations; relation
                 collection step; small-characteristic finite fields;
                 Vectors",
}


bibtype: inproceedings
filename: fparith.bib
label: Dimitrov:2013:ALI
author: Vassil Dimitrov and Kimmo Jarvinen
title: Another Look at Inversions over Binary Fields
crossref: IEEE:2013:PIS
pages: 211--218
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.25
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Vassil Dimitrov and Kimmo J{\"a}rvinen
rawtitle: Another Look at Inversions over Binary Fields
keywords:
Algorithm design and analysis; ARITH-21; binary fields; binary Galois fields; double-base representations; Galois fields; hardware implementations; inversion algorithms; Itoh-Tsujii algorithm; NIST; Polynomials; Prediction algorithms; public key cryptography; public key cryptosystems; Signal processing algorithms; Software; Software algorithms; software implementations; squaring computation; triple-base representations

entry:
@InProceedings{Dimitrov:2013:ALI,
  author =       "Vassil Dimitrov and Kimmo J{\"a}rvinen",
  title =        "Another Look at Inversions over Binary Fields",
  crossref =     "IEEE:2013:PIS",
  pages =        "211--218",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.25",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithm design and analysis; ARITH-21; binary
                 fields; binary Galois fields; double-base
                 representations; Galois fields; hardware
                 implementations; inversion algorithms; Itoh-Tsujii
                 algorithm; NIST; Polynomials; Prediction algorithms;
                 public key cryptography; public key cryptosystems;
                 Signal processing algorithms; Software; Software
                 algorithms; software implementations; squaring
                 computation; triple-base representations",
}


bibtype: article
filename: fparith.bib
label: Dingle:2013:RIT
author: Nicholas J. Dingle and Nicholas J. Higham
title: Reducing the influence of tiny normwise relative errors on performance profiles
journal: j-TOMS
volume: 39
number: 4
pages: 24:1--24:11
month: jul
monthnumber: 7
year: 2013
CODEN: ACMSCU
DOI: https://doi.org/10.1145/2491491.2491494
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Fri Jul 19 17:20:56 MDT 2013
bibtimestamp: 2013.07.19 17:20:56 MDT
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 24
journalURL: https://dl.acm.org/loi/toms
rawauthor: Nicholas J. Dingle and Nicholas J. Higham
rawtitle: Reducing the influence of tiny normwise relative errors on performance profiles
bibsource:
http://www.acm.org/pubs/contents/journals/toms/; https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

abstract:
It is a widespread but little-noticed phenomenon that the normwise relative error $ || x - y || / || x || $ of vectors $x$ and $y$ of floating point numbers of the same precision, where $y$ is an approximation to x, can be many orders of magnitude smaller than the unit roundoff. We analyze this phenomenon and show that in the $ infty $-norm it happens precisely when $x$ has components of widely varying magnitude and every component of $x$ of largest magnitude agrees with the corresponding component of $y$. Performance profiles are a popular way to compare competing algorithms according to particular measures of performance. We show that performance profiles based on normwise relative errors can give a misleading impression due to the influence of zero or tiny normwise relative errors. We propose a transformation that reduces the influence of these extreme errors in a controlled manner, while preserving the monotonicity of the underlying data and leaving the performance profile unchanged at its left end-point. Numerical examples with both artificial and genuine data illustrate the benefits of the transformation.

rawabstract:
It is a widespread but little-noticed phenomenon that the normwise relative error $ || x - y || / || x || $ of vectors $x$ and $y$ of floating point numbers of the same precision, where $y$ is an approximation to x, can be many orders of magnitude smaller than the unit roundoff. We analyze this phenomenon and show that in the $ \infty $-norm it happens precisely when $x$ has components of widely varying magnitude and every component of $x$ of largest magnitude agrees with the corresponding component of $y$. Performance profiles are a popular way to compare competing algorithms according to particular measures of performance. We show that performance profiles based on normwise relative errors can give a misleading impression due to the influence of zero or tiny normwise relative errors. We propose a transformation that reduces the influence of these extreme errors in a controlled manner, while preserving the monotonicity of the underlying data and leaving the performance profile unchanged at its left end-point. Numerical examples with both artificial and genuine data illustrate the benefits of the transformation.

entry:
@Article{Dingle:2013:RIT,
  author =       "Nicholas J. Dingle and Nicholas J. Higham",
  title =        "Reducing the influence of tiny normwise relative
                 errors on performance profiles",
  journal =      j-TOMS,
  volume =       "39",
  number =       "4",
  pages =        "24:1--24:11",
  month =        jul,
  year =         "2013",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/2491491.2491494",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Fri Jul 19 17:20:56 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toms/;
                 https://www.math.utah.edu/pub/bibnet/authors/h/higham-nicholas-john.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  abstract =     "It is a widespread but little-noticed phenomenon that
                 the normwise relative error $ || x - y || / || x || $
                 of vectors $x$ and $y$ of floating point numbers of the
                 same precision, where $y$ is an approximation to x, can
                 be many orders of magnitude smaller than the unit
                 roundoff. We analyze this phenomenon and show that in
                 the $ \infty $-norm it happens precisely when $x$ has
                 components of widely varying magnitude and every
                 component of $x$ of largest magnitude agrees with the
                 corresponding component of $y$. Performance profiles
                 are a popular way to compare competing algorithms
                 according to particular measures of performance. We
                 show that performance profiles based on normwise
                 relative errors can give a misleading impression due to
                 the influence of zero or tiny normwise relative errors.
                 We propose a transformation that reduces the influence
                 of these extreme errors in a controlled manner, while
                 preserving the monotonicity of the underlying data and
                 leaving the performance profile unchanged at its left
                 end-point. Numerical examples with both artificial and
                 genuine data illustrate the benefits of the
                 transformation.",
  acknowledgement = ack-nhfb,
  articleno =    "24",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: techreport
filename: fparith.bib
label: Doertel:2013:BKM
author: K. Doertel
title: Best Known Method: Avoid heterogeneous precision in control flow calculations
type: Report
institution: pub-INTEL
address: pub-INTEL:adr
year: 2013
bibdate: Sat Oct 31 07:00:07 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.10.31 07:00:07 ???
acknowledgement: ack-nhfb
rawauthor: K. Doertel
rawtitle: Best Known Method: Avoid heterogeneous precision in control flow calculations
entry:
@TechReport{Doertel:2013:BKM,
  author =       "K. Doertel",
  title =        "Best Known Method: Avoid heterogeneous precision in
                 control flow calculations",
  type =         "Report",
  institution =  pub-INTEL,
  address =      pub-INTEL:adr,
  pages =        "????",
  year =         "2013",
  bibdate =      "Sat Oct 31 07:00:07 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Edmunds:2013:AME
author: Michael G. Edmunds
title: Keynote II: The Antikythera Mechanism and the early history of mechanical computing
crossref: IEEE:2013:PIS
pages: 79--79
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.40
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
keywords: ARITH-21
acknowledgement: ack-nhfb
rawauthor: Michael G. Edmunds
rawtitle: Keynote {II}: The {Antikythera Mechanism} and the early history of mechanical computing
entry:
@InProceedings{Edmunds:2013:AME,
  author =       "Michael G. Edmunds",
  title =        "Keynote {II}: The {Antikythera Mechanism} and the
                 early history of mechanical computing",
  crossref =     "IEEE:2013:PIS",
  pages =        "79--79",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.40",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "ARITH-21",
}


bibtype: article
filename: fparith.bib
label: ElWazeer:2013:SVD
author: Khaled ElWazeer and Kapil Anand and Aparna Kotha and Matthew Smithson and Rajeev Barua
title: Scalable variable and data type detection in a binary rewriter
journal: j-SIGPLAN
volume: 48
number: 6
pages: 51--60
month: jun
monthnumber: 6
year: 2013
CODEN: SINODQ
DOI: https://doi.org/10.1145/2499370.2462165
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Mon Jul 1 17:15:38 MDT 2013
bibtimestamp: 2013.07.01 17:15:38 MDT
fjournal: ACM SIGPLAN Notices
remark: PLDI '13 conference proceedings.
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Khaled ElWazeer and Kapil Anand and Aparna Kotha and Matthew Smithson and Rajeev Barua
rawtitle: Scalable variable and data type detection in a binary rewriter
abstract:
We present scalable static analyses to recover variables, data types, and function prototypes from stripped x86 executables (without symbol or debug information) and obtain a functional intermediate representation (IR) for analysis and rewriting purposes. Our techniques on average run $ 352 times $ faster than current techniques and still have the same precision. This enables analyzing executables as large as millions of instructions in minutes which is not possible using existing techniques. Our techniques can recover variables allocated to the floating point stack, unlike current techniques. We have integrated our techniques to obtain a compiler level IR that works correctly if recompiled and produces the same output as the input executable. We demonstrate scalability, precision and correctness of our proposed techniques by evaluating them on the complete SPEC2006 benchmarks suite.

rawabstract:
We present scalable static analyses to recover variables, data types, and function prototypes from stripped x86 executables (without symbol or debug information) and obtain a functional intermediate representation (IR) for analysis and rewriting purposes. Our techniques on average run $ 352 \times $ faster than current techniques and still have the same precision. This enables analyzing executables as large as millions of instructions in minutes which is not possible using existing techniques. Our techniques can recover variables allocated to the floating point stack, unlike current techniques. We have integrated our techniques to obtain a compiler level IR that works correctly if recompiled and produces the same output as the input executable. We demonstrate scalability, precision and correctness of our proposed techniques by evaluating them on the complete SPEC2006 benchmarks suite.

entry:
@Article{ElWazeer:2013:SVD,
  author =       "Khaled ElWazeer and Kapil Anand and Aparna Kotha and
                 Matthew Smithson and Rajeev Barua",
  title =        "Scalable variable and data type detection in a binary
                 rewriter",
  journal =      j-SIGPLAN,
  volume =       "48",
  number =       "6",
  pages =        "51--60",
  month =        jun,
  year =         "2013",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/2499370.2462165",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Mon Jul 1 17:15:38 MDT 2013",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  abstract =     "We present scalable static analyses to recover
                 variables, data types, and function prototypes from
                 stripped x86 executables (without symbol or debug
                 information) and obtain a functional intermediate
                 representation (IR) for analysis and rewriting
                 purposes. Our techniques on average run $ 352 \times $
                 faster than current techniques and still have the same
                 precision. This enables analyzing executables as large
                 as millions of instructions in minutes which is not
                 possible using existing techniques. Our techniques can
                 recover variables allocated to the floating point
                 stack, unlike current techniques. We have integrated
                 our techniques to obtain a compiler level IR that works
                 correctly if recompiled and produces the same output as
                 the input executable. We demonstrate scalability,
                 precision and correctness of our proposed techniques by
                 evaluating them on the complete SPEC2006 benchmarks
                 suite.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  remark =       "PLDI '13 conference proceedings.",
}


bibtype: inproceedings
filename: fparith.bib
label: Engels:2013:NLL
author: Susanne Engels and Elif Bilge Kavun and Christof Paar and Tolga Yalcin and Hristina Mihajloska
title: A Non-Linear / Linear Instruction Set Extension for Lightweight Ciphers
crossref: IEEE:2013:PIS
pages: 67--75
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.36
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Susanne Engels and Elif Bilge Kavun and Christof Paar and Tolga Yalcin and Hristina Mihajloska
rawtitle: A Non-Linear\slash Linear Instruction Set Extension for Lightweight Ciphers
bibsource:
https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

keywords:
algebraic normal form; ANF; ARITH-21; binary matrix multiply-and-add form; bit permutation; Ciphers; cryptographic operation; cryptography; embedded CPU; embedded microcontroller; Hardware; instruction set extension; lightweight cipher; lightweight ciphers; lightweight cryptographic algorithm; linear instruction set extension; linear operation; matrix algebra; microcontrollers; modular architecture; nonlinear instruction set extension; nonlinear operation; Registers; s-box; Silicon; Software; Standards

entry:
@InProceedings{Engels:2013:NLL,
  author =       "Susanne Engels and Elif Bilge Kavun and Christof Paar
                 and Tolga Yalcin and Hristina Mihajloska",
  title =        "A Non-Linear\slash Linear Instruction Set Extension
                 for Lightweight Ciphers",
  crossref =     "IEEE:2013:PIS",
  pages =        "67--75",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.36",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/cryptography2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "algebraic normal form; ANF; ARITH-21; binary matrix
                 multiply-and-add form; bit permutation; Ciphers;
                 cryptographic operation; cryptography; embedded CPU;
                 embedded microcontroller; Hardware; instruction set
                 extension; lightweight cipher; lightweight ciphers;
                 lightweight cryptographic algorithm; linear instruction
                 set extension; linear operation; matrix algebra;
                 microcontrollers; modular architecture; nonlinear
                 instruction set extension; nonlinear operation;
                 Registers; s-box; Silicon; Software; Standards",
}


bibtype: inproceedings
filename: fparith.bib
label: Galal:2013:FGD
title: FPU Generator for Design Space Exploration
crossref: IEEE:2013:PIS
pages: 25--34
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.27
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawtitle: {FPU} Generator for Design Space Exploration
author:
Sameh Galal and Ofer Shacham and John S. Brunhaver and Jing Pu and Artem Vassiliev and Mark Horowitz

keywords:
adder; ARITH-21; Booth encoder; Booth-2 cascade multiply-add architecture; Booth-3 fused multiply-add architecture; Delays; design space exploration; Encoding; energy efficiency; fair apples-to-apples methodology; floating point; floating point arithmetic; floating point unit; FPU generator; Fused multiply add; Generators; latency-sensitive design; logic design; Logic gates; multipliers; optimisation; Optimization; optimization technique; power efficiency; Radiation detectors; summation tree; throughput-optimized design; Vegetation; Wallace combining tree

rawauthor:
Sameh Galal and Ofer Shacham and John S. Brunhaver and Jing Pu and Artem Vassiliev and Mark Horowitz

entry:
@InProceedings{Galal:2013:FGD,
  author =       "Sameh Galal and Ofer Shacham and John S. Brunhaver and
                 Jing Pu and Artem Vassiliev and Mark Horowitz",
  title =        "{FPU} Generator for Design Space Exploration",
  crossref =     "IEEE:2013:PIS",
  pages =        "25--34",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.27",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "adder; ARITH-21; Booth encoder; Booth-2 cascade
                 multiply-add architecture; Booth-3 fused multiply-add
                 architecture; Delays; design space exploration;
                 Encoding; energy efficiency; fair apples-to-apples
                 methodology; floating point; floating point arithmetic;
                 floating point unit; FPU generator; Fused multiply add;
                 Generators; latency-sensitive design; logic design;
                 Logic gates; multipliers; optimisation; Optimization;
                 optimization technique; power efficiency; Radiation
                 detectors; summation tree; throughput-optimized design;
                 Vegetation; Wallace combining tree",
}


bibtype: inproceedings
filename: fparith.bib
label: Giorgi:2013:PMM
author: Pascal Giorgi and Laurent Imbert and Thomas Izard
title: Parallel Modular Multiplication on Multi-core Processors
crossref: IEEE:2013:PIS
pages: 135--142
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.20
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Pascal Giorgi and Laurent Imbert and Thomas Izard
rawtitle: Parallel Modular Multiplication on Multi-core Processors
keywords:
Algorithm design and analysis; ARITH-21; Barrett; bipartite; Complexity theory; digital arithmetic; k-ary multipartite algorithms; k-ary multipartite multiplication; low level arithmetic operations; microprocessor chips; Modular multiplication; Montgomery; multi-core; multicore processors; multiprocessing systems; parallel arithmetic; parallel modular multiplications; Parallel processing; parallel processing; Program processors; Software algorithms; software parallelism; Synchronization; tripartite

entry:
@InProceedings{Giorgi:2013:PMM,
  author =       "Pascal Giorgi and Laurent Imbert and Thomas Izard",
  title =        "Parallel Modular Multiplication on Multi-core
                 Processors",
  crossref =     "IEEE:2013:PIS",
  pages =        "135--142",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.20",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithm design and analysis; ARITH-21; Barrett;
                 bipartite; Complexity theory; digital arithmetic; k-ary
                 multipartite algorithms; k-ary multipartite
                 multiplication; low level arithmetic operations;
                 microprocessor chips; Modular multiplication;
                 Montgomery; multi-core; multicore processors;
                 multiprocessing systems; parallel arithmetic; parallel
                 modular multiplications; Parallel processing; parallel
                 processing; Program processors; Software algorithms;
                 software parallelism; Synchronization; tripartite",
}


bibtype: article
filename: fparith.bib
label: Gonzalez-Navarro:2013:BID
author: Sonia Gonzalez-Navarro and Charles Tsen and Michael J. Schulte
title: Binary Integer Decimal-Based Floating-Point Multiplication
journal: j-IEEE-TRANS-COMPUT
volume: 62
number: 7
pages: 1460--1466
month: jul
monthnumber: 7
year: 2013
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2012.79
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jun 17 15:07:53 2013
bibtimestamp: 2013.06.17 15:07:53 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Sonia Gonzalez-Navarro and Charles Tsen and Michael J. Schulte
rawtitle: Binary Integer Decimal-Based Floating-Point Multiplication
entry:
@Article{Gonzalez-Navarro:2013:BID,
  author =       "Sonia Gonzalez-Navarro and Charles Tsen and Michael J.
                 Schulte",
  title =        "Binary Integer Decimal-Based Floating-Point
                 Multiplication",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "62",
  number =       "7",
  pages =        "1460--1466",
  month =        jul,
  year =         "2013",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2012.79",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jun 17 15:07:53 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: misc
filename: fparith.bib
label: Gustafson:2013:UCN
author: John Gustafson
pages: 1460--1466
day: 19
month: mar
monthnumber: 3
year: 2013
bibdate: Sat Apr 02 16:24:25 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.04.02 16:24:25 ???
URL: http://sites.ieee.org/scv-cs/files/2013/03/Right-SizingPrecision1.pdf
acknowledgement: ack-nhfb
howpublished: Web slides (64).
rawauthor: John Gustafson
title:
Unleashed Computing: The need to right-size precision to save energy, bandwidth, storage, and electrical power

rawtitle:
Unleashed Computing: The need to right-size precision to save energy, bandwidth, storage, and electrical power

entry:
@Misc{Gustafson:2013:UCN,
  author =       "John Gustafson",
  title =        "Unleashed Computing: The need to right-size precision
                 to save energy, bandwidth, storage, and electrical
                 power",
  howpublished = "Web slides (64).",
  day =          "19",
  month =        mar,
  year =         "2013",
  bibdate =      "Sat Apr 02 16:24:25 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://sites.ieee.org/scv-cs/files/2013/03/Right-SizingPrecision1.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Han:2013:HSP
author: Liu Han and Seok-Bum Ko
title: High-Speed Parallel Decimal Multiplication with Redundant Internal Encodings
journal: j-IEEE-TRANS-COMPUT
volume: 62
number: 5
pages: 956--968
month: may
monthnumber: 5
year: 2013
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2012.35
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Wed Jan 21 09:06:31 2015
bibtimestamp: 2015.01.21 09:06:31 ???
note: See comment cite Gorgin:2015:CXH.
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Liu Han and Seok-Bum Ko
rawnote: See comment \cite{Gorgin:2015:CXH}.
rawtitle: High-Speed Parallel Decimal Multiplication with Redundant Internal Encodings
abstract:
The decimal multiplication is one of the most important decimal arithmetic operations which have a growing demand in the area of commercial, financial, and scientific computing. In this paper, we propose a parallel decimal multiplication algorithm with three components, which are a partial product generation, a partial product reduction, and a final digit-set conversion. First, a redundant number system is applied to recode not only the multiplier, but also multiples of the multiplicand in signed-digit (SD) numbers. Furthermore, we present a multioperand SD addition algorithm to reduce the partial product array. Finally, a digit-set conversion algorithm with a hybrid prefix network to decrease the number of the logic gates on the critical path is discussed. An analysis of the timing delay and an HDL model synthesized under 90 nm technology show that by considering the tradeoff of designs among three components, the overall delay of the proposed $ 16 times 16$-digit multiplier takes about 11 percent less timing delay with 2 percent less area compared to the current fastest design.

keywords:
Adders; Algorithm design and analysis; Arrays; critical path; Decimal arithmetic; decimal arithmetic operations; Delay; digit-set conversion algorithm; Encoding; HDL model synthesis; high-speed parallel decimal multiplication algorithm; hybrid prefix network; logic design; logic gate number reduction; logic gates; Logic gates; multioperand SD adder; multioperand SD addition algorithm; multiplier recoding; multiplying circuits; parallel multiplication; partial-product array reduction; partial-product generation; partial-product reduction; redundant internal encodings; redundant number system; redundant number systems; SD numbers; signed-digit numbers; timing delay analysis

rawabstract:
The decimal multiplication is one of the most important decimal arithmetic operations which have a growing demand in the area of commercial, financial, and scientific computing. In this paper, we propose a parallel decimal multiplication algorithm with three components, which are a partial product generation, a partial product reduction, and a final digit-set conversion. First, a redundant number system is applied to recode not only the multiplier, but also multiples of the multiplicand in signed-digit (SD) numbers. Furthermore, we present a multioperand SD addition algorithm to reduce the partial product array. Finally, a digit-set conversion algorithm with a hybrid prefix network to decrease the number of the logic gates on the critical path is discussed. An analysis of the timing delay and an HDL model synthesized under 90 nm technology show that by considering the tradeoff of designs among three components, the overall delay of the proposed $ 16 \times 16$-digit multiplier takes about 11 percent less timing delay with 2 percent less area compared to the current fastest design.

entry:
@Article{Han:2013:HSP,
  author =       "Liu Han and Seok-Bum Ko",
  title =        "High-Speed Parallel Decimal Multiplication with
                 Redundant Internal Encodings",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "62",
  number =       "5",
  pages =        "956--968",
  month =        may,
  year =         "2013",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2012.35",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Wed Jan 21 09:06:31 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  note =         "See comment \cite{Gorgin:2015:CXH}.",
  abstract =     "The decimal multiplication is one of the most
                 important decimal arithmetic operations which have a
                 growing demand in the area of commercial, financial,
                 and scientific computing. In this paper, we propose a
                 parallel decimal multiplication algorithm with three
                 components, which are a partial product generation, a
                 partial product reduction, and a final digit-set
                 conversion. First, a redundant number system is applied
                 to recode not only the multiplier, but also multiples
                 of the multiplicand in signed-digit (SD) numbers.
                 Furthermore, we present a multioperand SD addition
                 algorithm to reduce the partial product array. Finally,
                 a digit-set conversion algorithm with a hybrid prefix
                 network to decrease the number of the logic gates on
                 the critical path is discussed. An analysis of the
                 timing delay and an HDL model synthesized under 90 nm
                 technology show that by considering the tradeoff of
                 designs among three components, the overall delay of
                 the proposed $ 16 \times 16$-digit multiplier takes
                 about 11 percent less timing delay with 2 percent less
                 area compared to the current fastest design.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "Adders; Algorithm design and analysis; Arrays;
                 critical path; Decimal arithmetic; decimal arithmetic
                 operations; Delay; digit-set conversion algorithm;
                 Encoding; HDL model synthesis; high-speed parallel
                 decimal multiplication algorithm; hybrid prefix
                 network; logic design; logic gate number reduction;
                 logic gates; Logic gates; multioperand SD adder;
                 multioperand SD addition algorithm; multiplier
                 recoding; multiplying circuits; parallel
                 multiplication; partial-product array reduction;
                 partial-product generation; partial-product reduction;
                 redundant internal encodings; redundant number system;
                 redundant number systems; SD numbers; signed-digit
                 numbers; timing delay analysis",
}


bibtype: inproceedings
filename: fparith.bib
label: Ioualalen:2013:SAF
author: Arnault Ioualalen and Matthieu Martel
title: Synthesizing accurate floating-point formulas
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 113--116
year: 2013
DOI: https://doi.org/10.1109/ASAP.2013.6567563
bibdate: Sat Apr 01 08:00:40 2017
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2017.04.01 08:00:40 ???
URL: https://hal.archives-ouvertes.fr/hal-00835736
acknowledgement: ack-nhfb
rawauthor: Arnault Ioualalen and Matthieu Martel
rawtitle: Synthesizing accurate floating-point formulas
booktitle:
Proceedings of the 24th IEEE International Conference on Application-Specific Systems, Architectures and Processors, June, 2013

rawbooktitle:
{Proceedings of the 24th IEEE International Conference on Application-Specific Systems, Architectures and Processors, June, 2013}

entry:
@InProceedings{Ioualalen:2013:SAF,
  author =       "Arnault Ioualalen and Matthieu Martel",
  editor =       "????",
  booktitle =    "{Proceedings of the 24th IEEE International Conference
                 on Application-Specific Systems, Architectures and
                 Processors, June, 2013}",
  title =        "Synthesizing accurate floating-point formulas",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "113--116",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ASAP.2013.6567563",
  bibdate =      "Sat Apr 01 08:00:40 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://hal.archives-ouvertes.fr/hal-00835736",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Jaffer:2013:EAR
author: Aubrey Jaffer
title: Easy Accurate Reading and Writing of Floating-Point Numbers
journal: arXiv.org
pages: 1--7
day: 28
month: oct
monthnumber: 10
year: 2013
MRclass: 65G04
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1310.8121
keywords: base conversion; input-output conversion; radix conversion; round-trip base conversion
subject: Numerical Analysis (cs.NA)
acknowledgement: ack-nhfb
rawauthor: Aubrey Jaffer
rawtitle: Easy Accurate Reading and Writing of Floating-Point Numbers
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/java2010.bib

abstract:
Presented here are algorithms for converting between (decimal) scientific-notation and (binary) IEEE-754 double-precision floating-point numbers. By employing a rounding integer quotient operation these algorithms are much simpler than those previously published. The values are stable under repeated conversions between the formats. Unlike Java-1.6, the scientific representations generated use only the minimum number of mantissa digits needed to convert back to the original binary values. Implemented in Java these algorithms execute as fast or faster than Java's native conversions over nearly all of the IEEE-754 double-precision range.

rawabstract:
Presented here are algorithms for converting between (decimal) scientific-notation and (binary) IEEE-754 double-precision floating-point numbers. By employing a rounding integer quotient operation these algorithms are much simpler than those previously published. The values are stable under repeated conversions between the formats. Unlike Java-1.6, the scientific representations generated use only the minimum number of mantissa digits needed to convert back to the original binary values. Implemented in Java these algorithms execute as fast or faster than Java's native conversions over nearly all of the IEEE-754 double-precision range.

entry:
@Article{Jaffer:2013:EAR,
  author =       "Aubrey Jaffer",
  title =        "Easy Accurate Reading and Writing of Floating-Point
                 Numbers",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--7",
  day =          "28",
  month =        oct,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  MRclass =      "65G04",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/java2010.bib",
  URL =          "http://arxiv.org/abs/1310.8121",
  abstract =     "Presented here are algorithms for converting between
                 (decimal) scientific-notation and (binary) IEEE-754
                 double-precision floating-point numbers. By employing a
                 rounding integer quotient operation these algorithms
                 are much simpler than those previously published. The
                 values are stable under repeated conversions between
                 the formats. Unlike Java-1.6, the scientific
                 representations generated use only the minimum number
                 of mantissa digits needed to convert back to the
                 original binary values. Implemented in Java these
                 algorithms execute as fast or faster than Java's native
                 conversions over nearly all of the IEEE-754
                 double-precision range.",
  acknowledgement = ack-nhfb,
  keywords =     "base conversion; input-output conversion; radix
                 conversion; round-trip base conversion",
  subject =      "Numerical Analysis (cs.NA)",
}


bibtype: inproceedings
filename: fparith.bib
label: Jeannerod:2013:CAC
author: Claude-Pierre Jeannerod and Nicolas Louvet and Jean-Michel Muller
title: On the Componentwise Accuracy of Complex Floating-Point Division with an FMA
crossref: IEEE:2013:PIS
pages: 83--90
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.8
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcw.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Claude-Pierre Jeannerod and Nicolas Louvet and Jean-Michel Muller
rawtitle: On the Componentwise Accuracy of Complex Floating-Point Division with an {FMA}
keywords:
2 determinants; absolute errors; Accuracy; Algorithm design and analysis; Approximation algorithms; Approximation methods; ARITH-21; compensation; complex division; complex floating-point division; componentwise accuracy; componentwise relative error; Digital arithmetic; division algorithms; Error analysis; error analysis; floating point arithmetic; floating-point arithmetic; FMA instruction; fused multiply-add (FMA); fused multiply-add instruction; Kahan compensated algorithm; nonnegative products; radix-two floating-point arithmetic; relative errors; rounding error analysis; Standards; straight-line program; unit roundoff

entry:
@InProceedings{Jeannerod:2013:CAC,
  author =       "Claude-Pierre Jeannerod and Nicolas Louvet and
                 Jean-Michel Muller",
  title =        "On the Componentwise Accuracy of Complex
                 Floating-Point Division with an {FMA}",
  crossref =     "IEEE:2013:PIS",
  pages =        "83--90",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.8",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcw.bib",
  acknowledgement = ack-nhfb,
  keywords =     "2 determinants; absolute errors; Accuracy; Algorithm
                 design and analysis; Approximation algorithms;
                 Approximation methods; ARITH-21; compensation; complex
                 division; complex floating-point division;
                 componentwise accuracy; componentwise relative error;
                 Digital arithmetic; division algorithms; Error
                 analysis; error analysis; floating point arithmetic;
                 floating-point arithmetic; FMA instruction; fused
                 multiply-add (FMA); fused multiply-add instruction;
                 Kahan compensated algorithm; nonnegative products;
                 radix-two floating-point arithmetic; relative errors;
                 rounding error analysis; Standards; straight-line
                 program; unit roundoff",
}


bibtype: article
filename: fparith.bib
label: Jeannerod:2013:FAK
author: Claude-Pierre Jeannerod and Nicolas Louvet and Jean-Michel Muller
title: Further analysis of Kahan's algorithm for the accurate computation of $ 2 times 2 $ determinants
journal: j-MATH-COMPUT
volume: 82
number: 284
pages: 2245--2264
year: 2013
CODEN: MCMPAF
DOI: https://doi.org/10.1090/S0025-5718-2013-02679-8
ISSN: 0025-5718 (print), 1088-6842 (electronic) OR 00255718 (print), 10886842 (electronic)
ISSNL: 0025-5718 OR 00255718
MRnumber: MR3073198
bibdate: Mon Jul 15 12:07:58 MDT 2013
bibtimestamp: 2013.07.15 12:07:58 MDT
fjournal: Mathematics of Computation
acknowledgement: ack-nhfb
ajournal: Math. Comput.
journalURL: http://www.ams.org/mcom/
rawauthor: Claude-Pierre Jeannerod and Nicolas Louvet and Jean-Michel Muller
rawtitle: Further analysis of {Kahan}'s algorithm for the accurate computation of $ 2 \times 2 $ determinants
bibsource:
http://www.ams.org/mcom/2013-82-284; https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib

URL:
http://www.ams.org/journals/mcom/2013-82-284/S0025-5718-2013-02679-8; http://www.ams.org/journals/mcom/2013-82-284/S0025-5718-2013-02679-8/S0025-5718-2013-02679-8.pdf

entry:
@Article{Jeannerod:2013:FAK,
  author =       "Claude-Pierre Jeannerod and Nicolas Louvet and
                 Jean-Michel Muller",
  title =        "Further analysis of {Kahan}'s algorithm for the
                 accurate computation of $ 2 \times 2 $ determinants",
  journal =      j-MATH-COMPUT,
  volume =       "82",
  number =       "284",
  pages =        "2245--2264",
  month =        "",
  year =         "2013",
  CODEN =        "MCMPAF",
  DOI =          "https://doi.org/10.1090/S0025-5718-2013-02679-8",
  ISSN =         "0025-5718 (print), 1088-6842 (electronic)",
  ISSN-L =       "0025-5718",
  MRnumber =     "MR3073198",
  bibdate =      "Mon Jul 15 12:07:58 MDT 2013",
  bibsource =    "http://www.ams.org/mcom/2013-82-284;
                 https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcomp2010.bib",
  URL =          "http://www.ams.org/journals/mcom/2013-82-284/S0025-5718-2013-02679-8;
                 http://www.ams.org/journals/mcom/2013-82-284/S0025-5718-2013-02679-8/S0025-5718-2013-02679-8.pdf",
  acknowledgement = ack-nhfb,
  ajournal =     "Math. Comput.",
  fjournal =     "Mathematics of Computation",
  journal-URL =  "http://www.ams.org/mcom/",
}


bibtype: article
filename: fparith.bib
label: Jeannerod:2013:IEB
author: Claude-Pierre Jeannerod and Siegfried M. Rump
title: Improved Error Bounds for Inner Products in Floating-Point Arithmetic
journal: j-SIAM-J-MAT-ANA-APPL
volume: 34
number: 2
pages: 338--344
year: 2013
CODEN: SJMAEL
DOI: https://doi.org/10.1137/120894488
ISSN: 0895-4798 (print), 1095-7162 (electronic) OR 08954798 (print), 10957162 (electronic)
ISSNL: 0895-4798 OR 08954798
bibdate: Fri Apr 5 06:24:05 MDT 2013
bibtimestamp: 2013.04.05 06:24:05 MDT
fjournal: SIAM Journal on Matrix Analysis and Applications
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/simax
onlinedate: January 2013
rawauthor: Claude-Pierre Jeannerod and Siegfried M. Rump
rawtitle: Improved Error Bounds for Inner Products in Floating-Point Arithmetic
bibsource:
http://epubs.siam.org/sam-bin/dbq/toc/SIMAX/34/2; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjmatanaappl.bib

entry:
@Article{Jeannerod:2013:IEB,
  author =       "Claude-Pierre Jeannerod and Siegfried M. Rump",
  title =        "Improved Error Bounds for Inner Products in
                 Floating-Point Arithmetic",
  journal =      j-SIAM-J-MAT-ANA-APPL,
  volume =       "34",
  number =       "2",
  pages =        "338--344",
  month =        "????",
  year =         "2013",
  CODEN =        "SJMAEL",
  DOI =          "https://doi.org/10.1137/120894488",
  ISSN =         "0895-4798 (print), 1095-7162 (electronic)",
  ISSN-L =       "0895-4798",
  bibdate =      "Fri Apr 5 06:24:05 MDT 2013",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SIMAX/34/2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjmatanaappl.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Matrix Analysis and Applications",
  journal-URL =  "http://epubs.siam.org/simax",
  onlinedate =   "January 2013",
}


bibtype: article
filename: fparith.bib
label: Jiang:2013:AED
title: Accurate evaluation of the $k$-th derivative of a polynomial and its application
journal: j-J-COMPUT-APPL-MATH
volume: 243
pages: 28--47
day: 1
month: may
monthnumber: 5
year: 2013
CODEN: JCAMDI
DOI: https://doi.org/10.1016/j.cam.2012.11.008
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
MRclass: 65D25
MRnumber: 3003371
MRreviewer: Ana Maria Acu
bibdate: Sat Feb 25 13:26:16 MST 2017
bibtimestamp: 2017.02.25 13:26:16 MST
URL: http://www.sciencedirect.com/science/article/pii/S0377042712005018
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawtitle: Accurate evaluation of the $k$-th derivative of a polynomial and its application
author:
Hao Jiang and Stef Graillat and Canbin Hu and Shengguo Li and Xiangke Liao and Lizhi Cheng and Fang Su

keywords:
compensated algorithm; derivative evaluation; error-free transformation; floating-point arithmetic; rounding error

rawauthor:
Hao Jiang and Stef Graillat and Canbin Hu and Shengguo Li and Xiangke Liao and Lizhi Cheng and Fang Su

entry:
@Article{Jiang:2013:AED,
  author =       "Hao Jiang and Stef Graillat and Canbin Hu and Shengguo
                 Li and Xiangke Liao and Lizhi Cheng and Fang Su",
  title =        "Accurate evaluation of the $k$-th derivative of a
                 polynomial and its application",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "243",
  number =       "??",
  pages =        "28--47",
  day =          "1",
  month =        may,
  year =         "2013",
  CODEN =        "JCAMDI",
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  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  MRclass =      "65D25",
  MRnumber =     "3003371",
  MRreviewer =   "Ana Maria Acu",
  bibdate =      "Sat Feb 25 13:26:16 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2010.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042712005018",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
  keywords =     "compensated algorithm; derivative evaluation;
                 error-free transformation; floating-point arithmetic;
                 rounding error",
}


bibtype: inproceedings
filename: fparith.bib
label: Jiang:2013:AFE
author: Hao Jiang and Stef Graillat and Roberto Barrio
title: Accurate and Fast Evaluation of Elementary Symmetric Functions
crossref: IEEE:2013:PIS
pages: 183--190
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.18
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Hao Jiang and Stef Graillat and Roberto Barrio
rawtitle: Accurate and Fast Evaluation of Elementary Symmetric Functions
keywords:
Accuracy; accurate algorithm; Algorithm design and analysis; ARITH-21; compensated algorithm; double-double library; elementary symmetric functions; error-free transformation; error-free transformations; floating point arithmetic; floating-point arithmetic; forward roundoff error bound; Libraries; mathematics computing; MATLAB poly function; Polynomials; psychological measurement; Rasch model; roundoff error; Roundoff errors; running error bound; shaper bound; summation algorithm; Vectors

entry:
@InProceedings{Jiang:2013:AFE,
  author =       "Hao Jiang and Stef Graillat and Roberto Barrio",
  title =        "Accurate and Fast Evaluation of Elementary Symmetric
                 Functions",
  crossref =     "IEEE:2013:PIS",
  pages =        "183--190",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.18",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Accuracy; accurate algorithm; Algorithm design and
                 analysis; ARITH-21; compensated algorithm;
                 double-double library; elementary symmetric functions;
                 error-free transformation; error-free transformations;
                 floating point arithmetic; floating-point arithmetic;
                 forward roundoff error bound; Libraries; mathematics
                 computing; MATLAB poly function; Polynomials;
                 psychological measurement; Rasch model; roundoff error;
                 Roundoff errors; running error bound; shaper bound;
                 summation algorithm; Vectors",
}


bibtype: inproceedings
filename: fparith.bib
label: Kadric:2013:APF
author: Edin Kadric and Paul Gurniak and Andre DeHon
title: Accurate Parallel Floating-Point Accumulation
crossref: IEEE:2013:PIS
pages: 153--162
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.19
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Edin Kadric and Paul Gurniak and Andr{\'e} DeHon
rawtitle: Accurate Parallel Floating-Point Accumulation
keywords:
$O(log N)$ depth; Accumulation; Accurate; accurate parallel floating-point accumulation; accurate summation; Adders; arbitrary throughput; ARITH-21; Clocks; conservative termination detection; Convergence; field programmable gate arrays; floating point arithmetic; Floating-Point Arithmetic; floating-point sums; FPGA; Hardware; IEEE standards; IEEE-754; Indexes; iterative algorithm; iterative methods; iterative refinement; Moore law scaling; Parallel; parallel associative reduction; Parallel processing; residue-preserving IEEE-754 double-precision floating-point adder; Rounding; standard adder; streaming accurate floating-point accumulation unit; tree reduce parallelism; Upper bound; Virtex 6 FPGA

entry:
@InProceedings{Kadric:2013:APF,
  author =       "Edin Kadric and Paul Gurniak and Andr{\'e} DeHon",
  title =        "Accurate Parallel Floating-Point Accumulation",
  crossref =     "IEEE:2013:PIS",
  pages =        "153--162",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.19",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "$O(\log N)$ depth; Accumulation; Accurate; accurate
                 parallel floating-point accumulation; accurate
                 summation; Adders; arbitrary throughput; ARITH-21;
                 Clocks; conservative termination detection;
                 Convergence; field programmable gate arrays; floating
                 point arithmetic; Floating-Point Arithmetic;
                 floating-point sums; FPGA; Hardware; IEEE standards;
                 IEEE-754; Indexes; iterative algorithm; iterative
                 methods; iterative refinement; Moore law scaling;
                 Parallel; parallel associative reduction; Parallel
                 processing; residue-preserving IEEE-754
                 double-precision floating-point adder; Rounding;
                 standard adder; streaming accurate floating-point
                 accumulation unit; tree reduce parallelism; Upper
                 bound; Virtex 6 FPGA",
}


bibtype: article
filename: fparith.bib
label: Kouretas:2013:LPL
author: Ioannis Kouretas and Charalambos Basetas and Vassilis Paliouras
title: Low-Power Logarithmic Number System Addition / Subtraction and Their Impact on Digital Filters
journal: j-IEEE-TRANS-COMPUT
volume: 62
number: 11
pages: 2196--2209
month: nov
monthnumber: 11
year: 2013
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2012.111
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Nov 15 08:54:34 2013
bibtimestamp: 2013.11.15 08:54:34 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Ioannis Kouretas and Charalambos Basetas and Vassilis Paliouras
rawtitle: Low-Power Logarithmic Number System Addition\slash Subtraction and Their Impact on Digital Filters
entry:
@Article{Kouretas:2013:LPL,
  author =       "Ioannis Kouretas and Charalambos Basetas and Vassilis
                 Paliouras",
  title =        "Low-Power Logarithmic Number System Addition\slash
                 Subtraction and Their Impact on Digital Filters",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "62",
  number =       "11",
  pages =        "2196--2209",
  month =        nov,
  year =         "2013",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2012.111",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Nov 15 08:54:34 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: book
filename: fparith.bib
label: Kulisch:2013:CAV
author: Ulrich Kulisch
title: Computer Arithmetic and Validity
volume: 33
publisher: pub-GRUYTER
address: pub-GRUYTER:adr
edition: Second
pages: xxii + 434
year: 2013
DOI: https://doi.org/10.1515/9783110301793
ISSN: 0179-0986 OR 01790986
ISSNL: 0179-0986 OR 01790986
LCCN: QA76.9.C62 K853 2013
bibdate: Sat May 18 08:56:52 MDT 2013
bibtimestamp: 2013.05.18 08:56:52 MDT
series: De Gruyter studies in mathematics
subject: computer arithmetic; computer arithmetic and logic units; floating-point arithmetic
acknowledgement: ack-nhfb
rawauthor: Ulrich Kulisch
rawtitle: Computer Arithmetic and Validity
ISBN:
3-11-030173-3, 3-11-030179-2 (e-book), 3-11-030180-6 (set) OR 3110301733, 3110301792 (ebook), 3110301806 (set)

ISBN13:
978-3-11-030173-1, 978-3-11-030179-3 (e-book), 978-3-11-030180-9 (set) OR 9783110301731, 9783110301793 (ebook), 9783110301809 (set)

bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/mathcw.bib; z3950.loc.gov:7090/Voyager

abstract:
This is the revised and extended second edition of the successful basic book on computer arithmetic. It is consistent with the newest recent standard developments in the field. The book shows how the arithmetic capability of the computer can be enhanced. The work is motivated by the desire and the need to improve the accuracy of numerical computing and to control the quality of the computed results (validity). The accuracy requirements for the elementary floating-point operations are extended to the customary product spaces of computations including interval spaces. The mathematical properties of these models are extracted and lead to a general theory of computer arithmetic. Detailed methods and circuits for the implementation of this advanced computer arithmetic are developed in the book. It illustrates how the extended arithmetic can be used to compute highly accurate and mathematically verified results. The book can be used as a high-level undergraduate textbook but also as reference work for research in computer arithmetic and applied mathematics.

TOC:
Foreword to the second edition vii Preface / ix Introduction / 1 I Theory of computer arithmetic 1 First concepts 13 1.1 Ordered sets / 13 1.2 Complete lattices and complete subnets / 18 1.3 Screens and roundings / 24 1.4 Arithmetic operations and roundings / 35 2 Ringoids and vectoids 43 2.1 Ringoids / 43 2.2 Vectoids / 54 3 Definition of computer arithmetic 62 3.1 Introduction / 62 3.2 Preliminaries / 65 3.3 The traditional definition of computer arithmetic / 69 3.4 Definition of computer arithmetic by semimorphisms / 70 3.5 A remark about roundings / 78 3.6 Uniqueness of the minus operator / 79 3.7 Rounding near zero / 81 4 Interval arithmetic 87 4.1 Interval sets and arithmetic / 88 4.2 Interval arithmetic over a linearly ordered set / 97 4.3 Interval matrices / 101 4.4 Interval vectors / 107 4.5 Interval arithmetic on a screen / 110 7.2 Arithmetic interval operations / 237 7.2.1 Algebraic operations / 238 7.2.2 Comments on the algebraic operations / 240 7.3 Circuitry for the arithmetic interval operations / 241 7.4 Comparisons and lattice operations / 242 7.4.1 Comments on comparisons and lattice operations / 243 7.4.2 Hardware support for comparisons and lattice operations / 243 7.5 Alternative circuitry for interval operations and comparisons / 244 7.5.1 Hardware support for interval arithmetic on x86-processors 245 7.5.2 Accurate evaluation of interval scalar products / 247 8 Scalar products and complete arithmetic 249 8.1 Introduction and motivation / 250 8.2 Historical remarks / 252 8.3 The ubiquity of the scalar product in numerical analysis / 257 8.4 Implementation principles / 260 8.4.1 Long adder and long shift / 262 8.4.2 Short adder with local memory on the arithmetic unit / 262 8.4.3 Remarks / 263 8.4.4 Fast carry resolution / 265 8.5 Informal sketch for computing an exact dot product / 267 8.6 Scalar product computation units (SPUs) / 267 8.6.1 SPU for computers with a 32 bit data bus / 269 8.6.2 A coprocessor chip for the exact scalar product / 272 8.6.3 SPU for computers with a 64 bit data bus / 275 8.7 Comments / 278 8.7.1 Rounding / 278 8.7.2 How much local memory should be provided on an SPU? / 279 8.8 The data format complete and complete arithmetic / 281 8.8.1 Low level instructions for complete arithmetic / 282 8.8.2 Complete arithmetic in high level programming languages / 283 8.9 Top speed scalar product units / 287 8.9.1 SPU with long adder for 64 bit data word / 287 8.9.2 SPU with long adder for 32 bit data word / 292 8.9.3 An FPGA coprocessor for the exact scalar product / 295 8.9.4 SPU with short adder and complete register / 295 8.9.5 Carry-free accumulation of products in redundant arithmetic 301 8.10 Hardware complete register window / 302 III Principles of verified computing 9 Sample applications 307 9.1 Basic properties of interval mathematics / 309 9.1.1 Interval arithmetic, a powerful calculus to deal with inequalities / 309 9.1.2 Interval arithmetic as executable set operations / 310 9.1.3 Enclosing the range of function values / 316 9.1.4 Nonzero property of a function, global optimization / 319 9.2 Differentiation arithmetic, enclosures of derivatives / 321 9.3 The interval Newton method / 329 9.4 The extended interval Newton method / 332 9.5 Verified solution of systems of linear equations / 333 9.6 Accurate evaluation of arithmetic expressions / 340 9.6.1 Complete expressions / 341 9.6.2 Accurate evaluation of polynomials / 342 9.6.3 Arithmetic expressions / 346 9.7 Multiple precision arithmetics / 347 9.7.1 Multiple precision floating-point arithmetic / 348 9.7.2 Multiple precision interval arithmetic / 351 9.7.3 Applications / 356 9.7.4 Adding an exponent part as a scaling factor to complete arithmetic / 358 9.8 Remarks on Kaucher arithmetic / 360 9.8.1 The basic operations of Kaucher arithmetic / 364 A Frequently used symbols 367 B On homomorphism 369 Bibliography 371 List of figures 421 List of tables 425 Index 427

rawabstract:
This is the revised and extended second edition of the successful basic book on computer arithmetic. It is consistent with the newest recent standard developments in the field. The book shows how the arithmetic capability of the computer can be enhanced. The work is motivated by the desire and the need to improve the accuracy of numerical computing and to control the quality of the computed results (validity). The accuracy requirements for the elementary floating-point operations are extended to the customary product spaces of computations including interval spaces. The mathematical properties of these models are extracted and lead to a general theory of computer arithmetic. Detailed methods and circuits for the implementation of this advanced computer arithmetic are developed in the book. It illustrates how the extended arithmetic can be used to compute highly accurate and mathematically verified results. The book can be used as a high-level undergraduate textbook but also as reference work for research in computer arithmetic and applied mathematics.

rawTOC:
Foreword to the second edition vii \\ Preface / ix \\ Introduction / 1 \\ I Theory of computer arithmetic \\ 1 First concepts 13 \\ 1.1 Ordered sets / 13 \\ 1.2 Complete lattices and complete subnets / 18 \\ 1.3 Screens and roundings / 24 \\ 1.4 Arithmetic operations and roundings / 35 \\ 2 Ringoids and vectoids 43 \\ 2.1 Ringoids / 43 \\ 2.2 Vectoids / 54 \\ 3 Definition of computer arithmetic 62 \\ 3.1 Introduction / 62 \\ 3.2 Preliminaries / 65 \\ 3.3 The traditional definition of computer arithmetic / 69 \\ 3.4 Definition of computer arithmetic by semimorphisms / 70 \\ 3.5 A remark about roundings / 78 \\ 3.6 Uniqueness of the minus operator / 79 \\ 3.7 Rounding near zero / 81 \\ 4 Interval arithmetic 87 \\ 4.1 Interval sets and arithmetic / 88 \\ 4.2 Interval arithmetic over a linearly ordered set / 97 \\ 4.3 Interval matrices / 101 \\ 4.4 Interval vectors / 107 \\ 4.5 Interval arithmetic on a screen / 110 \\ 7.2 Arithmetic interval operations / 237 \\ 7.2.1 Algebraic operations / 238 \\ 7.2.2 Comments on the algebraic operations / 240 \\ 7.3 Circuitry for the arithmetic interval operations / 241 \\ 7.4 Comparisons and lattice operations / 242 \\ 7.4.1 Comments on comparisons and lattice operations / 243 \\ 7.4.2 Hardware support for comparisons and lattice operations / 243 \\ 7.5 Alternative circuitry for interval operations and comparisons / 244 \\ 7.5.1 Hardware support for interval arithmetic on x86-processors 245 \\ 7.5.2 Accurate evaluation of interval scalar products / 247 \\ 8 Scalar products and complete arithmetic 249 \\ 8.1 Introduction and motivation / 250 \\ 8.2 Historical remarks / 252 \\ 8.3 The ubiquity of the scalar product in numerical analysis / 257 \\ 8.4 Implementation principles / 260 \\ 8.4.1 Long adder and long shift / 262 \\ 8.4.2 Short adder with local memory on the arithmetic unit / 262 \\ 8.4.3 Remarks / 263 \\ 8.4.4 Fast carry resolution / 265 \\ 8.5 Informal sketch for computing an exact dot product / 267 \\ 8.6 Scalar product computation units (SPUs) / 267 \\ 8.6.1 SPU for computers with a 32 bit data bus / 269 \\ 8.6.2 A coprocessor chip for the exact scalar product / 272 \\ 8.6.3 SPU for computers with a 64 bit data bus / 275 \\ 8.7 Comments / 278 \\ 8.7.1 Rounding / 278 \\ 8.7.2 How much local memory should be provided on an SPU? / 279 \\ 8.8 The data format complete and complete arithmetic / 281 \\ 8.8.1 Low level instructions for complete arithmetic / 282 \\ 8.8.2 Complete arithmetic in high level programming languages / 283 \\ 8.9 Top speed scalar product units / 287 \\ 8.9.1 SPU with long adder for 64 bit data word / 287 \\ 8.9.2 SPU with long adder for 32 bit data word / 292 \\ 8.9.3 An FPGA coprocessor for the exact scalar product / 295 \\ 8.9.4 SPU with short adder and complete register / 295 \\ 8.9.5 Carry-free accumulation of products in redundant arithmetic 301 \\ 8.10 Hardware complete register window / 302 \\ III Principles of verified computing \\ 9 Sample applications 307 \\ 9.1 Basic properties of interval mathematics / 309 \\ 9.1.1 Interval arithmetic, a powerful calculus to deal with inequalities / 309 \\ 9.1.2 Interval arithmetic as executable set operations / 310 \\ 9.1.3 Enclosing the range of function values / 316 \\ 9.1.4 Nonzero property of a function, global optimization / 319 \\ 9.2 Differentiation arithmetic, enclosures of derivatives / 321 \\ 9.3 The interval Newton method / 329 \\ 9.4 The extended interval Newton method / 332 \\ 9.5 Verified solution of systems of linear equations / 333 \\ 9.6 Accurate evaluation of arithmetic expressions / 340 \\ 9.6.1 Complete expressions / 341 \\ 9.6.2 Accurate evaluation of polynomials / 342 \\ 9.6.3 Arithmetic expressions / 346 \\ 9.7 Multiple precision arithmetics / 347 \\ 9.7.1 Multiple precision floating-point arithmetic / 348 \\ 9.7.2 Multiple precision interval arithmetic / 351 \\ 9.7.3 Applications / 356 \\ 9.7.4 Adding an exponent part as a scaling factor to complete \\ arithmetic / 358 \\ 9.8 Remarks on Kaucher arithmetic / 360 \\ 9.8.1 The basic operations of Kaucher arithmetic / 364 \\ A Frequently used symbols 367 \\ B On homomorphism 369 \\ Bibliography 371 \\ List of figures 421 \\ List of tables 425 \\ Index 427

entry:
@Book{Kulisch:2013:CAV,
  author =       "Ulrich Kulisch",
  title =        "Computer Arithmetic and Validity",
  volume =       "33",
  publisher =    pub-GRUYTER,
  address =      pub-GRUYTER:adr,
  edition =      "Second",
  pages =        "xxii + 434",
  year =         "2013",
  DOI =          "https://doi.org/10.1515/9783110301793",
  ISBN =         "3-11-030173-3, 3-11-030179-2 (e-book), 3-11-030180-6
                 (set)",
  ISBN-13 =      "978-3-11-030173-1, 978-3-11-030179-3 (e-book),
                 978-3-11-030180-9 (set)",
  ISSN =         "0179-0986",
  ISSN-L =       "0179-0986",
  LCCN =         "QA76.9.C62 K853 2013",
  bibdate =      "Sat May 18 08:56:52 MDT 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcw.bib;
                 z3950.loc.gov:7090/Voyager",
  series =       "De Gruyter studies in mathematics",
  abstract =     "This is the revised and extended second edition of the
                 successful basic book on computer arithmetic. It is
                 consistent with the newest recent standard developments
                 in the field. The book shows how the arithmetic
                 capability of the computer can be enhanced. The work is
                 motivated by the desire and the need to improve the
                 accuracy of numerical computing and to control the
                 quality of the computed results (validity). The
                 accuracy requirements for the elementary floating-point
                 operations are extended to the customary product spaces
                 of computations including interval spaces. The
                 mathematical properties of these models are extracted
                 and lead to a general theory of computer arithmetic.
                 Detailed methods and circuits for the implementation of
                 this advanced computer arithmetic are developed in the
                 book. It illustrates how the extended arithmetic can be
                 used to compute highly accurate and mathematically
                 verified results. The book can be used as a high-level
                 undergraduate textbook but also as reference work for
                 research in computer arithmetic and applied
                 mathematics.",
  acknowledgement = ack-nhfb,
  subject =      "computer arithmetic; computer arithmetic and logic
                 units; floating-point arithmetic",
  tableofcontents = "Foreword to the second edition vii \\
                 Preface / ix \\
                 Introduction / 1 \\
                 I Theory of computer arithmetic \\
                 1 First concepts 13 \\
                 1.1 Ordered sets / 13 \\
                 1.2 Complete lattices and complete subnets / 18 \\
                 1.3 Screens and roundings / 24 \\
                 1.4 Arithmetic operations and roundings / 35 \\
                 2 Ringoids and vectoids 43 \\
                 2.1 Ringoids / 43 \\
                 2.2 Vectoids / 54 \\
                 3 Definition of computer arithmetic 62 \\
                 3.1 Introduction / 62 \\
                 3.2 Preliminaries / 65 \\
                 3.3 The traditional definition of computer arithmetic /
                 69 \\
                 3.4 Definition of computer arithmetic by semimorphisms
                 / 70 \\
                 3.5 A remark about roundings / 78 \\
                 3.6 Uniqueness of the minus operator / 79 \\
                 3.7 Rounding near zero / 81 \\
                 4 Interval arithmetic 87 \\
                 4.1 Interval sets and arithmetic / 88 \\
                 4.2 Interval arithmetic over a linearly ordered set /
                 97 \\
                 4.3 Interval matrices / 101 \\
                 4.4 Interval vectors / 107 \\
                 4.5 Interval arithmetic on a screen / 110 \\
                 7.2 Arithmetic interval operations / 237 \\
                 7.2.1 Algebraic operations / 238 \\
                 7.2.2 Comments on the algebraic operations / 240 \\
                 7.3 Circuitry for the arithmetic interval operations /
                 241 \\
                 7.4 Comparisons and lattice operations / 242 \\
                 7.4.1 Comments on comparisons and lattice operations /
                 243 \\
                 7.4.2 Hardware support for comparisons and lattice
                 operations / 243 \\
                 7.5 Alternative circuitry for interval operations and
                 comparisons / 244 \\
                 7.5.1 Hardware support for interval arithmetic on
                 x86-processors 245 \\
                 7.5.2 Accurate evaluation of interval scalar products /
                 247 \\
                 8 Scalar products and complete arithmetic 249 \\
                 8.1 Introduction and motivation / 250 \\
                 8.2 Historical remarks / 252 \\
                 8.3 The ubiquity of the scalar product in numerical
                 analysis / 257 \\
                 8.4 Implementation principles / 260 \\
                 8.4.1 Long adder and long shift / 262 \\
                 8.4.2 Short adder with local memory on the arithmetic
                 unit / 262 \\
                 8.4.3 Remarks / 263 \\
                 8.4.4 Fast carry resolution / 265 \\
                 8.5 Informal sketch for computing an exact dot product
                 / 267 \\
                 8.6 Scalar product computation units (SPUs) / 267 \\
                 8.6.1 SPU for computers with a 32 bit data bus / 269
                 \\
                 8.6.2 A coprocessor chip for the exact scalar product /
                 272 \\
                 8.6.3 SPU for computers with a 64 bit data bus / 275
                 \\
                 8.7 Comments / 278 \\
                 8.7.1 Rounding / 278 \\
                 8.7.2 How much local memory should be provided on an
                 SPU? / 279 \\
                 8.8 The data format complete and complete arithmetic /
                 281 \\
                 8.8.1 Low level instructions for complete arithmetic /
                 282 \\
                 8.8.2 Complete arithmetic in high level programming
                 languages / 283 \\
                 8.9 Top speed scalar product units / 287 \\
                 8.9.1 SPU with long adder for 64 bit data word / 287
                 \\
                 8.9.2 SPU with long adder for 32 bit data word / 292
                 \\
                 8.9.3 An FPGA coprocessor for the exact scalar product
                 / 295 \\
                 8.9.4 SPU with short adder and complete register / 295
                 \\
                 8.9.5 Carry-free accumulation of products in redundant
                 arithmetic 301 \\
                 8.10 Hardware complete register window / 302 \\
                 III Principles of verified computing \\
                 9 Sample applications 307 \\
                 9.1 Basic properties of interval mathematics / 309 \\
                 9.1.1 Interval arithmetic, a powerful calculus to deal
                 with inequalities / 309 \\
                 9.1.2 Interval arithmetic as executable set operations
                 / 310 \\
                 9.1.3 Enclosing the range of function values / 316 \\
                 9.1.4 Nonzero property of a function, global
                 optimization / 319 \\
                 9.2 Differentiation arithmetic, enclosures of
                 derivatives / 321 \\
                 9.3 The interval Newton method / 329 \\
                 9.4 The extended interval Newton method / 332 \\
                 9.5 Verified solution of systems of linear equations /
                 333 \\
                 9.6 Accurate evaluation of arithmetic expressions / 340
                 \\
                 9.6.1 Complete expressions / 341 \\
                 9.6.2 Accurate evaluation of polynomials / 342 \\
                 9.6.3 Arithmetic expressions / 346 \\
                 9.7 Multiple precision arithmetics / 347 \\
                 9.7.1 Multiple precision floating-point arithmetic /
                 348 \\
                 9.7.2 Multiple precision interval arithmetic / 351 \\
                 9.7.3 Applications / 356 \\
                 9.7.4 Adding an exponent part as a scaling factor to
                 complete \\
                 arithmetic / 358 \\
                 9.8 Remarks on Kaucher arithmetic / 360 \\
                 9.8.1 The basic operations of Kaucher arithmetic / 364
                 \\
                 A Frequently used symbols 367 \\
                 B On homomorphism 369 \\
                 Bibliography 371 \\
                 List of figures 421 \\
                 List of tables 425 \\
                 Index 427",
}


bibtype: article
filename: fparith.bib
label: Kupriianova:2013:RCIa
author: O. Kupriianova and Ch. Lauter and Jean-Michel Muller
title: Radix Conversion for IEEE754-2008 Mixed Radix Floating-Point Arithmetic
journal: arXiv.org
pages: ??--??
day: 2
month: dec
monthnumber: 12
year: 2013
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1312.0455
subject: Mathematical Software (cs.MS)
acknowledgement: ack-nhfb
rawauthor: O. Kupriianova and Ch. Lauter and Jean-Michel Muller
rawtitle: Radix Conversion for {IEEE754-2008} Mixed Radix Floating-Point Arithmetic
abstract:
Conversion between binary and decimal floating-point representations is ubiquitous. Floating-point radix conversion means converting both the exponent and the mantissa. We develop an atomic operation for FP radix conversion with simple straight-line algorithm, suitable for hardware design. Exponent conversion is performed with a small multiplication and a lookup table. It yields the correct result without error. Mantissa conversion uses a few multiplications and a small lookup table that is shared amongst all types of conversions. The accuracy changes by adjusting the computing precision.

rawabstract:
Conversion between binary and decimal floating-point representations is ubiquitous. Floating-point radix conversion means converting both the exponent and the mantissa. We develop an atomic operation for FP radix conversion with simple straight-line algorithm, suitable for hardware design. Exponent conversion is performed with a small multiplication and a lookup table. It yields the correct result without error. Mantissa conversion uses a few multiplications and a small lookup table that is shared amongst all types of conversions. The accuracy changes by adjusting the computing precision.

entry:
@Article{Kupriianova:2013:RCIa,
  author =       "O. Kupriianova and Ch. Lauter and Jean-Michel Muller",
  title =        "Radix Conversion for {IEEE754-2008} Mixed Radix
                 Floating-Point Arithmetic",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "2",
  month =        dec,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1312.0455",
  abstract =     "Conversion between binary and decimal floating-point
                 representations is ubiquitous. Floating-point radix
                 conversion means converting both the exponent and the
                 mantissa. We develop an atomic operation for FP radix
                 conversion with simple straight-line algorithm,
                 suitable for hardware design. Exponent conversion is
                 performed with a small multiplication and a lookup
                 table. It yields the correct result without error.
                 Mantissa conversion uses a few multiplications and a
                 small lookup table that is shared amongst all types of
                 conversions. The accuracy changes by adjusting the
                 computing precision.",
  acknowledgement = ack-nhfb,
  subject =      "Mathematical Software (cs.MS)",
}


bibtype: inproceedings
filename: fparith.bib
label: Kupriianova:2013:RCIb
author: Olga Kupriianova and Christoph Lauter and Jean-Michel Muller
editor: Michael B. Matthews
title: Radix conversion for IEEE754-2008 mixed radix floating-point arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1134--1138
year: 2013
DOI: https://doi.org/10.1109/ACSSC.2013.6810471
ISBN: 1-4799-2390-7 OR 1479923907
ISBN13: 978-1-4799-2390-8 OR 9781479923908
bibdate: Fri Sep 29 10:52:22 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 10:52:22 ???
acknowledgement: ack-nhfb
rawauthor: Olga Kupriianova and Christoph Lauter and Jean-Michel Muller
raweditor: Michael B. Matthews
rawtitle: Radix conversion for {IEEE754-2008} mixed radix floating-point arithmetic
booktitle:
The Forty-Seventh Asilomar Conference on Signals, Systems and Computers. November 3--6, 2013. Pacific Grove, California

rawbooktitle:
{The Forty-Seventh Asilomar Conference on Signals, Systems and Computers. November 3--6, 2013. Pacific Grove, California}

entry:
@InProceedings{Kupriianova:2013:RCIb,
  author =       "Olga Kupriianova and Christoph Lauter and Jean-Michel
                 Muller",
  editor =       "Michael B. Matthews",
  booktitle =    "{The Forty-Seventh Asilomar Conference on Signals,
                 Systems and Computers. November 3--6, 2013. Pacific
                 Grove, California}",
  title =        "Radix conversion for {IEEE754-2008} mixed radix
                 floating-point arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1134--1138",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ACSSC.2013.6810471",
  ISBN =         "1-4799-2390-7",
  ISBN-13 =      "978-1-4799-2390-8",
  bibdate =      "Fri Sep 29 10:52:22 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Kurka:2013:UAA
author: Petr Kurka and Martin Delacourt
title: The Unary Arithmetical Algorithm in Bimodular Number Systems
crossref: IEEE:2013:PIS
pages: 127--134
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.10
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Petr K{\r{u}}rka and Martin Delacourt
rawtitle: The Unary Arithmetical Algorithm in Bimodular Number Systems
keywords:
Absorption; ARITH-21; bimodular number system; binary signed system; computational complexity; Convergence; Electronic mail; exact real arithmetic; expansion subshifts; linear average time complexity; Moebius number systems; Moebius transformation; Random variables; residue number systems; statistical analysis; statistical evidence; Time complexity; Transducers; unary arithmetical algorithm; Vectors

entry:
@InProceedings{Kurka:2013:UAA,
  author =       "Petr K{\r{u}}rka and Martin Delacourt",
  title =        "The Unary Arithmetical Algorithm in Bimodular Number
                 Systems",
  crossref =     "IEEE:2013:PIS",
  pages =        "127--134",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.10",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Absorption; ARITH-21; bimodular number system; binary
                 signed system; computational complexity; Convergence;
                 Electronic mail; exact real arithmetic; expansion
                 subshifts; linear average time complexity; Moebius
                 number systems; Moebius transformation; Random
                 variables; residue number systems; statistical
                 analysis; statistical evidence; Time complexity;
                 Transducers; unary arithmetical algorithm; Vectors",
}


bibtype: article
filename: fparith.bib
label: Lam:2013:DFP
author: Michael O. Lam and Jeffrey K. Hollingsworth and G. W. Stewart
title: Dynamic floating-point cancellation detection
journal: j-PARALLEL-COMPUTING
volume: 39
number: 3
pages: 146--155
month: mar
monthnumber: 3
year: 2013
CODEN: PACOEJ
ISSN: 0167-8191 (print), 1872-7336 (electronic) OR 01678191 (print), 18727336 (electronic)
ISSNL: 0167-8191 OR 01678191
bibdate: Wed Mar 27 07:19:15 MDT 2013
bibtimestamp: 2013.03.27 07:19:15 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0167819112000622
fjournal: Parallel Computing
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/01678191
rawauthor: Michael O. Lam and Jeffrey K. Hollingsworth and G. W. Stewart
rawtitle: Dynamic floating-point cancellation detection
bibsource:
http://www.sciencedirect.com/science/journal/01678191; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/parallelcomputing.bib

entry:
@Article{Lam:2013:DFP,
  author =       "Michael O. Lam and Jeffrey K. Hollingsworth and G. W.
                 Stewart",
  title =        "Dynamic floating-point cancellation detection",
  journal =      j-PARALLEL-COMPUTING,
  volume =       "39",
  number =       "3",
  pages =        "146--155",
  month =        mar,
  year =         "2013",
  CODEN =        "PACOEJ",
  ISSN =         "0167-8191 (print), 1872-7336 (electronic)",
  ISSN-L =       "0167-8191",
  bibdate =      "Wed Mar 27 07:19:15 MDT 2013",
  bibsource =    "http://www.sciencedirect.com/science/journal/01678191;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/parallelcomputing.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0167819112000622",
  acknowledgement = ack-nhfb,
  fjournal =     "Parallel Computing",
  journal-URL =  "http://www.sciencedirect.com/science/journal/01678191",
}


bibtype: misc
filename: fparith.bib
label: Lefevre:2013:HRC
author: Vincent Lefevre
title: Hardest-to-Round Cases: Part 2
pages: 30
day: 8
month: oct
monthnumber: 10
year: 2013
bibdate: Wed Oct 09 09:40:50 2019
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2019.10.09 09:40:50 ???
acknowledgement: ack-nhfb
howpublished: Lecture slides from ENS-Lyon, France.
rawauthor: Vincent Lef{\`e}vre
rawtitle: Hardest-to-Round Cases: Part 2
remark:
From the slides: `After 13,812,778 CPU core hours ($ approx $ 1576 years) for the first step'', the hardest cases for correct rounding in the IEEE 754 binary64 format were found for $ e^x $, $ 2^x $, $ 10^x $, $ sinh $, $ cosh $, $ sin (2 pi x) $, $ cos (2 pi x) $, $ tan (2 pi x) $; for $ x^n $ for $ n in [ - 180, - 2] $ and $ n in [3, 5188] $; for $ sin (x) $, $ cos (x) $, and $ tan (x) $ for $ x in [ - pi / 2, + pi / 2] $; and for their inverse functions.

entry:
@Misc{Lefevre:2013:HRC,
  author =       "Vincent Lef{\`e}vre",
  title =        "Hardest-to-Round Cases: Part 2",
  howpublished = "Lecture slides from ENS-Lyon, France.",
  pages =        "30",
  day =          "8",
  month =        oct,
  year =         "2013",
  bibdate =      "Wed Oct 09 09:40:50 2019",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  remark =       "From the slides: `After 13,812,778 CPU core hours ($
                 \approx $ 1576 years) for the first step'', the hardest
                 cases for correct rounding in the IEEE 754 binary64
                 format were found for $ e^x $, $ 2^x $, $ 10^x $, $
                 \sinh $, $ \cosh $, $ \sin (2 \pi x) $, $ \cos (2 \pi
                 x) $, $ \tan (2 \pi x) $; for $ x^n $ for $ n \in [ -
                 180, - 2] $ and $ n \in [3, 5188] $; for $ \sin (x) $,
                 $ \cos (x) $, and $ \tan (x) $ for $ x \in [ - \pi / 2,
                 + \pi / 2] $; and for their inverse functions.",
}


bibtype: techreport
filename: fparith.bib
label: Lefevre:2013:SML
author: Vincent Lefevre
title: Sipe: a mini-library for very low precision computations with correct rounding.
type: Report
number: hal-00864580
institution: INRIA, LIP / CNRS / ENS Lyon / Universite de Lyon
address: Lyon, France
pages: 13
day: 22
month: sep
monthnumber: 9
year: 2013
bibdate: Sat Dec 23 12:04:45 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.12.23 12:04:45 ???
URL: https://inria.hal.science/hal-00864580
acknowledgement: ack-nhfb
rawauthor: Vincent Lef{\`e}vre
rawtitle: {Sipe}: a mini-library for very low precision computations with correct rounding.
abstract:
Sipe is a mini-library in the form of a C header file, to perform radix-2 floating-point computations in very low precisions with correct rounding, either to nearest or toward zero. The goal of such a tool is to do proofs of algorithms / properties or computations of tight error bounds in these precisions by exhaustive tests, in order to try to generalize them to higher precisions. The currently supported operations are addition, subtraction, multiplication (possibly with the error term), fused multiply-add / subtract (FMA / FMS), and miscellaneous comparisons and conversions. sipe provides two implementations of these operations, with the same API and the same behavior: one based on integer arithmetic, and a new one based on floating-point arithmetic. Timing comparisons have been done with hardware IEEE-754 floating point and with GNU MPFR.

rawabstract:
Sipe is a mini-library in the form of a C header file, to perform radix-2 floating-point computations in very low precisions with correct rounding, either to nearest or toward zero. The goal of such a tool is to do proofs of algorithms\slash properties or computations of tight error bounds in these precisions by exhaustive tests, in order to try to generalize them to higher precisions. The currently supported operations are addition, subtraction, multiplication (possibly with the error term), fused multiply-add\slash subtract (FMA\slash FMS), and miscellaneous comparisons and conversions. sipe provides two implementations of these operations, with the same API and the same behavior: one based on integer arithmetic, and a new one based on floating-point arithmetic. Timing comparisons have been done with hardware IEEE-754 floating point and with GNU MPFR.

entry:
@TechReport{Lefevre:2013:SML,
  author =       "Vincent Lef{\`e}vre",
  title =        "{Sipe}: a mini-library for very low precision
                 computations with correct rounding.",
  type =         "Report",
  number =       "hal-00864580",
  institution =  "INRIA, LIP / CNRS / ENS Lyon / Universit{\'e} de
                 Lyon",
  address =      "Lyon, France",
  pages =        "13",
  day =          "22",
  month =        sep,
  year =         "2013",
  bibdate =      "Sat Dec 23 12:04:45 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://inria.hal.science/hal-00864580",
  abstract =     "Sipe is a mini-library in the form of a C header file,
                 to perform radix-2 floating-point computations in very
                 low precisions with correct rounding, either to nearest
                 or toward zero. The goal of such a tool is to do proofs
                 of algorithms\slash properties or computations of tight
                 error bounds in these precisions by exhaustive tests,
                 in order to try to generalize them to higher
                 precisions. The currently supported operations are
                 addition, subtraction, multiplication (possibly with
                 the error term), fused multiply-add\slash subtract
                 (FMA\slash FMS), and miscellaneous comparisons and
                 conversions. sipe provides two implementations of these
                 operations, with the same API and the same behavior:
                 one based on integer arithmetic, and a new one based on
                 floating-point arithmetic. Timing comparisons have been
                 done with hardware IEEE-754 floating point and with GNU
                 MPFR.",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Lefevre:2013:SSI
author: Vincent Lefevre
title: SIPE: Small Integer Plus Exponent
crossref: IEEE:2013:PIS
pages: 99--106
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.22
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
URL: http://hal.inria.fr/hal-00763954
acknowledgement: ack-nhfb
rawauthor: Vincent Lef{\`e}vre
rawtitle: {SIPE}: Small Integer Plus Exponent
keywords:
addition; Algorithm design and analysis; ARITH-21; arithmetic operations; C header file; Computers; Context; correct rounding; floating point arithmetic; floating-point computations; FMA; GNU MPFR; Hardware; hardware IEEE-754 floating point; IEEE standards; Libraries; low precision; mini-library; multiplication; radix 2; SIPE; small integer plus exponent; Standards; subtraction; Timing; timing comparisons

entry:
@InProceedings{Lefevre:2013:SSI,
  author =       "Vincent Lef{\`e}vre",
  title =        "{SIPE}: Small Integer Plus Exponent",
  crossref =     "IEEE:2013:PIS",
  pages =        "99--106",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.22",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://hal.inria.fr/hal-00763954",
  acknowledgement = ack-nhfb,
  keywords =     "addition; Algorithm design and analysis; ARITH-21;
                 arithmetic operations; C header file; Computers;
                 Context; correct rounding; floating point arithmetic;
                 floating-point computations; FMA; GNU MPFR; Hardware;
                 hardware IEEE-754 floating point; IEEE standards;
                 Libraries; low precision; mini-library; multiplication;
                 radix 2; SIPE; small integer plus exponent; Standards;
                 subtraction; Timing; timing comparisons",
}


bibtype: article
filename: fparith.bib
label: Lei:2013:FIE
author: Yuanwu Lei and Yong Dou and Yazhuo Dong and Jie Zhou and Fei Xia
journal: j-J-SUPERCOMPUTING
volume: 64
number: 2
pages: 580--605
month: may
monthnumber: 5
year: 2013
CODEN: JOSUED
DOI: https://doi.org/10.1007/s11227-012-0860-0
ISSN: 0920-8542 (print), 1573-0484 (electronic) OR 09208542 (print), 15730484 (electronic)
ISSNL: 0920-8542 OR 09208542
bibdate: Sat Feb 8 10:21:14 MST 2014
bibtimestamp: 2014.02.08 10:21:14 MST
URL: http://link.springer.com/article/10.1007/s11227-012-0860-0
fjournal: The Journal of Supercomputing
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/11227
rawauthor: Yuanwu Lei and Yong Dou and Yazhuo Dong and Jie Zhou and Fei Xia
title:
FPGA implementation of an exact dot product and its application in variable-precision floating-point arithmetic

bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0920-8542&volume=64&issue=2; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jsuper.bib

rawtitle:
{FPGA} implementation of an exact dot product and its application in variable-precision floating-point arithmetic

entry:
@Article{Lei:2013:FIE,
  author =       "Yuanwu Lei and Yong Dou and Yazhuo Dong and Jie Zhou
                 and Fei Xia",
  title =        "{FPGA} implementation of an exact dot product and its
                 application in variable-precision floating-point
                 arithmetic",
  journal =      j-J-SUPERCOMPUTING,
  volume =       "64",
  number =       "2",
  pages =        "580--605",
  month =        may,
  year =         "2013",
  CODEN =        "JOSUED",
  DOI =          "https://doi.org/10.1007/s11227-012-0860-0",
  ISSN =         "0920-8542 (print), 1573-0484 (electronic)",
  ISSN-L =       "0920-8542",
  bibdate =      "Sat Feb 8 10:21:14 MST 2014",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0920-8542&volume=64&issue=2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jsuper.bib",
  URL =          "http://link.springer.com/article/10.1007/s11227-012-0860-0",
  acknowledgement = ack-nhfb,
  fjournal =     "The Journal of Supercomputing",
  journal-URL =  "http://link.springer.com/journal/11227",
}


bibtype: article
filename: fparith.bib
label: Lei:2013:VCI
author: Yuanwu Lei and Yong Dou and Lei Guo and Jinbo Xu and Jie Zhou and Yazhuo Dong and Hongjian Li
title: VLIW coprocessor for IEEE-754 quadruple-precision elementary functions
journal: j-TACO
volume: 10
number: 3
pages: 12:1--12:??
month: sep
monthnumber: 9
year: 2013
DOI: https://doi.org/10.1145/2512430
ISSN: 1544-3566 (print), 1544-3973 (electronic) OR 15443566 (print), 15443973 (electronic)
ISSNL: 1544-3566 OR 15443566
bibdate: Mon Sep 16 17:20:12 MDT 2013
bibtimestamp: 2013.09.16 17:20:12 MDT
fjournal: ACM Transactions on Architecture and Code Optimization (TACO)
acknowledgement: ack-nhfb
articleno: 12
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J924
rawauthor: Yuanwu Lei and Yong Dou and Lei Guo and Jinbo Xu and Jie Zhou and Yazhuo Dong and Hongjian Li
rawtitle: {VLIW} coprocessor for {IEEE-754} quadruple-precision elementary functions
abstract:
In this article, a unified VLIW coprocessor, based on a common group of atomic operation units, for Quad arithmetic and elementary functions (QP_VELP) is presented. The explicitly parallel scheme of VLIW instruction and Estrin's evaluation scheme for polynomials are used to improve the performance. A two-level VLIW instruction RAM scheme is introduced to achieve high scalability and customizability, even for more complex key program kernels. Finally, the Quad arithmetic accelerator (QAA) with the QP_VELP array is implemented on ASIC. Compared with hyper-thread software implementation on an Intel Xeon E5620, QAA with 8 QP_VELP units achieves improvement by a factor of 18X.

rawabstract:
In this article, a unified VLIW coprocessor, based on a common group of atomic operation units, for Quad arithmetic and elementary functions (QP\_VELP) is presented. The explicitly parallel scheme of VLIW instruction and Estrin's evaluation scheme for polynomials are used to improve the performance. A two-level VLIW instruction RAM scheme is introduced to achieve high scalability and customizability, even for more complex key program kernels. Finally, the Quad arithmetic accelerator (QAA) with the QP\_VELP array is implemented on ASIC. Compared with hyper-thread software implementation on an Intel Xeon E5620, QAA with 8 QP\_VELP units achieves improvement by a factor of 18X.

entry:
@Article{Lei:2013:VCI,
  author =       "Yuanwu Lei and Yong Dou and Lei Guo and Jinbo Xu and
                 Jie Zhou and Yazhuo Dong and Hongjian Li",
  title =        "{VLIW} coprocessor for {IEEE-754} quadruple-precision
                 elementary functions",
  journal =      j-TACO,
  volume =       "10",
  number =       "3",
  pages =        "12:1--12:??",
  month =        sep,
  year =         "2013",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/2512430",
  ISSN =         "1544-3566 (print), 1544-3973 (electronic)",
  ISSN-L =       "1544-3566",
  bibdate =      "Mon Sep 16 17:20:12 MDT 2013",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/taco.bib",
  abstract =     "In this article, a unified VLIW coprocessor, based on
                 a common group of atomic operation units, for Quad
                 arithmetic and elementary functions (QP\_VELP) is
                 presented. The explicitly parallel scheme of VLIW
                 instruction and Estrin's evaluation scheme for
                 polynomials are used to improve the performance. A
                 two-level VLIW instruction RAM scheme is introduced to
                 achieve high scalability and customizability, even for
                 more complex key program kernels. Finally, the Quad
                 arithmetic accelerator (QAA) with the QP\_VELP array is
                 implemented on ASIC. Compared with hyper-thread
                 software implementation on an Intel Xeon E5620, QAA
                 with 8 QP\_VELP units achieves improvement by a factor
                 of 18X.",
  acknowledgement = ack-nhfb,
  articleno =    "12",
  fjournal =     "ACM Transactions on Architecture and Code Optimization
                 (TACO)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J924",
}


bibtype: article
filename: fparith.bib
label: Lowery:2013:RED
author: Bradley R. Lowery
title: Relative error due to a single bit-flip in floating-point arithmetic
journal: arXiv.org
pages: 1--6
day: 15
month: apr
monthnumber: 4
year: 2013
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1304.4292
subject: Numerical Analysis (cs.NA)
acknowledgement: ack-nhfb
rawauthor: Bradley R. Lowery
rawtitle: Relative error due to a single bit-flip in floating-point arithmetic
abstract:
We consider the error due to a single bit-flip in a floating point number. We assume IEEE 754 double precision arithmetic, which encodes binary floating point numbers in a 64-bit word. We assume that the bit-flip happens randomly so it has equi-probability (1/64) to hit any of the 64 bits. Since we want to mitigate the assumption on our initial floating-point number, we assume that it is uniformly picked among all normalized number. With this framework, we can summarize our findings as follows. The probability for a single bit flip to cause a relative error less than $ 10^-11 $ in a normalized floating-point number is above 25%; The probability for a single bit flip to cause a relative error less than $ 10^-6 $ in a normalized floating-point number is above 50%; Etc.

rawabstract:
We consider the error due to a single bit-flip in a floating point number. We assume IEEE 754 double precision arithmetic, which encodes binary floating point numbers in a 64-bit word. We assume that the bit-flip happens randomly so it has equi-probability (1/64) to hit any of the 64 bits. Since we want to mitigate the assumption on our initial floating-point number, we assume that it is uniformly picked among all normalized number. With this framework, we can summarize our findings as follows. The probability for a single bit flip to cause a relative error less than $ 10^{-11} $ in a normalized floating-point number is above 25\%; The probability for a single bit flip to cause a relative error less than $ 10^{-6} $ in a normalized floating-point number is above 50\%; Etc.

entry:
@Article{Lowery:2013:RED,
  author =       "Bradley R. Lowery",
  title =        "Relative error due to a single bit-flip in
                 floating-point arithmetic",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--6",
  day =          "15",
  month =        apr,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1304.4292",
  abstract =     "We consider the error due to a single bit-flip in a
                 floating point number. We assume IEEE 754 double
                 precision arithmetic, which encodes binary floating
                 point numbers in a 64-bit word. We assume that the
                 bit-flip happens randomly so it has equi-probability
                 (1/64) to hit any of the 64 bits. Since we want to
                 mitigate the assumption on our initial floating-point
                 number, we assume that it is uniformly picked among all
                 normalized number. With this framework, we can
                 summarize our findings as follows. The probability for
                 a single bit flip to cause a relative error less than $
                 10^{-11} $ in a normalized floating-point number is
                 above 25\%; The probability for a single bit flip to
                 cause a relative error less than $ 10^{-6} $ in a
                 normalized floating-point number is above 50\%; Etc.",
  acknowledgement = ack-nhfb,
  subject =      "Numerical Analysis (cs.NA)",
}


bibtype: article
filename: fparith.bib
label: Maitra:2013:DSM
author: Subhashis Maitra and Amitabha Sinha
title: Design and simulation of MAC unit using combinational circuit and adder
journal: j-COMP-ARCH-NEWS
volume: 41
number: 5
pages: 25--33
month: dec
monthnumber: 12
year: 2013
CODEN: CANED2
DOI: https://doi.org/10.1145/2641361.2641365
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Mon Aug 18 17:12:43 MDT 2014
bibtimestamp: 2014.08.18 17:12:43 MDT
fjournal: ACM SIGARCH Computer Architecture News
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J89
rawauthor: Subhashis Maitra and Amitabha Sinha
rawtitle: Design and simulation of {MAC} unit using combinational circuit and adder
abstract:
Hardware and timing complexities of MAC unit to perform arithmetic operation like addition or multiplication especially in the field of Digital Signal Processing (DSP) or Elliptic Curve Cryptography (ECC) are the major issues to the designer. The multiplication operation is essential and abundant in DSP Applications. In order to achieve maximum implementation efficiency and timing performance, designing a DSP systems is critical and frequently presents a significant challenge to hardware engineers. There are certain multipliers that simplify this challenge by abstracting away FPGA device specifics, while maintaining the required maximum performance and resource efficiency. These multipliers are able to perform parallel multiplication and hence constant coefficient multiplication, both with differing implementation styles. Again with the aid of instantaneous resource estimation, hardware engineers can rapidly select the optimal solution for their system. The latest additions to the IP provide fine control over the latency using the concept of pipelining of the multipliers that are purely combinatorial to be fully pipelined. Here a new compensation method that reduces both the hardware and timing complexities of the multiplier used for DSP application or ECC application has been proposed. The design of the MAC unit based on the proposed compensation method has been dealt here properly using Xilinx 13.2 and compared with array multiplier, Booth multiplier and Vedic multiplier to show its novelty over them. The hardware complexity is reduced to about 60% of the original multiplier. Design results show that the proposed architecture has lower hardware overhead, lower error and fast operating speed as compared with array, Booth and Vedic multiplier.

rawabstract:
Hardware and timing complexities of MAC unit to perform arithmetic operation like addition or multiplication especially in the field of Digital Signal Processing (DSP) or Elliptic Curve Cryptography (ECC) are the major issues to the designer. The multiplication operation is essential and abundant in DSP Applications. In order to achieve maximum implementation efficiency and timing performance, designing a DSP systems is critical and frequently presents a significant challenge to hardware engineers. There are certain multipliers that simplify this challenge by abstracting away FPGA device specifics, while maintaining the required maximum performance and resource efficiency. These multipliers are able to perform parallel multiplication and hence constant coefficient multiplication, both with differing implementation styles. Again with the aid of instantaneous resource estimation, hardware engineers can rapidly select the optimal solution for their system. The latest additions to the IP provide fine control over the latency using the concept of pipelining of the multipliers that are purely combinatorial to be fully pipelined. Here a new compensation method that reduces both the hardware and timing complexities of the multiplier used for DSP application or ECC application has been proposed. The design of the MAC unit based on the proposed compensation method has been dealt here properly using Xilinx 13.2 and compared with array multiplier, Booth multiplier and Vedic multiplier to show its novelty over them. The hardware complexity is reduced to about 60\% of the original multiplier. Design results show that the proposed architecture has lower hardware overhead, lower error and fast operating speed as compared with array, Booth and Vedic multiplier.

entry:
@Article{Maitra:2013:DSM,
  author =       "Subhashis Maitra and Amitabha Sinha",
  title =        "Design and simulation of {MAC} unit using
                 combinational circuit and adder",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "41",
  number =       "5",
  pages =        "25--33",
  month =        dec,
  year =         "2013",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/2641361.2641365",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Mon Aug 18 17:12:43 MDT 2014",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Hardware and timing complexities of MAC unit to
                 perform arithmetic operation like addition or
                 multiplication especially in the field of Digital
                 Signal Processing (DSP) or Elliptic Curve Cryptography
                 (ECC) are the major issues to the designer. The
                 multiplication operation is essential and abundant in
                 DSP Applications. In order to achieve maximum
                 implementation efficiency and timing performance,
                 designing a DSP systems is critical and frequently
                 presents a significant challenge to hardware engineers.
                 There are certain multipliers that simplify this
                 challenge by abstracting away FPGA device specifics,
                 while maintaining the required maximum performance and
                 resource efficiency. These multipliers are able to
                 perform parallel multiplication and hence constant
                 coefficient multiplication, both with differing
                 implementation styles. Again with the aid of
                 instantaneous resource estimation, hardware engineers
                 can rapidly select the optimal solution for their
                 system. The latest additions to the IP provide fine
                 control over the latency using the concept of
                 pipelining of the multipliers that are purely
                 combinatorial to be fully pipelined. Here a new
                 compensation method that reduces both the hardware and
                 timing complexities of the multiplier used for DSP
                 application or ECC application has been proposed. The
                 design of the MAC unit based on the proposed
                 compensation method has been dealt here properly using
                 Xilinx 13.2 and compared with array multiplier, Booth
                 multiplier and Vedic multiplier to show its novelty
                 over them. The hardware complexity is reduced to about
                 60\% of the original multiplier. Design results show
                 that the proposed architecture has lower hardware
                 overhead, lower error and fast operating speed as
                 compared with array, Booth and Vedic multiplier.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
}


bibtype: article
filename: fparith.bib
label: Maniatakos:2013:LCC
author: Michail Maniatakos and Prabhakar Kudva and Bruce M. Fleischer and Yiorgos Makris
title: Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers
journal: j-IEEE-TRANS-COMPUT
volume: 62
number: 7
pages: 1376--1388
month: jul
monthnumber: 7
year: 2013
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2012.81
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Jun 17 15:07:53 2013
bibtimestamp: 2013.06.17 15:07:53 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Michail Maniatakos and Prabhakar Kudva and Bruce M. Fleischer and Yiorgos Makris
rawtitle: Low-Cost Concurrent Error Detection for Floating-Point Unit ({FPU}) Controllers
entry:
@Article{Maniatakos:2013:LCC,
  author =       "Michail Maniatakos and Prabhakar Kudva and Bruce M.
                 Fleischer and Yiorgos Makris",
  title =        "Low-Cost Concurrent Error Detection for Floating-Point
                 Unit ({FPU}) Controllers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "62",
  number =       "7",
  pages =        "1376--1388",
  month =        jul,
  year =         "2013",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2012.81",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Jun 17 15:07:53 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Martin-Dorel:2013:SIR
author: Erik Martin-Dorel and Guillaume Melquiond and Jean-Michel Muller
title: Some issues related to double rounding
journal: j-BIT-NUM-MATH
volume: 53
number: 4
pages: 897--924
month: dec
monthnumber: 12
year: 2013
CODEN: BITTEL, NBITAB
DOI: https://doi.org/10.1007/s10543-013-0436-2
ISSN: 0006-3835 (print), 1572-9125 (electronic) OR 00063835 (print), 15729125 (electronic)
ISSNL: 0006-3835 OR 00063835
bibdate: Mon Dec 2 16:05:03 MST 2013
bibtimestamp: 2013.12.02 16:05:03 MST
URL: http://link.springer.com/article/10.1007/s10543-013-0436-2
fjournal: BIT Numerical Mathematics
acknowledgement: ack-nhfb
journalURL: http://link.springer.com/journal/10543
rawauthor: {\'E}rik Martin-Dorel and Guillaume Melquiond and Jean-Michel Muller
rawtitle: Some issues related to double rounding
bibsource:
http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0006-3835&volume=53&issue=4; https://www.math.utah.edu/pub/tex/bib/bit.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Martin-Dorel:2013:SIR,
  author =       "{\'E}rik Martin-Dorel and Guillaume Melquiond and
                 Jean-Michel Muller",
  title =        "Some issues related to double rounding",
  journal =      j-BIT-NUM-MATH,
  volume =       "53",
  number =       "4",
  pages =        "897--924",
  month =        dec,
  year =         "2013",
  CODEN =        "BITTEL, NBITAB",
  DOI =          "https://doi.org/10.1007/s10543-013-0436-2",
  ISSN =         "0006-3835 (print), 1572-9125 (electronic)",
  ISSN-L =       "0006-3835",
  bibdate =      "Mon Dec 2 16:05:03 MST 2013",
  bibsource =    "http://springerlink.metapress.com/openurl.asp?genre=issue&issn=0006-3835&volume=53&issue=4;
                 https://www.math.utah.edu/pub/tex/bib/bit.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://link.springer.com/article/10.1007/s10543-013-0436-2",
  acknowledgement = ack-nhfb,
  fjournal =     "BIT Numerical Mathematics",
  journal-URL =  "http://link.springer.com/journal/10543",
}


bibtype: inproceedings
filename: fparith.bib
label: Muller:2013:ADR
author: Jean-Michel Muller
editor: Michael B. Matthews
title: Avoiding double roundings in scaled Newton--Raphson division
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 396--399
year: 2013
DOI: https://doi.org/10.1109/ACSSC.2013.6810304
ISBN: 1-4799-2390-7 OR 1479923907
ISBN13: 978-1-4799-2390-8 OR 9781479923908
bibdate: Fri Sep 29 10:48:21 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 10:48:21 ???
acknowledgement: ack-nhfb
rawauthor: Jean-Michel Muller
raweditor: Michael B. Matthews
rawtitle: Avoiding double roundings in scaled {Newton--Raphson} division
booktitle:
The Forty-Seventh Asilomar Conference on Signals, Systems and Computers. November 3--6, 2013. Pacific Grove, California

rawbooktitle:
{The Forty-Seventh Asilomar Conference on Signals, Systems and Computers. November 3--6, 2013. Pacific Grove, California}

entry:
@InProceedings{Muller:2013:ADR,
  author =       "Jean-Michel Muller",
  editor =       "Michael B. Matthews",
  booktitle =    "{The Forty-Seventh Asilomar Conference on Signals,
                 Systems and Computers. November 3--6, 2013. Pacific
                 Grove, California}",
  title =        "Avoiding double roundings in scaled {Newton--Raphson}
                 division",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "396--399",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ACSSC.2013.6810304",
  ISBN =         "1-4799-2390-7",
  ISBN-13 =      "978-1-4799-2390-8",
  bibdate =      "Fri Sep 29 10:48:21 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Nathan:2013:REB
title: Recycled Error Bits: Energy-Efficient Architectural Support for Higher Precision Floating Point
journal: arXiv.org
pages: ??--??
day: 27
month: sep
monthnumber: 9
year: 2013
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1309.7321
subject: Hardware Architecture (cs.AR)
acknowledgement: ack-nhfb
rawtitle: Recycled Error Bits: Energy-Efficient Architectural Support for Higher Precision Floating Point
author:
Ralph Nathan and Bryan Anthonio and Shih-Lien Lu and Helia Naeimi and Daniel J. Sorin and Xiaobai Sun

abstract:
In this work, we provide energy-efficient architectural support for floating point accuracy. Our goal is to provide accuracy that is far greater than that provided by the processor's hardware floating point unit (FPU). Specifically, for each floating point addition performed, we ``recycle'' that operation's error: the difference between the finite-precision result produced by the hardware and the result that would have been produced by an infinite-precision FPU. We make this error architecturally visible such that it can be used, if desired, by software. Experimental results on physical hardware show that software that exploits architecturally recycled error bits can achieve accuracy comparable to a 2B-bit FPU with performance and energy that are comparable to a B-bit FPU.

rawabstract:
In this work, we provide energy-efficient architectural support for floating point accuracy. Our goal is to provide accuracy that is far greater than that provided by the processor's hardware floating point unit (FPU). Specifically, for each floating point addition performed, we ``recycle'' that operation's error: the difference between the finite-precision result produced by the hardware and the result that would have been produced by an infinite-precision FPU. We make this error architecturally visible such that it can be used, if desired, by software. Experimental results on physical hardware show that software that exploits architecturally recycled error bits can achieve accuracy comparable to a 2B-bit FPU with performance and energy that are comparable to a B-bit FPU.

rawauthor:
Ralph Nathan and Bryan Anthonio and Shih-Lien Lu and Helia Naeimi and Daniel J. Sorin and Xiaobai Sun

entry:
@Article{Nathan:2013:REB,
  author =       "Ralph Nathan and Bryan Anthonio and Shih-Lien Lu and
                 Helia Naeimi and Daniel J. Sorin and Xiaobai Sun",
  title =        "Recycled Error Bits: Energy-Efficient Architectural
                 Support for Higher Precision Floating Point",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "27",
  month =        sep,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1309.7321",
  abstract =     "In this work, we provide energy-efficient
                 architectural support for floating point accuracy. Our
                 goal is to provide accuracy that is far greater than
                 that provided by the processor's hardware floating
                 point unit (FPU). Specifically, for each floating point
                 addition performed, we ``recycle'' that operation's
                 error: the difference between the finite-precision
                 result produced by the hardware and the result that
                 would have been produced by an infinite-precision FPU.
                 We make this error architecturally visible such that it
                 can be used, if desired, by software. Experimental
                 results on physical hardware show that software that
                 exploits architecturally recycled error bits can
                 achieve accuracy comparable to a 2B-bit FPU with
                 performance and energy that are comparable to a B-bit
                 FPU.",
  acknowledgement = ack-nhfb,
  subject =      "Hardware Architecture (cs.AR)",
}


bibtype: article
filename: fparith.bib
label: Nguyen:2013:SED
author: Trung Duc Nguyen and Rodney Van Meter
title: A Space-Efficient Design for Reversible Floating Point Adder in Quantum Computing
journal: arXiv.org
pages: 1--11
day: 17
month: jun
monthnumber: 6
year: 2013
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1306.3760
subject: Quantum Physics (quant-ph); Emerging Technologies (cs.ET)
acknowledgement: ack-nhfb
rawauthor: Trung Duc Nguyen and Rodney {Van Meter}
rawtitle: A Space-Efficient Design for Reversible Floating Point Adder in Quantum Computing
abstract:
Reversible logic has applications in low-power computing and quantum computing. However, there are few existing designs for reversible floating-point adders and none suitable for quantum computation. In this paper we propose a space-efficient reversible floating-point adder, suitable for binary quantum computation, improving the design of Nachtigal et al. Our work focuses on improving the reversible designs of the alignment unit and the normalization unit, which are the most expensive parts. By changing a few elements of the existing algorithm, including the circuit designs of the RLZC (reversible leading zero counter) and converter, we have reduced the cost about 68%. We also propose fault-tolerant designs for the circuits. The KQ for our fault-tolerant design is almost sixty times as expensive as for a 32-bit fixed-point addition. We note that the floating-point representation makes in-place, truly reversible arithmetic impossible, requiring us to retain both inputs, which limits the sustainability of its use for quantum computation.

rawabstract:
Reversible logic has applications in low-power computing and quantum computing. However, there are few existing designs for reversible floating-point adders and none suitable for quantum computation. In this paper we propose a space-efficient reversible floating-point adder, suitable for binary quantum computation, improving the design of Nachtigal et al. Our work focuses on improving the reversible designs of the alignment unit and the normalization unit, which are the most expensive parts. By changing a few elements of the existing algorithm, including the circuit designs of the RLZC (reversible leading zero counter) and converter, we have reduced the cost about 68\%. We also propose fault-tolerant designs for the circuits. The KQ for our fault-tolerant design is almost sixty times as expensive as for a 32-bit fixed-point addition. We note that the floating-point representation makes in-place, truly reversible arithmetic impossible, requiring us to retain both inputs, which limits the sustainability of its use for quantum computation.

entry:
@Article{Nguyen:2013:SED,
  author =       "Trung Duc Nguyen and Rodney {Van Meter}",
  title =        "A Space-Efficient Design for Reversible Floating Point
                 Adder in Quantum Computing",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--11",
  day =          "17",
  month =        jun,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1306.3760",
  abstract =     "Reversible logic has applications in low-power
                 computing and quantum computing. However, there are few
                 existing designs for reversible floating-point adders
                 and none suitable for quantum computation. In this
                 paper we propose a space-efficient reversible
                 floating-point adder, suitable for binary quantum
                 computation, improving the design of Nachtigal et al.
                 Our work focuses on improving the reversible designs of
                 the alignment unit and the normalization unit, which
                 are the most expensive parts. By changing a few
                 elements of the existing algorithm, including the
                 circuit designs of the RLZC (reversible leading zero
                 counter) and converter, we have reduced the cost about
                 68\%. We also propose fault-tolerant designs for the
                 circuits. The KQ for our fault-tolerant design is
                 almost sixty times as expensive as for a 32-bit
                 fixed-point addition. We note that the floating-point
                 representation makes in-place, truly reversible
                 arithmetic impossible, requiring us to retain both
                 inputs, which limits the sustainability of its use for
                 quantum computation.",
  acknowledgement = ack-nhfb,
  subject =      "Quantum Physics (quant-ph); Emerging Technologies
                 (cs.ET)",
}


bibtype: article
filename: fparith.bib
label: Nikolajsen:2013:FSD
author: Jorgen L. Nikolajsen
title: Fractional Significant Digits
journal: j-SIAM-J-SCI-COMP
volume: 35
number: 2
pages: A561--A576
year: 2013
CODEN: SJOCE3
DOI: https://doi.org/10.1137/110828435
ISSN: 1064-8275 (print), 1095-7197 (electronic) OR 10648275 (print), 10957197 (electronic)
ISSNL: 1064-8275 OR 10648275
bibdate: Fri Jul 19 07:43:46 MDT 2013
bibtimestamp: 2013.07.19 07:43:46 MDT
fjournal: SIAM Journal on Scientific Computing
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sisc
onlinedate: January 2013
rawauthor: Jorgen L. Nikolajsen
rawtitle: Fractional Significant Digits
bibsource:
http://epubs.siam.org/sam-bin/dbq/toc/SISC/35/2; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib

entry:
@Article{Nikolajsen:2013:FSD,
  author =       "Jorgen L. Nikolajsen",
  title =        "Fractional Significant Digits",
  journal =      j-SIAM-J-SCI-COMP,
  volume =       "35",
  number =       "2",
  pages =        "A561--A576",
  month =        "????",
  year =         "2013",
  CODEN =        "SJOCE3",
  DOI =          "https://doi.org/10.1137/110828435",
  ISSN =         "1064-8275 (print), 1095-7197 (electronic)",
  ISSN-L =       "1064-8275",
  bibdate =      "Fri Jul 19 07:43:46 MDT 2013",
  bibsource =    "http://epubs.siam.org/sam-bin/dbq/toc/SISC/35/2;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjscicomput.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Scientific Computing",
  journal-URL =  "http://epubs.siam.org/sisc",
  onlinedate =   "January 2013",
}


bibtype: article
filename: fparith.bib
label: Ould-Bachir:2013:SAS
author: Tarek Ould-Bachir and Jean Pierre David
title: Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators
journal: j-TRETS
volume: 6
number: 1
pages: 1:1--1:??
month: may
monthnumber: 5
year: 2013
DOI: https://doi.org/10.1145/2457443.2457444
ISSN: 1936-7406 (print), 1936-7414 (electronic) OR 19367406 (print), 19367414 (electronic)
ISSNL: 1936-7406 OR 19367406
bibdate: Thu Mar 13 08:09:42 MDT 2014
bibtimestamp: 2014.03.13 08:09:42 MDT
fjournal: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
acknowledgement: ack-nhfb
articleno: 1
journalURL: http://portal.acm.org/toc.cfm?id=J1151
rawauthor: Tarek Ould-Bachir and Jean Pierre David
rawtitle: Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/trets.bib

abstract:
Advances in semiconductor technology brings to the market incredibly dense devices, capable of handling tens to hundreds floating-point operators on a single chip; so do the latest field programmable gate arrays (FPGAs). In order to alleviate the complexity of resorting to these devices in computationally intensive applications, this article proposes hardware schemes for the realization of addition-related floating-point operators based on the self-alignment technique (SAT). The article demonstrates that the schemes guarantee an accuracy as if summation was computed accurately in the precision of operator's internal mantissa, then faithfully rounded to working precision. To achieve such performance, the article adopts the redundant high radix carry-save (HRCS) format for the rapid addition of wide mantissas. Implementation results show that combining the SAT and the HRCS format allows the implementation of complex operators with reduced area and latency, more so when a fused-path approach is adopted. The article also proposes a new hardware operator for performing endomorphic HRCS additions and presents a new technique for speeding up the conversion from the redundant HRCS to a conventional binary format.

rawabstract:
Advances in semiconductor technology brings to the market incredibly dense devices, capable of handling tens to hundreds floating-point operators on a single chip; so do the latest field programmable gate arrays (FPGAs). In order to alleviate the complexity of resorting to these devices in computationally intensive applications, this article proposes hardware schemes for the realization of addition-related floating-point operators based on the self-alignment technique (SAT). The article demonstrates that the schemes guarantee an accuracy as if summation was computed accurately in the precision of operator's internal mantissa, then faithfully rounded to working precision. To achieve such performance, the article adopts the redundant high radix carry-save (HRCS) format for the rapid addition of wide mantissas. Implementation results show that combining the SAT and the HRCS format allows the implementation of complex operators with reduced area and latency, more so when a fused-path approach is adopted. The article also proposes a new hardware operator for performing endomorphic HRCS additions and presents a new technique for speeding up the conversion from the redundant HRCS to a conventional binary format.

entry:
@Article{Ould-Bachir:2013:SAS,
  author =       "Tarek Ould-Bachir and Jean Pierre David",
  title =        "Self-Alignment Schemes for the Implementation of
                 Addition-Related Floating-Point Operators",
  journal =      j-TRETS,
  volume =       "6",
  number =       "1",
  pages =        "1:1--1:??",
  month =        may,
  year =         "2013",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/2457443.2457444",
  ISSN =         "1936-7406 (print), 1936-7414 (electronic)",
  ISSN-L =       "1936-7406",
  bibdate =      "Thu Mar 13 08:09:42 MDT 2014",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/trets.bib",
  abstract =     "Advances in semiconductor technology brings to the
                 market incredibly dense devices, capable of handling
                 tens to hundreds floating-point operators on a single
                 chip; so do the latest field programmable gate arrays
                 (FPGAs). In order to alleviate the complexity of
                 resorting to these devices in computationally intensive
                 applications, this article proposes hardware schemes
                 for the realization of addition-related floating-point
                 operators based on the self-alignment technique (SAT).
                 The article demonstrates that the schemes guarantee an
                 accuracy as if summation was computed accurately in the
                 precision of operator's internal mantissa, then
                 faithfully rounded to working precision. To achieve
                 such performance, the article adopts the redundant high
                 radix carry-save (HRCS) format for the rapid addition
                 of wide mantissas. Implementation results show that
                 combining the SAT and the HRCS format allows the
                 implementation of complex operators with reduced area
                 and latency, more so when a fused-path approach is
                 adopted. The article also proposes a new hardware
                 operator for performing endomorphic HRCS additions and
                 presents a new technique for speeding up the conversion
                 from the redundant HRCS to a conventional binary
                 format.",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  fjournal =     "ACM Transactions on Reconfigurable Technology and
                 Systems (TRETS)",
  journal-URL =  "http://portal.acm.org/toc.cfm?id=J1151",
}


bibtype: article
filename: fparith.bib
label: Ozaki:2013:GEF
author: Katsuhisa Ozaki and Takeshi Ogita and Shin'ichi Oishi and Siegfried M. Rump
title: Generalization of error-free transformation for matrix multiplication and its application
journal: j-NONLINEAR-THEORY-APPL
volume: 4
number: 1
pages: 2--11
year: 2013
DOI: https://doi.org/10.1587/nolta.4.2
ISSN: 2185-4106 OR 21854106
ISSNL: 2185-4106 OR 21854106
bibdate: Sat Feb 8 19:02:28 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.02.08 19:02:28 ???
URL: https://www.jstage.jst.go.jp/article/nolta/4/1/4_2/_article
fjournal: Nonlinear Theory and Its Applications, IEICE
acknowledgement: ack-nhfb
journalURL: https://www.jstage.jst.go.jp/browse/nolta/
rawauthor: Katsuhisa Ozaki and Takeshi Ogita and Shin'ichi Oishi and Siegfried M. Rump
rawtitle: Generalization of error-free transformation for matrix multiplication and its application
entry:
@Article{Ozaki:2013:GEF,
  author =       "Katsuhisa Ozaki and Takeshi Ogita and Shin'ichi Oishi
                 and Siegfried M. Rump",
  title =        "Generalization of error-free transformation for matrix
                 multiplication and its application",
  journal =      j-NONLINEAR-THEORY-APPL,
  volume =       "4",
  number =       "1",
  pages =        "2--11",
  year =         "2013",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1587/nolta.4.2",
  ISSN =         "2185-4106",
  ISSN-L =       "2185-4106",
  bibdate =      "Sat Feb 8 19:02:28 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.jstage.jst.go.jp/article/nolta/4/1/4_2/_article",
  acknowledgement = ack-nhfb,
  fjournal =     "Nonlinear Theory and Its Applications, {IEICE}",
  journal-URL =  "https://www.jstage.jst.go.jp/browse/nolta/",
}


bibtype: inproceedings
filename: fparith.bib
label: Pedram:2013:FPA
author: Ardavan Pedram and Andreas Gerstlauer and Robert A. van de Geijn
title: Floating Point Architecture Extensions for Optimized Matrix Factorization
crossref: IEEE:2013:PIS
pages: 49--58
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.21
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Ardavan Pedram and Andreas Gerstlauer and Robert A. van de Geijn
rawtitle: Floating Point Architecture Extensions for Optimized Matrix Factorization
keywords:
Algorithm design and analysis; application specific integrated circuits; architectural modifications; architecture complexity; ARITH-21; Cholesky; Complexity theory; computational complexity; Computer architecture; custom linear algebra processor; dense linear systems; design trade-offs; floating point; floating point architecture extensions; floating point arithmetic; floating point units; full-custom ASIC designs; least mean squares methods; linear algebra; linear least-squares problems; low power; LU factorization; MAC units; Matrix decomposition; matrix decomposition; matrix factorization; optimized matrix factorization; QR factorizations; Registers; Vectors

entry:
@InProceedings{Pedram:2013:FPA,
  author =       "Ardavan Pedram and Andreas Gerstlauer and Robert A.
                 van de Geijn",
  title =        "Floating Point Architecture Extensions for Optimized
                 Matrix Factorization",
  crossref =     "IEEE:2013:PIS",
  pages =        "49--58",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.21",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithm design and analysis; application specific
                 integrated circuits; architectural modifications;
                 architecture complexity; ARITH-21; Cholesky; Complexity
                 theory; computational complexity; Computer
                 architecture; custom linear algebra processor; dense
                 linear systems; design trade-offs; floating point;
                 floating point architecture extensions; floating point
                 arithmetic; floating point units; full-custom ASIC
                 designs; least mean squares methods; linear algebra;
                 linear least-squares problems; low power; LU
                 factorization; MAC units; Matrix decomposition; matrix
                 decomposition; matrix factorization; optimized matrix
                 factorization; QR factorizations; Registers; Vectors",
}


bibtype: article
filename: fparith.bib
label: Pontarelli:2013:LCC
author: Salvatore Pontarelli and Pedro Reviriego and Chris J. Bleakley and Juan Antonio Maestro
title: Low Complexity Concurrent Error Detection for Complex Multiplication
journal: j-IEEE-TRANS-COMPUT
volume: 62
number: 9
pages: 1899--1903
month: sep
monthnumber: 9
year: 2013
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2012.246
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Nov 15 08:54:34 2013
bibtimestamp: 2013.11.15 08:54:34 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Salvatore Pontarelli and Pedro Reviriego and Chris J. Bleakley and Juan Antonio Maestro
rawtitle: Low Complexity Concurrent Error Detection for Complex Multiplication
entry:
@Article{Pontarelli:2013:LCC,
  author =       "Salvatore Pontarelli and Pedro Reviriego and Chris J.
                 Bleakley and Juan Antonio Maestro",
  title =        "Low Complexity Concurrent Error Detection for Complex
                 Multiplication",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "62",
  number =       "9",
  pages =        "1899--1903",
  month =        sep,
  year =         "2013",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2012.246",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Nov 15 08:54:34 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Rubio-Gonzalez:2013:PTA
title: Precimonious: Tuning assistant for floating-point precision
publisher: pub-ACM
address: pub-ACM:adr
pages: 27
year: 2013
bibdate: Sat Jun 4 17:18:19 2016
bibtimestamp: 2016.06.04 17:18:19 ???
acknowledgement: ack-nhfb
rawtitle: {Precimonious}: Tuning assistant for floating-point precision
author:
Cindy Rubio-Gonzalez and Cuong Nguyen and Hong Diep Nguyen and James Demmel and William Kahan and Koushik Sen and David H. Bailey and Costin Iancu and David Hough

booktitle:
Proceedings of the SC13's International Conference on High Performance Computing, Networking, Storage and Analysis, Denver, CO, USA

rawauthor:
Cindy Rubio-Gonz{\'a}lez and Cuong Nguyen and Hong Diep Nguyen and James Demmel and William Kahan and Koushik Sen and David H. Bailey and Costin Iancu and David Hough

rawbooktitle:
Proceedings of the {SC13's} International Conference on High Performance Computing, Networking, Storage and Analysis, Denver, {CO}, {USA}

entry:
@InProceedings{Rubio-Gonzalez:2013:PTA,
  author =       "Cindy Rubio-Gonz{\'a}lez and Cuong Nguyen and Hong
                 Diep Nguyen and James Demmel and William Kahan and
                 Koushik Sen and David H. Bailey and Costin Iancu and
                 David Hough",
  booktitle =    "Proceedings of the {SC13's} International Conference
                 on High Performance Computing, Networking, Storage and
                 Analysis, Denver, {CO}, {USA}",
  title =        "{Precimonious}: Tuning assistant for floating-point
                 precision",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "27",
  year =         "2013",
  bibdate =      "Sat Jun 4 17:18:19 2016",
  bibsource =    "https://www.math.utah.edu/pub/bibnet/authors/k/kahan-william-m.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Rump:2013:ASDa
author: Siegfried M. Rump
title: Accurate solution of dense linear systems, Part I: Algorithms in rounding to nearest
journal: j-J-COMPUT-APPL-MATH
volume: 242
pages: 157--184
month: apr
monthnumber: 4
year: 2013
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:26:15 MST 2017
bibtimestamp: 2017.02.25 13:26:15 MST
URL: http://www.sciencedirect.com/science/article/pii/S0377042712004360
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Siegfried M. Rump
rawtitle: Accurate solution of dense linear systems, {Part I}: Algorithms in rounding to nearest
entry:
@Article{Rump:2013:ASDa,
  author =       "Siegfried M. Rump",
  title =        "Accurate solution of dense linear systems, {Part I}:
                 Algorithms in rounding to nearest",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "242",
  number =       "??",
  pages =        "157--184",
  month =        apr,
  year =         "2013",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:26:15 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2010.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042712004360",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: article
filename: fparith.bib
label: Rump:2013:ASDb
author: Siegfried M. Rump
title: Accurate solution of dense linear systems, Part II: Algorithms using directed rounding
journal: j-J-COMPUT-APPL-MATH
volume: 242
pages: 185--212
month: apr
monthnumber: 4
year: 2013
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:26:15 MST 2017
bibtimestamp: 2017.02.25 13:26:15 MST
URL: http://www.sciencedirect.com/science/article/pii/S0377042712003974
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: Siegfried M. Rump
rawtitle: Accurate solution of dense linear systems, Part {II}: Algorithms using directed rounding
entry:
@Article{Rump:2013:ASDb,
  author =       "Siegfried M. Rump",
  title =        "Accurate solution of dense linear systems, Part {II}:
                 Algorithms using directed rounding",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "242",
  number =       "??",
  pages =        "185--212",
  month =        apr,
  year =         "2013",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:26:15 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2010.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042712003974",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: inproceedings
filename: fparith.bib
label: Rupley:2013:FPU
title: The Floating-Point Unit of the Jaguar x86 Core
crossref: IEEE:2013:PIS
pages: 7--16
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.24
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawtitle: The Floating-Point Unit of the {Jaguar} x86 Core
author:
Jeff Rupley and John King and Eric Quinnell and Frank Galloway and Ken Patton and Peter-Michael Seidel and James Dinh and Hai Bui and Anasua Bhowmik

keywords:
Adders; AES; AES instruction set; AMD Jaguar; AMD Jaguar x86 core; ARITH-21; arithmetic and logic unit; AVX; AVX instruction set; bypass network; CLMUL; CLMUL instruction set; CMOS process; complimentary metal oxide semiconductor; coprocessor model; coprocessors; Decoding; dedicated renamer; dual-issue scheduler; execution pipe; F16C; F16C instruction set; floating point arithmetic; floating-point adder; floating-point iterative multiplier; floating-point unit; formal verification; formal verification technique; FPU; free list; industry implementation; instruction sets; low-power design; Microarchitecture; MMX; native floating-point unit; Optimization; Out of order; physical register file; PRF; pseudorandom verification technique; Registers; retire queue; scheduling; size 28 nm; SSE; SSE4.2 instruction set; vector integer ALU; vector integer MUL unit; Vectors; x86 ISA extension; x87

rawauthor:
Jeff Rupley and John King and Eric Quinnell and Frank Galloway and Ken Patton and Peter-Michael Seidel and James Dinh and Hai Bui and Anasua Bhowmik

entry:
@InProceedings{Rupley:2013:FPU,
  author =       "Jeff Rupley and John King and Eric Quinnell and Frank
                 Galloway and Ken Patton and Peter-Michael Seidel and
                 James Dinh and Hai Bui and Anasua Bhowmik",
  title =        "The Floating-Point Unit of the {Jaguar} x86 Core",
  crossref =     "IEEE:2013:PIS",
  pages =        "7--16",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.24",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; AES; AES instruction set; AMD Jaguar; AMD
                 Jaguar x86 core; ARITH-21; arithmetic and logic unit;
                 AVX; AVX instruction set; bypass network; CLMUL; CLMUL
                 instruction set; CMOS process; complimentary metal
                 oxide semiconductor; coprocessor model; coprocessors;
                 Decoding; dedicated renamer; dual-issue scheduler;
                 execution pipe; F16C; F16C instruction set; floating
                 point arithmetic; floating-point adder; floating-point
                 iterative multiplier; floating-point unit; formal
                 verification; formal verification technique; FPU; free
                 list; industry implementation; instruction sets;
                 low-power design; Microarchitecture; MMX; native
                 floating-point unit; Optimization; Out of order;
                 physical register file; PRF; pseudorandom verification
                 technique; Registers; retire queue; scheduling; size 28
                 nm; SSE; SSE4.2 instruction set; vector integer ALU;
                 vector integer MUL unit; Vectors; x86 ISA extension;
                 x87",
}


bibtype: article
filename: fparith.bib
label: Russinoff:2013:CFV
author: David M. Russinoff
title: Computation and Formal Verification of SRT Quotient and Square Root Digit Selection Tables
journal: j-IEEE-TRANS-COMPUT
volume: 62
number: 5
pages: 900--913
month: may
monthnumber: 5
year: 2013
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2012.40
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Apr 30 12:26:22 2013
bibtimestamp: 2013.04.30 12:26:22 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: David M. Russinoff
rawtitle: Computation and Formal Verification of {SRT} Quotient and Square Root Digit Selection Tables
bibsource:
https://www.math.utah.edu/pub/tex/bib/elefunt.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib

entry:
@Article{Russinoff:2013:CFV,
  author =       "David M. Russinoff",
  title =        "Computation and Formal Verification of {SRT} Quotient
                 and Square Root Digit Selection Tables",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "62",
  number =       "5",
  pages =        "900--913",
  month =        may,
  year =         "2013",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2012.40",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Apr 30 12:26:22 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Saha:2013:PAF
author: Amrita Saha and Manideepa Mukherjee and Debanjana Datta and Sangita Saha and Amitabha Sinha
title: Performance analysis of a FPGA based novel binary and DBNS multiplier
journal: j-COMP-ARCH-NEWS
volume: 41
number: 2
pages: 9--16
month: may
monthnumber: 5
year: 2013
CODEN: CANED2
DOI: https://doi.org/10.1145/2490302.2490305
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Sat Jun 1 11:00:26 MDT 2013
bibtimestamp: 2013.06.01 11:00:26 MDT
fjournal: ACM SIGARCH Computer Architecture News
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J89
rawauthor: Amrita Saha and Manideepa Mukherjee and Debanjana Datta and Sangita Saha and Amitabha Sinha
rawtitle: Performance analysis of a {FPGA} based novel binary and {DBNS} multiplier
abstract:
Designing high performance Software Defined Radio (SDR) with low power and flexibility is a major challenge. While the high performance DSP processors are unable to meet the speed requirements of these SDRs, System on chips (SOCs) are also not suitable because of their limited flexibility. Recently dynamically reconfigurable FPGAs have emerged as high performance programmable hardware to execute highly parallel, computationally intensive signal processing functions efficiently. Since basic intention of an SDR is to implement different modulation / demodulation schemes and basic building blocks for such schemes are signal processing functions, FPGAs have become an important component for implementing these. However, the effectiveness of such an approach with respect to cost, performance and flexibility need to be examined. Double Base Number Systems (DBNS) have been gaining attention for compute intensive applications in signal processing because of their higher performance in arithmetic operations in general and particularly multiplication. Keeping these issues in view, this paper aims to present a new Software defined Radio. To Enhance the performance of the proposed architecture , analysis have been done employing both single index and multiple indices DBNS multipliers. Experiments and analysis on performance have also been done with its binary counterpart. Both DBNS and binary based architecture were implemented on Xilinx virtex iv FPGA using xilinx ISE 9.1 i.

rawabstract:
Designing high performance Software Defined Radio (SDR) with low power and flexibility is a major challenge. While the high performance DSP processors are unable to meet the speed requirements of these SDRs, System on chips (SOCs) are also not suitable because of their limited flexibility. Recently dynamically reconfigurable FPGAs have emerged as high performance programmable hardware to execute highly parallel, computationally intensive signal processing functions efficiently. Since basic intention of an SDR is to implement different modulation / demodulation schemes and basic building blocks for such schemes are signal processing functions, FPGAs have become an important component for implementing these. However, the effectiveness of such an approach with respect to cost, performance and flexibility need to be examined. Double Base Number Systems (DBNS) have been gaining attention for compute intensive applications in signal processing because of their higher performance in arithmetic operations in general and particularly multiplication. Keeping these issues in view, this paper aims to present a new Software defined Radio. To Enhance the performance of the proposed architecture , analysis have been done employing both single index and multiple indices DBNS multipliers. Experiments and analysis on performance have also been done with its binary counterpart. Both DBNS and binary based architecture were implemented on Xilinx virtex iv FPGA using xilinx ISE 9.1 i.

entry:
@Article{Saha:2013:PAF,
  author =       "Amrita Saha and Manideepa Mukherjee and Debanjana
                 Datta and Sangita Saha and Amitabha Sinha",
  title =        "Performance analysis of a {FPGA} based novel binary
                 and {DBNS} multiplier",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "41",
  number =       "2",
  pages =        "9--16",
  month =        may,
  year =         "2013",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/2490302.2490305",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Sat Jun 1 11:00:26 MDT 2013",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Designing high performance Software Defined Radio
                 (SDR) with low power and flexibility is a major
                 challenge. While the high performance DSP processors
                 are unable to meet the speed requirements of these
                 SDRs, System on chips (SOCs) are also not suitable
                 because of their limited flexibility. Recently
                 dynamically reconfigurable FPGAs have emerged as high
                 performance programmable hardware to execute highly
                 parallel, computationally intensive signal processing
                 functions efficiently. Since basic intention of an SDR
                 is to implement different modulation / demodulation
                 schemes and basic building blocks for such schemes are
                 signal processing functions, FPGAs have become an
                 important component for implementing these. However,
                 the effectiveness of such an approach with respect to
                 cost, performance and flexibility need to be examined.
                 Double Base Number Systems (DBNS) have been gaining
                 attention for compute intensive applications in signal
                 processing because of their higher performance in
                 arithmetic operations in general and particularly
                 multiplication. Keeping these issues in view, this
                 paper aims to present a new Software defined Radio. To
                 Enhance the performance of the proposed architecture ,
                 analysis have been done employing both single index and
                 multiple indices DBNS multipliers. Experiments and
                 analysis on performance have also been done with its
                 binary counterpart. Both DBNS and binary based
                 architecture were implemented on Xilinx virtex iv FPGA
                 using xilinx ISE 9.1 i.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
}


bibtype: article
filename: fparith.bib
label: SaiToh:2013:ZCL
author: Akira SaiToh
title: ZKCM: a C++ library for multiprecision matrix computation with applications in quantum information
journal: j-COMP-PHYS-COMM
volume: 184
number: 8
pages: 2005--2020
month: aug
monthnumber: 8
year: 2013
CODEN: CPHCBZ
ISSN: 0010-4655 (print), 1879-2944 (electronic) OR 00104655 (print), 18792944 (electronic)
ISSNL: 0010-4655 OR 00104655
bibdate: Wed May 15 07:02:08 MDT 2013
bibtimestamp: 2013.05.15 07:02:08 MDT
URL: http://www.sciencedirect.com/science/article/pii/S0010465513001306
fjournal: Computer Physics Communications
keywords: GNU GMP library; MPFR library
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00104655
rawauthor: Akira SaiToh
bibsource:
https://www.math.utah.edu/pub/tex/bib/compphyscomm2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/gnu.bib

rawtitle:
{ZKCM}: a {C++} library for multiprecision matrix computation with applications in quantum information

entry:
@Article{SaiToh:2013:ZCL,
  author =       "Akira SaiToh",
  title =        "{ZKCM}: a {C++} library for multiprecision matrix
                 computation with applications in quantum information",
  journal =      j-COMP-PHYS-COMM,
  volume =       "184",
  number =       "8",
  pages =        "2005--2020",
  month =        aug,
  year =         "2013",
  CODEN =        "CPHCBZ",
  ISSN =         "0010-4655 (print), 1879-2944 (electronic)",
  ISSN-L =       "0010-4655",
  bibdate =      "Wed May 15 07:02:08 MDT 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/compphyscomm2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/gnu.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0010465513001306",
  acknowledgement = ack-nhfb,
  fjournal =     "Computer Physics Communications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00104655",
  keywords =     "GNU GMP library; MPFR library",
}


bibtype: article
filename: fparith.bib
label: Shen:2013:SCC
author: Tao Shen and Zhugang Yuan
title: Stability criterion for a class of fixed-point digital filters using two's complement arithmetic
journal: j-APPL-MATH-COMP
volume: 219
number: 9
pages: 4880--4883
day: 1
month: jan
monthnumber: 1
year: 2013
CODEN: AMHCBQ
DOI: https://doi.org/10.1016/j.amc.2012.10.064
ISSN: 0096-3003 (print), 1873-5649 (electronic) OR 00963003 (print), 18735649 (electronic)
ISSNL: 0096-3003 OR 00963003
bibdate: Mon Dec 17 14:08:35 MST 2012
bibtimestamp: 2012.12.17 14:08:35 MST
URL: http://www.sciencedirect.com/science/article/pii/S0096300312010806
fjournal: Applied Mathematics and Computation
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/00963003/
rawauthor: Tao Shen and Zhugang Yuan
rawtitle: Stability criterion for a class of fixed-point digital filters using two's complement arithmetic
bibsource:
https://www.math.utah.edu/pub/tex/bib/applmathcomput2010.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Shen:2013:SCC,
  author =       "Tao Shen and Zhugang Yuan",
  title =        "Stability criterion for a class of fixed-point digital
                 filters using two's complement arithmetic",
  journal =      j-APPL-MATH-COMP,
  volume =       "219",
  number =       "9",
  pages =        "4880--4883",
  day =          "1",
  month =        jan,
  year =         "2013",
  CODEN =        "AMHCBQ",
  DOI =          "https://doi.org/10.1016/j.amc.2012.10.064",
  ISSN =         "0096-3003 (print), 1873-5649 (electronic)",
  ISSN-L =       "0096-3003",
  bibdate =      "Mon Dec 17 14:08:35 MST 2012",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/applmathcomput2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0096300312010806",
  acknowledgement = ack-nhfb,
  fjournal =     "Applied Mathematics and Computation",
  journal-URL =  "http://www.sciencedirect.com/science/journal/00963003/",
}


bibtype: inproceedings
filename: fparith.bib
label: Sohn:2013:IAF
author: Jongwook Sohn and Earl E. Swartzlander, Jr.
title: Improved Architectures for a Floating-Point Fused Dot Product Unit
crossref: IEEE:2013:PIS
pages: 41--48
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.26
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Jongwook Sohn and Earl E. {Swartzlander, Jr.}
rawtitle: Improved Architectures for a Floating-Point Fused Dot Product Unit
keywords:
Adders; alignment scheme; ARITH-21; complex multiplication; Computer architecture; data flow analysis; DCT butterfly operations; Digital signal processing; digital signal processing; Digital signal processing (DSP); discrete cosine transform butterfly operations; DSP applications; dual-path algorithm; early normalization; fast Fourier transform; FFT; floating point arithmetic; floating-point arithmetic; floating-point fused operations; floating-point fused two-term dot product unit; four-input leading zero anticipation; high-speed computer arithmetic; libraries; nonpipelined dual-path design; pipeline processing; Pipeline processing; pipelining; Power demand; signal processing; size 45 nm; standard cell library; Standards; two-term dot product unit; Vectors

entry:
@InProceedings{Sohn:2013:IAF,
  author =       "Jongwook Sohn and Earl E. {Swartzlander, Jr.}",
  title =        "Improved Architectures for a Floating-Point Fused Dot
                 Product Unit",
  crossref =     "IEEE:2013:PIS",
  pages =        "41--48",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.26",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; alignment scheme; ARITH-21; complex
                 multiplication; Computer architecture; data flow
                 analysis; DCT butterfly operations; Digital signal
                 processing; digital signal processing; Digital signal
                 processing (DSP); discrete cosine transform butterfly
                 operations; DSP applications; dual-path algorithm;
                 early normalization; fast Fourier transform; FFT;
                 floating point arithmetic; floating-point arithmetic;
                 floating-point fused operations; floating-point fused
                 two-term dot product unit; four-input leading zero
                 anticipation; high-speed computer arithmetic;
                 libraries; nonpipelined dual-path design; pipeline
                 processing; Pipeline processing; pipelining; Power
                 demand; signal processing; size 45 nm; standard cell
                 library; Standards; two-term dot product unit;
                 Vectors",
}


bibtype: inproceedings
filename: fparith.bib
label: Srinivasan:2013:SPF
title: Split-Path Fused Floating Point Multiply Accumulate (FPMAC)
crossref: IEEE:2013:PIS
pages: 17--24
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.32
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawtitle: Split-Path Fused Floating Point Multiply Accumulate ({FPMAC})
author:
Suresh Srinivasan and Ketan Bhudiya and Rajaraman Ramanarayanan and P. Sahit Babu and Tiju Jacob and Sanu K. Mathew and Ram Krishnamurthy and Vasantha Errgauntla

keywords:
Adders; ARITH-21; AVX ISA; contemporary client microprocessor; critical path computation; Delays; Double precision floating point multiply-accumulate; exponent difference; floating point arithmetic; FPMAC design; Hardware; IBM Power6; IEEE Rounding; IEEE standard; IEEE standards; instruction set architecture; instruction sets; ISA support; logic design; Logic gates; microprocessor area; microprocessor chips; microprocessor frequency; microprocessor power; Microprocessors; near path critical logic; Normalization; Program processors; server processor; split-path fused floating point multiply accumulate; SSE ISA; timing design; Wallace tree

rawauthor:
Suresh Srinivasan and Ketan Bhudiya and Rajaraman Ramanarayanan and P. Sahit Babu and Tiju Jacob and Sanu K. Mathew and Ram Krishnamurthy and Vasantha Errgauntla

entry:
@InProceedings{Srinivasan:2013:SPF,
  author =       "Suresh Srinivasan and Ketan Bhudiya and Rajaraman
                 Ramanarayanan and P. Sahit Babu and Tiju Jacob and Sanu
                 K. Mathew and Ram Krishnamurthy and Vasantha
                 Errgauntla",
  title =        "Split-Path Fused Floating Point Multiply Accumulate
                 ({FPMAC})",
  crossref =     "IEEE:2013:PIS",
  pages =        "17--24",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.32",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Adders; ARITH-21; AVX ISA; contemporary client
                 microprocessor; critical path computation; Delays;
                 Double precision floating point multiply-accumulate;
                 exponent difference; floating point arithmetic; FPMAC
                 design; Hardware; IBM Power6; IEEE Rounding; IEEE
                 standard; IEEE standards; instruction set architecture;
                 instruction sets; ISA support; logic design; Logic
                 gates; microprocessor area; microprocessor chips;
                 microprocessor frequency; microprocessor power;
                 Microprocessors; near path critical logic;
                 Normalization; Program processors; server processor;
                 split-path fused floating point multiply accumulate;
                 SSE ISA; timing design; Wallace tree",
}


bibtype: inproceedings
filename: fparith.bib
label: Sullivan:2013:TLA
author: Michael B. Sullivan and Earl E. Swartzlander, Jr.
title: Truncated Logarithmic Approximation
crossref: IEEE:2013:PIS
pages: 191--198
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.34
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Michael B. Sullivan and Earl E. {Swartzlander, Jr.}
rawtitle: Truncated Logarithmic Approximation
keywords:
Algorithm design and analysis; Analytical models; anti-logarithm generation; Approximation algorithms; approximation theory; ARITH-21; binary logarithm; computer arithmetic; Delays; Linear approximation; linear approximation algorithm; logarithm generation; logarithmic approximation; Logic gates; Mitchell approximation algorithm; mixed precision; resource utilization; Truncated approximate binary logarithms; truncated approximate logarithm

entry:
@InProceedings{Sullivan:2013:TLA,
  author =       "Michael B. Sullivan and Earl E. {Swartzlander, Jr.}",
  title =        "Truncated Logarithmic Approximation",
  crossref =     "IEEE:2013:PIS",
  pages =        "191--198",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.34",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "Algorithm design and analysis; Analytical models;
                 anti-logarithm generation; Approximation algorithms;
                 approximation theory; ARITH-21; binary logarithm;
                 computer arithmetic; Delays; Linear approximation;
                 linear approximation algorithm; logarithm generation;
                 logarithmic approximation; Logic gates; Mitchell
                 approximation algorithm; mixed precision; resource
                 utilization; Truncated approximate binary logarithms;
                 truncated approximate logarithm",
}


bibtype: article
filename: fparith.bib
label: Vazquez:2013:IAA
author: Alvaro Vazquez and Javier D. Bruguera
title: Iterative Algorithm and Architecture for Exponential, Logarithm, Powering, and Root Extraction
journal: j-IEEE-TRANS-COMPUT
volume: 62
number: 9
pages: 1721--1731
month: sep
monthnumber: 9
year: 2013
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2012.247
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Fri Nov 15 08:54:34 2013
bibtimestamp: 2013.11.15 08:54:34 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Alvaro Vazquez and Javier D. Bruguera
rawtitle: Iterative Algorithm and Architecture for Exponential, Logarithm, Powering, and Root Extraction
entry:
@Article{Vazquez:2013:IAA,
  author =       "Alvaro Vazquez and Javier D. Bruguera",
  title =        "Iterative Algorithm and Architecture for Exponential,
                 Logarithm, Powering, and Root Extraction",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "62",
  number =       "9",
  pages =        "1721--1731",
  month =        sep,
  year =         "2013",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2012.247",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Fri Nov 15 08:54:34 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: book
filename: fparith.bib
label: Warren:2013:HD
author: Henry S. Warren
title: Hacker's Delight
publisher: pub-AW
address: pub-AW:adr
edition: Second
pages: xvi + 494
year: 2013
ISBN: 0-321-84268-5 (hardcover) OR 0321842685 (hardcover)
ISBN13: 978-0-321-84268-8 (hardcover) OR 9780321842688 (hardcover)
LCCN: QA76.6 .W375 2013
bibdate: Mon Sep 23 11:53:48 MDT 2013
bibtimestamp: 2013.09.23 11:53:48 MDT
URL: http://www.pearsonhighered.com/educator/product/Hackers-Delight/9780321842688.page
subject: Computer programming
acknowledgement: ack-nhfb
rawauthor: Henry S. Warren
rawtitle: Hacker's Delight
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/master.bib; https://www.math.utah.edu/pub/tex/bib/mathcw.bib; z3950.loc.gov:7090/Voyager

TOC:
Foreword / xiii Preface / xv Chapter 1: Introduction / 1 1-1 Notation / 1 1-2 Instruction Set and Execution Time Model / 5 Chapter 2: Basics / 11 2-1 Manipulating Rightmost Bits / 11 2-2 Addition Combined with Logical Operations / 16 2-3 Inequalities among Logical and Arithmetic Expressions / 17 2-4 Absolute Value Function / 18 2-5 Average of Two Integers / 19 2-6 Sign Extension / 19 2-7 Shift Right Signed from Unsigned / 20 2-8 Sign Function / 20 2-9 Three-Valued Compare Function / 21 2-10 Transfer of Sign Function / 22 2-11 Decoding a Zero Means 2**n Field / 22 2-12 Comparison Predicates / 23 2-13 Overflow Detection / 28 2-14 Condition Code Result of Add, Subtract, and Multiply / 36 2-15 Rotate Shifts / 37 2-16 Double-Length Add/Subtract / 38 2-17 Double-Length Shifts / 39 2-18 Multibyte Add, Subtract, AbsoluteValue / 40 2-19 Doz, Max, Min / 41 2-20 Exchanging Registers / 45 2-21 Alternating among Two or More Values / 48 2-22 A Boolean Decomposition Formula / 51 2-23 Implementing Instructions for all 16 Binary Boolean Operations / 53 Chapter 3: Power-of-2 Boundaries / 59 3-1 Rounding Up/Down to a Multiple of a Known Power of 2 / 59 3-2 Rounding Up/Down to the Next Power of 2 / 60 3-3 Detecting a Power-of-2 Boundary Crossing / 63 Chapter 4: Arithmetic Bounds / 67 4-1 Checking Bounds of Integers / 67 4-2 Propagating Bounds through Adds and Subtracts / 70 4-3 Propagating Bounds through Logical Operations / 73 Chapter 5: Counting Bits / 81 5-1 Counting 1-Bits / 81 5-2 Parity / 96 5-3 Counting Leading 0's / 99 5-4 Counting Trailing 0's / 107 Chapter 6: Searching Words / 117 6-1 Find First 0-Byte / 117 6-2 Find First String of 1-Bits of a Given Length / 123 6-3 Find Longest String of 1-Bits / 125 6-4 Find Shortest String of 1-Bits / 126 Chapter 7: Rearranging Bits And Bytes / 129 7-1 Reversing Bits and Bytes / 129 7-2 Shuffling Bits / 139 7-3 Transposing a Bit Matrix / 141 7-4 Compress, or GeneralizedExtract / 150 7-5 Expand, or GeneralizedInsert / 156 7-6 Hardware Algorithms for Compress and Expand / 157 7-7 General Permutations, Sheep and Goats Operation / 161 7-8 Rearrangements and Index Transformations / 165 7-9 An LRU Algorithm / 166 Chapter 8: Multiplication / 171 8-1 Multiword Multiplication / 171 8-2 High-Order Half of 64-Bit Product / 173 8-3 High-Order Product Signed from/to Unsigned / 174 8-4 Multiplication by Constants / 175 Chapter 9: Integer Division / 181 9-1 Preliminaries / 181 9-2 Multiword Division / 184 9-3 Unsigned Short Division from Signed Division / 189 9-4 Unsigned Long Division / 192 9-5 Doubleword Division from Long Division / 197 Chapter 10: Integer Division by Constants / 205 10-1 Signed Division by a Known Power of 2 / 205 10-2 Signed Remainder from Division by a Known Power of 2 / 206 10-3 Signed Division and Remainder by Non-Powers of 2 / 207 10-4 Signed Division by Divisors 2 / 210 10-5 Signed Division by Divisors 2 / 218 10-6 Incorporation into a Compiler / 220 10-7 Miscellaneous Topics / 223 10-8 Unsigned Division / 227 10-9 Unsigned Division by Divisors 1 / 230 10-10 Incorporation into a Compiler (Unsigned) / 232 10-11 Miscellaneous Topics (Unsigned) / 234 10-12 Applicability to Modulus and Floor Division / 237 10-13 Similar Methods / 237 10-14 Sample Magic Numbers / 238 10-15 Simple Code in Python / 240 10-16 Exact Division by Constants / 240 10-17 Test for Zero Remainder after Division by a Constant / 248 10-18 Methods Not Using Multiply High / 251 10-19 Remainder by Summing Digits / 262 10-20 Remainder by Multiplication and Shifting Right / 268 10-21 Converting to Exact Division / 274 10-22 A Timing Test / 276 10-23 A Circuit for Dividing by 3 / 276 Chapter 11: Some Elementary Functions / 279 11-1 Integer Square Root / 279 11-2 Integer Cube Root / 287 11-3 Integer Exponentiation / 288 11-4 Integer Logarithm / 291 Chapter 12: Unusual Bases For Number Systems / 299 12-1 Base 2 / 299 12-2 Base 1 + i / 306 12-3 Other Bases / 308 12-4 What Is the Most Efficient Base? / 309 Chapter 13: Gray Code / 311 13-1 Gray Code / 311 13-2 Incrementing a Gray-Coded Integer / 313 13-3 Negabinary Gray Code / 315 13-4 Brief History and Applications / 315 Chapter 14: Cyclic Redundancy Check / 319 14-1 Introduction / 319 14-2 Theory / 320 14-3 Practice / 323 Chapter 15: Error-Correcting Codes / 331 15-1 Introduction / 331 15-2 The Hamming Code / 332 15-3 Software for SEC-DED on 32 Information Bits / 337 15-4 Error Correction Considered More Generally / 342 Chapter 16: Hilbert's Curve / 355 16-1 A Recursive Algorithm for Generating the Hilbert Curve / 356 16-2 Coordinates from Distance along the Hilbert Curve / 358 16-3 Distance from Coordinates on the Hilbert Curve / 366 16-4 Incrementing the Coordinates on the Hilbert Curve / 368 16-5 Non-Recursive Generating Algorithms / 371 16-6 Other Space-Filling Curves / 371 16-7 Applications / 372 Chapter 17: Floating-Point / 375 17-1 IEEE Format / 375 17-2 Floating-Point To/From Integer Conversions / 377 17-3 Comparing Floating-Point Numbers Using Integer Operations / 381 17-4 An Approximate Reciprocal Square Root Routine / 383 17-5 The Distribution of Leading Digits / 385 17-6 Table of Miscellaneous Values / 387 Chapter 18: Formulas for Primes / 391 18-1 Introduction / 391 18-2 Willans's Formulas / 393 18-3 Wormell's Formula / 397 18-4 Formulas for Other Difficult Functions / 398 Answers to Exercises: / 405 Appendix A: Arithmetic Tables for a 4-Bit Machine / 453 Appendix B: Newton's Method / 457 Appendix C: A Gallery of Graphs of Discrete Functions / 459 C-1 Plots of Logical Operations on Integers / 459 C-2 Plots of Addition, Subtraction, and Multiplication / 461 C-3 Plots of Functions Involving Division / 463 C-4 Plots of the Compress, SAG, and Rotate Left Functions / 464 C-5 2D Plots of Some Unary Functions / 466 Bibliography / 471 Index / 481

rawTOC:
Foreword / xiii \\ Preface / xv \\ Chapter 1: Introduction / 1 \\ 1-1 Notation / 1 \\ 1-2 Instruction Set and Execution Time Model / 5 \\ Chapter 2: Basics / 11 \\ 2-1 Manipulating Rightmost Bits / 11 \\ 2-2 Addition Combined with Logical Operations / 16 \\ 2-3 Inequalities among Logical and Arithmetic Expressions / 17 \\ 2-4 Absolute Value Function / 18 \\ 2-5 Average of Two Integers / 19 \\ 2-6 Sign Extension / 19 \\ 2-7 Shift Right Signed from Unsigned / 20 \\ 2-8 Sign Function / 20 \\ 2-9 Three-Valued Compare Function / 21 \\ 2-10 Transfer of Sign Function / 22 \\ 2-11 Decoding a Zero Means 2**n Field / 22 \\ 2-12 Comparison Predicates / 23 \\ 2-13 Overflow Detection / 28 \\ 2-14 Condition Code Result of Add, Subtract, and Multiply / 36 \\ 2-15 Rotate Shifts / 37 \\ 2-16 Double-Length Add/Subtract / 38 \\ 2-17 Double-Length Shifts / 39 \\ 2-18 Multibyte Add, Subtract, AbsoluteValue / 40 \\ 2-19 Doz, Max, Min / 41 \\ 2-20 Exchanging Registers / 45 \\ 2-21 Alternating among Two or More Values / 48 \\ 2-22 A Boolean Decomposition Formula / 51 \\ 2-23 Implementing Instructions for all 16 Binary Boolean Operations / 53 \\ Chapter 3: Power-of-2 Boundaries / 59 \\ 3-1 Rounding Up/Down to a Multiple of a Known Power of 2 / 59 \\ 3-2 Rounding Up/Down to the Next Power of 2 / 60 \\ 3-3 Detecting a Power-of-2 Boundary Crossing / 63 \\ Chapter 4: Arithmetic Bounds / 67 \\ 4-1 Checking Bounds of Integers / 67 \\ 4-2 Propagating Bounds through Adds and Subtracts / 70 \\ 4-3 Propagating Bounds through Logical Operations / 73 \\ Chapter 5: Counting Bits / 81 \\ 5-1 Counting 1-Bits / 81 \\ 5-2 Parity / 96 \\ 5-3 Counting Leading 0's / 99 \\ 5-4 Counting Trailing 0's / 107 \\ Chapter 6: Searching Words / 117 \\ 6-1 Find First 0-Byte / 117 \\ 6-2 Find First String of 1-Bits of a Given Length / 123 \\ 6-3 Find Longest String of 1-Bits / 125 \\ 6-4 Find Shortest String of 1-Bits / 126 \\ Chapter 7: Rearranging Bits And Bytes / 129 \\ 7-1 Reversing Bits and Bytes / 129 \\ 7-2 Shuffling Bits / 139 \\ 7-3 Transposing a Bit Matrix / 141 \\ 7-4 Compress, or GeneralizedExtract / 150 \\ 7-5 Expand, or GeneralizedInsert / 156 \\ 7-6 Hardware Algorithms for Compress and Expand / 157 \\ 7-7 General Permutations, Sheep and Goats Operation / 161 \\ 7-8 Rearrangements and Index Transformations / 165 \\ 7-9 An LRU Algorithm / 166 \\ Chapter 8: Multiplication / 171 \\ 8-1 Multiword Multiplication / 171 \\ 8-2 High-Order Half of 64-Bit Product / 173 \\ 8-3 High-Order Product Signed from/to Unsigned / 174 \\ 8-4 Multiplication by Constants / 175 \\ Chapter 9: Integer Division / 181 \\ 9-1 Preliminaries / 181 \\ 9-2 Multiword Division / 184 \\ 9-3 Unsigned Short Division from Signed Division / 189 \\ 9-4 Unsigned Long Division / 192 \\ 9-5 Doubleword Division from Long Division / 197 \\ Chapter 10: Integer Division by Constants / 205 \\ 10-1 Signed Division by a Known Power of 2 / 205 \\ 10-2 Signed Remainder from Division by a Known Power of 2 / 206 \\ 10-3 Signed Division and Remainder by Non-Powers of 2 / 207 \\ 10-4 Signed Division by Divisors 2 / 210 \\ 10-5 Signed Division by Divisors 2 / 218 \\ 10-6 Incorporation into a Compiler / 220 \\ 10-7 Miscellaneous Topics / 223 \\ 10-8 Unsigned Division / 227 \\ 10-9 Unsigned Division by Divisors 1 / 230 \\ 10-10 Incorporation into a Compiler (Unsigned) / 232 \\ 10-11 Miscellaneous Topics (Unsigned) / 234 \\ 10-12 Applicability to Modulus and Floor Division / 237 \\ 10-13 Similar Methods / 237 \\ 10-14 Sample Magic Numbers / 238 \\ 10-15 Simple Code in Python / 240 \\ 10-16 Exact Division by Constants / 240 \\ 10-17 Test for Zero Remainder after Division by a Constant / 248 \\ 10-18 Methods Not Using Multiply High / 251 \\ 10-19 Remainder by Summing Digits / 262 \\ 10-20 Remainder by Multiplication and Shifting Right / 268 \\ 10-21 Converting to Exact Division / 274 \\ 10-22 A Timing Test / 276 \\ 10-23 A Circuit for Dividing by 3 / 276 \\ Chapter 11: Some Elementary Functions / 279 \\ 11-1 Integer Square Root / 279 \\ 11-2 Integer Cube Root / 287 \\ 11-3 Integer Exponentiation / 288 \\ 11-4 Integer Logarithm / 291 \\ Chapter 12: Unusual Bases For Number Systems / 299 \\ 12-1 Base 2 / 299 \\ 12-2 Base 1 + i / 306 \\ 12-3 Other Bases / 308 \\ 12-4 What Is the Most Efficient Base? / 309 \\ Chapter 13: Gray Code / 311 \\ 13-1 Gray Code / 311 \\ 13-2 Incrementing a Gray-Coded Integer / 313 \\ 13-3 Negabinary Gray Code / 315 \\ 13-4 Brief History and Applications / 315 \\ Chapter 14: Cyclic Redundancy Check / 319 \\ 14-1 Introduction / 319 \\ 14-2 Theory / 320 \\ 14-3 Practice / 323 \\ Chapter 15: Error-Correcting Codes / 331 \\ 15-1 Introduction / 331 \\ 15-2 The Hamming Code / 332 \\ 15-3 Software for SEC-DED on 32 Information Bits / 337 \\ 15-4 Error Correction Considered More Generally / 342 \\ Chapter 16: Hilbert's Curve / 355 \\ 16-1 A Recursive Algorithm for Generating the Hilbert Curve / 356 \\ 16-2 Coordinates from Distance along the Hilbert Curve / 358 \\ 16-3 Distance from Coordinates on the Hilbert Curve / 366 \\ 16-4 Incrementing the Coordinates on the Hilbert Curve / 368 \\ 16-5 Non-Recursive Generating Algorithms / 371 \\ 16-6 Other Space-Filling Curves / 371 \\ 16-7 Applications / 372 \\ Chapter 17: Floating-Point / 375 \\ 17-1 IEEE Format / 375 \\ 17-2 Floating-Point To/From Integer Conversions / 377 \\ 17-3 Comparing Floating-Point Numbers Using Integer Operations / 381 \\ 17-4 An Approximate Reciprocal Square Root Routine / 383 \\ 17-5 The Distribution of Leading Digits / 385 \\ 17-6 Table of Miscellaneous Values / 387 \\ Chapter 18: Formulas for Primes / 391 \\ 18-1 Introduction / 391 \\ 18-2 Willans's Formulas / 393 \\ 18-3 Wormell's Formula / 397 \\ 18-4 Formulas for Other Difficult Functions / 398 \\ Answers to Exercises: / 405 \\ Appendix A: Arithmetic Tables for a 4-Bit Machine / 453 \\ Appendix B: Newton's Method / 457 \\ Appendix C: A Gallery of Graphs of Discrete Functions / 459 \\ C-1 Plots of Logical Operations on Integers / 459 \\ C-2 Plots of Addition, Subtraction, and Multiplication / 461 \\ C-3 Plots of Functions Involving Division / 463 \\ C-4 Plots of the Compress, SAG, and Rotate Left Functions / 464 \\ C-5 2D Plots of Some Unary Functions / 466 \\ Bibliography / 471 \\ Index / 481

entry:
@Book{Warren:2013:HD,
  author =       "Henry S. Warren",
  title =        "Hacker's Delight",
  publisher =    pub-AW,
  address =      pub-AW:adr,
  edition =      "Second",
  pages =        "xvi + 494",
  year =         "2013",
  ISBN =         "0-321-84268-5 (hardcover)",
  ISBN-13 =      "978-0-321-84268-8 (hardcover)",
  LCCN =         "QA76.6 .W375 2013",
  bibdate =      "Mon Sep 23 11:53:48 MDT 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/master.bib;
                 https://www.math.utah.edu/pub/tex/bib/mathcw.bib;
                 z3950.loc.gov:7090/Voyager",
  URL =          "http://www.pearsonhighered.com/educator/product/Hackers-Delight/9780321842688.page",
  acknowledgement = ack-nhfb,
  subject =      "Computer programming",
  tableofcontents = "Foreword / xiii \\
                 Preface / xv \\
                 Chapter 1: Introduction / 1 \\
                 1-1 Notation / 1 \\
                 1-2 Instruction Set and Execution Time Model / 5 \\
                 Chapter 2: Basics / 11 \\
                 2-1 Manipulating Rightmost Bits / 11 \\
                 2-2 Addition Combined with Logical Operations / 16 \\
                 2-3 Inequalities among Logical and Arithmetic
                 Expressions / 17 \\
                 2-4 Absolute Value Function / 18 \\
                 2-5 Average of Two Integers / 19 \\
                 2-6 Sign Extension / 19 \\
                 2-7 Shift Right Signed from Unsigned / 20 \\
                 2-8 Sign Function / 20 \\
                 2-9 Three-Valued Compare Function / 21 \\
                 2-10 Transfer of Sign Function / 22 \\
                 2-11 Decoding a Zero Means 2**n Field / 22 \\
                 2-12 Comparison Predicates / 23 \\
                 2-13 Overflow Detection / 28 \\
                 2-14 Condition Code Result of Add, Subtract, and
                 Multiply / 36 \\
                 2-15 Rotate Shifts / 37 \\
                 2-16 Double-Length Add/Subtract / 38 \\
                 2-17 Double-Length Shifts / 39 \\
                 2-18 Multibyte Add, Subtract, AbsoluteValue / 40 \\
                 2-19 Doz, Max, Min / 41 \\
                 2-20 Exchanging Registers / 45 \\
                 2-21 Alternating among Two or More Values / 48 \\
                 2-22 A Boolean Decomposition Formula / 51 \\
                 2-23 Implementing Instructions for all 16 Binary
                 Boolean Operations / 53 \\
                 Chapter 3: Power-of-2 Boundaries / 59 \\
                 3-1 Rounding Up/Down to a Multiple of a Known Power of
                 2 / 59 \\
                 3-2 Rounding Up/Down to the Next Power of 2 / 60 \\
                 3-3 Detecting a Power-of-2 Boundary Crossing / 63 \\
                 Chapter 4: Arithmetic Bounds / 67 \\
                 4-1 Checking Bounds of Integers / 67 \\
                 4-2 Propagating Bounds through Adds and Subtracts / 70
                 \\
                 4-3 Propagating Bounds through Logical Operations / 73
                 \\
                 Chapter 5: Counting Bits / 81 \\
                 5-1 Counting 1-Bits / 81 \\
                 5-2 Parity / 96 \\
                 5-3 Counting Leading 0's / 99 \\
                 5-4 Counting Trailing 0's / 107 \\
                 Chapter 6: Searching Words / 117 \\
                 6-1 Find First 0-Byte / 117 \\
                 6-2 Find First String of 1-Bits of a Given Length / 123
                 \\
                 6-3 Find Longest String of 1-Bits / 125 \\
                 6-4 Find Shortest String of 1-Bits / 126 \\
                 Chapter 7: Rearranging Bits And Bytes / 129 \\
                 7-1 Reversing Bits and Bytes / 129 \\
                 7-2 Shuffling Bits / 139 \\
                 7-3 Transposing a Bit Matrix / 141 \\
                 7-4 Compress, or GeneralizedExtract / 150 \\
                 7-5 Expand, or GeneralizedInsert / 156 \\
                 7-6 Hardware Algorithms for Compress and Expand / 157
                 \\
                 7-7 General Permutations, Sheep and Goats Operation /
                 161 \\
                 7-8 Rearrangements and Index Transformations / 165 \\
                 7-9 An LRU Algorithm / 166 \\
                 Chapter 8: Multiplication / 171 \\
                 8-1 Multiword Multiplication / 171 \\
                 8-2 High-Order Half of 64-Bit Product / 173 \\
                 8-3 High-Order Product Signed from/to Unsigned / 174
                 \\
                 8-4 Multiplication by Constants / 175 \\
                 Chapter 9: Integer Division / 181 \\
                 9-1 Preliminaries / 181 \\
                 9-2 Multiword Division / 184 \\
                 9-3 Unsigned Short Division from Signed Division / 189
                 \\
                 9-4 Unsigned Long Division / 192 \\
                 9-5 Doubleword Division from Long Division / 197 \\
                 Chapter 10: Integer Division by Constants / 205 \\
                 10-1 Signed Division by a Known Power of 2 / 205 \\
                 10-2 Signed Remainder from Division by a Known Power of
                 2 / 206 \\
                 10-3 Signed Division and Remainder by Non-Powers of 2 /
                 207 \\
                 10-4 Signed Division by Divisors 2 / 210 \\
                 10-5 Signed Division by Divisors 2 / 218 \\
                 10-6 Incorporation into a Compiler / 220 \\
                 10-7 Miscellaneous Topics / 223 \\
                 10-8 Unsigned Division / 227 \\
                 10-9 Unsigned Division by Divisors 1 / 230 \\
                 10-10 Incorporation into a Compiler (Unsigned) / 232
                 \\
                 10-11 Miscellaneous Topics (Unsigned) / 234 \\
                 10-12 Applicability to Modulus and Floor Division / 237
                 \\
                 10-13 Similar Methods / 237 \\
                 10-14 Sample Magic Numbers / 238 \\
                 10-15 Simple Code in Python / 240 \\
                 10-16 Exact Division by Constants / 240 \\
                 10-17 Test for Zero Remainder after Division by a
                 Constant / 248 \\
                 10-18 Methods Not Using Multiply High / 251 \\
                 10-19 Remainder by Summing Digits / 262 \\
                 10-20 Remainder by Multiplication and Shifting Right /
                 268 \\
                 10-21 Converting to Exact Division / 274 \\
                 10-22 A Timing Test / 276 \\
                 10-23 A Circuit for Dividing by 3 / 276 \\
                 Chapter 11: Some Elementary Functions / 279 \\
                 11-1 Integer Square Root / 279 \\
                 11-2 Integer Cube Root / 287 \\
                 11-3 Integer Exponentiation / 288 \\
                 11-4 Integer Logarithm / 291 \\
                 Chapter 12: Unusual Bases For Number Systems / 299 \\
                 12-1 Base 2 / 299 \\
                 12-2 Base 1 + i / 306 \\
                 12-3 Other Bases / 308 \\
                 12-4 What Is the Most Efficient Base? / 309 \\
                 Chapter 13: Gray Code / 311 \\
                 13-1 Gray Code / 311 \\
                 13-2 Incrementing a Gray-Coded Integer / 313 \\
                 13-3 Negabinary Gray Code / 315 \\
                 13-4 Brief History and Applications / 315 \\
                 Chapter 14: Cyclic Redundancy Check / 319 \\
                 14-1 Introduction / 319 \\
                 14-2 Theory / 320 \\
                 14-3 Practice / 323 \\
                 Chapter 15: Error-Correcting Codes / 331 \\
                 15-1 Introduction / 331 \\
                 15-2 The Hamming Code / 332 \\
                 15-3 Software for SEC-DED on 32 Information Bits / 337
                 \\
                 15-4 Error Correction Considered More Generally / 342
                 \\
                 Chapter 16: Hilbert's Curve / 355 \\
                 16-1 A Recursive Algorithm for Generating the Hilbert
                 Curve / 356 \\
                 16-2 Coordinates from Distance along the Hilbert Curve
                 / 358 \\
                 16-3 Distance from Coordinates on the Hilbert Curve /
                 366 \\
                 16-4 Incrementing the Coordinates on the Hilbert Curve
                 / 368 \\
                 16-5 Non-Recursive Generating Algorithms / 371 \\
                 16-6 Other Space-Filling Curves / 371 \\
                 16-7 Applications / 372 \\
                 Chapter 17: Floating-Point / 375 \\
                 17-1 IEEE Format / 375 \\
                 17-2 Floating-Point To/From Integer Conversions / 377
                 \\
                 17-3 Comparing Floating-Point Numbers Using Integer
                 Operations / 381 \\
                 17-4 An Approximate Reciprocal Square Root Routine /
                 383 \\
                 17-5 The Distribution of Leading Digits / 385 \\
                 17-6 Table of Miscellaneous Values / 387 \\
                 Chapter 18: Formulas for Primes / 391 \\
                 18-1 Introduction / 391 \\
                 18-2 Willans's Formulas / 393 \\
                 18-3 Wormell's Formula / 397 \\
                 18-4 Formulas for Other Difficult Functions / 398 \\
                 Answers to Exercises: / 405 \\
                 Appendix A: Arithmetic Tables for a 4-Bit Machine / 453
                 \\
                 Appendix B: Newton's Method / 457 \\
                 Appendix C: A Gallery of Graphs of Discrete Functions /
                 459 \\
                 C-1 Plots of Logical Operations on Integers / 459 \\
                 C-2 Plots of Addition, Subtraction, and Multiplication
                 / 461 \\
                 C-3 Plots of Functions Involving Division / 463 \\
                 C-4 Plots of the Compress, SAG, and Rotate Left
                 Functions / 464 \\
                 C-5 2D Plots of Some Unary Functions / 466 \\
                 Bibliography / 471 \\
                 Index / 481",
}


bibtype: article
filename: fparith.bib
label: Wiebe:2013:FPR
author: Nathan Wiebe and Vadym Kliuchnikov
title: Floating Point Representations in Quantum Circuit Synthesis
journal: arXiv.org
pages: ??--??
day: 23
month: may
monthnumber: 5
year: 2013
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1305.5528
subject: Quantum Physics (quant-ph)
acknowledgement: ack-nhfb
rawauthor: Nathan Wiebe and Vadym Kliuchnikov
rawtitle: Floating Point Representations in Quantum Circuit Synthesis
abstract:
We provide a non-deterministic quantum protocol that approximates the single qubit rotations $ R_x(2 a^2 b^2) $ using $ R_x(2 a) $ and $ R_x(2 b) $ and a constant number of Clifford and T operations. We then use this method to construct a ``floating point'' implementation of a small rotation wherein we use the aforementioned method to construct the exponent part of the rotation and also to combine it with a mantissa. This causes the cost of the synthesis to depend more strongly on the relative (rather than absolute) precision required. We analyze the mean and variance of the T-count required to use our techniques and provide new lower bounds for the T-count for ancilla free synthesis of small single-qubit axial rotations. We further show that our techniques can use ancillas to beat these lower bounds with high probability. We also discuss the T-depth of our method and see that the vast majority of the cost of the resultant circuits can be shifted to parallel computation paths.

rawabstract:
We provide a non-deterministic quantum protocol that approximates the single qubit rotations $ R_x(2 a^2 b^2) $ using $ R_x(2 a) $ and $ R_x(2 b) $ and a constant number of Clifford and T operations. We then use this method to construct a ``floating point'' implementation of a small rotation wherein we use the aforementioned method to construct the exponent part of the rotation and also to combine it with a mantissa. This causes the cost of the synthesis to depend more strongly on the relative (rather than absolute) precision required. We analyze the mean and variance of the T-count required to use our techniques and provide new lower bounds for the T-count for ancilla free synthesis of small single-qubit axial rotations. We further show that our techniques can use ancillas to beat these lower bounds with high probability. We also discuss the T-depth of our method and see that the vast majority of the cost of the resultant circuits can be shifted to parallel computation paths.

entry:
@Article{Wiebe:2013:FPR,
  author =       "Nathan Wiebe and Vadym Kliuchnikov",
  title =        "Floating Point Representations in Quantum Circuit
                 Synthesis",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "23",
  month =        may,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1305.5528",
  abstract =     "We provide a non-deterministic quantum protocol that
                 approximates the single qubit rotations $ R_x(2 a^2
                 b^2) $ using $ R_x(2 a) $ and $ R_x(2 b) $ and a
                 constant number of Clifford and T operations. We then
                 use this method to construct a ``floating point''
                 implementation of a small rotation wherein we use the
                 aforementioned method to construct the exponent part of
                 the rotation and also to combine it with a mantissa.
                 This causes the cost of the synthesis to depend more
                 strongly on the relative (rather than absolute)
                 precision required. We analyze the mean and variance of
                 the T-count required to use our techniques and provide
                 new lower bounds for the T-count for ancilla free
                 synthesis of small single-qubit axial rotations. We
                 further show that our techniques can use ancillas to
                 beat these lower bounds with high probability. We also
                 discuss the T-depth of our method and see that the vast
                 majority of the cost of the resultant circuits can be
                 shifted to parallel computation paths.",
  acknowledgement = ack-nhfb,
  subject =      "Quantum Physics (quant-ph)",
}


bibtype: article
filename: fparith.bib
label: Yabuki:2013:DPC
author: Michiro Yabuki and Takashi Tsuchiya
journal: arXiv.org
pages: 1--10
day: 14
month: may
monthnumber: 5
year: 2013
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1305.3128
subject: Chaotic Dynamics (nlin.CD)
acknowledgement: ack-nhfb
rawauthor: Michiro Yabuki and Takashi Tsuchiya
title:
Double Precision Computation of the Logistic Map Depends on Computational Modes of the Floating-point Processing Unit

abstract:
Today's most popular CPU can operate in two different computational modes for double precision computations. This fact is not very widely recognized among scientific computer users. The present paper reports the differences the modes bring about using the most thoroughly studied system in chaos theory, the logistic map. Distinct virtual periods due to finite precision come about depending on the computational modes for the parameter value corresponding to fully developed chaos. For other chaotic regime various virtual periods emerge depending on the computational modes and the mathematical expressions of the map. Differences in the bifurcation diagrams due to the modes and the expressions are surveyed exhaustively. A quantity to measure those differences is defined and calculated.

rawabstract:
Today's most popular CPU can operate in two different computational modes for double precision computations. This fact is not very widely recognized among scientific computer users. The present paper reports the differences the modes bring about using the most thoroughly studied system in chaos theory, the logistic map. Distinct virtual periods due to finite precision come about depending on the computational modes for the parameter value corresponding to fully developed chaos. For other chaotic regime various virtual periods emerge depending on the computational modes and the mathematical expressions of the map. Differences in the bifurcation diagrams due to the modes and the expressions are surveyed exhaustively. A quantity to measure those differences is defined and calculated.

rawtitle:
Double Precision Computation of the Logistic Map Depends on Computational Modes of the Floating-point Processing Unit

entry:
@Article{Yabuki:2013:DPC,
  author =       "Michiro Yabuki and Takashi Tsuchiya",
  title =        "Double Precision Computation of the Logistic Map
                 Depends on Computational Modes of the Floating-point
                 Processing Unit",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--10",
  day =          "14",
  month =        may,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1305.3128",
  abstract =     "Today's most popular CPU can operate in two different
                 computational modes for double precision computations.
                 This fact is not very widely recognized among
                 scientific computer users. The present paper reports
                 the differences the modes bring about using the most
                 thoroughly studied system in chaos theory, the logistic
                 map. Distinct virtual periods due to finite precision
                 come about depending on the computational modes for the
                 parameter value corresponding to fully developed chaos.
                 For other chaotic regime various virtual periods emerge
                 depending on the computational modes and the
                 mathematical expressions of the map. Differences in the
                 bifurcation diagrams due to the modes and the
                 expressions are surveyed exhaustively. A quantity to
                 measure those differences is defined and calculated.",
  acknowledgement = ack-nhfb,
  subject =      "Chaotic Dynamics (nlin.CD)",
}


bibtype: inproceedings
filename: fparith.bib
label: Yuce:2013:FCT
author: Bilgiday Yuce and H. Fatih Ugurdag and Sezer Goren and Gunham Dundar
title: A Fast Circuit Topology for Finding the Maximum of $N$ $k$-bit Numbers
crossref: IEEE:2013:PIS
pages: 59--66
year: 2013
DOI: https://doi.org/10.1109/ARITH.2013.35
ISSN: 1063-6889 OR 10636889
bibdate: Sat Aug 1 09:38:32 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.08.01 09:38:32 ???
acknowledgement: ack-nhfb
rawauthor: Bilgiday Yuce and H. Fatih Ugurdag and Sezer Goren and Gunham Dundar
rawtitle: A Fast Circuit Topology for Finding the Maximum of {$N$} $k$-bit Numbers
keywords:
AB; area complexity; Area-timing product; ARITH-21; arithmetic operation; array-based maximum finder; Arrays; binary search; Binary trees; Circuit topology; computational complexity; Computer arithmetic; Delays; digital arithmetic; fast circuit topology; iterative methods; k-bit binary numbers; Logic gates; Logic synthesis; Maximum finder; Minimum finder; network topology; program compilers; RTL code generators; standard-cell based iterative synthesis flow; Time complexity; time complexity; Timing optimization; Topology

entry:
@InProceedings{Yuce:2013:FCT,
  author =       "Bilgiday Yuce and H. Fatih Ugurdag and Sezer Goren and
                 Gunham Dundar",
  title =        "A Fast Circuit Topology for Finding the Maximum of
                 {$N$} $k$-bit Numbers",
  crossref =     "IEEE:2013:PIS",
  pages =        "59--66",
  year =         "2013",
  DOI =          "https://doi.org/10.1109/ARITH.2013.35",
  ISSN =         "1063-6889",
  bibdate =      "Sat Aug 1 09:38:32 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  keywords =     "AB; area complexity; Area-timing product; ARITH-21;
                 arithmetic operation; array-based maximum finder;
                 Arrays; binary search; Binary trees; Circuit topology;
                 computational complexity; Computer arithmetic; Delays;
                 digital arithmetic; fast circuit topology; iterative
                 methods; k-bit binary numbers; Logic gates; Logic
                 synthesis; Maximum finder; Minimum finder; network
                 topology; program compilers; RTL code generators;
                 standard-cell based iterative synthesis flow; Time
                 complexity; time complexity; Timing optimization;
                 Topology",
}


bibtype: article
filename: fparith.bib
label: Zhang:2013:BAF
author: Yiwei Zhang and Joseph P. Mcgeehan and Edward M. Regan and Stephen Kelly and Jose Luis Nunez-Yanez
title: Biophysically Accurate Floating Point Neuroprocessors for Reconfigurable Logic
journal: j-IEEE-TRANS-COMPUT
volume: 62
number: 3
pages: 599--608
month: mar
monthnumber: 3
year: 2013
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2011.257
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Tue Apr 30 12:26:22 2013
bibtimestamp: 2013.04.30 12:26:22 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Yiwei Zhang and Joseph P. Mcgeehan and Edward M. Regan and Stephen Kelly and Jose Luis Nunez-Yanez
rawtitle: Biophysically Accurate Floating Point Neuroprocessors for Reconfigurable Logic
entry:
@Article{Zhang:2013:BAF,
  author =       "Yiwei Zhang and Joseph P. Mcgeehan and Edward M. Regan
                 and Stephen Kelly and Jose Luis Nunez-Yanez",
  title =        "Biophysically Accurate Floating Point Neuroprocessors
                 for Reconfigurable Logic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "62",
  number =       "3",
  pages =        "599--608",
  month =        mar,
  year =         "2013",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2011.257",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Tue Apr 30 12:26:22 2013",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Akleylek:2014:AOF
author: S. Akleylek and F. Ozbudak and C. Ozel
title: On the arithmetic operations over finite fields of characteristic three with low complexity
journal: j-J-COMPUT-APPL-MATH
volume: 259 (part B)
pages: 546--554
day: 15
month: mar
monthnumber: 3
year: 2014
CODEN: JCAMDI
ISSN: 0377-0427 (print), 1879-1778 (electronic) OR 03770427 (print), 18791778 (electronic)
ISSNL: 0377-0427 OR 03770427
bibdate: Sat Feb 25 13:34:02 MST 2017
bibtimestamp: 2017.02.25 13:34:02 MST
URL: http://www.sciencedirect.com/science/article/pii/S0377042713004160
fjournal: Journal of Computational and Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/03770427
rawauthor: S. Akleylek and F. {\"O}zbudak and C. {\"O}zel
rawtitle: On the arithmetic operations over finite fields of characteristic three with low complexity
entry:
@Article{Akleylek:2014:AOF,
  author =       "S. Akleylek and F. {\"O}zbudak and C. {\"O}zel",
  title =        "On the arithmetic operations over finite fields of
                 characteristic three with low complexity",
  journal =      j-J-COMPUT-APPL-MATH,
  volume =       "259 (part B)",
  number =       "??",
  pages =        "546--554",
  day =          "15",
  month =        mar,
  year =         "2014",
  CODEN =        "JCAMDI",
  ISSN =         "0377-0427 (print), 1879-1778 (electronic)",
  ISSN-L =       "0377-0427",
  bibdate =      "Sat Feb 25 13:34:02 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jcomputapplmath2010.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0377042713004160",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Computational and Applied Mathematics",
  journal-URL =  "http://www.sciencedirect.com/science/journal/03770427",
}


bibtype: misc
filename: fparith.bib
label: Anonymous:2014:CLL
author: Anonymous
title: CR-Libm --- a library of correctly rounded elementary functions in double-precision
pages: 546--554
year: 2014
bibdate: Sat Oct 31 07:21:21 2015
bibtimestamp: 2015.10.31 07:21:21 ???
URL: http://lipforge.ens-lyon.fr/www/crlibm/
keywords: correct rounding; CR-Libm; floating-point arithmetic; scslib (software carry save library)
acknowledgement: ack-nhfb
howpublished: Web site
rawauthor: Anonymous
rawtitle: {CR-Libm} --- a library of correctly rounded elementary functions in double-precision
abstract:
CRlibm is a free mathematical library (libm) that provides: (1) implementations of the double-precision C99 standard elementary functions; (2) correctly rounded in the four IEEE-754 rounding modes; (3) with a comprehensive proof of both the algorithms used and their implementation; (4) sufficiently efficient in average time, worst-case time, and memory consumption to replace existing libms transparently.

rawabstract:
CRlibm is a free mathematical library (libm) that provides: (1) implementations of the double-precision C99 standard elementary functions; (2) correctly rounded in the four IEEE-754 rounding modes; (3) with a comprehensive proof of both the algorithms used and their implementation; (4) sufficiently efficient in average time, worst-case time, and memory consumption to replace existing libms transparently.

entry:
@Misc{Anonymous:2014:CLL,
  author =       "Anonymous",
  title =        "{CR-Libm} --- a library of correctly rounded
                 elementary functions in double-precision",
  howpublished = "Web site",
  year =         "2014",
  bibdate =      "Sat Oct 31 07:21:21 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/elefunt.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://lipforge.ens-lyon.fr/www/crlibm/",
  abstract =     "CRlibm is a free mathematical library (libm) that
                 provides: (1) implementations of the double-precision
                 C99 standard elementary functions; (2) correctly
                 rounded in the four IEEE-754 rounding modes; (3) with a
                 comprehensive proof of both the algorithms used and
                 their implementation; (4) sufficiently efficient in
                 average time, worst-case time, and memory consumption
                 to replace existing libms transparently.",
  acknowledgement = ack-nhfb,
  keywords =     "correct rounding; CR-Libm; floating-point arithmetic;
                 scslib (software carry save library)",
}


bibtype: article
filename: fparith.bib
label: Area:2014:ACS
author: Ivan Area and Dimitar K. Dimitrov and Eduardo Godoy and Vanessa Paschoa
title: Approximate Calculation of Sums I: Bounds for the Zeros of Gram Polynomials
journal: j-SIAM-J-NUMER-ANAL
volume: 52
number: 4
pages: 1867--1886
year: 2014
CODEN: SJNAAM
DOI: https://doi.org/10.1137/120887278
ISSN: 0036-1429 (print), 1095-7170 (electronic) OR 00361429 (print), 10957170 (electronic)
ISSNL: 0036-1429 OR 00361429
bibdate: Sat Sep 13 09:22:34 MDT 2014
bibtimestamp: 2014.09.13 09:22:34 MDT
fjournal: SIAM Journal on Numerical Analysis
acknowledgement: ack-nhfb
journalURL: http://epubs.siam.org/sinum
onlinedate: January 2014
rawauthor: Iv{\'a}n Area and Dimitar K. Dimitrov and Eduardo Godoy and Vanessa Paschoa
rawtitle: Approximate Calculation of Sums {I}: Bounds for the Zeros of {Gram} Polynomials
bibsource:
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entry:
@Article{Area:2014:ACS,
  author =       "Iv{\'a}n Area and Dimitar K. Dimitrov and Eduardo
                 Godoy and Vanessa Paschoa",
  title =        "Approximate Calculation of Sums {I}: Bounds for the
                 Zeros of {Gram} Polynomials",
  journal =      j-SIAM-J-NUMER-ANAL,
  volume =       "52",
  number =       "4",
  pages =        "1867--1886",
  month =        "????",
  year =         "2014",
  CODEN =        "SJNAAM",
  DOI =          "https://doi.org/10.1137/120887278",
  ISSN =         "0036-1429 (print), 1095-7170 (electronic)",
  ISSN-L =       "0036-1429",
  bibdate =      "Sat Sep 13 09:22:34 MDT 2014",
  bibsource =    "http://epubs.siam.org/toc/sjnaam/52/4;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/siamjnumeranal2010.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "SIAM Journal on Numerical Analysis",
  journal-URL =  "http://epubs.siam.org/sinum",
  onlinedate =   "January 2014",
}


bibtype: inproceedings
filename: fparith.bib
label: Arteaga:2014:DBR
author: A. Arteaga and O. Fuhrer and T. Hoefler
booktitle: Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium
title: Designing bit-reproducible portable high-performance applications
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1235--1244
year: 2014
DOI: https://doi.org/10.1109/IPDPS.2014.127
bibdate: Sat Oct 31 07:13:12 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.10.31 07:13:12 ???
acknowledgement: ack-nhfb
rawauthor: A. Arteaga and O. Fuhrer and T. Hoefler
rawbooktitle: {Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium}
rawtitle: Designing bit-reproducible portable high-performance applications
entry:
@InProceedings{Arteaga:2014:DBR,
  author =       "A. Arteaga and O. Fuhrer and T. Hoefler",
  booktitle =    "{Proceedings of the 2014 IEEE 28th International
                 Parallel and Distributed Processing Symposium}",
  title =        "Designing bit-reproducible portable high-performance
                 applications",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1235--1244",
  year =         "2014",
  DOI =          "https://doi.org/10.1109/IPDPS.2014.127",
  bibdate =      "Sat Oct 31 07:13:12 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Ballard:2014:CLB
author: G. Ballard and E. Carson and J. Demmel and M. Hoemmen and N. Knight and O. Schwartz
title: Communication lower bounds and optimal algorithms for numerical linear algebra
journal: j-ACTA-NUMERICA
volume: 23
pages: 1--155
year: 2014
CODEN: ANUMFU
DOI: https://doi.org/10.1017/S0962492914000038
ISSN: 0962-4929 (print), 1474-0508 (electronic) OR 09624929 (print), 14740508 (electronic)
ISSNL: 0962-4929 OR 09624929
bibdate: Mon May 12 19:01:04 MDT 2014
bibtimestamp: 2014.05.12 19:01:04 MDT
fjournal: Acta Numerica
keywords: accurate floating-point summation
acknowledgement: ack-nhfb
ajournal: Acta Numer.
journalURL: http://journals.cambridge.org/action/displayJournal?jid=ANU
rawauthor: G. Ballard and E. Carson and J. Demmel and M. Hoemmen and N. Knight and O. Schwartz
rawtitle: Communication lower bounds and optimal algorithms for numerical linear algebra
bibsource:
http://journals.cambridge.org/action/displayIssue?jid=ANU&volumeId=23&issueId=00; https://www.math.utah.edu/pub/tex/bib/actanumerica.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib

entry:
@Article{Ballard:2014:CLB,
  author =       "G. Ballard and E. Carson and J. Demmel and M. Hoemmen
                 and N. Knight and O. Schwartz",
  title =        "Communication lower bounds and optimal algorithms for
                 numerical linear algebra",
  journal =      j-ACTA-NUMERICA,
  volume =       "23",
  pages =        "1--155",
  year =         "2014",
  CODEN =        "ANUMFU",
  DOI =          "https://doi.org/10.1017/S0962492914000038",
  ISSN =         "0962-4929 (print), 1474-0508 (electronic)",
  ISSN-L =       "0962-4929",
  bibdate =      "Mon May 12 19:01:04 MDT 2014",
  bibsource =    "http://journals.cambridge.org/action/displayIssue?jid=ANU&volumeId=23&issueId=00;
                 https://www.math.utah.edu/pub/tex/bib/actanumerica.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "Acta Numer.",
  fjournal =     "Acta Numerica",
  journal-URL =  "http://journals.cambridge.org/action/displayJournal?jid=ANU",
  keywords =     "accurate floating-point summation",
}


bibtype: article
filename: fparith.bib
label: BasiriM:2014:EHB
author: Mohamed Asan Basiri M. and Noor Mahammad Sk
title: An Efficient Hardware-Based Higher Radix Floating Point MAC Design
journal: j-TODAES
volume: 20
number: 1
pages: 15:1--15:??
month: nov
monthnumber: 11
year: 2014
CODEN: ATASFO
DOI: https://doi.org/10.1145/2667224
ISSN: 1084-4309 (print), 1557-7309 (electronic) OR 10844309 (print), 15577309 (electronic)
ISSNL: 1084-4309 OR 10844309
bibdate: Wed Nov 19 11:18:40 MST 2014
bibtimestamp: 2014.11.19 11:18:40 MST
fjournal: ACM Transactions on Design Automation of Electronic Systems
acknowledgement: ack-nhfb
articleno: 15
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J776
rawauthor: Mohamed Asan {Basiri M.} and Noor Mahammad Sk
rawtitle: An Efficient Hardware-Based Higher Radix Floating Point {MAC} Design
bibsource:
http://www.acm.org/pubs/contents/journals/todaes/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/todaes.bib

abstract:
This article proposes an effective way of implementing a multiply accumulate circuit (MAC) for high-speed floating point arithmetic operations. The real-world applications related to digital signal processing and the like demand high-performance computation with greater accuracy. In general, digital signals are represented as a sequence of signed/unsigned fixed/floating point numbers. The final result of a MAC operation can be computed by feeding the mantissa of the previous MAC result as one of the partial products to a Wallace tree multiplier or Braun multiplier. Thus, the separate accumulation circuit can be avoided by keeping the circuit depth still within the bounds of the Wallace tree multiplier, namely $ O (log _2 n) $, or Braun multiplier, namely $ O (n) $. In this article, three kinds of floating point MACs are proposed. The experimental results show 48.54% of improvement in worst path delay achieved by the proposed floating point MAC using a radix-2 Wallace structure compared with a conventional floating point MAC without a pipeline using a 45nm technology library. The same proposed design gives 39.92% of improvement in worst path delay without a pipeline using a radix-4 Braun structure as compared with a conventional design. In this article, a radix-32 $ Q_32.32$-format-based floating point MAC is proposed using a Wallace tree/Braun multiplier. Also this article discusses the msb prediction problem and its solution in floating point arithmetic that is not available in modern fused multiply-add designs. The performance results show comparisons between the proposed floating point MAC with various floating point MAC designs for radix-2, -4, -8, and -16. The proposed design has lesser depth than a conventional floating point MAC as well as a lower area requirement than other ways of floating point MAC implementation, both with/without a pipeline.

rawabstract:
This article proposes an effective way of implementing a multiply accumulate circuit (MAC) for high-speed floating point arithmetic operations. The real-world applications related to digital signal processing and the like demand high-performance computation with greater accuracy. In general, digital signals are represented as a sequence of signed/unsigned fixed/floating point numbers. The final result of a MAC operation can be computed by feeding the mantissa of the previous MAC result as one of the partial products to a Wallace tree multiplier or Braun multiplier. Thus, the separate accumulation circuit can be avoided by keeping the circuit depth still within the bounds of the Wallace tree multiplier, namely $ O (\log_2 n) $, or Braun multiplier, namely $ O (n) $. In this article, three kinds of floating point MACs are proposed. The experimental results show 48.54\% of improvement in worst path delay achieved by the proposed floating point MAC using a radix-2 Wallace structure compared with a conventional floating point MAC without a pipeline using a 45nm technology library. The same proposed design gives 39.92\% of improvement in worst path delay without a pipeline using a radix-4 Braun structure as compared with a conventional design. In this article, a radix-32 $ Q_{32.32}$-format-based floating point MAC is proposed using a Wallace tree/Braun multiplier. Also this article discusses the msb prediction problem and its solution in floating point arithmetic that is not available in modern fused multiply-add designs. The performance results show comparisons between the proposed floating point MAC with various floating point MAC designs for radix-2, -4, -8, and -16. The proposed design has lesser depth than a conventional floating point MAC as well as a lower area requirement than other ways of floating point MAC implementation, both with/without a pipeline.

entry:
@Article{BasiriM:2014:EHB,
  author =       "Mohamed Asan {Basiri M.} and Noor Mahammad Sk",
  title =        "An Efficient Hardware-Based Higher Radix Floating
                 Point {MAC} Design",
  journal =      j-TODAES,
  volume =       "20",
  number =       "1",
  pages =        "15:1--15:??",
  month =        nov,
  year =         "2014",
  CODEN =        "ATASFO",
  DOI =          "https://doi.org/10.1145/2667224",
  ISSN =         "1084-4309 (print), 1557-7309 (electronic)",
  ISSN-L =       "1084-4309",
  bibdate =      "Wed Nov 19 11:18:40 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/todaes/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/todaes.bib",
  abstract =     "This article proposes an effective way of implementing
                 a multiply accumulate circuit (MAC) for high-speed
                 floating point arithmetic operations. The real-world
                 applications related to digital signal processing and
                 the like demand high-performance computation with
                 greater accuracy. In general, digital signals are
                 represented as a sequence of signed/unsigned
                 fixed/floating point numbers. The final result of a MAC
                 operation can be computed by feeding the mantissa of
                 the previous MAC result as one of the partial products
                 to a Wallace tree multiplier or Braun multiplier. Thus,
                 the separate accumulation circuit can be avoided by
                 keeping the circuit depth still within the bounds of
                 the Wallace tree multiplier, namely $ O (\log_2 n) $,
                 or Braun multiplier, namely $ O (n) $. In this article,
                 three kinds of floating point MACs are proposed. The
                 experimental results show 48.54\% of improvement in
                 worst path delay achieved by the proposed floating
                 point MAC using a radix-2 Wallace structure compared
                 with a conventional floating point MAC without a
                 pipeline using a 45nm technology library. The same
                 proposed design gives 39.92\% of improvement in worst
                 path delay without a pipeline using a radix-4 Braun
                 structure as compared with a conventional design. In
                 this article, a radix-32 $ Q_{32.32}$-format-based
                 floating point MAC is proposed using a Wallace
                 tree/Braun multiplier. Also this article discusses the
                 msb prediction problem and its solution in floating
                 point arithmetic that is not available in modern fused
                 multiply-add designs. The performance results show
                 comparisons between the proposed floating point MAC
                 with various floating point MAC designs for radix-2,
                 -4, -8, and -16. The proposed design has lesser depth
                 than a conventional floating point MAC as well as a
                 lower area requirement than other ways of floating
                 point MAC implementation, both with/without a
                 pipeline.",
  acknowledgement = ack-nhfb,
  articleno =    "15",
  fjournal =     "ACM Transactions on Design Automation of Electronic
                 Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J776",
}


bibtype: phdthesis
filename: fparith.bib
label: Boldo:2014:DFV
author: Sylvie Boldo
title: Deductive formal verification: How to make your floating-point programs behave
type: These d habilitation
school: Universite Paris-Sud
address: Paris, France
pages: iv + 80
month: oct
monthnumber: 10
year: 2014
bibdate: Fri Jan 31 15:49:31 2020
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2020.01.31 15:49:31 ???
URL: http://www.lri.fr/~sboldo/files/hdr.pdf
acknowledgement: ack-nhfb
rawauthor: Sylvie Boldo
rawtitle: Deductive formal verification: How to make your floating-point programs behave
entry:
@PhdThesis{Boldo:2014:DFV,
  author =       "Sylvie Boldo",
  title =        "Deductive formal verification: How to make your
                 floating-point programs behave",
  type =         "Th{\`e}se d habilitation",
  school =       "Universit{\b{e}} Paris-Sud",
  address =      "Paris, France",
  pages =        "iv + 80",
  month =        oct,
  year =         "2014",
  bibdate =      "Fri Jan 31 15:49:31 2020",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.lri.fr/~sboldo/files/hdr.pdf",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Bouvier:2014:DFB
author: Cyril Bouvier and Paul Zimmermann
title: Division-Free Binary-to-Decimal Conversion
journal: j-IEEE-TRANS-COMPUT
volume: 63
number: 8
pages: 1895--1901
month: aug
monthnumber: 8
year: 2014
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2014.2315621
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Aug 25 08:24:32 2014
bibtimestamp: 2014.08.25 08:24:32 ???
URL: https://members.loria.fr/PZimmermann/papers/get_str.pdf
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Cyril Bouvier and Paul Zimmermann
rawtitle: Division-Free Binary-to-Decimal Conversion
entry:
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  author =       "Cyril Bouvier and Paul Zimmermann",
  title =        "Division-Free Binary-to-Decimal Conversion",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "63",
  number =       "8",
  pages =        "1895--1901",
  month =        aug,
  year =         "2014",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2014.2315621",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Aug 25 08:24:32 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  URL =          "https://members.loria.fr/PZimmermann/papers/get_str.pdf",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: inproceedings
filename: fparith.bib
label: Chiang:2014:ESI
author: Wei-Fan Chiang and Ganesh Gopalakrishnan and Zvonimir Rakamaric and Alexey Solovyev
editor: ACM
title: Efficient Search for Inputs Causing High Floating-point Errors
publisher: pub-ACM
address: pub-ACM:adr
pages: 43--52
year: 2014
DOI: https://doi.org/10.1145/2555243.2555265
ISBN: 1-4503-2656-0 OR 1450326560
ISBN13: 978-1-4503-2656-8 OR 9781450326568
bibdate: Tue Mar 18 14:32:45 2014
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2014.03.18 14:32:45 ???
URL: http://dl.acm.org/citation.cfm?doid=2555243.2555265
acknowledgement: ack-nhfb
rawauthor: Wei-Fan Chiang and Ganesh Gopalakrishnan and Zvonimir Rakamari{\'c} and Alexey Solovyev
raweditor: {ACM}
rawtitle: Efficient Search for Inputs Causing High Floating-point Errors
booktitle:
PPoPP '14: Proceedings of the 19th ACM SIGPLAN symposium on Principles and practice of parallel programming

rawbooktitle:
{PPoPP '14: Proceedings of the 19th ACM SIGPLAN symposium on Principles and practice of parallel programming}

entry:
@InProceedings{Chiang:2014:ESI,
  author =       "Wei-Fan Chiang and Ganesh Gopalakrishnan and Zvonimir
                 Rakamari{\'c} and Alexey Solovyev",
  editor =       "{ACM}",
  booktitle =    "{PPoPP '14: Proceedings of the 19th ACM SIGPLAN
                 symposium on Principles and practice of parallel
                 programming}",
  title =        "Efficient Search for Inputs Causing High
                 Floating-point Errors",
  publisher =    pub-ACM,
  address =      pub-ACM:adr,
  pages =        "43--52",
  year =         "2014",
  DOI =          "https://doi.org/10.1145/2555243.2555265",
  ISBN =         "1-4503-2656-0",
  ISBN-13 =      "978-1-4503-2656-8",
  LCCN =         "????",
  bibdate =      "Tue Mar 18 14:32:45 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://dl.acm.org/citation.cfm?doid=2555243.2555265",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Cibikdiken:2014:CMM
author: Ali Osman Cibikdiken and Kemal Aydin
title: Computation of the monodromy matrix in floating point arithmetic with the Wilkinson Model
journal: j-COMPUT-MATH-APPL
volume: 67
number: 5
pages: 1186--1194
month: mar
monthnumber: 3
year: 2014
CODEN: CMAPDK
ISSN: 0898-1221 (print), 1873-7668 (electronic) OR 08981221 (print), 18737668 (electronic)
ISSNL: 0898-1221 OR 08981221
bibdate: Wed Mar 1 21:51:31 MST 2017
bibtimestamp: 2017.03.01 21:51:31 MST
URL: http://www.sciencedirect.com/science/article/pii/S0898122113006706
fjournal: Computers and Mathematics with Applications
acknowledgement: ack-nhfb
journalURL: http://www.sciencedirect.com/science/journal/08981221
rawauthor: Ali Osman {\c{C}}ibikdiken and Kemal Aydin
rawtitle: Computation of the monodromy matrix in floating point arithmetic with the {Wilkinson} Model
entry:
@Article{Cibikdiken:2014:CMM,
  author =       "Ali Osman {\c{C}}ibikdiken and Kemal Aydin",
  title =        "Computation of the monodromy matrix in floating point
                 arithmetic with the {Wilkinson} Model",
  journal =      j-COMPUT-MATH-APPL,
  volume =       "67",
  number =       "5",
  pages =        "1186--1194",
  month =        mar,
  year =         "2014",
  CODEN =        "CMAPDK",
  ISSN =         "0898-1221 (print), 1873-7668 (electronic)",
  ISSN-L =       "0898-1221",
  bibdate =      "Wed Mar 1 21:51:31 MST 2017",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/computmathappl2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://www.sciencedirect.com/science/article/pii/S0898122113006706",
  acknowledgement = ack-nhfb,
  fjournal =     "Computers and Mathematics with Applications",
  journal-URL =  "http://www.sciencedirect.com/science/journal/08981221",
}


bibtype: article
filename: fparith.bib
label: Darulova:2014:SCR
author: Eva Darulova and Viktor Kuncak
title: Sound compilation of reals
journal: j-SIGPLAN
volume: 49
number: 1
pages: 235--248
month: jan
monthnumber: 1
year: 2014
CODEN: SINODQ
DOI: https://doi.org/10.1145/2578855.2535874
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Tue Mar 4 17:04:57 MST 2014
bibtimestamp: 2014.03.04 17:04:57 MST
note: POPL '14 conference proceedings.
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Eva Darulova and Viktor Kuncak
rawnote: POPL '14 conference proceedings.
rawtitle: Sound compilation of reals
abstract:
Writing accurate numerical software is hard because of many sources of unavoidable uncertainties, including finite numerical precision of implementations. We present a programming model where the user writes a program in a real-valued implementation and specification language that explicitly includes different types of uncertainties. We then present a compilation algorithm that generates a finite-precision implementation that is guaranteed to meet the desired precision with respect to real numbers. Our compilation performs a number of verification steps for different candidate precisions. It generates verification conditions that treat all sources of uncertainties in a unified way and encode reasoning about finite-precision roundoff errors into reasoning about real numbers. Such verification conditions can be used as a standardized format for verifying the precision and the correctness of numerical programs. Due to their non-linear nature, precise reasoning about these verification conditions remains difficult and cannot be handled using state-of-the art SMT solvers alone. We therefore propose a new procedure that combines exact SMT solving over reals with approximate and sound affine and interval arithmetic. We show that this approach overcomes scalability limitations of SMT solvers while providing improved precision over affine and interval arithmetic. Our implementation gives promising results on several numerical models, including dynamical systems, transcendental functions, and controller implementations.

rawabstract:
Writing accurate numerical software is hard because of many sources of unavoidable uncertainties, including finite numerical precision of implementations. We present a programming model where the user writes a program in a real-valued implementation and specification language that explicitly includes different types of uncertainties. We then present a compilation algorithm that generates a finite-precision implementation that is guaranteed to meet the desired precision with respect to real numbers. Our compilation performs a number of verification steps for different candidate precisions. It generates verification conditions that treat all sources of uncertainties in a unified way and encode reasoning about finite-precision roundoff errors into reasoning about real numbers. Such verification conditions can be used as a standardized format for verifying the precision and the correctness of numerical programs. Due to their non-linear nature, precise reasoning about these verification conditions remains difficult and cannot be handled using state-of-the art SMT solvers alone. We therefore propose a new procedure that combines exact SMT solving over reals with approximate and sound affine and interval arithmetic. We show that this approach overcomes scalability limitations of SMT solvers while providing improved precision over affine and interval arithmetic. Our implementation gives promising results on several numerical models, including dynamical systems, transcendental functions, and controller implementations.

entry:
@Article{Darulova:2014:SCR,
  author =       "Eva Darulova and Viktor Kuncak",
  title =        "Sound compilation of reals",
  journal =      j-SIGPLAN,
  volume =       "49",
  number =       "1",
  pages =        "235--248",
  month =        jan,
  year =         "2014",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/2578855.2535874",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Tue Mar 4 17:04:57 MST 2014",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  note =         "POPL '14 conference proceedings.",
  abstract =     "Writing accurate numerical software is hard because of
                 many sources of unavoidable uncertainties, including
                 finite numerical precision of implementations. We
                 present a programming model where the user writes a
                 program in a real-valued implementation and
                 specification language that explicitly includes
                 different types of uncertainties. We then present a
                 compilation algorithm that generates a finite-precision
                 implementation that is guaranteed to meet the desired
                 precision with respect to real numbers. Our compilation
                 performs a number of verification steps for different
                 candidate precisions. It generates verification
                 conditions that treat all sources of uncertainties in a
                 unified way and encode reasoning about finite-precision
                 roundoff errors into reasoning about real numbers. Such
                 verification conditions can be used as a standardized
                 format for verifying the precision and the correctness
                 of numerical programs. Due to their non-linear nature,
                 precise reasoning about these verification conditions
                 remains difficult and cannot be handled using
                 state-of-the art SMT solvers alone. We therefore
                 propose a new procedure that combines exact SMT solving
                 over reals with approximate and sound affine and
                 interval arithmetic. We show that this approach
                 overcomes scalability limitations of SMT solvers while
                 providing improved precision over affine and interval
                 arithmetic. Our implementation gives promising results
                 on several numerical models, including dynamical
                 systems, transcendental functions, and controller
                 implementations.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
}


bibtype: article
filename: fparith.bib
label: Darulova:2014:TCR
author: Eva Darulova and Viktor Kuncak
title: Towards a Compiler for Reals
journal: arxiv.org
pages: 1--24
day: 1
month: oct
monthnumber: 10
year: 2014
bibdate: Sat Apr 02 15:52:17 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.04.02 15:52:17 ???
URL: http://arxiv.org/abs/1410.0198
acknowledgement: ack-nhfb
rawauthor: Eva Darulova and Viktor Kuncak
rawtitle: Towards a Compiler for Reals
abstract:
Numerical software, common in scientific computing or embedded systems, inevitably uses an approximation of the real arithmetic in which most algorithms are designed. In many domains, roundoff errors are not the only source of inaccuracy and measurement and other input errors further increase the uncertainty of the computed results. Adequate tools are needed to help users select suitable approximations, especially for safety-critical applications. We present the source-to-source compiler Rosa which takes as input a real-valued program with error specifications and synthesizes code over an appropriate floating-point or fixed-point data type. The main challenge of such a compiler is a fully automated, sound and yet accurate enough numerical error estimation. We present a unified technique for floating-point and fixed-point arithmetic of various precisions which can handle nonlinear arithmetic, determine closed- form symbolic invariants for unbounded loops and quantify the effects of discontinuities on numerical errors. We evaluate Rosa on a number of benchmarks from scientific computing and embedded systems and, comparing it to state-of-the-art in automated error estimation, show it presents an interesting trade-off between accuracy and performance.

rawabstract:
Numerical software, common in scientific computing or embedded systems, inevitably uses an approximation of the real arithmetic in which most algorithms are designed. In many domains, roundoff errors are not the only source of inaccuracy and measurement and other input errors further increase the uncertainty of the computed results. Adequate tools are needed to help users select suitable approximations, especially for safety-critical applications. We present the source-to-source compiler Rosa which takes as input a real-valued program with error specifications and synthesizes code over an appropriate floating-point or fixed-point data type. The main challenge of such a compiler is a fully automated, sound and yet accurate enough numerical error estimation. We present a unified technique for floating-point and fixed-point arithmetic of various precisions which can handle nonlinear arithmetic, determine closed- form symbolic invariants for unbounded loops and quantify the effects of discontinuities on numerical errors. We evaluate Rosa on a number of benchmarks from scientific computing and embedded systems and, comparing it to state-of-the-art in automated error estimation, show it presents an interesting trade-off between accuracy and performance.

entry:
@Article{Darulova:2014:TCR,
  author =       "Eva Darulova and Viktor Kuncak",
  title =        "Towards a Compiler for Reals",
  journal =      "arxiv.org",
  volume =       "??",
  number =       "??",
  pages =        "1--24",
  day =          "1",
  month =        oct,
  year =         "2014",
  bibdate =      "Sat Apr 02 15:52:17 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1410.0198",
  abstract =     "Numerical software, common in scientific computing or
                 embedded systems, inevitably uses an approximation of
                 the real arithmetic in which most algorithms are
                 designed. In many domains, roundoff errors are not the
                 only source of inaccuracy and measurement and other
                 input errors further increase the uncertainty of the
                 computed results. Adequate tools are needed to help
                 users select suitable approximations, especially for
                 safety-critical applications. We present the
                 source-to-source compiler Rosa which takes as input a
                 real-valued program with error specifications and
                 synthesizes code over an appropriate floating-point or
                 fixed-point data type. The main challenge of such a
                 compiler is a fully automated, sound and yet accurate
                 enough numerical error estimation. We present a unified
                 technique for floating-point and fixed-point arithmetic
                 of various precisions which can handle nonlinear
                 arithmetic, determine closed- form symbolic invariants
                 for unbounded loops and quantify the effects of
                 discontinuities on numerical errors. We evaluate Rosa
                 on a number of benchmarks from scientific computing and
                 embedded systems and, comparing it to state-of-the-art
                 in automated error estimation, show it presents an
                 interesting trade-off between accuracy and
                 performance.",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: DelBarrio:2014:ULP
author: Alberto A. Del Barrio and Nader Bagherzadeh and Roman Hermida
title: Ultra-low-power adder stage design for exascale floating point units
journal: j-TECS
volume: 13
number: 3s
pages: 105:1--105:??
month: mar
monthnumber: 3
year: 2014
DOI: https://doi.org/10.1145/2567932
ISSN: 1539-9087 (print), 1558-3465 (electronic) OR 15399087 (print), 15583465 (electronic)
ISSNL: 1539-9087 OR 15399087
bibdate: Mon Mar 24 17:17:02 MDT 2014
bibtimestamp: 2014.03.24 17:17:02 MDT
fjournal: ACM Transactions on Embedded Computing Systems
acknowledgement: ack-nhfb
articleno: 105
journalURL: http://portal.acm.org/browse_dl.cfm?&idx=J840
rawauthor: Alberto A. {Del Barrio} and Nader Bagherzadeh and Rom{\'a}n Hermida
rawtitle: Ultra-low-power adder stage design for exascale floating point units
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/tecs.bib

abstract:
Currently, the most powerful supercomputers can provide tens of petaflops. Future many-core systems are estimated to provide an exaflop. However, the power budget limitation makes these machines still infeasible and unaffordable. Floating Point Units (FPUs) are critical from both the power consumption and performance points of view of today's microprocessors and supercomputers. Literature offers very different designs. Some of them are focused on increasing performance no matter the penalty, and others on decreasing power at the expense of lower performance. In this article, we propose a novel approach for reducing the power of the FPU without degrading the rest of parameters. Concretely, this power reduction is also accompanied by an area reduction and a performance improvement. Hence, an overall energy gain will be produced. According to our experiments, our proposed unit consumes 17.5%, 23% and 16.5% less energy for single, double and quadruple precision, with an additional 15%, 21.5% and 14.5% delay reduction, respectively. Furthermore, area is also diminished by 4%, 4.5% and 5%.

rawabstract:
Currently, the most powerful supercomputers can provide tens of petaflops. Future many-core systems are estimated to provide an exaflop. However, the power budget limitation makes these machines still infeasible and unaffordable. Floating Point Units (FPUs) are critical from both the power consumption and performance points of view of today's microprocessors and supercomputers. Literature offers very different designs. Some of them are focused on increasing performance no matter the penalty, and others on decreasing power at the expense of lower performance. In this article, we propose a novel approach for reducing the power of the FPU without degrading the rest of parameters. Concretely, this power reduction is also accompanied by an area reduction and a performance improvement. Hence, an overall energy gain will be produced. According to our experiments, our proposed unit consumes 17.5\%, 23\% and 16.5\% less energy for single, double and quadruple precision, with an additional 15\%, 21.5\% and 14.5\% delay reduction, respectively. Furthermore, area is also diminished by 4\%, 4.5\% and 5\%.

entry:
@Article{DelBarrio:2014:ULP,
  author =       "Alberto A. {Del Barrio} and Nader Bagherzadeh and
                 Rom{\'a}n Hermida",
  title =        "Ultra-low-power adder stage design for exascale
                 floating point units",
  journal =      j-TECS,
  volume =       "13",
  number =       "3s",
  pages =        "105:1--105:??",
  month =        mar,
  year =         "2014",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/2567932",
  ISSN =         "1539-9087 (print), 1558-3465 (electronic)",
  ISSN-L =       "1539-9087",
  bibdate =      "Mon Mar 24 17:17:02 MDT 2014",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/tecs.bib",
  abstract =     "Currently, the most powerful supercomputers can
                 provide tens of petaflops. Future many-core systems are
                 estimated to provide an exaflop. However, the power
                 budget limitation makes these machines still infeasible
                 and unaffordable. Floating Point Units (FPUs) are
                 critical from both the power consumption and
                 performance points of view of today's microprocessors
                 and supercomputers. Literature offers very different
                 designs. Some of them are focused on increasing
                 performance no matter the penalty, and others on
                 decreasing power at the expense of lower performance.
                 In this article, we propose a novel approach for
                 reducing the power of the FPU without degrading the
                 rest of parameters. Concretely, this power reduction is
                 also accompanied by an area reduction and a performance
                 improvement. Hence, an overall energy gain will be
                 produced. According to our experiments, our proposed
                 unit consumes 17.5\%, 23\% and 16.5\% less energy for
                 single, double and quadruple precision, with an
                 additional 15\%, 21.5\% and 14.5\% delay reduction,
                 respectively. Furthermore, area is also diminished by
                 4\%, 4.5\% and 5\%.",
  acknowledgement = ack-nhfb,
  articleno =    "105",
  fjournal =     "ACM Transactions on Embedded Computing Systems",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?&idx=J840",
}


bibtype: misc
filename: fparith.bib
label: Demmel:2014:THS
author: James Demmel and Hong Diep Nguyen
title: Toward hardware support for Reproducible BLAS
pages: 105:1--105:??
day: 24
month: sep
monthnumber: 9
year: 2014
bibdate: Mon Jan 04 15:49:09 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.01.04 15:49:09 ???
URL: http://bebop.cs.berkeley.edu/reproblas/img/pdf.png
acknowledgement: ack-nhfb
howpublished: SCAN 2014 talk slides.
rawauthor: James Demmel and Hong Diep Nguyen
rawtitle: Toward hardware support for Reproducible {BLAS}
entry:
@Misc{Demmel:2014:THS,
  author =       "James Demmel and Hong Diep Nguyen",
  title =        "Toward hardware support for Reproducible {BLAS}",
  howpublished = "SCAN 2014 talk slides.",
  day =          "24",
  month =        sep,
  year =         "2014",
  bibdate =      "Mon Jan 04 15:49:09 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://bebop.cs.berkeley.edu/reproblas/img/pdf.png",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Doerr:2014:RRP
author: Benjamin Doerr and Magnus Wahlstrom
title: Randomized Rounding in the Presence of a Cardinality Constraint
journal: j-ACM-J-EXP-ALGORITHMICS
volume: 19
number: 1
pages: 1.2:1--1.2:??
month: may
monthnumber: 5
year: 2014
DOI: https://doi.org/10.1145/2594409
ISSN: 1084-6654 OR 10846654
ISSNL: 1084-6654 OR 10846654
bibdate: Wed May 21 14:36:05 MDT 2014
bibtimestamp: 2014.05.21 14:36:05 MDT
fjournal: Journal of Experimental Algorithmics (JEA)
acknowledgement: ack-nhfb
articleno: 1.2
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J430
rawauthor: Benjamin Doerr and Magnus Wahlstr{\"o}m
rawtitle: Randomized Rounding in the Presence of a Cardinality Constraint
bibsource:
http://portal.acm.org/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jea.bib

abstract:
We consider the problem of generating randomized roundings that satisfy a single cardinality constraint and admit Chernoff-type large deviation bounds for weighted sums of the variables. That this can be done efficiently was proven by Srinivasan [2001], a different approach was later given by the first author [Doerr 2006]. In this work, we (a) present an improved version of the bitwise derandomization given by Doerr, (b) give the first derandomization of Srinivasan's tree-based randomized approach and prove its correctness, and (c) experimentally compare the resulting algorithms. Our experiments show that adding a single cardinality constraint typically reduces the rounding errors and only moderately increases the running times. In general, our derandomization of the tree-based approach is superior to the derandomized bitwise one, while the two randomized versions produce very similar rounding errors. When implementing the derandomized tree-based approach, however, the choice of the tree is important.

rawabstract:
We consider the problem of generating randomized roundings that satisfy a single cardinality constraint and admit Chernoff-type large deviation bounds for weighted sums of the variables. That this can be done efficiently was proven by Srinivasan [2001], a different approach was later given by the first author [Doerr 2006]. In this work, we (a) present an improved version of the bitwise derandomization given by Doerr, (b) give the first derandomization of Srinivasan's tree-based randomized approach and prove its correctness, and (c) experimentally compare the resulting algorithms. Our experiments show that adding a single cardinality constraint typically reduces the rounding errors and only moderately increases the running times. In general, our derandomization of the tree-based approach is superior to the derandomized bitwise one, while the two randomized versions produce very similar rounding errors. When implementing the derandomized tree-based approach, however, the choice of the tree is important.

entry:
@Article{Doerr:2014:RRP,
  author =       "Benjamin Doerr and Magnus Wahlstr{\"o}m",
  title =        "Randomized Rounding in the Presence of a Cardinality
                 Constraint",
  journal =      j-ACM-J-EXP-ALGORITHMICS,
  volume =       "19",
  number =       "1",
  pages =        "1.2:1--1.2:??",
  month =        may,
  year =         "2014",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/2594409",
  ISSN =         "1084-6654",
  ISSN-L =       "1084-6654",
  bibdate =      "Wed May 21 14:36:05 MDT 2014",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jea.bib",
  abstract =     "We consider the problem of generating randomized
                 roundings that satisfy a single cardinality constraint
                 and admit Chernoff-type large deviation bounds for
                 weighted sums of the variables. That this can be done
                 efficiently was proven by Srinivasan [2001], a
                 different approach was later given by the first author
                 [Doerr 2006]. In this work, we (a) present an improved
                 version of the bitwise derandomization given by Doerr,
                 (b) give the first derandomization of Srinivasan's
                 tree-based randomized approach and prove its
                 correctness, and (c) experimentally compare the
                 resulting algorithms. Our experiments show that adding
                 a single cardinality constraint typically reduces the
                 rounding errors and only moderately increases the
                 running times. In general, our derandomization of the
                 tree-based approach is superior to the derandomized
                 bitwise one, while the two randomized versions produce
                 very similar rounding errors. When implementing the
                 derandomized tree-based approach, however, the choice
                 of the tree is important.",
  acknowledgement = ack-nhfb,
  articleno =    "1.2",
  fjournal =     "Journal of Experimental Algorithmics (JEA)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J430",
}


bibtype: article
filename: fparith.bib
label: Drane:2014:SCF
author: T. A. Drane and T. M. Rose and G. A. Constantinides
title: On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays
journal: j-IEEE-TRANS-COMPUT
volume: 63
number: 10
pages: 2513--2525
month: oct
monthnumber: 10
year: 2014
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2013.126
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Thu Nov 06 07:29:34 2014
bibtimestamp: 2014.11.06 07:29:34 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: T. A. Drane and T. M. Rose and G. A. Constantinides
rawtitle: On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays
keywords:
arbitrary array; bit vectors; correct rounding; correct-by-construction; Data-path design; elemental semiconductors; faithfully rounded truncated arrays; faithfully rounded truncated multipliers; fixed point arithmetic; fixed-point multiplication; floating-point arithmetic; hardware description languages; HDL code; heuristically inspired schemes; high-speed arithmetic; Monte Carlo methods; Monte Carlo simulation; multiplying circuits; parallel circuits; partial product array; Si; silicon; silicon area; systematic creation; truncated multiplier schemes; word length 32 bit; worst-case analysis; worst-case error

entry:
@Article{Drane:2014:SCF,
  author =       "T. A. Drane and T. M. Rose and G. A. Constantinides",
  title =        "On the Systematic Creation of Faithfully Rounded
                 Truncated Multipliers and Arrays",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "63",
  number =       "10",
  pages =        "2513--2525",
  month =        oct,
  year =         "2014",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2013.126",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Thu Nov 06 07:29:34 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
  keywords =     "arbitrary array; bit vectors; correct rounding;
                 correct-by-construction; Data-path design; elemental
                 semiconductors; faithfully rounded truncated arrays;
                 faithfully rounded truncated multipliers; fixed point
                 arithmetic; fixed-point multiplication; floating-point
                 arithmetic; hardware description languages; HDL code;
                 heuristically inspired schemes; high-speed arithmetic;
                 Monte Carlo methods; Monte Carlo simulation;
                 multiplying circuits; parallel circuits; partial
                 product array; Si; silicon; silicon area; systematic
                 creation; truncated multiplier schemes; word length 32
                 bit; worst-case analysis; worst-case error",
}


bibtype: article
filename: fparith.bib
label: Du:2014:AEP
author: Peibing Du and Hao Jiang and Lizhi Cheng
title: Accurate Evaluation of Polynomials in Legendre Basis
journal: j-J-APPL-MATH
volume: 2014
pages: 742538:1--742538:13
year: 2014
DOI: https://doi.org/10.1155/2014/742538
ISSN: 1110-757X (print), 1687-0042 (electronic) OR 1110757X (print), 16870042 (electronic)
ISSNL: 1110-757X OR 1110757X
bibdate: Mon Mar 19 14:19:47 2018
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2018.03.19 14:19:47 ???
URL: https://www.hindawi.com/journals/jam/2014/742538/
fjournal: Journal of Applied Mathematics
acknowledgement: ack-nhfb
journalURL: http://www.hindawi.com/journals/jam/
rawauthor: Peibing Du and Hao Jiang and Lizhi Cheng
rawtitle: Accurate Evaluation of Polynomials in {Legendre} Basis
entry:
@Article{Du:2014:AEP,
  author =       "Peibing Du and Hao Jiang and Lizhi Cheng",
  title =        "Accurate Evaluation of Polynomials in {Legendre}
                 Basis",
  journal =      j-J-APPL-MATH,
  volume =       "2014",
  pages =        "742538:1--742538:13",
  year =         "2014",
  DOI =          "https://doi.org/10.1155/2014/742538",
  ISSN =         "1110-757X (print), 1687-0042 (electronic)",
  ISSN-L =       "1110-757X",
  bibdate =      "Mon Mar 19 14:19:47 2018",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "https://www.hindawi.com/journals/jam/2014/742538/",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Applied Mathematics",
  journal-URL =  "http://www.hindawi.com/journals/jam/",
}


bibtype: article
filename: fparith.bib
label: Dumas:2014:NRI
author: Jean-Guillaume Dumas
title: On Newton--Raphson Iteration for Multiplicative Inverses Modulo Prime Powers
journal: j-IEEE-TRANS-COMPUT
volume: 63
number: 8
pages: 2106--2109
month: aug
monthnumber: 8
year: 2014
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2013.94
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Aug 25 08:24:32 2014
bibtimestamp: 2014.08.25 08:24:32 ???
note: See corrections cite Walther:2019:VNR.
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Jean-Guillaume Dumas
rawnote: See corrections \cite{Walther:2019:VNR}.
rawtitle: On {Newton--Raphson} Iteration for Multiplicative Inverses Modulo Prime Powers
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib; https://www.math.utah.edu/pub/tex/bib/toms.bib

entry:
@Article{Dumas:2014:NRI,
  author =       "Jean-Guillaume Dumas",
  title =        "On {Newton--Raphson} Iteration for Multiplicative
                 Inverses Modulo Prime Powers",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "63",
  number =       "8",
  pages =        "2106--2109",
  month =        aug,
  year =         "2014",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2013.94",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Aug 25 08:24:32 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  note =         "See corrections \cite{Walther:2019:VNR}.",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Gilani:2014:EEP
author: Syed Zohaib Gilani and Nam Sung Kim and Michael Schulte
title: Energy-Efficient Pixel-Arithmetic
journal: j-IEEE-TRANS-COMPUT
volume: 63
number: 8
pages: 1--1
month: aug
monthnumber: 8
year: 2014
CODEN: ITCOB4
DOI: https://doi.org/10.1109/TC.2014.2325827
ISSN: 0018-9340 (print), 1557-9956 (electronic) OR 00189340 (print), 15579956 (electronic)
ISSNL: 0018-9340 OR 00189340
bibdate: Mon Aug 25 08:24:32 2014
bibtimestamp: 2014.08.25 08:24:32 ???
fjournal: IEEE Transactions on Computers
acknowledgement: ack-nhfb
ajournal: IEEE Trans. Comput.
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12
rawauthor: Syed Zohaib Gilani and Nam Sung Kim and Michael Schulte
rawtitle: Energy-Efficient Pixel-Arithmetic
entry:
@Article{Gilani:2014:EEP,
  author =       "Syed Zohaib Gilani and Nam Sung Kim and Michael
                 Schulte",
  title =        "Energy-Efficient Pixel-Arithmetic",
  journal =      j-IEEE-TRANS-COMPUT,
  volume =       "63",
  number =       "8",
  pages =        "1--1",
  month =        aug,
  year =         "2014",
  CODEN =        "ITCOB4",
  DOI =          "https://doi.org/10.1109/TC.2014.2325827",
  ISSN =         "0018-9340 (print), 1557-9956 (electronic)",
  ISSN-L =       "0018-9340",
  bibdate =      "Mon Aug 25 08:24:32 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetranscomput2010.bib",
  acknowledgement = ack-nhfb,
  ajournal =     "IEEE Trans. Comput.",
  fjournal =     "IEEE Transactions on Computers",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12",
}


bibtype: article
filename: fparith.bib
label: Gladshtein:2014:DBP
author: Michael Gladshtein
title: Delay-based processing-in-wire for design of QCA serial decimal arithmetic units
journal: j-JETC
volume: 10
number: 2
pages: 13:1--13:??
month: feb
monthnumber: 2
year: 2014
DOI: https://doi.org/10.1145/2564927
ISSN: 1550-4832 (print), 1550-4840 (electronic) OR 15504832 (print), 15504840 (electronic)
ISSNL: 1550-4832 OR 15504832
bibdate: Fri Feb 28 17:06:25 MST 2014
bibtimestamp: 2014.02.28 17:06:25 MST
fjournal: ACM Journal on Emerging Technologies in Computing Systems (JETC)
acknowledgement: ack-nhfb
articleno: 13
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J967
rawauthor: Michael Gladshtein
rawtitle: Delay-based processing-in-wire for design of {QCA} serial decimal arithmetic units
bibsource:
http://www.acm.org/pubs/contents/journals/jetc/; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jetc.bib

abstract:
Quantum-dot cellular automata (QCA) technology is now considered to be one of the prospective technologies for a nanocomputer creation. The physical properties of QCA and its expanding range of computer applications make it expedient to use the novel paradigm of nanocomputer architecture: serial decimal storage-transfer-processing. The delay-based encoding of decimal digits allows the use a delay element as a main element of QCA serial arithmetic units. The simple implementation of the delay element by a short length of QCA wire results in reduction of complexity and of the area required for a QCA circuit. The theoretical basics of delay-based processing-in-wire and design examples of QCA serial decimal arithmetic units are presented.

rawabstract:
Quantum-dot cellular automata (QCA) technology is now considered to be one of the prospective technologies for a nanocomputer creation. The physical properties of QCA and its expanding range of computer applications make it expedient to use the novel paradigm of nanocomputer architecture: serial decimal storage-transfer-processing. The delay-based encoding of decimal digits allows the use a delay element as a main element of QCA serial arithmetic units. The simple implementation of the delay element by a short length of QCA wire results in reduction of complexity and of the area required for a QCA circuit. The theoretical basics of delay-based processing-in-wire and design examples of QCA serial decimal arithmetic units are presented.

entry:
@Article{Gladshtein:2014:DBP,
  author =       "Michael Gladshtein",
  title =        "Delay-based processing-in-wire for design of {QCA}
                 serial decimal arithmetic units",
  journal =      j-JETC,
  volume =       "10",
  number =       "2",
  pages =        "13:1--13:??",
  month =        feb,
  year =         "2014",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/2564927",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Feb 28 17:06:25 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Quantum-dot cellular automata (QCA) technology is now
                 considered to be one of the prospective technologies
                 for a nanocomputer creation. The physical properties of
                 QCA and its expanding range of computer applications
                 make it expedient to use the novel paradigm of
                 nanocomputer architecture: serial decimal
                 storage-transfer-processing. The delay-based encoding
                 of decimal digits allows the use a delay element as a
                 main element of QCA serial arithmetic units. The simple
                 implementation of the delay element by a short length
                 of QCA wire results in reduction of complexity and of
                 the area required for a QCA circuit. The theoretical
                 basics of delay-based processing-in-wire and design
                 examples of QCA serial decimal arithmetic units are
                 presented.",
  acknowledgement = ack-nhfb,
  articleno =    "13",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}


bibtype: article
filename: fparith.bib
label: Goualard:2014:HDY
author: Frederic Goualard
title: How do you compute the midpoint of an interval?
journal: j-TOMS
volume: 40
number: 2
pages: 11:1--11:25
month: feb
monthnumber: 2
year: 2014
CODEN: ACMSCU
DOI: https://doi.org/10.1145/2493882
ISSN: 0098-3500 (print), 1557-7295 (electronic) OR 00983500 (print), 15577295 (electronic)
ISSNL: 0098-3500 OR 00983500
bibdate: Fri Mar 14 06:30:41 MDT 2014
bibtimestamp: 2014.03.14 06:30:41 MDT
fjournal: ACM Transactions on Mathematical Software (TOMS)
acknowledgement: ack-nhfb
articleno: 11
journalURL: https://dl.acm.org/loi/toms
rawauthor: Fr{\'e}d{\'e}ric Goualard
rawtitle: How do you compute the midpoint of an interval?
abstract:
The algorithm that computes the midpoint of an interval with floating-point bounds requires some careful devising to handle all possible inputs correctly. We review several implementations from prominent C/C++ interval arithmetic packages and analyze their potential failure to deliver the expected results. We then show how to amend them to avoid common pitfalls. The results presented are also relevant to noninterval arithmetic computation such as the implementation of bisection methods. Enough background on IEEE 754 floating-point arithmetic is provided for this article to serve as a practical introduction to the analysis of floating-point computation.

rawabstract:
The algorithm that computes the midpoint of an interval with floating-point bounds requires some careful devising to handle all possible inputs correctly. We review several implementations from prominent C/C++ interval arithmetic packages and analyze their potential failure to deliver the expected results. We then show how to amend them to avoid common pitfalls. The results presented are also relevant to noninterval arithmetic computation such as the implementation of bisection methods. Enough background on IEEE 754 floating-point arithmetic is provided for this article to serve as a practical introduction to the analysis of floating-point computation.

entry:
@Article{Goualard:2014:HDY,
  author =       "Fr{\'e}d{\'e}ric Goualard",
  title =        "How do you compute the midpoint of an interval?",
  journal =      j-TOMS,
  volume =       "40",
  number =       "2",
  pages =        "11:1--11:25",
  month =        feb,
  year =         "2014",
  CODEN =        "ACMSCU",
  DOI =          "https://doi.org/10.1145/2493882",
  ISSN =         "0098-3500 (print), 1557-7295 (electronic)",
  ISSN-L =       "0098-3500",
  bibdate =      "Fri Mar 14 06:30:41 MDT 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/toms/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/toms.bib",
  abstract =     "The algorithm that computes the midpoint of an
                 interval with floating-point bounds requires some
                 careful devising to handle all possible inputs
                 correctly. We review several implementations from
                 prominent C/C++ interval arithmetic packages and
                 analyze their potential failure to deliver the expected
                 results. We then show how to amend them to avoid common
                 pitfalls. The results presented are also relevant to
                 noninterval arithmetic computation such as the
                 implementation of bisection methods. Enough background
                 on IEEE 754 floating-point arithmetic is provided for
                 this article to serve as a practical introduction to
                 the analysis of floating-point computation.",
  acknowledgement = ack-nhfb,
  articleno =    "11",
  fjournal =     "ACM Transactions on Mathematical Software (TOMS)",
  journal-URL =  "https://dl.acm.org/loi/toms",
}


bibtype: article
filename: fparith.bib
label: Graillat:2014:MRE
author: Stef Graillat and Vincent Lefevre and Jean-Michel Muller
title: On the maximum relative error when computing $ x^n $ in floating-point arithmetic
journal: arXiv.org
pages: ??--??
day: 11
month: feb
monthnumber: 2
year: 2014
bibdate: Wed Sep 30 12:43:49 MDT 2015
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2015.09.30 12:43:49 MDT
URL: http://arxiv.org/abs/1402.2991
subject: Numerical Analysis (cs.NA); Numerical Analysis (math.NA)
acknowledgement: ack-nhfb
rawauthor: Stef Graillat and Vincent Lef{\`e}vre and Jean-Michel Muller
rawtitle: On the maximum relative error when computing $ x^n $ in floating-point arithmetic
abstract:
In this paper, we improve the usual relative error bound for the computation of $ x^n $ through iterated multiplications by x in binary floating-point arithmetic. The obtained error bound is only slightly better than the usual one, but it is simpler. We also discuss the more general problem of computing the product of n terms.

rawabstract:
In this paper, we improve the usual relative error bound for the computation of $ x^n $ through iterated multiplications by x in binary floating-point arithmetic. The obtained error bound is only slightly better than the usual one, but it is simpler. We also discuss the more general problem of computing the product of n terms.

entry:
@Article{Graillat:2014:MRE,
  author =       "Stef Graillat and Vincent Lef{\`e}vre and Jean-Michel
                 Muller",
  title =        "On the maximum relative error when computing $ x^n $
                 in floating-point arithmetic",
  journal =      "arXiv.org",
  volume =       "??",
  number =       "??",
  pages =        "??--??",
  day =          "11",
  month =        feb,
  year =         "2014",
  CODEN =        "????",
  ISSN =         "????",
  ISSN-L =       "????",
  bibdate =      "Wed Sep 30 12:43:49 MDT 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://arxiv.org/abs/1402.2991",
  abstract =     "In this paper, we improve the usual relative error
                 bound for the computation of $ x^n $ through iterated
                 multiplications by x in binary floating-point
                 arithmetic. The obtained error bound is only slightly
                 better than the usual one, but it is simpler. We also
                 discuss the more general problem of computing the
                 product of n terms.",
  acknowledgement = ack-nhfb,
  subject =      "Numerical Analysis (cs.NA); Numerical Analysis
                 (math.NA)",
}


bibtype: inproceedings
filename: fparith.bib
label: Hormigo:2014:ODC
author: J. Hormigo and J. Villalba
editor: Michael B. Matthews
title: Optimizing DSP circuits by a new family of arithmetic operators
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 871--875
year: 2014
DOI: https://doi.org/10.1109/ACSSC.2014.7094576
ISBN: 1-4799-8297-0, 1-4799-8298-9, 1-4799-8295-4 OR 1479982970, 1479982989, 1479982954
ISBN13: 978-1-4799-8297-4 OR 9781479982974
ISSN: 1058-6393 OR 10586393
LCCN: TK7801
bibdate: Sun Jun 19 14:59:21 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.06.19 14:59:21 ???
acknowledgement: ack-nhfb
rawauthor: J. Hormigo and J. Villalba
raweditor: Michael B. Matthews
rawtitle: Optimizing {DSP} circuits by a new family of arithmetic operators
booktitle:
Proceedings of the 48th Asilomar Conference on Signals, Systems, and Computers, November 2--5, 2014, Pacific Grove, California

rawbooktitle:
{Proceedings of the 48th Asilomar Conference on Signals, Systems, and Computers, November 2--5, 2014, Pacific Grove, California}

entry:
@InProceedings{Hormigo:2014:ODC,
  author =       "J. Hormigo and J. Villalba",
  editor =       "Michael B. Matthews",
  booktitle =    "{Proceedings of the 48th Asilomar Conference on
                 Signals, Systems, and Computers, November 2--5, 2014,
                 Pacific Grove, California}",
  title =        "Optimizing {DSP} circuits by a new family of
                 arithmetic operators",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "871--875",
  year =         "2014",
  DOI =          "https://doi.org/10.1109/ACSSC.2014.7094576",
  ISBN =         "1-4799-8297-0, 1-4799-8298-9, 1-4799-8295-4",
  ISBN-13 =      "978-1-4799-8297-4",
  ISSN =         "1058-6393",
  LCCN =         "TK7801",
  bibdate =      "Sun Jun 19 14:59:21 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: techreport
filename: fparith.bib
label: Jeannerod:2014:REF
author: Claude-Pierre Jeannerod and Siegfried M. Rump
title: On relative errors of floating-point operations: optimal bounds and applications
type: Preprint
pages: 871--875
year: 2014
bibdate: Mon May 30 07:31:09 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.05.30 07:31:09 ???
acknowledgement: ack-nhfb
rawauthor: Claude-Pierre Jeannerod and Siegfried M. Rump
rawtitle: On relative errors of floating-point operations: optimal bounds and applications
entry:
@TechReport{Jeannerod:2014:REF,
  author =       "Claude-Pierre Jeannerod and Siegfried M. Rump",
  title =        "On relative errors of floating-point operations:
                 optimal bounds and applications",
  type =         "Preprint",
  number =       "??",
  institution =  "????",
  address =      "????",
  month =        "????",
  year =         "2014",
  bibdate =      "Mon May 30 07:31:09 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: inproceedings
filename: fparith.bib
label: Joldes:2014:CRF
author: Mioara Joldes and Jean-Michel Muller and Valentina Popescu
editor: IEEE
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 63--67
year: 2014
DOI: https://doi.org/10.1109/ASAP.2014.6868632
ISBN: 1-4799-3608-1 OR 1479936081
ISBN13: 978-1-4799-3608-3 OR 9781479936083
bibdate: Fri Sep 29 10:47:32 2023
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2023.09.29 10:47:32 ???
acknowledgement: ack-nhfb
rawauthor: Mioara Joldes and Jean-Michel Muller and Valentina Popescu
raweditor: {IEEE}
booktitle:
2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors. 18-20 June 2014. Zurich, Switzerland

title:
On the computation of the reciprocal of floating point expansions using an adapted Newton--Raphson iteration

rawbooktitle:
{2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors. 18-20 June 2014. Z{\"u}rich, Switzerland}

rawtitle:
On the computation of the reciprocal of floating point expansions using an adapted {Newton--Raphson} iteration

entry:
@InProceedings{Joldes:2014:CRF,
  author =       "Mioara Joldes and Jean-Michel Muller and Valentina
                 Popescu",
  editor =       "{IEEE}",
  booktitle =    "{2014 IEEE 25th International Conference on
                 Application-Specific Systems, Architectures and
                 Processors. 18-20 June 2014. Z{\"u}rich, Switzerland}",
  title =        "On the computation of the reciprocal of floating point
                 expansions using an adapted {Newton--Raphson}
                 iteration",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "63--67",
  year =         "2014",
  DOI =          "https://doi.org/10.1109/ASAP.2014.6868632",
  ISBN =         "1-4799-3608-1",
  ISBN-13 =      "978-1-4799-3608-3",
  bibdate =      "Fri Sep 29 10:47:32 2023",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Joldes:2014:SSH
author: Mioara Joldes and Valentina Popescu and Warwick Tucker
title: Searching for Sinks for the Henon Map using a Multiple-precision GPU Arithmetic Library
journal: j-COMP-ARCH-NEWS
volume: 42
number: 4
pages: 63--68
year: 2014
CODEN: CANED2
DOI: https://doi.org/10.1145/2693714.2693726
ISSN: 0163-5964 (print), 1943-5851 (electronic) OR 01635964 (print), 19435851 (electronic)
ISSNL: 0163-5964 OR 01635964
bibdate: Wed Dec 3 16:18:50 MST 2014
bibtimestamp: 2014.12.03 16:18:50 MST
fjournal: ACM SIGARCH Computer Architecture News
remark: HEART '14 conference proceedings.
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J89
rawauthor: Mioara Joldes and Valentina Popescu and Warwick Tucker
rawtitle: Searching for Sinks for the {H{\'e}non} Map using a Multiple-precision {GPU} Arithmetic Library
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/sigarch.bib

abstract:
Today, GPUs represent an important hardware development platform for many problems in dynamical systems, where massive parallel computations are needed. Beside that, many numerical studies of chaotic dynamical systems require a computing precision higher than common floating point (FP) formats. One such application is locating invariant sets for chaotic dynamical systems. In particular, we focus on rigorously proving the existence of stable periodic orbits for the Henon map for parameter values close to the classical ones. For that, we present a multiple-precision floating-point arithmetic library in CUDA programming language for the NVIDIA GPU platform. Our library extends the precision using so-called FP expansions, where a number is represented as the unevaluated sum of standard machine precision FP numbers. This format offers the advantage of using directly available and highly optimized hardware FP operations. We generalize algorithms used by multiple-precisions libraries such as Bailey's QD, or the analogue GPU version, GQD.

rawabstract:
Today, GPUs represent an important hardware development platform for many problems in dynamical systems, where massive parallel computations are needed. Beside that, many numerical studies of chaotic dynamical systems require a computing precision higher than common floating point (FP) formats. One such application is locating invariant sets for chaotic dynamical systems. In particular, we focus on rigorously proving the existence of stable periodic orbits for the H{\'e}non map for parameter values close to the classical ones. For that, we present a multiple-precision floating-point arithmetic library in CUDA programming language for the NVIDIA GPU platform. Our library extends the precision using so-called FP expansions, where a number is represented as the unevaluated sum of standard machine precision FP numbers. This format offers the advantage of using directly available and highly optimized hardware FP operations. We generalize algorithms used by multiple-precisions libraries such as Bailey's QD, or the analogue GPU version, GQD.

entry:
@Article{Joldes:2014:SSH,
  author =       "Mioara Joldes and Valentina Popescu and Warwick
                 Tucker",
  title =        "Searching for Sinks for the {H{\'e}non} Map using a
                 Multiple-precision {GPU} Arithmetic Library",
  journal =      j-COMP-ARCH-NEWS,
  volume =       "42",
  number =       "4",
  pages =        "63--68",
  year =         "2014",
  CODEN =        "CANED2",
  DOI =          "https://doi.org/10.1145/2693714.2693726",
  ISSN =         "0163-5964 (print), 1943-5851 (electronic)",
  ISSN-L =       "0163-5964",
  bibdate =      "Wed Dec 3 16:18:50 MST 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigarch.bib",
  abstract =     "Today, GPUs represent an important hardware
                 development platform for many problems in dynamical
                 systems, where massive parallel computations are
                 needed. Beside that, many numerical studies of chaotic
                 dynamical systems require a computing precision higher
                 than common floating point (FP) formats. One such
                 application is locating invariant sets for chaotic
                 dynamical systems. In particular, we focus on
                 rigorously proving the existence of stable periodic
                 orbits for the H{\'e}non map for parameter values close
                 to the classical ones. For that, we present a
                 multiple-precision floating-point arithmetic library in
                 CUDA programming language for the NVIDIA GPU platform.
                 Our library extends the precision using so-called FP
                 expansions, where a number is represented as the
                 unevaluated sum of standard machine precision FP
                 numbers. This format offers the advantage of using
                 directly available and highly optimized hardware FP
                 operations. We generalize algorithms used by
                 multiple-precisions libraries such as Bailey's QD, or
                 the analogue GPU version, GQD.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGARCH Computer Architecture News",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J89",
  remark =       "HEART '14 conference proceedings.",
}


bibtype: article
filename: fparith.bib
label: Korzen:2014:PPP
author: Marcin Korzen and Szymon Jaroszewicz
title: PaCAL: A Python Package for Arithmetic Computations with Random Variables
journal: j-J-STAT-SOFT
volume: 57
number: 10
pages: ??--??
month: may
monthnumber: 5
year: 2014
CODEN: JSSOBK
ISSN: 1548-7660 OR 15487660
ISSNL: 1548-7660 OR 15487660
bibdate: Mon Jun 16 11:01:52 MDT 2014
bibtimestamp: 2014.06.16 11:01:52 MDT
URL: http://www.jstatsoft.org/v57/i10
fjournal: Journal of Statistical Software
acknowledgement: ack-nhfb
journalURL: http://www.jstatsoft.org/
rawauthor: Marcin Korze{\'n} and Szymon Jaroszewicz
rawtitle: {PaCAL}: A {Python} Package for Arithmetic Computations with Random Variables
bibsource:
https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/jstatsoft.bib; https://www.math.utah.edu/pub/tex/bib/prng.bib

entry:
@Article{Korzen:2014:PPP,
  author =       "Marcin Korze{\'n} and Szymon Jaroszewicz",
  title =        "{PaCAL}: A {Python} Package for Arithmetic
                 Computations with Random Variables",
  journal =      j-J-STAT-SOFT,
  volume =       "57",
  number =       "10",
  pages =        "??--??",
  month =        may,
  year =         "2014",
  CODEN =        "JSSOBK",
  ISSN =         "1548-7660",
  ISSN-L =       "1548-7660",
  bibdate =      "Mon Jun 16 11:01:52 MDT 2014",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/jstatsoft.bib;
                 https://www.math.utah.edu/pub/tex/bib/prng.bib",
  URL =          "http://www.jstatsoft.org/v57/i10",
  acknowledgement = ack-nhfb,
  fjournal =     "Journal of Statistical Software",
  journal-URL =  "http://www.jstatsoft.org/",
  pubdates =     "Submitted 2012-02-14; Accepted 2013-07-21",
}


bibtype: inproceedings
filename: fparith.bib
label: Leeser:2014:MIR
author: Miriam Leeser and Sayan Mukherjee and Jaideep Ramachandran and Thomas Wahl
editor: IEEE
title: Make it real: Effective floating-point reasoning via exact arithmetic
publisher: pub-IEEE
address: pub-IEEE:adr
pages: 1--4
year: 2014
DOI: https://doi.org/10.7873/DATE.2014.130
ISBN: 1-4799-3297-3, 3-9815370-2-5 OR 1479932973, 3981537025
ISBN13: 978-1-4799-3297-9, 978-3-9815370-2-4 OR 9781479932979, 9783981537024
LCCN: TK7870 .D467 2014
bibdate: Sat Jun 4 17:09:03 2016
bibsource: https://www.math.utah.edu/pub/tex/bib/fparith.bib
bibtimestamp: 2016.06.04 17:09:03 ???
URL: http://ieeexplore.ieee.org/servlet/opac?punumber=6784162
acknowledgement: ack-nhfb
rawauthor: Miriam Leeser and Sayan Mukherjee and Jaideep Ramachandran and Thomas Wahl
raweditor: {IEEE}
rawtitle: Make it real: Effective floating-point reasoning via exact arithmetic
booktitle:
Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden, Germany March 24--28, 2014

rawbooktitle:
{Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden, Germany March 24--28, 2014}

entry:
@InProceedings{Leeser:2014:MIR,
  author =       "Miriam Leeser and Sayan Mukherjee and Jaideep
                 Ramachandran and Thomas Wahl",
  editor =       "{IEEE}",
  booktitle =    "{Design, Automation and Test in Europe Conference and
                 Exhibition (DATE), Dresden, Germany March 24--28,
                 2014}",
  title =        "Make it real: Effective floating-point reasoning via
                 exact arithmetic",
  publisher =    pub-IEEE,
  address =      pub-IEEE:adr,
  pages =        "1--4",
  year =         "2014",
  DOI =          "https://doi.org/10.7873/DATE.2014.130",
  ISBN =         "1-4799-3297-3, 3-9815370-2-5",
  ISBN-13 =      "978-1-4799-3297-9, 978-3-9815370-2-4",
  LCCN =         "TK7870 .D467 2014",
  bibdate =      "Sat Jun 4 17:09:03 2016",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/fparith.bib",
  URL =          "http://ieeexplore.ieee.org/servlet/opac?punumber=6784162",
  acknowledgement = ack-nhfb,
}


bibtype: article
filename: fparith.bib
label: Lei:2014:FIS
author: Yuanwu Lei and Lei Guo and Yong Dou and Sheng Ma and Jinbo Xu
title: FPGA Implementation of a Special-Purpose VLIW Structure for Double-Precision Elementary Function
journal: j-TRETS
volume: 7
number: 2
pages: 8:1--8:??
month: jun
monthnumber: 6
year: 2014
DOI: https://doi.org/10.1145/2617594
ISSN: 1936-7406 (print), 1936-7414 (electronic) OR 19367406 (print), 19367414 (electronic)
ISSNL: 1936-7406 OR 19367406
bibdate: Mon Jun 30 18:26:23 MDT 2014
bibtimestamp: 2014.06.30 18:26:23 MDT
fjournal: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
acknowledgement: ack-nhfb
articleno: 8
journalURL: http://portal.acm.org/toc.cfm?id=J1151
rawauthor: Yuanwu Lei and Lei Guo and Yong Dou and Sheng Ma and Jinbo Xu
abstract:
In the current article, the capability and flexibility of field programmable gate-arrays (FPGAs) to implement IEEE-754 double-precision floating-point elementary functions are explored. To perform various elementary functions on the unified hardware efficiently, we propose a special-purpose very long instruction word (VLIW) processor, called DP_VELP. This processor is equipped with multiple basic units, and its performance is improved through an explicitly parallel technique. Pipelined evaluation of polynomial approximation with Estrin's scheme is proposed, by scheduling basic components in an optimal order to avoid data hazard stalls and achieve minimal latency. The custom VLIW processor can achieve high scalability. Under the control of specific VLIW instructions, the basic units are combined into special-purpose hardware for elementary functions. Common elementary functions are presented as examples to illustrate the design of elementary function in DP_VELP in detail. Minimax approximation scheme is used to reduce degree of polynomial. Compromise between the size of lookup table and the latency is discussed, and the internal precision is carefully planned to guarantee accuracy of the result. Finally, we create a prototype of the DP_VELP unit and an FPGA accelerator based on the DP_VELP unit on a Xilinx XC6VLX760 FPGA chip to implement the SGP4/SDP4 application. Compared with previous researches, the proposed design can achieve low latency with a reasonable amount of resources and evaluate a variety of elementary functions with the unified hardware to satisfy the demands in scientific applications. Experimental results show that the proposed design guarantees more than 99% of correct rounding. Moreover, the SGP4/SDP4 accelerator, which is equipped with 39 DP_VELP units and runs at 200 MHz, outperforms the parallel software approach with hyper-thread technology on an Intel Xeon Quad E5620 CPU at 2.40 GHz by a factor of 7X.

rawabstract:
In the current article, the capability and flexibility of field programmable gate-arrays (FPGAs) to implement IEEE-754 double-precision floating-point elementary functions are explored. To perform various elementary functions on the unified hardware efficiently, we propose a special-purpose very long instruction word (VLIW) processor, called DP_VELP. This processor is equipped with multiple basic units, and its performance is improved through an explicitly parallel technique. Pipelined evaluation of polynomial approximation with Estrin's scheme is proposed, by scheduling basic components in an optimal order to avoid data hazard stalls and achieve minimal latency. The custom VLIW processor can achieve high scalability. Under the control of specific VLIW instructions, the basic units are combined into special-purpose hardware for elementary functions. Common elementary functions are presented as examples to illustrate the design of elementary function in DP_VELP in detail. Minimax approximation scheme is used to reduce degree of polynomial. Compromise between the size of lookup table and the latency is discussed, and the internal precision is carefully planned to guarantee accuracy of the result. Finally, we create a prototype of the DP_VELP unit and an FPGA accelerator based on the DP_VELP unit on a Xilinx XC6VLX760 FPGA chip to implement the SGP4/SDP4 application. Compared with previous researches, the proposed design can achieve low latency with a reasonable amount of resources and evaluate a variety of elementary functions with the unified hardware to satisfy the demands in scientific applications. Experimental results show that the proposed design guarantees more than 99\% of correct rounding. Moreover, the SGP4/SDP4 accelerator, which is equipped with 39 DP_VELP units and runs at 200 MHz, outperforms the parallel software approach with hyper-thread technology on an Intel Xeon Quad E5620 CPU at 2.40 GHz by a factor of 7X.

rawtitle:
{FPGA} Implementation of a Special-Purpose {VLIW} Structure for Double-Precision Elementary Function

entry:
@Article{Lei:2014:FIS,
  author =       "Yuanwu Lei and Lei Guo and Yong Dou and Sheng Ma and
                 Jinbo Xu",
  title =        "{FPGA} Implementation of a Special-Purpose {VLIW}
                 Structure for Double-Precision Elementary Function",
  journal =      j-TRETS,
  volume =       "7",
  number =       "2",
  pages =        "8:1--8:??",
  month =        jun,
  year =         "2014",
  CODEN =        "????",
  DOI =          "https://doi.org/10.1145/2617594",
  ISSN =         "1936-7406 (print), 1936-7414 (electronic)",
  ISSN-L =       "1936-7406",
  bibdate =      "Mon Jun 30 18:26:23 MDT 2014",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/trets.bib",
  abstract =     "In the current article, the capability and flexibility
                 of field programmable gate-arrays (FPGAs) to implement
                 IEEE-754 double-precision floating-point elementary
                 functions are explored. To perform various elementary
                 functions on the unified hardware efficiently, we
                 propose a special-purpose very long instruction word
                 (VLIW) processor, called DP_VELP. This processor is
                 equipped with multiple basic units, and its performance
                 is improved through an explicitly parallel technique.
                 Pipelined evaluation of polynomial approximation with
                 Estrin's scheme is proposed, by scheduling basic
                 components in an optimal order to avoid data hazard
                 stalls and achieve minimal latency. The custom VLIW
                 processor can achieve high scalability. Under the
                 control of specific VLIW instructions, the basic units
                 are combined into special-purpose hardware for
                 elementary functions. Common elementary functions are
                 presented as examples to illustrate the design of
                 elementary function in DP_VELP in detail. Minimax
                 approximation scheme is used to reduce degree of
                 polynomial. Compromise between the size of lookup table
                 and the latency is discussed, and the internal
                 precision is carefully planned to guarantee accuracy of
                 the result. Finally, we create a prototype of the
                 DP_VELP unit and an FPGA accelerator based on the
                 DP_VELP unit on a Xilinx XC6VLX760 FPGA chip to
                 implement the SGP4/SDP4 application. Compared with
                 previous researches, the proposed design can achieve
                 low latency with a reasonable amount of resources and
                 evaluate a variety of elementary functions with the
                 unified hardware to satisfy the demands in scientific
                 applications. Experimental results show that the
                 proposed design guarantees more than 99\% of correct
                 rounding. Moreover, the SGP4/SDP4 accelerator, which is
                 equipped with 39 DP_VELP units and runs at 200 MHz,
                 outperforms the parallel software approach with
                 hyper-thread technology on an Intel Xeon Quad E5620 CPU
                 at 2.40 GHz by a factor of 7X.",
  acknowledgement = ack-nhfb,
  articleno =    "8",
  fjournal =     "ACM Transactions on Reconfigurable Technology and
                 Systems (TRETS)",
  journal-URL =  "http://portal.acm.org/toc.cfm?id=J1151",
}


bibtype: article
filename: fparith.bib
label: Lindstrom:2014:FRC
author: Peter Lindstrom
title: Fixed-Rate Compressed Floating-Point Arrays
journal: j-IEEE-TRANS-VIS-COMPUT-GRAPH
volume: 20
number: 12
pages: 2674--2683
month: dec
monthnumber: 12
year: 2014
CODEN: ITVGEA
DOI: https://doi.org/10.1109/TVCG.2014.2346458
ISSNL: 1077-2626 OR 10772626
bibdate: Thu Feb 12 16:40:54 MST 2015
bibtimestamp: 2015.02.12 16:40:54 MST
URL: http://csdl.computer.org/csdl/trans/tg/2014/12/06876024-abs.html
fjournal: IEEE Transactions on Visualization and Computer Graphics
acknowledgement: ack-nhfb
journalURL: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2945
rawauthor: Peter Lindstrom
rawtitle: Fixed-Rate Compressed Floating-Point Arrays
ISSN:
1077-2626 (print), 1941-0506 (electronic), 2160-9306 OR 10772626 (print), 19410506 (electronic), 21609306

bibsource:
https://www.math.utah.edu/pub/tex/bib/datacompression.bib; https://www.math.utah.edu/pub/tex/bib/fparith.bib; https://www.math.utah.edu/pub/tex/bib/ieeetransviscomputgraph.bib

entry:
@Article{Lindstrom:2014:FRC,
  author =       "Peter Lindstrom",
  title =        "Fixed-Rate Compressed Floating-Point Arrays",
  journal =      j-IEEE-TRANS-VIS-COMPUT-GRAPH,
  volume =       "20",
  number =       "12",
  pages =        "2674--2683",
  month =        dec,
  year =         "2014",
  CODEN =        "ITVGEA",
  DOI =          "https://doi.org/10.1109/TVCG.2014.2346458",
  ISSN =         "1077-2626 (print), 1941-0506 (electronic), 2160-9306",
  ISSN-L =       "1077-2626",
  bibdate =      "Thu Feb 12 16:40:54 MST 2015",
  bibsource =    "https://www.math.utah.edu/pub/tex/bib/datacompression.bib;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/ieeetransviscomputgraph.bib",
  URL =          "http://csdl.computer.org/csdl/trans/tg/2014/12/06876024-abs.html",
  abstract-URL = "http://csdl.computer.org/csdl/trans/tg/2014/12/06876024-abs.html",
  acknowledgement = ack-nhfb,
  fjournal =     "IEEE Transactions on Visualization and Computer
                 Graphics",
  journal-URL =  "http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2945",
}


bibtype: article
filename: fparith.bib
label: Long:2014:SIF
author: Fan Long and Stelios Sidiroglou-Douskos and Deokhwan Kim and Martin Rinard
title: Sound input filter generation for integer overflow errors
journal: j-SIGPLAN
volume: 49
number: 1
pages: 439--452
month: jan
monthnumber: 1
year: 2014
CODEN: SINODQ
DOI: https://doi.org/10.1145/2578855.2535888
ISSN: 0362-1340 (print), 1523-2867 (print), 1558-1160 OR 03621340 (print), 15232867 (print), 15581160
ISSNL: 0362-1340 OR 03621340
bibdate: Tue Mar 4 17:04:57 MST 2014
bibtimestamp: 2014.03.04 17:04:57 MST
note: POPL '14 conference proceedings.
fjournal: ACM SIGPLAN Notices
acknowledgement: ack-nhfb
journalURL: http://portal.acm.org/browse_dl.cfm?idx=J706
rawauthor: Fan Long and Stelios Sidiroglou-Douskos and Deokhwan Kim and Martin Rinard
rawnote: POPL '14 conference proceedings.
rawtitle: Sound input filter generation for integer overflow errors
abstract:
We present a system, SIFT, for generating input filters that nullify integer overflow errors associated with critical program sites such as memory allocation or block copy sites. SIFT uses a static program analysis to generate filters that discard inputs that may trigger integer overflow errors in the computations of the sizes of allocated memory blocks or the number of copied bytes in block copy operations. Unlike all previous techniques of which we are aware, SIFT is sound --- if an input passes the filter, it will not trigger an integer overflow error at any analyzed site. Our results show that SIFT successfully analyzes (and therefore generates sound input filters for) 56 out of 58 memory allocation and block memory copy sites in analyzed input processing modules from five applications (VLC, Dillo, Swfdec, Swftools, and GIMP). These nullified errors include six known integer overflow vulnerabilities. Our results also show that applying these filters to 62895 real-world inputs produces no false positives. The analysis and filter generation times are all less than a second.

rawabstract:
We present a system, SIFT, for generating input filters that nullify integer overflow errors associated with critical program sites such as memory allocation or block copy sites. SIFT uses a static program analysis to generate filters that discard inputs that may trigger integer overflow errors in the computations of the sizes of allocated memory blocks or the number of copied bytes in block copy operations. Unlike all previous techniques of which we are aware, SIFT is sound --- if an input passes the filter, it will not trigger an integer overflow error at any analyzed site. Our results show that SIFT successfully analyzes (and therefore generates sound input filters for) 56 out of 58 memory allocation and block memory copy sites in analyzed input processing modules from five applications (VLC, Dillo, Swfdec, Swftools, and GIMP). These nullified errors include six known integer overflow vulnerabilities. Our results also show that applying these filters to 62895 real-world inputs produces no false positives. The analysis and filter generation times are all less than a second.

entry:
@Article{Long:2014:SIF,
  author =       "Fan Long and Stelios Sidiroglou-Douskos and Deokhwan
                 Kim and Martin Rinard",
  title =        "Sound input filter generation for integer overflow
                 errors",
  journal =      j-SIGPLAN,
  volume =       "49",
  number =       "1",
  pages =        "439--452",
  month =        jan,
  year =         "2014",
  CODEN =        "SINODQ",
  DOI =          "https://doi.org/10.1145/2578855.2535888",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Tue Mar 4 17:04:57 MST 2014",
  bibsource =    "http://portal.acm.org/;
                 https://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 https://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  note =         "POPL '14 conference proceedings.",
  abstract =     "We present a system, SIFT, for generating input
                 filters that nullify integer overflow errors associated
                 with critical program sites such as memory allocation
                 or block copy sites. SIFT uses a static program
                 analysis to generate filters that discard inputs that
                 may trigger integer overflow errors in the computations
                 of the sizes of allocated memory blocks or the number
                 of copied bytes in block copy operations. Unlike all
                 previous techniques of which we are aware, SIFT is
                 sound --- if an input passes the filter, it will not
                 trigger an integer overflow error at any analyzed site.
                 Our results show that SIFT successfully analyzes (and
                 therefore generates sound input filters for) 56 out of
                 58 memory allocation and block memory copy sites in
                 analyzed input processing modules from five
                 applications (VLC, Dillo, Swfdec, Swftools, and GIMP).
                 These nullified errors include six known integer
                 overflow vulnerabilities. Our results also show that
                 applying these filters to 62895 real-world inputs
                 produces no false positives. The analysis and filter
                 generation times are all less than a second.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
}


